UPD17P068GF-3BA [NEC]
4-BIT SINGLE-CHIP MICROCONTROLLER WITH ON-CHIP HARDWARE FOR TV SYSTEMS; 带有片上硬件电视系统的4位单片微控制器![UPD17P068GF-3BA](http://pdffile.icpdf.com/pdf1/p00028/img/icpdf/UPD17_145270_icpdf.jpg)
型号: | UPD17P068GF-3BA |
厂家: | ![]() |
描述: | 4-BIT SINGLE-CHIP MICROCONTROLLER WITH ON-CHIP HARDWARE FOR TV SYSTEMS |
文件: | 总36页 (文件大小:197K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17P068
4-BIT SINGLE-CHIP MICROCONTROLLER
WITH ON-CHIP HARDWARE FOR TV SYSTEMS
The µPD17P068 is a one-time PROM version of the µPD17068 that has on-chip mask ROM.
The µPD17P068, which can be programmed only once, is suited for testing during development of µPD17068
systems and limited production runs.
Use this data sheet together with µPD17068 documents.
The µPD17P068 does not provide a level of reliability intended for mass production of the customer's
products. Use it only for functional evaluation when experimenting or doing product trial tests.
FEATURES
• Compatible with the µPD17068
• One-time PROM
: 12160 × 16 bits
• Operating voltage : VDD = 5 V ± 10 %
ORDERING INFORMATION
Part Number
Package
µPD17P068GF-3BA
100-pin plastic QFP (14 × 20mm)
The inform ation in this docum ent is subject to change w ithout notice.
Document No. U10336EJ1V0DS00
Date Published November 1995 P
Printed in Japan
1995
©
µPD17P068
FUNCTIONAL OUTLINE
Part Number
µPD17068
µPD17P068
Item
Mask ROM
One-time PROM
Program memory (ROM)
• 12160 × 16 bits
Table reference area: 12160 × 16 bits
Character ROM (CROM)
Data memory (RAM)
• 6144 × 16 bits
• 1007 × 4 bits (including area serving also as VRAM)
Data buffer: 4 × 4 bits, general register: 16 × 4 bits
Video RAM (VRAM)
System register
• 672 × 4 bits (also used as data memory (RAM))
• 12 × 4 bits
Register file
• 12 × 4 bits
General port register
Instruction execution time
Stack levels
• 12 × 4 bits
• 2 µs (when using 8-MHz crystal resonator)
• 12 levels (stack manipulation possible)
• I/O ports
:
:
:
19
4
General ports
• Input ports
• Output ports
21
• Number of displayable characters
• Display format
: 192 characters max. per screen
(up to 350 characters with program)
: 16 × 16-dot mode 15 lines × 24 columns
: 14 × 16-dot mode 17 lines × 24 columns
: 255 types (user programmable)
: 16 × 16 dots and 14 × 16 dots selectable
(2 dots can be placed between
characters)
IDC
• Character types
• Character format
(Image Display Controller)
• Color
: 15 colors
• Character size
: Vertical
: 16 sizes (specifiable for
each line)
Horizontal : 24 sizes (specifiable for
each character)
• 2 systems
2
Serial interface
Serial interface 0 (compatible with 2-wire system, 3-wire system and I C Bus)
Serial interface 1 (3-wire system)
D/A converter
A/D converter
• 8 bits × 9 channels (PWM output, 12.5 V max.)
• 6 bits × 8 channels (successive approximation by software)
• 10 channels (maskable interrupt)
Interrupt
External interrupt : 3 channels (INT0, INTNC, VSYNC, HSYNC)
Internal interrupt
: 7 channels (timer 0, 1, serial interface 0, 1, basic timer 2,
VRAM pointer, timer 0 overflow)
2
µPD17P068
Part Number
µPD17068
µPD17P068
Item
Timer 0
Timer 1
: 10 µs to 204.75 ms (interrupt)
: 1 µs to 256 ms (interrupt)
Basic timer 0 : 1, 5, 100 ms (carry)
Basic timer 1 : 125 µs, 1 ms, 5 ms, 100 ms, external (carry)
Timer
Basic timer 2 : 125 µs, 1 ms, 5 ms, 100 ms, external (interrupt)
Watch timer
: Date, Hour, Minute, Second (counter)
• Power-on reset
Reset
• Reset with CE pin (CE pin: Low level → High level)
• Power interruption detection
Supply voltage
Package
VDD = 5 V ± 10 %
100-pin plastic QFP (14 × 20 mm)
3
µPD17P068
BLOCK DIAGRAM
ADC
ADC
ADC
ADC
ADC
ADC
0
1
2
3
4
5
VCO
PSC
EO
(P0D
(P0D
(P0D
(P0D
(P1C
0
/MD
/MD
/MD
/MD
0
/XTOUT)
1
1
/XTIN
)
PLL
A/D
Converter
2
2
)
3
0
3)
RAM
/D
0)
×
1007 4 bits
ADC
7
(P1C
2
/D
2
)
OSCIN
OSC
Circuit
VRAM
(672× 4 bits)
OSCOUT
PWM
PWM
PWM
PWM
PWM
0
3
4
7
8
(P2C
(P2C
(P2B
(P2B
(P2A
0
3
0
3
0
)
)
)
)
)
HSYNC
SYSTEM REG.
RF
D/A
Converter
VSYNC
RED
GREEN
BLUE
IDC
XTIN (P0D
XTOUT (P0D
CKOUT (P1B
1/ADC
2
)
BLANK
0/ADC )
1
OSC
ALU
I (P0B
2)
1
)
Watch
Timer
Hsync
Counter
HSCNT (P0B
3)
Instruction
Decoder
Timer0
Timer1
P0A
P0B
P0C
0
0
0
-P0A
3
4
4
4
4
4
4
4
4
-P0B
-P0C
-P0D
3
3
3
3
3
3
3
0
One-time PROM
12160 ×16 bits
CROM
P0D
P1A
0
×
6144 16 bits
Basic
Timer0
0-P1A
Program Counter
P1B
(D
0-P1B
4
Basic
Timer1
-D7)
Port
TMIN (P1B
3)
P1C
0
-P1C
-P1D
P2A
Stack
P1D
0
Basic
Timer2
×
12 14 bits
SDA (P0A
SCL (P0A
SCK (P0A
SO (P0A
SI (P0B
0
)
P2B
0
-P2B
3
3
2
4
4
3
1)
Serial
I/O0
0
2
)
P2C0-P2C
P2D -P2D
0
3
)
0
0
0
)
SCK
SO
SI
1
(P2D
(P2D
(P2D
0
)
X
IN/CLK
CPU
Serial
I/O1
Main
Oscillator
1
1
)
X
OUT
Peripheral
1
2
)
V
DD
INTNC (VPP
)
CE
RLSSTP/P1B
Interrupt
Reset
INT
0
2
GND , GND
0
1
4
µPD17P068
PIN CONFIGURATION (Top View)
(1) Normal operation mode
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P1D2
P1D1
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P0D2 /ADC3
P0D3 /ADC4
P1C0 /ADC5
P1C1 /ADC6
NC
2
P1D0
3
INT0
4
NC
5
P1B3/TMIN
P1B2/RLSSTP
NC
P1B1 /CKOUT
P1B0
6
7
P1C2 /ADC7
P1C3
8
9
NC
ADC0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
P0C0
µ
NC
NC
P1A3
P0C1
P1A2
NC
P0C2
NC
NC
NC
NC
P0C3
P1A1
NC
P2C0 /PWM0
NC
P1A0
NC
P2A0/PWM8
NC
P2C1 /PWM1
NC
NC
P2C2 /PWM2
NC
P2D2/SI1
P2D1/SO1
P2D0/SCK1
NC
P2C3 /PWM3
NC
P2B0 /PWM4
P2B1 /PWM5
P2B2 /PWM6
P2B3 /PWM7
GND0
OSCOUT
OSCIN
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5
µPD17P068
(2) PROM programming mode
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MD
MD
2
3
(OPEN)
2
3
D0
(L)
4
D1
(OPEN)
5
(OPEN)
D
D
7
6
6
7
D2
D3
(OPEN)
8
9
D
D
5
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
µ
(OPEN)
(OPEN)
(L)
(OPEN)
GND
0
(OPEN)
(L)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Caution Contents in parentheses indicate how to handle unused pins in PROM programming mode.
L: Connect to GND via a resistor (470 Ω) separately.
OPEN: Leave unconnected.
6
µPD17P068
PIN IDENTIFICATIONS
ADC0-ADC7
BLANK
BLUE
: A/D converter input
P1C0-P1C3
P1D0-P1D3
P2A0
: Port 1C
: Port 1D
: Port 2A
: Port 2B
: Port 2C
: Port 2D
: Blanking signal output
: Character signal output
: Chip enable
CE
P2B0-P2B3
P2C0-P2C3
P2D0-P2D2
PSC
CKOUT
: Watch timer adjustment
output
CLK
: Address update clock input
: Data input/output
: Error out
: Pulse swallow control output
: Pulse-width modulation output
: Character signal output
: Clock stop release signal input
: Shift clock input/output
: Shift clock input/output
: Serial data input/output
: Serial data input
D0-D7
PWM0-PWM8
RED
EO
GND0-GND2
GREEN
HSCNT
: Ground
RLSSTP
: Character signal output
: Horizontal synchronizing
signal counter input
: Horizontal synchronizing
signal input
SCK0, SCK1
SCL
SDA
HSYNC
Sl0, Sl1
SO0, SO1
TMIN
:
Serial data output
I
: Character signal output
: External interrupt request
signal input
: Event input of basic timer 1 or 2
: Local oscillation input
INT0, INTNC
VCO
VDD0, VDD1
VPP
:
Positive power supply
MD0-MD3
NC
: Operation mode select
: No connection
: Program voltage application
: Vertical synchronizing signal input
: Main clock oscillation
VSYNC
OSCIN, OSCOUT : LC oscillation for IDC
XIN, XOUT
XTIN, XTOUT
P0A0-P0A3
P0B0-P0B3
P0C0-P0C3
P0D0-P0D3
P1A0-P1A3
P1B0-P1B3
: Port 0A
: Port 0B
: Port 0C
: Port 0D
: Port 1A
: Port 1B
: Watch timer oscillation
7
µPD17P068
CONTENTS
1. PIN FUNCTIONS................................................................................................................................. 9
1.1 Normal Operation Mode ........................................................................................................................... 9
1.2 PROM Programming Mode .................................................................................................................... 13
1.3 Pin Equivalent Circuits .......................................................................................................................... 14
1.4 Handling of Unused Pins ....................................................................................................................... 19
1.5 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode) ................................... 21
2. WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY)............................ 22
2.1 Operation Modes in Program Memory Write/Read/Verify................................................................. 23
2.2 PROM Write Procedure .......................................................................................................................... 24
2.3 PROM Read Procedure .......................................................................................................................... 25
3. ELECTRICAL SPECIFICATIONS .................................................................................................... 26
4. PACKAGE DRAWING ...................................................................................................................... 31
APPENDIX DEVELOPMENT TOOLS.................................................................................................... 32
8
µPD17P068
1. PIN FUNCTIONS
1.1 Normal Operation Mode
(1) Port pins
Pin Name
P0A0
Description
I/O
I/O
Output Type
When Reset
Shared by
SDA
SCL
SCK0
SO0
4-bit I/O port.
These pins serve as a bit-selectable
4-bit input/output port. All these pins
are set to input pins when power (VDD)
is turned on, when clock is stopped, or
when reset signal is input to the CE pin.
N-ch open drain
P0A1
Input
P0A2
CMOS push-pull
CMOS push-pull
P0A3
4-bit I/O port.
P0B0
Sl0
These pins serve as a bit-selectable 4-bit
input/output port. All these pins are set to
input pins when power (VDD) is turned
on, when clock is stopped, or when reset
signal is input to the CE pin.
P0B1
—
I/O
Input
P0B2
l
P0B3
HSCNT
P0C0
These pins serve as a 4-bit output port.
The output state of each pin is undefined
after power (VDD) is turned on.
—
O
I
CMOS push-pull
Undefined output
P0C3
P0D0
P0D1
P0D2
P0D3
P1A0
ADC1/XTOUT
ADC2/XTIN
ADC3
These pins serve as a 4-bit input port.
These pins serve as a 4-bit output port.
—
Input with pull-
down resistor
ADC4
N-ch open-drain
Middle voltage,
high current
O
Undefined output
—
—
P1A3
P1B0
4-bit I/O port.
P1B1
P1B2
P1B3
CKOUT
RLSSTP
TMIN
These pins serve as a bit-selectable 4-bit
input/output port.
I/O
I/O
CMOS push-pull
Input
P1C0
ADC5
4-bit I/O port. These pins serve as 4-bit-
selectable 4-bit I/O port.
CMOS push-pull
CMOS push-pull
Input
P1C2
P1C3
P1D0
ADC7
—
—
These pins serve as a 4-bit output port.
This pin serves as a 1-bit output port.
These pins serve as a 4-bit output port.
These pins serve as a 4-bit output port.
O
O
O
O
Undefined output
Undefined output
Undefined output
Undefined output
P1D3
P2A0
N-ch open-drain
Middle voltage
PWM8
P2B0
P2B3
P2C0
P2C3
PWM4
PWM7
PWM0
PWM3
N-ch open-drain
Middle voltage
N-ch open-drain
Middle voltage
These pins serve as a bit-selectable 3-bit
input/output port. All these pins are set to
input pins when power (VDD) is turned on,
when clock is stopped, or when reset
signal is input to the CE pin.
P2D0
P2D1
P2D2
SCK1
SO1
Sl1
I/O
CMOS push-pull
Input
9
µPD17P068
(2) Non-port pins
Pin Name
Description
I/O
O
Output Type
When Reset
Shared by
This pin outputs signals from the charge
pump of the PLL frequency synthesizer.
If the frequency divided from the local
oscillator (VCO) frequency is higher (lower)
than the reference frequency, high (low)
level is output from this pin, respectively.
When the two frequencies match, this pin
is placed in the high-impedance state.
EO
CMOS 3-state
High-impedance
—
This pin outputs pulse swallow control
signal. This signal switches division ratio
for the dedicated prescaler µPB595.
PSC
VCO
O
CMOS push-pull
Output
—
—
This pin is the input of the local oscillator.
The output signal coming from the local
oscillator (VCO) in the tuner and divided by
the dedicated prescaler µPB595 should be
input to this pin, where the µPB595 is a
two-module prescaler capable of frequency
division up to 1 GHz.
Internally
pulled down
I
—
This pin is the input of the H sync signal
counter.
HSCNT
BLANK
I
—
Input
P0B3
—
This active-high pin outputs blanking
signals to delete video signals.
O
CMOS push-pull
Low level output
This active-high pin outputs character
data that correspond the R signal (one of
the RGB signals of IDC).
RED
GREEN
BLUE
O
O
O
CMOS push-pull
CMOS push-pull
CMOS push-pull
Low level output
Low level output
Low level output
—
—
—
This active-high pin outputs character data
that correspond the G signal (one of the
RGB signals of IDC).
This active-high pin outputs character data
that correspond the B signal (one of the
RGB signals of IDC).
This pin outputs character data that
correspond the I signal of IDC.
I
O
I
CMOS push-pull
Input
Input
Input
P0B2
—
The H sync signals for IDC should be
input to this pin in an active-low manner.
HSYNC
VSYNC
—
—
The V sync signals for IDC should be input
to this pin in an active-low manner.
I
—
These are the input and output pins of the
LC oscillation circuit for IDC. Adjust the
oscillation frequency to 10 MHz.
OSCIN
OSCOUT
ADC0
—
I
—
—
—
—
—
These are the analog input pins of the
6-bit resolution A/D converter.
Input
ADC1
P0D0/XTOUT
P0D1/XTIN
P0D2
ADC2
ADC3
ADC4
ADC5
These are the analog input pins of the
6-bit resolution A/D converter.
I
—
Input
P0D3
P1C0
P1C2
ADC7
10
µPD17P068
Pin Name
PWM0
Description
I/O
O
Output Type
When Reset
Shared by
P2C0
PWM3
PWM4
P2C3
P2B0
Low-level output
or high impe-
dance
These are the output pins of the
8-bit resolution D/A converter.
N-ch open-drain
Middle-voltage
PWM7
PWM8
P2B3
P2A0
TMIN
This pin is the input of basic timer 1 or 2.
I
—
—
Input
P1B3
A 32.768-kHz crystal resonator for watch
timer operation should be connected to
these pins.
XTIN
P0D1/ADC2
—
—
XTOUT
P0D0/ADC1
P1B1
This pin outputs the signal to control the
watch timer.
CKOUT
O
CMOS push-pull
CMOS push-pull
Input
Input
SCK0
P0A2
These pins input and output shift clocks.
I/O
SCK1
Sl0
P2D0
P0B0
These pins input serial data.
These pins output serial data.
I
—
Input
Input
Sl1
P2D2
P0A3
SO0
O
CMOS push-pull
SO1
SCL
P2D1
P0A1
These pins input and output shift clocks.
These pins input and output serial data.
I/O
I/O
N-ch open-drain
N-ch open-drain
Input
Input
SDA
P0A0
This pin inputs interrupt request signal
from external device. An interrupt
request is issued at the rising or falling
edge of the input signal applied to this
pin.
INT0
I
I
—
—
Input
Input
—
This pin inputs interrupt request signal
with noise canceller. Using this pin to
input signals with noise such as
INTNC
commands from a remote control unit
simplifies programming processes.
The interrupt request issuing timing is
programmable to either rising or falling
edge of the input signal to this pin.
—
11
µPD17P068
Pin Name
Description
I/O
Output Type
When Reset
Shared by
This pin selects a device to be activated,
or resets this device.
(1) Use as input of device selection signal
When CE=high, PLL synthesizer and
IDC operate. When CE=low, their
operation are disabled (stops).
(2) Use as reset input
CE
I
—
Input
—
When CE changes from low to high,
this device is reset in synchronization
with the carry FF operation for the
internal basic interval timer 0.
This pin inputs the clock stop release
signal.
RLSSTP
I
—
—
Input
P1B2
—
An 8-MHz crystal resonator for main
clock generation should be connected to
these pins.
XIN
—
—
XOUT
These pins supply positive power voltage
for this device. The power supply voltage
of 5 V ± 10 % should be applied to these
pins when all functions operate.
VDD0
When IDC is disabled, the voltage range
from 4.0 to 5.5 V is allowed. When clock
is stopped, the applied voltage to these
pins may be lowered down to 2.5 V.
Because this device internally has the
power-on reset circuit, the voltages applied
to these pins are changed from 0 to 4.0 V,
system reset sequence is started and the
program is implemented from address 0H.
To assure normal operations of the
—
—
—
—
VDD1
power-on reset circuit, the rise time from
0 to 4.0 V should be shorter than 500 ms.
GND0
These pins supply the ground level for
this device.
—
—
—
—
—
—
—
—
GND2
NC
This pin should be left unconnected.
12
µPD17P068
1.2 PROM Programming Mode
Pin Name
Description
I/O
I/O
Output Type
D0
8-bit data input/output pins used in
program memory write, read, verify
modes.
CMOS push-pull
D7
MD0
Input pins that select an operation mode
in program memory write, read, verify
modes.
I
—
MD3
CLK
Clock input for address update in program
memory write, read, verify modes.
I
—
—
Programming voltage (+12.5 V) application
pin in program memory write, read, verify
modes.
VPP
—
Positive power supply.
VDD0
+5 V should be applied to these pins in
program memory write, read, verify modes.
—
—
—
—
VDD1
GND0
Ground pin
GND2
Remark The other pins are not used in the PROM programming mode. How to handle the other pins are
described in the section "PIN CONFIGURATION (2) PROM programming mode".
13
µPD17P068
1.3 Pin Equivalent Circuits
(1) P0A (P0A3/SO0, P0A2/SCK0)
P0B (P0B2/l, P0B1, P0B0/Sl0)
(Input/output)
P1B (P1B2/RLSSTP, P1B1/CKOUT, P1B0)
P1C (P1C3, P1C2/ADC7, P1C1/ADC6, P1C0/ADC5)
A/D converter (P1C/ADC only)
VDD
RESET (other than P1C)
Read instruction (P1C only)
VDD
(2) P2D (P2D2/Sl1, P2D1/SO1, P2D0/SCK1) : (Input/output)
VDD
RESET
VDD
14
µPD17P068
(3) P0A (P0A1/SCL, P0A0/SDA) : (Input/output)
VDD
(4) P0C (P0C3, P0C2, P0C1, P0C0)
P1D (P1D3, P1D2, P1D1, P1D0)
(Output)
RED, GREEN, BLUE, BLANK
PSC
VDD
(5) P1A (P1A3, P1A2, P1A1, P1A0)
P2A (P2A0/PWM8)
(Output)
P2B (P2B3/PWM7, P2B2/PWM6, P2B1/PWM5, P2B0/PWM4)
P2C (P2C3/PWM3, P2C2/PWM2, P2C1/PWM1, P2C0/PWM0)
(6) P0D (P0D3/ADC4, P0D2/ADC3, P0D1/ADC2/XTIN, P0D0/ADC1/XTOUT) : (Input)
VDD
High on-resistance
15
µPD17P068
(7) ADC0 : (Input)
VDD
(8) P0B3/HSCNT : (Input/output)
VDD
RESET
Port
VDD
VDD
H sync signal counter
VDD
16
µPD17P068
(9) P1B3/TMIN : (Input/output)
VDD
RESET
Port
VDD
VDD
Timer counter
VDD
(10) HSYNC, VSYNC, CE, INT0, INTNC : (Schmitt triggered input)
VDD
17
µPD17P068
(11) XIN, OSCIN :
XOUT, OSCOUT :
High on-resistance
VDD
VDD
XIN, OSCIN
XOUT, OSCOUT
(12) EO : (Output)
VDD
(13) VCO : (Input)
VDD
VDD
(Input)
18
µPD17P068
1.4 Handling of Unused Pins
The following are recommended for handling unused pins.
Table 1-1. Handling of Unused Pins (1/2)
(a) Port pins
Pin Name
P0A0/SDA
Input/Output Circuit Type
Recommended Handling when in Unused State
Note 1
Input/output
Specify a general-purpose input port by software and connect each pin
Note 2
P0A1/SCL
to VDD or GND through a resistor.
P0A2/SCK0
P0A3/SO0
P0B0/SI0
P0B1
P0B2/I
P0B3/HSCNT
P0C0-P0C3
CMOS push-pull output
Input
Open
Note 2
P0D0/ADC1/XTOUT
P0D1/ADC2/XTIN
Individually connect to GND through a resistor.
P0D2/ADC3, P0D3/ADC4
P1A0-P1A3
N-ch open-drain output
Specify low-level output by software, then open.
Note 1
P1B0
Input/output
Specify a general-purpose input port by software and connect each pin
Note 2
P1B1/CKOUT
P1B2/RLSSTP
P1B3/TMIN
to VDD or GND through a resistor.
P1C0/ADC5-P1C2/ADC7
P1C3
P1D0-P1D3
CMOS push-pull output
N-ch open-drain output
Open
P2A0/PWM8
Specify low-level output by software, then open.
P2B0/PWM4-P2B3/PWM7
P2C0/PWM0-P2C3/PWM3
Note 1
P2D0/SCK1
P2D1/SO1
P2D2/SI1
Input/output
Specify a general-purpose input port by software and connect each pin
Note 2
to VDD or GND through a resistor.
Notes 1. Input ports go to input mode when the power supply rises, when the clock stops, and on CE reset.
2. Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down
(connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with
a high value, because the pin comes near to being in high impedance, the consumed (through) current
increases. This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor
is a few tens of kΩ.
19
µPD17P068
Table 1-1. Handling of Unused Pins (2/2)
(b) Pins other than ports
Pin Name
Input/Output Circuit Type
Recommended Handling when in Unused State
Note
ADC0
BLANK
BLUE
CE
Input
Connect to VDD or GND through a resistor.
Output
Output
Input
Open
Open
Note
Connect to VDD through a resistor.
EO
Output
Output
Input
Open
GREEN
HSYNC
INT0
Open
Note
Note
Note
Connect to VDD or GND through a resistor.
Connect to VDD or GND through a resistor.
Connect to VDD or GND through a resistor.
Input
INTNC
OSCIN
OSCOUT
PSC
Input
Note
Input
Connect to VDD through a resistor.
Output
Output
Output
Open
Open
Open
RED
VCO
Input with pull-down resistor Open
Input Connect to VDD or GND through a resistor.
Note
VSYNC
Note Be careful of the fact that when an external pull-up (connection to VDD through a resistor) or pull-down
(connection GND through a resistor) is made, if the pull-up or pull-down is done through a resistor with a high
value, because the pin comes near to being in high impedance, the consumed (through) current increases.
This also depends on the application circuit, but a typical value for a pull-up or pull-down resistor is a few tens
of kΩ.
20
µPD17P068
1.5 Notes on Using the CE and INTNC Pins (Only in Normal Operation Mode)
In addition to the functions shown in 1.1 Normal Operation Mode, the CE pin also has the function of setting
a test mode (for IC testing) in which the internal operations of the µPD17P068 are tested.
Also, the INTNC pin has the function of the VPP pin for program memory write/verify.
When a voltage higher than VDD is applied to either of these pins, the test or program memory write/verify
mode is set. This means that, even during normal operation, the µPD17P068 may be set in the test mode if
noise exceeding VDD is applied.
For example, if the wiring length of the CE or INTNC pin is too long, noise superimposed on the wiring line
of the pin may cause the above problem.
Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take
noise preventive measures as shown below by using external components.
• Connect diode with low VF between VDD
•
Connect capacitor between VDD
and CE/INTNC pin
and CE/INTNC pin
VDD
VDD
Diode with
low V
VDD
V
DD
F
CE, INTNC
CE, INTNC
21
µPD17P068
2. WRITE, READ, AND VERIFY OF ONE-TIME PROM (PROGRAM MEMORY)
The program memory contained in the µPD17P068 is the 12160 × 16-bit one-time PROM that can electrically
be written one time only. This PROM is accessed in 16 bits per word in normal operation mode, and in 8 bits
per word in write, read, verify modes. The 16 bits of a word in normal mode are divided into higher 8 bits and
lower 8 bits which are assigned to even and odd addresses, respectively.
When the PROM is written, read, or verified, set this device into the PROM mode. In this mode, these pins
are used as shown in the table below. Notice that no address input pins are provided. Addresses are
automatically updated by the clock signal supplied from the CLK pin.
Table 2-1. Pins Used in Program Memory Write, Read, and Verify Modes
Pin
VPP
Function
Programming voltage (+12.5 V) application
Address update clock input
CLK
MD0-MD3
D0-D7
Operation mode selection
8-bit data input/output
VDD0, VDD1
Power supply voltage (+5 V) application
To write the internal PROM, use the NEC-specified PROM programming equipment (PROM programmer) and
program adapter as listed below.
PROM programmer
AF-9703
AF-9704
AF-9705
AF-9706
AF-9808L
(Ando Electric Corporation)
(Ando Electric Corporation)
(Ando Electric Corporation)
(Ando Electric Corporation)
(Ando Electric Corporation)
Program adapter
Remark For details on these PROM programmer and program adapter, consult with Ando Electric
Corporation (03-3733-1151 Tokyo, Japan).
22
µPD17P068
2.1 Operation Modes in Program Memory Write/Read/Verify
When +5 V is applied to the VDD pin and +12.5 V is applied to the VPP pin, this device enters the program
memory write/read/verify modes. Operation mode is determined by the setting of MD0 to MD3 pins as indicated
in the table below.
All input pins irrelevant to the program memory write/read/verify operation should be left unconnected or
connected to GND via a pull-down resistor of 470 Ω (Refer to the section "PIN CONFIGURATION (2) PROM
programming mode). "
Table 2-2. Operation Modes in Program Memory Write/Read/Verify
Pin States
Operation Mode
VPP
VDD
MD0
H
MD1
L
MD2
H
MD3
L
Program memory address 0 clear
Write
L
L
H
L
H
H
H
H
H
H
+12.5 V
+5 V
Read, Verify
H
X
Program inhibit
Remark X: L or H
23
µPD17P068
2.2 PROM Write Procedure
Data can be written to the PROM in high speeds by using the following procedures.
(1)
Set the pins not used for programming as indicated in section "PIN CONFIGURATION (2) PROM
programming mode." Set the CLK pin to low level.
Supply +5 V to the VDD and VPP pins.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Provide a 10-µs wait state.
Program memory address 0 clear mode is entered.
Supply +6 V to the VDD pin, and +12.5 V to the VPP pin.
Program inhibit mode is entered.
Provide write data for 1 ms in write mode.
Program inhibit mode is entered.
Use the verify mode to test data. If the data has been written, proceed to (10). If not, repeat steps
(7) to (9).
(10) Provide write data (for additional writing) for 1 ms times the number of repeats performed between
steps (7) to (9).
(11) Program inhibit mode is entered.
(12) Provide four pulses to the CLK pin to increment the address.
(13) Repeat steps (7) to (12) until the last address is reached.
(14) Program memory address 0 clear mode.
(15) Supply +5 V to VDD and VPP pins.
(16) Turn off the power for this device.
The procedures from (2) to (12) are illustrated in the chart below.
Repeat X times
Address
increment
Additional
write
Write
Verify
VPP
VDD
VPP
GND
V
DD + 1
VDD
V
DD
GND
CLK
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data
output
Data input
Data input
D
0-D7
MD
MD
0
1
MD
MD
2
3
24
µPD17P068
2.3 PROM Read Procedure
Data can be read from the PROM by using the following procedures.
(1)
Set the pins not used for programming as indicated in section "PIN CONFIGURATION (2) PROM
programming mode." Set the CLK pin to low level.
Supply +5 V to the VDD and VPP pins.
(2)
(3)
(4)
(5)
(6)
(7)
Provide a 10-µs wait state.
Program memory address 0 clear mode is entered.
Supply +6 V to the VDD pin, and +12.5 V to the VPP pin.
Program inhibit mode is entered.
Use the verify mode to output data. Provide clock pulses to the CLK pin to output the data of an address.
The address is automatically incremented every four clock pulses. Repeat the four-pulse cycles until
the last address is reached.
(8)
(9)
Program inhibit mode is entered.
Program memory address 0 clear mode.
(10) Supply +5 V to the VDD and VPP pins.
(11) Turn off the power for this device.
The procedures from (2) to (9) are illustrated in the chart below.
VPP
VDD
VPP
GND
V
DD +1
V
DD
VDD
GND
CLK
Hi-Z
Hi-Z
Data output
Data output
D
0
-D
7
0
1
MD
MD
"L"
MD
MD
2
3
25
µPD17P068
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 ˚C)
Parameter
Supply voltage
Symbol
VDD
VI
Conditions
Ratings
Unit
V
−0.3 to +6.0
Input voltage
−0.3 to VDD + 0.3
V
Output voltage
VO
Except for P1A, P2B, P2C
−0.3 to VDD + 0.3
V
High-level output current
IOH
1 pin
−12
mA
mA
mA
mA
mA
mA
V
All pins
−20
Low-level output current
IOL1
IOL2
1 pin (except for P1A)
All pins (except for P1A)
1 pin (P1A only)
All pins (P1A only)
P1A, P2A, P2B, P2C
12
20
17
60
13
Output withstand voltage
Storage temperature
VBDS
Tstg
−55 to +125
˚C
Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single
parameter or even momentarily. That is, the absolute maximum ratings are rated values at which
the product is on the verge of suffering physical damage, and therefore the product must be used
under conditions which ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = 25 ˚C)
Parameter
Supply voltage
Symbol
Conditions
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
VDD1
VDD2
VDD3
VDDR
VBDS
trise
Only CPU operates
4.0
5.0
5.5
V
Only watchdog timer operates (CPU stops)
2.3
5.0
5.5
V
Data retention voltage
Output withstand voltage
Supply voltage rise time
Input amplitude
Clock stops
2.3
5.5
V
P1A, P2A, P2B, P2C
VDD = 0 → 4.5 V
VCO
12.5
500
5.5
V
3
ms
VP−P
VIN
0.7
26
µPD17P068
DC Characteristics (Reference characteristics: TA = −40 to +85 ˚C, V DD = 5 V ± 10 %)
Parameter
Supply current
Symbol
Conditions
Operation of all functions
MIN.
TYP.
11
MAX.
23
Unit
mA
IDD1
VDD = 5 V, TA = 25 ˚C, fVCO = 20 MHz
VIN = 0.7 VP-P, IDC operation
OSCIN = 10 MHz, XIN pin square wave input
(fIN = 8 MHz, VIN = VDD)
IDD2
CPU and PLL operation
7
12
mA
VDD = 5 V, TA = 25 ˚C, fVCO = 20 MHz
VIN = 0.7 VP-P, XIN pin square wave input
(fIN = 8 MHz, VIN = VDD)
IDD3
Only CPU operates
6.5
2.5
9
mA
mA
VDD = 5 V, TA = 25 ˚C, XIN pin square wave input
(fIN = 8 MHz, VIN = VDD)
IDD4
HALT instruction
4.5
VDD = 5 V, TA = 25 ˚C, XIN pin square wave input
(fIN = 8 MHz, VIN = VDD)
Data retention current
IDDR1
Main clock stop, watch timer operation
VDD = 2.5 V, TA = 25 ˚C
5
15
2
10
25
15
µA
µA
µA
Main clock stop, watch timer operation
VDD = 5 V, TA = 25 ˚C
IDDR2
Main clock stop, watch timer operation
VDD = 5 V, TA = 25 ˚C
High-level input voltage
VIH1
VIH2
VIH3
VIL1
VIL2
IOH1
P0A, P0B, P1B, P1C, P2D
0.7VDD
0.8VDD
0.7VDD
V
V
CE, INT0, INTNC, VSYNC, HSYNC
P0D
V
Low-level input voltage
High-level output current
P0A, P0B, P0D, P1B, P1C, P2D
CE, INT0, INTNC, VSYNC, HSYNC
P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D,
BLANK, RED, GREEN, BLUE, PSC
VOH = VDD − 1 V
0.2 VDD
0.2 VDD
V
V
−1
−5
mA
IOH2
EO
VOH = VDD − 1 V
−1
−2.5
mA
mA
Low-level output current
IOL1
P0A2, P0A3, P0B, P0C, P1B, P1C, P1D, P2D,
1
10
PSC
VOL = 1 V
IOL11
IOL2
IOL3
IOL4
IOL5
IIH
BLANK, RED, GREEN, BLUE
VOL = 1 V
VOL = 1 V
1
1
8.5
6
mA
mA
mA
mA
mA
mA
µA
EO
P0A0, P0A1
PWM (P2A, P2B, P2C)
P1A
VOL = 1 V
1
4.0
1.5
30
VOL = 1 V
1
VOL = 1 V
15
0.1
High-level input current
High-level output leakage
Output off leakage current
Internal pull-down resistor
VCO
VIH = VDD
0.65
1.3
0.5
±1
85
72
47
ILOH
IL
P1A, P2A, P2B, P2C
EO
VO = 12.5 V
VO = VDD or 0 V
VIH = VDD
±10−3
41
µA
RPD1
RPD2
RPD3
P0D (KEY)
P0D (KEY)
19
23
29
kΩ
kΩ
kΩ
VIH = VDD = 5 V
41
P0D (KEY)
VIH = VDD = 5 V, TA = 25 ˚C
41
27
µPD17P068
AC Characteristics (Reference characteristics: TA = −40 to +85 ˚C, V DD = 5 V ± 10 %)
Parameter
Input frequency 1
Input frequency 2
Input frequency 3
Symbol
fVCO
Conditions
VCO square wave input
MIN.
0.7
45
TYP.
MAX.
Unit
MHz
Hz
VIN = 0.7 VP−P
20
65
20
fTMR
TMIN (P1B3)
Duty 50 %
fHS
HSCNT (P0B3)
10
kHz
A/D Converter Characteristics (Reference characteristics: TA = −10 to +50 ˚C, V DD = 5 V ± 10 %)
Parameter
Symbol
Conditions
MIN.
1
TYP.
MAX.
±1.5
6
Unit
LSB
bit
A/D conversion absolute accuracy
A/D conversion resolution
A/D input impedance
ADC0-ADC7
ADC0-ADC7
ADC0-ADC7
±1
MΩ
DC Programming Characteristics (TA = 25 ˚C, V DD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.5 V)
Parameter
Symbol
VIH1
VIH2
VIL1
VIL2
ILI
Conditions
MIN.
0.7 VDD
VDD − 0.5
0
TYP.
MAX.
VDD
Unit
V
High-level input voltage
Except for CLK
CLK
VDD
V
Low-level input voltage
Except for CLK
CLK
0.3 VDD
0.4
V
0
V
Input leakage current
High-level output voltage
Low-level output voltage
VDD supply current
VIN = VIL or VIH
IOH = −1 mA
IOL = 1 mA
±10
µA
V
VOH
VOL
IDD
VDD − 1.0
1.0
30
30
V
mA
mA
VPP supply current
IPP
MD0 = VIL, MD1 = VIH
Cautions 1. VPP must not exceed +13.5 V including overshoot.
2. VDD should be applied before VPP and cut after VPP.
28
µPD17P068
AC Programming Characteristics (TA = 25 ˚C, V DD = 6.0 ± 2.5 V, VPP = 12.5 ± 0.5 V)
Parameter
Symbol
tAS
Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
ns
Note
Address setup time
(vs. MD0↓)
2
2
MD1 setup time (vs. MD0↓)
tM1S
tDS
Data setup time (vs. MD0↓)
2
Note
Address hold time
(vs. MD0↑)
tAH
2
Data hold time (vs. MD0↑)
MD0↑→ data output float delay time
VPP setup time (vs. MD3↑)
VDD setup time (vs. MD3↑)
Initial program pulse width
Additional program pulse width
MD0 setup time (vs. MD1↑)
MD0↓→ data output delay time
MD1 hold time (vs. MD0↑)
MD1 recovery time (vs. MD0↓)
Program counter reset time
CLK input high-/low-level width
CLK input frequency
tDH
2
tDF
0
130
tVPS
tVDS
tPW
2
µs
µs
ms
ms
µs
µs
µs
µs
µs
µs
MHz
µs
µs
µs
µs
µs
ns
2
0.95
0.95
2
1.0
1.05
21.0
tOPW
tM0S
tDV
MD0 = MD1 = VIL
1
tM1H
tM1R
tPCR
tXH, tXL
fX
tM1H + tM1R ≥ 50 µs
2
2
10
0.125
4.19
Initial mode setting time
tI
2
2
2
2
MD3 setup time (vs. MD1↑)
MD3 hold time (vs. MD1↓)
tM3S
tM3H
tM3SR
tDAD
tHAD
tM3HR
tDFR
MD3 setup time (vs. MD0↓)
When program memory is read
Note
Address
Address
→ data output delay time
→ data output hold time
2
Note
0
2
130
MD3 hold time (vs. MD0↑)
µs
µs
MD3↓→ data output float delay time
2
Note The internal address increment (+1) is performed on the fall of the 3rd clock, where 4 clocks comprise one
cycle. The internal clock is not connected to a pin.
29
µPD17P068
Program Memory Write Timing
t
t
VPS
VDS
V
PP
V
PP
V
DD
GND
DD + 1
V
V
DD
V
DD
t
t
XH
GND
CLK
t
XL
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data
output
D0-D7
Data input
Data input
Data input
DH
t
DS
t
I
t
DH
t
DF
t
DS
t
AH
t
AS
t
DV
MD
MD
MD
MD
0
t
PW
t
M0S
t
OPW
tM1R
1
tPCR
tM1S
tM1H
2
3
t
M3H
t
M3S
Program Memory Read Timing
t
t
VPS
VDS
V
PP
V
PP
V
DD
GND
VDD + 1
V
DD
V
DD
t
XH
GND
CLK
t
DAD
t
XL
t
HAD
Hi-Z
Hi-Z
Data output
Data output
D0-D7
t
DV
t
DFR
t
M3HR
t
I
MD
MD
MD
MD
0
1
"L"
t
PCR
2
3
t
M3SR
30
µPD17P068
4. PACKAGE DRAWING
100 PIN PLASTIC QFP (14 20)
A
B
51
50
80
81
detail of lead end
C D
S
R
Q
31
30
100
1
F
M
J
G
H
I
P
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
23.2±0.2
20.0±0.2
14.0±0.2
0.913
0.787
0.551
–0.008
+0.009
–0.008
+0.009
–0.008
D
F
17.2±0.2
0.8
0.677±0.008
0.031
G
0.6
0.024
+0.004
0.012
H
0.30±0.10
–0.005
I
0.15
0.006
J
K
0.65 (T.P.)
1.6±0.2
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.8±0.2
–0.008
+0.004
0.006
+0.10
0.15
M
–0.003
–0.05
0.10
N
P
Q
R
S
0.004
2.7
0.106
0.125±0.075
5°±5°
0.005±0.003
5°±5°
3.0 MAX.
0.119 MAX.
S100GF-65-3BA-3
31
µPD17P068
APPENDIX DEVELOPMENT TOOLS
The following tools are available to provide µPD17P068’s program development environment.
Hardware
Product
Description
The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators common to the
17K series. The IE-17K and IE-17K-ET should be connected with the host
computer (PC-9800 series or IBM PC/ATTM ) through an RS-232-C cable. The
In-circuit emulator
IE-17K
EMU-17K should be installed to an extension slot in the host computer
Note 1
IE-17K-ET
EMU-17K
(PC-9800 series). Each of the three products function as a dedicated emulator
Note 2
for each device by connecting it with an individual system evaluation board
(SE board). Using SIMPLEHOST which features an excellent user-machine
interface, makes user’s debugging environment more powerful. If the EMU-
17K is used, user can monitor the contents of the data memory in real time.
SE board
This SE board is for the µPD17068, 17P068, and 17008. This board can perform
evaluations of user’s system. To debug user’s programs, use it together with
an in-circuit emulator.
(SE-17008)
Emulation probe
This probe is used when emulating the µPD17P068GF.
(EP-17068GF)
Conversion socket
This socket converts pin arrangement for the 100-pin plastic QFP (14 × 20 mm)
to connect the emulation probe EP-17068GF to the target system.
Note 3
(EV-9200GF-100
)
PROM programmer
These products write programs to the internal PROM of the µPD17P068.
To perform programming, the program adapter AF-9808L is required to connect
to the PROM programmer.
Note 4
AF-9703
Note 4
AF-9704
AF-9705
Note 4
Note 4
AF-9706
Program adapter
This adapter is used together with the PROM programmer to program the
PROM in the µPD17P068.
Note 4
(AF-9808L
)
Notes 1. Inexpensive type: Power supply is required to connect externally.
2. Manufactured by IC Corporation. For details, call 03-3447-3793 Tokyo, Japan.
3. If the EP-17068GF is purchased, one EV-9200GF-100 is attached as a companion product. EV-9200GF-
100s can separately be purchased in 5-piece units.
4. Manufactured by Ando Electric Corporation. For details, call 03-3733-1151 Tokyo, Japan.
32
µPD17P068
Software
Host
Computer
Product
Description
OS
Media
Ordering Code
5 inch 2HD
µS5A10AS17K
This assembler can be used
for all 17K series devices.
To develop program of the
µPD17P068, the device file
(AS17068) are also required.
PC-9800 Series
MS-DOSTM
3.5 inch 2HD µS5A13AS17K
5 inch 2HC µS7B10AS17K
17K series
assembler
(AS17K)
IBM PC/AT
DOSTM
PC
3.5 inch 2HC µS7B13AS17K
5 inch 2HD µS5A10AS17068
3.5 inch 2HD µS5A13AS17068
5 inch 2HC µS7B10AS17068
3.5 inch 2HC µS7B13AS17068
This product is the device
file for the µPD17P068.
This device file is used
together with the assembler
AS17K.
PC-9800 series
IBM PC/AT
MS-DOS
PC DOS
Device file
(AS17068)
This software is used to
develop programs using an
in-circuit emulator and the
host computer.
5 inch 2HD
3.5 inch 2HD
5 inch 2HC
µS5A10lE17K
µS5A13lE17K
µS7B10lE17K
µS7B13lE17K
PC-9800 Series MS-DOS
Support
software
(SIMPLEHOST)
This product runs under
WindowsTM system and pro-
vides users with an excellent
user-machine interface.
Windows
IBM PC/AT
PC DOS
3.5 inch 2HC
Remark These products run with the versions of the operation systems shown below.
OS
Version
Note
MS-DOS
PC DOS
Windows
Ver.3.30 to Ver.5.00A
Note
Ver.3.1 to Ver.5.0
Ver.3.0 to Ver.3.1
Note With these products, the task swap function
is disabled though the Ver.5.00/5.00A of
MS-DOS and Ver.5.0 of the PC DOS support
the task swap function.
33
µPD17P068
[MEMO]
34
µPD17P068
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
35
µPD17P068
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
SIMPLEHOST is a registered trademark of NEC Corp.
MS-DOS and Windows are trademarks of Microsoft Corp.
PC/AT and PC DOS are trademarks of IBM Corp.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
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