UPD431000AGU-A10-9KH [NEC]
Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 13.40 MM, PLASTIC, REVERSE, TSOP1-32;
| 型号： | UPD431000AGU-A10-9KH |
| 厂家： | 
NEC |
| 描述： | Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 8 X 13.40 MM, PLASTIC, REVERSE, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD431000A
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
Description
The µPD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The µPD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In
addition to this, A and B versions are low voltage operations.
The µPD431000A is packed in 32-pin plastic DIP, 32-pin plastic SOP and 32-pin plastic TSOP (I) (8 × 13.4 mm) and
(8 × 20 mm).
Features
• 131,072 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Operating ambient temperature: TA = 0 to 70 °C
• Low VCC data retention: 2.0 V (MIN.)
• Output Enable input for easy application
• Two Chip Enable inputs: /CE1, CE2
Part number
Access time
ns (MAX.)
Operating supply Operating ambient
Supply current
At standby
voltage
V
temperature
°C
At operating
mA (MAX.)
At data retention
µA (MAX.)
µA (MAX.) Note1
µPD431000A-xxL
µPD431000A-xxLL
µPD431000A-Axx
µPD431000A-Bxx
70, 85
4.5 to 5.5
0 to 70
70
100
20
15
3
70 Note2, 100
3.0 to 5.5
2.7 to 5.5
35 Note3
30 Note4
13 Note5
11 Note6
70 Note2, 120, 150
Notes 1. TA ≤ 40 °C
2. VCC = 4.5 to 5.5 V
3. 70 mA (VCC > 3.6 V)
4. 70 mA (VCC > 3.3 V)
5. 20 µA (VCC > 3.6 V)
6. 20 µA (VCC > 3.3 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M11657EJAV0DS00 (10th edition)
Date Published April 2001 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
©
1990, 1993, 1995
µPD431000A
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient
Remark
voltage
V
temperature
°C
µPD431000ACZ-70L
32-PIN PLASTIC DIP
(15.24mm (600))
70
85
4.5 to 5.5
0 to 70
L version
LL version
L version
LL version
µPD431000ACZ-85L
µPD431000ACZ-70LL
µPD431000ACZ-85LL
µPD431000AGW-70L
µPD431000AGW-85L
70
85
32-PIN PLASTIC SOP
(13.34 mm (525))
70
4.5 to 5.5
85
µPD431000AGW-70LL
µPD431000AGW-85LL
µPD431000AGW-A10
µPD431000AGW-B12
µPD431000AGW-B15
µPD431000AGZ-85L-KJH
µPD431000AGZ-70LL-KJH
µPD431000AGZ-85LL-KJH
µPD431000AGZ-B15-KJH
µPD431000AGZ-70LL-KKH
µPD431000AGZ-B15-KKH
µPD431000AGU-B12-9JH
µPD431000AGU-B15-9JH
70
85
100
120
150
85
3.0 to 5.5
2.7 to 5.5
A version
B version
32-PIN PLASTIC TSOP(I)
(8x20) (Normal bent)
4.5 to 5.5
L version
70
LL version
85
150
70
2.7 to 5.5
4.5 to 5.5
2.7 to 5.5
2.7 to 5.5
B version
LL version
B version
B version
32-PIN PLASTIC TSOP(I)
(8x20) (Reverse bent)
32-PIN PLASTIC TSOP(I)
(8x13.4) (Normal bent)
150
120
150
2
Data Sheet M11657EJAV0DS
µPD431000A
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-PIN PLASTIC DIP (15.24 mm (600))
[µPD431000ACZ-xxL]
[µPD431000ACZ-xxLL]
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
2
A15
CE2
/WE
A13
A8
3
4
5
A6
6
A5
7
A9
A4
8
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O1
I/O2
I/O3
GND
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
3
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC SOP (13.34 mm (525))
[µPD431000AGW-xxL]
[µPD431000AGW-xxLL]
[µPD431000AGW-Axx]
[µPD431000AGW-Bxx]
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
2
A15
CE2
/WE
A13
A8
3
4
5
A6
6
A5
7
A9
A4
8
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O1
I/O2
I/O3
GND
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC TSOP(I) (8x20) (Normal bent)
[µPD431000AGZ-xxL-KJH]
[µPD431000AGZ-xxLL-KJH]
[µPD431000AGZ-Bxx-KJH]
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent)
[µPD431000AGZ-xxLL-KKH]
[µPD431000AGZ-Bxx-KKH]
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A11
A9
A8
A13
/WE
CE2
A15
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
[µPD431000AGU-Bxx-9JH]
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
/OE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
6
Data Sheet M11657EJAV0DS
µPD431000A
Block Diagram
VCC
GND
A0
A16
Address
buffer
Row
decoder
Memory cell array
1,048,576 bits
Sense amplifier /
Switching circuit
I/O1
Input data
controller
Output data
controller
I/O8
Column decoder
Address buffer
/CE1
CE2
/OE
/WE
Truth Table
/CE1
CE2
×
/OE
/WE
×
Mode
I/O
Supply current
H
×
L
L
L
×
×
H
L
×
Not selected
High impedance
ISB
L
×
H
H
Output disable
Read
ICCA
H
H
DOUT
DIN
H
L
Write
Remark × : VIH or VIL
7
Data Sheet M11657EJAV0DS
µPD431000A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
V
–0.5 Note to +7.0
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5 Note to VCC + 0.5
0 to 70
V
TA
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
µPD431000A-xxL
µPD431000A-xxLL
µPD431000A-Axx
µPD431000A-Bxx
Unit
MIN.
4.5
MAX.
5.5
MIN.
3.0
MAX.
5.5
MIN.
2.7
MAX.
5.5
Supply voltage
VCC
VIH
VIL
TA
V
V
High level input voltage
2.2
VCC+0.5
+0.8
2.2
VCC+0.5
+0.5
2.2
VCC+0.5
+0.5
Low level input voltage
–0.3 Note
0
–0.3 Note
0
–0.3 Note
0
V
Operating ambient temperature
70
70
70
°C
Note –3.0 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Input / Output capacitance
Symbol
CIN
Test conditions
MIN.
TYP.
MAX.
6
Unit
pF
VIN = 0 V
VI/O = 0 V
CI/O
10
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are not 100% tested.
8
Data Sheet M11657EJAV0DS
µPD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
µPD431000A-xxL
µPD431000A-xxLL
µPD431000A-Axx
Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 –1.0
+1.0 –1.0
+1.0
+1.0
µA
µA
I/O leakage
current
ILO
VI/O = 0 V to VCC,
/CE1 = VIH or CE2 = VIL
or /WE = VIL or /OE = VIH
/CE1 = VIL, CE2 = VIH,
II/O = 0 mA
Operating
ICCA1
40
70
40
70
40
70
mA
supply current
Minimum cycle time VCC ≤ 3.6 V
/CE1 = VIL, CE2 = VIH, II/O = 0 mA,
–
15
–
–
15
–
35
15
8
ICCA2
Cycle time = ∞
VCC ≤ 3.6 V
ICCA3
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
Cycle time = 1 µs, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
VCC ≤ 3.6 V
10
10
10
–
3
–
8
3
Standby
ISB
ISB1
/CE1 = VIH or CE2 = VIL
VCC ≤ 3.6 V
3
mA
supply current
–
–
2
/CE1 ≥ VCC − 0.2 V,
2
100
–
1
20
–
1
20
13
20
13
µA
CE2 ≥ VCC − 0.2 V
CE2 ≤ 0.2 V
VCC ≤ 3.6 V
0.5
1
ISB2
2
–
100
–
1
–
20
–
VCC ≤ 3.6 V
0.5
High level
VOH1
IOH = –1.0 mA, VCC ≥ 4.5 V
IOH = –0.5 mA
2.4
–
2.4
–
2.4
2.4
VCC–0.1
0.4
–
V
V
output voltage
VOH2
VOL1
IOH = –0.02 mA
–
–
Low level
IOL = 2.1 mA, VCC ≥ 4.5 V
IOL = 1.0 mA
0.4
–
0.4
0.4
0.1
output voltage
VOL2
IOL = 0.02 mA
–
–
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
9
Data Sheet M11657EJAV0DS
µPD431000A
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
µPD431000A-Bxx
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL
or /WE = VIL or /OE = VIH
Operating supply current
ICCA1
ICCA2
ICCA3
/CE1 = VIL, CE2 = VIH, II/O = 0 mA
Minimum cycle time
40
70
30
15
7
mA
VCC ≤ 3.3 V
VCC ≤ 3.3 V
/CE1 = VIL, CE2 = VIH, II/O = 0 mA,
Cycle time = ∞
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
Cycle time = 1 µs, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
/CE1 = VIH or CE2 = VIL
10
VCC ≤ 3.3 V
VCC ≤ 3.3 V
VCC ≤ 3.3 V
VCC ≤ 3.3 V
7
3
Standby supply current
ISB
ISB1
mA
2
/CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V
CE2 ≤ 0.2 V
1
20
11
20
11
µA
0.5
1
ISB2
0.5
High level output voltage
Low level output voltage
VOH1
IOH = –1.0 mA, VCC ≥ 4.5 V
IOH = –0.5 mA
2.4
2.4
V
V
VOH2
VOL1
IOH = –0.02 mA
VCC–0.1
IOL = 2.1 mA, VCC ≥ 4.5 V
IOL = 1.0 mA
0.4
0.4
0.1
VOL2
IOL = 0.02 mA
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless product classification.
10
Data Sheet M11657EJAV0DS
µPD431000A
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[µPD431000A-70L, µPD431000A-85L, µPD431000A-70LL, µPD431000A-85LL]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
1.5 V
Test points
Test points
1.5 V
1.5 V
0.8 V
Output Waveform
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tCO1, tCO2, tOE, tOH)
(tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
1.8 kΩ
I/O (Output)
I/O (Output)
990 Ω
990 Ω
100 pF
5 pF
CL
CL
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[µPD431000A-A10, µPD431000A-B12, µPD431000A-B15]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
1.5 V
Test points
1.5 V
1.5 V
0.5 V
Output Waveform
1.5 V
Test points
Output Load
AC characteristics should be measured with the following output load conditions.
Part number
Output load condition
tAA, tCO1, tCO2, tOE, tOH
1TTL + 50 pF
tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW
1TTL + 5 pF
µPD431000A-A10, 431000A-B12
µPD431000A-B15
1TTL + 100 pF
1TTL + 5 pF
11
Data Sheet M11657EJAV0DS
µPD431000A
Read Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
µPD431000A-70 µPD431000A-85
VCC ≥ 3.0 V
µPD431000A-A10
Unit Condition
µPD431000A-Axx
µPD431000A-Bxx
MIN.
70
MAX.
MIN.
85
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
70
35
85
85
85
45
100
100
100
50
Note
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
25
25
25
30
30
30
35
35
35
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/2)
Parameter
Symbol
VCC ≥ 2.7 V
Unit Condition
µPD431000A-B12
µPD431000A-B15
MIN.
MAX.
MIN.
MAX.
Read cycle time
tRC
tAA
120
150
ns
Address access time
120
120
120
60
150
150
150
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
40
40
40
50
50
50
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M11657EJAV0DS
µPD431000A
Read Cycle Timing Chart
t
RC
Address (Input)
/CE1 (Input)
t
AA
t
OH
t
CO1
CO2
t
t
HZ1
t
t
LZ1
CE2 (Input)
/OE (Input)
t
HZ2
LZ2
t
OE
t
OHZ
t
OLZ
High impedance
I/O (Output)
Data out
Remark In read cycle, /WE should be fixed to high level.
13
Data Sheet M11657EJAV0DS
µPD431000A
Write Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
µPD431000A-70 µPD431000A-85
VCC ≥ 3.0 V
µPD431000A-A10
Unit Condition
`
µPD431000A-Axx
µPD431000A-Bxx
MIN.
70
55
55
55
0
MAX.
MIN.
85
70
70
70
0
MAX.
MIN.
100
80
80
80
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
tAS
Write pulse width
tWP
tWR
tDW
tDH
50
5
60
5
60
0
Write recovery time
Data valid to end of write
Data hold time
35
0
35
0
60
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
25
30
35
Note
5
5
5
Note See the output load.
Remark These AC characteristics are in common regardless package types.
Write Cycle (2/2)
Parameter
Symbol
VCC ≥ 2.7 V
Unit Condition
µPD431000A-B12
MIN. MAX.
µPD431000A-B15
MIN. MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
120
100
100
100
0
150
120
120
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
tAS
Write pulse width
tWP
tWR
tDW
tDH
85
0
100
0
Write recovery time
Data valid to end of write
Data hold time
60
0
80
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
40
50
ns
ns
Note
5
5
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
14
Data Sheet M11657EJAV0DS
µPD431000A
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
t
CW1
CW2
/CE1 (Input)
CE2 (Input)
t
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
15
Data Sheet M11657EJAV0DS
µPD431000A
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC
Address (Input)
tAS
tCW1
/CE1 (Input)
tCW2
CE2 (Input)
/WE (Input)
tAW
tWP
tWR
tDW
tDH
High impedance
I/O (Input)
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
16
Data Sheet M11657EJAV0DS
µPD431000A
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
Address (Input)
/CE1 (Input)
t
CW1
t
AS
t
CW2
CE2 (Input)
t
AW
t
WP
t
WR
/WE (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
17
Data Sheet M11657EJAV0DS
µPD431000A
Low VCC Data Retention Characteristics (TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
µPD431000A-xxL
µPD431000A-xxLL
Unit
µPD431000A-Axx
µPD431000A-Bxx
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Data retention
supply voltage
VCCDR1
/CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V
VCCDR2 CE2 ≤ 0.2 V
2.0
5.5
2.0
5.5
V
2.0
5.5
2.0
5.5
Data retention
supply current
ICCDR1
VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V,
1
1
50 Note1
0.5
0.5
10 Note2
µA
ns
ms
CE2 ≥ VCC − 0.2 V
ICCDR2
tCDR
VCC = 3.0 V, CE2 ≤ 0.2 V
50 Note1
10 Note2
Chip deselection
to data retention
mode
0
5
0
5
Operation
tR
recovery time
Notes 1. 15 µA (TA ≤ 40 °C)
2. 3 µA (TA ≤ 40 °C)
18
Data Sheet M11657EJAV0DS
µPD431000A
Data Retention Timing Chart
(1) /CE1 Controlled
t
CDR
Data retention mode
t
R
V
CC
4.5 VNote
/CE1
V
IH (MIN.)
VCCDR (MIN.)
/CE1 ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
t
CDR
Data retention mode
t
R
V
CC
4.5 VNote
V
IH (MIN.)
V
CCDR (MIN.)
CE2
VIL (MAX.)
CE2 ≤ 0.2 V
GND
Note A version : 3.0 V, B version : 2.7 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
19
Data Sheet M11657EJAV0DS
µPD431000A
Package Drawings
32-PIN PLASTIC DIP (15.24mm(600))
32
17
1
16
A
K
L
J
I
P
F
C
M
D
R
N
M
B
H
G
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.25 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
40.64 MAX.
1.27 MAX.
2.54 (T.P.)
0.50±0.10
1.1 MIN.
2. Item "K" to center of leads when formed parallel.
3.2±0.3
0.51 MIN.
4.31 MAX.
5.08 MAX.
15.24 (T.P.)
13.2
J
K
L
+0.10
0.25
M
−0.05
N
P
R
0.25
0.9 MIN.
0 - 15°
P32C-100-600A-2
20
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC SOP (13.34 mm (525))
32
17
detail of lead end
P
1
16
A
H
I
F
G
J
S
B
L
N
S
C
K
D
M
M
ITEM MILLIMETERS
E
A
B
C
20.61 MAX.
0.78 MAX.
1.27 (T.P.)
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.10
0.40
D
−0.05
E
F
G
H
I
0.15±0.05
2.95 MAX.
2.7
14.1±0.3
11.3
J
1.4±0.2
+0.10
0.20
K
−0.05
L
M
N
0.8±0.2
0.12
0.10
+7°
3°
P
−3°
P32GW-50-525A-1
21
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC TSOP(I) (8x20)
detail of lead end
1
32
F
G
R
Q
L
16
17
S
E
P
I
J
A
S
C
B
M
D
M
K
N
S
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
0.97±0.08
18.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
K
L
M
N
P
0.10
0.10
20.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S32GZ-50-KJH1-2
22
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC TSOP(I) (8x20)
detail of lead end
E
1
32
S
L
Q
R
G
16
17
F
M
M
D
K
N
S
C
B
S
I
J
A
P
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
0.97±0.08
18.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
K
L
M
N
P
0.10
0.10
20.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S32GZ-50-KKH1-2
23
Data Sheet M11657EJAV0DS
µPD431000A
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
S
T
R
L
16
17
U
Q
P
I
J
A
G
S
H
B
C
M
K
N
S
D
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
1.0±0.05
12.4±0.2
11.8±0.1
0.8±0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4±0.2
0.1±0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6±0.15
P32GU-50-9JH-2
24
Data Sheet M11657EJAV0DS
µPD431000A
Recommended Soldering Conditions
The following conditions must be met when soldering conditions of the µPD431000A.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
Types of Surface Mount Device
µPD431000AGW-xxL
µPD431000AGW-xxLL
µPD431000AGW-Axx
µPD431000AGW-Bxx
: 32-PIN PLASTIC SOP (13.34 mm (525))
: 32-PIN PLASTIC SOP (13.34 mm (525))
: 32-PIN PLASTIC SOP (13.34 mm (525))
: 32-PIN PLASTIC SOP (13.34 mm (525))
µPD431000AGZ-xxL-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent)
µPD431000AGZ-xxLL-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent)
µPD431000AGZ-xxLL-KKH : 32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent)
µPD431000AGZ-Bxx-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent)
µPD431000AGZ-Bxx-KKH : 32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent)
µPD431000AGU-Bxx-9JH : 32-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
Please consult with our sales offices.
Types of Through Hole Mount Device
µPD431000ACZ-xxL: 32-PIN PLASTIC DIP (15.24 mm (600))
µPD431000ACZ-xxLL: 32-PIN PLASTIC DIP (15.24 mm (600))
Soldering process
Wave soldering (Only to leads)
Partial heating method
Soldering conditions
Solder temperature: 260 °C or below, Flow time: 10 seconds or below
Pin temperature : 300 °C or below, Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
25
Data Sheet M11657EJAV0DS
µPD431000A
[MEMO]
26
Data Sheet M11657EJAV0DS
µPD431000A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
27
Data Sheet M11657EJAV0DS
µPD431000A
•
The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
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and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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