UPD43256BGU-A85-A [NEC]
256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT; 256K - BIT的CMOS静态RAM的32K字×8位
| 型号： | UPD43256BGU-A85-A |
| 厂家： | 
NEC |
| 描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT |
| 文件： | 总28页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The μPD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available. And A and B versions are wide voltage operations.
The μPD43256B is packed in 28-pin PLASTIC DIP, 28-pin PLASTIC SOP and 28-pin PLASTIC TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number
Access time
ns (MAX.)
Operating supply Operating ambient
Supply current
voltage
V
temperature
°C
At operating
mA (MAX.)
At standby At data retention
μA (MAX.)
μA (MAX.) Note1
μPD43256B-xxL
μPD43256B-xxLL
μPD43256B-Axx
μPD43256B-BxxNote2
70, 85
4.5 to 5.5
0 to 70
45
50
15
3
2
85, 100Note2, 120Note2
100, 120, 150
3.0 to 5.5
2.7 to 5.5
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. Access time: 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M10770EJEV0DS00 (14th edition)
Date Published June 2006 NS CP (K)
Printed in Japan
1990, 1993, 1994
μPD43256B
Ordering Information
(1/2)
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient Remark
voltage
V
temperature
°C
μPD43256BCZ-70L
28-pin PLASTIC DIP
(15.24 mm (600))
70
85
4.5 to 5.5
0 to 70
L version
LL version
L version
LL version
A version
μPD43256BCZ-85L
μPD43256BCZ-70LL
70
μPD43256BCZ-85LL
85
μPD43256BGU-70L
28-pin PLASTIC SOP
(11.43 mm (450))
70
μPD43256BGU-85L
85
μPD43256BGU-70LL
μPD43256BGU-85LL
μPD43256BGU-A85
70
85
85
3.0 to 5.5
μPD43256BGU-A10
100
120
100
120
70
μPD43256BGU-A12
μPD43256BGU-B10
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
B version
LL version
A version
μPD43256BGU-B12
μPD43256BGW-70LL-9JL
μPD43256BGW-85LL-9JL
μPD43256BGW-A85-9JL
μPD43256BGW-A10-9JL
μPD43256BGW-A12-9JL
μPD43256BGW-B10-9JL
μPD43256BGW-B12-9JL
μPD43256BGW-B15-9JL
μPD43256BGW-70LL-9KL
μPD43256BGW-85LL-9KL
μPD43256BGW-A85-9KL
μPD43256BGW-A10-9KL
μPD43256BGW-A12-9KL
μPD43256BGW-B10-9KL
μPD43256BGW-B12-9KL
μPD43256BGW-B15-9KL
28-pin PLASTIC TSOP (I)
(8x13.4) (Normal bent)
85
85
100
120
100
120
150
70
2.7 to 5.5
B version
28-pin PLASTIC TSOP (I)
(8x13.4) (Reverse bent)
4.5 to 5.5
3.0 to 5.5
LL version
A version
85
85
100
120
100
120
150
2.7 to 5.5
B version
Data Sheet M10770EJEV0DS
2
μPD43256B
(2/2)
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient Remark
voltage
V
temperature
°C
μPD43256BGU-70L-A
28-pin PLASTIC SOP
(11.43 mm (450))
70
85
4.5 to 5.5
0 to 70
L version
LL version
A version
μPD43256BGU-85L-A
μPD43256BGU-70LL-A
70
μPD43256BGU-85LL-A
85
μPD43256BGU-A85-A
85
3.0 to 5.5
μPD43256BGU-A10-A
100
120
100
120
70
μPD43256BGU-A12-A
μPD43256BGU-B10-A
2.7 to 5.5
4.5 to 5.5
3.0 to 5.5
B version
LL version
A version
μPD43256BGU-B12-A
μPD43256BGW-70LL-9JL-A
μPD43256BGW-85LL-9JL-A
μPD43256BGW-A85-9JL-A
μPD43256BGW-A10-9JL-A
μPD43256BGW-A12-9JL-A
μPD43256BGW-B10-9JL-A
μPD43256BGW-B12-9JL-A
μPD43256BGW-B15-9JL-A
μPD43256BGW-70LL-9KL-A
μPD43256BGW-85LL-9KL-A
μPD43256BGW-A85-9KL-A
μPD43256BGW-A10-9KL-A
μPD43256BGW-A12-9KL-A
μPD43256BGW-B10-9KL-A
μPD43256BGW-B12-9KL-A
μPD43256BGW-B15-9KL-A
28-pin PLASTIC TSOP (I)
(8x13.4) (Normal bent)
85
85
100
120
100
120
150
70
2.7 to 5.5
B version
28-pin PLASTIC TSOP (I)
(8x13.4) (Reverse bent)
4.5 to 5.5
3.0 to 5.5
LL version
A version
85
85
100
120
100
120
150
2.7 to 5.5
B version
Remark Products with -A at the end of the part number are lead-free products.
Data Sheet M10770EJEV0DS
3
μPD43256B
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-pin PLASTIC DIP (15.24 mm (600))
[ μPD43256BCZ-xxL ]
[ μPD43256BCZ-xxLL ]
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
/WE
A13
A8
3
A6
4
A5
5
A9
A4
6
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A3
7
A2
8
A1
9
A0
10
11
12
13
14
I/O1
I/O2
I/O3
GND
A0 - A14
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS
/WE
/OE
VCC
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
GND
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10770EJEV0DS
4
μPD43256B
28-pin PLASTIC SOP (11.43 mm (450))
[ μPD43256BGU-xxL ]
[ μPD43256BGU-xxLL ]
[ μPD43256BGU-Axx ]
[ μPD43256BGU-Bxx ]
[ μPD43256BGU-xxL-A ]
[ μPD43256BGU-xxLL-A ]
[ μPD43256BGU-Axx-A ]
[ μPD43256BGU-Bxx-A ]
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
/WE
A13
A8
3
A6
4
A5
5
A9
A4
6
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A3
7
A2
8
A1
9
A0
10
11
12
13
14
I/O1
I/O2
I/O3
GND
A0 - A14
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS
/WE
/OE
VCC
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
GND
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10770EJEV0DS
5
μPD43256B
28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
[ μPD43256BGW-xxLL-9JL ]
[ μPD43256BGW-Axx-9JL ]
[ μPD43256BGW-Bxx-9JL ]
[ μPD43256BGW-xxLL-9JL-A ]
[ μPD43256BGW-Axx-9JL-A ]
[ μPD43256BGW-Bxx-9JL-A ]
/OE
A11
A9
A8
A13
/WE
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
VCC
A14
A12
A7
A6
A5
9
10
11
12
13
14
A4
A3
A1
A2
28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
[ μPD43256BGW-xxLL-9KL ]
[ μPD43256BGW-Axx-9KL ]
[ μPD43256BGW-Bxx-9KL ]
[ μPD43256BGW-xxLL-9KL-A ]
[ μPD43256BGW-Axx-9KL-A ]
[ μPD43256BGW-Bxx-9KL-A ]
A10
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/OE
A11
A9
A8
A13
/WE
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
VCC
A14
A12
A7
A6
A5
A1
A2
A4
A3
A0 - A14
:
:
:
:
Address inputs
/OE : Output Enable
I/O1 - I/O8
/CS
Data inputs / outputs VCC
:
Power supply
Ground
Chip Select
GND :
/WE
Write Enable
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10770EJEV0DS
6
μPD43256B
Block Diagram
A0
Address
buffer
Row
decoder
Memory cell array
262,144 bits
A14
Sense amplifier /
Switching circuit
I/O1
I/O8
Input data
controller
Output data
controller
Column decoder
Address buffer
/CS
/OE
/WE
V
CC
GND
Truth Table
/CS
H
/OE
×
/WE
×
Mode
I/O
Supply current
Not selected
Output disable
Write
High impedance
ISB
L
H
H
ICCA
L
×
L
DIN
L
L
H
Read
DOUT
Remark × : VIH or VIL
Data Sheet M10770EJEV0DS
7
μPD43256B
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
–0.5Note to +7.0
–0.5Note to VCC + 0.5
0 to 70
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
μPD43256B-xxL
μPD43256B-xxLL
μPD43256B-Axx
μPD43256B-Bxx
Parameter
Symbol Condition
Unit
MIN.
4.5
MAX.
5.5
MIN.
3.0
MAX.
5.5
MIN.
2.7
MAX.
5.5
Supply voltage
VCC
VIH
VIL
TA
V
V
High level input voltage
2.2
VCC+0.5
+0.8
2.2
VCC+0.5
+0.5
2.2
VCC+0.5
+0.5
Low level input voltage
–0.3 Note
–0.3 Note
–0.3 Note
V
°C
Operating ambient temperature
0
70
0
70
0
70
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
pF
CIN
VIN = 0 V
VI/O = 0 V
5
8
Input / Output capacitance
CI/O
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M10770EJEV0DS
8
μPD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
μPD43256B-xxL
μPD43256B-xxLL
Parameter
Symbol
Test condition
Unit
MIN. TYP. MAX. MIN. TYP. MAX.
μA
μA
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0
+1.0
–1.0
–1.0
+1.0
+1.0
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
Operating supply current
ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA
45
10
10
45
10
10
mA
ICCA2
ICCA3
/CS = VIL, II/O = 0 mA
/CS ≤ 0.2 V, Cycle = 1 MHz,
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
Standby supply current
High level output voltage
Low level output voltage
ISB
/CS = VIH
3
3
mA
μA
V
/CS ≥ VCC − 0.2 V
ISB1
1.0
50
0.5
15
VOH1 IOH = –1.0 mA
VOH2 IOH = –0.1 mA
2.4
2.4
VCC–0.5
VCC–0.5
VOL
IOL = 2.1 mA
0.4
0.4
V
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
9
μPD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
μPD43256B-Axx
MIN.
μPD43256B-Bxx
Parameter
Symbol
Test condition
Unit
TYP. MAX. MIN.
TYP. MAX.
+1.0
μA
μA
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0
+1.0
–1.0
–1.0
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
+1.0
μPD43256B-Axx
Operating supply current
ICCA1
/CS = VIL,
45
–
–
45
20
10
5
mA
μPD43256B-Bxx
VCC ≤ 3.3 V
Minimum cycle time,
II/O = 0 mA
–
ICCA2
ICCA3
ISB
/CS = VIL, II/O = 0 mA
10
–
VCC ≤ 3.3 V
/CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA,
10
–
10
5
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
VCC ≤ 3.3 V
Standby supply current
/CS = VIH
3
3
mA
VCC ≤ 3.3 V
VCC ≤ 3.3 V
–
2
/CS ≥ VCC − 0.2 V
μA
ISB1
0.5
15
–
0.5
0.5
15
10
IOH = –1.0 mA, VCC ≥ 4.5 V
High level output voltage
Low level output voltage
VOH1
2.4
2.4
2.4
2.4
V
V
IOH = –0.5 mA, VCC < 4.5 V
VOH2 IOH = –0.02 mA
VCC–0.1
VCC–0.1
IOL = 2.1 mA, VCC ≥ 4.5 V
VOL
0.4
0.4
0.1
0.4
0.4
0.1
IOL = 1.0 mA, VCC < 4.5 V
IOL = 0.02 mA
VOL1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
10
μPD43256B
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ μPD43256B-70L, μPD43256B-85L, μPD43256B-70LL, μPD43256B-85LL ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
1.5 V
Test points
1.5 V
0.8 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tACS, tOE, tOH)
(tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
1.8 kΩ
I/O (Output)
I/O (Output)
990 Ω
990 Ω
100 pF
5 pF
C
L
C
L
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[ μPD43256B-A85, μPD43256B-A10, μPD43256B-A12, μPD43256B-B10, μPD43256B-B12, μPD43256B-B15 ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
1.5 V
Test points
1.5 V
0.5 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH
tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 100 pF
1TTL + 5 pF
Data Sheet M10770EJEV0DS
11
μPD43256B
Read Cycle (1/2)
VCC ≥ 4.5 V
Parameter
Symbol
Unit
Condition
μPD43256B-70
μPD43256B-85
μPD43256B-A85/A10/A12
μPD43256B-B10/B12/B15
MIN.
MAX.
MIN.
85
MAX.
Read cycle time
tRC
tAA
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
35
85
85
40
Note
/CS access time
tACS
tOE
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
tOH
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
30
30
30
30
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
VCC ≥ 3.0 V
μPD43256B μPD43256B μPD43256B μPD43256B μPD43256B μPD43256B
-A85 -A10 -A12 -B10 -B12 -B15
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Parameter
Symbol
Unit Con-
dition
Read cycle time
tRC
tAA
85
100
120
100
120
150
ns
Address access
time
85
100
120
100
120
150
ns Note
/CS access time
/OE access time
tACS
85
50
100
60
120
60
100
60
120
60
150
70
ns
ns
ns
tOE
tOH
Output hold from
address change
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
/CS to output in
low impedance
tCLZ
tOLZ
tCHZ
tOHZ
ns
ns
ns
ns
/OE to output in
low impedance
/CS to output in
high impedance
35
35
35
35
40
40
35
35
40
40
50
50
/OE to output in
high impedance
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
12
μPD43256B
Read Cycle Timing Chart
tRC
Address (Input)
/CS (Input)
tAA
tOH
tACS
tCHZ
tCLZ
/OE (Input)
I/O (Output)
tOHZ
t
OE
t
OLZ
High impedance
Data out
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M10770EJEV0DS
13
μPD43256B
Write Cycle (1/2)
VCC ≥ 4.5 V
Parameter
Symbol
Unit
Condition
μPD43256B-70
μPD43256B-85
μPD43256B-A85/A10/A12
μPD43256B-B10/B12/B15
MIN.
MAX.
MIN.
85
70
70
60
35
0
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
70
50
50
55
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
Data valid to end of write
Data hold time
Address setup time
tAS
0
0
Write recovery time
tWR
tWHZ
tOW
0
0
/WE to output in high impedance
Output active from end of write
30
30
Note
10
10
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
VCC ≥ 3.0 V
μPD43256B μPD43256B μPD43256B μPD43256B μPD43256B μPD43256B
-A85 -A10 -A12 -B10 -B12 -B15
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Parameter
Symbol
Unit Con-
dition
Write cycle time
tWC
tCW
tAW
85
70
70
100
70
120
90
100
70
120
90
150
100
100
ns
ns
ns
/CS to end of write
Address valid to
end of write
70
90
70
90
Write pulse width
tWP
tDW
60
60
60
60
80
70
60
60
80
70
90
80
ns
ns
Data valid to end
of write
ns
Data hold time
Address setup
tDH
tAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
Write recovery
tWR
tWHZ
ns
/WE to output in
high impedance
30
35
40
35
40
50
ns Note
Output active
tOW
10
10
10
10
10
10
ns
from end of write
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
14
μPD43256B
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
t
CW
/CS (Input)
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
Data Sheet M10770EJEV0DS
15
μPD43256B
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
Address (Input)
t
AS
t
CW
/CS (Input)
/WE (Input)
t
AW
t
WP
t
WR
t
DW
t
DH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M10770EJEV0DS
16
μPD43256B
Low VCC Data Retention Characteristics (TA = 0 to 70 °C)
μPD43256B-xxL
μPD43256B-xxLL
μPD43256B-Axx
μPD43256B-Bxx
Parameter
Symbol
Test Condition
Unit
MIN.
TYP.
0.5
MAX.
MIN.
TYP.
MAX.
/CS ≥ VCC − 0.2 V
VCC = 3.0 V, /CS ≥ VCC − 0.2 V
Data retention supply voltage
Data retention supply current
VCCDR
2.0
5.5
2.0
5.5
V
20Note1
0.5
7Note2
μA
ns
ICCDR
tCDR
Chip deselection
0
5
0
5
to data retention mode
Operation recovery time
tR
ms
Notes 1. 3 μA (TA ≤ 40 °C)
2. 2 μA (TA ≤ 40 °C), 1 μA (TA ≤ 25 °C)
Data Retention Timing Chart
tCDR
Data retention mode
tR
VCC
4.5 VNote
/CS
VIH (MIN.)
V
CCDR (MIN.)
/CS ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
Data Sheet M10770EJEV0DS
17
μPD43256B
Package Drawings
28-PIN PLASTIC DIP (15.24 mm (600))
28
15
1
14
A
J
K
L
I
F
C
B
R
M
M
D
N
H
G
NOTES
1. Each lead centerline is located within 0.25 mm
ITEM MILLIMETERS
of its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
38.10 MAX.
2.54 MAX.
2.54 (T.P.)
0.50 0.10
1.2 MIN.
2. Item "K" to center of leads when formed parallel.
3.6 0.3
0.51 MIN.
4.31 MAX.
5.72 MAX.
15.24 (T.P.)
13.2
J
K
L
+0.10
0.25
M
−0.05
N
R
0.25
0 - 15°
P28C-100-600A1-2
Data Sheet M10770EJEV0DS
18
μPD43256B
28-PIN PLASTIC SOP (11.43 mm (450))
28
15
detail of lead end
P
1
14
A
F
H
G
I
J
S
C
L
N
S
M
D
M
B
K
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.6
18.0
A
−0.05
B
C
1.27 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.2 0.1
2.95 MAX.
2.55 0.1
11.8 0.3
8.4 0.1
1.7 0.2
0.22 0.05
0.7 0.2
0.12
J
K
L
M
N
0.10
+7°
3°
P
−3°
P28GU-50-450A-4
Data Sheet M10770EJEV0DS
19
μPD43256B
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
S
R
Q
14
15
P
I
A
J
G
S
B
C
H
M
M
D
L
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
8.0 0.1
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4 0.2
11.8 0.1
0.8 0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5 0.1
0.08
0.10
13.4 0.2
0.1 0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9JL-2
Data Sheet M10770EJEV0DS
20
μPD43256B
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
Q
R
14
15
S
K
M
N
M
D
S
L
H
C
B
S
G
J
I
A
P
NOTE
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
A
B
C
8.0 0.1
its true position (T.P.) at maximum material condition.
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4 0.2
11.8 0.1
0.8 0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5 0.1
0.08
0.10
13.4 0.2
0.1 0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9KL-2
Data Sheet M10770EJEV0DS
21
μPD43256B
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD43256B.
Types of Surface Mount Device
μPD43256BGU-xxL
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-xxLL
μPD43256BGU-Axx
: 28-pin PLASTIC SOP (11.43 mm (450))
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-Bxx
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGW-xxLL-9JL
μPD43256BGW-xxLL-9KL
μPD43256BGW-Axx-9JL
μPD43256BGW-Axx-9KL
μPD43256BGW-Bxx-9JL
μPD43256BGW-Bxx-9KL
μPD43256BGU-xxL-A
μPD43256BGU-xxLL-A
μPD43256BGU-Axx-A
μPD43256BGU-Bxx-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC SOP (11.43 mm (450))
: 28-pin PLASTIC SOP (11.43 mm (450))
: 28-pin PLASTIC SOP (11.43 mm (450))
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGW-xxLL-9JL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-xxLL-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Axx-9JL-A
μPD43256BGW-Axx-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Bxx-9JL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-Bxx-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
Types of Through Hole Mount Device
μPD43256BCZ-xxL
μPD43256BCZ-xxLL
: 28-pin PLASTIC DIP (15.24 mm (600))
: 28-pin PLASTIC DIP (15.24 mm (600))
Soldering process
Soldering conditions
Solder temperature : 260 °C or below,
Wave soldering (only to leads)
Partial heating method
Flow time : 10 seconds or below
Terminal temperature : 300 °C or below,
Time : 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
Data Sheet M10770EJEV0DS
22
μPD43256B
Revision History
Edition/
Page
Previous
Type of
revision
Location
Description
Date
This
(Previous edition → This edition)
edition
p.1
edition
p.1
14th edition/
Jun. 2006
Deletion
−
Description of Version X and P has been deleted.
Data Sheet M10770EJEV0DS
23
μPD43256B
[ MEMO ]
Data Sheet M10770EJEV0DS
24
μPD43256B
[ MEMO ]
Data Sheet M10770EJEV0DS
25
μPD43256B
[ MEMO ]
Data Sheet M10770EJEV0DS
26
μPD43256B
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M10770EJEV0DS
27
μPD43256B
•
The information in this document is current as of June, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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•
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defined above).
M8E 02. 11-1
相关型号：
UPD43256BGW-70LL-A
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, PLASTIC, TSOP1-28
RENESAS
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