UPD441000LGU-B70X-9KH [NEC]
1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION; 1M位CMOS静态RAM 128K - WORD 8位的扩展工作温度
| 型号： | UPD441000LGU-B70X-9KH |
| 厂家： | 
NEC |
| 描述： | 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总28页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD441000L-X
µ
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD441000L-X is a high speed, low power, 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The µPD441000L-X has two chip enable pins (/CE1, CE2) to extend the capacity.
★
The µPD441000L-X is packed in 32-pin plastic SOP and 32-pin plastic TSOP (I) (8×13.4 mm) and (8×20 mm).
Features
• 131,072 words by 8 bits organization
• Fast access time : 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation
(B version : VCC = 2.7 to 3.6 V, C version : VCC = 2.2 to 3.6 V, D version : VCC = 1.8 to 3.6 V)
• Low VCC data retention
(B version : 2.0 V (MIN.), C version, D version : 1.5 V (MIN.))
• Operating ambient temperature : TA = –25 to +85 °C
• Output Enable input for easy application
• Two Chip Enable inputs : /CE1, CE2
Part number
Access time Operating supply Operating ambient
Supply current
At standby
ns (MAX.)
voltage
V
temperature
°C
At operating
mA (MAX.)
At data retention
µA (MAX.)
µA (MAX.)
µPD441000L-BxxX
µPD441000L-CxxX
µPD441000L-DxxX
70, 85, 100
100, 120
120, 150
2.7 to 3.6
2.2 to 3.6
1.8 to 3.6
−25 to +85
25
2
2Note
Note 0.5 µ
A ≤ 40 °C)
A (T
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13714EJ5V0DSJ1 (5th edition)
Date Published December 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
1998
©
µPD441000L-X
★
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating
Operating
Remark
supply voltage temperature
V
°C
µPD441000LGW-B70X
32-pin Plastic SOP
(13.34 mm (525))
70
85
2.7 to 3.6
−25 to +85
B version
µPD441000LGW-B85X
µPD441000LGW-B10X
100
70
µPD441000LGU-B70X-9JH
µPD441000LGU-B85X-9JH
µPD441000LGU-B10X-9JH
µPD441000LGU-B70X-9KH
µPD441000LGU-B85X-9KH
µPD441000LGU-B10X-9KH
µPD441000LGZ-B70X-KJH
µPD441000LGZ-B85X-KJH
µPD441000LGZ-B10X-KJH
µPD441000LGZ-B70X-KKH
µPD441000LGZ-B85X-KKH
µPD441000LGZ-B10X-KKH
µPD441000LGW-C10X
32-pin Plastic TSOP (I)
(8×13.4) (Normal bent)
85
100
70
32-pin Plastic TSOP (I)
(8×13.4) (Reverse bent)
85
100
70
32-pin Plastic TSOP (I)
(8×20) (Normal bent)
85
100
70
32-pin Plastic TSOP (I)
(8×20) (Reverse bent)
85
100
100
120
100
120
100
120
100
120
100
120
120
150
120
150
120
150
120
150
120
150
32-pin Plastic SOP
2.2 to 3.6
C version
µPD441000LGW-C12X
(13.34 mm (525))
µPD441000LGU-C10X-9JH
µPD441000LGU-C12X-9JH
µPD441000LGU-C10X-9KH
µPD441000LGU-C12X-9KH
µPD441000LGZ-C10X-KJH
µPD441000LGZ-C12X-KJH
µPD441000LGZ-C10X-KKH
µPD441000LGZ-C12X-KKH
µPD441000LGW-D12X
32-pin Plastic TSOP (I)
(8×13.4) (Normal bent)
32-pin Plastic TSOP (I)
(8×13.4) (Reverse bent)
32-pin Plastic TSOP (I)
(8×20) (Normal bent)
32-pin Plastic TSOP (I)
(8×20) (Reverse bent)
32-pin Plastic SOP
1.8 to 3.6
D version
µPD441000LGW-D15X
(13.34 mm (525))
µPD441000LGU-D12X-9JH
µPD441000LGU-D15X-9JH
µPD441000LGU-D12X-9KH
µPD441000LGU-D15X-9KH
µPD441000LGZ-D12X-KJH
µPD441000LGZ-D15X-KJH
µPD441000LGZ-D12X-KKH
µPD441000LGZ-D15X-KKH
32-pin Plastic TSOP (I)
(8×13.4) (Normal bent)
32-pin Plastic TSOP (I)
(8×13.4) (Reverse bent)
32-pin Plastic TSOP (I)
(8×20) (Normal bent)
32-pin Plastic TSOP (I)
(8×20) (Reverse bent)
2
Data Sheet M13714EJ5V0DS
µPD441000L-X
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-pin Plastic SOP (13.34 mm (525))
[ µPD441000LGW-BxxX ]
[ µPD441000LGW-CxxX ]
[ µPD441000LGW-DxxX ]
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
2
A15
CE2
/WE
A13
A8
3
4
5
A6
6
A5
7
A9
A4
8
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
★
A3
9
A2
10
11
12
13
14
15
16
A1
A0
I/O1
I/O2
I/O3
GND
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
3
Data Sheet M13714EJ5V0DS
µPD441000L-X
32-pin Plastic TSOP (I) (8×13.4) (Normal bent)
[ µPD441000LGU-BxxX-9JH ]
[ µPD441000LGU-CxxX-9JH ]
[ µPD441000LGU-DxxX-9JH ]
32-pin Plastic TSOP (I) (8×20) (Normal bent)
[ µPD441000LGZ-BxxX-KJH ]
[ µPD441000LGZ-CxxX-KJH ]
[ µPD441000LGZ-DxxX-KJH ]
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
★
NC
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M13714EJ5V0DS
µPD441000L-X
32-pin Plastic TSOP (I) (8×13.4) (Reverse bent)
[ µPD441000LGU-BxxX-9KH ]
[ µPD441000LGU-CxxX-9KH ]
[ µPD441000LGU-DxxX-9KH ]
32-pin Plastic TSOP (I) (8×20) (Reverse bent)
[ µPD441000LGZ-BxxX-KKH ]
[ µPD441000LGZ-CxxX-KKH ]
[ µPD441000LGZ-DxxX-KKH ]
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
/WE
CE2
A15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
★
NC
A16
A14
A12
A7
A6
A5
A4
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
GND
NC
: Write Enable
: Output Enable
: Power supply
: Ground
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M13714EJ5V0DS
µPD441000L-X
Block Diagram
A0
Address
buffer
Row
decoder
Memory cell array
1,048,576 bits
A16
Sense amplifier /
Switching circuit
I/O1
I/O8
Input data
controller
Output data
controller
Column decoder
Address buffer
/CE1
CE2
/OE
/WE
V
CC
GND
Truth Table
/CE1
CE2
×
/OE
×
/WE
Mode
Not selected
Not selected
Output disable
Read
I/O
Supply current
ISB
H
×
L
L
L
×
×
High impedance
High impedance
High impedance
DOUT
L
×
H
H
L
H
H
L
ICCA
H
H
×
Write
DIN
Remark × : VIH or VIL
6
Data Sheet M13714EJ5V0DS
µPD441000L-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VCC
VT
Condition
Rating
Unit
V
Supply voltage
–0.5Note to +4.6
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5Note to VCC+0.5
V
TA
–25 to +85
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
µPD441000L-BxxX µPD441000L-CxxX µPD441000L-DxxX Unit
MIN.
2.7
MAX.
3.6
MIN.
2.2
MAX.
3.6
MIN.
1.8
MAX.
3.6
Supply voltage
VCC
VIH
V
V
High level input voltage
Low level input voltage
2.7 V ≤ VCC ≤ 3.6 V
2.2 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.2 V
2.4
VCC+0.5
–
2.4
VCC+0.5
VCC+0.5
–
2.4
VCC+0.5
VCC+0.5
VCC+0.5
+0.2
–
2.0
2.0
–
–
–
1.6
VIL
TA
–0.3 Note
+0.5
+85
–0.3 Note
+0.3
–0.3 Note
V
Operating ambient
temperature
–25
–25
+85
–25
+85
°C
Note –3.0 V (MIN.) (Pulse width : 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
CIN
VIN = 0 V
VI/O = 0 V
6
pF
pF
Input / Output capacitance
CI/O
10
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
7
Data Sheet M13714EJ5V0DS
µPD441000L-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
µPD441000L-BxxX µPD441000L-CxxX µPD441000L-DxxX Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage
current
ILI
VIN = 0 V to VCC
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 µA
I/O leakage
current
ILO
VI/O = 0 V to VCC, /CE1 = VIH or
CE2 = VIL or /WE = VIL or /OE = VIH
/CE1 = VIL, CE2 = VIH,
–1.0
+1.0 –1.0
+1.0 –1.0
+1.0 µA
Operating
supply current
ICCA1
23
–
25
–
23
20
–
25
23
–
23
20
17
25
23
20
5
mA
Minimum cycle time, VCC ≤ 2.7 V
II/O = 0 mA
VCC ≤ 2.2 V
–
–
ICCA2
/CE1 = VIL, CE2 = VIH,
II/O = 0 mA
5
5
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
4
4
–
–
3
ICCA3
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
4
4
4
Cycle = 1 MHz, II/O = 0 mA,
VIL ≤ 0.2 V,
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
–
3
–
3
3
VIH ≥ VCC – 0.2 V
Standby
ISB
/CE1 = VIH or CE2 = VIL
0.3
2
0.3
2
0.3 mA
supply current
ISB1
/CE1 ≥ VCC – 0.2 V,
0.05
–
0.05
0.04
–
0.05
0.04
2
2
µA
CE2 ≥ VCC – 0.2 V
CE2 ≤ 0.2 V
VCC ≤ 2.7 V
–
2
VCC ≤ 2.2 V
–
–
–
0.03 1.5
ISB2
VOH
VOL
0.05
–
2
0.05
0.04
–
2
0.05
0.04
2
2
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
2
–
–
–
0.03 1.5
High level
IOH = –0.5 mA
IOL = 1.0 mA
2.4
–
2.4
1.8
–
2.4
1.8
1.5
0.4
V
V
output voltage
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
Low level
0.4
0.4
output voltage
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types and access time.
8
Data Sheet M13714EJ5V0DS
µPD441000L-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ µPD441000L-B70X, µPD441000L-B85X, µPD441000L-B10X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test Points
Test Points
1.5 V
0.5 V
Output Waveform
1.5 V
1.5 V
Output Load
1TTL + 50 pF
[ µPD441000L-C10X, µPD441000L-C12X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.0 V
1.1 V
0.3 V
Test Points
1.1 V
Output Waveform
1.1 V
Test Points
1.1 V
Output Load
1TTL + 30 pF
[ µPD441000L-D12X, µPD441000L-D15X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
1.6 V
0.9 V
0.2 V
Test Points
0.9 V
Output Waveform
0.9 V
Test Points
0.9 V
Output Load
1TTL + 30 pF
9
Data Sheet M13714EJ5V0DS
µPD441000L-X
Read Cycle (1/3) (B version)
Parameter
Symbol
µ
-B70X
PD441000L
µ
-B85X
PD441000L
µ
-B10X Unit Condition
PD441000L
MIN.
70
MAX.
MIN.
85
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
70
35
85
85
85
45
100
100
100
50
Note 1
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
25
25
25
30
30
30
35
35
35
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/3) (C version)
Parameter
Symbol
µ
-C10X
MAX.
µ
-C12X
Unit Condition
ns
PD441000L
PD441000L
MIN.
100
MIN.
120
MAX.
Read cycle time
tRC
tAA
Address access time
100
100
100
50
120
120
120
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
35
35
35
40
40
40
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
10
Data Sheet M13714EJ5V0DS
µPD441000L-X
Read Cycle (3/3) (D version)
Parameter
Symbol
µ
-D12X
MAX.
µ
-D15X
MAX.
Unit Condition
ns
PD441000L
PD441000L
MIN.
120
MIN.
150
Read cycle time
tRC
tAA
Address access time
120
120
120
60
150
150
150
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
/CE1 access time
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in low impedance
CE2 to output in low impedance
/OE to output in low impedance
/CE1 to output in high impedance
CE2 to output in high impedance
/OE to output in high impedance
tOH
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
40
40
40
50
50
50
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart
t
RC
Address (Input)
/CE1 (Input)
t
AA
t
OH
t
CO1
CO2
t
t
HZ1
t
t
LZ1
CE2 (Input)
/OE (Input)
t
HZ2
LZ2
t
OE
t
OHZ
t
OLZ
High impedance
I/O (Output)
Data out
Remark In read cycle, /WE should be fixed to high level.
11
Data Sheet M13714EJ5V0DS
µPD441000L-X
Write Cycle (1/3) (B version)
Parameter
Symbol
µ
-B70X
PD441000L
µ
-B85X
PD441000L
µ
-B10X Unit Condition
PD441000L
MIN.
70
55
55
55
0
MAX.
MIN.
85
70
70
70
0
MAX.
MIN.
100
80
80
80
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
50
0
60
0
60
0
Write recovery time
Data valid to end of write
Data hold time
35
0
35
0
40
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
25
30
35
Note
5
5
5
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Write Cycle (2/3) (C version)
Parameter
Symbol
µ
-C10X
MAX.
µ
-C12X
Unit Condition
PD441000L
PD441000L
MIN.
100
80
80
80
0
MIN.
120
100
100
100
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
60
0
85
Write recovery time
0
Data valid to end of write
Data hold time
45
0
60
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
35
40
ns
ns
Note
5
5
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M13714EJ5V0DS
µPD441000L-X
Write Cycle (3/3) (D version)
Parameter
Symbol
µ
-D12X
MAX.
µ
-D15X
MAX.
Unit Condition
PD441000L
PD441000L
MIN.
120
100
100
100
0
MIN.
150
120
120
120
0
Write cycle time
tWC
tCW1
tCW2
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
85
100
0
Write recovery time
0
Data valid to end of write
Data hold time
60
80
0
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
40
50
ns
ns
Note
5
5
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
13
Data Sheet M13714EJ5V0DS
µPD441000L-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
t
CW1
CW2
/CE1 (Input)
CE2 (Input)
t
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
14
Data Sheet M13714EJ5V0DS
µPD441000L-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC
Address (Input)
tAS
tCW1
/CE1 (Input)
tCW2
CE2 (Input)
/WE (Input)
tAW
tWP
tWR
tDW
tDH
High impedance
I/O (Input)
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
15
Data Sheet M13714EJ5V0DS
µPD441000L-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
Address (Input)
/CE1 (Input)
t
CW1
t
AS
t
CW2
CE2 (Input)
t
AW
t
WP
t
WR
/WE (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
16
Data Sheet M13714EJ5V0DS
µPD441000L-X
Low VCC Data Retention Characteristics (TA = –25 to +85 °C)
Parameter
Symbol
Test Condition
µPD441000L
µPD441000L
µPD441000L
Unit
V
-BxxX
-CxxX
-DxxX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Data retention
supply voltage
VCCDR1 /CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V
2
3.6 1.5
3.6 1.5
3.6
VCCDR2 CE2 ≤ 0.2 V
2
3.6 1.5
3.6 1.5
3.6
Data retention
supply current
ICCDR1
VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V,
0.05 2 Note
0.05 2 Note
0.05 2 Note
0.05 2 Note
0.05 2 Note µA
CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V
ICCDR2
tCDR
VCC = 3.0 V, CE2 ≤ 0.2 V
0.05 2 Note
Chip deselection to
data retention mode
0
5
0
5
0
5
ns
Operation recovery
time
tR
ms
Note 0.5 µ
A ≤ 40 °C)
A (T
17
Data Sheet M13714EJ5V0DS
µPD441000L-X
Data Retention Timing Chart
(1) /CE1 Controlled
t
CDR
Data retention mode
t
R
★
V
CC
V
CC (MIN.)Note
/CE1
V
IH (MIN.)
VCCDR (MIN.)
/CE1 ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V.
The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
t
CDR
Data retention mode
t
R
V
CC
★
V
CC (MIN.)Note
V
IH (MIN.)
V
CCDR (MIN.)
CE2
V
IL (MAX.)
GND
CE2 ≤ 0.2 V
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
18
Data Sheet M13714EJ5V0DS
µPD441000L-X
Package Drawings
★
32-PIN PLASTIC SOP (13.34 mm (525))
32
17
detail of lead end
P
1
16
A
H
I
F
G
J
S
B
L
N
S
C
K
D
M
M
ITEM MILLIMETERS
E
A
B
C
20.61 MAX.
0.78 MAX.
1.27 (T.P.)
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.10
0.40
D
−0.05
E
F
G
H
I
0.15±0.05
2.95 MAX.
2.7
14.1±0.3
11.3
J
1.4±0.2
+0.10
0.20
K
−0.05
L
M
N
0.8±0.2
0.12
0.10
+7°
3°
P
−3°
P32GW-50-525A-1
19
Data Sheet M13714EJ5V0DS
µPD441000L-X
★
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
S
T
R
L
16
17
U
Q
P
I
J
A
G
S
H
B
C
M
K
N
S
D
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
1.0±0.05
12.4±0.2
11.8±0.1
0.8±0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4±0.2
0.1±0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6±0.15
P32GU-50-9JH-2
20
Data Sheet M13714EJ5V0DS
µPD441000L-X
★
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
U
L
Q
R
T
16
17
S
M
D
M
C
K
N
S
H
B
S
J
G
A
I
P
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
1.0±0.05
12.4±0.2
11.8±0.1
0.8±0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4±0.2
0.1±0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6±0.15
P32GU-50-9KH-2
21
Data Sheet M13714EJ5V0DS
µPD441000L-X
★
32-PIN PLASTIC TSOP(I) (8x20)
detail of lead end
1
32
F
G
R
Q
L
16
17
S
E
P
I
J
A
S
C
B
M
D
M
K
N
S
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
0.97±0.08
18.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
K
L
M
N
P
0.10
0.10
20.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S32GZ-50-KJH1-2
22
Data Sheet M13714EJ5V0DS
µPD441000L-X
★
32-PIN PLASTIC TSOP(I) (8x20)
detail of lead end
E
1
32
S
L
Q
R
G
16
17
F
M
M
D
K
N
S
C
B
S
I
J
A
P
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
0.97±0.08
18.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
K
L
M
N
P
0.10
0.10
20.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S32GZ-50-KKH1-2
23
Data Sheet M13714EJ5V0DS
µPD441000L-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD441000L-X.
★
Types of Surface Mount Device
µPD441000LGW-BxxX
: 32-pin Plastic SOP (13.34 mm (525))
µPD441000LGW-CxxX
: 32-pin Plastic SOP (13.34 mm (525))
µPD441000LGW-DxxX
: 32-pin Plastic SOP (13.34 mm (525))
µPD441000LGU-BxxX-9JH
µPD441000LGU-CxxX-9JH
µPD441000LGU-DxxX-9JH
µPD441000LGU-BxxX-9KH
µPD441000LGU-CxxX-9KH
µPD441000LGU-DxxX-9KH
µPD441000LGZ-BxxX-KJH
µPD441000LGZ-CxxX-KJH
µPD441000LGZ-DxxX-KJH
µPD441000LGZ-BxxX-KKH
µPD441000LGZ-CxxX-KKH
µPD441000LGZ-DxxX-KKH
: 32-pin Plastic TSOP (I) (8×13.4) (Normal bent)
: 32-pin Plastic TSOP (I) (8×13.4) (Normal bent)
: 32-pin Plastic TSOP (I) (8×13.4) (Normal bent)
: 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent)
: 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent)
: 32-pin Plastic TSOP (I) (8×13.4) (Reverse bent)
: 32-pin Plastic TSOP (I) (8×20) (Normal bent)
: 32-pin Plastic TSOP (I) (8×20) (Normal bent)
: 32-pin Plastic TSOP (I) (8×20) (Normal bent)
: 32-pin Plastic TSOP (I) (8×20) (Reverse bent)
: 32-pin Plastic TSOP (I) (8×20) (Reverse bent)
: 32-pin Plastic TSOP (I) (8×20) (Reverse bent)
24
Data Sheet M13714EJ5V0DS
µPD441000L-X
[ MEMO ]
25
Data Sheet M13714EJ5V0DS
µPD441000L-X
[ MEMO ]
26
Data Sheet M13714EJ5V0DS
µPD441000L-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
27
Data Sheet M13714EJ5V0DS
µPD441000L-X
•
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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