UPD4416001G5-A17-9JF [NEC]
16M-BIT CMOS FAST SRAM 16M-WORD BY 1-BIT; 16M - BIT的CMOS快速SRAM 16M - BY WORD 1位
| 型号： | UPD4416001G5-A17-9JF |
| 厂家： | 
NEC |
| 描述： | 16M-BIT CMOS FAST SRAM 16M-WORD BY 1-BIT |
| 文件： | 总12页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4416001
16M-BIT CMOS FAST SRAM
16M-WORD BY 1-BIT
Description
The µPD4416001 is a high speed, low power, 16,777,216 bits (16,777,216 words by 1 bits) CMOS static RAM.
Operating supply voltage is 3.3 V ± 0.3 V.
The µPD4416001 is packaged in a 54-PIN PLASTIC TSOP (II).
Features
• 16,777,216 words by 1 bits
• Fast access time : 15, 17 ns (MAX.)
• Output Enable input for easy application
Ordering Information
Part number
Package
Supply voltage
V
Access time
ns (MAX.)
15
Supply current mA (MAX.)
At operating
165
At standby
10
•
•
µPD4416001G5-A15-9JF
µPD4416001G5-A17-9JF
54-PIN PLASTIC TSOP (II)
(10.16 mm (400))
3.3 ± 0.3
17
160
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14077EJ3V0DS00 (3rd edition)
Date Published December 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.
1999
©
µ
PD4416001
Pin Configuration (Marking Side)
/xxx indicates active low signal.
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
[µPD4416001G5−xxx−9JF]
NC
VCC
NC
NC
GND
NC
A0
A1
A2
A3
A4
NC
GND
NC
NC
VCC
NC
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A23
A22
A21
A20
A19
A18
/OE
GND
IC
A17
A16
A15
A14
A13
A12
DOUT
GND
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A5
/CS
VCC
/WE
A6
A7
A8
A9
A10
A11
DIN
VCC
NC
NC
GND
NC
NC
VCC
NC
A0 - A23
: Address Inputs
: Data Input
IN
D
OUT
D
: Data Output
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
/CS
/WE
/OE
CC
V
GND
NC
IC
: No connection
: Internal connection Note
Note Leave this pin connect to GND.
Remark Refer to Package Drawing for 1-pin index mark.
2
Data Sheet M14077EJ3V0DS
µ
PD4416001
Block Diagram
VCC
GND
A0
Address
buffer
Row
decoder
Memory cell array
16,777,216 bits
A23
DIN
Input data
controller
Sense / Switch
Output data
controller
DOUT
Column decoder
Address buffer
/CS
/WE
/OE
Truth Table
/CS
/OE
×
/WE
×
Mode
I/O
High impedance
DOUT
Supply current
H
L
L
L
Not selected
Read
ISB
ICC
L
H
×
L
Write
DIN
H
H
Output disable
High impedance
Remark × : Don’t care
3
Data Sheet M14077EJ3V0DS
µ
PD4416001
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
V
–0.5 Note to +4.0
–0.5 Note to +4.0
0 to 70
•
•
Input / Output voltage
Operating ambient temperature
Storage temperature
V
TA
°C
°C
Tstg
–55 to +125
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
2.0
VCC + 0.3
+0.8
V
Low level input voltage
VIL
–0.3 Note
0
V
Operating ambient temperature
TA
70
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
Unit
VIN = 0 V to VCC
+2
+2
µA
µA
ILO
VOUT = 0 V to VCC,
–2
/CS = VIH or /OE = VIH or /WE = VIL
Operating supply current
Standby supply current
ICC
/CS = VIL, IOUT = 0 mA,
Minimum cycle time
Cycle time : 15 ns
Cycle time : 17 ns
165
160
80
mA
mA
•
•
ISB
/CS = VIH, VIN = VIH or VIL, Minimum cycle time
/CS ≥ VCC – 0.2 V,
ISB1
10
VIN ≤ 0.2 V or VCC – 0.2 V ≤ VIN
IOH = –4.0 mA
High level output voltage
Low level output voltage
VOH
VOL
2.4
V
V
IOL = +8.0 mA
0.4
IN
V
OUT
Remark
: Input voltage, V
: Output voltage
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Input capacitance
Test condition
MIN.
TYP.
MAX.
Unit
CIN
VIN = 0 V
6
8
pF
pF
Input / Output capacitance
COUT
VOUT = 0 V
IN
OUT
Remarks 1. V : Input voltage, V
: Output voltage
2. These parameters are periodically sampled and not 100% tested.
4
Data Sheet M14077EJ3V0DS
µ
PD4416001
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
LVTTL Interface
Input Waveform (Rise and Fall Time ≤ 3 ns)
3.0 V
1.5 V
Test Points
1.5 V
GND
Output Waveform
1.5 V
Test Points
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2.
Figure 1
Figure 2
AA ACS OE OH
CLZ OLZ CHZ OHZ WHZ OW
(for t , t , t , t
)
(for t , t , t , t , t
, t
)
V
TT = +1.5 V
+3.3 V
50 Ω
317 Ω
ZO = 50 Ω
DOUT (Output)
DOUT (Output)
351 Ω
30 pF
5 pF
C
L
C
L
L
Remark C includes capacitances of the probe and jig, and stray capacitances.
.
5
Data Sheet M14077EJ3V0DS
µ
PD4416001
Read Cycle
Parameter
Symbol
-A15
-A17
Unit
Notes
MIN.
15
MAX.
MIN.
17
MAX.
Read cycle time
tRC
tAA
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
15
15
7
17
17
8
1
/CS access time
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output hold in high impedance
tOH
3
3
0
3
3
0
tCLZ
tOLZ
tCHZ
tOHZ
2, 3
7
7
8
8
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ±200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
RC
Address (Input)
t
AA
t
OH
DOUT (Output)
Previous data output
Data output
Remarks 1. In read cycle, /WE should be fixed to high level.
IL
2. /CS = /OE = V
Read Cycle Timing Chart 2 (/CS Access)
t
RC
Address (Input)
/CS (Input)
t
AA
ACS
t
t
t
CLZ
t
CHZ
/OE (Input)
t
OHZ
t
OE
OLZ
High impedance
High impedance
DOUT (Output)
Data output
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
6
Data Sheet M14077EJ3V0DS
µ
PD4416001
Write Cycle
Parameter
Symbol
-A15
-A17
Unit
Notes
MIN.
15
10
10
10
7
MAX.
MIN.
17
11
11
11
8
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
Data valid to end of write
Data hold time
0
0
Address setup time
tAS
0
0
Write recovery time
tWR
tWHZ
tOW
1
1
/WE to output in high impedance
Output active from end of write
7
8
1, 2
3
3
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
/CS (Input)
t
CW
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
ACS
t
CLZ
t
DW
t
DH
DIN (Input)
Data in
t
OH
t
WHZ
t
OW
High impedance
DOUT (Output)
t
AA
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
•
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE.
WHZ
OUT
, D
2. During t
pins are in the output state, therefore the input signals of opposite phase to the
output must not be applied.
OUT
3. When /WE is at low level, the D
pins are always high impedance. When /WE is at high level, read
OUT
operation is executed. Therefore /OE should be at high level to make the D
pins high impedance.
7
Data Sheet M14077EJ3V0DS
µ
PD4416001
Write Cycle Timing Chart 2 (/CS Controlled)
tWC
Address (Input)
tAS
tCW
/CS (Input)
tAW
tWP
tWR
tDH
/WE (Input)
tDW
Data in
DIN (Input)
High impedance
DOUT (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
•
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
8
Data Sheet M14077EJ3V0DS
µ
PD4416001
Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54
28
detail of lead end
F
P
E
1
27
A
H
I
J
G
S
L
C
N
S
B
K
D
M
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
22.22±0.05
0.91 MAX.
0.80 (T.P.)
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
+0.08
0.32
D
−0.07
E
F
G
H
I
0.10±0.05
1.1±0.1
1.00
11.76±0.20
10.16±0.10
0.80±0.20
J
+0.025
0.145
K
−0.015
L
M
N
0.50±0.10
0.13
0.10
+7°
3°
P
−3°
S54G5-80-9JF-2
9
Data Sheet M14077EJ3V0DS
µ
PD4416001
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4416001.
Type of Surface Mount Device
µPD4416001 : 54-PIN PLASTIC TSOP (II) (10.16 mm (400))
10
Data Sheet M14077EJ3V0DS
µ
PD4416001
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
11
Data Sheet M14077EJ3V0DS
µ
PD4416001
•
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
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M8E 00. 4
相关型号：
UPD4416008G5-A15-9JF-A
Standard SRAM, 2MX8, 15ns, CMOS, PDSO54, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
NEC
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