UPD44164084 [NEC]
18M-BIT DDRII SRAM 4-WORD BURST OPERATION; 18M位DDRII SRAM 4字突发操作型号: | UPD44164084 |
厂家: | NEC |
描述: | 18M-BIT DDRII SRAM 4-WORD BURST OPERATION |
文件: | 总32页 (文件大小:391K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44164084, 44164184, 44164364
18M-BIT DDRII SRAM
4-WORD BURST OPERATION
Description
The µPD44164084 is a 2,097,152-word by 8-bit, the µPD44164184 is a 1,048,576-word by 18-bit and the
µPD44164364 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The µPD44164084, µPD44164184 and µPD44164364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply and HSTL I/O
• DLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Four-tick burst for reduced address frequency
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15822EJ7V1DS00 (7th edition)
Date Published July 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
µPD44164084, 44164184, 44164364
Ordering Information
Part number
Cycle
Time
ns
Clock
Frequency
MHz
Organization Core Supply
I/O
Package
(word x bit)
Voltage
V
Interface
µPD44164084F5-E40-EQ1
µPD44164084F5-E50-EQ1
µPD44164084F5-E60-EQ1
µPD44164184F5-E40-EQ1
µPD44164184F5-E50-EQ1
µPD44164184F5-E60-EQ1
µPD44164364F5-E50-EQ1
µPD44164364F5-E60-EQ1
4.0
5.0
6.0
4.0
5.0
6.0
5.0
6.0
250
200
167
250
200
167
200
167
2 M x 8-bit
1.8 ± 0.1
HSTL
165-pin PLASTIC
BGA (13 x 15)
1 M x 18-bit
512 K x 36-bit
Data Sheet M15822EJ7V1DS
2
µPD44164084, 44164184, 44164364
Pin Configurations
/××× indicates active low signal.
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44164084F5-EQ1]
1
2
3
A
4
5
/NW1
NC
A
6
7
NC
/NW0
A
8
9
A
10
VSS
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
VSS
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
R, /W
A
/K
/LD
A
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
G
H
J
NC
NC
DQ0
NC
NC
NC
TDI
K
L
M
N
P
R
VSS
VSS
A
A
C
A
A
A
A
/C
A
A
A
: Address inputs
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
DQ0 to DQ7
/LD
R, /W
/NW0, /NW1
K, /K
C, /C
CQ, /CQ
ZQ
/DLL
: Data inputs / outputs
: Synchronous load
: Read Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: No connection
Remark Refer to Package Drawing for the index mark.
Data Sheet M15822EJ7V1DS
3
µPD44164084, 44164184, 44164364
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44164184F5-EQ1]
1
2
VSS
3
4
5
/BW1
NC
A
6
7
NC
/BW0
A1
8
9
A
10
VSS
NC
11
CQ
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
A
R, /W
A
/K
/LD
A
DQ9
NC
NC
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
NC
NC
VSS
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
VSS
VSS
NC
NC
A
A
C
A
A
NC
DQ0
TDI
TCK
A
A
/C
A
A
TMS
A0, A1, A
DQ0 to DQ17
/LD
R, /W
/BW0, /BW1
K, /K
C, /C
CQ, /CQ
ZQ
: Address inputs
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: No connection
/DLL
Remark Refer to Package Drawing for the index mark.
Data Sheet M15822EJ7V1DS
4
µPD44164084, 44164184, 44164364
165-pin PLASTIC BGA (13 x 15)
(Top View)
[µPD44164364F5-EQ1]
1
2
3
4
5
/BW2
/BW3
A
6
7
/BW1
/BW0
A1
8
9
A
10
VSS
11
CQ
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
VSS
NC
R, /W
A
/K
/LD
A
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
DQ17
NC
DQ29
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
VSS
VSS
A
A
C
A
A
DQ9
TMS
TCK
A
A
/C
A
A
A0, A1, A
DQ0 to DQ35
/LD
R, /W
/BW0 to /BW3
K, /K
C, /C
CQ, /CQ
ZQ
: Address inputs
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: No connection
/DLL
Remark Refer to Package Drawing for the index mark.
Data Sheet M15822EJ7V1DS
5
µPD44164084, 44164184, 44164364
Pin Identification
Symbol
Description
A0
A1
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. Balls 3A, 10A, and 2A are reserved for the next higher-order address inputs on future devices.
All transactions operate on a burst of four words (two clock periods of bus activity). A0 and A1 are used as the
lowest two address bits for BURST READ and BURST WRITE operations permitting a random burst start
address on x18 and x36 devices. These inputs are ignored when device is deselected or once BURST
operation is in progress.
DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and /K. Output
data is synchronized to the respective C and /C data clocks or to K and /K if C and /C are tied to HIGH.
x8 device uses DQ0 to DQ7.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
/LD
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods of bus
activity).
R, /W
Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when R, /W is
HIGH, WRITE when R, /W is LOW) for the loaded address. R, /W must meet the setup and hold times around
the rising edge of K.
/BWx
/NWx
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
K, /K
C, /C
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous
inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
/C is used as the output timing reference for first and third output data. The rising edge of C is used as the
output reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C
may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and
/C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation.
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. This pin cannot be connected directly to GND or left unconnected. Also, in this product, there is no
function to minimize the output impedance by connecting ZQ directly to VDDQ.
CQ, /CQ
ZQ
/DLL
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
VREF
VDD
IEEE 1149.1 Test Output: 1.8V I/O level.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.
VSS
NC
Power Supply: Ground
No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
Data Sheet M15822EJ7V1DS
6
µPD44164084, 44164184, 44164364
Block Diagram
CLK
Burst
Logic
A1'
A1
D1
D0
Q1
Q0
A0
A0'
R
Address
Register
Address
/LD
/W
E
Compare
/C
C
A0''
A0'''
Output control
Logic
Write address
Register
K
E
E
A0'
Input
Register
/A0'
A0'
ZQ
0
2 :1
MUX
Memory
Array
CLK
/A0'
K
1
A0'
Output Buffer
E
DQ
0
1
/K
Input
Register
E
A0'''
Output Enable
Register
C
R, /W
R, /W
Register
E
Data Sheet M15822EJ7V1DS
7
µPD44164084, 44164184, 44164364
Burst Sequence
Linear Burst Sequence Table
[µPD44164184, µPD44164364]
A1, A0
0, 0
A1, A0
0, 1
A1, A0
1, 0
A1, A0
1, 1
External Address
1st Internal Burst Address
2nd Internal Burst Address
3rd Internal Burst Address
0, 1
1, 0
1, 1
0, 0
1, 0
1, 1
0, 0
0, 1
1, 1
0, 0
0, 1
1, 0
Truth Table
Operation
WRITE cycle
/LD R, /W
CLK
DQ
L
L
L → H
L → H
L → H
Data in
Data out
High-Z
Load address, input write data on two
consecutive K and /K rising edge
READ cycle
Input data
Input clock
D(A1)
D(A2)
D(A3)
D(A4)
K(t+1) ↑
/K(t+1) ↑
K(t+2) ↑
/K(t+2) ↑
L
H
Load address, read data on two
consecutive C and /C rising edge
NOP (No operation)
Output data
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Output clock /C(t+1) ↑
C(t+2) ↑ /C(t+2) ↑ C(t+3) ↑
H
X
X
X
STANDBY(Clock stopped)
Stopped Previous state
Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refer to the next internal
burst address in accordance with the linear burst sequence.
7. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
Data Sheet M15822EJ7V1DS
8
µPD44164084, 44164184, 44164364
Byte Write Operation
[µPD44164084]
Operation
K
L → H
–
/K
–
/NW0
/NW1
Write DQ0 to DQ7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
Write DQ0 to DQ3
Write DQ4 to DQ7
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remark H : High level, L : Low level, → : rising edge.
[µPD44164184]
Operation
K
L → H
–
/K
–
/BW0
/BW1
Write DQ0 to DQ17
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remark H : High level, L : Low level, → : rising edge.
[µPD44164364]
Operation
K
L → H
–
/K
–
/BW0
/BW1
/BW2
/BW3
Write DQ0 to DQ35
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
L → H
–
Write DQ0 to DQ8
Write DQ9 to DQ17
Write DQ18 to DQ26
Write DQ27 to DQ35
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remark H : High level, L : Low level, → : rising edge.
Data Sheet M15822EJ7V1DS
9
µPD44164084, 44164184, 44164364
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 4
Load, Count = 4
READ DOUBLE
Write
Read
WRITE DOUBLE
Count = Count + 2
Count = Count + 2
Always
Count = 2
Always
Count = 2
Load
NOP,
NOP,
Count = 4
Count = 4
ADVANCE ADDRESS
BY TWO
ADVANCE ADDRESS
BY TWO
NOP
NOP
Supply voltage provided
Power UP
Remarks 1. A0 and A1 are internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 4.
2. State transitions: L = (/LD = LOW); /L = (/LD = HIGH); R = (/R, W = HIGH); W = (/R, W = LOW).
3. State machine control timing sequence is controlled by K.
Data Sheet M15822EJ7V1DS
10
µPD44164084, 44164184, 44164364
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
Unit
V
VDD
VDDQ
VIN
+2.9
Output supply voltage
Input voltage
VDD
VDD + 0.5 (2.9 V MAX.)
VDDQ + 0.5 (2.9 V MAX.)
70
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
TA
V
°C
°C
Tstg
–55
+125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit
V
Note
Output supply voltage
High level input voltage
Low level input voltage
Clock input voltage
VDDQ
VIH (DC)
VIL (DC)
VIN
1.4
VDD
V
1
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.95
V
1, 2
1, 2
1, 2
V
–0.3
V
Reference voltage
VREF
0.68
V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter
High level input voltage
Low level input voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
VREF + 0.2
–
TYP.
MAX.
–
Unit
V
Note
1
1
VREF – 0.2
V
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Data Sheet M15822EJ7V1DS
11
µPD44164084, 44164184, 44164364
DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
x8, x18 x36
Input leakage current
I/O leakage current
Operating supply current
(Read Write cycle)
ILI
–2
–2
–
–
+2
+2
µA
µA
ILO
IDD
VIN ≤ VIL or VIN ≥ VIH, –E40
620
540
470
320
−
mA
II/O = 0 mA
–E50
–E60
620
570
–
Cycle = MAX.
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH, –E40
mA
II/O = 0 mA
–E50
–E60
270
250
Cycle = MAX.
High level output voltage
Low level output voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ – 0.2
VDDQ/2–0.12
VSS
–
–
–
–
VDDQ
VDDQ/2+0.12
0.2
V
V
V
V
3, 4
3, 4
3, 4
3, 4
VDDQ/2–0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Input capacitance
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
4
6
5
5
7
6
Input / Output capacitance
Clock Input capacitance
CI/O
VI/O = 0 V
Vclk = 0 V
pF
Cclk
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M15822EJ7V1DS
12
µPD44164084, 44164184, 44164364
AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V)
AC Test Conditions
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.25 V
0.75 V
Test Points
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
V
DDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
Data Sheet M15822EJ7V1DS
13
µPD44164084, 44164184, 44164364
Read and Write Cycle
-E40
-E50
-E60
Parameter
Symbol
Unit Note
(250 MHz)
(200 MHz)
(167 MHz)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time (K, /K, C, /C) TKHKH
ns
ns
ns
ns
ns
ns
ns
1
2
4.0
–
8.4
0.2
–
–
–
5.0
–
8.4
0.2
–
–
–
–
–
2.3
2.8
3.55
–
6.0
–
8.4
0.2
–
–
–
–
–
–
Clock phase jitter (K, /K, C, /C)
Clock HIGH time (K, /K, C, /C)
Clock LOW time (K, /K, C, /C)
Clock to /clock (K→/K., C→/C.)
Clock to /clock (/K→K., /C→C.)
TKC var
TKHKL
TKLKH
TKH /KH
T /KHKH
1.6
1.6
1.8
1.8
0
0
0
0
2.0
2.0
2.2
2.2
–
0
0
0
2.4
2.4
2.7
2.7
–
–
0
0
–
Clock to data clock 200 to 250 MHz TKHCH
1.8
2.3
2.8
3.55
–
(K→C., /K→/C.)
167 to 200 MHz
133 to 167 MHz
< 133 MHz
2.8
3.55
–
DLL lock time (K, C)
K static to DLL reset
TKC lock
TKC reset
Cycle
ns
3
1,024
30
1,024
30
1,024
30
–
–
–
Output Times
C, /C HIGH to output valid
C, /C HIGH to output hold
C, /C HIGH to echo clock valid
C, /C HIGH to echo clock hold
CQ, /CQ HIGH to output valid
CQ, /CQ HIGH to output hold
C HIGH to output High-Z
TCHQV
TCHQX
ns
ns
ns
ns
ns
ns
ns
ns
–
–0.45
–
–0.45
–
–0.3
–
–0.45
0.45
–
0.45
–
0.3
–
0.45
–
–
–0.45
–
–0.45
–
–0.35
–
–0.45
0.45
–
0.45
–
0.35
–
0.45
–
–
–0.5
–
–0.5
–
–0.4
–
–0.5
0.5
–
0.5
–
0.4
–
0.5
–
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
4
4
C HIGH to output Low-Z
TCHQX1
Setup Times
Address valid to K rising edge
Synchronous load input (/LD),
read write input (R, /W) valid to
K rising edge
TAVKH
TIVKH
ns
ns
5
5
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
Data inputs and write data select
inputs (/BWx, /NWx) valid to
K, /K rising edge
TDVKH
ns
5
0.35
–
0.4
–
0.5
–
Hold Times
K rising edge to address hold
K rising edge to
TKHAX
TKHIX
ns
ns
5
5
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
synchronous load input (/LD),
read write input (R, /W) hold
K, /K rising edge to data inputs and
write data select inputs (/BWx, /NWx)
hold
TKHDX
ns
5
0.35
–
0.4
–
0.5
–
Data Sheet M15822EJ7V1DS
14
µPD44164084, 44164184, 44164364
Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5. VDDQ is 1.5 V DC.
Data Sheet M15822EJ7V1DS
15
µPD44164084, 44164184, 44164364
Read and Write Timing
NOP
1
READ
(burst of 4)
READ
(burst of 4)
NOP
NOP
WRITE
(burst of 4)
WRITE
(burst of 4)
READ
(burst of 4)
2
3
4
5
6
7
8
9
10
11
12
13
TKHKH
K
TKHKL TKLKH
TKLKH
TKH/KH
T/KHKH
/K
/LD
TIVKH
TKHIX
R, /W
TAVKH
TKHAX
Address
DQ
A2
A1
A3
A4
A0
TKHDX
TKHDX
TDVKH
TDVKH
D21
D22
D23
D24
D31 D32
D33
D34
Q41
Q01 Q02 Q03
TCHQX
Q04
Q11
Q12
Q13
Q14
Qx2
TCQHQX
TCHQX
TCQHQV
TCHQX1
TCHQV
TKHCH
TKHCH
TCHQV
TCHQZ
CQ
TCHCQX
TCHCQV
/CQ
C
TCHCQX
TCHCQV
TKHKL TKLKH TKHKH TKH/KH T/KHKH
/C
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disable (high impedance) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
Data Sheet M15822EJ7V1DS
16
µPD44164084, 44164184, 44164364
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
2R
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test Mode Select. This is the command input for the TAP controller state machine.
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.
TDO
1R
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
ILI
Conditions
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
µA
Note
JTAG Input leakage current
JTAG I/O leakage current
0 V ≤ VIN ≤ VDD
–
–
ILO
0 V ≤ VIN ≤ VDDQ,
µA
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
VIH
VIL
1.3
–0.3
1.6
1.4
–
–
–
–
–
–
–
VDD + 0.3
V
V
V
V
V
V
+0.5
–
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 µA
| IOHT | = 2 mA
IOLC = 100 µA
IOLT = 2 mA
–
JTAG output low voltage
0.2
0.4
–
Data Sheet M15822EJ7V1DS
17
µPD44164084, 44164184, 44164364
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0 V
0.9 V
Test Points
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
Data Sheet M15822EJ7V1DS
18
µPD44164084, 44164184, 44164364
JTAG AC Characteristics (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
tTHTH
fTF
100
–
–
–
–
–
–
10
–
ns
MHz
ns
tTHTL
tTLTH
40
40
–
ns
Output time
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
tTLOX
tTLOV
tDVTH
tTHDX
0
–
–
–
–
–
–
20
–
ns
ns
ns
ns
10
10
–
Setup time
TMS setup time
Capture setup time
tMVTH
tCS
10
10
–
–
–
–
ns
ns
Hold time
TMS hold time
Capture hold time
tTHMX
tCH
10
10
–
–
–
–
ns
ns
JTAG Timing Diagram
t
THTH
TCK
TMS
TDI
t
MVTH
t
THTL
t
TLTH
t
THMX
t
DVTH
t
THDX
t
TLOV
t
TLOX
TDO
Data Sheet M15822EJ7V1DS
19
µPD44164084, 44164184, 44164364
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Bypass register
ID register
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
107
bit
Boundary register
bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 0001 0101
0000 0000 0001 0110
0000 0000 0001 0111
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
µPD44164084
µPD44164184
µPD44164364
2M x 8
1M x 18
XXXX
XXXX
XXXX
1
1
1
00000010000
512K x 36
00000010000
Data Sheet M15822EJ7V1DS
20
µPD44164084, 44164184, 44164364
SCAN Exit Order
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
no.
x8
x18 x36
no.
x8
x18
x36
no.
x8
x18
NC
x36
NC
1
2
/C
C
A
A
A
A
A
A
A
6R
6P
6N
7P
7N
7R
8R
8P
9R
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
NC
NC
NC
NC
10D
9E
73
74
NC
2C
3E
2D
2E
1E
2F
3F
1G
1F
DQ4 DQ11 DQ20
3
NC DQ7 DQ17 10C
75
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ29
NC
4
NC
NC
NC
NC DQ16 11D
76
5
NC
NC
NC
NC
9C
9D
77
NC
6
78
DQ12 DQ30
7
DQ3 DQ8 DQ8 11B
79
NC
NC
NC
DQ21
NC
8
NC
NC
NC
NC DQ7 11C
80
9
NC
NC
CQ
–
NC
NC
9B
10B
11A
Internal
9A
81
NC
10
11
12
13
14
15
16
17
NC DQ0 DQ0 11P
82
DQ5 DQ13 DQ22 3G
NC
NC
NC
NC DQ9 10P
83
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ31 2G
NC
NC
NC
NC
10N
9P
84
NC
NC
1J
2J
A
85
NC DQ1 DQ11 10M
A
8B
86
DQ14 DQ23
3K
3J
NC
NC
NC
NC DQ10 11N
A
A1
A0
/LD
A1
A0
7C
87
NC
NC
NC
DQ32
NC
NC
NC
NC
NC
9M
9N
NC
6C
88
2K
1K
2L
3L
1M
1L
3N
8A
89
NC
18 DQ0 DQ2 DQ2 11L
NC
NC /BW1 7A
90
DQ6 DQ15 DQ33
19
20
21
22
23
24
25
NC
NC
NC
NC DQ1 11M
55 /NW0 /BW0 /BW0 7B
91
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ24
NC
NC
NC
NC
NC
9L
56
57
58
K
6B
6A
92
10L
/K
93
NC
NC DQ3 DQ3 11K
NC
NC /BW3 5B
94
DQ16 DQ25
NC
NC
NC
NC DQ12 10K
59 /NW1 /BW1 /BW2 5A
95
NC
NC
NC
DQ34 3M
NC
NC
NC
NC
9J
60
61
62
63
64
65
66
67
68
69
70
71
72
R, /W
A
4A
5C
4B
3A
1H
1A
96
NC
NC
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
9K
97
26 DQ1 DQ4 DQ13 10J
A
98
DQ7 DQ17 DQ26
27
28
29
30
31
32
33
34
NC
NC DQ4 11J
A
A
NC
99
NC
NC
NC
NC
NC
NC
A
DQ35
NC
ZQ
NC
NC
11H
10G
9G
/DLL
/CQ
100
101
102
103
104
105
106
107
NC
NC
NC
NC
NC
NC DQ9 DQ27 2B
NC DQ5 DQ5 11F
NC
NC
NC
NC DQ18 3B
A
NC
NC
NC
NC DQ14 11G
NC
NC
NC
NC
1C
1B
A
NC
NC
NC
NC
9F
A
10F
NC DQ10 DQ19 3D
A
35 DQ2 DQ6 DQ6 11E
36 NC NC DQ15 10E
NC
NC
NC DQ28 3C
NC NC 1D
A
Data Sheet M15822EJ7V1DS
21
µPD44164084, 44164184, 44164364
JTAG Instructions
Instructions
EXTEST
Description
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output driver is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
BYPASS
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR
state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the RAM
clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the
I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing
the TAP to sample metastable input will not harm the device, repeatable results cannot be expected.
RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus
hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except
capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state
then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
1
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
1
1
0
1
1
1
Note 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
Data Sheet M15822EJ7V1DS
22
µPD44164084, 44164184, 44164364
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.
TDO should be left unconnected.
Data Sheet M15822EJ7V1DS
23
Test Logic Operation (Instruction Scan)
TCK
TMS
Controller
state
TDI
Instruction
Register state
IDCODE
New Instruction
Output Inactive
TDO
Test Logic (Data Scan)
TCK
TMS
Controller
state
TDI
Instruction
Register state
Instruction
IDCODE
Output Inactive
TDO
µPD44164084, 44164184, 44164364
Package Drawing
165-PIN PLASTIC BGA (13x15)
B
E
w S
B
ZD
ZE
11
10
9
8
A
7
6
D
5
4
3
2
1
R P M M L K J H G F E D C B A
w
S A
INDEX MARK
A
A2
A1
y1
S
S
y
e
S
(UNIT:mm)
ITEM DIMENSIONS
M
φ
φ
x
b
S A B
D
E
13.00 0.10
15.00 0.10
0.15
w
e
1.00
A
1.40 0.11
0.40 0.05
1.00
A1
A2
b
0.50 0.05
0.08
x
y
0.10
y1
ZD
ZE
0.20
1.50
0.50
P165F5-100-EQ1
Data Sheet M15822EJ7V1DS
26
µPD44164084, 44164184, 44164364
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
µPD44164084F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
µPD44164184F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
µPD44164364F5-EQ1: 165-pin PLASTIC BGA (13 x 15)
Data Sheet M15822EJ7V1DS
27
µPD44164084, 44164184, 44164364
Revision History
Edition/
Page
Previous
edition
7th edition/ Throughout Throughout
Feb. 2004 p.12 p.12
Type of
revision
Location
Description
Date
This
edition
(Previous edition → This edition)
Deletion
Ordering Information
µPD44164364F5-E40-EQ1
Modification DC Characteristics IDD (MAX.)
MAX.
x8, x18
Unit
MAX.
x8, x18
Unit
mA
x36
TBD
530
480
x36
−
-E40
-E50
-E60
560
480
410
mA
-E40
-E50
-E60
620
540
470
620
570
DC Characteristics ISB1 (MAX.)
MAX.
x8, x18
Unit
MAX.
Unit
mA
x36
x8, x18
320
x36
-E40
-E50
-E60
250
210
190
mA
-E40
-E50
-E60
−
270
250
p.26
p.26
Modification Package Drawing
Preliminary version → Standardized version
Data Sheet M15822EJ7V1DS
28
µPD44164084, 44164184, 44164364
[MEMO]
Data Sheet M15822EJ7V1DS
29
µPD44164084, 44164184, 44164364
[MEMO]
Data Sheet M15822EJ7V1DS
30
µPD44164084, 44164184, 44164364
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
Data Sheet M15822EJ7V1DS
31
µPD44164084, 44164184, 44164364
•
The information in this document is current as of July, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号:
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DDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
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