UPD442000AGU-DD85X-9KH [NEC]
2M-BIT CMOS STATIC RAM 256K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION; 2M- BIT的CMOS静态RAM 256K - WORD 8位的扩展工作温度
| 型号： | UPD442000AGU-DD85X-9KH |
| 厂家： | 
NEC |
| 描述： | 2M-BIT CMOS STATIC RAM 256K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总28页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD442000A-X
2M-BIT CMOS STATIC RAM
256K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD442000A-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) CMOS static RAM.
The µPD442000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available.
The µPD442000A-X is packed in 32-pin PLASTIC TSOP (I) (Normal bent) and 32-pin PLASTIC TSOP (I) (Reverse
bent).
Features
• 262,144 words by 8 bits organization
• Fast access time : 55, 70, 85, 100, 120 ns (MAX.)
• Low voltage operation : VCC = 2.7 to 3.6 V (-BB55X, -BB70X, -BB85X)
VCC = 2.2 to 3.6 V (-BC70X, -BC85X, -BC10X)
VCC = 1.8 to 2.2 V (-DD85X, -DD10X, -DD12X)
• Low VCC data retention : 1.0 V (MIN.)
• Operating ambient temperature : TA = –25 to +85 °C
• Output Enable input for easy application
• Two Chip Enable inputs : /CE1, CE2
µPD442000A
Access time Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
V
temperature
°C
At operating
mA (MAX.)
30 Note
30
At standby At data retention
µA (MAX.)
µA (MAX.)
-BB55X, -BB70X, -BB85X
-BC70X, -BC85X, -BC10X
-DD85X, -DD10X, -DD12X
55, 70, 85
70, 85, 100
85, 100, 120
2.7 to 3.6
2.2 to 3.6
1.8 to 2.2
−25 to +85
2
1
15
1.5
Note Cycle time ≥ 70 ns, -BB55X : 35 mA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14669EJ7V0DS00 (7th edition)
Date Published October 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2000
©
µPD442000A-X
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating
supply voltage
V
Operating
temperature
°C
µPD442000AGU-BB55X-9JH
µPD442000AGU-BB70X-9JH
µPD442000AGU-BB85X-9JH
µPD442000AGU-BC70X-9JH
µPD442000AGU-BC85X-9JH
µPD442000AGU-BC10X-9JH
µPD442000AGU-DD85X-9JH
µPD442000AGU-DD10X-9JH
µPD442000AGU-DD12X-9JH
µPD442000AGU-BB55X-9KH
µPD442000AGU-BB70X-9KH
µPD442000AGU-BB85X-9KH
µPD442000AGU-BC70X-9KH
µPD442000AGU-BC85X-9KH
µPD442000AGU-BC10X-9KH
µPD442000AGU-DD85X-9KH
µPD442000AGU-DD10X-9KH
µPD442000AGU-DD12X-9KH
32-pin PLASTIC TSOP (I)
55
70
2.7 to 3.6
2.2 to 3.6
1.8 to 2.2
2.7 to 3.6
2.2 to 3.6
1.8 to 2.2
−25 to +85
(8×13.4) (Normal bent)
85
70
85
100
85
100
120
55
32-pin PLASTIC TSOP (I)
(8×13.4) (Reverse bent)
70
85
70
85
100
85
100
120
2
Data Sheet M14669EJ7V0DS
µPD442000A-X
Pin Configurations
/xxx indicates active low signal.
32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
[ µPD442000AGU-9JH ]
Marking Side
A11
A9
A8
A13
/WE
CE2
A15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
9
10
11
12
13
14
15
16
A1
A2
A3
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
: Write Enable
: Output Enable
: Power supply
: Ground
GND
Remark Refer to Package Drawings for the 1-pin index mark.
3
Data Sheet M14669EJ7V0DS
µPD442000A-X
32-pin PLASTIC TSOP (I) (8×13.4) (Reverse bent)
[ µPD442000AGU-9KH ]
Marking Side
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
/WE
CE2
A15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
A1
A2
A3
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs
/CE1, CE2 : Chip Enable 1, 2
/WE
/OE
VCC
: Write Enable
: Output Enable
: Power supply
: Ground
GND
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M14669EJ7V0DS
µPD442000A-X
Block Diagram
VCC
GND
A0
A17
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
Sense amplifier /
Switching circuit
I/O1
Input data
controller
Output data
controller
I/O8
Column decoder
Address buffer
/CE1
CE2
/OE
/WE
Truth Table
/CE1
CE2
×
/OE
×
/WE
Mode
I/O
Supply current
ISB
H
×
L
L
L
×
×
Not selected
Not selected
Output disable
Read
High-Z
High-Z
High-Z
DOUT
L
×
H
H
L
H
H
L
ICCA
H
H
×
Write
DIN
Remark × : VIH or VIL
5
Data Sheet M14669EJ7V0DS
µPD442000A-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Condition
Rating
Unit
-BB55X, -BB70X, -BB85X
-BC70X, -BC85X, -BC10X
-DD85X, -DD10X, -DD12X
Supply voltage
VCC
VT
–0.5 Note to +4.0
–0.5 Note to +2.7
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
–0.5 Note to VCC+0.4 (4.0 V MAX.) –0.5 Note to VCC+0.4 (2.7 V MAX.)
TA
–25 to +85
–25 to +85
°C
°C
Tstg
–55 to +125
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
-BB55X,-BB70X,-BB85X -BC70X,-BC85X,-BC10X-DD85X,-DD10X,-DD12X Unit
MIN.
2.7
MAX.
3.6
MIN.
2.2
MAX.
3.6
MIN.
1.8
MAX.
2.2
Supply voltage
VCC
VIH
V
V
High level input voltage
2.7 V ≤ VCC ≤ 3.6 V
2.2 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.2 V
2.4
VCC+0.4
–
2.4
VCC+0.4
VCC+0.3
–
–
–
–
2.0
–
–
–
–
–
1.6
VCC+0.2
+0.2
+85
Low level input voltage
Operating ambient
temperature
VIL
TA
–0.3 Note
+0.5
+85
–0.3 Note
+0.4
–0.2 Note
V
–25
–25
+85
–25
°C
Note –1.0 V (MIN.) (Pulse width : 20 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Input / Output capacitance
Symbol
CIN
Test condition
MIN.
TYP.
MAX.
8
Unit
pF
VIN = 0 V
VI/O = 0 V
CI/O
10
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are not 100% tested.
6
Data Sheet M14669EJ7V0DS
µPD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
-BB55X, -BB70X, -BB85X
Unit
MIN.
–1.0
–1.0
TYP.
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /CE1 = VIH or
CE2 = VIL or /WE = VIL or /OE = VIH
Operating supply current
ICCA1
/CE1 = VIL, CE2 = VIH,
Minimum cycle time,
II/O = 0 mA
Cycle time = 55 ns
Cycle time ≥ 70 ns
–
–
35
30
mA
ICCA2
/CE1 = VIL, CE2 = VIH,
Cycle time = ∞, II/O = 0 mA
–
–
4
4
ICCA3
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
Cycle time = 1 µs, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
/CE1 = VIH or CE2 = VIL
/CE1 ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V
CE2 ≤ 0.2 V
Standby supply current
ISB
ISB1
ISB2
VOH
VOL
–
0.35
2
mA
0.1
0.1
µA
2
High level output voltage
Low level output voltage
IOH = –0.5 mA
2.4
V
V
IOL = 1.0 mA
0.4
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
7
Data Sheet M14669EJ7V0DS
µPD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
-BC70X, -BC85X, -BC10X -DD85X, -DD10X, -DD12X Unit
MIN. TYP. MAX. MIN.
TYP. MAX.
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0
+1.0
–1.0
–1.0
µA
µA
ILO
VI/O = 0 V to VCC, /CE1 = VIH or
CE2 = VIL or /WE = VIL or /OE = VIH
/CE1 = VIL, CE2 = VIH,
+1.0
Operating supply current
ICCA1
ICCA2
ICCA3
–
–
–
–
–
–
–
30
25
–
–
–
–
–
–
–
–
–
–
mA
Minimum cycle time,
II/O = 0 mA
VCC ≤ 2.7 V
VCC ≤ 2.2 V
15
–
/CE1 = VIL, CE2 = VIH,
4
VCC ≤ 2.7 V
VCC ≤ 2.2 V
2
–
Cycle time = ∞,
II/O = 0 mA
–
1
/CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V,
Cycle time = 1 µs, II/O = 0 mA,
4
–
VIL ≤ 0.2 V,
VCC ≤ 2.7 V
–
–
3
–
–
–
–
3
VIH ≥ VCC – 0.2 V
/CE1 = VIH or CE2 = VIL
VCC ≤ 2.2 V
Standby supply current
ISB
ISB1
ISB2
VOH
VOL
–
0.35
0.35
–
–
–
mA
VCC ≤ 2.7 V
VCC ≤ 2.2 V
–
–
–
–
–
0.35
–
/CE1 ≥ VCC – 0.2 V,
CE2 ≥ VCC – 0.2 V
0.1
0.08
–
2
–
µA
VCC ≤ 2.7 V
VCC ≤ 2.2 V
2
–
–
–
0.05
–
1.5
–
CE2 ≤ 0.2 V
IOH = –0.5 mA
IOL = 1.0 mA
0.1
0.08
–
2
VCC ≤ 2.7 V
VCC ≤ 2.2 V
2
–
–
–
0.05
1.5
High level output voltage
Low level output voltage
2.4
1.8
–
–
–
V
V
VCC ≤ 2.7 V
VCC ≤ 2.2 V
1.5
0.4
0.4
–
–
–
VCC ≤ 2.7 V
VCC ≤ 2.2 V
0.4
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
8
Data Sheet M14669EJ7V0DS
µPD442000A-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 5 ns)
0.9VCC
V
CC/2
Test points
Test points
V
V
CC/2
0.1VCC
Output Waveform
VCC/2
CC/2
Output Load
[ -BB55X, -BB70X, -BB85X ]
1TTL + 50 pF
[ -BC70X, -BC85X, -BC10X, -DD85X, -DD10X, -DD12X ]
1TTL + 30 pF
9
Data Sheet M14669EJ7V0DS
µPD442000A-X
Read Cycle (1/3)
Parameter
Symbol
VCC ≥ 2.7 V
Unit Condition
-BB55X
-BB70X
-BB85X
MIN. MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
tRC
tAA
55
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
/CE1 access time
55
55
55
30
70
70
70
35
85
85
85
40
Note 1
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in Low-Z
CE2 to output in Low-Z
/OE to output in Low-Z
/CE1 to output in High-Z
CE2 to output in High-Z
/OE to output in High-Z
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
20
20
20
25
25
25
30
30
30
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Read Cycle (2/3)
Parameter
Symbol
VCC ≥ 2.2 V
Unit Condition
-BC70X
-BC85X
-BC10X
MIN.
70
MAX.
MIN.
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
85
ns
Address access time
/CE1 access time
70
70
70
35
85
85
85
40
100
100
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in Low-Z
CE2 to output in Low-Z
/OE to output in Low-Z
/CE1 to output in High-Z
CE2 to output in High-Z
/OE to output in High-Z
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
25
25
25
30
30
30
35
35
35
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
10
Data Sheet M14669EJ7V0DS
µPD442000A-X
Read Cycle (3/3)
Parameter
Symbol
VCC ≥ 1.8 V
Unit
Condition
-DD85X
-DD10X
-DD12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
tRC
tAA
85
100
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
/CE1 access time
85
85
85
40
100
100
100
50
120
120
120
60
Note 1
tCO1
tCO2
tOE
CE2 access time
/OE to output valid
Output hold from address change
/CE1 to output in Low-Z
CE2 to output in Low-Z
/OE to output in Low-Z
/CE1 to output in High-Z
CE2 to output in High-Z
/OE to output in High-Z
tOH
10
10
10
5
10
10
10
5
10
10
10
5
tLZ1
tLZ2
tOLZ
tHZ1
tHZ2
tOHZ
Note 2
30
30
30
35
35
35
40
40
40
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
11
Data Sheet M14669EJ7V0DS
µPD442000A-X
Read Cycle Timing Chart
tRC
Address (Input)
/CE1 (Input)
tAA
tOH
tCO1
tHZ1
tLZ1
CE2 (Input)
/OE (Input)
t
CO2
tHZ2
t
LZ2
tOE
tOHZ
tOLZ
High-Z
I/O (Output)
Data out
Remark In read cycle, /WE should be fixed to high level.
12
Data Sheet M14669EJ7V0DS
µPD442000A-X
Write Cycle (1/3)
Parameter
Symbol
VCC ≥ 2.7 V
Unit Condition
-BB55X
MIN. MAX.
-BB70X
-BB85X
MIN. MAX.
MIN.
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
55
50
50
50
0
70
55
55
55
0
85
70
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
Write pulse width
tAS
tWP
tWR
tDW
tDH
45
0
50
0
55
0
Write recovery time
Data valid to end of write
Data hold time
25
0
30
0
35
0
/WE to output in High-Z
Output active from end of write
tWHZ
tOW
20
25
30
Note
5
5
5
Note The output load is 1TTL + 5 pF.
Write Cycle (2/3)
Parameter
Symbol
VCC ≥ 2.2 V
Unit Condition
-BC70X
MAX.
-BC85X
-BC10X
MIN.
70
55
55
55
0
MIN.
MAX.
MIN.
100
80
80
80
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
85
70
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
tAS
Write pulse width
tWP
tWR
tDW
tDH
50
0
55
0
60
0
Write recovery time
Data valid to end of write
Data hold time
30
0
35
0
40
0
/WE to output in High-Z
Output active from end of write
tWHZ
tOW
25
30
35
ns
ns
Note
5
5
5
Note The output load is 1TTL + 5 pF.
13
Data Sheet M14669EJ7V0DS
µPD442000A-X
Write Cycle (3/3)
Parameter
Symbol
VCC ≥ 1.8 V
Unit
Condition
-DD85X
MIN. MAX.
-DD10X
-DD12X
MIN. MAX.
MIN.
MAX.
Write cycle time
tWC
tCW1
tCW2
tAW
85
70
70
70
0
100
80
80
80
0
120
100
100
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1 to end of write
CE2 to end of write
Address valid to end of write
Address setup time
Write pulse width
tAS
tWP
tWR
tDW
tDH
55
0
60
0
85
0
Write recovery time
Data valid to end of write
Data hold time
35
0
40
0
60
0
/WE to output in High-Z
Output active from end of write
tWHZ
tOW
30
35
40
Note
5
5
5
Note The output load is 1TTL + 5 pF.
14
Data Sheet M14669EJ7V0DS
µPD442000A-X
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
Address (Input)
tCW1
/CE1 (Input)
CE2 (Input)
tCW2
tAW
tAS
tWP
tWR
/WE (Input)
tOW
tWHZ
tDW
tDH
High-Z
High-Z
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
15
Data Sheet M14669EJ7V0DS
µPD442000A-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
Address (Input)
t
AS
t
CW1
/CE1 (Input)
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
I/O (Input)
t
DW
t
DH
High-Z
High-Z
Data in
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
16
Data Sheet M14669EJ7V0DS
µPD442000A-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
Address (Input)
/CE1 (Input)
t
CW1
t
AS
t
CW2
CE2 (Input)
t
AW
t
WP
t
WR
/WE (Input)
I/O (Input)
t
DW
t
DH
High-Z
High-Z
Data in
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
17
Data Sheet M14669EJ7V0DS
µPD442000A-X
Low VCC Data Retention Characteristics (TA = –25 to +85 °C)
Parameter
Symbol
Test Condition
Unit
-BB55X,-BB70X, -BB85X -BC70X,-BC85X, -BC10X-DD85X,-DD10X, -DD12X
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Data retention
supply voltage
VCCDR1 /CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V
1.0
3.6
1.0
3.6
1.0
2.2
V
VCCDR2 CE2 ≤ 0.2 V
1.0
3.6
1
1.0
3.6
1
1.0
2.2
1
Data retention
supply current
ICCDR1 VCC = 1.2 V, /CE1 ≥ VCC − 0.2 V,
CE2 ≥ VCC − 0.2 V
0.05
0.05
0.05
0.05
0.05
0.05
µA
ns
ns
ICCDR2 VCC = 1.2 V, CE2 ≤ 0.2 V
tCDR
1
1
1
Chip deselection
to data retention
mode
0
0
0
Note
Note
Note
Operation
tR
tRC
tRC
tRC
recovery time
Note tRC : Read cycle time
18
Data Sheet M14669EJ7V0DS
µPD442000A-X
Data Retention Timing Chart
(1) /CE1 Controlled
t
CDR
Data retention mode
t
R
V
CC
V
CC (MIN.)Note
/CE1
V
IH (MIN.)
VCCDR (MIN.)
/CE1 ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X)
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be ≥ VCC − 0.2 V or ≤ 0.2 V.
The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
t
CDR
Data retention mode
t
R
V
CC
V
CC (MIN.)Note
V
IH (MIN.)
V
CCDR (MIN.)
CE2
VIL (MAX.)
CE2 ≤ 0.2 V
GND
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X)
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
19
Data Sheet M14669EJ7V0DS
µPD442000A-X
Package Drawings
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
S
T
R
L
16
17
U
Q
P
I
J
A
G
S
H
B
C
M
K
N
S
D
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
1.0±0.05
12.4±0.2
11.8±0.1
0.8±0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4±0.2
0.1±0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6±0.15
P32GU-50-9JH-2
20
Data Sheet M14669EJ7V0DS
µPD442000A-X
32-PIN PLASTIC TSOP(I) (8x13.4)
detail of lead end
1
32
U
L
Q
R
T
16
17
S
M
D
M
C
K
N
S
H
B
S
J
G
A
I
P
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
G
H
I
8.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
1.0±0.05
12.4±0.2
11.8±0.1
0.8±0.2
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
J
+0.025
K
0.145
−0.015
L
M
N
P
0.5
0.08
0.08
13.4±0.2
0.1±0.05
Q
+5°
3°
R
−3°
S
T
U
1.2 MAX.
0.25
0.6±0.15
P32GU-50-9KH-2
21
Data Sheet M14669EJ7V0DS
µPD442000A-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD442000A-X.
Types of Surface Mount Device
µPD442000AGU-9JH : 32-pin PLASTIC TSOP (I) (8×13.4) (Normal bent)
µPD442000AGU-9KH : 32-pin PLASTIC TSOP (I) (8×13.4) (Reverse bent)
22
Data Sheet M14669EJ7V0DS
µPD442000A-X
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
6th edition/ pp.6, 7
Jul. 2002
pp.6, 7
Modification DC Characteristics
-BB55X,-BB70X,-BB85X(MAX.) : ISB = 0.6mA → 0.35mA
-BC70X,-BC85X,-BC10X(MAX.) : ISB = 0.6mA → 0.35mA
-BC70X,-BC85X,-BC10X(MAX.) :
ISB(VCC ≥ 2.7 V) = 0.6mA → 0.35mA
-DD85X,-DD10X,-DD12X(MAX.) : ISB = 0.6mA → 0.35mA
Integration of Input Waveform and Output Waveform
p.8
p.8
Modification AC Characteristics
7th edition/ pp.2, 4, 21-22 pp.2, 3, 19-20 Addition
Oct. 2002
Ordering Information,
Pin Configurations,
Package Drawings,
Recommended
32-pin PLASTIC TSOP (I) (8×13.4) (Reverse bent)
µPD442000AGU-***-9KH
*** : Speed grades
BB55X, BB70X, BB85X, BC70X, BC85X, BC10X,
Soldering Conditions DD85X, DD10X, DD12X
23
Data Sheet M14669EJ7V0DS
µPD442000A-X
[ MEMO ]
24
Data Sheet M14669EJ7V0DS
µPD442000A-X
[ MEMO ]
25
Data Sheet M14669EJ7V0DS
µPD442000A-X
[ MEMO ]
26
Data Sheet M14669EJ7V0DS
µPD442000A-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
27
Data Sheet M14669EJ7V0DS
µPD442000A-X
•
The information in this document is current as of October, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
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Customers must check the quality grade of each semiconductor product before using it in a particular
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD442000AGU-DD85X-9KH-A
Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, PLASTIC, TSOP1-32
NEC
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