UPD44322162GF-A44 [NEC]
Cache SRAM, 2MX16, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100;
| 型号： | UPD44322162GF-A44 |
| 厂家： | 
NEC |
| 描述： | Cache SRAM, 2MX16, 2.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100 静态存储器 |
| 文件： | 总40页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µ
PD44322162, 44322182, 44322322, 44322362
32M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Description
The µPD44322162 is a 2,097,152-word by 16-bit, the µPD44322182 is a 2,097,152-word by 18-bit, µPD44322322 is a
1,048,576-word by 32-bit and the µPD44322362 is a 1,048,576-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The µPD44322162, µPD44322182, µPD44322322 and µPD44322362 integrates unique synchronous peripheral
circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of
the single clock input (CLK).
The µPD44322162, µPD44322182, µPD44322322 and µPD44322362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD44322162, µPD44322182, µPD44322322 and µPD44322362 are packaged in 100-pin PLASTIC LQFP with a
1.4 mm package thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.
Features
• 3.3 V or 2.5 V core supply
• Synchronous operation
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• Single-Cycle deselect timing
• All registers triggered off positive clock edge
• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD44322322, µPD44322362)
/BW1 to /BW2, /BWE (µPD44322162, µPD44322182)
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M16355EJ1V0PM00 (1st edition)
Date Published September 2002 NS CP(K)
Printed in Japan
2002
©
µPD44322162, 44322182, 44322322, 44322362
Ordering Information
(1/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Package
µPD44322162GF-A44
µPD44322162GF-A50
µPD44322162GF-A60
µPD44322182GF-A44
µPD44322182GF-A50
µPD44322182GF-A60
µPD44322322GF-A44
µPD44322322GF-A50
µPD44322322GF-A60
µPD44322362GF-A44
µPD44322362GF-A50
µPD44322362GF-A60
µPD44322162GF-C50
µPD44322162GF-C60
µPD44322182GF-C50
µPD44322182GF-C60
µPD44322322GF-C50
µPD44322322GF-C60
µPD44322362GF-C50
µPD44322362GF-C60
µPD44322162F1-A44-FQ2
µPD44322162F1-A50-FQ2
µPD44322162F1-A60-FQ2
µPD44322182F1-A44-FQ2
µPD44322182F1-A50-FQ2
µPD44322182F1-A60-FQ2
µPD44322322F1-A44-FQ2
µPD44322322F1-A50-FQ2
µPD44322322F1-A60-FQ2
µPD44322362F1-A44-FQ2
µPD44322362F1-A50-FQ2
µPD44322362F1-A60-FQ2
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
225
200
167
225
200
167
225
200
167
225
200
167
200
167
200
167
200
167
200
167
225
200
167
225
200
167
225
200
167
225
200
167
3.3 ± 0.165
3.3 V or 2.5 V LVTTL 100-pin PLASTIC LQFP (14 × 20)
2.5 ± 0.125
2.5 V LVTTL
3.3 ± 0.165
3.3 V or 2.5 V LVTTL 165-pin PLASTIC FBGA (15 x 17)
Preliminary Product Information M16355EJ1V0PM
2
µPD44322162, 44322182, 44322322, 44322362
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
2.5 V LVTTL
Package
µPD44322162F1-C50-FQ2
µPD44322162F1-C60-FQ2
µPD44322182F1-C50-FQ2
µPD44322182F1-C60-FQ2
µPD44322322F1-C50-FQ2
µPD44322322F1-C60-FQ2
µPD44322362F1-C50-FQ2
µPD44322362F1-C60-FQ2
3.1
3.5
3.1
3.5
3.1
3.5
3.1
3.5
200
167
200
167
200
167
200
167
2.5 ± 0.125
165-pin PLASTIC FBGA (15 x 17)
Preliminary Product Information M16355EJ1V0PM
3
µPD44322162, 44322182, 44322322, 44322362
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[µPD44322162GF, µPD44322182GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
NC
NC
2
3
V
DDQ
4
V
V
DD
Q
V
SS
Q
5
SS
Q
NC
NC
6
NC
7
I/OP1, NC
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
Q
V
DD
VDDQ
I/O11
I/O12
NC
I/O6
I/O5
V
SS
V
DD
NC
NC
V
DD
V
SS
I/O13
I/O14
ZZ
I/O4
I/O3
V
DD
Q
Q
V
V
DD
Q
V
SS
SS
Q
I/O15
I/O16
I/O2
I/O1
NC
I/OP2, NC
NC
NC
V
SS
Q
Q
VSS
Q
V
DD
VDDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
Preliminary Product Information M16355EJ1V0PM
4
µPD44322162, 44322182, 44322322, 44322362
Pin Identifications
[µPD44322162GF, µPD44322182GF]
Symbol
Pin No.
Description
A0 to A20
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, Synchronous Address Input
49, 50, 43, 42, 39, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23
Synchronous Data In,
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1, NCNote
I/OP2, NCNote
/ADV
74
24
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
83
/AP
84
/AC
85
/CE,CE2, /CE2
98, 97, 92
/BW1, /BW2, /BWE 93, 94, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 51, 52, 53, 56, 57, No Connection
66, 75, 78, 79, 95, 96
Note NC (No Connection) is used in the µPD44322162GF.
I/OP1, I/OP2 are used in the µPD44322182GF.
Preliminary Product Information M16355EJ1V0PM
5
µPD44322162, 44322182, 44322322, 44322362
100-pin PLASTIC LQFP (14 x 20)
[µPD44322322GF, µPD44322362GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2, NC
I/O16
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
I/O15
I/O18
3
V
V
DD
Q
V
DD
Q
Q
4
SSQ
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
V
V
SS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DD
Q
V
DD
I/O10
I/O9
I/O23
I/O24
NC
V
SS
NC
V
DD
V
DD
NC
ZZ
V
SS
I/O25
I/O26
I/O8
I/O7
V
V
DD
Q
V
DD
Q
Q
SSQ
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
V
V
SS
Q
V
SS
Q
Q
DD
Q
V
DD
I/O2
I/O31
I/O32
I/O1
I/OP1, NC
I/OP4, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for the 1-pin index mark.
Preliminary Product Information M16355EJ1V0PM
6
µPD44322162, 44322182, 44322322, 44322362
[µPD44322322GF, µPD44322362GF]
Symbol
Pin No.
Description
Synchronous Address Input
A0 to A19
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43, 42, 39
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, Synchronous Data In,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23,
24, 25, 28, 29
Synchronous / Asynchronous Data Out
I/OP1, NCNote
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
/ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
83
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/AP
84
/AC
85
/CE, CE2, /CE2
98, 97, 92
/BWE1 to /BWE4, /BWE 93, 94, 95, 96, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 66
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD44322322GF.
I/OP1 to I/OP4 are used in the µPD44322362GF.
Preliminary Product Information M16355EJ1V0PM
7
µPD44322162, 44322182, 44322322, 44322362
165-pin PLASTIC FBGA (15 x 17)
(Top View)
[µPD44322162F1, µPD44322182F1]
1
NC
2
A7
3
4
/BW2
NC
5
NC
6
7
/BWE
/GW
VSS
8
9
10
A9
11
A20
NC
A
B
C
D
E
F
/CE
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A19
A1
/AC
/G
/ADV
/AP
NC
A6
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A8
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A12
A2
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A17
A10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
A14
A15
I/OP1, NC
I/O8
I/O7
I/O6
I/O5
ZZ
NC
I/O9
I/O10
I/O11
I/O12
VSS
NC
VSS
NC
VSS
NC
VSS
G
H
J
NC
VSS
NC
VSS
I/O13
I/O14
I/O15
I/O16
I/OP2, NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A4
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
NC
K
L
NC
VSS
NC
NC
VSS
NC
M
N
P
R
NC
VSS
NC
NC
VSS
NC
NC
TDI
TMS
TDO
TCK
A18
A16
MODE
A5
A3
A0
A11
Remark Refer to Package Drawings for the index mark.
Preliminary Product Information M16355EJ1V0PM
8
µPD44322162, 44322182, 44322322, 44322362
[µPD44322162F1, µPD44322182F1]
Symbol
Pin No.
Description
6R, 6P, 4R, 3R, 3P, 2R, 2B, 2A, 10B, 10A, 8R, 9R, 4P,
A0 to A20
Synchronous Address Input
9P, 10P, 10R, 11R, 8P, 11P, 6N, 11A
10M, 10L, 10K, 10J, 11G, 11F, 11E, 11D, 2D, 2E, 2F, 2G,
I/O1 to I/O16
Synchronous Data In,
1J, 1K, 1L, 1M
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1, NCNote
11C
I/OP2, NCNote
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
1N
9A
/ADV
9B
/AP
8A
/AC
3A, 3B, 6A
5B, 4A, 7A
7B
/CE,CE2, /CE2
/BW1, /BW2, /BWE
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/GW
/G
8B
6B
1R
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
11H
ZZ
4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D, 8E, 8F, 8G, 8H,
VDD
8J, 8K, 8L, 8M
2H, 4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M, 6C,
VSS
Ground
6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D, 7E, 7F, 7G,
7H, 7J, 7K, 7L, 7M, 7N, 8C, 8N
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F,
VDDQ
NC
Output Buffer Power Supply
No Connection
9G, 9J, 9K, 9L, 9M, 9N
1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1P, 2C, 2J, 2K, 2L, 2M,
2N, 2P, 3H, 4B, 5A, 5N, 9H, 10C, 10D, 10E, 10F, 10G,
10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N
TMS
TDI
5R
5P
7R
7P
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
TCK
TDO
Note
NC (No Connection) is used in the µPD44322162GF.
I/OP1 to I/OP2 are used in the µPD44322182GF.
Preliminary Product Information M16355EJ1V0PM
9
µPD44322162, 44322182, 44322322, 44322362
165-pin PLASTIC FBGA (15 x 17)
(Top View)
[µPD44322322F1, µPD44322362F1]
1
NC
2
3
4
5
6
7
/BWE
/GW
VSS
8
9
10
A9
11
NC
A
B
C
D
E
F
A7
/CE
/BW3
/BW4
VSS
/BW2
/BW1
VSS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A19
A1
/AC
/G
/ADV
/AP
NC
A6
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A8
NC
I/OP3, NC
I/O17
I/O18
I/O19
I/O20
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A17
A10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
I/OP2, NC
I/O12
I/O11
I/O10
I/O9
I/O21
I/O22
I/O23
I/O24
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
I/O16
I/O15
I/O14
I/O13
NC
VSS
VSS
VSS
VSS
G
H
J
VSS
VSS
VSS
VSS
ZZ
I/O25
I/O26
I/O27
I/O28
I/OP4, NC
NC
I/O29
I/O30
I/O31
I/O32
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A4
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O8
I/O7
I/O6
I/O5
NC
I/O4
K
L
VSS
VSS
I/O3
VSS
VSS
I/O2
M
N
P
R
VSS
VSS
I/O1
NC
VSS
I/OP1, NC
A18
NC
A12
A2
TDI
TMS
TDO
TCK
A14
A15
MODE
A5
A3
A0
A11
A16
Remark Refer to Package Drawings for the index mark.
Preliminary Product Information M16355EJ1V0PM
10
µPD44322162, 44322182, 44322322, 44322362
[µPD44322322F1, µPD44322362F1]
Symbol
Pin No.
Description
6R, 6P, 4R, 3R, 3P, 2R, 2B, 2A, 10B, 10A, 8R, 9R,
4P, 9P, 10P, 10R, 11R, 8P, 11P, 6N
11M, 11L, 11K, 11J, 10M, 10L, 10K, 10J, 11G, 11F,
11E, 11D, 10G, 10F, 10E, 10D, 1D, 1E, 1F, 1G, 2D,
2E, 2F, 2G, 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M
11N
A0 to A19
Synchronous Address Input
I/O1 to I/O32
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NCNote
Synchronous Data In (Parity),
I/OP2, NCNote
Synchronous / Asynchronous Data Out (Parity)
11C
I/OP3, NCNote
1C
I/OP4, NCNote
1N
9A
/ADV
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
9B
/AP
8A
/AC
3A, 3B, 6A
5B, 5A, 4A, 4B, 7A
7B
/CE,CE2, /CE2
/BWE1 to /BWE4, /BWE
Synchronous Byte Write Enable Input
Synchronous Global Write Input
/GW
/G
8B
6B
1R
Asynchronous Output Enable Input
Clock Input
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
11H
ZZ
4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 8D, 8E, 8F, 8G,
VDD
8H, 8J, 8K, 8L, 8M
2H, 4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M,
VSS
Ground
6C, 6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D, 7E,
7F, 7G, 7H, 7J, 7K, 7L, 7M, 7N, 8C, 8N
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E,
VDDQ
NC
Output Buffer Power Supply
No Connection
9F, 9G, 9J, 9K, 9L, 9M, 9N
1A, 1B, 1H, 1P, 2C, 2N, 2P, 3H, 5N, 9H, 10C, 10H,
10N, 11A, 11B
TMS
TDI
5R
5P
7R
7P
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
TCK
TDO
Note NC (No Connection) is used in the µPD44322322GF.
I/OP1 to I/OP4 are used in the µPD44322362GF.
Preliminary Product Information M16355EJ1V0PM
11
µPD44322162, 44322182, 44322322, 44322362
Block Diagrams
[µPD44322162, µPD44322182]
21
18
21
Address
A0 to A20
Registers
A0, A1
A1’
MODE
/ADV
CLK
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
2,048 × 16 columns
(33,554,432 bits)
2,048 × 18 columns
(37,748,736 bits)
/BWE
16/18
/GW
/CE
16/18
Enable
Register
Output
Registers Buffers
Output
CE2
/CE2
Enable Delay
Register
/G
Input
Registers
2
16/18
I/O1 to I/O16
I/OP1 to I/OP2
Power Down Control
ZZ
Burst Sequence
[µPD44322162, µPD44322182]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, A1, A0
A20 to A2, A1, /A0
A20 to A2, /A1, A0
A20 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 1
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 1, 0
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 1
A20 to A2, 0, 0
A20 to A2, 0, 1
A20 to A2, 1, 0
Preliminary Product Information M16355EJ1V0PM
12
µPD44322162, 44322182, 44322322, 44322362
[µPD44322322, µPD44322362]
20
18
20
Address
A0 to A19
Registers
A0, A1
MODE
/ADV
CLK
A1’
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
/BW3
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
1,024 × 32 columns
(33,554,432 bits)
Byte 3
Write Register
Byte 3
Write Driver
1,024 × 36 columns
(37,748,736 bits)
Byte 4
Write Register
Byte 4
Write Driver
/BW4
/BWE
32/36
32/36
Output
Registers Buffers
Output
/GW
/CE
Enable
Register
CE2
/CE2
Enable delay
Register
Input
Registers
/G
4
32/36
I/O1 to I/O32
I/OP1 to I/OP4
Power Down Control
ZZ
[µPD44322322, µPD44322362]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, A1, A0
A19 to A2, A1, /A0
A19 to A2, /A1, A0
A19 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 1
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 1, 0
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 1
A19 to A2, 0, 0
A19 to A2, 0, 1
A19 to A2, 1, 0
Preliminary Product Information M16355EJ1V0PM
13
µPD44322162, 44322182, 44322322, 44322362
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
I/O
Dout
H
×
High-Z
High-Z, Din
High-Z
×
Remark × : don’t care
Synchronous Truth Table
Operation
/CE
H
L
CE2
/CE2
×
/AP
×
/AC
L
/ADV
×
/WRITE
CLK
Address
None
Deselected Note
×
L
×
L
×
H
H
×
×
×
×
H
×
×
×
×
×
×
×
×
×
×
H
H
H
H
H
L
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
Deselected Note
×
L
×
×
None
Deselected Note
L
H
×
L
×
×
None
Deselected Note
L
H
H
L
L
×
None
Deselected Note
L
H
L
L
×
None
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
L
×
×
External
External
Next
L
L
H
H
×
L
×
×
×
H
H
H
H
L
L
H
×
×
L
Next
×
H
×
H
H
×
Current
Current
External
Next
H
L
×
L
H
H
×
×
×
H
H
H
H
L
L
H
×
×
L
L
Next
×
H
×
H
H
L
Current
Current
H
×
L
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD44322162, µPD44322182]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [µPD44322322, µPD44322362]
Preliminary Product Information M16355EJ1V0PM
14
µPD44322162, 44322182, 44322322, 44322362
Partial Truth Table for Write Enables
[µPD44322162, µPD44322182]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
Read Cycle
H
H
H
H
L
H
L
L
L
×
×
H
L
L
×
×
H
H
L
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
×
Remark × : don’t care
[µPD44322322, µPD44322362]
Operation
/GW
H
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
L
L
L
×
×
H
L
L
×
×
H
H
L
×
H
H
L
×
H
H
L
Read Cycle
H
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
L
×
×
×
Remark × : don’t care
Pass-Through Truth Table
Previous Cycle
Present Cycle
Add /CEs /WRITE /G
Next Cycle
Operation
Operation
Add /WRITE
Ak
I/O
Operation
I/O
Write Cycle
L
Dn(Ak) Read Cycle
(Begin Burst)
Am
L
H
L
Q1(Ak)
Read Q1(Am)
Deselected
-
H
×
×
High-Z
No Carry Over from
Previous Cycle
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD44322162, µPD44322182]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [µPD44322322, µPD44322362]
/CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH.
/CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW.
ZZ (Sleep) Truth Table
ZZ
≤ 0.2 V
Chip Status
Active
Open
Active
≥ VDD − 0.2 V
Sleep
Preliminary Product Information M16355EJ1V0PM
15
µPD44322162, 44322182, 44322322, 44322362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit Notes
Supply voltage
-A44, -A50, -A60
-C50, -C60
V
V
V
+3.0
Output supply voltage
Input voltage
VDDQ
VIN
VDD
VDD + 0.5
VDDQ + 0.5
70
V
V
1, 2
1, 2
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
TA
°C
°C
Tstg
–55
+125
Notes 1. –2.0 V (MIN.) (Pulse width : 2 ns)
2. VDDQ + 2.3 V (MAX.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
(1/2)
Unit
Parameter
Symbol
Conditions
-A44, -A50, -A60
MIN.
TYP.
3.3
MAX.
3.465
Supply voltage
VDD
3.135
V
2.5 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
2.5
2.9
V
V
V
VDDQ + 0.3
+0.7
VIL
–0.3 Note
VDDQ
VIH
3.135
2.0
3.3
3.465
VDDQ + 0.3
+0.8
V
V
V
VIL
–0.3 Note
Note –0.8 V (MIN.) (Pulse Width : 2 ns)
Recommended DC Operating Conditions (TA = 0 to 70 °C)
(2/2)
Parameter
Symbol
Conditions
Unit
-C50, -C60
TYP.
MIN.
2.375
2.375
1.7
MAX.
2.625
Supply voltage
VDD
VDDQ
VIH
2.5
2.5
V
V
V
V
Output supply voltage
High level input voltage
Low level input voltage
2.625
VDDQ + 0.3
+0.7
VIL
–0.3 Note
Note –0.8 V (MIN.) (Pulse Width : 2 ns)
Preliminary Product Information M16355EJ1V0PM
16
µPD44322162, 44322182, 44322322, 44322362
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
Note
Input leakage current
I/O leakage current
Operating supply current
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled
ILO
–2
+2
µA
IDD
Device selected, Cycle = MAX.
-A44
440
410
360
180
mA
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA -A50, -C50
-A60, -C60
IDD1
Suspend cycle, Cycle = MAX.
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH,
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Device deselected, Cycle = 0 MHz
VIN ≤ VIL or VIN ≥ VIH, All inputs are static
Device deselected, Cycle = 0 MHz
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
VI/O ≤ 0.2 V, All inputs are static
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
Standby supply current
ISB
70
60
mA
ISB1
ISB2
ISBZZ
VOH
VOL
130
60
Power down supply current
2.5 V LVTTL Interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL Interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
Input capacitance
6.0
8.0
6.0
Input / Output capacitance
Clock Input capacitance
CI/O
VI/O = 0 V
pF
Cclk
Vclk = 0 V
pF
Remark These parameters are periodically sampled and not 100% tested.
Preliminary Product Information M16355EJ1V0PM
17
µPD44322162, 44322182, 44322322, 44322362
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time = 1 ns (20 to 80 %))
2.4 V
1.2 V
Test points
1.2 V
V
SS
Output waveform
1.2 V
Test points
1.2 V
3.3 V LVTTL Interface
Input waveform (Rise / Fall time = 1 ns (20 to 80%))
3.0 V
1.5 V
Test ponts
1.5 V
V
SS
Output waveform
1.5 V
Test points
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
VT = +1.2 V / +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitance's of the probe and jig, and stray capacitances.
Preliminary Product Information M16355EJ1V0PM
18
µPD44322162, 44322182, 44322322, 44322362
Read and Write Cycle
Parameter
Symbol
-A44
-A50, -C50
(200 MHz)
-A60, -C60
(167 MHz)
Unit
Note
(225 MHz)
Standard
Alias
TCYC
TCD
TOE
TDC1
TDC2
TOLZ
TOHZ
TCZ
TCH
TCL
TAS
TSS
TDS
TWS
–
MIN.
MAX.
–
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
4.4
–
5.0
–
–
3.1
3.1
–
6.0
–
–
3.5
3.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
2.8
2.8
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output High-Z
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
–
–
–
0
0
0
1.5
0
–
1.5
0
–
1.5
0
–
–
–
–
0
2.8
2.8
–
0
3.1
3.1
–
0
3.5
3.5
–
1.5
1.8
1.8
1.4
1.5
2.0
2.0
1.5
1.5
2.0
2.0
1.5
TKLKH
–
–
–
TAVKH
TADSVKH
TDVKH
TWVKH
–
–
–
Data in
Write enable
Address advance TADVVKH
Chip enable
Address
TEVKH
TKHAX
–
Hold times
TAH
TSH
TDH
TWH
–
0.4
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX
TKHDX
Write enable
TKHWX
Address advance TKHADVX
Chip enable
TKHEX
TZZE
–
Power down entry time
TZZE
TZZR
–
–
8.8
8.8
–
–
10.0
10.0
–
–
12.0
12.0
ns
ns
Power down recovery time
TZZR
Preliminary Product Information M16355EJ1V0PM
19
READ CYCLE
TKHKH
CLK
/AP
/AC
TKHKL
TKLKH
TADSVKH
TKHADSX
TADSVKH
TKHADSX
TAVKH
TKHAX
A1
A2
A3
Address
/ADV
µ
TADVVKH
TKHADVX
TWVKH
TKHWX
TKHWX
/BWE
/BWs
TWVKH
/GW
TEVKH
TKHEX
/CEs Note1
/G
TGLQV
TGHQZ
High-Z
High-Z
Data In
TKHQV
Q2(A2)
TKHQZ
TGLQX
TKHQX2
Note2
High-Z
High-Z
Q1(A1)
Q1(A2)
Q3(A2)
Q4(A2) Q1(A2)
Data Out
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs are disabled within one clock cycle after deselect.
Notes 1.
2.
Qn(A2) refers to output from address A2. Q1 to Q4 refer to outputs according to burst sequence.
Remark
WRITE CYCLE
TKHKH
CLK
/AP
TADSVKH TKHADSX
TKHKL
TKLKH
TADSVKH TKHADSX
/AC
Address
/ADV
TAVKH
TKHAX
A1
A2
A3
µ
TADVVKH
TKHADVX
TWVKH
TKHWX
/BWENote1
/BWs
TWVKH
TKHWX
/GWNote1
TEVKH
TKHEX
/CEs Note2
/G
TDVKH
TKHDX
High-Z
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
Data In
TGHQZ
High-Z
Data Out
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
TADSVKH
/AP
/AC
TKHADSX
TAVKH
TKHAX
A1
A2
A3
Address
/ADV
µ
TADVVKH
TKHADVX
TWVKH
TKHWX
/BWE Note1
/BWs
TKHWX
TWVKH
/GW Note1
TEVKH
TKHEX
/CEs Note2
/G
TDVKH
TKHDX
High-Z
High-Z
High-Z
Data In
D1(A2)
TGHQZ
TKHQV
TKHQX1
TGLQX
Q1(A2)
High-Z
High-Z
Data Out
Q1(A1)
Q1(A3) Q2(A3)
Q3(A3)
Q4(A3)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
SINGLE READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
/AC
TAVKH TKHAX
A2
A5
A8
A3
A4
Address
A7
A9
A1
A6
TKHWX
TKHWX
TWVKH
/BWE Note1
/BWs
µ
TWVKH
/GW Note1
TEVKH
TKHEX
/CEs Note2
/G
TDVKH TKHDX
High-Z
High-Z
High-Z
TKHQV
Q1(A7)
Data In
D1(A5) D1(A6)
D1(A7)
TGLQV
TGLQX
Q1(A1)
TKHQZ
Q1(A9)
TGHQZ
Note3
High-Z
Data Out
Q1(A8)
Q1(A2) Q1(A3)
Q1(A4)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
2.
Notes
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs are disabled within one clock cycle after deselect.
3.
/AP is HIGH and /ADV is don't care.
Remark
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
µ
Address
A1
A2
/ADV
/BWE
/BWs
/GW
/CEs
/G
High-Z
High-Z
Q1(A1)
Q1(A2)
Data Out
TZZR
TZZE
ZZ
Power Down (ISBZZ) State
STOP CLOCK CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
µ
/ADV
/BWE
/BWs
/GW
/CEs
/G
High-Z
High-Z
Data In
High-Z
High-Z
Q1(A1)
Q1(A2)
Data Out
Note
Power Down State (ISB1
)
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
µPD44322162, 44322182, 44322322, 44322362
JTAG Specifications
Only the 165-pin PLASTIC FBGA package of µPD44322162, µPD44322182, µPD44322322 and µPD44322362
support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin Name
TCK
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling
edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
Test Data Input. This is the input side of the serial registers placed between TDI and TDO.The register placed
between TDI and TDO is deter-mined by the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 3.3 ± 0.165 V )
(1/2)
Note
Parameter
Symbol
ILI
Conditions
0 V ≤ VIN ≤ VDD
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
µA
JTAG Input leakage current
JTAG I/O leakage current
–
–
ILO
0 V ≤ VIN ≤ VDDQ ,
µA
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
JTAG output low voltage
VIH
VIL
2.0
–0.3
2.4
–
–
–
–
–
VDD+0.3
+0.5
–
V
V
V
V
VOH
VOL
IOH = –4.0 mA
IOL = 8.0 mA
0.4
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 2.5 ± 0.125 V)
(2/2)
Note
Parameter
Symbol
ILI
Conditions
0 V ≤ VIN ≤ VDD
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
µA
JTAG Input leakage current
JTAG I/O leakage current
–
–
ILO
0 V ≤ VIN ≤ VDDQ ,
µA
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
VIH
VIL
1.7
–0.3
1.7
–
–
VDD+0.3
+0.5
V
V
V
VOH
IOH = –2.0 mA
IOL = –1.0 mA
IOH = 2.0 mA
IOL = 1.0 mA
2.1
JTAG output low voltage
VOL
0.7
0.4
V
Preliminary Product Information M16355EJ1V0PM
26
µPD44322162, 44322182, 44322322, 44322362
JTAG AC Test Conditions (TA = 0 to 70 °C)
[-A44, -A50, -A60]
Input waveform (rise / fall time ≤ 1 ns )
Output waveform
1.5 V
1.5 V
Test Points
[-C50, -C60]
Input waveform (rise / fall time ≤ 1 ns )
2.4 V
1.2 V
1.2 V
Test Points
0 V
Output waveform
1.2 V
1.2 V
Test Points
Output load
VTT = 1.2 V / 1.5 V
50 Ω
Z
O
= 50 Ω
TDO
20 pF
Preliminary Product Information M16355EJ1V0PM
27
µPD44322162, 44322182, 44322322, 44322362
JTAG AC Characteristics (TA = 0 to 70 °C)
Parameter
Symbol
tTHTH
Conditions
MIN.
100
40
TYP.
MAX.
Unit
ns
Note
Clock Cycle Time (TCK)
Clock Phase Time (TCK)
Setup Time (TMS / TDI)
Hold Time (TMS / TDI)
TCK Low to TDO Valid (TDO)
–
–
tTHTL / tTLTH
tMVTH / tDVTH
tTHMX / tTHDX
tTLQV
ns
10
–
ns
10
–
ns
–
20
ns
JTAG Timing Diagram
Preliminary Product Information M16355EJ1V0PM
28
µPD44322162, 44322182, 44322322, 44322362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the
input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
Unit
bit
3
1
bit
ID register
32
77
bit
Boundary register
bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
µPD44322162
µPD44322182
µPD44322322
µPD44322362
2M x 16
2M x 18
1M x 32
1M x 36
XXXX
XXXX
XXXX
XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
1
1
1
1
00000010000
00000010000
00000010000
Preliminary Product Information M16355EJ1V0PM
29
µPD44322162, 44322182, 44322322, 44322362
SCAN Exit Order
[ µPD44322162 (2M words by 16 bits) ]
[ µPD44322182 (2M words by 18 bits) ]
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
1
A19
A17
A10
A11
A13
A14
A15
A16
A18
ZZ
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
NC
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1
A19
A17
A10
A11
A13
A14
A15
A16
A18
ZZ
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
NC
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
2
2
3
8R
3
8R
4
9R
/BW2
NC
4
9R
/BW2
NC
5
9P
5
9P
6
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
11B
10A
10B
9A
CE2
/CE
A7
6
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
11B
10A
10B
9A
CE2
/CE
A7
7
7
8
8
9
A6
9
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
NC
NC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/OP1
NC
NC
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
NC
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/OP2
NC
1K
1L
1K
1L
1M
1N
2K
2L
1M
1N
2K
2L
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2M
2J
NC
NC
2M
2J
A20
NC
NC
A20
NC
NC
A5
2R
1R
3P
3R
4R
4P
6P
6R
A5
2R
1R
3P
3R
4R
4P
6P
6R
A9
MODE
A4
A9
MODE
A4
A8
A8
/ADV
/AP
/AC
/G
A3
/ADV
/AP
/AC
/G
A3
9B
A2
9B
A2
8A
A12
A1
8A
A12
A1
8B
8B
/BWE
7A
A0
/BWE
7A
A0
38
39
/GW
CLK
7B
6B
38
39
/GW
CLK
7B
6B
Preliminary Product Information M16355EJ1V0PM
30
µPD44322162, 44322182, 44322322, 44322362
[ µPD44322322 (1M words by 32 bits) ]
[ µPD44322362 (1M words by 36 bits) ]
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
Bit
no.
Signal
name
Bump
ID
1
A19
A17
A10
A11
A13
A14
A15
A16
A18
ZZ
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
/BW2
/BW3
/BW4
CE2
/CE
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1
A19
A17
A10
A11
A13
A14
A15
A16
A18
ZZ
6N
8P
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/CE2
/BW1
/BW2
/BW3
/BW4
CE2
/CE
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1A
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
2
2
3
8R
3
8R
4
9R
4
9R
5
9P
5
9P
6
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
11B
10A
10B
9A
6
10P
10R
11R
11P
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
11B
10A
10B
9A
7
7
8
A7
8
A7
9
A6
9
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
NC
NC
NC
I/OP1
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/OP2
NC
NC
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
NC
NC
I/OP3
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/OP4
A5
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
NC
1K
1L
1K
1L
1M
2J
1M
2J
2K
2L
2K
2L
2M
1N
2R
1R
3P
3R
4R
4P
6P
6R
2M
1N
2R
1R
3P
3R
4R
4P
6P
6R
NC
NC
A5
NC
A9
MODE
A4
A9
MODE
A4
A8
A8
/ADV
/AP
A3
/ADV
/AP
A3
9B
A2
9B
A2
/AC
8A
A12
/AC
8A
A12
/G
8B
A1
/G
8B
A1
/BWE
7A
A0
/BWE
7A
A0
38
39
/GW
CLK
7B
6B
38
39
/GW
CLK
7B
6B
Preliminary Product Information M16355EJ1V0PM
31
µPD44322162, 44322182, 44322322, 44322362
JTAG Instructions
Instructions
EXTEST
Description
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to high impedance any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS
SAMPLE
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (High impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Cording
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
Note
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
Preliminary Product Information M16355EJ1V0PM
32
µPD44322162, 44322182, 44322322, 44322362
TAP Controller State Diagram
Disabling The Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.
TDO should be left unconnected.
Preliminary Product Information M16355EJ1V0PM
33
Test Logic Operation (Instruction Scan)
TCK
TMS
Contoroller
state
µ
TDI
Instruction
Register state
IDCODE
New Instruction
Output Inactive
TDO
Test Logic (Data Scan)
TCK
TMS
Controller
state
µ
TDI
Instructin
Register state
Instruction
IDCODE
Output Inactive
TDO
µPD44322162, 44322182, 44322322, 44322362
Package Drawings
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Preliminary Product Information M16355EJ1V0PM
36
µPD44322162, 44322182, 44322322, 44322362
165-PIN PLASTIC FBGA (15x17)
E
w S B
ZD
ZE
B
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
w S A
INDEX MARK
y1 S
A2
h
A
S
ITEM MILLIMETERS
A1
e
y
D
E
15.00
17.00
2.50
1.50
1.00
0.60
1.40
0.40
1.00
0.45
0.08
0.08
0.15
0.20
S
ZD
ZE
e
φ M
x
φ
b
S A B
h
A
A1
A2
b
y
x
w
y1
This package drawing is a preliminary version. It may be changed in the future.
Preliminary Product Information M16355EJ1V0PM
37
µPD44322162, 44322182, 44322322, 44322362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD44322162, µPD44322182, µPD44322322 and
µPD44322362.
Types of Surface Mount Devices
µPD44322162GF
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 165-pin PLASTIC FBGA (15 x 17)
: 165-pin PLASTIC FBGA (15 x 17)
: 165-pin PLASTIC FBGA (15 x 17)
: 165-pin PLASTIC FBGA (15 x 17)
µPD44322182GF
µPD44322322GF
µPD44322362GF
µPD44322162F1-FQ2
µPD44322182 F1-FQ2
µPD44322322 F1-FQ2
µPD44322362 F1-FQ2
Preliminary Product Information M16355EJ1V0PM
38
µPD44322162, 44322182, 44322322, 44322362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Product Information M16355EJ1V0PM
39
µPD44322162, 44322182, 44322322, 44322362
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
相关型号：
UPD44322183F1-A44-FQ2
Cache SRAM, 2MX18, 2.8ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165
RENESAS
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