UPD44324185F5-E50-EQ2

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD44324085, 44324095, 44324185, 44324365

36M-BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Description

The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a

2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The µPD44324085, µPD44324095, µPD44324185 and µPD44324365 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K

and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with µs restart

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M16782EJ1V0DS00 (1st edition)

Date Published October 2004 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2003

µPD44324085, 44324095, 44324185, 44324365

Ordering Information

Part number

Cycle

Time

ns

Clock

Frequency

MHz

Organization Core Supply

I/O

Package

(word x bit)

Voltage

V

Interface

µPD44324085F5-E33-EQ2 ^Note

µPD44324085F5-E40-EQ2

µPD44324085F5-E50-EQ2

µPD44324095F5-E33-EQ2 ^Note

µPD44324095F5-E40-EQ2

µPD44324095F5-E50-EQ2

µPD44324185F5-E33-EQ2 ^Note

µPD44324185F5-E40-EQ2

µPD44324185F5-E50-EQ2

µPD44324365F5-E33-EQ2 ^Note

µPD44324365F5-E40-EQ2

µPD44324365F5-E50-EQ2

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

300

250

200

300

250

200

300

250

200

300

250

200

4 M x 8-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

FBGA (13 x 15)

4 M x 9-bit

2 M x 18-bit

1M x 36-bit

Note Under development

Preliminary Data Sheet M16782EJ1V0DS

2

µPD44324085, 44324095, 44324185, 44324365

Pin Configurations

/××× indicates active low signal.

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324085F5-EQ2]

1

2

3

A

4

5

/NW1

NC

A

6

7

NC

/NW0

A

8

9

A

10

A

11

CQ

Q3

D3

NC

Q2

NC

ZQ

D1

NC

Q0

D0

NC

TDI

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

NC

D4

R, /W

A

/K

/LD

A

NC

Q4

NC

Q5

VDDQ

NC

D6

NC

Q7

A

K

NC

VDDQ

NC

A

NC

D2

VSS

A

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

D5

VDDQ

VSS

VDDQ

VSS

NC

VREF

Q1

G

H

J

VREF

NC

Q6

K

L

NC

TMS

M

N

P

R

NC

D7

VSS

NC

TCK

A

C

A

/C

A

: Address inputs

: Data inputs

: Data outputs

: Synchronous load

: Read Write input

: Nibble Write data select

: Input clock

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

D0 to D7

Q0 to Q7

/LD

R, /W

/NW0, /NW1

K, /K

TCK

TDO

V^REF

V^DD

V^DDQ

VSS

C, /C

: Output clock

CQ, /CQ

ZQ

/DLL

: Echo clock

: Output impedance matching

: DLL disable

NC

: No connection

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet M16782EJ1V0DS

3

µPD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324095F5-EQ2]

1

2

3

A

4

5

6

7

NC

/BW0

A

8

9

A

10

A

11

CQ

Q4

D4

NC

Q3

NC

ZQ

D2

NC

Q1

D1

NC

Q0

TDI

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

NC

D5

R, /W

A

NC

A

/K

/LD

A

NC

Q5

NC

Q6

VDDQ

NC

D7

NC

Q8

A

K

NC

VDDQ

NC

A

NC

D3

VSS

A

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

D6

VDDQ

VSS

VDDQ

VSS

NC

VREF

Q2

NC

D0

G

H

J

VREF

NC

Q7

K

L

M

N

P

R

NC

D8

VSS

NC

TCK

A

C

A

/C

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

D0 to D8

Q0 to Q8

/LD

R, /W

/BW0

K, /K

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

C, /C

: Output clock

CQ, /CQ

ZQ

/DLL

: Echo clock

: Output impedance matching

: DLL disable

NC

: No connection

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet M16782EJ1V0DS

4

µPD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324185F5-EQ2]

1

2

3

4

5

/BW1

NC

A

6

7

NC

/BW0

A

8

9

A

10

VSS

NC

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

Q9

A

R, /W

A

/K

/LD

A

D9

K

NC

VDDQ

NC

A

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

A

VSS

A

VSS

D11

NC

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

NC

D6

VDDQ

VSS

VDDQ

VSS

Q12

D13

VREF

NC

VREF

Q4

G

H

J

K

L

NC

D3

Q15

NC

Q1

M

N

P

R

D17

NC

VSS

NC

D0

A

C

A

TCK

A

/C

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

D0 to D17

Q0 to Q17

/LD

R, /W

/BW0, /BW1

K, /K

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

C, /C

: Output clock

CQ, /CQ

ZQ

/DLL

: Echo clock

: Output impedance matching

: DLL disable

NC

: No connection

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb.

Preliminary Data Sheet M16782EJ1V0DS

5

µPD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324365F5-EQ2]

1

2

3

4

5

/BW2

/BW3

A

6

7

/BW1

/BW0

A

8

9

10

VSS

Q17

Q7

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

/CQ

Q27

D27

D28

Q29

Q30

D30

/DLL

D31

Q32

Q33

D33

D34

Q35

TDO

V^SS

NC

R, /W

A

/K

/LD

A

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

A

K

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

VSS

A

VSS

VDD

VSS

A

VSS

A

VSS

VDD

VSS

A

VSS

D15

D6

VDDQ

VSS

VDDQ

VSS

Q14

D13

VREF

Q4

G

H

J

K

L

D3

Q11

Q1

M

N

P

R

VSS

D9

A

C

A

D0

A

/C

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

D0 to D35

Q0 to Q35

/LD

R, /W

/BW0 to /BW3

K, /K

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

C, /C

: Output clock

CQ, /CQ

ZQ

/DLL

: Echo clock

: Output impedance matching

: DLL disable

NC

: No connection

Remarks 1. Refer to Package Drawing for the index mark.

2. 3A and 10A are expansion addresses: 3A for 72Mb and 10A for 144Mb.

Preliminary Data Sheet M16782EJ1V0DS

6

µPD44324085, 44324095, 44324185, 44324365

Pin Identification

Symbol

Description

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). These

inputs are ignored when device is deselected.

D0 to Dxx

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K

during WRITE operations. See Pin Configurations for ball site location of individual signals.

x8 device uses D0 to D7.

x9 device uses D0 to D8.

x18 device uses D0 to D17.

x36 device uses D0 to D35.

Q0 to Qxx

Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges

if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site

location of individual signals.

x8 device uses Q0 to Q7.

x9 device uses Q0 to Q8.

x18 device uses Q0 to Q17.

x36 device uses Q0 to Q35.

/LD

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus

activity).

R, /W

Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when R, /W is

HIGH, WRITE when R, /W is LOW) for the loaded address. R, /W must meet the setup and hold times around

the rising edge of K.

/BWx

/NWx

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations

for signal to data relationships.

K, /K

C, /C

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous

inputs must meet setup and hold times around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

/C is used as the output timing reference for first output data. The rising edge of C is used as the output

reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to

force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied

HIGH, C and /C must remain HIGH and not be toggled during device operation.

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates.

CQ, /CQ

ZQ

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. This pin cannot be connected directly to GND or left unconnected.

/DLL

DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

VREF

VDD

IEEE 1149.1 Test Output: 1.8V I/O level.

HSTL Input Reference Voltage: Nominally V^DDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics

and Operating Conditions for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level

applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.

Preliminary Data Sheet M16782EJ1V0DS

7

µPD44324085, 44324095, 44324185, 44324365

Block Diagram

[µPD44324085]

21

ADDRESS

/LD

ADDRESS

REGISTRY

& LOGIC

21

20

R, /W

K

/K

R, /W

/NW0

/NW1

2²¹x 16

DATA

16

8

2

16

8

D0 to D7

/LD

Q0 to Q7

REGISTRY

& LOGIC

MEMORY

ARRAY

MUX

CQ,

/CQ

K

C, /C

/K

OR

K, /K

[µPD44324095]

21

ADDRESS

/LD

ADDRESS

REGISTRY

& LOGIC

R, /W

K

/K

R, /W

/BW0

2²¹x 18

DATA

18

9

2

18

9

D0 to D8

/LD

Q0 to Q8

REGISTRY

& LOGIC

MEMORY

ARRAY

MUX

CQ,

/CQ

K

C, /C

OR

K, /K

/K

[µPD44324185]

20

ADDRESS

/LD

ADDRESS

REGISTRY

& LOGIC

R, /W

K

/K

R, /W

/BW0

/BW1

2²⁰x 36

DATA

36

18

2

36

18

Q0 to Q17

REGISTRY

& LOGIC

D0 to D17

/LD

MEMORY

ARRAY

MUX

CQ,

/CQ

K

C, /C

OR

/K

K, /K

Preliminary Data Sheet M16782EJ1V0DS

8

µPD44324085, 44324095, 44324185, 44324365

[µPD44324365]

19

ADDRESS

/LD

ADDRESS

REGISTRY

& LOGIC

19

R, /W

K

/K

R, /W

/BW0

/BW1

/BW2

/BW3

2¹⁹x 72

DATA

72

36

2

72

Q0 to Q35

REGISTRY

& LOGIC

MEMORY

ARRAY

MUX

36

D0 to D35

CQ,

/CQ

/LD

K

C, /C

/K

OR

K, /K

Power-on Sequence

The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after

DD/VDDQ stable and when starting the clock before VDD/VDDQ stable.

V

1. Clock starts after V^DD/VDDQ stable

V

DD/VDDQ

V

DD/VDDQ Stable (< 0.1 V DC per 50 ns)

Clock

Clock Start

1,024 cycles or more

Stable Clock

Start

Normal Operation

2. Clock starts before V^DD/VDDQ stable

V

DD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

Clock

Clock Start

30 ns (MIN.)

1,024 cycles or more Start

DLL Reset or DLL Off

Stable Clock

Normal Operation

Preliminary Data Sheet M16782EJ1V0DS

9

µPD44324085, 44324095, 44324185, 44324365

Truth Table

Operation

/LD R, /W

CLK

D or Q

Data in

WRITE cycle

L

L → H

Load address, input write data on two

consecutive K and /K rising edge

READ cycle

Input data

Input clock

D(A+0)

D(A+1)

K(t+1) ↑

/K(t+1) ↑

L

H

L → H

Data out

Output data

Output clock

High-Z

Previous state

Load address, read data on two

consecutive C and /C rising edge

NOP (No operation)

Q(A+0)

Q(A+1)

/C(t+1) ↑

C(t+2) ↑

H

X

L → H

STANDBY(Clock stopped)

Stopped

Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet M16782EJ1V0DS

10

µPD44324085, 44324095, 44324185, 44324365

Byte Write Operation

[µPD44324085]

Operation

K

/K

–

/NW0

/NW1

Write D0 to D7

L → H

0

1

0

1

0

1

–

L → H

–

L → H

–

Write D0 to D3

Write D4 to D7

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324095]

Operation

Write D0 to D8

K

/K

–

/BW0

L → H

0

1

–

L → H

–

L → H

–

Write nothing

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324185]

Operation

Write D0 to D17

K

L → H

–

/K

–

/BW0

/BW1

0

1

0

1

0

1

L → H

–

Write D0 to D8

Write D9 to D17

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324365]

Operation

Write D0 to D35

K

L → H

–

/K

–

/BW0

/BW1

/BW2

/BW3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

–

Write D0 to D8

Write D9 to D17

Write D18 to D26

Write D27 to D35

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

Preliminary Data Sheet M16782EJ1V0DS

11

µPD44324085, 44324095, 44324185, 44324365

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 2

Write

Load, Count = 2

READ DOUBLE

Read

WRITE DOUBLE

Count = Count + 2

Load

NOP,

Count = 2

NOP

Supply voltage provided

Power UP

Remark State machine control timing sequence is controlled by K.

Preliminary Data Sheet M16782EJ1V0DS

12

µPD44324085, 44324095, 44324185, 44324365

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol Conditions

MIN.

–0.5

0

TYP.

MAX.

Unit

V

Supply voltage

VDD

VDDQ

VIN

+2.5

Output supply voltage

Input voltage

VDD

VDD + 0.5 (2.5 V MAX.)

VDDQ + 0.5 (2.5 V MAX.)

70

V

Input / Output voltage

Operating ambient temperature

Storage temperature

VI/O

TA

V

°C

Tstg

–55

+125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70 °C)

Parameter

Supply voltage

Symbol

Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit

V

Note

VDD

Output supply voltage

High level input voltage

Low level input voltage

Clock input voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

VDD

V

1

VREF + 0.1

–0.3

VDDQ + 0.3

VREF – 0.1

VDDQ + 0.3

0.95

V

1, 2

V

–0.3

V

Reference voltage

VREF

0.68

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (TA = 0 to 70 °C)

Parameter

High level input voltage

Low level input voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF + 0.2

–

TYP.

MAX.

–

Unit

V

Note

1

VREF – 0.2

V

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Preliminary Data Sheet M16782EJ1V0DS

13

µPD44324085, 44324095, 44324185, 44324365

DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit Note

x8, x9 x18 x36

Input leakage current

I/O leakage current

Operating supply current

(Read Write cycle)

ILI

–2

–

+2

µA

ILO

IDD

VIN ≤ VIL or VIN ≥ VIH, –E33

750 1,050 1,200 mA

650 900 1,000

550 750 850

II/O = 0 mA

–E40

–E50

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH, –E33

550

500

mA

II/O = 0 mA

–E40

–E50

Cycle = MAX.

400

High level output voltage

Low level output voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note1

VOL(Low) IOL ≤ 0.1 mA

VOL Note2

VDDQ – 0.2

VDDQ/2–0.12

VSS

–

VDDQ

V

3, 4

VDDQ/2+0.12

0.2

VDDQ/2–0.12

VDDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

Capacitance (TA = 25 °C, f = 1MHz)

Parameter

Input capacitance

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

pF

4

6

5

7

6

Input / Output capacitance

Clock Input capacitance

CI/O

VI/O = 0 V

Vclk = 0 V

pF

Cclk

pF

Remark These parameters are periodically sampled and not 100% tested.

Preliminary Data Sheet M16782EJ1V0DS

14

µPD44324085, 44324095, 44324185, 44324365

AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V)

AC Test Conditions

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

0.25 V

0.75 V

Test Points

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

VDDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Preliminary Data Sheet M16782EJ1V0DS

15

µPD44324085, 44324095, 44324185, 44324365

Read and Write Cycle

-E33

-E40

-E50

Parameter

Symbol

Unit Note

(300 MHz)

(250 MHz)

(200 MHz)

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Clock

Average Clock cycle time (K, /K, C, /C) TKHKH

ns

1

2

3.3

–

8.4

0.2

–

4.0

–

8.4

0.2

–

5.0

–

8.4

0.2

–

2.3

2.8

3.55

–

Clock phase jitter (K, /K, C, /C)

Clock HIGH time (K, /K, C, /C)

Clock LOW time (K, /K, C, /C)

Clock to /clock (K→/K., C→/C.)

Clock to /clock (/K→K., /C→C.)

TKC var

TKHKL

TKLKH

TKH /KH

T /KHKH

1.32

1.49

0

1.6

1.8

–

0

2.0

2.2

–

0

–

Clock to data clock 250 to 300 MHz TKHCH

1.45

1.8

2.3

2.8

3.55

–

(K→C., /K→/C.)

200 to 250 MHz

167 to 200 MHz

133 to 167 MHz

< 133 MHz

1.8

2.3

2.8

3.55

–

DLL lock time (K, C)

K static to DLL reset

TKC lock

TKC reset

Cycle

ns

3

1,024

30

1,024

30

1,024

30

–

Output Times

C, /C HIGH to output valid

C, /C HIGH to output hold

C, /C HIGH to echo clock valid

C, /C HIGH to echo clock hold

CQ, /CQ HIGH to output valid

CQ, /CQ HIGH to output hold

C HIGH to output High-Z

TCHQV

TCHQX

ns

–

– 0.45

–

– 0.45

–

– 0.27

–

– 0.45

0.45

–

0.45

–

0.27

–

0.45

–

– 0.45

–

– 0.45

–

– 0.3

–

– 0.45

0.45

–

0.45

–

0.3

–

0.45

–

– 0.45

–

– 0.45

–

– 0.35

–

– 0.45

0.45

–

0.45

–

0.35

–

0.45

–

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

4

C HIGH to output Low-Z

TCHQX1

Setup Times

Address valid to K rising edge

Synchronous load input (/LD),

read write input (R, /W) valid to

K rising edge

TAVKH

TIVKH

ns

5

0.4

–

0.5

–

0.6

–

Data inputs and write data select

inputs (/BWx, /NWx) valid to

K, /K rising edge

TDVKH

ns

5

0.3

–

0.35

–

0.4

–

Hold Times

K rising edge to address hold

K rising edge to

TKHAX

TKHIX

ns

5

0.4

–

0.5

–

0.6

–

synchronous load input (/LD),

read write input (R, /W) hold

K, /K rising edge to data inputs and

write data select inputs (/BWx, /NWx)

hold

TKHDX

ns

5

0.3

–

0.35

–

0.4

–

Preliminary Data Sheet M16782EJ1V0DS

16

µPD44324085, 44324095, 44324185, 44324365

Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

3. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.

DLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept inactive during these cycles.

4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

5. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.

5. V^DDQ is 1.5 V DC.

Preliminary Data Sheet M16782EJ1V0DS

17

µPD44324085, 44324095, 44324185, 44324365

Read and Write Timing

NOP

WRITE

(burst of 2)

WRITE

(burst of 2)

READ

(burst of 2)

READ

(burst of 2)

READ

(burst of 2)

NOP

1

2

3

4

5

6

7

8

K

TKHKL TKLKH

TKHKH

TKH/KH

T/KHKH

/K

/LD

TKHIX

TIVKH

R, /W

A0

A2

A4

TDVKH TKHDX

A1

A3

Address

TDVKH TKHDX

TKHAX

TAVKH

Data in

D21

D22

D31

D32

Data out

Q01

Q02

Q11

Q12

Q41

Q42

Qx2

TCHQX1

TCHQZ

TCQHQV

TCHQX

TCHQV

CQ

TCHCQX

TCHCQV

/CQ

TCHCQX

TCHCQV

TKHCH

C

TKHKL TKLKH

TKHKH

TKH/KH T/KHKH

TKHCH

/C

Remarks 1. Q01 refers to output from address A0+0.

Q02 refers to output from the next internal burst address following A0, i.e., A0+1.

2. Outputs are disable (high impedance) one clock cycle after a NOP.

3. In this example, if address A3=A4, data Q41=D31, Q42=D32.

Write data is forwarded immediately as read results.

Preliminary Data Sheet M16782EJ1V0DS

18

µPD44324085, 44324095, 44324185, 44324365

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

Test Mode Select. This is the command input for the TAP controller state machine.

TMS

TDI

10R

11R

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. Output changes in response to the falling edge of TCK. This is the

output side of the serial registers placed between TDI and TDO.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

–5.0

TYP.

MAX.

+5.0

Unit

µA

Note

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

–

ILO

0 V ≤ VIN ≤ VDDQ,

µA

Outputs disabled

JTAG input high voltage

JTAG input low voltage

JTAG output high voltage

VIH

VIL

1.3

–0.3

1.6

1.4

–

VDD+0.3

V

+0.5

–

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 µA

| IOHT | = 2 mA

IOLC = 100 µA

IOLT = 2 mA

–

JTAG output low voltage

0.2

0.4

–

Preliminary Data Sheet M16782EJ1V0DS

19

µPD44324085, 44324095, 44324185, 44324365

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

Preliminary Data Sheet M16782EJ1V0DS

20

µPD44324085, 44324095, 44324185, 44324365

JTAG AC Characteristics (TA = 0 to 70 °C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Clock

Clock cycle time

Clock frequency

Clock high time

Clock low time

tTHTH

fTF

100

–

10

–

ns

MHz

ns

tTHTL

tTLTH

40

–

ns

Output time

TCK low to TDO unknown

TCK low to TDO valid

TDI valid to TCK high

TCK high to TDI invalid

tTLOX

tTLOV

tDVTH

tTHDX

0

–

20

–

ns

10

–

Setup time

TMS setup time

Capture setup time

tMVTH

tCS

10

–

ns

Hold time

TMS hold time

Capture hold time

tTHMX

tCH

10

–

ns

JTAG Timing Diagram

tTHTH

TCK

tMVTH

tTHTL

t

TLTH

TMS

TDI

tTHMX

tDVTH

tTHDX

tTLOV

tTLOX

TDO

Preliminary Data Sheet M16782EJ1V0DS

21

µPD44324085, 44324095, 44324185, 44324365

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

Part number Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 0100 0101

0000 0000 0100 0110

0000 0000 0100 0111

0000 0000 0100 1000

ID [11:1] vendor ID no.

00000010000

ID [0] fix bit

µPD44324085

µPD44324095

µPD44324185

µPD44324365

4M x 8

4M x 9

XXXX

1

00000010000

2M x 18

1M x 36

00000010000

Preliminary Data Sheet M16782EJ1V0DS

22

µPD44324085, 44324095, 44324185, 44324365

SCAN Exit Order

Bit

Signal name

x9 x18 x36

Bump

ID

Bit

Signal name

X9 x18 x36

Bump

ID

Bit

Signal name

Bump

ID

no.

x8

no.

x8

no.

x8

X9

x18 x36

1

/C

C

A

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

NC NC

NC D15 10D

NC Q15 9E

73

74

NC

Q4

D4

NC

Q5

D5

NC

Q5

D5

NC

NC Q28

Q11 Q20

D11 D20

NC D29

NC Q29

2C

3E

2D

2E

1E

2F

3F

1G

1F

2

3

Q7

D7

Q7 10C

D7 11D

75

4

76

5

NC D16 9C

NC Q16 9D

77

6

78

NC Q12 Q21

NC D12 D21

7

Q3

D3

Q4

D4

Q8

D8

Q8 11B

D8 11C

79

8

80

NC

Q6

D6

NC D30

NC Q30

9

NC NC

NC D17 9B

NC Q17 10B

11A

81

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

NC Q0

NC D0

Q0

D0

Q0 11P

D0 10P

82

Q13 Q22 3G

CQ

83

D13 D22

2G

1H

1J

NC NC NC D9 10N

NC NC NC Q9 9P

A

VSS

VSS 10A

84

/DLL

A

9A

8B

7C

6C

8A

85

NC

Q6

D6

NC

NC D31

NC Q31

NC NC Q1

NC NC D1

Q1 10M

D1 11N

86

2J

A

87

NC Q14 Q23

NC D14 D23

3K

3J

NC NC NC D10 9M

NC NC NC Q10 9N

A

88

/LD

89

NC

Q7

D7

NC

NC D32

NC Q32

Q15 Q24

D15 D24

2K

1K

2L

3L

Q0

D0

Q1

D1

Q2

D2

Q2 11L

D2 11M

NC NC

NC /BW1 7A

90

55 /NW0 /BW0 /BW0 /BW0 7B

91

NC NC NC D11 9L

NC NC NC Q11 10L

56

57

58

K

6B

6A

92

/K

93

NC

Q7

D7

NC D33 1M

NC NC Q3

NC NC D3

Q3 11K

D3 10K

NC NC

NC /BW3 5B

94

NC Q33

1L

59 /NW1 NC /BW1 /BW2 5A

95

NC Q16 Q25

3N

NC NC NC D12 9J

NC NC NC Q12 9K

60

61

62

63

64

65

66

67

68

69

70

71

72

R, /W

4A

5C

4B

3A

2A

1A

96

NC D16 D25 3M

A

97

NC

Q8

D8

NC

NC D34

1N

Q1

D1

Q2

D2

Q4

D4

Q4 10J

D4 11J

11H

98

NC Q34 2M

A

NC

99

Q17 Q26

D17 D26

NC D35

NC Q35

3P

2N

ZQ

VSS

100

101

102

103

104

105

106

107

108

109

NC NC NC D13 10G

NC NC NC Q13 9G

/CQ

NC

2P

NC NC

Q9 Q18 2B

D9 D18 3B

NC D27 1C

NC Q27 1B

1P

NC NC Q5

NC NC D5

Q5 11F

D5 11G

A

–

3R

4R

NC NC NC D14 9F

NC NC NC Q14 10F

4P

NC NC Q10 Q19 3D

NC NC D10 D19 3C

5P

Q2

D2

Q3

D3

Q6

D6

Q6 11E

D6 10E

5N

NC NC

NC D28 1D

5R

Internal

Preliminary Data Sheet M16782EJ1V0DS

23

µPD44324085, 44324095, 44324185, 44324365

JTAG Instructions

Instructions

EXTEST

Description

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

The BYPASS instruction is loaded in the instruction register when the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

1

0

1

IDCODE

0

1

0

SAMPLE-Z

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

0

1

Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

Preliminary Data Sheet M16782EJ1V0DS

24

µPD44324085, 44324095, 44324185, 44324365

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs.

TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and

may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.

TDO should be left unconnected.

Preliminary Data Sheet M16782EJ1V0DS

25

µPD44324085, 44324095, 44324185, 44324365

Package Drawing

165-PIN PLASTIC FBGA (13x15)

E

w S B

ZD

ZE

B

11

10

9

8

7

A

6

5

D

4

3

2

1

R P N M L K J H G F E D C B A

w S A

INDEX MARK

y1 S

A2

h

A

S

ITEM MILLIMETERS

A1

e

y

D

E

13.00

15.00

1.50

0.50

1.00

0.60

1.40

0.40

1.00

0.50

0.08

0.15

0.20

S

ZD

ZE

e

φ M

x

φ

b

S A B

h

A

A1

A2

b

y

x

w

y1

This package drawing is a preliminary version. It may be changed in the future.

Preliminary Data Sheet M16782EJ1V0DS

28

µPD44324085, 44324095, 44324185, 44324365

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

µPD44324085F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324095F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324185F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324365F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

Preliminary Data Sheet M16782EJ1V0DS

29

µPD44324085, 44324095, 44324185, 44324365

Revision History

Edition/

Page

Type of

revision

Location

Description

Date

This

edition

(Previous edition → This edition)

1st edition/

Oct. 2004

Modification



Preliminary Product Information

Throughout Throughout

→ Preliminary Data sheet

F5-EQ1 → F5-EQ2

Package Code

Deletion

Addition



−E60 (167MHz)

p.2

Ordering Information

"Note Under development" has been added to

−E33.

pp.3-6

p.9

pp.3-6



Pin Configurations

Remark 2 has been added

Power-on sequence has been added

Power-on Sequence

p.14

Modification DC Characteristics IDD (MAX.)

MAX.

Unit

x8, x9 x18 x36

−E33 760 780 810

−E40 650 670 700

−E50 550 570 600

x8, x9 x18 x36

mA

−E33 750 1,050 1,200

−E40 650 900 1,000

−E50 550 750 850

DC Characteristics ISB1 (MAX.)

MAX.

Unit

x8, x9 x18 x36

mA

−E33

−E40

−E50

290

250

210

−E33

−E40

−E50

550

500

400

Preliminary Data Sheet M16782EJ1V0DS

30

µPD44324085, 44324095, 44324185, 44324365

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

Preliminary Data Sheet M16782EJ1V0DS

31

µPD44324085, 44324095, 44324185, 44324365

•

The information in this document is current as of October, 2004. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD44324185F5-E50-EQ2
厂家：	NEC
描述：	36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION 36M - BIT DDRII SRAM独立的I / O 2字突发操作存储内存集成电路静态存储器双倍数据速率
文件：	总32页 (文件大小：351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44324185F5-E50-EQ2 [NEC]

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