UPD44646366F5-E33-FQ1-A

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

72M-BIT DDR II+ SRAM

2.0 & 2.5 Cycle Read Latency

4-WORD BURST OPERATION

Description

The μPD44646094 and μPD44646096 are 8,388,608-word by 9-bit, the μPD44646184 and μPD44646186 are

4,194,304-word by 18-bit and the μPD44646364 and μPD44646366 are 2,097,152-word by 36-bit synchronous double

data rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44646xx4 is for 2.0 cycle and the μPD44646xx6 is for 2.5 cycle read latency. The μPD44646094, μPD44646096,

μPD44646184, μPD44646186, μPD44646364 and μPD44646366 integrate unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• Core (VDD) = 1.8 ± 0.1 V power supply

I/O (V^DDQ) = 1.5 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15x17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Four - tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two Echo clocks (CQ and CQ#)

• Data Valid pin (QVLD) supported

• Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,

2.5 ns (400 MHz) for 2.5 cycle read latency

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18524EJ1V0DS00 (1st edition)

Date Published November 2006 NS CP(N)

Printed in Japan

2006

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Ordering Information

2.0 Cycle Read Latency

Core

Part number

Cycle

Clock

Organization

(word x bit)

I/O

Package

Supply

Time

ns

Frequency

MHz

375

Voltage

Interface

V

μPD44646094F5-E27-FQ1

μPD44646094F5-E30-FQ1

μPD44646094F5-E33-FQ1

μPD44646184F5-E27-FQ1

μPD44646184F5-E30-FQ1

μPD44646184F5-E33-FQ1

μPD44646364F5-E27-FQ1

μPD44646364F5-E30-FQ1

μPD44646364F5-E33-FQ1

μPD44646094F5-E27-FQ1-A

μPD44646094F5-E30-FQ1-A

μPD44646094F5-E33-FQ1-A

μPD44646184F5-E27-FQ1-A

μPD44646184F5-E30-FQ1-A

μPD44646184F5-E33-FQ1-A

μPD44646364F5-E27-FQ1-A

μPD44646364F5-E30-FQ1-A

μPD44646364F5-E33-FQ1-A

2.66

3.0

8M x 9-bit

4M x 18-bit

2M x 36-bit

8M x 9-bit

4M x 18-bit

2M x 36-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

333

3.3

300

2.66

3.0

375

333

3.3

300

2.66

3.0

375

333

3.3

300

2.66

3.0

375

333

300

375

333

300

375

333

300

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

Lead-free

3.3

2.66

3.0

3.3

2.66

3.0

3.3

Remark Products with -A at the end of the part number are lead-free products.

Preliminary Data Sheet M18524EJ1V0DS

2

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

2.5 Cycle Read Latency

Core

Part number

Cycle

Clock

Organization

(word x bit)

I/O

Package

Supply

Time

ns

Frequency

MHz

400

Voltage

V

Interface

μPD44646096F5-E25-FQ1

μPD44646096F5-E27-FQ1

μPD44646096F5-E30-FQ1

μPD44646096F5-E33-FQ1

μPD44646186F5-E25-FQ1

μPD44646186F5-E27-FQ1

μPD44646186F5-E30-FQ1

μPD44646186F5-E33-FQ1

μPD44646366F5-E25-FQ1

μPD44646366F5-E27-FQ1

μPD44646366F5-E30-FQ1

μPD44646366F5-E33-FQ1

μPD44646096F5-E25-FQ1-A

μPD44646096F5-E27-FQ1-A

μPD44646096F5-E30-FQ1-A

μPD44646096F5-E33-FQ1-A

μPD44646186F5-E25-FQ1-A

μPD44646186F5-E27-FQ1-A

μPD44646186F5-E30-FQ1-A

μPD44646186F5-E33-FQ1-A

μPD44646366F5-E25-FQ1-A

μPD44646366F5-E27-FQ1-A

μPD44646366F5-E30-FQ1-A

μPD44646366F5-E33-FQ1-A

2.5

8M x 9-bit

4M x 18-bit

2M x 36-bit

8M x 9-bit

4M x 18-bit

2M x 36-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

2.66

3.0

375

333

3.3

300

2.5

400

2.66

3.0

375

333

3.3

300

2.5

400

2.66

3.0

375

333

3.3

300

2.5

2.66

3.0

400

375

333

300

400

375

333

300

400

375

333

300

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

Lead-free

3.3

2.5

2.66

3.0

3.3

2.5

2.66

3.0

3.3

Remark Products with -A at the end of the part number are lead-free products.

3

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Feature Differences between DDR II and DDR II+

Features

Frequency (DLL/PLL ON)

Organization

DDR II

120 MHz to 300 MHz

x8 / x9 / x18 / x36

1.8 ± 0.1 V

DDR II+

300 MHz to 400 MHz

x9 / x18 / x36

Note

VDD

1.8 ± 0.1 V

VDDQ

1.8 ± 0.1 V or 1.5 ± 0.1 V

1.5 clocks

1.5 ± 0.1 V

Read Latency

2.0 & 2.5 clocks

1.0 clocks

1

2

Write Latency

1.0 clocks

Input Clocks (K, K#)

Output Clocks (C, C#)

Echo Clock Number (CQ, CQ#)

Package

Single Ended (K, K#)

Yes

Single Ended (K, K#)

No

1 Pair

3

165 (11x15) pin PLASTIC BGA

Fixed Burst Address for DDR CIO;

A0 and A1 for burst 4

Yes

No

4

5

QVLD

Yes

Notes 1. DDR II+ read latency is not user selectable. Offered as two different devices.

2. DDR II+ write latency is 1.0 cycle regardless of read latency.

3. Echo Clocks are single-ended inputs.

4. Linear burst is not supported at DDR II + CIO.

5. Edge aligned with Echo Clocks.

Preliminary Data Sheet M18524EJ1V0DS

4

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Pin Configurations

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44646094], [μPD44646096]

8M x 9-bit

1

CQ#

NC

2

3

A

4

5

NC

NC/288M

A

6

K#

7

8

9

A

10

A

11

CQ

DQ4

NC

A

B

C

D

E

F

A

R, W#

A

LD#

A

NC/144M

BW0#

A

NC

VREF

NC

DQ7

NC

TCK

NC

DQ5

NC

DQ6

VDDQ

NC

DQ8

A

K

NC

VDDQ

NC

A

NC

VREF

DQ2

NC

TMS

NC

VSS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ3

NC

G

H

J

NC

DLL#

NC

ZQ

NC

K

L

NC

DQ1

NC

M

N

P

R

NC

VSS

NC

A

QVLD

NC

A

DQ0

TDI

TDO

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ8

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0#

K, K#

CQ, CQ#

ZQ

: Echo clock

V^DDQ

V^SS

: Power Supply

: Output impedance matching

: DLL/PLL disable

: Q Valid output

: Ground

DLL#

NC

: No connection

QVLD

NC/xxM

: Expansion address for xxMb

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 7A and 5B are expansion addresses: 7A for 144Mb and 5B for 288Mb.

5

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44646184], [μPD44646186]

4M x 18-bit

1

CQ#

NC

2

A

3

4

5

BW1#

NC/288M

A

6

K#

7

8

9

A

10

A

11

CQ

A

B

C

D

E

F

A

R, W#

A

LD#

A

NC/144M

BW0#

NC

DQ9

NC

K

NC

VDDQ

NC

A

NC

DQ8

NC

VSS

NC

VSS

A

VSS

DQ7

NC

DQ10

DQ11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

NC

DQ13

VDDQ

NC

DLL#

NC

VREF

NC

VREF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

VSS

NC

A

QVLD

NC

A

NC

DQ0

TDI

TDO

TCK

A

TMS

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ17

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0#, BW1#

K, K#

CQ, CQ#

ZQ

: Echo clock

V^DDQ

V^SS

: Power Supply

: Output impedance matching

: DLL/PLL disable

: Q Valid output

: Ground

DLL#

NC

: No connection

QVLD

NC/xxM

: Expansion address for xxMb

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 7A and 5B are expansion addresses: 7A for 144Mb and 5B for 288Mb.

Preliminary Data Sheet M18524EJ1V0DS

6

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44646364], [μPD44646366]

2M x 36-bit

1

CQ#

NC

2

3

4

5

BW2#

BW3#

A

6

K#

7

BW1#

BW0#

NC

VSS

VDD

VSS

A

8

9

A

10

A

11

CQ

A

B

C

D

E

F

A

R, W#

A

LD#

A

NC/144M

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

K

NC

VDDQ

NC

A

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

NC

VSS

NC

VSS

A

VSS

DQ17

NC

DQ29

NC

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ15

NC

DQ30

DQ31

VREF

NC

G

H

J

NC

DLL#

NC

VREF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

NC

DQ11

NC

DQ35

NC

VSS

NC

A

QVLD

NC

A

DQ9

TMS

TDO

TCK

A

: Address inputs

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

DQ0 to DQ35

LD#

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

TDI

TCK

TDO

V^REF

VDD

R, W#

BW0# to BW3#

K, K#

CQ, CQ#

ZQ

: Echo clock

V^DDQ

V^SS

: Power Supply

: Output impedance matching

: DLL/PLL disable

: Q Valid output

: Ground

DLL#

NC

: No connection

QVLD

NC/xxM

: Expansion address for xxMb

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A is expansion addresses: 2A for 144Mb.

7

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Pin Identification

Symbol

Description

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of four words (two clock period of bus activity). These

inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).

DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output

data is synchronized to the respective K and K#.

x9 device uses DQ0 to DQ8.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

LD#

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transactions operate on a burst of 4 data (two clock period of bus

activity).

R, W#

Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#

is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times

around the rising edge of K. If a synchronous load command (LD# = LOW) is input, inputs of R,W# and LD# on

the subsequent of K are ignored.

BWx#

Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and written

during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K# for

each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data

relationships.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx# and DQxx.

K, K#

CQ, CQ#

ZQ

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All

synchronous inputs must meet setup and hold times around the clock rising edges.

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ

tristates. If K and K# are stopped in the single clock mode, CQ and CQ# will also stop.

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ, CQ, CQ# and QVLD output impedance are set to 0.2 x RQ, where RQ is a resistor from this

bump to ground. The output impedance can be minimized by directly connect ZQ to V^DDQ. This pin cannot be

connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon

power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new

output impedance is reset by implementing power-on sequence.

DLL#

DLL/PLL Disable: When DLL# is LOW, the operation can be performed at a clock frequency slower than

TKHKH (MAX.) without the DLL/PLL circuit being used. The AC/DC characteristics cannot be guaranteed. For

normal operation, DLL# must be HIGH and it can be connected to V^DDQ through a 10 kΩ or less resistor.

QVLD

Q valid Output: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

TDO

VREF

VDD

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

IEEE 1149.1 Test Output: 1.8 V I/O level.

HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for

range.

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. See Recommended DC Operating

Conditions and DC Characteristics for range.

VDDQ

VSS

Power Supply: Ground

No Connect: These signals are not connected internally.

NC

Preliminary Data Sheet M18524EJ1V0DS

8

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Block Diagram

x9/x18/x36

Write Register

Address

Register

A

Write Driver

x9/x18/x36

DQx

CQ#

Add.

Dec.

Output

Buffer

K#

K

Memory Array

CQ

CLK

Gen.

QVLD

DLL#

Sense AMPs

MUX

R, W#

BWx#

LD#

Control

Logic

x36/x72/x144

x18/x36/x72

Output Register

9

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Power-On Sequence in DDR II+ SRAM

DDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

The following power-up supply voltage application is recommended: V^SS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ

can be applied simultaneously, as long as V^DDQ does not exceed VDD by more than 0.5 V during power-up. The

following power-down supply voltage removal sequence is recommended: V^IN, VREF, VDDQ, VDD, VSS. VDD and VDDQ

can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.

Power-On Sequence

Apply power and tie DLL# to HIGH.

- Apply V^DDbefore VDDQ.

- Apply V^DDQ before VREF or at the same time as VREF.

Provide stable clock for more than 2,048 cycles to lock the DLL/PLL.

DLL/PLL Constraints

The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified

as TKC var. The DLL/PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the

DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.

Power-On Waveforms

V

DD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

DLL#

Clock

Fix HIGH (or tied to V^DDQ)

2,048 cycles or more

Unstable Clock

Normal Operation

Start

Stable Clock

Preliminary Data Sheet M18524EJ1V0DS

10

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Truth Table

Read Latency = 2.0 clocks

[μPD44646094], [μPD44646184], [μPD44646364]

Operation

CLK

LD# R,W#

DQ

WRITE cycle

L → H

L

Data in

D^A(A+2)

DA(A+3)

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

Input clock

DA(A+0)

DA(A+1)

K(t+2) ↑

K#(t+2) ↑

K(t+1) ↑

K#(t+1) ↑

L → H

L

H

Data out

Q^A(A+2)

QA(A+3)

Load address, read data on two

consecutive K and K# rising edge

NOP (No operation)

Output data

Output clock

QA(A+0)

QA(A+1)

K(t+3) ↑

K#(t+3) ↑

K(t+2) ↑

K#(t+2) ↑

L → H

H

X

DQ = High-Z

Clock stop

Stopped

Previous state

Read Latency = 2.5 clocks

[μPD44646096], [μPD44646186], [μPD44646366]

Operation

CLK

LD# R,W#

DQ

WRITE cycle

L → H

L

Data in

D^A(A+2)

DA(A+3)

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

DA(A+0)

DA(A+1)

K(t+2) ↑

K#(t+2) ↑

Input clock

K(t+1) ↑

K#(t+1) ↑

L → H

L

H

Data out

Q^A(A+2)

QA(A+3)

Load address, read data on two

consecutive K and K# rising edge

NOP (No operation)

Output data

QA(A+0)

QA(A+1)

K#(t+3) ↑ K (t+4) ↑

Output clock K#(t+2) ↑

K(t+3) ↑

L → H

H

X

DQ = High-Z

Clock stop

Stopped

Previous state

Remarks

Remarks listed below are for both products with 2.0 and 2.5 Cycle Read Latency.

1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K and are registered at the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A+0 refers to the address input during a WRITE or READ cycle.

A+1, A+2 and A+3 refers to the next internal burst address in accordance with the burst sequence.

7. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart

by overcoming transmission line charging symmetrically.

11

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Byte Write Operation

[μPD44646094], [μPD44646096]

Operation

K

K#

–

BW0#

Write DQ0 to DQ8

Write nothing

L → H

0

1

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[μPD44646184], [μPD44646186]

Operation

K

L → H

–

K#

–

BW0#

BW1#

Write DQ0 to DQ17

Write DQ0 to DQ8

Write DQ9 to DQ17

Write nothing

0

1

0

1

0

1

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD44646364], [μPD44646366]

Operation

K

L → H

–

K#

–

BW0#

BW1#

BW2#

BW3#

Write DQ0 to DQ35

Write DQ0 to DQ8

Write DQ9 to DQ17

Write DQ18 to DQ26

Write DQ27 to DQ35

Write nothing

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Preliminary Data Sheet M18524EJ1V0DS

12

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 4

WRITE DOUBLE

Load, Count = 4

READ DOUBLE

Write

Read

Count = Count + 2

Always

Count = 2

Always

Count = 2

Load

NOP,

Count = 4

ADVANCE ADDRESS

BY TWO

ADVANCE ADDRESS

BY TWO

NOP

Supply voltage provided

Power UP

Remarks 1. Bus cycle is terminated after burst count = 4.

2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R#, W = HIGH); W = (R#, W = LOW).

3. State machine control timing sequence is controlled by K.

13

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol Conditions

MIN.

–0.5

0

TYP.

MAX.

Unit

V

Supply voltage

VDD

VDDQ

VIN

+2.5

Output supply voltage

Input voltage

VDD

VDD + 0.5 (2.5 V MAX.)

VDDQ + 0.5 (2.5 V MAX.)

70

V

Input / Output voltage

Operating ambient temperature

Storage temperature

VI/O

TA

V

°C

Tstg

–55

+125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T^A= 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD

Conditions

MIN.

1.7

TYP.

1.8

MAX.

1.9

Unit

V

Note

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

1.5

1.6

V

1

VREF + 0.1

–0.30

0.68

VDDQ + 0.30

VREF – 0.1

VDDQ + 0.30

0.85

V

1, 2

V

VREF

0.75

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (T^A= 0 to 70°C)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF + 0.2

–

TYP.

MAX.

–

Unit

V

Note

1

VREF – 0.2

V

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Preliminary Data Sheet M18524EJ1V0DS

14

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

x9 x18 x36

+2

Unit Note

Input leakage current

I/O leakage current

Operating supply current

(Read Write cycle)

ILI

–2

–

μA

ILO

IDD

+2

VIN ≤ VIL

-E25 ^Note1

-E27

TBD

mA

100％ read cycles

and

or VIN ≥ VIH,

II/O = 0 mA

Cycle = MAX.

TBD

100％ write cycles

-E30

TBD

-E33

TBD

-E25 ^Note1

TBD

mA

50％ read cycles

and

-E27

TBD

50％ write cycles

-E30

TBD

-E33

TBD

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH,

-E25 ^Note1

TBD

II/O = 0 mA

-E27

TBD

-E30

TBD

-E33

TBD

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note2

VOL(Low) IOL ≤ 0.1 mA

VOL Note3

VDDQ – 0.2

VDDQ/2–0.12

VSS

–

VDDQ

V

4,5

VDDQ/2+0.12

0.2

VDDQ/2–0.12

VDDQ/2+0.12

Notes 1. -E25 is valid for 2.5 Cycle Read Latency products.

2. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

4. AC load current is higher than the shown DC values.

5. HSTL outputs meet JEDEC HSTL Class I standards.

Capacitance (T^A= 25°C, f = 1 MHz)

Parameter

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

Input capacitance (Address, Control)

Input / Output capacitance

(DQ, CQ, CQ#, QVLD)

4

5

pF

CI/O

VI/O = 0 V

Clock Input capacitance

Cclk

Vclk = 0 V

4

pF

Remark These parameters are periodically sampled and not 100% tested.

Thermal Resistance

Parameter

Symbol

θ j-a

Test conditions

MIN.

TYP.

TBD

MAX.

Unit

°C/W

Thermal resistance (junction – ambient)

θ j-c

Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.

15

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

AC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)

AC Test Conditions (V^DD= 1.8 ± 0.1 V, VDDQ = 1.5 ± 0.1 V)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

VDDQ / 2

0.75 V

50 Ω

VREF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Preliminary Data Sheet M18524EJ1V0DS

16

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Read and Write Cycle

Parameter

Symbol

-E25 ^Note1

-E27

-E30

-E33

Unit

Note

(333 MHz)

(400 MHz)

(375 MHz)

(300 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Average Clock cycle time (K, K#)

Clock phase jitter (K, K#)

Clock HIGH time (K, K#)

Clock LOW time (K, K#)

TKHKH

TKC var

TKHKL

TKLKH

ns

2

3

2.5

–

3.25

0.20

–

2.66

–

3.46

0.20

–

3.0

–

3.9

0.20

–

3.3

–

4.2

0.20

–

ns

0.4

TKHKH

–

Clock HIGH to Clock# HIGH

(K → K#)

Clock# HIGH to Clock HIGH

(K# → K)

TKHK#H

TK#HKH

ns

1.06

–

1.13

–

1.28

–

1.40

–

DLL/PLL lock time (K)

TKC lock

4

5

2,048

30

–

2,048

30

–

2,048

30

–

2,048

30

–

Cycle

ns

K static to DLL/PLL reset

TKC reset

Output Times

CQ HIGH to CQ# HIGH (CQ → CQ#)

CQ# HIGH to CQ HIGH (CQ# → CQ)

K, K# HIGH to output valid

K, K# HIGH to output hold

K, K# HIGH to echo clock valid

K, K# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

K HIGH to output High-Z

TCQHCQ#H

TCQ#HCQH

TKHQV

ns

6

0.9

–

0.98

–

1.15

–

1.3

–

0.45

–

0.45

–

0.45

–

0.45

–

TKHQX

– 0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

TKHCQV

TKHCQX

TCQHQV

TCQHQX

TKHQZ

0.45

–

0.45

–

0.45

–

0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

7

0.20

–

0.20

–

0.20

–

0.20

–

– 0.20

–

– 0.20

–

– 0.20

–

– 0.20

–

0.45

–

0.45

–

0.45

–

0.45

–

K HIGH to output Low-Z

TKHQX1

TCQHQVLD

– 0.45

CQ, CQ# HIGH to QVLD valid

– 0.20 0.20 – 0.20 0.20 – 0.20 – 0.20 – 0.20 0.20

Setup Times

Address valid to K rising edge

TAVKH

TIVKH

ns

8

0.4

–

0.4

–

0.4

–

0.4

–

Synchronous load input (LD#), read

write input (R, W#) valid to K rising edge

Data inputs and write data select inputs

(BWx#) valid to K, K# rising edge

TDVKH

ns

8

0.28

–

0.28

–

0.28

–

0.28

–

Hold Times

K rising edge to address hold

TKHAX

TKHIX

ns

8

0.4

–

0.4

–

0.4

–

0.4

–

K rising edge to synchronous load input

(LD#), read write input (R, W#) hold

K, K# rising edge to data inputs and

write data select inputs (BWx#) hold

TKHDX

ns

8

0.28

–

0.28

–

0.28

–

0.28

–

Notes 1. -E25 is valid for 2.5 Cycle Read Latency products.

2. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock

regardless of RL = 2.0 and 2.5 clock products in this operation. The AC/DC characteristics cannot be

guaranteed, however.

3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

4. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.

DLL/PLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.

17

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

5. K input is monitored for this operation. See below for the timing.

K

TKC reset

or

K

6. Guaranteed by design.

7. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

8. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold

times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise

noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. V^DDQ is 1.5 V DC.

Preliminary Data Sheet M18524EJ1V0DS

18

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Read and Write Timing

2.0 Cycle Read Latency

[μPD44646094], [μPD44646184], [μPD44646364]

NOP

READ

NOP

READ

NOP

WRITE

(burst of 4)

1

2

3

4

5

6

7

8

9

10

11

TKHKH

K

TKHKL

TKLKH

TKHK#H

TK#HKH

K#

LD#

TIVKH

TKHIX

R, W#

TKHAX

TAVKH

Address

QVLD

A0

A1

TCQHQVLD

A2

TCQHQVLD

Read Latency = 2.0 clocks

TKHDX

TDVKH

TKHQV

TKHQX

TKHQV

TKHQX

TDVKH

TKHQZ

TKHCQX1

D11

D12

D13

D14

Q20

DQ

Q01 Q02 Q03

Q04

TCQHQX

TCQHQV

TCQHQX

TCQHQV

TKHCQV

TKHCQX

CQ

TCQ#HCQH

TCQHCQ#H

TKHCQV

TKHCQX

CQ#

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (high impedance) 4 clocks after the last READ (LD# = LOW, R, W# = HIGH) is input

in the sequences of [READ]-[NOP].

3. The third NOP cycle between Read to Write transition may not be necessary for correct device

operation when Read latency = 2.0 cycles; however at high frequency operation, it may be required to

avoid bus contention.

19

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

2.5 Cycle Read Latency

[μPD44646096], [μPD44646186], [μPD44646366]

READ

(burst of 4)

WRITE

(burst of 4)

NOP

READ

(burst of 4)

NOP

1

2

3

4

5

6

7

8

9

10

11

TKHKH

K

TKHKL TKLKH

TKLKH

TKHK#H

TK#HKH

K#

LD#

TIVKH

TKHIX

R, W#

TKHAX

TAVKH

Address

QVLD

A0

A1

TCQHQVLD

A2

TCQHQVLD

Read Latency = 2.5 clocks

TKHQV

TKHQX

TKHCQX1

TKHDX

TKHQZ TDVKH

TKHDX

TDVKH

TKHQV

TKHQX

D11

D12

D13

D14

DQ

Q01 Q02 Q03

Q04

TCQHQX

TCQHQV

TCQHQX

TCQHQV

TKHCQV

TKHCQX

CQ

TCQHCQ#H TCQ#HCQH

TKHCQV

TKHCQX

CQ#

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (high impedance) 4.5 clocks after the last READ (LD# = LOW, R, W# = HIGH) is

input in the sequences of [READ]-[NOP].

3. The third NOP cycle between Read to Write transition may not be necessary for correct device

operation when Read latency = 2.5 cycles; however at high frequency operation, it may be required to

avoid bus contention.

Preliminary Data Sheet M18524EJ1V0DS

20

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Application Example

ZQ

CQ#

CQ

ZQ

R =

250 Ω

R =

250 Ω

CQ#

. . .

SRAM#1

SRAM#4

CQ

QVLD

DQ

A

DQ

A

QVLD

LD#

R, W# BWx# K/K#

LD#

R, W#

BWx# K/K#

V

t

SRAM

Controller

R

Data IO

V

t

Address

LD#

R

R, W#

BW#

QVLD

V

t

R

SRAM#1 CQ/CQ#

SRAM#4 CQ/CQ#

V

t

R

Source CLK/CLK#

Return CLK/CLK#

V

t

R

R = 50 Ω V

t

= Vref

Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ#, QVLD and DQ with termination.

21

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

TMS

TDI

10R

11R

Test Mode Select. This is the command input for the TAP controller state machine.

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between TDI and

TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

−5.0

TYP.

MAX.

+5.0

Unit

μA

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

−

ILO

0 V ≤ VIN ≤ VDDQ,

μA

Outputs disabled

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

VIH

VIL

1.3

−0.3

1.6

1.4

−

VDD+0.3

V

+0.5

−

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 μA

| IOHT | = 2 mA

IOLC = 100 μA

IOLT = 2 mA

−

JTAG output LOW voltage

0.2

0.4

−

Preliminary Data Sheet M18524EJ1V0DS

22

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

23

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

JTAG AC Characteristics (T^A= 0 to 70°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

tTHTH

fTF

50

−

20

−

ns

MHz

ns

tTHTL

tTLTH

20

−

ns

Output time

TCK LOW to TDO unknown

TCK LOW to TDO valid

tTLOX

tTLOV

0

−

ns

−

10

Setup time

TMS setup time

TDI valid to TCK HIGH

Capture setup time

tMVTH

tDVTH

tCS

5

−

ns

Hold time

TMS hold time

tTHMX

tTHDX

tCH

5

−

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

tTHTH

TCK

tMVTH

tTHTL

tTLTH

TMS

TDI

tTHMX

tDVTH

tTHDX

tTLOV

tTLOX

TDO

Preliminary Data Sheet M18524EJ1V0DS

24

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

2.0 Cycle Read Latency

Part number

μPD44646094

μPD44646184

μPD44646364

Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 1000 1111

0000 0000 1001 0000

0000 0000 1001 0001

ID [11:1] vendor ID no. ID [0] fix bit

8M x 9

4M x 18

2M x 36

XXXX

00000010000

1

2.5 Cycle Read Latency

Part number

μPD44646096

μPD44646186

μPD44646366

Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 1001 1011

0000 0000 1001 1100

0000 0000 1001 1101

ID [11:1] vendor ID no. ID [0] fix bit

8M x 9

4M x 18

2M x 36

XXXX

00000010000

1

25

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

Bump

ID

no.

x9

x18 x36

no.

x9

x18 x36

no.

x9

x18 x36

NC

1

2

3

4

5

6

7

8

9

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

10D

9E

73

2C

QVLD

74 DQ5 DQ11 DQ20 3E

A

NC DQ7 DQ17 10C

NC NC DQ16 11D

75

76

77

78

79

80

81

NC NC DQ29 2D

NC

2E

1E

NC

9C

9D

NC DQ12 DQ30 2F

NC NC DQ21 3F

43 DQ4 DQ8 DQ8 11B

NC

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

NC

NC DQ7 11C

1G

1F

NC

9B

10B

11A

10A

9A

10 DQ0 DQ0 DQ0 11P

82 DQ6 DQ13 DQ22 3G

11

12

13

14

15

16

17

NC NC DQ9 10P

CQ

A

83

84

85

86

87

88

89

90

NC NC DQ31 2G

NC

10N

9P

DLL#

NC

1H

1J

2J

A

NC

NC DQ1 DQ11 10M

NC NC DQ10 11N

8B

A

NC

LD#

NC

7C

NC DQ14 DQ23 3K

NC NC DQ32 3J

NC

9M

9N

6C

NC

8A

2K

1K

18 DQ1 DQ2 DQ2 11L

NC

NC BW1# 7A

BW0#

K

19

20

21

22

23

24

25

NC NC DQ1 11M

7B

6B

6A

91 DQ7 DQ15 DQ33 2L

NC

9L

92

93

94

95

96

97

98

NC NC DQ24 3L

K#

NC

10L

1M

1L

NC DQ3 DQ3 11K

NC NC DQ12 10K

NC

NC BW3# 5B

NC BW1# BW2# 5A

NC DQ16 DQ25 3N

NC NC DQ34 3M

NC

9J

R, W#

4A

5C

4B

3A

2A

1A

NC

9K

A

1N

2M

26 DQ2 DQ4 DQ13 10J

27

28

29

30

31

32

33

34

NC NC DQ4 11J

A

99 DQ8 DQ17 DQ26 3P

100 NC NC DQ35 2N

ZQ

NC

11H

10G

9G

A

NC

CQ#

101

102

103

104

105

106

107

108

109

2P

1P

NC DQ9 DQ27 2B

NC NC DQ18 3B

NC DQ5 DQ5 11F

NC NC DQ14 11G

A

–

3R

NC

1C

1B

4R

NC

9F

4P

10F

NC DQ10 DQ19 3D

NC NC DQ28 3C

NC

5P

35 DQ3 DQ6 DQ6 11E

36 NC NC DQ15 10E

5N

1D

5R

Internal

Preliminary Data Sheet M18524EJ1V0DS

26

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

When the BYPASS instruction is loaded in the instruction register, the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

27

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Output Pin States of CQ, CQ#, QVLD and DQ

Instructions

Control-Register Status

Output Pin Status

CQ, CQ#, QVLD

DQ

EXTEST

0

1

0

1

0

1

0

1

0

1

Update

SRAM

High-Z

SRAM

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Boundary Scan

Register

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 109).

CAPTURE

Register

There are three statuses:

SRAM

Output

Update : Contents of the “Update Register” are output to the

output pin (QDR Pad).

Update

Register

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG ctrl”.

Update

QDR

Pad

SRAM

Output

Driver

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

Preliminary Data Sheet M18524EJ1V0DS

28

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Boundary Scan Register Status of Output Pins CQ, CQ#, QVLD and DQ

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ, CQ#, QVLD

DQ

Pad

−

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

−

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

No definition

−

Pad

Internal

−

Pad

Internal

Pad

−

No definition

−

Boundary Scan

Register

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

CAPTURE

Register

There are two statuses:

Internal

SRAM

Output

Update

Register

Pad

: Contents of the output pin (QDR Pad) are

captured in the “CAPTURE Register” in the

Boundary Scan Register.

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

29

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix

them to V^DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also

when the TAP controller is not used.

Preliminary Data Sheet M18524EJ1V0DS

30

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Package Drawing

165-PIN PLASTIC BGA (15x17)

B

E

w S

B

ZD

ZE

11

10

9

8

A

7

6

D

5

4

3

2

1

R P N M L K J H G F E D C B A

w

S A

INDEX MARK

A

A2

A1

y1

S

y

e

S

(UNIT:mm)

ITEM DIMENSIONS

M

b

x

S A B

D

E

15.00 0.10

17.00 0.10

0.15

w

e

1.00

A

1.40 0.11

0.40 0.05

1.00

A1

A2

b

0.50 0.05

0.08

x

y

0.10

y1

ZD

ZE

0.20

2.50

1.50

This package drawing is a preliminary version. It may be changed in the future.

33

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD44646094F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646184F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646364F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646096F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646186F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646366F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44646094F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44646184F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44646364F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44646096F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44646186F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44646366F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

Preliminary Data Sheet M18524EJ1V0DS

34

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

35

Preliminary Data Sheet M18524EJ1V0DS

μPD44646094, 44646184, 44646364, 44646096, 44646186, 44646366

QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,

Renesas, IDT, NEC Electronics, and Samsung.

•

The information in this document is current as of November, 2006. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD44646366F5-E33-FQ1-A
厂家：	NEC
描述：	DDR SRAM, 2MX36, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165 双倍数据速率静态存储器
文件：	总36页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44646366F5-E33-FQ1-A [NEC]

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