UPD44647184F5-E27-FQ1

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

μPD44647094,44647184,44647364,44647096,44647186,44647366

72M-BIT QDR^TMII+ SRAM

2.0 & 2.5 Cycle Read Latency

4-WORD BURST OPERATION

Description

The μPD44647094 and μPD44647096 are 8,388,608-word by 9-bit, the μPD44647184 and μPD44647186 are

4,194,304-word by 18-bit and the μPD44647364 and μPD44647366 are 2,097,152-word by 36-bit synchronous quad data

rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The μPD44647xx4 is for 2.0 cycle and the μPD44647xx6 is for 2.5 cycle read latency. The μPD44647094,

μPD44647096, μPD44647184, μPD44647186, μPD44647364 and μPD44647366 integrate unique synchronous

peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on

the positive edge of K and K#.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

Features

• Core (VDD) = 1.8 ± 0.1 V power supply

I/O (V^DDQ) = 1.5 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15x17)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100% bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two Echo clocks (CQ and CQ#)

• Data Valid pin (QVLD) supported

• Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,

2.5 ns (400 MHz) for 2.5 cycle read latency

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M18526EJ1V0DS00 (1st edition)

Date Published November 2006 NS CP(N)

Printed in Japan

2006

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Ordering Information

2.0 Cycle Read Latency

Core

Part number

Cycle

Clock

Organization

(word x bit)

I/O

Package

Supply

Time

ns

Frequency

MHz

375

Voltage

Interface

V

μPD44647094F5-E27-FQ1

μPD44647094F5-E30-FQ1

μPD44647094F5-E33-FQ1

μPD44647184F5-E27-FQ1

μPD44647184F5-E30-FQ1

μPD44647184F5-E33-FQ1

μPD44647364F5-E27-FQ1

μPD44647364F5-E30-FQ1

μPD44647364F5-E33-FQ1

μPD44647094F5-E27-FQ1-A

μPD44647094F5-E30-FQ1-A

μPD44647094F5-E33-FQ1-A

μPD44647184F5-E27-FQ1-A

μPD44647184F5-E30-FQ1-A

μPD44647184F5-E33-FQ1-A

μPD44647364F5-E27-FQ1-A

μPD44647364F5-E30-FQ1-A

μPD44647364F5-E33-FQ1-A

2.66

3.0

8M x 9-bit

4M x 18-bit

2M x 36-bit

8M x 9-bit

4M x 18-bit

2M x 36-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

333

3.3

300

2.66

3.0

375

333

3.3

300

2.66

3.0

375

333

3.3

300

2.66

3.0

375

333

300

375

333

300

375

333

300

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

Lead-free

3.3

2.66

3.0

3.3

2.66

3.0

3.3

Remark Products with -A at the end of the part number are lead-free products.

Preliminary Data Sheet M18526EJ1V0DS

2

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

2.5 Cycle Read Latency

Core

Part number

Cycle

Clock

Organization

(word x bit)

I/O

Package

Supply

Time

ns

Frequency

MHz

400

Voltage

V

Interface

μPD44647096F5-E25-FQ1

μPD44647096F5-E27-FQ1

μPD44647096F5-E30-FQ1

μPD44647096F5-E33-FQ1

μPD44647186F5-E25-FQ1

μPD44647186F5-E27-FQ1

μPD44647186F5-E30-FQ1

μPD44647186F5-E33-FQ1

μPD44647366F5-E25-FQ1

μPD44647366F5-E27-FQ1

μPD44647366F5-E30-FQ1

μPD44647366F5-E33-FQ1

μPD44647096F5-E25-FQ1-A

μPD44647096F5-E27-FQ1-A

μPD44647096F5-E30-FQ1-A

μPD44647096F5-E33-FQ1-A

μPD44647186F5-E25-FQ1-A

μPD44647186F5-E27-FQ1-A

μPD44647186F5-E30-FQ1-A

μPD44647186F5-E33-FQ1-A

μPD44647366F5-E25-FQ1-A

μPD44647366F5-E27-FQ1-A

μPD44647366F5-E30-FQ1-A

μPD44647366F5-E33-FQ1-A

2.5

8M x 9-bit

4M x 18-bit

2M x 36-bit

8M x 9-bit

4M x 18-bit

2M x 36-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

2.66

3.0

375

333

3.3

300

2.5

400

2.66

3.0

375

333

3.3

300

2.5

400

2.66

3.0

375

333

3.3

300

2.5

2.66

3.0

400

375

333

300

400

375

333

300

400

375

333

300

1.8 ± 0.1

HSTL

165-pin PLASTIC

BGA (15x17)

Lead-free

3.3

2.5

2.66

3.0

3.3

2.5

2.66

3.0

3.3

Remarks

Products with -A at the end of the part number are lead-free products.

3

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Feature Differences between QDR II and QDR II+

Features

Frequency (DLL/PLL ON)

Organization

QDR II

120 MHz to 300 MHz

x8 / x9 / x18 / x36

1.8 ± 0.1 V

QDR II+

300 MHz to 400 MHz

x9 / x18 / x36

1.8 ± 0.1 V

Note

VDD

VDDQ

1.8 ± 0.1 V or 1.5 ± 0.1 V

1.5 clocks

1.5 ± 0.1 V

Read Latency (RL)

Input Clocks (K, K#)

Output Clocks (C, C#)

Echo Clock Number (CQ, CQ#)

Package

2.0 & 2.5 clocks

Single Ended (K, K#)

No

1

2

3

Single Ended (K, K#)

Yes

1 Pair

165 (11x15) pin PLASTIC BGA

Yes

165 (11x15) pin PLASTIC BGA

Yes

Individual Byte Write (BWx#)

QVLD

No

Yes

Notes 1. QDR II+ read latency is not user selectable. Offered as two different devices.

2. Echo Clocks are single-ended inputs.

3. Edge aligned with Echo Clocks

Preliminary Data Sheet M18526EJ1V0DS

4

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Pin Configurations

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44647094], [μPD44647096]

8M x 9-bit

1

CQ#

NC

2

3

A

4

5

NC

NC/288M

A

6

K#

7

8

9

A

10

A

11

CQ

Q4

D4

NC

Q3

NC

ZQ

D2

NC

Q1

D1

NC

Q0

TDI

A

B

C

D

E

F

A

NC

D5

W#

R#

NC/144M

BW0#

A

NC

Q5

NC

Q6

VDDQ

NC

D7

NC

Q8

A

K

A

NC

VDDQ

NC

A

NC

D3

NC

VSS

NC

VSS

A

VSS

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

D6

VDDQ

VSS

VDDQ

VSS

NC

VREF

Q2

NC

D0

G

H

J

NC

DLL#

NC

VREF

NC

Q7

K

L

NC

M

N

P

R

NC

D8

NC

VSS

NC

TCK

A

QVLD

NC

A

TDO

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

D0 to D8

Q0 to Q8

R#

TDI

TCK

TDO

V^REF

VDD

W#

: Write input

BW0#

K, K#

CQ, CQ#

ZQ

: Byte Write data select

: Input clock

V^DDQ

V^SS

: Power Supply

: Echo clock

: Ground

: Output impedance matching

: DLL/PLL disable

: Q Valid output

NC

: No connection

DLL#

NC/xxM

: Expansion address for xxMb

QVLD

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 7A and 5B are expansion addresses: 7A for 144Mb and 5B for 288Mb.

5

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44647184], [μPD44647186]

4M x 18-bit

1

CQ#

NC

2

NC/144M

Q9

3

4

5

BW1#

NC

A

6

K#

7

NC/288M

BW0#

A

8

9

A

10

A

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

A

W#

R#

D9

A

K

A

NC

VDDQ

NC

A

NC

Q7

NC

D6

NC

D10

Q10

Q11

D12

Q13

VDDQ

D14

Q14

D15

D16

Q16

Q17

A

VSS

NC

VSS

A

VSS

NC

D11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

Q12

D13

VREF

NC

VREF

Q4

D3

G

H

J

NC

DLL#

NC

K

L

NC

Q15

NC

Q1

NC

D0

M

N

P

R

NC

D17

NC

VSS

NC

A

QVLD

NC

A

TDO

TCK

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

TMS

: IEEE 1149.1 Test input

D0 to D17

Q0 to Q17

R#

TDI

TCK

TDO

V^REF

V^DD

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

W#

: Write input

BW0#, BW1#

K, K#

: Byte Write data select

: Input clock

VDDQ

V^SS

: Power Supply

CQ, CQ#

ZQ

: Echo clock

: Ground

: Output impedance matching

: DLL/PLL disable

: Q Valid output

NC

: No connection

DLL#

NC/xxM

: Expansion address for xxMb

QVLD

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A and 7A are expansion addresses: 2A for 144Mb and 7A for 288Mb.

Preliminary Data Sheet M18526EJ1V0DS

6

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

165-pin PLASTIC BGA (15x17)

(Top View)

[μPD44647364], [μPD44647366]

2M x 36-bit

1

2

3

4

5

BW2#

BW3#

A

6

K#

7

BW1#

BW0#

A

8

9

10

11

CQ

Q8

D8

D7

Q6

Q5

D5

ZQ

D4

Q3

Q2

D2

D1

Q0

TDI

A

B

C

D

E

F

CQ#

Q27

D27

D28

Q29

Q30

D30

DLL#

D31

Q32

Q33

D33

D34

Q35

TDO

A

W#

R#

A

NC/288M

Q18

Q28

D20

D29

Q21

D22

VREF

Q31

D32

Q24

Q34

D26

D35

TCK

NC/144M

Q17

Q7

D18

D19

Q19

Q20

D21

Q22

VDDQ

D23

Q23

D24

D25

Q25

Q26

A

K

A

D17

D16

Q16

Q15

D14

Q13

VDDQ

D12

Q12

D11

D10

Q10

Q9

VSS

NC

VSS

A

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

D15

D6

VDDQ

VSS

VDDQ

VSS

Q14

D13

VREF

Q4

G

H

J

K

L

D3

Q11

Q1

M

N

P

R

VSS

D9

A

QVLD

NC

A

D0

A

TMS

A

: Address inputs

: Data inputs

: Data outputs

: Read input

TMS

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

D0 to D35

Q0 to Q35

R#

TDI

TCK

TDO

V^REF

VDD

W#

: Write input

BW0# to BW3#

K, K#

: Byte Write data select

: Input clock

V^DDQ

V^SS

: Power Supply

CQ, CQ#

ZQ

: Echo clock

: Ground

: Output impedance matching

: DLL/PLL disable

: Q Valid output

NC

: No connection

DLL#

NC/xxM

: Expansion address for xxMb

QVLD

Remarks 1. ×××# indicates active LOW signal.

2. Refer to Package Drawing for the index mark.

3. 2A and 10A are expansion addresses: 10A for 144Mb and 2A for 288Mb.

7

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Pin Identification

Symbol

Description

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These

inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).

D0 to Dxx

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#

during WRITE operations. See Pin Configurations for ball site location of individual signals.

x9 device uses D0 to D8.

x18 device uses D0 to D17.

x36 device uses D0 to D35.

Q0 to Qxx

Synchronous Data Outputs: Output data is synchronized to the respective K and K# rising edges. Data is output

in synchronization with K and K#, depending on the R# command. See Pin Configurations for ball site location

of individual signals.

x9 device uses Q0 to Q8.

x18 device uses Q0 to Q17.

x36 device uses Q0 to Q35.

R#

Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a READ command (R# =

LOW) is input, an input of R# on the subsequent rising edge of K is ignored.

W#

Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be

initiated. This input must meet setup and hold times around the rising edge of K. If a WRITE command (W# =

LOW) is input, an input of W# on the subsequent rising edge of K is ignored.

BWx#

Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and written

during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K# for

each of the two rising edges comprising the WRITE cycle. See Pin Configurations for signal to data

relationships.

x9 device uses BW0#.

x18 device uses BW0#, BW1#.

x36 device uses BW0# to BW3#.

See Byte Write Operation for relation between BWx#, and Dxx.

K, K#

CQ, CQ#

ZQ

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All

synchronous inputs must meet setup and hold times around the clock rising edges.

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates. If K and K# are stopped, CQ and CQ# will also stop.

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. Q, CQ, CQ# and QVLD output impedance are set to 0.2 x RQ, where RQ is a resistor from this

bump to ground. The output impedance can be minimized by directly connect ZQ to V^DDQ. This pin cannot be

connected directly to GND or left unconnected. The output impedance is adjusted every 1,024 cycles upon

power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new output

impedance is reset by implementing power-on sequence.

DLL#

DLL/PLL Disable: When DLL# is LOW, the operation can be performed at a clock frequency slower than

TKHKH (MAX.) without the DLL/PLL circuit being used. The AC/DC characteristics cannot be guaranteed. For

normal operation, DLL# must be HIGH and it can be connected to V^DDQ through a 10 kΩ or less resistor.

QVLD

Q valid Output: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ#.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

VREF

VDD

IEEE 1149.1 Test Output: 1.8 V I/O level.

HSTL Input Reference Voltage: Nominally V^DDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for

range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. See Recommended DC Operating Conditions

and DC Characteristics for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are not connected internally.

Preliminary Data Sheet M18526EJ1V0DS

8

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Block Diagram

[μPD44647094], [μPD44647096]

21

ADDRESS

R#

21

ADDRESS

REGISTRY

W#

& LOGIC

K

W#

MUX

BW0#

9

2

18

Q0 to Q8

36

DATA

REGISTRY

& LOGIC

2²¹x 36

MEMORY

ARRAY

9

D0 to D8

R#

18

K

CQ,

CQ#

K

QVLD

K, K#

K#

[μPD44647184], [μPD44647186]

20

ADDRESS

R#

20

ADDRESS

REGISTRY

W#

& LOGIC

K

W#

MUX

BW0#

36

18

BW1#

D0 to D17

R#

Q0 to Q17

72

DATA

REGISTRY

& LOGIC

2

²⁰x 72

MEMORY

18

ARRAY

2

36

K

CQ,

CQ#

K

QVLD

K, K#

K#

[μPD44647364], [μPD44647366]

19

ADDRESS

R#

19

ADDRESS

REGISTRY

W#

& LOGIC

K

W#

MUX

BW0#

BW1#

BW2#

72

36

2

Q0 to Q35

¹⁹x 144

144

DATA

2

BW3#

REGISTRY

MEMORY

ARRAY

36

& LOGIC

D0 to D35

CQ,

CQ#

R#

K

QVLD

K, K#

K#

9

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Power-On Sequence in QDR II+ SRAM

QDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

The following power-up supply voltage application is recommended: V^SS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ

can be applied simultaneously, as long as V^DDQ does not exceed VDD by more than 0.5 V during power-up. The

following power-down supply voltage removal sequence is recommended: V^IN, VREF, VDDQ, VDD, VSS. VDD and VDDQ

can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.

Power-On Sequence

Apply power and tie DLL# to HIGH.

- Apply V^DDbefore VDDQ.

- Apply V^DDQ before VREF or at the same time as VREF.

Provide stable clock for more than 2,048 cycles to lock the DLL/PLL.

DLL/PLL Constraints

The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified

as TKC var. The DLL/PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the

DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.

Power-On Waveforms

VDD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

DLL#

Clock

Fix HIGH (or tied to V^DDQ)

2,048 cycles or more

Unstable Clock

Normal Operation

Start

Stable Clock

Preliminary Data Sheet M18526EJ1V0DS

10

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Truth Table

2.0 Cycle Read Latency

[μPD44647094], [μPD44647184], [μPD44647364]

Operation

CLK

R#

H

W#

L

D or Q

WRITE cycle

L → H

Data in

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

Input clock

DA(A+0)

DA(A+1)

DA(A+2)

DA(A+3)

K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑

L → H

L

X

Data out

Load address, read data on two

consecutive K and K# rising edge

NOP (No operation)

Output data

Output clock

QA(A+0)

QA(A+1)

QA(A+2)

QA(A+3)

K(t+2) ↑ K#(t+2) ↑ K(t+3) ↑ K#(t+3) ↑

L → H

H

X

H

X

D = X, Q = High-Z

Previous state

Clock stop

Stopped

2.5 Cycle Read Latency

[μPD44647096], [μPD44647186], [μPD44647366]

Operation

CLK

R#

H

W#

L

D or Q

Data in

WRITE cycle

L → H

Load address, input write data on two

consecutive K and K# rising edge

READ cycle

Input data

DA(A+0)

DA(A+1)

DA(A+2)

DA(A+3)

Input clock

Data out

K(t+1) ↑ K#(t+1) ↑ K(t+2) ↑ K#(t+2) ↑

L → H

L

X

Load address, read data on two

consecutive K and K# rising edge

NOP (No operation)

Output data

QA(A+0)

QA(A+1)

QA(A+2)

QA(A+3)

Output clock K#(t+2) ↑ K(t+3) ↑ K#(t+3) ↑ K(t+4) ↑

D = X, Q = High-Z

L → H

H

X

H

X

Clock stop

Stopped

Previous state

Remarks

Remarks listed below are for both products with 2.0 and 2.5 Cycle Read Latency.

1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.

3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at

the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart

by overcoming transmission line charging symmetrically.

7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation

however it is strongly recommended that this signal is brought HIGH as shown in the truth table.

8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating

consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The

device will ignore the second request.

11

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Byte Write Operation

[μPD44647094], [μPD44647096]

Operation

K

K#

–

BW0#

Write D0 to D8

Write nothing

L → H

0

1

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE

operation provided that the setup and hold requirements are satisfied.

[μPD44647184], [μPD44647186]

Operation

K

L → H

–

K#

–

BW0#

BW1#

Write D0 to D17

Write D0 to D8

Write D9 to D17

Write nothing

0

1

0

1

0

1

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

[μPD44647364], [μPD44647366]

Operation

K

K#

–

BW0#

BW1#

BW2#

BW3#

Write D0 to D35

Write D0 to D8

Write D9 to D17

Write D18 to D26

Write D27 to D35

Write nothing

L → H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remarks 1. H : HIGH, L : LOW, → : rising edge.

2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST

WRITE operation provided that the setup and hold requirements are satisfied.

Preliminary Data Sheet M18526EJ1V0DS

12

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Bus Cycle State Diagram

LOAD NEW

READ ADDRESS;

R_Count = 0;

R_Init = 1

LOAD NEW

WRITE ADDRESS;

W_Count = 0

Always

W# = LOW & W_Count = 4

R# = LOW & R_Count = 4

Always

WRITE DOUBLE;

READ DOUBLE;

W_Count = W_Count+2

R_Count = R_Count+2

R# = HIGH

& R_Count = 4

W# = LOW

R_Init = 0

W_Count = 2

Always

R_Count = 2

Always

R# = LOW

W# = HIGH

& W_Count = 4

INCREMENT READ

ADDRESS BY TWO

R_Init = 0

INCREMENT WRITE

ADDRESS BY TWO

R# = HIGH

W# = HIGH

READ PORT NOP

R_Init = 0

WRITE PORT NOP

Power UP

Supply voltage

provided

Supply voltage

provided

Remarks 1. The address is concatenated with two additional internal LSBs to facilitate burst operation.

The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3.

Bus cycle is terminated at the end of this sequence (burst count = 4).

2. Read and write state machines can be active simultaneously.

Read and write cannot be simultaneously initiated. Read takes precedence.

3. State machine control timing is controlled by K.

13

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol Conditions

MIN.

–0.5

0

TYP.

MAX.

Unit

V

Supply voltage

VDD

VDDQ

VIN

+2.5

Output supply voltage

Input voltage

VDD

VDD + 0.5 (2.5 V MAX.)

VDDQ + 0.5 (2.5 V MAX.)

70

V

Input / Output voltage

Operating ambient temperature

Storage temperature

VI/O

TA

V

°C

Tstg

–55

+125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T^A= 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD

Conditions

MIN.

1.7

TYP.

1.8

MAX.

1.9

Unit

V

Note

Output supply voltage

Input HIGH voltage

Input LOW voltage

Clock input voltage

Reference voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

1.5

1.6

V

1

VREF + 0.1

–0.30

0.68

VDDQ + 0.30

VREF – 0.1

VDDQ + 0.30

0.85

V

1, 2

V

VREF

0.75

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (T^A= 0 to 70°C)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF + 0.2

–

TYP.

MAX.

–

Unit

V

Note

1

VREF – 0.2

V

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Preliminary Data Sheet M18526EJ1V0DS

14

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

x9 x18 x36

+2

Unit Note

Input leakage current

ILI

–2

–

μA

I/O leakage current

Operating supply current

(Read Write cycle)

ILO

IDD

+2

VIN ≤ VIL

-E25 ^Note1

-E27

TBD

VDDQ

mA

100％ read cycles

and

or VIN ≥ VIH,

II/O = 0 mA

Cycle = MAX.

100％ write cycles

-E30

-E33

-E25 ^Note1

mA

50％ read cycles

and

-E27

50％ write cycles

-E30

-E33

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH,

-E25 ^Note1

II/O = 0 mA

-E27

-E30

-E33

Output HIGH voltage

Output LOW voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note2

VDDQ – 0.2

VDDQ/2–0.12

VSS

–

V

4,5

VDDQ/2+0.12

0.2

VOL(Low) IOL ≤ 0.1 mA

VOL Note3

VDDQ/2–0.12

VDDQ/2+0.12

Notes 1. -E25 is valid for 2.5 Cycle Read Latency products.

2. Outputs are impedance-controlled. | I^OH| = (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.

4. AC load current is higher than the shown DC values.

5. HSTL outputs meet JEDEC HSTL Class I standards.

Capacitance (T^A= 25°C, f = 1 MHz)

Parameter

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

pF

Input capacitance (Address, Control)

Input / Output capacitance

(D, Q, CQ, CQ#, QVLD)

4

5

CI/O

VI/O = 0 V

pF

Clock Input capacitance

Cclk

Vclk = 0 V

4

pF

Remark These parameters are periodically sampled and not 100% tested.

Thermal Resistance

Parameter

Symbol

θ j-a

Test conditions

MIN.

TYP.

TBD

MAX.

Unit

°C/W

Thermal resistance (junction – ambient)

Thermal resistance (junction – case)

θ j-c

Remark These parameters are simulated under the condition of air flow velocity = 1 m/s.

15

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

AC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)

AC Test Conditions (V^DD= 1.8 ± 0.1 V, VDDQ = 1.5 ± 0.1 V)

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

Test Points

0.25 V

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

V

DDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Preliminary Data Sheet M18526EJ1V0DS

16

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Read and Write Cycle

Parameter

Symbol

-E25 ^Note1

-E27

-E30

-E33

Unit

Note

(333 MHz)

(400 MHz)

(375 MHz)

(300 MHz)

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Average Clock cycle time (K, K#)

Clock phase jitter (K, K#)

Clock HIGH time (K, K#)

Clock LOW time (K, K#)

TKHKH

TKC var

TKHKL

TKLKH

ns

2

3

2.5

–

3.25

0.20

–

2.66

–

3.46

0.20

–

3.0

–

3.9

0.20

–

3.3

–

4.2

0.20

–

ns

0.4

TKHKH

–

Clock HIGH to Clock# HIGH

(K → K#)

Clock# HIGH to Clock HIGH

(K# → K)

TKHK#H

TK#HKH

ns

1.06

–

1.13

–

1.28

–

1.40

–

DLL/PLL lock time (K)

TKC lock

4

5

2,048

30

–

2,048

30

–

2,048

30

–

2,048

30

–

Cycle

ns

K static to DLL/PLL reset

TKC reset

Output Times

CQ HIGH to CQ# HIGH (CQ → CQ#) TCQHCQ#H

CQ# HIGH to CQ HIGH (CQ# → CQ) TCQ#HCQH

ns

6

0.9

–

0.98

–

1.15

–

1.3

–

0.45

–

K, K# HIGH to output valid

K, K# HIGH to output hold

K, K# HIGH to echo clock valid

K, K# HIGH to echo clock hold

CQ, CQ# HIGH to output valid

CQ, CQ# HIGH to output hold

K HIGH to output High-Z

TKHQV

TKHQX

–

0.45

–

0.45

–

0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

TKHCQV

TKHCQX

TCQHQV

TCQHQX

TKHQZ

0.45

–

0.45

–

0.45

–

0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

– 0.45

–

7

0.20

–

0.20

–

0.20

–

0.20

–

– 0.20

–

– 0.20

–

– 0.20

–

– 0.20

–

0.45

–

0.45

–

0.45

–

0.45

–

K HIGH to output Low-Z

TKHQX1

TCQHQVLD

– 0.45

CQ, CQ# HIGH to QVLD valid

– 0.20 0.20 – 0.20 0.20 – 0.20 – 0.20 – 0.20 0.20

Setup Times

Address valid to K rising edge

TAVKH

TIVKH

ns

8

0.4

–

0.4

–

0.4

–

0.4

–

Control inputs (R#, W#) valid to K

rising edge

Data inputs and write data select

inputs (BWx#) valid to

K, K# rising edge

TDVKH

ns

8

0.28

–

0.28

–

0.28

–

0.28

–

Hold Times

K rising edge to address hold

TKHAX

TKHIX

ns

8

0.4

–

0.4

–

0.4

–

0.4

–

K rising edge to control inputs (R#,

W#) hold

K, K# rising edge to data inputs and

write data select inputs (BWx#) hold

TKHDX

ns

8

0.28

–

0.28

–

0.28

–

0.28

–

Notes 1. -E25 is valid for 2.5 Cycle Read Latency products.

2. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock

regardless of RL = 2.0 and 2.5 clock products in this operation. The AC/DC characteristics cannot be

guaranteed, however.

3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

4. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention.

DLL/PLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.

17

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

5. K input is monitored for this operation. See below for the timing.

K

TKC reset

or

K

6. Guaranteed by design.

7. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

8. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. V^DDQ is 1.5 V DC.

Preliminary Data Sheet M18526EJ1V0DS

18

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Read and Write Timing

2.0 Cycle Read Latency

[μPD44647094], [μPD44647184], [μPD44647364]

Remarks 1. Q00 refers to output from address A0+0.

Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.

2. Outputs are disabled (high impedance) 4.0 clocks after the last READ (R# = LOW) is input in the

sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].

3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.

Write data is forwarded immediately as read results. This remark applies to whole diagram.

19

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

2.5 Cycle Read Latency

[μPD44647096], [μPD44647186], [μPD44647366]

Remarks 1. Q00 refers to output from address A0+0.

Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.

2. Outputs are disabled (high impedance) 4.5 clocks after the last READ (R# = LOW) is input in the

sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].

3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.

Write data is forwarded immediately as read results. This remark applies to the whole diagram.

Preliminary Data Sheet M18526EJ1V0DS

20

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Application Example

R =

ZQ

250 Ω

CQ#

CQ

Q

QVLD

CQ

Q

SRAM#1

SRAM#4

. . .

D

A

D

QVLD

R#

W# BWx# K/K#

A

R# W# BWx# K/K#

Vt

SRAM

Controller

R

Data In

Vt

Data Out

Address

R#

R

V

t

R

W#

BW#

QVLD

Vt

R

SRAM#1 CQ/CQ#

V

t

R

SRAM#4 CQ/CQ#

V

t

Source CLK/CLK#

Return CLK/CLK#

Vt

R

R = 50 Ω V = Vref

t

Remark AC specifications are defined at the condition of SRAM outputs, CQ, CQ#, QVLD and Q with termination.

21

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

Test Mode Select. This is the command input for the TAP controller state machine.

TMS

TDI

10R

11R

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. This is the output side of the serial registers placed between TDI and

TDO. Output changes in response to the falling edge of TCK.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

−5.0

TYP.

MAX.

+5.0

Unit

μA

−

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

ILO

0 V ≤ VIN ≤ VDDQ,

μA

Outputs disabled

−

JTAG input HIGH voltage

JTAG input LOW voltage

JTAG output HIGH voltage

VIH

VIL

1.3

−0.3

1.6

1.4

−

VDD+0.3

V

+0.5

−

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 μA

| IOHT | = 2 mA

IOLC = 100 μA

IOLT = 2 mA

−

JTAG output LOW voltage

0.2

0.4

−

Preliminary Data Sheet M18526EJ1V0DS

22

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

23

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

JTAG AC Characteristics (TA = 0 to 70°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Clock

−

20

−

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

tTHTH

fTF

50

−

ns

MHz

ns

tTHTL

tTLTH

20

−

ns

Output time

−

TCK LOW to TDO unknown

TCK LOW to TDO valid

tTLOX

tTLOV

0

ns

−

10

Setup time

−

TMS setup time

TDI valid to TCK HIGH

Capture setup time

tMVTH

tDVTH

tCS

5

ns

Hold time

−

TMS hold time

tTHMX

tTHDX

tCH

5

ns

TCK HIGH to TDI invalid

Capture hold time

JTAG Timing Diagram

tTHTH

TCK

tMVTH

tTHTL

tTLTH

TMS

TDI

tTHMX

tDVTH

tTHDX

tTLOV

tTLOX

TDO

Preliminary Data Sheet M18526EJ1V0DS

24

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

2.0 Cycle Read Latency

Part number

μPD44647094

μPD44647184

μPD44647364

Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 1001 0101

0000 0000 1001 0110

0000 0000 1001 0111

ID [11:1] vendor ID no. ID [0] fix bit

8M x 9

4M x 18

2M x 36

XXXX

00000010000

1

2.5 Cycle Read Latency

Part number

μPD44647096

μPD44647186

μPD44647366

Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 1010 0001

0000 0000 1010 0010

0000 0000 1010 0011

ID [11:1] vendor ID no. ID [0] fix bit

8M x 9

4M x 18

2M x 36

XXXX

00000010000

1

25

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

SCAN Exit Order

Bit

Signal name

Bump

ID

Bit

Signal name

x9 x18 x36

Bump

ID

Bit

Signal name

Bump

ID

no.

x9

x18 x36

no.

x9

x18

x36

1

2

3

4

5

6

7

8

9

NC

6R

6P

6N

7P

7N

7R

8R

8P

9R

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

NC

Q4

D4

NC D15 10D

NC Q15 9E

73

74

NC

Q5

D5

NC

NC Q28

Q11 Q20

D11 D20

2C

3E

2D

2E

1E

2F

3F

1G

1F

3G

2G

1H

1J

QVLD

A

Q7

D7

Q7 10C

D7 11D

75

76

NC

D29

NC D16 9C

NC Q16 9D

77

NC Q29

78

NC Q12 Q21

Q8

D8

Q8 11B

D8 11C

79

NC

Q6

D6

D12 D21

NC D30

80

NC

NC D17

9B

81

NC Q30

Q13 Q22

D13 D22

DLL#

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

Q0

D0

Q0

D0

Q0 11P

D0 10P

D9 10N

NC Q17 10B

82

CQ

A

11A

83

NC NC

A

NC 10A

84

Q9

9P

A

9A

8B

7C

6C

8A

85

NC

D31

NC

Q1

D1

Q1 10M

D1 11N

A

86

NC Q31

2J

A

87

NC Q14 Q23

3K

3J

NC NC D10 9M

NC NC Q10 9N

NC

R#

88

NC

Q7

D7

NC

D14 D23

NC D32

89

2K

1K

2L

3L

1M

1L

3N

3M

1N

Q1

Q2

D2 11M

9L

NC NC Q11 10L

11L

NC

NC BW1# 7A

90

NC Q32

Q15 Q24

D15 D24

D1

D2

BW0#

K

7B

6B

6A

91

NC NC D11

92

K#

93

NC

D33

NC

Q3

D3

Q3 11K

D3 10K

NC BW3# 5B

94

NC Q33

NC BW1# BW2# 5A

95

NC Q16 Q25

NC NC D12

9J

W#

A

4A

5C

4B

3A

2A

1A

96

NC

Q8

D8

NC

D16 D25

NC D34

NC NC Q12 9K

97

Q2

D2

Q4

D4

ZQ

Q4

D4

10J

11J

11H

A

98

NC Q34 2M

A

99

Q17 Q26

D17 D26

3P

2N

A

NC

CQ#

NC

100

101

102

103

104

105

106

107

108

109

NC NC D13 10G

NC NC Q13 9G

NC

D35

2P

NC

Q9 Q18 2B

D9 D18 3B

NC Q35

1P

NC

Q5

D5

Q5 11F

D5 11G

A

–

3R

NC D27 1C

NC Q27 1B

4R

NC NC D14

9F

4P

NC NC Q14 10F

NC Q10 Q19 3D

NC D10 D19 3C

5P

Q3

D3

Q6

D6

Q6 11E

D6 10E

5N

NC

NC D28 1D

5R

Internal

Preliminary Data Sheet M18526EJ1V0DS

26

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

When the BYPASS instruction is loaded in the instruction register, the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

0

1

IDCODE

0

1

0

SAMPLE-Z

1

2

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

2

1

0

1

Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

27

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Output Pin States of CQ, CQ#, QVLD and Q

Instructions

Control-Register Status

Output Pin Status

CQ, CQ#, QVLD

Q

EXTEST

0

1

0

1

0

1

0

1

0

1

Update

SRAM

High-Z

SRAM

High-Z

Update

SRAM

High-Z

SRAM

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

Register, bit no. 109).

Boundary Scan

Register

CAPTURE

Register

There are three statuses:

Update : Contents of the “Update Register” are output to

the output pin (QDR Pad).

Update

Register

SRAM

Output

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG

ctrl”.

Update

QDR

Pad

SRAM

Output

Driver

High-Z

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

High-Z

JTAG ctrl

Preliminary Data Sheet M18526EJ1V0DS

28

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Boundary Scan Register Status of Output Pins CQ, CQ#, QVLD and Q

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ, CQ#, QVLD

Q

Pad

–

EXTEST

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

READ (Low-Z)

NOP (High-Z)

Pad

–

IDCODE

SAMPLE-Z

SAMPLE

BYPASS

No definition

–

Pad

Internal

–

Pad

Internal

Pad

–

No definition

–

Boundary Scan

Register

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

CAPTURE

Register

There are two statuses:

Internal

SRAM

Output

Update

Register

Pad

: Contents of the output pin (QDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Register.

Pad

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

29

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open but fix

them to V^DDvia a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected also

when the TAP controller is not used.

Preliminary Data Sheet M18526EJ1V0DS

30

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Package Drawing

165-PIN PLASTIC BGA (15x17)

B

E

w S

B

ZD

ZE

11

10

9

8

A

7

6

D

5

4

3

2

1

R P N M L K J H G F E D C B A

w

S A

INDEX MARK

A

A2

A1

y1

S

y

e

S

(UNIT:mm)

ITEM DIMENSIONS

M

b

x

S A B

D

E

15.00 0.10

17.00 0.10

0.15

w

e

1.00

A

1.40 0.11

0.40 0.05

1.00

A1

A2

b

0.50 0.05

0.08

x

y

0.10

y1

ZD

ZE

0.20

2.50

1.50

This package drawing is a preliminary version. It may be changed in the future.

33

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

μPD44647094F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647184F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647364F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647096F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647186F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647366F5-FQ1 : 165-pin PLASTIC BGA (15x17)

μPD44647094F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44647184F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44647364F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44647096F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44647186F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

μPD44647366F5-FQ1-A : 165-pin PLASTIC BGA (15x17)

Preliminary Data Sheet M18526EJ1V0DS

34

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

35

Preliminary Data Sheet M18526EJ1V0DS

μPD44647094, 44647184, 44647364, 44647096, 44647186, 44647366

QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,

Renesas, IDT, NEC Electronics, and Samsung.

•

The information in this document is current as of November, 2006. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD44647184F5-E27-FQ1
厂家：	NEC
描述：	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165 静态存储器
文件：	总36页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44647184F5-E27-FQ1 [NEC]

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