UPD4481162GF-C50 [NEC]
512KX16 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100;
| 型号： | UPD4481162GF-C50 |
| 厂家： | 
NEC |
| 描述： | 512KX16 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100 静态存储器 内存集成电路 |
| 文件： | 总40页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4481162, 4481182, 4481322, 4481362
8M-BIT ZEROSBTM SRAM
PIPELINED OPERATION
Description
The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a
262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness or 165-pin TAPE FBGA for high density and low capacitive loading.
Features
• Low voltage core supply (A version : VDD = 3.3 ± 0.165V, C version : VDD = 2.5 ± 0.125V)
• Synchronous operation
• 100 percent bus utilization
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• All registers triggered off positive clock edge
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 - /BW4 (µPD4481322 and µPD4481362), /BW1 - /BW2 (µPD4481162 and µPD4481182)
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15562EJ1V0DS00 (1st edition)
Date Published June 2001 NS CP(K)
Printed in Japan
2001
©
µPD4481162, 4481182, 4481322, 4481362
Ordering Information
(1/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Package
µPD4481162GF-A50
µPD4481162GF-A60
µPD4481162GF-A75
µPD4481182GF-A50
µPD4481182GF-A60
µPD4481182GF-A75
µPD4481322GF-A50
µPD4481322GF-A60
µPD4481322GF-A75
µPD4481362GF-A50
µPD4481362GF-A60
µPD4481362GF-A75
µPD4481162GF-C50
µPD4481162GF-C60
µPD4481162GF-C75
µPD4481182GF-C50
µPD4481182GF-C60
µPD4481182GF-C75
µPD4481322GF-C50
µPD4481322GF-C60
µPD4481322GF-C75
µPD4481362GF-C50
µPD4481362GF-C60
µPD4481362GF-C75
µPD4481162F9-A50-EQx
µPD4481162F9-A60-EQx
µPD4481162F9-A75-EQx
µPD4481182F9-A50-EQx
µPD4481182F9-A60-EQx
µPD4481182F9-A75-EQx
µPD4481322F9-A50-EQx
µPD4481322F9-A60-EQx
µPD4481322F9-A75-EQx
µPD4481362F9-A50-EQx
µPD4481362F9-A60-EQx
µPD4481362F9-A75-EQx
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
3.3 ± 0.165
2.5 ± 0.125
3.3 ± 0.165
3.3 V or 2.5 V
LVTTL
100-pin PLASTIC LQFP
(14 x 20)
2.5 V
LVTTL
3.3 V or 2.5 V
LVTTL
165-pin TAPE FBGA
(13 x 15)
Remark "EQx" of part number is package specifications. However, this is not available.
2
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Package
µPD4481162F9-C50-EQx
µPD4481162F9-C60-EQx
µPD4481162F9-C75-EQx
µPD4481182F9-C50-EQx
µPD4481182F9-C60-EQx
µPD4481182F9-C75-EQx
µPD4481322F9-C50-EQx
µPD4481322F9-C60-EQx
µPD4481322F9-C75-EQx
µPD4481362F9-C50-EQx
µPD4481362F9-C60-EQx
µPD4481362F9-C75-EQx
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
200
167
133
200
167
133
200
167
133
200
167
133
2.5 ± 0.125
2.5 V
165-pin TAPE FBGA
(13 x 15)
LVTTL
Remark "EQx" of part number is package specifications. However, this is not available.
3
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 × 20)
[µPD4481162GF, µPD4481182GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
2
3
V
DDQ
4
VDDQ
V
SSQ
5
V
SSQ
NC
NC
6
NC
7
I/OP1, NC
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O11
I/O12
I/O6
I/O5
V
V
V
DD
DD
DD
V
V
V
SS
DD
DD
V
SS
ZZ
I/O13
I/O14
I/O4
I/O3
V
DD
Q
Q
V
V
DD
Q
V
SS
SSQ
I/O15
I/O16
I/O2
I/O1
NC
I/OP2, NC
NC
NC
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for 1-pin index mark.
4
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Pin Identifications
[µPD4481162GF, µPD4481182GF]
Symbol
Pin No.
Description
A0 - A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46, 47, 48, 49, 50, 83, 80
Synchronous Address Input
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, NCNote
I/OP2, NCNote
ADV
74
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
24
85
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1, /BW2
/G
93, 94
86
CLK
89
/CKE
87
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
31
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection
51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96
Note NC (No Connection) is used in the µPD4481162GF.
I/OP1 - I/OP2 are used in the µPD4481182GF.
5
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
100-pin PLASTIC LQFP (14 × 20)
[µPD4481322GF, µPD4481362GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
2
I/O18
3
I/O15
V
DD
Q
Q
4
V
DD
SS
Q
V
SS
5
V
Q
I/O19
I/O20
I/O21
I/O22
6
I/O14
I/O13
I/O12
I/O11
7
8
9
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
Q
VDD
VDD
Q
I/O23
I/O24
I/O10
I/O9
VDD
VDD
VDD
VSS
VDD
VDD
VSS
ZZ
I/O25
I/O26
I/O8
I/O7
V
DD
Q
Q
V
DD
SS
Q
V
SS
V
Q
I/O27
I/O28
I/O29
I/O30
I/O6
I/O5
I/O4
I/O3
V
SS
Q
Q
VSS
Q
VDD
VDD
Q
I/O31
I/O32
I/O2
I/O1
I/OP4, NC
I/OP1, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawings for 1-pin index mark.
6
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[µPD4481322GF, µPD4481362GF]
Symbol
Pin No.
Description
A0 - A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
85
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
/CE, CE2, /CE2
/WE
98, 97, 92
88
/BW1 - /BW4
/G
93, 94, 95, 96
86
89
87
31
CLK
/CKE
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
Power Supply
MODE
ZZ
64
VDD
VSS
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
38, 39, 42, 43, 84
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4481322GF.
I/OP1 - I/OP4 are used in the µPD4481362GF.
7
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
165-pin TAPE FBGA
[µPD4481162F9-EQx, µPD4481182F9-EQx]
Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC
NC
A7
A6
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BW2
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
NC
/BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
/CKE
/WE
VSS
ADV
/G
A17
NC
A8
A9
A18
NC
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A10
A11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
I/OP1
I/O8
I/O7
I/O6
I/O5
ZZ
NC
I/O9
I/O10
I/O11
I/O12
VDD
NC
VSS
NC
NC
VSS
NC
NC
VSS
NC
G
H
J
NC
VSS
NC
NC
VSS
NC
I/O13
I/O14
I/O15
I/O16
I/OP2
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O4
I/O3
I/O2
I/O1
NC
NC
K
L
NC
VSS
NC
NC
VSS
NC
M
N
P
R
NC
VSS
NC
NC
VDD
TDO
TCK
NC
NC
TDI
TMS
A14
A15
NC
MODE
NC
A4
A3
A0
A12
A16
8
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[µPD4481162F9-EQx, µPD4481182F9-EQx]
Symbol Pin No.
Description
A0 - A18
6R, 6P, 4P, 4R, 3R, 3P, 2B, 2A, 10A, 10B, 8P, Synchronous Address Input
8R, 9R, 9P, 10P, 10R, 11R, 9A, 11A
I/O1 - I/O16
10M, 10L, 10K, 10J, 11G, 11F, 11E, 11D, 2D,
Synchronous Data In,
2E, 2F, 2G, 1J, 1K, 1L, 1M
11C
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1, NCNote
I/OP2, NCNote
ADV
1N
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
8A
/CE, CE2, /CE2
/WE
3A, 3B, 6A
4H
/BW1, /BW2
/G
5B, 4A
8B
CLK
6B
/CKE
7A
Synchronous Clock Enable Input
MODE
1R
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
ZZ
11H
VDD
2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 7N, 8D, Power Supply
8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M
VSS
4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M, Ground
6C, 6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D,
7E, 7F, 7G, 7H, 7J, 7K, 7L, 7M, 8C, 8N
VDDQ
NC
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, Output Buffer Power Supply
9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N
1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1P, 2C, 2J, 2K, No Connection
2L, 2M, 2N, 2P, 2R, 3H, 4B, 5A, 5N, 6N, 9B, 9H,
10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J,
11K, 11L, 11M, 11N, 11P
TMS
TDI
5R
5P
7R
7P
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
TCK
TDO
Note NC (No Connection) is used in the µPD4481162F9-EQx.
I/OP1 - I/OP2 are used in the µPD4481182F9-EQx .
9
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
165-pin TAPE FBGA
[µPD4481322F9-EQx, µPD4481362F9-EQx]
Top View
1
2
3
4
5
6
7
8
9
10
11
NC
NC
A7
A6
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
/BW3
/BW4
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
/BW2
/BW1
VSS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
/CKE
/WE
VSS
ADV
/G
A17
NC
A8
A9
NC
NC
A
B
C
D
E
F
I/OP3
I/O18
I/O20
I/O22
I/O24
NC
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A10
A11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
I/OP2
I/O15
I/O13
I/O11
I/O9
ZZ
I/O17
I/O19
I/O21
I/O23
VDD
VSS
VSS
I/O16
I/O14
I/O12
I/O10
NC
VSS
VSS
VSS
VSS
VSS
VSS
G
H
J
VSS
VSS
I/O26
I/O28
I/O30
I/O32
I/OP4
NC
I/O25
I/O27
I/O29
I/O31
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O8
I/O6
I/O4
I/O2
NC
I/O7
I/O5
I/O3
I/O1
I/OP1
NC
VSS
VSS
K
L
VSS
VSS
VSS
VSS
M
N
P
R
NC
VDD
TDO
TCK
NC
TDI
TMS
A14
A15
MODE
NC
A4
A3
A0
A12
A16
10
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[µPD4481322F9-EQx, µPD4481362F9-EQx]
Symbol Pin No.
Description
A0 - A17
6R, 6P, 4P, 4R, 3R, 3P, 2B, 2A, 10A, 10B, 8P, 8R, Synchronous Address Input
9R, 9P, 10P, 10R, 11R, 9A
I/O1 - I/O32
11M, 10M, 11L, 10L, 11K, 10K, 11J, 10J, 11G,
10G, 11F, 10F, 11E, 10E, 11D, 10D, 2D, 1D, 2E,
1E, 2F, 1F, 2G, 1G, 2J, 1J, 2K, 1K, 2L, 1L, 2M, 1M
11N
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
ADV
Synchronous Data In (Parity),
11C
Synchronous / Asynchronous Data Out (Parity)
1C
1N
8A
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
/CE, CE2, /CE2
/WE
3A, 3B, 6A
7B
/BW1 - /BW4
/G
5B, 5A, 4A, 4B
8B
6B
7A
1R
CLK
/CKE
Synchronous Clock Enable Input
MODE
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
ZZ
11H
VDD
2H, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 7N, 8D,
8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M
Power Supply
VSS
4C, 4N, 5C, 5D, 5E, 5F, 5G, 5H, 5J, 5K, 5L, 5M,
6C, 6D, 6E, 6F, 6G, 6H, 6J, 6K, 6L, 6M, 7C, 7D,
7E, 7F, 7G, 7H, 7J, 7K, 7L, 7M, 8C, 8N
3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D,
9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N
Ground
VDDQ
NC
Output Buffer Power Supply
No Connection
1A, 1B, 1H, 1P, 2C, 2N, 2P, 2R, 3H, 5N, 6N, 9B,
9H, 10C, 10H, 10N, 11A, 11B, 11P
5R
TMS
TDI
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
5P
7R
7P
TCK
TDO
Note NC (No Connection) is used in the µPD4481322F9-EQx.
I/OP1 - I/OP4 are used in the µPD4481362F9-EQx.
11
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Block Diagrams
[µPD4481162, µPD4481182]
19
17
19
A0 - A18
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
19
19
Write address
register 1
Write address
register 0
Memory Cell Array
1,024 rows
ADV
/BW1
/BW2
Write registry and
data coherency
control logic
Write
drivers
16/18
16/18
I/O1 - I/O16
I/OP1, I/OP2
512 x 16 columns
(8,388,608 bits)
512 x 18 columns
(9,437,184 bits)
/WE
E
E
16/18
16/18
16/18
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
Burst Sequence
[µPD4481162, µPD4481182]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, A1, A0
A18 - A2, A1, /A0
A18 - A2, /A1, A0
A18 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
12
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[µPD4481322, µPD4481362]
18
16
18
A0 - A17
MODE
Address
register 0
A1
A0
A1’
A0’
Burst
logic
ADV
K
K
CLK
/CKE
18
18
Write address
register 1
Write address
register 0
Memory Cell Array
1,024 rows
ADV
/BW1
/BW2
/BW3
/BW4
/WE
Write registry and
data coherency
control logic
Write
drivers
32/36
32/36
I/O1 - I/O32
256 x 32 columns
(8,388,608 bits)
256 x 36 columns
(9,437,184 bits)
I/OP1 - I/OP4
E
E
32/36
32/36
32/36
Input
register 1
Input
register 0
E
E
Read
logic
/G
/CE
CE2
/CE2
ZZ
Power down control
[µPD4481322, µPD4481362]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, A1, A0
A17 - A2, A1, /A0
A17 - A2, /A1, A0
A17 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
13
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
State Diagram
DS
BURST
DS
DS
DESELECT
READ
WRITE
DS
DS
WRITE
READ
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
BURST
BURST
WRITE
WRITE
READ
BURST
READ
BURST
WRITE
BURST
BURST
Command
DS
Operation
Deselect
Read
Write
New Read
New Write
Burst
Burst Read, Burst Write or Continue Deselect
Remarks 1. States change on the rising edge of the clock.
2. A Stall of Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only
blocks the clock (CLK) input and does not change the state of the device.
14
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Asynchronous Truth Table
Operation
Read Cycle
/G
L
I/O
Data-Out
Hi-Z
Read Cycle
H
×
Write Cycle
Hi-Z, Data-In
Hi-Z
Deselected
×
Remark × : don’t care
Synchronous Truth Table
Operation
Deselected
/CE
H
×
CE2 /CE2 ADV
/WE /BWs /CKE
CLK
I/O
Hi-Z
Address
None
Note
×
L
×
×
H
×
L
×
L
×
L
×
×
L
L
×
×
×
×
H
×
L
×
L
×
×
×
×
×
×
×
×
L
L
H
H
×
L
L
L
L
L
L
L
L
L
L
H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
1
1
1
1
Deselected
Hi-Z
None
Deselected
×
×
×
H
×
H
×
H
×
×
L
Hi-Z
None
Continue Deselected
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Write Abort
Write Cycle / Write Abort
Stall / Ignore Clock Edge
×
H
L
Hi-Z
None
L
Data-Out
Data-Out
Data-In
Data-In
Hi-Z
External
Next
×
H
L
L
External
Next
×
H
L
L
External
Next
×
H
×
Hi-Z
×
−
Current
2
Notes 1. Deselect status is held until new “Begin Burst” entry.
2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Low-Z).
If it occurs during a write cycle, the bus will remain Hi-Z. No write operation will be performed during the
Ignore Clock Edge cycle.
Remarks 1. × : don’t care
2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
15
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Partial Truth Table for Write Enables
[µPD4481162, µPD4481182]
Operation
/WE
H
/BW1
/BW2
Read Cycle
×
L
×
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
Write Abort / NOP
L
L
H
L
L
L
L
H
H
Remark × : don’t care
[µPD4481322, µPD4481362]
Operation
/WE
H
L
/BW1
/BW2
/BW3
/BW4
Read Cycle
×
L
×
H
L
×
H
H
L
×
H
H
H
L
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
L
H
H
H
L
L
H
H
L
L
H
L
L
L
Write Abort / NOP
L
H
H
H
H
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
≤ 0.2 V
Chip Status
Active
Active
Sleep
Open
≥ VDD − 0.2 V
16
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
MIN.
–0.5
TYP.
MAX.
+4.0
Unit
V
Supply voltage
for A version
for C version
–0.5
+3.0
Output supply voltage
Input voltage
VDDQ
VIN
–0.5
VDD
V
V
–0.5 Note
–0.5 Note
0
VDD + 0.5
VDDQ + 0.5
70
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
TA
V
°C
°C
Tstg
–55
+125
Note –2.0 V (MIN.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
for A Version [µPD4481162-Axx, µPD4481182-Axx, µPD4481322-Axx, µPD4481362-Axx]
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
TYP.
3.3
MAX.
3.465
Unit
V
3.135
2.5 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
2.5
3.3
2.9
VDDQ + 0.3
+0.7
V
V
V
VIL
–0.3 Note
VDDQ
VIH
3.135
2.0
3.465
VDDQ + 0.3
+0.8
V
V
V
VIL
–0.3 Note
Note –0.8 V (MIN.) (Pulse width : 2 ns)
for C Version [µPD4481162-Cxx, µPD4481182-Cxx, µPD4481322-Cxx, µPD4481362-Cxx]
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
2.375
2.375
1.7
TYP.
2.5
MAX.
2.625
Unit
V
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.5
2.625
V
VDDQ + 0.3
+0.7
V
VIL
–0.3 Note
V
Note –0.8 V (MIN.) (Pulse width : 2 ns)
17
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
DC Characteristics (TA = 0 to 70°C, VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
Parameter
Input leakage current
I/O leakage current
Operating supply current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled.
Device selected, Cycle = MAX. -A50, -C50
ILO
–2
+2
µA
IDD
400
350
300
TBD
mA
VIN ≤ VIL or VIN ≥ VIH,
-A60, -C60
-A75, -C75
II/O = 0 mA
Standby supply current
ISB
Device deselected, Cycle = 0 MHz,
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
Device deselected, Cycle = 0 MHz,
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
VI/O ≤ 0.2 V, All inputs are static.
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
mA
ISB1
TBD
ISB2
ISBZZ
VOH
VOL
130
Power down supply current
2.5 V LVTTL Interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
TBD
mA
V
IOH = –2.0 mA
IOL = –1.0 mA
IOH = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL Interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
2.4
V
V
IOL = +8.0 mA
0.4
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test condition
VIN = 0 V
MIN.
TYP.
MAX.
5.0
Unit
pF
Input capacitance
Input / Output capacitance
Clock input capacitance
CI/O
VI/O = 0 V
8.0
pF
Cclk
Vclk = 0 V
6.0
pF
Remark These parameters are not 100% tested.
18
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
AC Characteristics (TA = 0 to 70°C, VDD = 3.3 ± 0.165 V or 2.5 ± 0.125 V)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time≤ 2.4 ns)
2.4 V
V
DDQ/2
Test points
Test points
VDDQ/2
VSS
Output waveform
VDDQ/2
VDDQ/2
3.3 V LVTTL Interface
Input waveform (Rise / Fall time≤ 3.0 ns)
3.0 V
1.5 V
Test points
Test points
1.5 V
VSS
Output waveform
1.5 V
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
Figure External load at test
ZO = 50 Ω
I/O (Output)
C
L
50 Ω
VT = +1.2 V / +1.5 V
Remark CL includes capacitances of the probe and jig, and stray capacitances.
19
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Read and Write Cycle
Parameter
Symbol
-A50, -C50
(200 MHz)
-A60, -C60
(167 MHz)
-A75, -C75
(133 MHz)
Unit Notes
Standard
Alias
TCYC
TCD
TOE
TDC1
TDC2
TOLZ
TOHZ
TCZ
TCH
TCL
TAS
TSS
TDS
TWS
–
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
ns
ns
ns
5
–
6
–
7.5
–
–
4.2
4.2
–
Clock access time
–
3.2
3.2
–
–
3.5
3.5
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output Hi-Z
Clock high to output Hi-Z
Clock high pulse width
Clock low pulse width
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
1.5
1.5
0
1.5
1.5
0
1.5
1.5
0
–
–
–
1
1
–
–
–
0
3.2
3.2
–
0
3.5
3.5
–
0
4.2
3.5
–
1, 2
1.5
1.8
1.8
1.5
1.5
1.8
1.8
1.5
1.5
2.2
2.2
1.5
TKLKH
–
–
–
Setup times
Address
TAVKH
TADSVKH
TDVKH
TWVKH
–
–
–
Address status
Data in
Write enable
Address advance TADVVKH
Chip enable
Address
TEVKH
TKHAX
–
Hold times
TAH
TSH
TDH
TWH
–
0.5
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX
TKHDX
Write enable
TKHWX
Address advance TKHADVX
Chip enable
TKHEX
TZZE
–
Power down entry time
TZZE
TZZR
ns
ns
10
10
–
–
12
12
–
–
15
15
–
–
Power down recovery time
TZZR
Notes 1. Transition is measured ±200 mV from steady state.
2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (0 °C, VDD
max.) than TKHQZ, which is a max. parameter (worse case at 70 °C, VDD min.).
20
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
READ / WRITE CYCLE
1
2
TKHKH
3
4
5
6
7
8
9
10
CLK
TKHKL TKLKH
TEVKH TKHEX
TCVKH TKHCX
/CKE
/CEs Note 1
ADV
TADVVKH TKHADVX
TWVKH TKHWX
TWVKH TKHWX
/WE
/BWs Note 2
Address
A1
A2
A3
A4
A5
A6
A7
TAVKH TKHAX
D (A1)
D (A2)
D (A2+1)
D (A5)
Data In
TDVKH TKHDX
TKHQX1
TKHQX2
Q (A3)
TGLQV TKHQZ
Q (A4)
Q (A4+1)
Q (A6)
Data Out
/G
TKHQX2
TGHQZ
TKHQV
TGLQX
BURST
WRITE
D (A2+1)
BURST
READ
Q (A4+1)
WRITE
D (A1)
WRITE
D (A2)
READ
Q (A3)
READ
Q (A4)
WRITE
D (A5)
READ
Q (A6)
WRITE
Q (A7)
Command
DESELECT
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When
/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables
(/BW1, /BW2, /BW3 or /BW4) are LOW.
21
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
NOP, STALL AND DESELECT CYCLE
1
2
3
4
5
6
7
8
9
10
CLK
/CKE
/CEs
ADV
/WE
/BWs
Address
A1
A2
A3
A4
A5
D (A1)
D (A4)
Data In
TKHQZ
Q (A2)
Q (A3)
Q (A5)
TKHQX2
Data Out
WRITE
D (A1)
READ
Q (A2)
READ
Q (A3)
WRITE
D (A4)
READ
Q (A5)
CONTINUE
DESELECT
Command
STALL
STALL
NOP
DESELECT
22
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
POWER DOWN (ZZ) CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
TKHKH
CLK
/CKE
TKHKL TKLKH
/CEs Note
ADV
/WE Note
/BWs
Address
/G
A1
A2
Data Out
ZZ
Q1 (A2)
Q (A1)
TZZEH TZZES
TZZRH TZZRS
Power Down (ISBZZ) State
Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power
down state entry.
23
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
JTAG Specification
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 support a limited set of JTAG functions as in IEEE
standard 1149.1.
Test Access Port (TAP) Pins
Pin Name
TCK
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling
edge of TCK.
TMS
TDI
Test Mode Select. This is the command input for the TAP controller state machine.
Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed
between TDI and TDO is deter-mined by the state of the TAP controller state machine and the instruction that is
currently loaded in the TAP instruction.
TDO
Test Data Output. Output changes in response to the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (Tj = 0 to 70 °C)
Parameter
Symbol
VIH
Conditions
MIN.
2.0
–0.3
2.4
–
TYP.
MAX.
VDD + 0.3
+0.8
Unit
V
Note
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
JTAG output low voltage
VIL
V
VOH
VOL
IOH = –8 mA
IOL = 8 mA
–
V
0.4
V
24
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
JTAG AC Test Conditions (Tj = 0 to 70 °C)
Input waveform (rise / fall time = 1 ns (20 to 80 %))
3.0 V
1.5 V
1.5 V
Test Points
0 V
Output waveform
1.5 V
1.5 V
Test Points
Output load (VTT=1.5 V)
V
TT
50 Ω
ZO = 50 Ω
TDO
25
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
JTAG AC Characteristics (Tj = 0 to 70 °C)
Parameter
Symbol
tTHTH
Conditions
MIN.
100
40
TYP.
MAX.
Unit
ns
Note
Clock cycle time (TCK)
Clock phase time (TCK)
Setup time (TMS / TDI)
Hold time (TMS / TDI)
TCK low to TDO valid (TDO)
–
–
tTHTL / tTLTH
tMVTH / tDVTH
tTHMX / tTHDX
tTLQV
ns
10
–
ns
10
–
ns
–
20
ns
JTAG Timing Diagram
t
THTH
TCK
TMS
TDI
t
MVTH
t
THTL
t
TLTH
t
THMX
t
DVTH
t
THDX
t
TLQV
TDO
26
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the
input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
512K x 16/18
256K x 16/18
Unit
bit
3
1
3
1
bit
32
51
32
70
bit
Boundary register
bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
µPD4481162
µPD4481182
µPD4481322
µPD4481362
512K x 16
512K x 18
256K x 16
256K x 18
XXXX
XXXX
XXXX
XXXX
0000 0000 0000 1000
0000 0000 0000 1001
0000 0000 0000 1010
0000 0000 0000 1011
1
1
1
1
00000010000
00000010000
00000010000
27
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
SCAN Exit Order
[µPD4481162F9-EQx / µPD4481182F9-EQx (512K words by 16/18 bits)]
Bit no. Signal name
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit no.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal name
/WE
CLK
/CE2
/BW1
/BW2
CE2
/CE
A7
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
2
A10
A11
A12
A13
A14
A15
A16
I/O
3
4
5
6
7
8
9
I/O
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
I/O
I/O
I/O
ZZ
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
A18
A9
I/O
I/O
A8
MODE
A5
A17
NC
ADV
/G
A4
A3
A2
/CKE
A1
A0
28
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[µPD4481322F9-EQx / µPD4481362F9-EQx (256K words by 32/36 bits)]
Bit no. Signal name Bit no. Signal name
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
A10
A11
A12
A13
A14
A15
A16
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
/CE2
/BW1
/BW2
/BW3
/BW4
CE2
/CE
A7
2
3
4
5
6
7
8
9
I/O
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ZZ
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A9
I/O
A8
I/O
A17
NC
ADV
/G
MODE
A5
A4
A3
/CKE
/WE
CLK
A2
A1
A0
29
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
JTAG Instructions
Instructions
EXTEST
Description
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to Hi-Z any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS
SAMPLE
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (Hi-Z) and the boundary register is connected between TDI and TDO when the TAP controller
is moved to the shift-DR state.
JTAG Instruction Cording
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
IDCODE
SAMPLE-Z
BYPASS
SAMPLE
BYPASS
BYPASS
BYPASS
Note
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
30
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1k resistor.
TDO should be left unconnected.
31
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
select-IR-Scan
select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
32
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
select-DR-Scan
Run-Test/Idle
33
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Package Drawings
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
34
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
165-PIN TAPE FBGA (13x15)
TBD
35
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4481162, 4481182, 4481322 and 4481362.
Types of Surface Mount Devices
µPD4481162GF
µPD4481182GF
µPD4481322GF
µPD4481362GF
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
: 100-pin PLASTIC LQFP (14 x 20)
µPD4481162F9-EQx : 165-pin TAPE FBGA (13 x 15)
µPD4481182F9-EQx : 165-pin TAPE FBGA (13 x 15)
µPD4481322F9-EQx : 165-pin TAPE FBGA (13 x 15)
µPD4481362F9-EQx : 165-pin TAPE FBGA (13 x 15)
36
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[MEMO]
37
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
[MEMO]
38
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
39
Preliminary Data Sheet M15562EJ1V0DS
µPD4481162, 4481182, 4481322, 4481362
ZEROSB is a trademark of NEC Corporation.
•
The information in this document is current as of June, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD4481162GF-C50-A
512KX16 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
NEC
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