UPD4481362GF-A75Y_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD4481162, 4481182, 4481322, 4481362

8M-BIT ZEROSB^TMSRAM

PIPELINED OPERATION

Description

The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a

262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).

In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal

operation.

The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness for high density and low capacitive loading.

Features

• Low voltage core supply : V_DD= 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y)

V_DD= 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)

• Synchronous operation

• Operating temperature : T_A= 0 to 70 °C (-A44, -A50, -A60, -A75, -C60, -C75)

T_A= −40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y)

• 100 percent bus utilization

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for pipelined operation

• All registers triggered off positive clock edge

• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4 (µPD4481322 and µPD4481362)

/BW1 and /BW2 (µPD4481162 and µPD4481182)

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M15562EJ3V0DS00 (3rd edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark shows major revised points.

2001

µPD4481162, 4481182, 4481322, 4481362

Ordering Information

(1/2)

Part number

Access

Clock

Frequency

MHz

Core Supply

Voltage

V

I/O Interface

Operating

Temperature

°C

Package

Time

ns

µPD4481162GF-A44

µPD4481162GF-A50

µPD4481162GF-A60

µPD4481162GF-A75

µPD4481182GF-A44

µPD4481182GF-A50

µPD4481182GF-A60

µPD4481182GF-A75

µPD4481322GF-A44

µPD4481322GF-A50

µPD4481322GF-A60

µPD4481322GF-A75

µPD4481362GF-A44

µPD4481362GF-A50

µPD4481362GF-A60

µPD4481362GF-A75

µPD4481162GF-C60

µPD4481162GF-C75

µPD4481182GF-C60

µPD4481182GF-C75

µPD4481322GF-C60

µPD4481322GF-C75

µPD4481362GF-C60

µPD4481362GF-C75

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

3.5

4.2

3.5

4.2

3.5

4.2

3.5

4.2

225

200

167

133

225

200

167

133

225

200

167

133

225

200

167

133

167

133

167

133

167

133

167

133

3.3 ± 0.165

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

100-pin PLASTIC

LQFP (14 x 20)

0 to 70

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

2.5 V LVTTL

2.5 ± 0.125

Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60 (167 MHz).

2

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

(2/2)

Part number

Access

Time

ns

Clock

Frequency

MHz

Core Supply

Voltage

V

I/O Interface

Operating

Temperature

°C

Package

µPD4481162GF-A44Y

µPD4481162GF-A50Y

µPD4481162GF-A60Y

µPD4481162GF-A75Y

µPD4481182GF-A44Y

µPD4481182GF-A50Y

µPD4481182GF-A60Y

µPD4481182GF-A75Y

µPD4481322GF-A44Y

µPD4481322GF-A50Y

µPD4481322GF-A60Y

µPD4481322GF-A75Y

µPD4481362GF-A44Y

µPD4481362GF-A50Y

µPD4481362GF-A60Y

µPD4481362GF-A75Y

µPD4481162GF-C60Y

µPD4481162GF-C75Y

µPD4481182GF-C60Y

µPD4481182GF-C75Y

µPD4481322GF-C60Y

µPD4481322GF-C75Y

µPD4481362GF-C60Y

µPD4481362GF-C75Y

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

2.8

3.2

3.5

4.2

3.5

4.2

3.5

4.2

3.5

4.2

3.5

4.2

225

200

167

133

225

200

167

133

225

200

167

133

225

200

167

133

167

133

167

133

167

133

167

133

3.3 ± 0.165

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

100-pin PLASTIC

LQFP (14 x 20)

−40 to +85

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

3.3 V LVTTL ^Note

3.3 V or 2.5 V LVTTL

2.5 V LVTTL

2.5 ± 0.125

Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60Y (167 MHz).

3

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Pin Configurations

/××× indicates active low signal.

100-pin PLASTIC LQFP (14 × 20)

[µPD4481162GF, µPD4481182GF]

Marking Side

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A18

NC

2

3

V

DDQ

4

VDDQ

V

SSQ

5

VSSQ

NC

6

NC

7

I/OP1, NC

I/O8

I/O9

8

I/O10

9

I/O7

V

SS

Q

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

Q

V

DD

Q

I/O11

I/O12

I/O6

I/O5

VDD

VSS

VDD

VSS

ZZ

I/O13

I/O14

I/O4

I/O3

V

DD

Q

V

DDQ

V

SS

VSSQ

I/O15

I/O16

I/O2

I/O1

NC

I/OP2, NC

NC

V

SS

Q

V

SS

Q

V

DD

Q

NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Remark Refer to Package Drawing for the 1-pin index mark.

4

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Pin Identifications

[µPD4481162GF, µPD4481182GF]

Symbol

Pin No.

Description

A0 to A18

37, 36, 35, 34, 33, 32, 100, 99, 82, 81,

44, 45, 46, 47, 48, 49, 50, 83, 80

Synchronous Address Input

I/O1 to I/O16

58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,

18, 19, 22, 23

Synchronous / Asynchronous Data Out

I/OP1, NC^Note

I/OP2, NC^Note

ADV

74

Synchronous Data In (Parity),

Synchronous / Asynchronous Data Out (Parity)

Synchronous Address Load / Advance Input

Synchronous Chip Enable Input

Synchronous Write Enable Input

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

Clock Input

24

85

/CE, CE2, /CE2

/WE

98, 97, 92

88

/BW1, /BW2

/G

93, 94

86

CLK

89

/CKE

87

Synchronous Clock Enable Input

Asynchronous Burst Sequence Select Input

Have to tied to V^DDor V^SSduring normal operation

Asynchronous Power Down State Input

Power Supply

MODE

31

ZZ

64

V^DD

V^SS

14, 15, 16, 41, 65, 66, 91

17, 40, 67, 90

Ground

V^DDQ

V^SSQ

NC

4, 11, 20, 27, 54, 61, 70, 77

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Power Supply

Output Buffer Ground

1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection

51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96

Note NC (No Connection) is used in the µPD4481162GF.

I/OP1 and I/OP2 are used in the µPD4481182GF.

5

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

100-pin PLASTIC LQFP (14 × 20)

[µPD4481322GF, µPD4481362GF]

Marking Side

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

I/OP3, NC

I/O17

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/OP2, NC

I/O16

2

I/O18

3

I/O15

V

DD

Q

4

V

DD

SS

Q

V

SS

5

V

Q

I/O19

I/O20

I/O21

I/O22

6

I/O14

I/O13

I/O12

I/O11

7

8

9

V

SS

Q

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VSS

Q

VDD

Q

I/O23

I/O24

I/O10

I/O9

VDD

VSS

VDD

VSS

ZZ

I/O25

I/O26

I/O8

I/O7

V

DD

Q

V

DD

SS

Q

V

SS

V

Q

I/O27

I/O28

I/O29

I/O30

I/O6

I/O5

I/O4

I/O3

V

SS

Q

VSS

Q

VDD

Q

I/O31

I/O32

I/O2

I/O1

I/OP4, NC

I/OP1, NC

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Remark Refer to Package Drawing for the 1-pin index mark.

6

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[µPD4481322GF, µPD4481362GF]

Symbol

Pin No.

Description

A0 to A17

37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

45, 46, 47, 48, 49, 50, 83

I/O1 to I/O32

52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

I/OP1, NC ^Note

I/OP2, NC^Note

I/OP3, NC^Note

I/OP4, NC^Note

ADV

51

Synchronous Data In (Parity),

80

Synchronous / Asynchronous Data Out (Parity)

1

30

85

Synchronous Address Load / Advance Input

Synchronous Chip Enable Input

Synchronous Write Enable Input

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

Clock Input

/CE, CE2, /CE2

/WE

98, 97, 92

88

/BW1 to /BW4

/G

93, 94, 95, 96

86

89

87

31

CLK

/CKE

Synchronous Clock Enable Input

Asynchronous Burst Sequence Select Input

Have to tied to V^DDor V^SSduring normal operation

Asynchronous Power Down State Input

Power Supply

MODE

ZZ

64

V^DD

V^SS

14, 15, 16, 41, 65, 66, 91

17, 40, 67, 90

Ground

V^DDQ

V^SSQ

NC

4, 11, 20, 27, 54, 61, 70, 77

5, 10, 21, 26, 55, 60, 71, 76

38, 39, 42, 43, 84

Output Buffer Power Supply

Output Buffer Ground

No Connection

Note NC (No Connection) is used in the µPD4481322GF.

I/OP1 to I/OP4 are used in the µPD4481362GF.

7

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Block Diagrams

[µPD4481162, µPD4481182]

19

17

19

A0 to A18

MODE

Address

register 0

A1

A0

A1’

A0’

Burst

logic

ADV

K

CLK

/CKE

19

Write address

register 1

Write address

register 0

Memory Cell Array

1,024 rows

ADV

/BW1

/BW2

Write registry and

data coherency

control logic

Write

drivers

16/18

I/O1 to I/O16

I/OP1, I/OP2

512 x 16 columns

(8,388,608 bits)

512 x 18 columns

(9,437,184 bits)

/WE

E

16/18

Input

register 1

Input

register 0

E

Read

logic

/G

/CE

CE2

/CE2

ZZ

Power down control

Burst Sequence

[µPD4481162, µPD4481182]

Interleaved Burst Sequence Table (MODE = V^DD)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A18 to A2, A1, A0

A18 to A2, A1, /A0

A18 to A2, /A1, A0

A18 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V^SS)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A18 to A2, 0, 0

A18 to A2, 0, 1

A18 to A2, 1, 0

A18 to A2, 1, 1

A18 to A2, 0, 1

A18 to A2, 1, 0

A18 to A2, 1, 1

A18 to A2, 0, 0

A18 to A2, 1, 0

A18 to A2, 1, 1

A18 to A2, 0, 0

A18 to A2, 0, 1

A18 to A2, 1, 1

A18 to A2, 0, 0

A18 to A2, 0, 1

A18 to A2, 1, 0

8

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[µPD4481322, µPD4481362]

18

16

18

A0 to A17

MODE

Address

register 0

A1

A0

A1’

A0’

Burst

logic

ADV

K

CLK

/CKE

18

Write address

register 1

Write address

register 0

Memory Cell Array

1,024 rows

ADV

/BW1

/BW2

/BW3

/BW4

/WE

Write registry and

data coherency

control logic

Write

drivers

32/36

I/O1 to I/O32

256 x 32 columns

(8,388,608 bits)

256 x 36 columns

(9,437,184 bits)

I/OP1 to I/OP4

E

32/36

Input

register 1

Input

register 0

E

Read

logic

/G

/CE

CE2

/CE2

ZZ

Power down control

[µPD4481322, µPD4481362]

Interleaved Burst Sequence Table (MODE = V^DD)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A17 to A2, A1, A0

A17 to A2, A1, /A0

A17 to A2, /A1, A0

A17 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V^SS)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A17 to A2, 0, 0

A17 to A2, 0, 1

A17 to A2, 1, 0

A17 to A2, 1, 1

A17 to A2, 0, 1

A17 to A2, 1, 0

A17 to A2, 1, 1

A17 to A2, 0, 0

A17 to A2, 1, 0

A17 to A2, 1, 1

A17 to A2, 0, 0

A17 to A2, 0, 1

A17 to A2, 1, 1

A17 to A2, 0, 0

A17 to A2, 0, 1

A17 to A2, 1, 0

9

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

State Diagram

DS

BURST

DS

DESELECT

READ

WRITE

DS

WRITE

READ

BEGIN

READ

BEGIN

WRITE

READ

WRITE

READ

BURST

WRITE

READ

BURST

READ

BURST

WRITE

BURST

Command

DS

Operation

Deselect

Read

Write

New Read

New Write

Burst

Burst Read, Burst Write or Continue Deselect

Remarks 1. States change on the rising edge of the clock.

2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only

blocks the clock (CLK) input and does not change the state of the device.

10

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Asynchronous Truth Table

Operation

Read Cycle

/G

L

I/O

Dout

Read Cycle

H

×

High-Z

High-Z, Din

High-Z

Write Cycle

Deselected

×

Remark × : don’t care

Synchronous Truth Table

Operation

Deselected

/CE

H

×

CE2 /CE2 ADV

/WE /BWs /CKE

CLK

I/O

High-Z

Dout

Address

None

Note

×

L

×

H

×

H

×

H

×

H

×

L

×

L

×

L

×

L

×

H

×

L

×

L

×

L

H

×

L

H

L → H

1

Deselected

None

Deselected

×

L

None

Continue Deselected

Read Cycle / Begin Burst

Read Cycle / Continue Burst

Write Cycle / Begin Burst

Write Cycle / Continue Burst

Write Cycle / Write Abort

Stall / Ignore Clock Edge

×

H

L

None

L

External

H

L

Dout

L

Din

External

H

L

Din

L

High-Z

−

External

H

×

Current

2

Notes 1. Deselect status is held until new “Begin Burst” entry.

2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low

impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will

be performed during the Ignore Clock Edge cycle.

Remarks 1. × : don’t care

2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.

/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.

11

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Partial Truth Table for Write Enables

[µPD4481162, µPD4481182]

Operation

/WE

H

/BW1

/BW2

Read Cycle

×

L

×

H

L

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / All Bytes

Write Abort / NOP

L

H

L

H

Remark × : don’t care

[µPD4481322, µPD4481362]

Operation

/WE

H

L

/BW1

/BW2

/BW3

/BW4

Read Cycle

×

L

×

H

L

×

H

L

×

H

L

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / Byte 3 (I/O [17:24], I/OP3)

Write Cycle / Byte 4 (I/O [25:32], I/OP4)

Write Cycle / All Bytes

L

H

L

H

L

H

L

Write Abort / NOP

L

H

Remark × : don’t care

ZZ (Sleep) Truth Table

ZZ

≤ 0.2 V

Chip Status

Active

Sleep

Open

≥ V^DD− 0.2 V

12

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Electrical Specifications

Absolute Maximum Ratings

Parameter

Supply voltage

Symbol

Conditions

MIN.

–0.5

TYP.

MAX.

+4.0

Unit

V

V^DD

-A44, -A50, -A60, -A75

-A44Y, -A50Y, -A60Y, -A75Y

-C60, -C75

–0.5

+3.0

-C60Y, -C75Y

Output supply voltage

Input voltage

V^DDQ

V^IN

–0.5

–0.5 ^Note

0

V^DD

V^DD+ 0.5

V^DDQ + 0.5

70

V

Input / Output voltage

Operating ambient

temperature

V^I/O

T^A

V

-A44, -A50, -A60, -A75, -C60, -C75

-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y

°C

–40

+85

Storage temperature

T^stg

–55

+125

°C

Note –2.0 V (MIN.) (Pulse width : 2 ns)

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions

(1/2)

Parameter

Symbol

V^DD

Conditions

-A44, -A50, -A60, -A75

Unit

-A44Y, -A50Y, -A60Y, -A75Y

MIN.

TYP.

3.3

MAX.

3.465

Supply voltage

3.135

V

2.5 V LVTTL Interface

Output supply voltage

High level input voltage

Low level input voltage

3.3 V LVTTL Interface

Output supply voltage

High level input voltage

Low level input voltage

V^DDQ

V^IH

2.375

1.7

–0.3 ^Note

2.5

2.9

V^DDQ + 0.3

+0.7

V

V^IL

V^DDQ

V^IH

3.135

2.0

–0.3 ^Note

3.3

3.465

V^DDQ + 0.3

+0.8

V

V^IL

Note –0.8 V (MIN.) (Pulse width : 2 ns)

Recommended DC Operating Conditions

(2/2)

Parameter

Symbol

Conditions

-C60, -C75

-C60Y, -C75Y

TYP.

Unit

MIN.

2.375

1.7

MAX.

2.625

Supply voltage

V^DD

V^DDQ

V^IH

2.5

V

Output supply voltage

High level input voltage

Low level input voltage

2.625

V^DDQ + 0.3

+0.7

V^IL

–0.3 ^Note

Note –0.8 V (MIN.) (Pulse width : 2 ns)

13

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

DC Characteristics (V^DD= 3.3 ± 0.165 V or 2.5 ± 0.125 V)

Parameter

Input leakage current

I/O leakage current

Operating supply current

Symbol

I^LI

Test condition

MIN.

–2

TYP.

MAX.

+2

Unit

µA

V^IN(except ZZ, MODE) = 0 V to V^DD

V^I/O= 0 V to V^DDQ, Outputs are disabled.

I^LO

–2

+2

µA

I^DD

Device selected,

Cycle = MAX.

-A44

440

mA

-A44Y

V^IN≤ V^ILor V^IN≥ V^IH,

I^I/O= 0 mA

-A50

400

320

300

30

-A50Y

-A60, -C60

-A60Y, -C60Y

-A75, -C75

-A75Y, -C75Y

Standby supply current

I^SB

Device deselected, Cycle = 0 MHz,

V^IN≤ V^ILor V^IN≥ V^IH, All inputs are static.

Device deselected, Cycle = 0 MHz,

V^IN≤ 0.2 V or V^IN≥ V^DD– 0.2 V,

V^I/O≤ 0.2 V, All inputs are static.

Device deselected, Cycle = MAX.

V^IN≤ V^ILor V^IN≥ V^IH

mA

I^SB1

15

I^SB2

I^SBZZ

V^OH

V^OL

130

15

Power down supply current

2.5 V LVTTL Interface

High level output voltage

ZZ ≥ V^DD– 0.2 V, V^I/O≤ V^DDQ + 0.2 V

mA

V

I^OH= –2.0 mA

I^OH= –1.0 mA

I^OL= +2.0 mA

I^OL= +1.0 mA

1.7

2.1

Low level output voltage

0.7

0.4

V

3.3 V LVTTL Interface

High level output voltage

Low level output voltage

V^OH

V^OL

I^OH= –4.0 mA

I^OL= +8.0 mA

2.4

V

0.4

Capacitance (T^A= 25 °C, f = 1MHz)

Parameter

Symbol

C^IN

Test condition

V^IN= 0 V

MIN.

TYP.

MAX.

6.0

Unit

pF

Input capacitance

Input / Output capacitance

Clock input capacitance

C^I/O

V^I/O= 0 V

8.0

pF

C^clk

V^clk= 0 V

6.0

pF

Remark These parameters are periodically sampled and not 100% tested.

14

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

AC Characteristics (V^DD= 3.3 ± 0.165 V or 2.5 ± 0.125 V)

AC Test Conditions

2.5 V LVTTL Interface

Input waveform (Rise / Fall time≤ 2.4 ns)

2.4 V

1.2 V

Test points

1.2 V

VSS

Output waveform

1.2 V

3.3 V LVTTL Interface

Input waveform (Rise / Fall time≤ 3.0 ns)

3.0 V

1.5 V

Test points

1.5 V

VSS

Output waveform

1.5 V

Output load condition

C^L: 30 pF

5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)

Figure External load at test

ZO = 50 Ω

I/O (Output)

C

L

50 Ω

VT = +1.2 V / +1.5 V

Remark C^Lincludes capacitances of the probe and jig, and stray capacitances.

15

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Read and Write Cycle (2.5 V LVTTL Interface)

Parameter Symbol

-A44, -A50, -A60, -C60

-A44Y, -A50Y, -A60Y, -C60Y

(167 MHz)

-A75, -C75

-A75Y, -C75Y

(133 MHz)

Unit Notes

Standard

Alias

TCYC

TCD

MIN.

MAX.

MIN.

MAX.

Cycle time

TKHKH

TKHQV

TGLQV

TKHQX1

TKHQX2

TGLQX

TGHQZ

TKHQZ

TKHKL

TKLKH

TAVKH

ns

6

–

3.5

–

7.5

–

4.2

–

Clock access time

Output enable access time

Clock high to output active

Clock high to output change

Output enable to output active

Output disable to output High-Z

Clock high to output High-Z

Clock high pulse width

TOE

–

TDC1

TDC2

TOLZ

TOHZ

TCZ

ns

1, 2

1.5

0

1.5

0

–

1

–

0

3.5

–

0

4.2

3.5

–

1, 2

1.5

1.8

1.5

2.2

1.5

TCH

Clock low pulse width

TCL

–

Setup times

Address

TAS

–

Address advance TADVVKH TADVS

Clock enable

Chip enable

Data in

TEVKH

TCVKH

TDVKH

TWVKH

TKHAX

TCES

TCSS

TDS

Write enable

Address

TWS

TAH

Hold times

0.5

–

0.5

–

ns

Address advance TKHADVX TADVH

Clock enable

Chip enable

Data in

TKHEX

TKHCX

TKHDX

TKHWX

TZZE

TCEH

TCSH

TDH

Write enable

TWH

TZZE

TZZR

Power down entry time

ns

–

12

–

15

Power down recovery time

TZZR

Notes 1. Transition is measured 200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus

contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T^Amin.,

V^DDmax.) than TKHQZ, which is a max. parameter (worse case at T^Amax., V^DDmin.).

16

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Read and Write Cycle (3.3 V LVTTL Interface)

Parameter Symbol

-A44

-A44Y

-A50

-A50Y

-A60

-A60Y

-A75

-A75Y

Unit Notes

(225 MHz)

(200 MHz)

(167 MHz)

(133 MHz)

Standard

Alias

TCYC

TCD

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Cycle time

TKHKH

TKHQV

TGLQV

TKHQX1

TKHQX2

TGLQX

TGHQZ

TKHQZ

TKHKL

TKLKH

TAVKH

ns

4.4

–

2.8

–

5

–

3.2

–

6

–

3.5

–

7.5

–

4.2

–

Clock access time

Output enable access time

Clock high to output active

Clock high to output change

Output enable to output active

Output disable to output High-Z

Clock high to output High-Z

Clock high pulse width

TOE

–

TDC1

TDC2

TOLZ

TOHZ

TCZ

ns

1, 2

1.5

0

1.5

0

1.5

0

1.5

0

–

1

–

0

2.8

–

0

3.2

–

0

3.5

–

0

4.2

3.5

–

1, 2

1.5

1.8

1.4

1.5

1.8

1.5

1.8

1.5

2.2

1.5

TCH

Clock low pulse width

TCL

–

Setup times

Address

TAS

–

Address advance TADVVKH TADVS

Clock enable

Chip enable

Data in

TEVKH

TCVKH

TDVKH

TWVKH

TKHAX

TCES

TCSS

TDS

Write enable

Address

TWS

TAH

Hold times

0.4

0.5

–

0.5

–

0.5

–

ns

–

Address advance TKHADVX TADVH

Clock enable

Chip enable

Data in

TKHEX

TKHCX

TKHDX

TKHWX

TZZE

TCEH

TCSH

TDH

Write enable

TWH

TZZE

TZZR

Power down entry time

ns

–

8.8

–

10

–

12

–

15

Power down recovery time

TZZR

Notes 1. Transition is measured 200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus

contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T^Amin.,

V^DDmax.) than TKHQZ, which is a max. parameter (worse case at T^Amax., V^DDmin.).

17

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

READ / WRITE CYCLE

1

2

TKHKH

3

4

5

6

7

8

9

10

CLK

TKHKL TKLKH

TEVKH TKHEX

/CKE

TCVKH TKHCX

/CEs ^{Note 1}

TADVVKH TKHADVX

TWVKH TKHWX

ADV

/WE

/BWs ^{Note 2}

Address

A1

A2

A3

A4

A5

A6

A7

TAVKH TKHAX

High-Z

Q (A6)

D (A1)

D (A2)

D (A2+1)

D (A5)

Data In

TDVKH TKHDX

High-Z

TKHQX1

TKHQX2

Q (A3)

TGLQV TKHQZ

High-Z

Q (A4)

Q (A4+1)

Data Out

/G

TKHQX2

TGHQZ

TKHQV

TGLQX

BURST

WRITE

D (A2+1)

BURST

READ

Q (A4+1)

WRITE

D (A1)

WRITE

D (A2)

READ

Q (A3)

READ

Q (A4)

WRITE

D (A5)

READ

Q (A6)

WRITE

Q (A7)

Command

DESELECT

Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When

/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.

2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables

(/BW1, /BW2, /BW3 or /BW4) are LOW.

18

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

NOP, STALL AND DESELECT CYCLE

1

2

3

4

5

6

7

8

9

10

CLK

/CKE

/CEs

ADV

/WE

/BWs

Address

A1

A2

A3

A4

A5

High-Z

D (A1)

D (A4)

Data In

TKHQZ

High-Z

Q (A2)

Q (A3)

Q (A5)

TKHQX2

Data Out

WRITE

D (A1)

READ

Q (A2)

READ

Q (A3)

WRITE

D (A4)

READ

Q (A5)

CONTINUE

DESELECT

Command

STALL

NOP

DESELECT

19

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

POWER DOWN (ZZ) CYCLE

1

2

3

4

5

6

7

8

9

10

11

12

TKHKH

CLK

/CKE

TKHKL TKLKH

/CEs ^Note

ADV

/WE ^Note

/BWs

Address

/G

A1

A2

High-Z

Data Out

ZZ

Q1 (A2)

Q (A1)

TZZE

TZZR

Power Down (ISBZZ) State

Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power

down state entry.

20

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Package Drawing

100-PIN PLASTIC LQFP (14x20)

A

B

80

81

51

50

detail of lead end

S

C

D

R

Q

31

30

100

1

F

M

G

J

H

I

K

P

S

N

S

L

M

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

A

B

C

D

F

22.0 0.2

20.0 0.2

14.0 0.2

16.0 0.2

0.825

G

0.575

+0.08

0.32

H

−0.07

I

J

0.13

0.65 (T.P.)

1.0 0.2

0.5 0.2

K

L

+0.06

0.17

M

−0.05

N

P

Q

0.10

1.4

0.125 0.075

+7°

3°

R

S

−3°

1.7 MAX.

S100GF-65-8ET-1

21

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of the µPD4481162, 4481182, 4481322 and 4481362.

Types of Surface Mount Devices

µPD4481162GF

µPD4481182GF

µPD4481322GF

µPD4481362GF

: 100-pin PLASTIC LQFP (14 x 20)

22

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Revision History

Edition/

Page

Type of

revision

Location

Description

Date

This

edition

(Previous edition → This edition)

3rd edition/ Throughout Throughout Modification

Dec. 2002 Addition

−

Preliminary Data Sheet → Data Sheet

Extended operating temperature products

(T^A= −40 to +85 °C)

23

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[MEMO]

24

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[MEMO]

25

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[MEMO]

26

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

27

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

ZEROSB is a trademark of NEC Electronics Corporation.

•

The information in this document is current as of December, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD4481362GF-A75Y
厂家：	NEC
描述：	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100 静态存储器内存集成电路
文件：	总28页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD4481362GF-A75Y [NEC]

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