UPD4482361GF-A85-A [NEC]
Cache SRAM, 256KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100;
| 型号： | UPD4482361GF-A85-A |
| 厂家： | 
NEC |
| 描述： | Cache SRAM, 256KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, LQFP-100 ISM频段 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4482161, 4482181, 4482321, 4482361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a
262,144-word by 32-bit and the µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
• 3.3 V or 2.5 V core supply
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)
TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs for flow through operation
• All registers triggered off positive clock edge
• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482321, µPD4482361)
/BW1, /BW2, /BWE (µPD4482161, µPD4482181)
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14521EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000
µPD4482161, 4482181, 4482321, 4482361
Ordering Information
(1/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Operating
Temperature
°C
Package
µPD4482161GF-A65
µPD4482161GF-A75
µPD4482161GF-A85
µPD4482181GF-A65
µPD4482181GF-A75
µPD4482181GF-A85
µPD4482321GF-A65
µPD4482321GF-A75
µPD4482321GF-A85
µPD4482361GF-A65
µPD4482361GF-A75
µPD4482361GF-A85
µPD4482161GF-C75
µPD4482161GF-C85
µPD4482181GF-C75
µPD4482181GF-C85
µPD4482321GF-C75
µPD4482321GF-C85
µPD4482361GF-C75
µPD4482361GF-C85
6.5
7.5
8.5
6.5
7.5
8.5
6.5
7.5
8.5
6.5
7.5
8.5
7.5
8.5
7.5
8.5
7.5
8.5
7.5
8.5
133
117
100
133
117
100
133
117
100
133
117
100
117
100
117
100
117
100
117
100
3.3 ± 0.165
3.3 V LVTTL Note
0 to 70
100-pin PLASTIC
3.3 V or 2.5 V LVTTL
LQFP (14 × 20)
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
2.5 ± 0.125
2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).
Data Sheet M14521EJ3V0DS
2
µPD4482161, 4482181, 4482321, 4482361
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
Operating
Temperature
°C
Package
µPD4482161GF-A65Y
µPD4482161GF-A75Y
µPD4482161GF-A85Y
µPD4482181GF-A65Y
µPD4482181GF-A75Y
µPD4482181GF-A85Y
µPD4482321GF-A65Y
µPD4482321GF-A75Y
µPD4482321GF-A85Y
µPD4482361GF-A65Y
µPD4482361GF-A75Y
µPD4482361GF-A85Y
µPD4482161GF-C75Y
µPD4482161GF-C85Y
µPD4482181GF-C75Y
µPD4482181GF-C85Y
µPD4482321GF-C75Y
µPD4482321GF-C85Y
µPD4482361GF-C75Y
µPD4482361GF-C85Y
6.5
7.5
8.5
6.5
7.5
8.5
6.5
7.5
8.5
6.5
7.5
8.5
7.5
8.5
7.5
8.5
7.5
8.5
7.5
8.5
133
117
100
133
117
100
133
117
100
133
117
100
117
100
117
100
117
100
117
100
3.3 ± 0.165
3.3 V LVTTL Note
100-pin PLASTIC
−40 to +85
3.3 V or 2.5 V LVTTL
LQFP (14 × 20)
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
3.3 V LVTTL Note
3.3 V or 2.5 V LVTTL
2.5 ± 0.125
2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).
Data Sheet M14521EJ3V0DS
3
µPD4482161, 4482181, 4482321, 4482361
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[µPD4482161GF, µPD4482181GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
2
3
V
DDQ
4
VDDQ
V
SS
Q
5
V
SS
Q
NC
NC
6
NC
7
I/OP1, NC
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O11
I/O12
NC
I/O6
I/O5
V
SS
V
DD
NC
NC
V
DD
V
SS
I/O13
I/O14
ZZ
I/O4
I/O3
V
DD
Q
Q
V
V
DD
Q
V
SS
SS
Q
I/O15
I/O16
I/O2
I/O1
NC
I/OP2, NC
NC
NC
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14521EJ3V0DS
4
µPD4482161, 4482181, 4482321, 4482361
Pin Identification (µPD4482161GF, µPD4482181GF)
Symbol
A0 to A18
Pin No.
Description
Synchronous Address Input
37, 36, 35, 34, 33, 32, 100, 99, 82,
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9,
Synchronous Data In,
12, 13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
I/OP1, NCNote
74
I/OP2, NCNote
24
/ADV
83
/AP
84
/AC
85
/CE, CE2, /CE2
98, 97, 92
/BW1, /BW2, /BWE
93, 94, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4482161GF.
I/OP1 and I/OP2 are used in the µPD4482181GF.
Data Sheet M14521EJ3V0DS
5
µPD4482161, 4482181, 4482321, 4482361
100-pin PLASTIC LQFP (14 x 20)
[µPD4482321GF, µPD4482361GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2, NC
I/O16
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
I/O15
I/O18
3
V
DDQ
V
DD
Q
Q
4
VSS
Q
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
VSS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
V
DD
I/O10
I/O9
I/O23
I/O24
NC
VSS
NC
V
DD
V
DD
NC
ZZ
V
SS
I/O25
I/O26
I/O8
I/O7
V
DDQ
V
DD
Q
Q
VSS
Q
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
VSS
Q
V
SS
Q
Q
VDDQ
V
DD
I/O2
I/O31
I/O32
I/O1
I/OP1, NC
I/OP4, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14521EJ3V0DS
6
µPD4482161, 4482181, 4482321, 4482361
Pin Identification (µPD4482321GF, µPD4482361GF)
Symbol Pin No.
A0 to A17
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC Note
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
/ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
83
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/AP
84
/AC
85
/CE, CE2, /CE2
/BW1 to /BW4, /BWE
/GW
98, 97, 92
93, 94, 95, 96, 87
88
86
89
31
/G
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 39, 42, 66
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4482321GF.
I/OP1 to I/OP4 are used in the µPD4482361GF.
Data Sheet M14521EJ3V0DS
7
µPD4482161, 4482181, 4482321, 4482361
Block Diagrams
[µPD4482161, µPD4482181]
19
19
17
19
Address
register
A0 to A18
A0, A1
MODE
/ADV
CLK
Q1
Binary
A1’
A0’
counter
and logic
/AC
/AP
Row and column
decoders
CLR
Q0
8/9
8/9
Memory cell array
1,024 rows
Byte 1
Byte 1
/BW1
/BW2
Write register
Write driver
Byte 2
Write register
Byte 2
Write driver
512 × 16 columns
(8,388,608 bits)
512 × 18 columns
(9,437,184 bits)
/BWE
16/18
16/18
Input
register
Output
buffer
/GW
/CE
Enable
register
CE2
/CE2
/G
2
16/18
I/O1 to I/O16
I/OP1 to I/OP2
Power down control
ZZ
Burst Sequence
[µPD4482161, µPD4482181]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 to A2, A1, A0
A18 to A2, A1, /A0
A18 to A2, /A1, A0
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
Data Sheet M14521EJ3V0DS
8
µPD4482161, 4482181, 4482321, 4482361
[µPD4482321, µPD4482361]
18
18
16
18
Address
register
A0 to A17
A0, A1
MODE
/ADV
CLK
Q1
Binary
A1’
A0’
counter
and logic
/AC
/AP
Row and column
decoders
CLR
Q0
8/9
8/9
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
/BW3
Write register
Write driver
Byte 2
Write register
Byte 2
Write driver
256 × 32 columns
(8,388,608 bits)
256 × 36 columns
(9,437,184 bits)
Byte 3
Write register
Byte 3
Write driver
Byte 4
Write register
Byte 4
Write driver
/BW4
/BWE
32/36
32/36
Input
register
Output
buffer
/GW
/CE
Enable
register
CE2
/CE2
/G
4
32/36
I/O1 to I/O32
I/OP1 to I/OP4
Power down control
ZZ
Burst Sequence
[µPD4482321, µPD4482361]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, A1, A0
A17 to A2, A1, /A0
A17 to A2, /A1, A0
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
Data Sheet M14521EJ3V0DS
9
µPD4482161, 4482181, 4482321, 4482361
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
I/O
Dout
H
×
High-Z
High-Z, Din
High-Z
×
Remark × : don’t care
Synchronous Truth Table
Operation
/CE
H
L
CE2
×
/CE2
×
/AP
×
/AC
L
/ADV
×
/WRITE
CLK
Address
None
Deselected Note
×
×
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
Deselected Note
L
×
L
×
×
None
Deselected Note
L
×
H
×
L
×
×
×
None
Deselected Note
L
L
H
H
L
L
×
×
None
Deselected Note
L
×
H
L
L
×
×
None
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
L
H
H
×
×
×
×
External
External
Next
L
L
H
H
×
L
×
H
H
H
H
H
L
L
L
L
L
×
×
H
H
H
H
L
L
H
×
×
×
L
Next
×
×
H
×
H
H
×
Current
Current
External
Next
H
L
×
×
H
×
L
H
H
×
×
×
H
H
H
H
L
H
×
×
×
L
Next
×
×
H
×
H
H
Current
Current
H
×
×
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW
or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1 to /BW4 and /GW are HIGH, and /BWE is LOW.
Data Sheet M14521EJ3V0DS
10
µPD4482161, 4482181, 4482321, 4482361
Partial Truth Table for Write Enables
[µPD4482161, µPD4482181]
Operation
/GW
H
/BWE
/BW1
/BW2
Read Cycle
H
L
L
L
L
×
×
H
L
×
H
H
L
Read Cycle
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
H
L
H
L
L
×
×
Remark × : don’t care
[µPD4482321, µPD4482361]
Operation
/GW
H
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
L
L
L
L
L
L
×
×
H
L
×
H
H
L
×
H
H
H
L
×
H
H
H
H
L
Read Cycle
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
H
H
H
H
H
L
H
H
H
L
H
H
L
H
L
Write Cycle / All Bytes
L
×
×
×
×
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
Chip Status
≤ 0.2 V
Active
Active
Sleep
Open
≥ VDD − 0.2 V
Data Sheet M14521EJ3V0DS
11
µPD4482161, 4482181, 4482321, 4482361
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
-A65, -A75, -A85
MIN.
–0.5
TYP.
MAX.
+4.0
Unit Notes
V
Supply voltage
-A65Y, -A75Y, -A85Y
-C75, -C85
–0.5
+3.0
V
-C75Y, -C85Y
Output supply voltage
Input voltage
VDDQ
VIN
–0.5
–0.5
–0.5
0
VDD
VDD + 0.5
VDDQ + 0.5
70
V
V
V
1, 2
1, 2
Input / Output voltage
Operating ambient
temperature
VI/O
TA
-A65, -A75, -A85, -C75, -C85
-A65Y, -A75Y, -A85Y, -C75Y, -C85Y
°C
–40
–55
+85
Storage temperature
Tstg
+125
°C
Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns)
2. VDDQ + 2.3 V (MAX.)(Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
(1/2)
Parameter
Symbol
VDD
Conditions
-A65, -A75, -A85
-A65Y, -A75Y, -A85Y
TYP.
Unit
MIN.
MAX.
3.465
Supply voltage
3.135
3.3
V
2.5 V LVTTL interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
–0.3 Note
2.5
2.9
V
V
V
VDDQ + 0.3
+0.7
VIL
VDDQ
VIH
3.135
2.0
–0.3 Note
3.3
3.465
VDDQ + 0.3
+0.8
V
V
V
VIL
Note –0.8 V (MIN.)(Pulse width : 2 ns)
Recommended DC Operating Conditions
(2/2)
Parameter
Symbol
Conditions
-C75, -C85
-C75Y, -C85Y
TYP.
Unit
MIN.
2.375
2.375
1.7
MAX.
2.625
Supply voltage
VDD
VDDQ
VIH
2.5
2.5
V
V
V
V
Output supply voltage
High level input voltage
Low level input voltage
2.625
VDDQ + 0.3
+0.7
VIL
–0.3 Note
Note –0.8 V (MIN.)(Pulse width : 2 ns)
Data Sheet M14521EJ3V0DS
12
µPD4482161, 4482181, 4482321, 4482361
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
I/O leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit Note
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled.
µA
µA
ILO
–2
+2
Operating supply current
IDD
Device selected,
Cycle = MAX.
-A65
250
mA
-A65Y
VIN ≤ VIL or VIN ≥ VIH,
II/O = 0 mA
-A75, -C75
-A75Y, -C75Y
-A85, -C85
-A85Y, -C85Y
225
200
150
IDD1
Suspend cycle, Cycle = MAX.
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Device deselected, Cycle = 0 MHz
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
Device deselected, Cycle = 0 MHz
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V
VI/O ≤ 0.2 V, All inputs are static.
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
Standby supply current
ISB
30
15
mA
ISB1
ISB2
ISBZZ
VOH
VOL
110
15
Power down supply current
2.5 V LVTTL interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Input capacitance
Test condition
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
CIN
CI/O
Cclk
6.0
8.0
6.0
Input / Output capacitance
Clock input capacitance
VI/O = 0 V
Vclk = 0 V
pF
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M14521EJ3V0DS
13
µPD4482161, 4482181, 4482321, 4482361
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
2.5 V LVTTL interface
Input waveform (Rise / Fall time ≤ 2.4 ns)
2.4 V
1.2 V
Test points
Test points
1.2 V
V
SS
Output waveform
1.2 V
1.2 V
3.3 V LVTTL interface
Input waveform (Rise / Fall time ≤ 3.0 ns)
3.0 V
1.5 V
Test points
Test points
1.5 V
1.5 V
V
SS
Output waveform
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
V
T
= +1.2 V / +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14521EJ3V0DS
14
µPD4482161, 4482181, 4482321, 4482361
Read and Write Cycle (2.5 V LVTTL Interface)
Parameter Symbol
-A65, -A75, -C75
-A65Y, -A75Y, -C75Y
(117 MHz)
-A85, -C85
-A85Y, -C85Y
(100MHz)
Unit Note
Standard
Alias
TCYC
TCD
MIN.
8.6
–
MAX.
–
MIN.
MAX.
–
Cycle time
TKHKH
TKHQV
TGLQV
10.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
7.5
3.5
–
8.5
3.5
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
TOE
–
–
TKHQX1 TDC1
TKHQX2 TDC2
2.5
2.5
0
2.5
2.5
0
–
–
TGLQX
TOLZ
TOHZ
TCZ
–
–
Output disable to output High-Z TGHQZ
0
3.5
5.0
–
0
3.5
5.0
–
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
TKHQZ
TKHKL
TKLKH
TAVKH
2.5
2.5
2.5
1.5
2.5
2.5
2.5
2.0
TCH
TCL
–
–
TAS
–
–
TADSVKH TSS
Data in
TDVKH
TWVKH
TDS
TWS
–
Write enable
Address advance TADVVKH
Chip enable
Hold times Address
TEVKH
TKHAX
–
TAH
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX TSH
TKHDX
TKHWX
TDH
TWH
–
Write enable
Address advance TKHADVX
Chip enable
Power down entry time
Power down recovery time
TKHEX
TZZE
–
TZZE
TZZR
–
–
8.6
8.6
–
–
10.0
10.0
ns
ns
TZZR
Data Sheet M14521EJ3V0DS
15
µPD4482161, 4482181, 4482321, 4482361
Read and Write Cycle (3.3 V LVTTL Interface)
Parameter Symbol
-A65
-A65Y
-A75
-A75Y
-A85
-A85Y
Unit Note
(133 MHz)
(117 MHz)
(100MHz)
Standard
Alias
TCYC
TCD
MIN.
MAX.
–
MIN.
MAX.
–
MIN.
MAX.
–
Cycle time
TKHKH
TKHQV
TGLQV
7.5
–
8.6
–
10.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
6.5
3.5
–
7.5
3.5
–
8.5
3.5
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
TOE
–
–
–
TKHQX1 TDC1
TKHQX2 TDC2
2.5
2.5
0
2.5
2.5
0
2.5
2.5
0
–
–
–
TGLQX
TOLZ
TOHZ
TCZ
–
–
–
Output disable to output High-Z TGHQZ
0
3.5
5.0
–
0
3.5
5.0
–
0
3.5
5.0
–
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
TKHQZ
TKHKL
TKLKH
TAVKH
2.5
2.5
2.5
1.5
2.5
2.5
2.5
1.5
2.5
2.5
2.5
2.0
TCH
TCL
–
–
–
TAS
–
–
–
TADSVKH TSS
Data in
TDVKH
TWVKH
TDS
TWS
–
Write enable
Address advance TADVVKH
Chip enable
Hold times Address
TEVKH
TKHAX
–
TAH
0.5
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX TSH
TKHDX
TKHWX
TDH
TWH
–
Write enable
Address advance TKHADVX
Chip enable
Power down entry time
Power down recovery time
TKHEX
TZZE
–
TZZE
TZZR
–
–
7.5
7.5
–
–
8.6
8.6
–
–
10.0
10.0
ns
ns
TZZR
Data Sheet M14521EJ3V0DS
16
READ CYCLE
TKHKH
CLK
/AP
/AC
TKHKL
TKLKH
TADSVKH
TKHADSX
TADSVKH
TKHADSX
TAVKH
TKHAX
A1
A2
Address
/ADV
A3
TADVVKH
TKHADVX
µ
TWVKH
TKHWX
TKHWX
/BWE
/BWs
TWVKH
/GW
TEVKH
TKHEX
/CEsNote
/G
TGLQV
High-Z
Data In
TKHQV
TGHQZ
TKHQX2
High-Z
TKHQZ
TGLQX
High-Z
High-Z
Q1(A1)
Q1(A2)
Q2(A2)
Q3(A2)
Q1(A2)
Q4(A2)
Q1(A3)
Data Out
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Qn(A2) refers to output from address A2. Q1 to Q4 refer to outputs according to burst sequence.
Remark
WRITE CYCLE
TKHKH
CLK
/AP
/AC
TADSVKH TKHADSX
TKHKL
TKLKH
TADSVKH TKHADSX
TAVKH
TKHAX
Address
/ADV
A1
A2
A3
TADVVKH
TKHADVX
TKHWX
µ
TWVKH
/BWENote1
/BWs
TWVKH
TKHWX
/GWNote1
TEVKH
TKHEX
/CEsNote2
/G
TDVKH
TKHDX
High-Z
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
Data In
TGHQZ
High-Z
Data Out
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
TADSVKH
/AP
/AC
TKHADSX
TAVKH
TKHAX
A1
A2
A3
Address
/ADV
TADVVKH
TKHADVX
µ
TWVKH
TKHWX
/BWENote1
/BWs
TKHWX
TWVKH
/GWNote1
TEVKH
TKHEX
/CEsNote2
/G
TDVKH
TKHDX
High-Z
High-Z
D1(A2)
Data In
TGHQZ
TKHQV
TKHQX1
TGLQX
Q1(A3) Q2(A3)
High-Z
High-Z
High-Z
Q1(A1)
Data Out
Q3(A3)
Q4(A3)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
SINGLE READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
/AC
TAVKH TKHAX
A2
A5
A8
A3
A4
Address
A7
A9
A1
A6
TWVKH TKHWX
/BWE Note1
/BWs
TWVKH TKHWX
/GW Note1
µ
TEVKH
TKHEX
/CEs Note2
/G
TDVKH TKHDX
D1(A5) D1(A6)
High-Z
High-Z
TKHQV
Q1(A8)
Data In
D1(A7)
TGLQV
TGLQX
Q1(A1)
TKHQZ
Q1(A9)
TGHQZ
Note3
High-Z
High-Z
Data Out
Q1(A2) Q1(A3)
Q1(A4)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
2.
Notes
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs are disabled within one clock cycle after deselect.
3.
/AP is HIGH and /ADV is don't care.
Remark
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
µ
/ADV
/BWE
/BWs
/GW
/CEs
/G
High-Z
High-Z
Q1(A1)
Q1(A2)
Q2(A2)
Data Out
TZZE
TZZR
ZZ
Power Down (ISBZZ) State
STOP CLOCK CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
/ADV
µ
/BWE
/BWs
/GW
/CE
/G
High-Z
High-Z
Data In
High-Z
High-Z
Q1(A1)
Q1(A2)
Data Out
Q2(A2)
Note
Power Down State (ISB1
)
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
µPD4482161, 4482181, 4482321, 4482361
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
14.0 0.2
16.0 0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125 0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Data Sheet M14521EJ3V0DS
23
µPD4482161, 4482181, 4482321, 4482361
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4482161, 4482181, 4482321 and 4482361.
Types of Surface Mount Devices
µPD4482161GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482181GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482321GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482361GF : 100-pin PLASTIC LQFP (14 x 20)
Data Sheet M14521EJ3V0DS
24
µPD4482161, 4482181, 4482321, 4482361
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
3rd edition/ Throughout Throughout Modification
−
−
Preliminary Data Sheet → Data Sheet
Extended operating temperature products
(TA = −40 to +85 °C)
Dec. 2002
Addition
p.20
−
Addition
Timing Chart
SINGLE READ / WRITE CYCLE
Data Sheet M14521EJ3V0DS
25
µPD4482161, 4482181, 4482321, 4482361
[MEMO]
Data Sheet M14521EJ3V0DS
26
µPD4482161, 4482181, 4482321, 4482361
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14521EJ3V0DS
27
µPD4482161, 4482181, 4482321, 4482361
•
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
©2020 ICPDF网 联系我们和版权申明