UPD4483362GF-A75 [NEC]
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE; 8M - BIT的CMOS同步快速静态RAM 256K - WORD 36位HSTL接口/寄存器 - 寄存器/后写
| 型号： | UPD4483362GF-A75 |
| 厂家： | 
NEC |
| 描述： | 8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 文件： | 总16页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4483362
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The µPD4483362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The µPD4483362 is suitable for applications which require synchronous operation, high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The µPD4483362 is packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and
low capacitive loading.
Features
• Fully synchronous operation
• HSTL Input / Output levels
• Fast clock access time : 3.8 ns (133 MHz)
• Asynchronous output enable control : /G
• Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
• Common I/O using three-state outputs
• Internally self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• 3.3 V (Chip) / 1.5 V (I/O) supply
• 100-pin PLASTIC LQFP package, 14 mm x 20 mm
• Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
3.8 ns
Clock frequency
133 MHz
Package
µPD4483362GF-A75
100-pin PLASTIC LQFP (14 x 20)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14440EJ1V0DS00 (1st edition)
Date Published April 2001 NS CP(K)
Printed in Japan
2001
©
µPD4483362
Pin Configuration (Marking Side)
/xxx indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[ µPD4483362GF ]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQc9
DQc8
DQc7
VDDQ
VSSQ
DQc6
DQc5
DQc4
DQc3
VSSQ
VDDQ
DQc2
DQc1
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb9
DQb8
DQb7
VDDQ
VSSQ
DQb6
DQb5
DQb4
DQb3
VSSQ
VDDQ
DQb2
DQb1
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
NC
NC
VDD
VSS
ZZ
DQd1
DQd2
VDDQ
VSSQ
DQd3
DQd4
DQd5
DQd6
VSSQ
VDDQ
DQd7
DQd8
DQd9
DQa1
DQa2
VDDQ
VSSQ
DQa3
DQa4
DQa5
DQa6
VSSQ
VDDQ
DQa7
DQa8
DQa9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
2
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
Pin Name and Functions
Pin name
Pin No.
Description
SA0 to SA17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83
DQa1 to DQa9
DQb1 to DQb9
DQc1 to DQc9
DQd1 to DQd9
/SS
63, 62, 59, 58, 57, 56, 53, 52, 51
Synchronous Data Input / Output
68, 69, 72, 73, 74, 75, 78, 79, 80
13, 12, 9, 8, 7, 6, 3, 2, 1
18, 19, 22, 23, 24, 25, 28, 29, 30
98
Synchronous Chip Select
Synchronous Byte Write Enable
Synchronous Byte "a" Write Enable
Synchronous Byte "b" Write Enable
Synchronous Byte "c" Write Enable
Synchronous Byte "d" Write Enable
Asynchronous Output Enable
Asynchronous Sleep Mode
Main Clock Input
/SW
85
/SBa Note1
/SBb Note1
/SBc Note1
/SBd Note1
/G
93
95
96
97
86
ZZ Note2
K, /K
64
89, 88
VDD
15, 41, 65, 91
Core Power Supply
VSS
17, 40, 67, 90
Ground
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
38, 43, 87
Output Buffer Power Supply
Output Buffer Ground
VSSQ
VREF
Input Reference
NC
14, 16, 31, 39, 42, 66, 84, 92, 94
No Connection
Notes 1. If Byte Write Operation is not used, Byte Write Pins (/SBa, /SBb, /SBc, /SBd) are to be tied to VSS.
2. If Sleep Mode is not used, ZZ Pin is to be tied to VSS.
Remark This device only supports Single Differential Clock, R / R Mode.
(R / R stands for Registered Input / Registered Output.)
Preliminary Data Sheet M14440EJ1V0DS
3
µPD4483362
Late Write Block Diagram
18
SA0 to SA17
Address
register
Mux
K
K
Write address
register
/K
/K
/SS
/SS
Write
clock
generator
/SW
/SBa
/SBb
/SBc
/SBd
/SW
/SBa
/SBb
/SBc
/SBd
Memory
cell array
9,437,184 bits
Write
control
logic
Read
comp.
Data Data
in
out
Mux
DQa1 to DQa9
DQb1 to DQb9
DQc1 to DQc9
DQd1 to DQd9
36
Data
in
register
Output
Register
/G
/G
ZZ
ZZ
4
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
Synchronous Truth Table
ZZ
L
/SS
H
L
/SW
×
/SBa
/SBb
/SBc
×
/SBd
Mode
Not selected
Read
DQa1–9 DQb1–9 DQc1–9 DQd1–9 Power
×
×
L
×
×
L
×
×
L
Hi-Z
Dout
Din
Hi-Z
Dout
Din
Hi-Z
Dout
Din
Hi-Z
Dout
Din
Active
Active
Active
Active
Active
Active
Standby
L
H
L
×
L
L
L
Write
L
L
L
L
H
L
H
H
L
Write
Din
Hi-Z
Din
Hi-Z
Din
Hi-Z
Din
L
L
L
H
H
×
L
Write
Hi-Z
Hi-Z
Hi-Z
L
L
L
H
×
H
H
×
Abort Write
Sleep Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
×
×
×
Remark × : Don’t care
Output Enable Truth Table
Mode
Read
/G
L
DQ
Dout
Hi-Z
Hi-Z
Read
H
×
Sleep (ZZ=H)
Write (/SW=L)
Deselect (/SS=H)
×
Hi-Z, Din
Hi-Z
×
Remark × : Don’t care
Preliminary Data Sheet M14440EJ1V0DS
5
µPD4483362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VDD
VDDQ
VIN
Condition
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit
V
Note
1
1
1
1
Output supply voltage
Input voltage
+4.0
V
VDD+0.3
VDDQ+0.3
50
V
Input / Output voltage
Operating temperature
Storage temperature
VI/O
V
TA
°C
°C
Tstg
–55
+125
Note 1. –2.0 V MIN. (Pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 50 °C)
Parameter
Core supply voltage
Symbol
VDD
Conditions
MIN.
3.135
1.4
TYP.
3.3
MAX.
3.465
Unit
V
Output buffer supply voltage
Input reference voltage
Low level input voltage
High level input voltage
VDDQ
VREF
VIL
1.5
1.6
V
0.7
0.75
0.8
V
–0.3 Note
VREF+0.1
VREF–0.1
VDDQ+0.3
V
VIH
V
Note –0.8 V MIN. (Pulse width : 2 ns)
Recommended AC Operating Conditions (TA = 0 to 50 °C)
Parameter
Input reference voltage
Low level input voltage
High level input voltage
Symbol
VREF (RMS)
VIL
Conditions
MIN.
–5%
TYP.
MAX.
+5%
Unit
V
–0.3
VREF–0.2
VDDQ+0.3
V
VIH
VREF+0.2
V
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Note
Input capacitance
Symbol
CIN
Test conditions
MAX.
5.5
Unit
pF
VIN = 0 V
Input / Output capacitance
Clock Input Capacitance
CI/O
VI/O = 0 V
Vclk = 0 V
7.0
pF
Cclk
6.0
pF
Note These parameters are not 100% tested.
6
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
DQ leakage current
Symbol
ILI
Conditions
VIN = 0 to VDD
MIN.
–5
TYP.
MAX.
+5
Unit
µA
ILO
VI/O = 0 to VDDQ
–5
+5
µA
Operating supply current
IDD
VIN = VIH or VIL, /SS = VIL, ZZ = VIL,
Cycle = MAX., IDQ = 0 mA
ZZ = VIH, All other inputs = VIH or VIL,
Cycle = DC, IDQ = 0 mA
350
mA
Sleep mode power supply current
ISBZZ
20
mA
Output Voltage on Push-Pull Output Buffer Mode
Parameter
Low level output voltage
High level output voltage
Symbol
VOL
Conditions
MIN.
–
TYP.
MAX.
0.3
–
Unit
V
IOL = +2 mA
IOH = –2 mA
VOH
VDDQ–0.3
V
Preliminary Data Sheet M14440EJ1V0DS
7
µPD4483362
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
Input waveform (rise and fall time = 0.5 ns (20 to 80%))
1.25 V
V
DDQ / 2
V
DDQ / 2
Test Points
0.25 V
Output waveform
V
DDQ / 2
V
DDQ / 2
Test Points
8
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
Single Differential Clock, Registered Input / Registered Output Mode
Parameter
Symbol
–A75 (133 MHz)
Unit
Notes
MIN.
MAX.
Clock cycle time
tKHKH
tKHKL /
tKLKH
tAVKH
tDVKH
tWVKH
tSVKH
tKHAX
tKHDX
tKHWX
tKHSX
tKHQV
tKHQX
tGLQV
tGLQX
tGHQZ
tKHQZ
tKHQZ2
tKHQX2
tZZR
7.5
2.0
–
–
ns
ns
Clock phase time
Setup times
Address
1.5
0.5
–
–
ns
Write data
Write enable
Chip select
Address
Hold times
ns
Write data
Write enable
Chip select
Clock access time
K high to Q change
/G low to Q valid
–
1.5
–
3.8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
1
2
2
2
2
2
3.8
–
/G low to Q change
/G high to Q Hi-Z
0
0
3.8
3.8
3.8
–
K high to Q Hi-Z (/SW)
K high to Q Hi-Z (/SS)
K high to Q Lo-Z
1.5
1.5
1.5
–
Sleep Mode Recovery
Sleep Mode Enable
7.5
7.5
tZZE
–
Notes 1. See figure. (VTT = 0.75 V)
V
TT
50 Ω
ZO = 50 Ω
DQ (Output)
20 pF
2. See figure. (VTT = 0.75 V)
V
TT
50 Ω
DQ (Output)
5 pF
Preliminary Data Sheet M14440EJ1V0DS
9
µPD4483362
10
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
Preliminary Data Sheet M14440EJ1V0DS
11
µPD4483362
12
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Preliminary Data Sheet M14440EJ1V0DS
13
µPD4483362
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4483362.
Type of Surface Mount Device
µPD4483362GF: 100-pin PLASTIC LQFP (14 x 20)
14
Preliminary Data Sheet M14440EJ1V0DS
µPD4483362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M14440EJ1V0DS
15
µPD4483362
•
The information in this document is current as of April, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
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M8E 00. 4
相关型号：
UPD4483362GF-A75-A
Cache SRAM, 256KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
NEC
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