UPD4565161G5-A75-9JF [NEC]
Synchronous DRAM, 4MX16, 5.4ns, MOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54;
| 型号： | UPD4565161G5-A75-9JF |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM, 4MX16, 5.4ns, MOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总96页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4565421, 4565821, 4565161
64M-BIT VIRTUAL CHANNELTM SDRAM
Description
The 64M-bit Virtual Channel (VC) SDRAM is implemented to be 100% pin and package compatible to the industry
standard SDRAM. It uses the same command protocol and interface as SDRAM. The VC SDRAM command set is a
superset of the SDRAM. It also follows the same electrical and timing specifications of the SDRAM, such that it is
possible for one product platform to be used with the VC SDRAM and non-VC SDRAM part.
Features
• Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Dual internal banks controlled by Bank Select Address
• Sixteen Channels controlled by Channel Select Address
• Quad segments controlled by Segment Select Address
• Byte control (x16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and 16)
• Read latency (1, 2)
• Prefetch Read latency (4)
• Auto precharge and without auto precharge
• Auto refresh and Self refresh
• x4, x8, x16 organization
• Single 3.3 V ± 0.3 V power supply
• Interface: LVTTL
• Refresh cycle: 4 K cycles / 64 ms
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published October 1999 NS CP(K)
Printed in Japan
M13022EJDV0DS00 (13th edition)
The mark • shows major revised points.
1997,1998
©
µPD4565421, 4565821, 4565161
★
Ordering Information
Part number
Organization
Clock
Read
Prefetch
read
Channel
and
Package
(word x bit x bank)
frequency
latency
MHz
latency
4
Interface
(MAX.)
µPD4565421G5-A70-9JFNote
µPD4565421G5-A75-9JF
µPD4565421G5-A10-9JF
µPD4565421G5-A15-9JF
µPD4565821G5-A70-9JFNote
µPD4565821G5-A75-9JF
µPD4565821G5-A10-9JF
µPD4565821G5-A15-9JF
µPD4565161G5-A70-9JFNote
µPD4565161G5-A75-9JF
µPD4565161G5-A10-9JF
µPD4565161G5-A15-9JF
8M x 4 x 2
4M x 8 x 2
2M x 16 x 2
143
133
100
67
2
16 channels
and
54-pin
Plastic
LVTTL
TSOP(II)
(400 mil)
1
2
143
133
100
67
1
2
143
133
100
67
1
Note Under development
2
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Part Number
★
[ x4, x8 ]
µ
PD4 5 65 8 2 1 G5 - A75
NEC Memory
Synchronous DRAM
Data rate
No letter : Single Data Rate
Note
Minimum Cycle Time
D : Double Data Rate
70 : 7 ns (143MHz)
75 : 7.5 ns (133MHz)
10 : 10 ns (100MHz)
15 : 15 ns (67MHz)
Memory Density
64 :
65 :
64M bits Standard SDRAM
64M bits VC SDRAM
128 :
125 :
128M bits Standard SDRAM
128M bits VC SDRAM
Low Voltage
Note
A : 3.3
± 0.3 V
Organization
4 : x4
8 : x8
Package
G5 : TSOP(II)
Number of Banks and Channel
Note
1 : 2 banks and 8 Channels
2 : 2 banks and 16 Channels
3 : 2 banks and 32 Channels
4 : 4 banks and 8 Channels
5 : 4 banks and 16 Channels
6 : 4 banks and 32 Channels
Note
Note
Note
Note
Interface
1 : LVTTL
2 : SSTL
Note
Note Reserved
3
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
[ x16 ]
µ
PD4 5 65 16 1 G5 - A75
NEC Memory
Synchronous DRAM
Data rate
No letter : Single Data Rate
Note
Minimum Cycle Time
D : Double Data Rate
70 : 7 ns (143MHz)
75 : 7.5 ns (133MHz)
10 : 10 ns (100MHz)
15 : 15 ns (67MHz)
Memory Density
64 :
65 :
64M bits Standard SDRAM
64M bits VC SDRAM
128 :
125 :
128M bits Standard SDRAM
128M bits VC SDRAM
Low Voltage
Note
A : 3.3
± 0.3 V
Word and Number of Channel
Note 15 : x16 bits and 8 Channels
16 : x16 bits and 16 Channels
17 : x16 bits and 32 Channels
Package
G5 : TSOP(II)
Note
Number of Banks and Interface
1 : 2 Banks and LVTTL
Note 2 : 2 Banks and SSTL
Note Reserved
4
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pin Configurations
/xxx indicates active low signal.
[µPD4565421]
54-pin Plastic TSOP (II) (400mil)
8M words x 4 bits x 2 banks
V
CC
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
2
NC
V
CC
Q
3
VSSQ
NC
4
NC
DQ3
DQ0
5
V
SS
Q
6
V
CC
Q
NC
NC
Q
7
NC
NC
8
V
CC
9
VSS
Q
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ2
DQ1
V
SS
Q
VCCQ
NC
NC
V
CC
VSS
NC
NC
/WE
/CAS
/RAS
/CS
DQM
CLK
CKE
NC
A11
A9
Bank Address(A13)
A12
Auto Precharge(A10)
A8
A0
A1
A2
A3
A7
A6
A5
A4
V
CC
VSS
A0 - A13
A0 - A12
A0 - A7
DQ0 - DQ3
/CS
:
:
:
:
:
:
:
:
Address inputs
DQM
CKE
CLK
:
:
:
:
:
:
:
:
DQ mask enable
Clock enable
Row address inputs
Column address inputs
Data inputs/outputs
Chip select
System clock input
Supply voltage
Ground
V
V
V
V
CC
SS
CC
/RAS
Row address strobe
Column address strobe
Write enable
Q
Supply voltage for DQ
Ground for DQ
No connection
/CAS
SSQ
/WE
NC
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
5
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
[µPD4565821]
54-pin Plastic TSOP (II) (400mil)
4M words x 8 bits x 2 banks
V
CC
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ7
V
CC
Q
3
VSSQ
NC
DQ1
4
NC
DQ6
5
V
SS
Q
6
VCCQ
NC
DQ2
7
NC
DQ5
8
V
CC
Q
9
VSSQ
NC
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NC
DQ4
V
SS
Q
VCCQ
NC
NC
V
CC
VSS
NC
NC
/WE
DQM
CLK
CKE
NC
A11
A9
/CAS
/RAS
/CS
Bank Address(A13)
A12
Auto Precharge(A10)
A8
A0
A1
A2
A3
A7
A6
A5
A4
V
CC
VSS
A0 - A13
A0 - A12
A0 - A6
DQ0 - DQ7
/CS
:
:
:
:
:
:
:
:
Address inputs
DQM
CKE
CLK
:
:
:
:
:
:
:
:
DQ mask enable
Clock enable
Row address inputs
Column address inputs
Data inputs/outputs
Chip select
System clock input
Supply voltage
Ground
V
V
V
V
CC
SS
CC
/RAS
Row address strobe
Column address strobe
Write enable
Q
Supply voltage for DQ
Ground for DQ
No connection
/CAS
SSQ
/WE
NC
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
6
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
[µPD4565161]
54-pin Plastic TSOP (II) (400mil)
2M words x 1 bits x 2 banks
6
V
CC
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ0
2
DQ15
V
CC
Q
3
VSSQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
Q
6
VCCQ
DQ3
DQ4
7
DQ12
DQ11
8
V
CC
Q
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SS
Q
VCCQ
DQ7
DQ8
V
CC
VSS
LDQM
NC
UDQM
CLK
CKE
NC
A11
A9
/WE
/CAS
/RAS
/CS
Bank Address(A13)
A12
Auto Precharge(A10)
A8
A0
A1
A2
A3
A7
A6
A5
A4
V
CC
VSS
A0 - A13
A0 - A12
A0 - A5
DQ0 - DQ15
/CS
:
:
:
:
:
:
:
:
Address inputs
UDQM
LDQM
CKE
:
:
:
:
:
:
:
:
:
Upper DQ mask enable
Lower DQ mask enable
Clock enable
Row address inputs
Column address inputs
Data inputs/outputs
Chip select
CLK
System clock input
Supply voltage
V
V
V
V
CC
SS
CC
/RAS
Row address strobe
Column address strobe
Write enable
Ground
/CAS
Q
Supply voltage for DQ
Ground for DQ
/WE
SSQ
NC
No connection
Remark Refer to 1. Input/ Output Pin Function for Bank address, Channel address and Segment address.
7
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
VC SDRAM Architecture
The Virtual Channel Memory (VC Memory) is a memory core technology designed to improve memory data
throughput efficiency and initial latency of memories. Intended for use in next generation memory systems, the VC
Memory technology is ideal memory for a wide range of application such as Multimedia PC, Game machine, Internet
Server etc…. The slow core operation memory such as DRAM, Flash Memory and Mask ROM can get very
significant performance improvements with VC Memory technology.
Today's memory subsystems are accessed by multiple tasks/sources (memory masters), working in multitasking
mode. Each memory master accesses memory with an address locality with a time locality, a block size and a
number of contiguous accesses. Virtual Channel Memory architecture is designed for this multitasking, multiple
masters, interleaving access scenarios. The VC Memory provides memory masters with Virtual Channels. Each
channel is a set of resources that constitute a fast dedicated path for each memory masters to access the memory.
The Virtual Channels will minimize the overhead resulting from other memory master's accesses, reduce the access
latency and facilitate automatic data sharing.
Each channel is equipped with a data row buffer and its own independent operating modes. To the memory
masters, this looks like its own very fast memory. The system memory controller associates these channels to the
memory masters for their accesses. Thus, the channels are made to track the accesses of these memory masters.
The system memory controller has complete controls over the operations of the channels. It can schedule and issue
commands that causes segments of memory rows to be loaded into the channels or for data from the channels to be
written back to the memory rows. Any channels can store the data from any rows, can be written to any rows and
hence are fully associative. Then the Read and Write operations will be occurring as much as possible with these
high speed channels, minimizing all overheads associated with the DRAM bank operations.
The Read/Write operations of the channels (foreground operations) can operate independently with the DRAM bank
operations (background operations) of Activate, Precharge, Prefetch (Loading row data to channel) and Restore
(Writing channel data to row). Then VC Memory also further enhances performance by allowing the system memory
controller to schedule the foreground and background operations to operate concurrently.
VC SDRAM architecture offers the following features and benefits:
1. Multiplies the effective data throughput performance of conventional DRAM core.
2. Achieving close to full data bus bandwidth with low latency, interleaved random row, random column Read/Write
through the channels.
3. Transparent DRAM bank operations through the concurrent foreground and Background Operations
4. Very wide (128 bytes wide) internal data transfer bus between Channel and memory core
5. Equivalence of tens of multiple memory banks by using only a fraction of the frequency of Row Activate and
Precharge of conventional DRAM core.
8
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Block Diagram
Address
Channel Control
Address Buffer
and
Refresh counter
Address
Channel Selector
Bank B
Bank A
Mode
register
/CS
/RAS
/CAS
/WE
Memory Cell Array
Row Decoder
DQM
Data Control Circuit
CKE
CLK
Clock Generator
Latch Circuit
Input and Output Buffer
DQ
DQ
9
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Conceptual Schematic 1
Background
Foreground
Prefetch Operation
Restore Operation
Read Operation
Write Operation
Prefetch Operation
(from Segment of memory core
to channel)
Read Operation
( from channel )
DQ
16 Channels
Bank B
Bank A
gSemnt
gSemnt
One segment : 1/4 Row
One segment means
one data transfer size
at the background
operations.
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
Write Operation
( to channel )
DQ
Restore Operation
(from Channel
Row Decoder
to Segment of memory core)
10
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Conceptual Schematic 2
Prefetch Operation
The data is fetched from a segment to any channel buffer.
Bank A
gSemnt
16 Channels
gSemnt
gSemnt
gSemnt
Row Decoder
Bank B
gSemnt
gSemnt
gSemnt
gSemnt
Row Decoder
Restore Operation
The data is transferred from a channel buffer to any segment.
Bank A
gSemnt
16 Channels
gSemnt
gSemnt
gSemnt
Row Decoder
Bank B
gSemnt
gSemnt
gSemnt
gSemnt
Row Decoder
11
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Data size of segment and channel
4 K (4096) bits
1 Row
Memory cell
4 Segments
16 Channels
1 K (1024) bits
One segment means one data transfer size at the prefetch and restore operation.
1 K (1024) bits
1
2
3
4
5
16
x 4 bits organization
One channel density
256 bits
1024 (1K) bits / 4
Column Selector
1024 (1K) bits
Input and Output Buffer
0
1
2
3
x 8 bits organization
One channel density
128 bits
1024 (1K) bits / 8
Column Selector
1024 (1K) bits
Input and Output Buffer
0
1
2
3
4
5
6
7
x 16 bits organization
One channel density
Column Selector
64 bits
1024 (1K) bits / 16
1024 (1K) bits
Input and Output Buffer
3
0
1
2
4
5
6
7
8
9 10111213 1415
12
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
1. Input/Output Pin Function
(1/3)
Pin name
CLK
Input/Output
Input
Function
CLK is the master clock input. Other inputs signals for all commands are
referenced to the CLK rising edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal
clock is not issued and the VC SDRAM suspends operation.
When the VC SDRAM is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
Chip select.
/CS
Input
Input
/CS low starts the command input cycle, which occurs on rising edge of CLK.
During /CS high, commands are ignored but operations continue.
Command Inputs.
/RAS, /CAS, /WE
The combination of these signals defines the command being entered.
For details, refer to the Command Table in Command Functions. The symbol
names (/RAS, /CAS, /WE) do not refer to the functional meanings used for
conventional DRAM.
DQM
Input
For x4, x8 devices
For x8,x4 devices
UDQM LDQM
For x16 device
DQM controls I/O buffers.
For x16 device
UDQM and LDQM control upper byte and lower byte I/O buffers, respectively.
In read mode
DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode
DQM controls the word mask. Input data is written to the memory cell if DQM is
low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ3
DQ0 - DQ7
DQ0 - DQ15
Input/Output
DQ pins have the same function as I/O pins on a Standard Synchronous DRAM.
DQ0 - DQ3 (for x 4 device)
DQ0 - DQ7 (for x 8 device)
DQ0 - DQ15 (for x 16 device)
NC
−
No connect. Leave these pins unconnected.
VCC and VSS are power supply pins for internal circuits.
VCC
(Power supply)
VSS
VCCQ
VSSQ
(Power supply)
VCCQ and VSSQ are power supply pins for the output buffers.
13
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
(2/3)
Pin name
A0 - A13
Input/Output
Input
Function
Address specification. These pins provide memory source and target addresses
(bank, row, column, etc.), and channel addresses.
Row Address
Row Address is determined by A0 - A12 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address
Column Address is determined by A0 - A7 at the CLK rising edge in the read or write
command cycle. It depends on the bit organization.
: A0 - A7 for x4 device
: A0 - A6 for x8 device
: A0 - A5 for x16 device.
Bank Address(A13)
A13 is the bank select signal.
In command cycle, A13 low select bank A, and A13 high select bank B.
14
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
(3/3)
Pin name
A0 - A13
Input/Output
Input
Function
Channel Address(A8, A9, A10, A11, A12)
A8, A9, A11, A12 are the channel select signals.
In prefetch, restore, read and write operations, channel is determined by A8, A9, A11 and A12.
A12
0
Channel number
A11 A9
A8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
2
0
3
0
4
0
5
0
6
0
7
1
8
1
9
1
10
11
12
13
14
15
1
1
1
1
1
In set register operation, channel is determined by A9, A10, A11 and A12.
A12
0
Channel number
A11 A10 A9
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
2
0
3
0
4
0
5
0
6
0
7
1
8
1
9
1
10
11
12
13
14
15
1
1
1
1
1
Segment Address(A0, A1, A10, A13)
A0, A1, A10, A13 are the segment select signals.
In prefetch and restore operations, column address in channel is determined by A0, A1.
In prefetch read operation, segment is determined by A10, A13.
Auto precharge Address(A10)
A10 defines the precharge mode.
In the precharge command cycle
High level: All banks are precharged.
Low level: Only the bank selected by A13 is precharged.
In the prefetch or restore command cycle
High level: Auto precharge
Low level: Without auto precharge
15
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
2. Truth Table
2.1 Command Execution
All commands are executed with the signal combination at the rising edge of the clock (CLK), /CS (Chip Select)
must be low at the command input cycle. CKE (Clock Enable) must be high at one clock before the command input
cycle as shown in below. The state of the /RAS, /CAS, and /WE signals specifies the command function to be
executed. Some commands have the same signal combination for /RAS, /CAS, and /WE and are distinguished by
some of address Input signals. When /CS becomes high, operations continue as specified in the command, but
further commands (signal states that would specify a command) are not registered until /CS becomes low.
This state is Device deselect.
n - 1
n
n + 1
CLK
CKE
/CS
H
L
/RAS
/CAS
/WE
Command
Address
16
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
2.2 Command Truth Table
Function
Symbol /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Device deselect
DESL
NOP
PFC
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
x
H
H
H
H
H
H
H
H
H
L
x
H
H
H
H
H
H
H
L
x
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
L
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
No operation
Prefetch without auto precharge
Pair prefetch
BA Cha. Cha.
BA Cha. Cha.
BA Cha. Cha.
BA Cha. Cha.
BA Cha. Cha.
BA Cha. Cha.
L
L
H
H
L
H
x
Cha. Cha.
Cha. Cha.
Cha. Cha.
Cha. Cha.
Cha. Cha.
Cha. Cha.
L
L
L
L
H
H
L
H
L
H
x
Seg. Seg.
Seg. Seg.
Seg. Seg.
Seg. Seg.
Seg. Seg.
Seg. Seg.
PPF
Prefetch with auto precharge
Pair prefetch with auto precharge
Restore without auto precharge
Restore with auto precharge
Channel read
PFCA
PPFA
RST
RSTA
READ
WRIT
ACT
x
x
Cha. Cha.
Cha. Cha.
Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Channel write
L
L
x
Bank activate
H
H
L
BA Row Row Row Row Row Row Row Row Row Row Row Row Row
Seg. Cha. Cha. Seg. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Prefetch read with auto precharge PFR
L
Precharge selected bank
Precharge all banks
PRE
PALL
SCLR
SCCR
L
BA
x
x
x
L
x
x
L
L
H
L
x
x
L
x
x
x
x
L
L
x
x
L
L
x
x
x
x
x
x
x
x
x
x
L
L
Set register operation
L
L
L
L
L
H
H
H
PRL RL RL RL WT
BL BL BL
L
L
L
Cha. Cha. Cha. Cha.
L
x
x
Remark Abbreviations in the table mean as follows.
: High level : Low level
H
L
X
: High or Low level (Don' t care)
Row : Row address
Col. : Column address
Seg. : Segment address
BA : Bank Address
Cha. : Channel address
BL
: Burst length
RL
: Read Latency
PRL : Prefetch Read Latency
WT : Wrap Type
17
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
2.3 CKE Truth Table
Current state
Function
Symbol
CKE
n–1
/CS
/RAS
/CAS
/WE
Address
n
L
Activating
Any
Clock suspend mode entry
Clock suspend
–
–
H
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
L
Clock suspend
Idle
Clock suspend mode exit
Auto refresh command
Self refresh entry
–
L
H
H
L
x
x
x
x
REF
SELF
–
H
H
L
L
L
L
H
x
L
L
H
x
L
L
H
x
H
H
H
x
Idle
Self refresh
Self refresh exit
H
H
L
L
Idle
Power down entry
Power down exit
–
–
H
L
x
x
x
Power down
H
H
L
x
x
x
H
H
H
Remark H: High level, L: Low level, x: High or Low level (Don' t care)
18
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
3. Commands
Device deselect (DESL)
/CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
High
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Remark x: High or Low level (Don' t care)
The device is deselected state by this command.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0 to A13
19
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
No operation (NOP)
/CS /RAS /CAS /WE
Low High High High
A13 A12 A11 A10 A9
A8
x
A7
x
A6
x
A5
x
A4
x
A3
x
A2
x
A1
x
A0
x
x
x
x
x
x
Remark x: High or Low level (Don' t care)
This command is not a execution command. No operations begin or terminate by this command.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A0 to A13
20
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch without auto precharge (PFC)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. Low Cha. Cha. Low Low Low
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer which is chosen by channel address. The Segment and Bank fields
specify the source segment and bank. In addition, the Channel Address field specifies the destination channel.
A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. In
case of A10: high, with auto precharge operation occurs after data fetch operation. (Please refer to PFCA
command.) (Bank precharge is necessary after data fetch.)
This fetched command can be issued continuously without any precharge operation. For instance, when the first
operation has been done from one of segment on activated row area to one of channel, if the second prefetch
operation is required from same activated row, but different channel, the second prefetch command can be issued
without any precharge operation. tPPD (PFC to PFC/PFCA command period) is required between first and second
prefetch command. When the new row address area need to be activated on same bank, bank precharge is
necessary after this PFC command. tPPL (PFC to PRE command period) is required between PFC and PRE.
Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Valid
Valid
Valid
Bank select
Channel address
Valid
Valid
Channel address
A8
A7
A6
A5
A2 to A4
A1
Valid
Valid
Segment address
A0
21
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair prefetch without auto precharge (PPF)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
A5
x
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. Low Cha. Cha. Low High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a couple of
segments of the activated row in a bank to a couple of channels which are chosen by channel address. (Please
refer to Pair Prefetch Operation.) The Segment and Bank fields specify the source segment and bank. In addition,
the Channel Address field specifies the destination channel.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs.
In case of A10: high, with auto precharge operation occurs after data fetch operation.
(Please refer to PPFA command.)
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Valid
Valid
Valid
Bank select
Channel address
Valid
Valid
Channel address
A8
A7
A6
A2 to A5
A1
Valid
Valid
Segment address
A0
22
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch with auto precharge (PFCA)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. High Cha. Cha. Low Low Low
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer, and precharge operation is performed automatically, which closes the
activated row after data fetch operation.
The Segment and Bank fields specify the source segment and bank.
In addition, the Channel Address field specifies the destination channel.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to PFC command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Valid
Valid
Valid
Bank select
Channel address
Valid
Valid
Channel address
A8
A7
A6
A5
A2 to A4
A1
Valid
Valid
Segment address
A0
23
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair prefetch with auto precharge (PPFA)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
A5
x
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. High Cha. Cha. Low High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a couple of
segments of the activated row in a bank to a couple of channels which are chosen by channel address. Precharge
operation is performed automatically, which closes the activated row after data fetch operation. (Please refer to Pair
Prefetch Operation.) The Segment and Bank fields specify the source segment and bank. In addition, the Channel
Address field specifies the destination channel.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to PPF command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Valid
Valid
Valid
Bank select
Channel address
Valid
Valid
Channel address
A8
A7
A6
A2 to A5
A1
Valid
Valid
Segment address
A0
24
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore without auto precharge (RST)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
x
A5
x
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. Low Cha. Cha. High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by
following ACT command.
The command Bank Address field specifies the destination bank.
The Channel Address fields specify the source channel.
The Segment number field specifies the destination segment.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to RSTA command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Bank select
Valid
Valid
Valid
Channel address
Valid
Valid
Channel address
Segment address
A8
A7
A2 to A6
A1
Valid
Valid
A0
25
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore with auto precharge (RSTA)
/CS /RAS /CAS /WE
Low High High Low
A13 A12 A11 A10 A9
A8
A7
A6
x
A5
x
A4
x
A3
x
A2
x
A1
A0
BA Cha. Cha. High Cha. Cha. High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by
following ACT command.
In addition, precharge operation is performed automatically which closes the active row after data restore
operation.
The command Bank Address field specifies the destination bank.
The Channel Address fields specify the source channel.
The Segment number field specifies the destination segment.
A10 specify the optional precharge operation.
In case of A10: low, without auto precharge operation occurs. (Please refer to RSTA command.)
In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A11
A10
A9
Valid
Valid
Valid
Bank select
Channel address
Valid
Valid
Channel address
Segment address
A8
A7
A2 to A6
A1
Valid
Valid
A0
26
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Channel read (READ)
/CS /RAS /CAS /WE
Low High Low High
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
x
Cha. Cha. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
x
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Read (READ) reads data words from a channel buffer onto the data bus (DQ). The Channel Address field
specifies the source channel. The Column Address field specifies the starting location of the data word in the buffer
(Data words may be 4, 8, or 16 bits.). The burst-length field in the channel control register for the channel specifies
the number of data words to complete the read operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
Valid
Valid
A12
A11
Channel address
A10
Valid
Valid
Valid
A9
Channel address
Column address
A8
A0 to A7
27
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Channel write (WRIT)
/CS /RAS /CAS /WE
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low High Low
Low
Low Cha. Cha. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
x
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Write(WRIT) writes data from the data bus (DQ) into a channel buffer. The Channel Address field specifies
the destination channel. The Column Address field specifies the starting location of the data word in the buffer (Data
words may be 4, 8 or 16 bits.).
The burst-length field in the channel control register for the channel specifies the number of data words to complete
the write operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
Valid
Valid
A12
A11
Channel address
A10
Valid
Valid
Valid
A9
Channel address
Column address
A8
A0 to A7
28
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Bank activate (ACT)
/CS /RAS /CAS /WE
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low
Low High High
BA Row Row Row Row Row Row Row Row Row Row Row Row Row
Remark BA: Bank address, Row: Row address
Activation causes row contents to be placed into the bank's sense amplifier. The command Bank Address and
Row Address fields specify bank and row. This device has two banks, each with 8,192 rows. This command
activates the bank selected by bank address(A13) and a row address selected by A0 through A12. The row remains
active for access until a Precharge command is issued to the bank. A Precharge command must be issued before
another row can be activated in that bank. Each bank can have one row active. This command corresponds to a
conventional DRAM’s /RAS falling.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
Valid
Valid
A13
Bank select
Row address
A0 to A12
29
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch read with auto precharge (PFR)
/CS /RAS /CAS /WE
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Low High Low Seg. Cha. Cha. Seg. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
Remark Seg.: Segment address, Cha.: Channel address, Col.: Column address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the
activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (DQ).
In addition, precharge operation is performed automatically, which closes the activated row after data fetch
operation.
The Segment fields specify the source segment. In addition, the Channel Address field specifies the destination
channel.
The Column Address field specifies the starting location of the data word in the buffer (Data words may be 4, 8, or
16 bits.). The burst-length field in the channel control register for the channel specifies the number of data words to
complete the read operation.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
Valid
A13
Segment address
Valid
Valid
Valid
Valid
Valid
Valid
A12
A11
Channel address
Segment address
Channel address
A10
A9
A8
A0 to A7
Column address
30
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Precharge selected bank (PRE)
/CS /RAS /CAS /WE
Low Low Low Low
A13 A12 A11 A10 A9
BA Low
A8
x
A7
x
A6
x
A5
A4
x
A3
x
A2
x
A1
x
A0
x
x
x
x
Low
Remark BA: Bank address, x: High or Low level (Don' t care)
This command closes (deactivates) an activated row in a bank, in order to prepare the bank for an Activate or
Restore command to activate a new row. After precharging, a bank is in the Idle state.
The Bank field specifies the bank to precharge and A10 Low specifies the command.
After this command, tRP (precharge to activate command period) must be satisfied for next activate command to
precharging bank.
This command corresponds to a conventional DRAM’s /RAS rising.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
Bank select
Valid
A13
A11,A12
A10
A6 to A9
A5
A0 to A4
31
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Precharge all banks (PALL)
/CS /RAS /CAS /WE
A13 A12 A11 A10 A9
High
A8
x
A7
x
A6
x
A5
A4
x
A3
x
A2
x
A1
x
A0
x
Low
Low
Low
Low
x
x
x
x
Low
Remark x: High or Low level (Don' t care)
The signal combination is Reserved (with command modifier A10 High). The PALL command is typically used
during auto refresh operation and initialization. Replace with Precharge commands for each bank.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A11 to A13
A10
A6 to A9
A5
A0 to A4
32
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Set Channel Latency Register (SCLR)
/CS /RAS /CAS /WE
Low Low Low Low
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
RL
A1
A0
Low Low Low Low Low Low Low Low High PRL RL
RL WT
Remark PRL: Prefetch Read Latency, RL: Read Latency, WT: Wrap Type
This command sets the Read Latency value which specifies read delay time in channel read operation.
In addition, this command sets the Wrap type which specifies the order(Sequential or Interleave) in which the burst
data will be addressed.
Moreover, this command sets the Read Latency value which specifies read delay time in prefetch read operation.
The commands can only be executed with all memory banks idle and no burst operations in progress.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A6 to A13
A5
Valid
Valid
Valid
Valid
Valid
Prefetch Read Latency
Read Latency
A4
A3
A2
A1
A0
Wrap Type
33
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Set Channel Control Register (SCCR)
/CS /RAS /CAS /WE
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
x
A3
x
A2
BL
A1
BL
A0
BL
Low Low Low Low Low. Cha. Cha. Cha. Cha. Low Low High High
Remark Cha.: Channel address, BL: Burst Length, x: High or Low level (Don' t care)
This command sets Burst Length in channel address.
Burst Length for the 0-15 channels is the same.
This command is executed during Initialization.
The commands can only be executed with all memory banks idle and no burst operations in progress.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
Valid
Valid
A12
A11
Channel address
Valid
Valid
A10
A9
A7,A8
A5,A6
A3,A4
Valid
Valid
Valid
A2
A1
A0
Burst length
34
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Auto Refresh (REF)
CKE
/CS
Low
/RAS
Low
/CAS
Low
/WE
High
Address
n–1
n
High High
High or Low level (Don' t care)
This command is a request to begin the auto refresh operation. The refresh address is generated internally.
Before executing auto refresh, all banks must be in the idle state. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the VC SDRAM cannot accept any other command.
n−1
n
CLK
CKE
H
H
/CS
/RAS
/CAS
/WE
A0 to A13
35
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Self Refresh (SELF)
CKE
/CS
Low
/RAS
Low
/CAS
Low
/WE
High
Address
n–1
n
High Low
High or Low level (Don' t care)
After the command execution, self refresh operation continues while CKE remains low. During self refresh mode,
the internal refresh controller takes care of refresh interval and refresh operation. There is no need for external
control. Before executing self refresh, both banks must be in the idle state.
During self refresh mode, both background and foreground operation can not be executed.
n−1
n
L
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A0 to A13
36
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
4. Simplified State Diagram
CKE:low
SELF
Power
Down
IDLE
Stand by
Self
Refresh
CKE:high
SELF exit
Set
Auto
Channel Latency
Register
Refresh
Set
Active
Power
Down
Channel Control
Register
Read
Suspend
Write
Suspend
Row
Active
READ
Channel
WRIT
Channel
Read
READ
WRIT
Write
Active
stand by
Prefetch
Read
PFC,
PPF
Restore
Prefetch
Prefetch
Restore
with
with
without
without
Auto Precharge
PRE
Precharge
Auto Precharge
Auto Precharge
Auto Precharge
Automatic sequence
Manual input
PRE
Power ON
foreground
operation
background
operation
37
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
5. Prefetch Read Operation ( Optional )
This operation fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words
from a channel buffer onto the data bus (DQ). In addition, precharge operation is performed automatically, which
closes the activated row after data fetch operation.
When Read latency of SCLR (Set Channel Latency Register) is set up 1, this operation can not be used.
The value of tAPRD may be larger than that of tAPD depending on the product.
Prefetch Operation
Read Operation
DQ
16 Channels
Bank B
Bank A
gSemnt
gSemnt
gSemnt
Prefetch Read Operation
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
DQ
Row Decoder
( Burst length = 4 )
7 8
0
1
2
3
4
5
6
CLK
Command
DQ
t
APD
ACT
PFC
READ
Read latency = 2
Q0
Hi-Z
Q3
Q1
Q2
t
APRD
Command
ACT
PFR
Prefetch read latency = 4
Hi-Z
Q3
DQ
Q0
Q1
Q2
38
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
6. Write Operation and Restore Operation
Write command proceeds write operation to the channel. When the system needs to refill the channel with new
data, restore operation may be necessary. The restore operation needs both restore command and active command.
Restore command must be first command. Restore operation is also fully associative operation.
The data in the channel can be transferred to anywhere on memory core array. Another write and read operation to
another channel can proceed during this restore operation.
The another background operation is illegal while tRAD (RST/RSTA to ACT(R) command delay time).
In addition, the foreground operation to the same channel set by RST command is illegal too.
DQ
16 Channels
Bank B
Bank A
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
gSemnt
Write Operation
( to channel )
DQ
Restore Operation
(from Channel to Segment)
Row Decoder
( Burst length = 2 )
0
1
2
3
4
5
6
7
8
CLK
t
RCD
Command
RST
ACT (R)
READ
WRIT
PRE
t
RAD
t
RAS
Channel 1
Channel
Channel 1
Channel 1
Address
A13
Col. 0
Segment Row 0
Col. 1
BankA
BankA
BankA
BankA
L
without
Auto
Precharge
with
Auto
Precharge
A10
DQM
DQ
Hi-Z
Q1-1
D1-0
D1-1
Remark ACT(R) command is ACT command after RST command.
39
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
7. Pair Prefetch Operation
Pair prefetch operation fetches data from a couple of segments to a couple of channels at one operations. In this
operation, four segments are devided to two segment pairs and sixteen channels are devided to eight channels pairs.
Each pair of segments and channels consists of odd address and even address. In addition, prefetch operation is
from even segment to even channel and from odd segment to odd channel. If the even segment is selected at
command input, the first prefetch operation starts from even segment to even channel. Moreover, if the odd segment
is selected at command input, the first prefetch operation starts from odd segment to odd channel.
The Segment and bank fields specify the source segment and bank. In addition, the Channel Address field
specifies the destination channel.
Prefetch to even channel from even segment.
Prefetch to odd channel from odd segment.
pair
pair
4 Segments
1
0
2
3
0
1
2
3
4
5
6
7
8
9
10 11
pair
12 13
pair
14 15
pair
16 Channels
pair
pair
pair
pair
pair
40
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair prefetch command
CLK
CKE
/CS
H
Command
Valid
/RAS, /CAS, /WE
A0, A1
Odd
Segment address
Channel address
Even
Odd
Even
Valid
Odd
Odd
A8, A9, A11, A12
Even
Even
case2
Illegal
case1
Illegal
Case1. Segment=Even(0) and Channel=Even(6)
1st Prefetch operation is from even segment to even channel
2nd Prefetch operation is from odd segment to odd channel
pair
pair
4 Segments
1
0
2
3
1st prefetch
2nd prefetch
0
1
2
3
4
5
6
7
8
9
10 11
pair
12 13
pair
14 15
16 Channels
pair
pair
pair
pair
pair
pair
Case2. Segment=Odd(3) and Channel=Odd(15)
1st Prefetch operation is from odd segment to odd channel
2nd Prefetch operation is from even segment to even channel
pair
pair
4 Segments
1
0
2
3
2nd prefetch
1st prefetch
0
1
2
3
4
5
6
7
8
9
10 11
pair
12 13
pair
14 15
pair
16 Channels
pair
pair
pair
pair
pair
41
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
8. Set Register Operation
JEDEC standard test set (Refresh counter test)
A13 A12 A11 A10 A9 A7
A8
A8
A8
A8
A6
A6
A6
A6
A5
A5
A5
A5
A4
A4
A4
A3
,
A2
A1
A1
A1
A1
A0
A0
A0
A0
,
Don t
care
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
Don t care
Use in future
A13 A12 A11 A10 A9
A7
A3
A2
Vender specification
A13 A12 A11 A10 A9
A7
A3
A2
,
Valid
data input
Don t care
Valid data input
Mode register set
A13 A12 A11 A10 A9
A7
A4
A3
A2
Valid data input
Valid data input
1
A6(0) Set Channel Latency Register (SCLR)
A6(1) Set Channel Control Register (SCCR)
42
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
9. Set Channel Latency Register (SCLR)
CLK
CKE
/CS
/RAS
/CAS
/WE
A0
H
Valid
Valid
Valid
Valid
Valid
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
1
Wrap type
A0
0
Wrap type
Sequential
Interleave
1
Read latency
A3
A2
0
A1
Read latency
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Reserved
1
0
1
2
1
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
1
Prefetch read latency
A4 Prefetch read latency
0
1
Reserved
4
When Read latency is set up 1,
Prefetch read latency (A4) is don't care.
43
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
10. Set Channel Control Register (SCCR)
CLK
CKE
/CS
/RAS
/CAS
/WE
A0
H
Valid
A1
Valid
Valid
A2
A3
A4
A5
A6
A7
A8
Valid
Valid
Valid
Valid
A9
A10
A11
A12
A13
A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
,
0
0
0
1
Channel address
Channel number
1
Don t care
Burst length
Burst length
A1
0
A0
0
Sequential
Interleave
A2
0
A12
0
Channel number
A11 A10 A9
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
2
0
0
1
0
4
4
0
0
2
1
1
8
8
0
0
3
0
0
16
16
1
0
4
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
5
1
0
1
0
6
1
1
1
0
7
1
8
1
9
1
10
11
12
13
14
15
1
1
1
1
1
44
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
11. Burst Length and Sequence
[Burst of Two]
Starting Address
Addressing Sequence
Addressing Sequence
(column address A0)
Sequential
(decimal)
0, 1
Interleave
(decimal)
0, 1
(binary)
0
1
1, 0
1, 0
[Burst of Four]
Starting Address
Addressing Sequence
Sequential
(decimal)
Addressing Sequence
Interleave
(column address A1,A0)
(binary)
00
(decimal)
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
[Burst of Eight]
Starting Address
Addressing Sequence
Sequential
Addressing Sequence
Interleave
(column address A2-A0)
(binary)
000
(decimal)
(decimal)
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
001
010
011
100
101
110
111
45
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
[Burst of Sixteen]
Starting Address
Addressing Sequence
Addressing Sequence
(column address A3-A0)
Sequential
Interleave
(binary)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(decimal)
(decimal)
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0
2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1
3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2
4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3
5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4
6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5
7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6
8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7
9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8
10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9
11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10
12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11
13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12
14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13
15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14
2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13
3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12
4,5,6,7,0,1,2,3,12,13,14,15,8,9,10,11
5,4,7,6,1,0,3,2,13,12,15,14,9,8,11,10
6,7,4,5,2,3,0,1,14,15,12,13,10,11,8,9
7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8
8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7
9,8,11,10,13,12,15,14,1,0,3,2,5,4,7,6
10,11,8,9,14,15,12,13,2,3,0,1,6,7,4,5
11,10,9,8,15,14,13,12,3,2,1,0,7,6,5,4
12,13,14,15,8,9,10,11,4,5,6,7,0,1,2,3
13,12,15,14,9,8,11,10,5,4,7,6,1,0,3,2
14,15,12,13,10,11,8,9,6,7,4,5,2,3,0,1
15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
46
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
12. Initialization
The VC SDRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.
After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more auto refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
47
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and Auto Refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
Voltage on power supply pin relative to GND VCC, VCCQ
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
VT
IO
V
mA
W
PD
TA
1
Operating ambient temperature
Storage temperature
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC, VCCQ
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
2.0
V
CC + 0.3Note1
V
VIL
–0.3Note2
0.8
V
TA
0
70
°C
Notes 1. VIH (MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns)
2. VIL (MIN.) = –1.5 V (Pulse width ≤ 5 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CI
Test condition
MIN.
TYP.
MAX.
4
Unit
pF
A0 - A13,CLK, CKE, /CS,
/RAS, /CAS, /WE,
DQM, UDQM, LDQM
DQ
2.5
Data input/output capacitance
CI/O
4
6.5
pF
48
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
Grade
Maximum.
Unit Notes
x4
90
x8
90
x16
90
Operating current
( Prefetch mode at one
bank active )
ICC1P tRC ≥ tRC(MIN.)
-A70
-A75
-A10
-A15
-A70
-A75
-A10
-A15
mA
mA
1
1
Prefetch is executed one time during tRC.
85
80
70
90
85
80
70
1
85
80
70
90
85
80
70
1
85
80
70
90
85
80
70
1
Operating current
( Restore mode at one
bank active )
ICC1R tRC ≥ tRC(MIN.)
Precharge standby current
in power down mode
CKE ≤ VIL(MAX.), tCK = 15 ns
CKE ≤ VIL(MAX.), tCK = ∞
mA
mA
ICC2P
0.5
25
0.5
25
0.5
25
ICC2PS
Precharge standby current
in non power down mode
ICC2N CKE ≥ VIH(MIN.), tCK = 15 ns
/CS≥VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞
Input signals are stable.
8
8
8
Active standby current in
power down mode
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
5
4
5
4
5
4
mA
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns
/CS ≥ VIH(MIN.)
25
25
25
Input signals are changed one time during 30 ns.
ICC3NS CKE≥VIH(MIN.),tCK=∞
Input signals are stable.
10
10
10
Operating current
(Burst mode)
tCK ≥ tCK(MIN.),
-A70
-A75
-A10
-A15
60
60
45
35
70
65
50
40
100
95
mA
mA
mA
2
3
ICC4
ICC5
ICC6
IO = 0 mA,
Background: precharge standby
75
60
Auto refresh current
tRCF ≥ tRCF(MIN.)
-A70 145 145
-A75 135 135
-A10 115 115
-A15 110 110
145
135
115
110
1
Self refresh current
CKE ≤ 0.2 V
1
1
★
Notes 1. ICC1 depends on cycle rates. In addition to this, ICC1 is measured on condition that addresses are changed
only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
II(L)
Test condition
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4 mA
MIN. TYP. MAX. Unit
Note
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
µA
µA
V
– 1.0
– 1.5
2.4
–
–
–
–
+ 1.0
+ 1.5
–
IO(L)
VOH
VOL
IO = + 4 mA
V
–
0.4
49
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
• AC measurements assume tT = 1 ns.
• Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL.
• If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH(MIN.) and VIL(MAX.).
• An access time is measured at 1.4 V.
t
CK2
t
CK2
t
CH
t
CL
t
CH
t
CL
CLK
CKE
t
CKH
t
CKS
t
S
t
H
Command
Address
DQM
(Input)
Valid
t
DS
t
DH
t
DS
t
DH
Data (Input)
Valid
Valid
t
AC2
t
AC2
t
LZ
t
OH2
t
HZ
Hi-Z
Hi-Z
Data (Output)
Valid
Valid
50
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
AC characteristics
Parameter
Symbol
-A70
-A75
-A10
-A15
Unit
Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
tCK
tAC
tCH
tCL
7
−
5.4
−
7.5
−
−
5.4
−
10
−
3
3
3
0
3
2
1
2
1
2
1
2
1
−
2
−
6
15
−
3
3
3
0
3
2
1
2
1
2
1
2
1
−
2
−
12
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CLK
Access time from CLK
CLK high level width
−
1
1
2.5
2.5
2.7
0
2.5
2.5
2.7
0
−
CLK low level width
−
−
−
−
Data-out hold time
tOH
tLZ
−
−
−
−
Data-out low-impedance time
Data-out high-impedance time
Data-in setup time
−
−
−
−
tHZ
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
−
5.5
−
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
−
5.5
−
6
6
tDS
tDH
tS
−
−
Data-in hold time
−
−
−
−
Address, Command, DQM setup time
Address, Command, DQM hold time
CKE setup time
−
−
−
−
tH
−
−
−
−
tCKS
tCKH
tCKSP
tT
−
−
−
−
CKE hold time
−
−
−
−
CKE setup time (Power down exit)
Transition time
−
−
−
−
30
64
−
30
64
−
30
64
−
30
64
−
Refresh time (4,096 refresh cycle)
Mode register set cycle time
tREF
tRSC
2
2
Note1 Output load.
Z = 50Ω
Output
50pF
51
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
AC characteristics (Background to Background operation)
Parameter
Symbol
-A70
-A75
-A10
-A15
Unit
Notes
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SAME BANK OPERATION
ACT to ACT/REF Command period
REF to REF/ ACT Command period
ACT to PRE Command period
tRC
tRCF
tRAS
tRP
70
70
49
20
15
−
67.5
67.5
52.5
20
−
80
90
60
20
20
−
90
90
60
30
30
−
ns
ns
ns
ns
ns
−
−
−
−
120,000
120,000
120,000
120,000
PRE to ACT / REF Command period
−
−
−
−
−
−
−
−
ACT to PFC/PFCA/PPF/PPFA
Command delay time
tAPD
15
ACT to PFR Command delay time
(Prefetch Read Operation)
tAPRD
20
−
20
−
20
−
TBD
−
ns
3
PFC to PRE Command delay time
tPPL
tPAL
tPPP
tPPA
tRAD
21
42
42
63
7
−
−
22.5
45
−
−
30
50
60
80
10
−
−
30
60
75
90
10
−
−
ns
ns
ns
ns
ns
PFCA / PFR to ACT/REF Command delay time
PPF to PRE Command delay time
−
45
−
−
−
PPFA to ACT/REF Command delay time
RST / RSTA to ACT(R) Note1 Command delay time
−
67.5
7.5
−
−
−
28
30
40
60
2
SAME,OTHER BANK OPERATION
ACT(R) Note1 to PFC/PFCA/PFR/PPF/PPFA
Command delay time
tRPD
35
−
37.5
−
40
−
45
−
ns
PFC to PFC / PFCA Command delay time
tPPD
21
42
−
−
22.5
45
−
−
30
60
−
−
30
75
−
−
ns
ns
PPF to PPF / PPFA Command delay time
tPPPD
OTHER BANK OPERATION
ACT to ACT/ACT(R) or ACT(R) to ACT
Command delay time
tRRD
14
−
15
−
20
−
30
−
ns
ACT(R) to ACT(R) Command delay time
tRRDR
tPRD
28
21
42
−
−
−
30
22.5
45
−
−
−
40
30
60
−
−
−
45
30
75
−
−
−
ns
ns
ns
PFC /PFCA to RST /RSTA Command delay time
PPF /PPFA to RST /RSTA Command delay time
tPPRD
Notes 1 ACT(R) command is ACT command after RST command.
2 The another background operation and same channel foreground operation are illegal while tRAD period.
3 When Read latency of SCLR (Set Channel Latency Register) is set up 1, this operation can not used.
52
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
AC characteristics (Foreground to Foreground operation)
Parameter
Symbol
-A70
-A75
-A10
-A15
Unit Note
ns
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ/WRITE to READ/WRITE
Command delay time
tCCD
7
−
7.5
−
10
−
15
−
AC characteristics (Background to Foreground operation)
(after same channel Prefetch/Restore)
Parameter
Symbol
-A70
-A75
-A10
-A15
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tPCD
14
35
−
−
15
−
−
20
50
−
−
30
75
−
−
ns
ns
PFC/PFCA/PPF/PPFA to READ/WRITE
Command delay time
tPPCD
37.5
PPF/PPFA to READ/WRITE
Command delay time
(2nd prefetch channel read write)
ACT(R) to READ/WRITE
tRCD
28
−
30
−
40
−
45
−
ns
1
Command delay time
Note1 ACT(R) command is ACT command after RST command.
53
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Power on Sequence and Auto Refresh
0
1
2
3
4
5
6
7
8
16
17
25
26
CLK
SCLR
REF
REF
ACT
Command PALL
SCCR
SCCR
t
RP
t
RSC
t
RSC
t
RSC
t
RCF
t
RCF
Read latency
Wrap type
Burst length
Channel
Burst length
Channel
Row 1
BankA
Address
A10
A7, A8
A6
H
L
L
L
L
L
H
H
A5
It is necessary to input SCCR command 16 times
(16 channels)
to set burst length for channel.
DQM
DQ
Hi-Z
1st
SCCR
2nd
SCCR
54
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
/CS Function (Only /CS signal needs to be issued at minimum rate)
( Read latency = 2, Burst length = 2 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
H
CKE
/CS
/RAS
/CAS
/WE
Bank
Row
Row
Row
Row
Row
Bank
A13
Channel
Channel
Channel
A8,A9,A11,A12
A10
Column
Column
Column
Column
Column
Column
A5,A6,A7
A2,A3,A4
A0,A1
Segment
DQM
DQ
L
Hi-Z
Q1-0 Q1-1
D1-0
D1-1
Command
ACT
PFC
READ
WRIT
55
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Clock Suspension during Burst Read (using CKE Function)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
t
APD
t
PCD
Command
ACT
PFC
READ
Channel
1
Channel
1
Channel
Segment
1
Address
A13
Row 0
BankA
Col. 0
BankA
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q1-0 Q1-1
Q1-2
Q1-3
1 clock
suspend
2 clocks
suspend
3 clocks
suspend
56
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Clock Suspension during Burst Write (using CKE Function)
( Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
t
APD
t
PCD
Command
ACT
PFC
WRIT
Channel
1
Channel
1
Channel
Segment
1
Address
A13
Row 0
BankA
Col. 0
BankA
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
D1-0
D1-1
D1-2
D1-3
1 clock
suspend
2 clocks
suspend
3 clocks
suspend
57
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Power Down Mode
( Read latency = 2, Burst length = 2 )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
t
CKSP
t
CKSP
PFC
PRE
Command ACT
Channel
READ
Channel
1
Channel
1
Segment
1
Address
Row 0
Col. 0
A13 BankA
A10
BankA
BankA
L
without
Auto
Precharge
DQM
DQ
L
Hi-Z
Q1-0 Q1-1
Power down mode
entry
Power down mode
exit
Power down mode
entry
Power down mode
exit
Active standby
Precharge standby
58
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Set Register Operation
0
1
2
3
4
5
6
7
8
CLK
t
RSC
t
RSC
Command
Channel
SCLR
SCCR
SCLR
Read latency,
Wrap type
Channel,
Burst lenght
Read latency,
Wrap type
Address
A6
H
L
L
L
L
L
A7 to A8
DQM
DQ
L
Hi-Z
59
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read Operation
( Burst length = 4 )
0
1
2
3
4
CLK
Command
READ
Read latency = 2
L
DQM
Hi-Z
DQ
Q1
Q3
Q2
Q0
Write Operation
( Burst length = 4 )
0
1
2
3
CLK
WRIT
Command
Write latency = 0
DQM
DQ
L
D1
D2
D3
D0
60
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
DQM Operation in READ
( Burst length = 4 )
CLK
DQM
Read mask latency = 2
Mask
Hi-Z
DQ
Hi-Z
Q0
Q1
Q3
DQM Operation in WRITE
( Burst length = 4 )
CLK
DQM
Write mask latency = 0
DQ
D1
D3
Mask
Mask
61
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Read Operation
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
Command
Channel
READ
READ
Channel 3
Col. 0
t
CCD
Channel 1
Address
DQM
Col. 0
L
Hi-Z
DQ
Q3-3
Q1-0
Q1-1
Q1-2
Q1-3
Q3-0
Q3-1
Q3-2
Write to Write Operation
( Burst length = 4 )
8
0
1
2
3
4
5
6
7
CLK
Command
WRIT
WRIT
Channel 3
Col. 0
t
CCD
Channel
Channel 1
Col. 0
Address
DQM
L
Hi-Z
DQ
D1-0
D1-1
D1-2
D1-3
D3-0
D3-1
D3-2
D1-3
62
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Write Operation
( Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
Command
Channel
READ
Channel 1
Col. 0
WRIT
t
CCD
Channel 3
Address
DQM
Col. 0
L
Hi-Z
DQ
Q1-0
Q1-1
Q1-2
D3-0
D3-1
D3-2
D3-3
Write to Read Operation
( Burst length = 8 )
7 8
0
1
2
3
4
5
6
CLK
Command
WRIT
READ
Channel 3
Col. 0
t
CCD
Channel 1
Col. 0
Channel
Address
DQM
L
Hi-Z
Hi-Z
DQ
D1-0
D1-1
D1-2
Q3-0
Q3-1
Q3-2
Q3-3
63
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
t
APD
t
PCD
Command
ACT
PFC
READ
PRE
ACT
t
RAS
t
RP
Channel 1
Channel
Channel 1
t
RC
Address
A13
Row 0
BankA
Segment
BankA
Col. 0
Row 1
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Prefetch to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
t
PPL
Command
ACT
PFC
READ
PRE
READ
Channel 5
Col. 7
Channel
Channel 1 Channel 4
Segment
Col. 0
Address
A13
Row 0
BankA
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q4-0
Q4-1
Q4-2
Q5-7
64
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
8
0
1
2
3
4
5
6
7
CLK
t
APD
t
PCD
Command
ACT
PFC
WRIT
PRE
ACT
t
RAS
t
RP
Channel 1
Channel 1
Channel
t
RC
Address
A13
Row 0
BankA
Segment
BankA
Col. 0
Row 1
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
D1-0
D1-1
D1-2
D1-3
Prefetch to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
7 8
0
1
2
3
4
5
6
CLK
t
PPL
Command
ACT
PFC
WRIT
PRE
WRIT
Channel 3
Channel 4
Col. 0
Channel
Channel 1
Address
A13
Segment
BankA
Row 0
BankA
Col. 7
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
D3-9
D4-0
D4-1
D4-2
D3-7
D3-8
65
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
t
APD
t
PPL
Command
READ
ACT
PFC
READ
Channel 1
Col. 7
PRE
t
PCD
Channel 1
Channel 1
Channel
Address
A13
Segment
BankA
Col. 0
Row 0
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Q1-7
Q1-8
Prefetch
Termination
66
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
t
APD
t
PPL
Command
READ
ACT
PFC
WRIT
PRE
t
PCD
Channel 1
Channel
Channel 1
Col. 3
Channel 1
Address
A13
Segment
BankA
Col. 0
Row 0
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Prefetch Termination
D1-3 D1-4 D1-5
Hi-Z
Q1-0
Q1-1
Q1-2
D1-6
67
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Write to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Burst length = 8 )
7 8
0
1
2
3
4
5
6
CLK
t
APD
t
PPL
Command
WRIT
ACT
PFC
WRIT
PRE
t
PCD
Channel 1
Channel 1
Channel 1
Col. 1
Channel
Address
A13
Col. 0
Row 0
BankA
Segment
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Prefetch Termination
D1-1 D1-2
MASK
D1-4
Hi-Z
D1-0
D1-1
D1-2
D1-3
D1-3
68
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Write to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
t
APD
t
PPL
Command
WRIT
Channel 1
Col. 0
ACT
PFC
READ
PRE
t
PCD
Channel 1
Channel
Channel 1
Address
A13
Row 0
BankA
Segment
BankA
Col. 1
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Prefetch Termination
MASK
D1-4
Hi-Z
D1-0
D1-1
D1-2
D1-3
Q1-1
69
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
t
RCD
RST
ACT (R)
Command
READ
Channel 1
Col. 0
PRE
t
RAD
t
RAS
Channel 1
Channel
Address Segment
Row 0
BankA
A13
A10
BankA
BankA
L
without
Auto
Precharge
DQM
DQ
L
Hi-Z
Q1-0
Q1-1
Q1-2
Remark ACT(R) command is ACT command after RST command.
70
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
RST
ACT (R)
Command
READ
PRE
t
RAD
t
RAS
Channel
Channel 7
Col. 0
Channel 1
Address
A13
Segment Row 0
BankA
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q7-0
Q7-1
Q7-2
Q7-3
Remark ACT(R) command is ACT command after RST command.
71
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
7 8
0
1
2
3
4
5
6
CLK
t
RCD
RST
ACT (R)
Command
WRIT
Channel 1
Col. 0
PRE
t
RAD
t
RAS
Channel 1
Channel
Address Segment
Row 0
BankA
A13
A10
BankA
BankA
L
without
Auto
Precharge
DQM
DQ
L
Hi-Z
D1-0
D1-1
D1-2
D1-3
Remark ACT(R) command is ACT command after RST command.
72
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
7 8
0
1
2
3
4
5
6
CLK
Command
RST
ACT (R)
WRIT
PRE
t
RAD
t
RAS
Channel 1
Channel 3
Col. 0
Channel
Address Segment
Row 0
BankA
A13
A10
BankA
BankA
L
without
Auto
Precharge
DQM
DQ
L
Hi-Z
D3-0
D3-1
D3-2
D3-3
Remark ACT(R) command is ACT command after RST command.
73
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
CLK
t
RCD
Command
RST
ACT (R)
READ
READ
PRE
t
RAD
t
RAS
Channel 1
Channel 1
Channel 1
Channel
Address
A13
Col. 0
Segment
BankA
Row 0
BankA
Col. 4
BankA
L
without
Auto
Precharge
A10
DQM
DQ
L
Restore Termination
Hi-Z
Q1-0
Q1-1
Q1-4
Remark ACT(R) command is ACT command after RST command.
74
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
t
RCD
Command
RST
ACT (R)
READ
Channel 1
Col. 0
WRIT
Channel 1
Col. 5
PRE
t
RAD
t
RAS
Channel 1
Channel
Address
A13
Segment
BankA
Row 0
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Restore Termination
Hi-Z
D1-7
Q1-0
Q1-1
D1-5
D1-6
Remark ACT(R) command is ACT command after RST command.
75
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Write to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Burst length = 8 )
7 8
0
1
2
3
4
5
6
CLK
t
RCD
Command
RST
ACT (R)
WRIT
Channel 1
Col. 0
WRIT
Channel 1
Col. 1
PRE
t
RAD
t
RAS
Channel 1
Channel
Address
A13
Segment
BankA
Row 0
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
Restore Termination
MASK
D1-2
Hi-Z
D1-3
D1-0
D1-1
D1-1
D1-2
Remark ACT(R) command is ACT command after RST command.
76
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Write to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
CLK
t
RCD
Command
RST
ACT (R)
WRIT
READ
Channel 1
Col. 1
PRE
t
RAD
t
RAS
Channel 1
Channel
Channel 1
Address
A13
Col. 0
Segment
BankA
Row 0
BankA
BankA
L
without
Auto
Precharge
A10
DQM
DQ
MASK
D1-2
Restore Termination
Hi-Z
D1-0
D1-1
Q1-1
Remark ACT(R) command is ACT command after RST command.
77
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch to Prefetch Operation without Auto Precharge
0
1
2
3
4
5
6
7
8
9
10
CLK
t
RRD
t
APD
t
PPD
t
PPD
Command
ACT
ACT
PFC
PFC
PFC
Channel
Channel 1
Channel 8
Channel 2
Segment 1
BankB
Segment 2
BankB
Segment 3
BankA
Address
A13
Row 0
BankA
Row 1
BankB
without
Auto
Precharge
without
Auto
Precharge
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
78
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch to Restore Operation without Auto Precharge (Other Bank Restore)
0
1
2
3
4
5
6
7
8
CLK
t
APD
t
PRD
Command
RST
ACT (R)
ACT
PFC
t
RAD
Channel 1
Channel
Channel 2
Address
A13
Segment 1
BankA
Segment 1
BankB
Row 0
BankA
Row 0
BankB
without
Auto
Precharge
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Remark ACT(R) command is ACT command after RST command.
79
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Prefetch Operation with Auto Precharge
0
1
2
3
4
5
6
7
8
9
CLK
t
PAL
t
APD
Command
ACT
PFC A
ACT
t
RC
Channel 1
Channel
Address
A13
Segment 1
BankA
Row 0
BankA
Row 0
BankA
Auto
A10
Precharge
DQM
DQ
L
Hi-Z
80
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore to Prefetch Operation without Auto precharge
0
1
2
3
4
5
6
7
8
CLK
t
RAD
t
RAS
Command
RST
ACT (R)
RST
ACT (R)
PRE
PFC
t
RPD
t
RAD
t
RRDR
Channel 1
Channel Channel 2
Address Segment 1
Channel 1
Segment 2
BankB
Segment 3
BankB
Row 0
BankA
Row 1
BankB
A13
A10
BankA
BankA
L
without
Auto
Precharge
without
Auto
Precharge
without
Auto
Precharge
DQM
DQ
L
Hi-Z
Remark ACT(R) command is ACT command after RST command.
81
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Restore Operation with Auto Precharge
0
1
2
3
4
5
6
7
8
9
CLK
t
RAD
t
RC
Command
RSTA
ACT (R)
RST
ACT (R)
ACT
t
RAD
t
RRDR
Channel 2
Channel 1
Channel
Address Segment 1
Segment 3
BankB
Row 0
BankA
Row 1
BankB
Row 0
BankA
A13
A10
BankA
without
Auto
Precharge
Auto
Precharge
DQM
DQ
L
Hi-Z
Remark ACT(R) command is ACT command after RST command.
82
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Burst length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK
t
APRD
t
PAL
Command READ
ACT
PFR
ACT
t
RC
Channel 1
Channel
Channel 1
PRL=4
(Prefetch Read Latency)
Illegal to input any other
background operation.
Address
A13
Col. 8
Row 0
BankA
Col. 0
Row 1
BankA
Segment
Segment
A10
DQM
DQ
L
READ will be interrupted by PFR.
Q1-10 Q1-11
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Q1-4
Q1-8
Q1-9
83
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Write to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Burst length = 8)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
t
APRD
t
PAL
Command
WRIT
ACT
PFR
ACT
t
RC
Channel 1
Channel 1
Channel
PRL=4
(Prefetch Read Latency)
Illegal to input any other
background operation.
Address
A13
Col. 8
L
Row 0
BankA
Col. 0
Row 1
BankA
Segment
Segment
A10
DQM
DQ
L
WRIT will be interrupted by PFR.
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
D1-8
D1-9
D1-10
D1-11
84
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair Prefetch Operation
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
t
APD
t
PCD
t
RP
t
PPP
Command READ
ACT
PPF
READ
READ
PRE
ACT
t
PPCD
Channel 1
Channel
Channel 7
Channel 6
Channel 7
Illegal to input channel 6
(2nd prefetch channel)
Address
A13
Col. 8
Row 0
BankA
Segment 1
Col. 0
Col. 0
Row 1
BankA
BankA
BankA
Bank
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q7-0
Q7-1
Q7-2
Q6-0
Q1-8
Q1-9
Q1-10
Q1-11
Q6-1
85
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair Prefetch Operation with Auto Precharge
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
t
APD
t
PCD
t
PPCD
Command READ
ACT
PPFA
READ
READ
ACT
t
PPA
Channel 1
Channel
Channel 8
Channel 9
Channel 8
Illegal to input channel 9
(2nd prefetch channel)
Address
A13
Col. 8
Row 0
BankA
Segment 2
BankA
H
Col. 0
Col. 0
Row 1
BankA
A10
DQM
DQ
L
Hi-Z
Q8-0
Q8-1
Q8-2
Q9-0
Q1-8
Q1-9
Q1-10
Q1-11
Q9-1
86
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Pair Prefetch to Pair Prefetch Operation
( Read latency = 2, Burst length = 4 )
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
t
APD
t
PCD
Command READ
ACT
PPF
READ
PPF
t
PPPD
Channel 1
Channel
Channel 7
Channel 3
Channel 7
Illegal to input channel 6
(2nd prefetch channel)
Address
A13
Col. 8
Row 0
BankA
Segment 1
Col. 0
Segment 3
BankA
BankA
without
Auto
Precharge
without
Auto
Precharge
A10
DQM
DQ
L
Hi-Z
Q7-0
Q7-1
Q7-2
Q7-3
Q1-8
Q1-9
Q1-10
Q1-11
87
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Read to Pair Prefetch to Write Operation (Same Channel Prefetch)
( Read latency = 2, Burst length = 8 )
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
t
APD
t
PCD
t
RP
Command READ
ACT
PPF
WRIT
PRE
ACT
t
PPP
Channel 6
(Channel 7)
Channel 7
Channel 7
Channel
Illegal to input channel 6
(2nd prefetch channel)
Address
A13
Col. 8
Row 0
BankA
Segment 1
Col. 0
Row 1
BankA
BankA
BankA
Bank
without
Auto
Precharge
A10
DQM
DQ
Hi-Z
D7-0
D7-1
D7-2
D7-3
D7-4
D7-5
D7-6
Q6-8
Q6-9
Q6-10
Prefetch Termination
88
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Auto Refresh Operation
0
1
2
3
4
9
10
11
12
CLK
t
RP
t
RCF
Command
PALL
H
REF
ACT
Address
A10
DQM
DQ
L
Hi-Z
89
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Self Refresh Operation (Entry and Exit)
0
1
2
3
4
5
6
96
97
98
99
100 101
108 109
CLK
CKE
t
RP
t
RCF
Command
PALL
REF
ACT
Address
A10
H
DQM
DQ
L
Self refresh entry
Self refresh exit
90
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
14. Package Drawing
★
54PIN PLASTIC TSOP (II) (400mil)
54
28
detail of lead end
F
P
E
1
27
A
H
I
J
G
S
L
C
N
S
B
K
D
M
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
22.22±0.05
0.91 MAX.
0.80 (T.P.)
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
+0.08
0.32
D
−0.07
E
F
G
H
I
0.10±0.05
1.1±0.1
1.00
11.76±0.20
10.16±0.10
0.80±0.20
J
+0.025
0.145
K
−0.015
L
M
N
0.50±0.10
0.13
0.10
+7°
3°
P
−3°
S54G5-80-9JF-1
91
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
15. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the PD4565
.
×××
µ
Type of Surface Mount Device
PD4565421G5 : 54-pin Plastic TSOP (II) (400 mil)
µ
PD4565821G5 : 54-pin Plastic TSOP (II) (400 mil)
µ
PD4565161G5 : 54-pin Plastic TSOP (II) (400 mil)
µ
92
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
Revision History
(1/2)
16.
Edition /
Date
Page
Description
Location
This
Previous
edition
Type of
revision
edition
10th edition / Throughout Throughout Modification Clock frequency (-A75)
Feb. ‘99
p.1
p.1
Modification Tittle
p.3, 4
p.3, 4
Addition
Deletion
Note (D : Double Data Rate)
Note (128 : 128M bits Standard SDRAM)
X32
p.4
p.4
Deletion
Modification
Deletion
Deletion
Deletion
Addition
Word and Number of Channel, Number of Banks and interface
PD4565422
PD4565822
PD4565162
p.5
p.6
p.5
p.6
µ
µ
µ
p.7
p.7
WT : Wrap Type
p.17
p.41
p.52
p.55
p.17
p.41
p.52
p.55
tAPD, tAPED (Timing Chart)
Addition
Note 1, Note 2 (Recommended Operating Conditions)
tCK2 (Symbol)
Addition
Modification
tAC2 (Symbol, -A70 (MAX.), -A75 (MAX.))
tOH2 (Symbol, -A70 (MIN.), -A75 (MIN.))
tDS, tDH, tS, tH, tCKS, tCKH, tCKSP, tT (-A70 (MIN.), -A75 (MIN.))
tRC, tRCF (-A75 (MIN.))
p.56
p.87
p.56
p.87
Modification
tRCPD (-A75 (MIN.), -A10 (MIN.))
tAPD (Parameter)
tAPRD (Parameter, -A15 (MIN.), Note)
Timing Chart (Read to Prefetch Read with Auto Precharge Operation)
Timing Chart (Write to Prefetch Read with Auto Precharge Operation)
16. Recommended Soldering Conditions
Modification
Deletion
11th edition /
June, ‘99
p.1
p.2
p.15
p.17
p.18
-
p.1
Features : One channel for write buffer (Dummy Channel)
Note (A75L, A10L, A15L)
p.2
p.15
p.17
p.18
p.23
p.30
p.31
p.37
p.40
p.43
A13 , Channel number 16
Deletion
PDF , WRD , WRDA
Modification Power down exit
Deletion Prefetch to dummy without auto precharge (PFD)
-
Dummy channel write without auto restore (WRD)
Dummy channel write with auto restore (WRDA)
-
p.34
p.37
-
Modification Set Channel Control Register (SCCR)
Simplified State Diagram
Deletion
Dummy Channel
93
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
(2/2)
Edition /
Date
Page
Description
Location
This
Previous
edition
Type of
revision
edition
11th edition /
June, ‘99
p.44
p.49
p.51
p.52
p.48
p.53
p.55
p.56
Modification Set Channel Control Register (SCCR)
ICC6 (-AxxL)
Note1
Deletion
tRCPD, tDAL
Modification
Modification
tAPD, tRPD
p.53
p.54
p.57
p.58
tPCD
Power on Sequence and Auto Refresh
Prefetch to Dummy and Write to Dummy with Auto Restore
-
-
-
p.89
p.90
p.91
Deletion
Operation
Prefetch to Dummy and Write to Dummy with Auto Restore
Operation
Prefetch to Dummy, Write to Dummy and write to Dummy with Auto
Restore Operation
12th edition /
July, ‘99
p.17
p.38
p.49
p.2
p.17
p.38
p.49
p.2
Modification SCCR (A13)
Addition
Modification
Deletion
5th line
I
CC5
(Test condition)
13th edition /
Oct. ‘99
Low Power Operation
p.3
p.3
p.49
p.91
p.49
p.91
CC5
I
(-AxxL)
Modification
Package Drawing
94
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
95
Data Sheet M13022EJDV0DS00
µPD4565421, 4565821, 4565161
[MEMO]
VIRTUAL CHANNEL is a trademark of NEC Corporation.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
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• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
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• Descriptions of circuits, software, and other related information in this document are provided for illustrative
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of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
相关型号：
UPD4565421G5-A75L-9JF
Synchronous DRAM, 16MX4, 5.4ns, MOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
NEC
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