UPD4664312F9-B65X-CR2 [NEC]
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION; 64M - BIT的CMOS移动指明内存4M- WORD 16位扩展的工作温度
| 型号： | UPD4664312F9-B65X-CR2 |
| 厂家： | 
NEC |
| 描述： | 64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总36页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The µPD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The µPD4664312-X is packed in 93-pin TAPE FBGA.
Features
• 4,194,304 words by 16 bits organization
• Fast access time: 65, 75 ns (MAX.)
• Fast page access time: 18, 25 ns (MAX.)
• Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
• Low voltage operation:2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)
• Operating ambient temperature: TA = –25 to +85 °C
• Output Enable input for easy application
• Chip Enable input: /CS pin
• Standby Mode input: MODE pin
• Standby Mode1: Normal standby (Memory cell data hold valid)
• Standby Mode2: Density of memory cell data hold is variable
µPD4664312
Access
time
Operating supply
Operating
ambient
Supply current
voltage
V
At operating
At standby µA (MAX.)
ns (MAX.)
temperature mA (MAX.)
°C
Density of data hold
Chip
I/O
–
64M bits 16M bits 8M bits 4M bits 0M bit
-B65X
-BE75X Note
65
75
2.7 to 3.1
–25 to +85
45
40
100
60
50
45
10
2.7 to 3.1 1.65 to 2.1
Note Under development
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15867EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan
The mark shows major revised points.
2001
©
µPD4664312-X
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating supply voltage
Operating
temperature
°C
V
Chip
I/O
–
µPD4664312F9-B65X-CR2
93-pin TAPE FBGA (12 x 9)
65
75
2.7 to 3.1
2.7 to 3.1
–25 to +85
µPD4664312F9-BE75X-CR2 Note
1.65 to 2.1
Note Under development
2
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Pin Configurations
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[ µPD4664312F9-B65X-CR2 ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
N P
B C D E F G H J K L M
P N
M L K J H G F E D C B A
A
Top View
N
A
B
C
D
E
F
G
H
J
K
L
M
P
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
A14
A10
NC
NC
A17
A4
NC
A16
NC
NC
NC
NC
NC
NC
NC
A15
A12
A19
MODE
NC
A21
A13
A9
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
GND
I/O7
NC
NC
A11
A8
I/O14
I/O5
NC
I/O6
NC
I/O12
NC
NC
/WE
NC
/LB
A7
A20
NC
A18
A5
V
CC
NC
NC
NC
I/O10
I/O0
/CS
I/O11
I/O2
I/O8
NC
/UB
A6
I/O1
GND
A0
NC
NC
A3
A2
A1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0 to A21
: Address inputs
/LB, /UB
VCC
: Byte data select
: Power supply
: Ground
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
GND
NC Note
: No Connection
MODE
/WE
/OE
: Standby mode
: Write enable
: Output enable
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
3
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
93-pin TAPE FBGA (12 x 9)
[ µPD4664312F9-BE75X-CR2 ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
N P
B C D E F G H J K L M
P N
M L K J H G F E D C B A
A
Top View
N
A
B
C
D
E
F
G
H
J
K
L
M
P
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
A14
A10
NC
NC
A17
A4
NC
A16
NC
NC
NC
NC
NC
NC
NC
A15
A12
A19
MODE
NC
A21
A13
A9
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
GND
I/O7
NC
NC
A11
A8
I/O14
I/O5
I/O6
NC
I/O12
NC
NC
/WE
NC
/LB
A7
A20
NC
A18
A5
V
CC
V
CCQ
NC
NC
NC
I/O10
I/O0
/CS
I/O11
I/O2
I/O8
NC
/UB
A6
I/O1
GND
A0
NC
NC
A3
A2
A1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0 to A21
: Address inputs
/LB, /UB
VCC
: Byte data select
: Power supply
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
VCCQ
GND
NC Note
: Input / Output power supply
: Ground
MODE
/WE
/OE
: Standby mode
: Write enable
: Output enable
: No Connection
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
4
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Block Diagram
Standby mode control
V
CC
Refresh
control
VCCQ
GND
Memory cell array
67,108,864 bits
Refresh
counter
Row
decoder
A0
Address
buffer
A21
Sense amplifier /
Switching circuit
I/O0 to I/O7
Output data
controller
Input data
controller
Column decoder
I/O8 to I/O15
Address buffer
/CS
MODE
/LB
/UB
/WE
/OE
Remark VCCQ is the input / output power supply for -BE75X.
5
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Truth Table
/CS MODE /OE
/WE
/LB
/UB
Mode
I/O
Supply
I/O0 to I/O7
High-Z
High-Z
High-Z
High-Z
DOUT
I/O8 to I/O15
High-Z
High-Z
High-Z
High-Z
DOUT
current
ISB1
H
×
×
L
H
H
L
×
×
×
H
L
×
×
×
H
×
×
H
×
Not selected (Standby Mode 1)
Not selected (Standby Mode 1)
Not selected (Standby Mode 2) Note
Output disable
×
ISB2
ICCA
H
H
H
×
×
L
L
H
L
L
H
L
H
L
L
H
L
Word read
Lower byte read
DOUT
High-Z
DOUT
Upper byte read
High-Z
DIN
H
L
Word write
DIN
Lower byte write
DIN
High-Z
DIN
Upper byte write
High-Z
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition).
Remark ×: VIH or VIL, H: VIH, L: VIL
6
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
CONTENTS
1. Initialization .................................................................................................................................................................... 8
2. Partial Refresh ............................................................................................................................................................... 9
2.1 Standby Mode........................................................................................................................................................... 9
2.2 Density Switching...................................................................................................................................................... 9
2.3 Standby Mode Status Transition............................................................................................................................... 9
2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10
3. Page Read Operation .................................................................................................................................................. 11
3.1 Features of Page Read Operation.......................................................................................................................... 11
3.2 Page Length ........................................................................................................................................................... 11
3.3 Page-Corresponding Addresses............................................................................................................................. 11
3.4 Page Start Address................................................................................................................................................. 11
3.5 Page Direction ........................................................................................................................................................ 11
3.6 Interrupt during Page Read Operation.................................................................................................................... 11
3.7 When page read is not used................................................................................................................................... 11
4. Mode Register Settings................................................................................................................................................ 12
4.1 Mode Register Setting Method ............................................................................................................................... 12
4.2 Cautions for Setting Mode Register........................................................................................................................ 13
5. Electrical Specifications ............................................................................................................................................... 14
6. Timing Charts............................................................................................................................................................... 20
7. Package Drawing......................................................................................................................................................... 30
8. Recommended Soldering Conditions .......................................................................................................................... 31
9. Revision History........................................................................................................................................................... 32
7
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
1. Initialization
Initialize the µPD4664312-X at power application using the following sequence to stabilize internal circuits.
(1) Following power application, make MODE high level after fixing MODE to low level for the period of tVHMH. Make
/CS high level before making MODE high level.
(2) /CS and MODE are fixed to high level for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure1-1. Initialization Timing Chart
Normal Operation
Initialization
/CS (Input)
t
CHMH
t
MHCL
t
VHMH
MODE (Input)
VCC
V
CC (MIN.)
Cautions 1. Make MODE low level when starting the power supply.
2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (VCC
(MIN.)).
8
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is
low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after
applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits,
8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from
Standby Mode 2.
For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit
Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
9
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 2-1. Standby Mode State Machine
Power On
Initialization
Initial State
/CS = VIL
MODE = VIH
Active
MODE = VIL
MODE = VIH,
/CS = VIH or
/LB, /UB = VIH
MODE = VIL
/CS = VIL,
MODE = VIH
/CS = VIL,
MODE = VIH
Standby Mode 2
(16M bits / 8M bits
/ 4M bits)
MODE = VIL
Standby
Mode 1
MODE = VIL
Standby Mode 2
(Data not held)
2.4 Addresses for Which Partial Refresh Is Supported
Data hold density
16M bits
Correspondence address
000000H to 0FFFFFH
8M bits
4M bits
000000H to 07FFFFH
000000H to 03FFFFH
10
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
3. Page Read Operation
3.1 Features of Page Read Operation
Features
Page length
8 Words Mode
8 words
Page read-corresponding addresses
Page read start address
Page direction
A2, A1, A0
Don’t care
Don’t care
Enabled Note
Interrupt during page read operation
Note An interrupt is output when /CS = H or in case A3 or a higher address changes.
3.2 Page Length
8 words is supported as the page lengths.
3.3 Page-Corresponding Addresses
The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read
operation.
3.4 Page Start Address
Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address.
3.5 Page Direction
Since random page read is possible, there is not restriction on the page direction.
3.6 Interrupt during Page Read Operation
When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses.
3.7 When page read is not used
Since random page read is supported, even when not using page read, random access is possible as usual.
11
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power
application is undefined, be sure to set the mode register after initialization at power application. When setting the
density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for re-
setup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not
necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to
set the mode register.
4.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (3FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
Table 4-1. shows the commands and command sequences.
Table 4-1. Command sequence
Command sequence
1st bus cycle
(Read cycle)
2nd bus cycle
(Read cycle)
3rd bus cycle
(Write cycle)
4th bus cycle
(Write cycle)
Partial refresh density
16M bits
Address
Data
Address
Data
Address
Data
00H
00H
00H
00H
Address
Data
04H
05H
06H
07H
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
–
–
–
–
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
–
–
–
–
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
8M bits
4M bits
0M bit
4th bus cycle (Write cycle)
I/O
15
0
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
Mode Register setting
0
PL
PD
Page length
1
8 words
I/O1 I/O0
Density
16M bits
8M bits
4M bits
0M bit
Partial refresh
density
0
0
1
1
0
1
0
1
12
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
4.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every
cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register is not performed correctly.
When the highest address (3FFFFFH) is read consecutively three or more times, the mode register setting entries are
not performed correctly. (Immediately after the highest address is read, the setting of the mode register is not performed
correctly.) Perform the setting of the mode register after power application or after accessing other than the highest
address.
Once the refresh density has been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set
the mode register again after power application.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
13
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
5. Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Condition
Rating
Unit
-B65X
–0.5 Note to +4.0
–
-BE75X
Supply voltage
VCC
VCCQ
VT
–0.5 Note to +4.0
–0.5 Note to +4.0
V
V
Input / Output supply voltage
Input / Output voltage
–0.5 Note to VCC + 0.4 (4.0 V MAX.) –0.5 Note to VCCQ + 0.4 (4.0 V MAX.)
V
Operating ambient temperature
Storage temperature
TA
–25 to +85
–25 to +85
°C
°C
Tstg
–55 to +125
–55 to +125
Note –1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
-B65X
-BE75X
Unit
MIN.
2.7
MAX.
3.1
MIN.
2.7
MAX.
3.1
Supply voltage
VCC
VCCQ
VIH
V
V
Input / Output supply voltage
High level input voltage
–
–
1.65
2.1
0.8VCC
–0.3 Note
–25
VCC+0.3
0.2VCC
+85
0.8VCCQ
–0.3 Note
–25
VCCQ+0.3
0.2VCCQ
+85
V
Low level input voltage
VIL
V
Operating ambient temperature
TA
°C
Note –0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Input capacitance
Input / Output capacitance
Symbol
CIN
Test condition
MIN.
TYP.
MAX.
8
Unit
pF
VIN = 0 V
VI/O = 0 V
CI/O
10
pF
Remarks 1. VIN: Input voltage, VI/O: Input / Output voltage
2. These parameters are not 100% tested.
14
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
Density of
data hold
-B65X
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /CS = VIH or
/WE = VIL or /OE = VIH
/CS = VIL, Minimum cycle time,
II/O = 0 mA
Operating supply current
Standby supply current
ICCA
ISB1
ISB2
45
mA
/CS ≥ VCC − 0.2 V,
64M bits
60
100
µA
MODE ≥ VCC − 0.2 V
/CS ≥ VCC − 0.2 V,
16M bits
8M bits
4M bits
0M bit
50
45
40
60
50
45
10
MODE ≤ 0.2 V
High level output voltage
Low level output voltage
VOH
VOL
IOH = –0.5 mA
IOL = 1 mA
0.8VCC
V
V
0.2VCC
Remark VIN: Input voltage, VI/O: Input / Output voltage
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
Density of
data hold
-BE75X
TYP.
Unit
MIN.
–1.0
–1.0
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCCQ
µA
µA
ILO
VI/O = 0 V to VCCQ, /CS = VIH or
/WE = VIL or /OE = VIH
/CS = VIL, Minimum cycle time,
II/O = 0 mA
Operating supply current
Standby supply current
ICCA
40
mA
I
SB1
/CS ≥ VCC − 0.2 V,
64M bits
60
100
µA
MODE ≥ VCC − 0.2 V
/CS ≥ VCC − 0.2 V,
ISB2
16M bits
8M bits
4M bits
0M bit
50
45
40
60
50
45
10
MODE ≤ 0.2 V
High level output voltage
Low level output voltage
VOH
VOL
IOH = –0.5 mA
IOL = 1 mA
0.8VCCQ
V
V
0.2VCCQ
Remark VIN: Input voltage, VI/O: Input / Output voltage
15
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ -B65X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Vcc
0.8Vcc
Vcc / 2
Test points
Vcc / 2
0.2Vcc
GND
5ns
Output Waveform
Vcc / 2
Test points
Vcc / 2
[ -BE75X ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
VccQ
0.8VccQ
VccQ / 2
Test points
VccQ / 2
0.2VccQ
GND
5ns
Output Waveform
VccQ / 2
Test points
VccQ / 2
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2.
Figure 5-1.
[ -B65X ]
Figure 5-2.
[ -BE75X ]
CL: 30 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
CL: 30 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ)
ZO = 50 Ω
ZO = 50 Ω
I/O (Output)
I/O (Output)
CL
50 Ω
CL
50 Ω
V
CC / 2
V
CCQ / 2
16
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Read Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MAX.
MIN.
65
MAX.
MIN.
75
Read cycle time
tRC
tAA
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
Address access time
65
65
45
65
75
75
50
75
/CS access time
/OE to output valid
/LB, /UB to output valid
tBA
Output hold from address change
Page read cycle time
tOH
5
5
tPRC
tPAA
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tASO
tOHAH
tCHAH
tBHAH
tCLOL
tOLCH
tCP
18
25
Page access time
18
25
/CS to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
/LB, /UB to output in high impedance
Address set to /OE low level
/OE high level to address hold
/CS high level to address hold
/LB, /UB high level to address hold
/CS low level to /OE low level
/OE low level to /CS high level
/CS high level pulse width
/LB, /UB high level pulse width
/OE high level pulse width
10
5
10
5
5
5
25
25
25
25
25
25
0
–5
0
0
–5
0
0
0
ns 3, 4
0
10,000
10,000
0
10,000
10,000
ns
ns
ns
ns
ns
5
45
10
10
2
45
10
10
2
tBP
tOP
5
Notes 1. Output load: 30 pF
2. Output load: 5 pF
3. When tASO ≥ | tCHAH |, | tBHAH |, tCHAH and tBHAH (MIN.) are –15 ns.
t
CHAH, tBHAH
Address (Input)
/LB, /UB, /CS (Input)
/OE (Input)
t
ASO
4. tBHAH is specified from when both /LB and /UB become high level.
5. tCLOL and tOP (MAX.) are applied while /CS is being hold at low level.
17
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Write Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MIN.
65
55
55
55
50
0
MAX.
MIN.
75
60
60
60
55
0
MAX.
Write cycle time
tWC
tCW
ns
/CS to end of write
ns
Address valid to end of write
/LB, /UB to end of write
Write pulse width
tAW
ns
tBW
ns
tWP
ns
Write recovery time
tWR
ns
/CS pulse width
tCP
10
10
10
0
10
10
10
0
ns
/LB, /UB high level pulse width
/WE high level pulse width
Address setup time
tBP
ns
tWHP
tAS
ns
ns
/OE high level to address hold
/CS high level to address hold
/LB, /UB high level to address hold
Data valid to end of write
Data hold time
tOHAH
tCHAH
tBHAH
tDW
–5
0
–5
0
ns
ns
1
0
0
ns 1, 2
30
0
35
0
ns
ns
tDH
/OE high level to /WE set
/WE high level to /OE set
tOES
tOEH
0
10,000
10,000
0
10,000
10,000
ns
ns
3
10
10
Notes 1. When tAS ≥ | tCHAH |, | tBHAH | and tCP ≥ 18 ns, tCHAH and tBHAH (MIN.) are –15 ns.
t
CHAH, tBHAH
Address (Input)
/LB, /UB, /CS (Input)
/WE (Input)
t
AS
2. tBHAH is specified from when both /LB and /UB become high level.
3. tOES and tOEH (MAX.) are applied while /CS is being hold at low level.
18
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Initialization
Parameter
Symbol
tVHMH
MIN.
50
MAX.
Unit Note
Power application to MODE low level hold
/CS high level to MODE high level
Following power application
µs
ns
µs
tCHMH
0
tMHCL
200
MODE high level hold to /CS low level
Standby Mode 2 Entry / Exit
Parameter
Symbol
tCHML
MIN.
0
MAX.
Unit Note
ns
Standby mode 2 entry
/CS high level to MODE low level
Standby mode 2 exit to normal operation
MODE high level to /CS low level
Standby mode 2 exit to normal operation
MODE high level to /CS low level
tMHCL1
30
ns
1
2
tMHCL2
200
µs
Notes 1. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M
bits).
2. This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
19
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
6. Timing Charts
Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled)
t
RC
t
RC
A3
A2
A1
Address (Input)
/CS (Input)
t
ACS
t
CHAH
t
CHAH
t
ACS
t
CP
t
CP
t
CLZ
t
CLZ
t
CHZ
t
CHZ
/OE (Input)
/LB, /UB (Input)
I/O (Output)
High-Z
High-Z
High-Z
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-2. Read Cycle Timing Chart 2 (/OE Controlled)
t
RC
t
RC
Address (Input)
/CS (Input)
A3
A2
A1
t
BHAH
t
AA
tAA
t
BHAH
t
OE
t
OHAH
tASO
t
OE
t
ASO
t
ASO
tOHAH
/OE (Input)
t
OP
t
OP
/LB, /UB (Input)
t
OHZ
t
OLZ
tOHZ
t
OLZ
High-Z
High-Z
High-Z
I/O (Output)
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
20
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled)
t
RC
t
RC
Address (Input)
/CS (Input)
A2
A1
A3
t
t
CHAH
t
AA
t
OHAH
t
ACS
t
BHAH
t
BHAH
CHZ
OHAH
t
t
CLZ
t
OE
t
ASO
t
OHZ
t
CLOL
t
OE
/OE (Input)
/LB, /UB (Input)
I/O (Output)
t
OHZ
t
OLZ
t
OLZ
High-Z
High-Z
High-Z
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-4. Read Cycle Timing Chart 4 (Address Controlled)
t
RC
t
RC
A2
A1
A3
Address (Input)
/CS (Input)
t
AA
t
AA
/OE (Input)
/LB, /UB (Input)
t
OH
t
OH
tOH
I/O (Output)
Data Out Q2
Data Out Q1
Remark In read cycle, MODE and /WE should be fixed to high level.
21
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled)
t
RC
t
RC
Address (Input)
A2
A1
A3
/CS (Input)
/OE (Input)
t
BHAH
t
BHAH
/LB, /UB (Input)
I/O (Output)
t
BP
tBP
t
BA
t
BA
t
BHZ
tBHZ
t
BLZ
t
BLZ
High-Z
High-Z
High-Z
Data Out Q1
Data Out Q2
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-6. Page Read Cycle Timing Chart
t
RC
t
PRC
t
PRC
t
PRC
t
PRC
t
PRC
t
PRC
tPRC
Address
(A3 to A21) (Input)
A
N
A
N+1
AN+2
AN+3
A
N+4
A
N+5
A
N+6
AN+7
Page Address
(A0 to A2) (Input)
t
OH
/CS (Input)
/OE (Input)
t
CHZ
t
OE
t
OHZ
t
ACS
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
PAA
t
OH
t
OH
tOH
t
OH
t
OH
t
OH
t
OH
High-Z
I/O (Output)
Q
N
Q
N+1
Q
N+2
Q
N+3
Q
N+4
Q
N+5
Q
N+6
QN+7
Remarks 1. In read cycle, MODE and /WE should be fixed to high level.
2. /LB and /UB are low level.
22
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled)
t
WC
t
WC
A3
Address (Input)
A2
A1
t
AS
t
AS
tCW
t
AS
t
WR
tWR
t
CW
/CS (Input)
/WE (Input)
t
CP
t
CP
/LB, /UB (Input)
t
OHAH
t
ASO
t
OES
t
OEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DW
tDH
High-Z
High-Z
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
23
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled)
t
WC
tWC
A3
Address (Input)
/CS (Input)
A2
A1
t
CHAH
tCHAH
t
CW
tCW
t
AS
t
WP
t
WR
t
CP
t
AS
t
WP
t
WR
tCP
/WE (Input)
t
WHP
t
BHAH
t
BHAH
/LB, /UB (Input)
t
OHAH
t
ASO
t
OES
t
OEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DW
tDH
High-Z
High-Z
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
24
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled)
t
WC
t
WC
A3
Address (Input)
/CS (Input)
A2
A1
t
AW
tAW
t
AS
t
WP
t
WR
t
AS
t
WP
tWR
/WE (Input)
t
WHP
t
BHAH
t
BHAH
/LB, /UB (Input)
t
OHAH
t
ASO
t
OES
t
OEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DW
tDH
High-Z
High-Z
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
25
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled)
t
WC
t
WC
Address (Input)
A3
A2
A1
/CS (Input)
/WE (Input)
t
BW
tWR
t
AS
t
BW
t
AS
t
WR
/LB, /UB (Input)
t
BP
tBP
t
OHAH
tASO
t
OES
t
OEH
/OE (Input)
I/O (Input)
t
DW
t
DH
t
DW
tDH
High-Z
High-Z
High-Z
Data In D1
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
26
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled)
t
WC
t
WC
Address (Input)
A1
A3
A2
/CS (Input)
/WE (Input)
t
AS
t
BW
tWR
/LB (Input)
t
AS
t
BW
tWR
/UB (Input)
/OE (Input)
t
BP
t
OHAH
t
ASO
t
OES
t
OEH
t
DW
tDH
High-Z
High-Z
I/O0 to I/O7 (Input)
I/O8 to I/O15 (Input)
Data In D1
t
DW
tDH
High-Z
High-Z
Data In D2
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
27
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-12. Mode Register Setting Timing Chart
Mode Register Setting
t
RC
t
RC
t
WC
t
WC
Address (Input)
/CS (Input)
3FFFFFH
3FFFFFH
3FFFFFH
3FFFFFH
/OE (Input)
t
WP
t
WR
t
WP
t
WR
/WE (Input)
t
DW
t
DH
t
DW
t
DH
High-Z
High-Z
High-Z
xxxxH
xxxxH
I/O (Input)
/LB, /UB (Input)
Figure 6-13. Mode Register Setting Flow Chart
Start
Address= 3FFFFFH
Read with toggled the /CS, /OE
No
No
No
Address= 3FFFFFH
Read with toggled the /CS, /OE
Address = 3FFFFFH
Write
No
No
Data = 00H?
No
Address = 3FFFFFH
Write
Fail
Note
Data = xxH?
Mode register setting exit
End
Note xxH = 04H, 05H, 06H, 07H
28
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart
MODE (Input)
t
CHML
t
MHCL1
/CS (Input)
Standby
mode 1
Standby mode 2
(Data hold: 16M bits / 8M bits / 4M bits)
Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart
MODE (Input)
t
CHML
t
MHCL2
/CS (Input)
Standby mode 2
(Data not held)
Standby
mode 1
29
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
7. Package Drawing
93-PIN TAPE FBGA (12x9)
ZD
ZE
w S
B
B
E
10
9
8
7
6
5
4
3
2
1
A
P N M L K J H G F E D C B A
INDEX MARK
w
S A
ITEM MILLIMETERS
A
D
E
9.0 0.1
12.0 0.1
0.2
A2
y1
S
w
e
0.8
S
A
1.3 0.1
0.16 0.05
1.14
A1
A2
b
A1
A B
0.40 0.05
0.08
y
S
e
x
M
φ
φ
x
y
0.1
b
S
y1
ZD
ZE
0.2
0.9
0.8
P93F9-80-CR2
30
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
8. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4664312-X.
Type of Surface Mount Device
µPD4664312F9-CR2: 93-pin TAPE FBGA (12 x 9)
31
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
9. Revision History
Edition/
Date
Page
Type of
revision
Location
Description
(Previous edition → This edition)
This
edition
Previous
edition
5th edition/ Throughout Throughout
Aug. 2002
Deletion
Class
-C75X, -C85X, -E85X, -E10X,
-BE85X, -CE80X, -CE90X
2.6 to 3.1 V → 2.7 to 3.1 V
Fast access time: 80, 85, 90, 100 ns
Fast page access time: 30, 35 ns
-BE75X: TBD → 40 mA
Modification Supply Voltage (Chip)
Deletion Features
p.1
p.1
pp.1, 15
p.17
pp.1, 15
pp.17, 18
p.22
Modification Operating supply current
Addition Read Cycle
tOP (MIN.): 2ns
p.20
Modification Figure 6-2
Modification Figure 6-3
Timing charts are modified.
Timing charts are modified.
p.21
p.23
32
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
[ MEMO ]
33
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
[ MEMO ]
34
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
35
Preliminary Data Sheet M15867EJ5V0DS
µPD4664312-X
•
The information in this document is current as of August, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD4664312F9-BE75X-CR2
64M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
NEC
UPD4701AC-A
Binary Counter, 4000/14000/40000 Series, Asynchronous, Positive Edge Triggered, 12-Bit, Bidirectional, CMOS, PDIP24, 0.600 INCH, PLASTIC, DIP-24
NEC
©2020 ICPDF网 联系我们和版权申明