UPD70216HLP-12 [NEC]

V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR; V40HLTM ， V50HLTM 16/8 ， 16位微处理器


型号：	UPD70216HLP-12
厂家：	NEC
描述：	V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR V40HLTM ， V50HLTM 16/8 ， 16位微处理器微控制器和处理器外围集成电路微处理器装置时钟
文件：	总110页 (文件大小：614K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD70208H, 70216H

V40HL^TM, V50HL^TM

16/8, 16-BIT MICROPROCESSOR

DESCRIPTION

The µPD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the µPD70208 (V40^TM) with

16-bit architecture, 8-bit data bus, and general-purpose peripheral functions.

The µPD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the µPD70216 (V50^TM) with 16-

bit architecture, 16-bit data bus, and general-purpose peripheral functions.

The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the

clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also

capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems.

Details are given in the following manuals. Be sure to read when carrying out design work.

• V40HL, V50HL User’s Manual – Hardware (U11610E)

• 16-bit V series^TMUser’s Manual – Instruction (U11301J: Japanese version)

FEATURES

• High-speed, low-power version of V40 and V50

• High-performance CPU (V20^TM/V30^TMsoftware compatible)

• Minimum instruction execution time:

100 ns (20 MHz, 5 V)

200 ns (10 MHz, 3 V)

• Memory addressing space: 1M bytes

• High-speed multiply/divide instructions:

0.95 to 2.8 µs (20 MHz, 5 V)

1.9 to 5.6 µs (10 MHz, 3 V)

• Maskable (ICU) & non-maskable (NMI) interrupt inputs

µPD8080AF emulation function

•

• Standby functions, clock stoppage capability

• Standard peripheral LSI functions on chip

• Clock generator (CG)

• Programmable wait control unit (WCU)

• Refresh control unit (REFU)

• Timer/counter unit (TCU)

• Serial control unit (SCU)

··· µPD71054 subset

··· µPD71051 subset

• Interrupt control unit (ICU) ··· µPD71059 subset

• DMA control unit (DMAU)

··· µPD71071/71037 subset (functions of either selectable)

• Operating frequency: 10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally)

5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

The mark shows the the major revised points.

Document No. U13225EJ4V0DS00 (4th edition)

Date Published April 1999 N CP(K)

Printed in Japan

1995

µPD70208H, 70216H

ORDERING INFORMATION

(1) V40HL

Max. Operating

Part Number

Package

80-pin plastic QFP (14 × 20 mm)

Frequency (MHz)

µPD70208HGF-10-3B9

12.5

(Resin thickness 2.7 mm)

µPD70208HGF-12-3B9

µPD70208HGF-16-3B9

µPD70208HGF-20-3B9

µPD70208HGK-10-9EU

µPD70208HGK-12-9EU

µPD70208HGK-16-9EU

µPD70208HGK-20-9EU

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

12.5

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

µPD70208HLP-10

µPD70208HLP-12

µPD70208HLP-16

µPD70208HLP-20

68-pin plastic QFJ (950 × 950 mil)

12.5

(2) V50HL

Max. Operating

Part Number

Package

Frequency (MHz)

µPD70216HGF-10-3B9

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

12.5

µPD70216HGF-12-3B9

µPD70216HGF-16-3B9

µPD70216HGF-20-3B9

µPD70216HGK-10-9EU

µPD70216HGK-12-9EU

µPD70216HGK-16-9EU

µPD70216HGK-20-9EU

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic QFP (14 × 20 mm)

(Resin thickness 2.7 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

12.5

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

80-pin plastic TQFP (Fine pitch) (12 × 12 mm)

(Resin thickness 1.0 mm)

µPD70216HLP-10

µPD70216HLP-12

µPD70216HLP-16

µPD70216HLP-20

68-pin plastic QFJ (950 × 950 mil)

12.5

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

PIN CONFIGURATION (Top View)

(1) V40HL

•

80-pin Plastic QFP (14 × 20 mm)

µPD70208HGF-10-3B9

µPD70208HGF-12-3B9

µPD70208HGF-16-3B9

µPD70208HGF-20-3B9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

A16/PS0

IORD

A15

A14

A13

A12

A11

A10

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

GND

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

High

ASTB

QS0

QS1

POLL

TCTL2

TOUT2

TCLK

INTP7

INTP6

END/TC

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Caution Leave IC pin open.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

•

80-pin Plastic TQFP (Fine pitch) (12 × 12 mm)

µPD70208HGK-10-9EU

µPD70208HGK-12-9EU

µPD70208HGK-16-9EU

µPD70208HGK-20-9EU

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

A15

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

A14

A13

A12

A11

A10

GND

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

High

ASTB

QS0

QS1

POLL

TCTL2

TOUT2

TCLK

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

•

68-pin Plastic QFJ (950 × 950 mil)

µPD70208HLP-10

µPD70208HLP-12

µPD70208HLP-16

µPD70208HLP-20

1 68 67 66 65 64 63 62 61

A15

A14

A13

A12

A11

A10

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

GND

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

High

ASTB

QS0

QS1

POLL

TCTL2

TOUT2

TCLK

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) V50HL

80-pin Plastic QFP (14 × 20 mm)

•

µPD70216HGF-10-3B9

µPD70216HGF-12-3B9

µPD70216HGF-16-3B9

µPD70216HGF-20-3B9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

A16/PS0

IORD

AD15

AD14

AD13

AD12

AD11

AD10

AD9

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

AD8

GND

AD7

GND

UBE

AD6

ASTB

QS0

AD5

AD4

QS1

AD3

POLL

TCTL2

TOUT2

TCLK

AD2

AD1

AD0

INTP7

INTP6

END/TC

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Caution Leave IC pin open.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

•

80-pin Plastic TQFP (Fine pitch) (12 × 12 mm)

µPD70216HGK-10-9EU

µPD70216HGK-12-9EU

µPD70216HGK-16-9EU

µPD70216HGK-20-9EU

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AD15

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

AD14

AD13

AD12

AD11

AD10

AD9

AD8

GND

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

GND

UBE

ASTB

QS0

QS1

POLL

TCTL2

TOUT2

TCLK

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

•

68-pin Plastic QFJ (950 × 950 mil)

µPD70216HLP-10

µPD70216HLP-12

µPD70216HLP-16

µPD70216HLP-20

1 68 67 66 65 64 63 62 61

AD15

AD14

AD13

AD12

AD11

AD10

AD9

MWR

IOWR

BUSLOCK

BUFR/W

BUFEN

CLKOUT

AD8

GND

AD7

GND

UBE

AD6

ASTB

QS0

AD5

AD4

QS1

AD3

POLL

TCTL2

TOUT2

TCLK

AD2

AD1

AD0

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

PIN NAMES

A8-A15

Address Bus

A16/PS0-A19/PS3

AD0-AD15

ASTB

Address/Processor Status

Address Bus/Data Bus

Address Strobe

Bus Status

BS0-BS2

BUFEN

Buffer Enable

BUFR/W

BUSLOCK

CLKOUT

DMAAK0-DMAAK2

DMAAK3/TXD

DMARQ0-DMARQ2

DMARQ3/RXD

END/TC

GND

Buffer Read/Write

Bus Lock

Clock Output

DMA Acknowledge

DMA Acknowledge/Transmit Data

DMA Request

DMA Request/Receive Data

End/Terminal Count

Ground

High

High Level Output

Hold Acknowledge

Hold Request

HLDAK

HLDRQ

Internally Connected

Interrupt Acknowledge/Serial Ready/Timer Output 1

Interrupt Request from Peripherals

I/O Read

INTAK/SRDY/TOUT1

INTP1-INTP7

IORD

IOWR

I/O Write

MRD

Memory Read

MWR

Memory Write

No Connection

NMI

Non-Maskable Interrupt Request

Poll

POLL

QS0, QS1

READY

Queue Status

Ready

REFRQ

Refresh Request

Reset

RESET

RESOUT

TCLK

Reset Output

Timer Clock

TCTL2

Timer Control 2

Timer Output 2

TOUT2

UBE

Upper Byte Enable

Power Supply

V^DD

X1, X2

Crystal

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

BLOCK DIAGRAM

(1) V40HL

TOUT2

TOUT1

TCTL2

TCLK

POLL

BUSLOCK

BUFEN

BUFR/W

High

BIU

SCU

TCU

ASTB

IOWR

IORD

INTP7

INTP6

INTP5

INTP4

INTP3

INTP2

INTP1

MWR

WCU

MRD

READY

RESOUT

RESET

ICU

CPU

HLDAK

HLDRQ

INTAK

NMI

BAU

REFU

DMAU

CPU : Central Processing Unit

REFU : Reflesh Control Unit

Clock Generator

Bus Interface Unit

TCU

SCU

ICU

Timer/Count Unit

BIU

Serial Control Unit

Interrupt Control Unit

BAU : Bus Arbitration Unit

WCU : Wait Control Unit

DMAU : DMA Control Unit

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) V50HL

TOUT2

TOUT1

TCTL2

TCLK

POLL

BUSLOCK

BUFEN

BUFR/W

UBE

SCU

TCU

BIU

ASTB

IOWR

IORD

INTP7

INTP6

INTP5

INTP4

INTP3

INTP2

INTP1

MWR

WCU

MRD

READY

RESOUT

RESET

ICU

CPU

HLDAK

HLDRQ

INTAK

NMI

BAU

DMAU

REFU

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DIFFERENCES FROM V40 AND V50

Item

V40HL, V50HL

V40, V50

Operating supply voltage

3 V, 5 V

5 V

VDD = 5 V

MAX. : 10, 12.5, 16, 20 MHz

MIN. : DC

MAX. : 8, 10 MHz

MIN. : 2 MHz

Operating

frequency

VDD = 3 V

MAX. : 5, 6.25, 8, 10 MHz

MIN. : DC

No operation

Clock generator

(CG)

Variable scaling factor

Fixed scaling factor

Variable instruction cycle time

Maximum input frequency: 40 MHz

Fixed instruction cycle time

Maximum input frequency: 20 MHz

Internal I/O relocation

function

Switchable 8-bit boundary or 16-bit boundary

relocation function

V40: Relocation possible on 8-bit boundary

V50: Relocation possible on 16-bit boundary

Note 1

Wait control unit (WCU)

Memory space: 5 divisions

Memory space: 3 divisions

I/O space: Not divided

Note 2

I/O space: 3 divisions

Refresh control unit

(REFU)

Refresh address: 16 bits

Refresh address: 9 bits

No REFRQ extended timing

REFRQ extended timing supported

Dedicated baud rate generator incorporated

Serial control unit (SCU)

DMA control unit (DMAU)

Standby functions

No dedicated baund rate generator

incorporated

µPD71071/71037 subset (either function

µPD71071 subset

selectable)

HALT mode, STOP mode

HALT mode only

Notes 1. Divided into 3 when a reset is performed.

2. Not divided when a reset is performed.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

CONTENTS

1. PIN FUNCTIONS ................................................................................................................................... 15

1.1 LIST OF PIN FUNCTIONS ...........................................................................................................................

1.2 PROCESSING OF UNUSED PINS ..............................................................................................................

2. MEMORY AND I/O CONFIGURATION ................................................................................................ 19

2.1 MEMORY SPACE.........................................................................................................................................

2.2 I/O SPACE .................................................................................................................................................... 21

3. CPU ........................................................................................................................................................ 22

4. CG (CLOCK GENERATOR) ................................................................................................................. 24

5. BIU (BUS INTERFACE UNIT) .............................................................................................................. 24

6. BAU (BUS ARBITRATION UNIT) ........................................................................................................ 25

7. WCU (WAIT CONTROL UNIT) ................................................................................................................ 27

7.1 FEATURES ...................................................................................................................................................

7.2 RELATION BETWEEN WCU AND READY PIN ........................................................................................

8. REFU (REFRESH CONTROL UNIT) .................................................................................................... 29

8.1 FEATURES ...................................................................................................................................................

8.2 REFRESH OPERATIONS ............................................................................................................................

9. TCU (TIMER/COUNTER UNIT) ............................................................................................................ 30

9.1 FEATURES ...................................................................................................................................................

9.2 TCU INTERNAL BLOCK DIAGRAM ...........................................................................................................

10. SCU (SERIAL CONTROL UNIT) .......................................................................................................... 31

10.1 FEATURES ...................................................................................................................................................

10.2 SCU INTERNAL BLOCK DIAGRAM...........................................................................................................

11. ICU (INTERRUPT CONTROL UNIT) .................................................................................................... 32

11.1 FEATURES ...................................................................................................................................................

11.2 ICU INTERNAL BLOCK DIAGRAM ............................................................................................................

12. DMAU (DMA CONTROL UNIT) ............................................................................................................ 33

12.1 FEATURES ...................................................................................................................................................

12.2 DMAU INTERNAL BLOCK DIAGRAM .......................................................................................................

13. STANDBY FUNCTIONS........................................................................................................................ 34

14. RESET OPERATION ............................................................................................................................. 34

15. INSTRUCTION SET............................................................................................................................... 35

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

16. ELECTRICAL SPECIFICATIONS ......................................................................................................... 66

16.1 AT 5 V OPERATION ....................................................................................................................................

16.2 AT 3 V OPERATION ....................................................................................................................................

17. PACKAGE DRAWINGS ........................................................................................................................ 100

18. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 103

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

1. PIN FUNCTIONS

1.1 LIST OF PIN FUNCTIONS

Pin Name

Input/Output

3-state I/O

3-state output

Output

Function

Note 1, 3

AD0 to AD15

Time-division address/data bus

Address bus

Note 2, 3

AD0 to AD7

Note 2, 3

A8 to A15

Note 3

A16/PS0 to A19/PS3

Time-division address/processor status

Refresh request

REFRQ

HLDRQ

HLDAK

RESET

RESOUT

READY

NMI

Input

Bus hold request

Output

Bus hold acknowledge

Reset

Input

Output

System reset output

Bus cycle end

Input

Non-maskable interrupt

Memory read strobe

I/O read strobe

Note 3

MRD

3-state output

Output

Note 3

MWR

Note 3

IORD

Note 3

IOWR

I/O write strobe

ASTB

Address strobe

Note 1, 3

UBE

3-state output

Input

Data bus upper byte enable

High level output

Note 2

High

Note 3

BUSLOCK

Bus lock

POLL

Floating-point operation processor polling

Buffer read/write

Note 3

BUFR/W

3-state output

Input

Note 3

BUFEN

Buffer enable

Crystal/external clock

—

CLKOUT

Output

Clock output

Note 3

BS0 to BS2

3-state output

Output

Bus status

QS0, QS1

TOUT2

Queue status

Output

Timer 2 output

TCTL2

Input

Timer 2 control

TCLK

Input

Timer clock

INTP1 to INTP7

INTAK/SRDY/TOUT1

Input

Maskable interrupts

Output

Interrupt acknowledge/serial reception ready/timer 1 output

Notes 1. V50HL only

2. V40HL only

3. These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold

the status before the high-impedance state until driven by an external device. It is not necessary to pull

up or down the data bus. To invert the level of the pin that goes into a high-impedance state by an

external device, a drive current higher than the latch invert current (I^ILH, IILL) is necessary.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Pin Name

DMAAK3/TXD

Input/Output

Output

Input

Output

Input

I/O

Function

DMA acknowledge 3/serial transmit data

DMA request 3/serial receive data

DMA acknowledge

DMARQ3/RXD

DMAAK0 to DMAAK2

DMARQ0 to DMARQ2

DMA request

END/TC

VDD

DMA service forcible termination/DMA service completion

Positive power supply pin

—

GND

—

Ground potential pin

—

Internal connection pin (External connection impossible)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

1.2 PROCESSING OF UNUSED PINS

Table 1-1 shows the processing (recommended connection) of the unused pins. Use of a resistor with a resistance of

1 to 10 kΩ is recommended to connect these pins to VDD or GND via resistor.

Table 1-1. Processing of Unused Pins

Pin Name

Input/Output

3-state I/O

3-state output

Output

Recommended Connection

Note 1

AD0 to AD15

Open

Note 2

AD0 to AD7

Note 2

A8 to A15

A16/PS0 to A19/PS3

REFRQ

HLDRQ

HLDAK

RESOUT

READY

NMI

Input

Connect to GND via resistor

Output

Open

Output

Open

Input

Connect to VDD via resistor

Connect to GND via resistor

Open

Input

MRD

3-state output

Output

MWR

IORD

IOWR

ASTB

Note 1

UBE

3-state output

Output

Note 2

High

BUSLOCK

3-state output

Input

POLL

Connect to GND via resistor

Open

BUFR/W

3-state output

Output

BUFEN

CLKOUT

Open

BS0 to BS2

QS0, QS1

3-state output

Output

TOUT2

Output

TCTL2

Input

Connect to GND via resistor

Open

TCLK

Input

INTP1 to INTP7

INTAK/SRDY/TOUT1

DMAAK3/TxD

DMARQ3/RxD

DMAAK0 to DMAAK2

DMARQ0 to DMARQ2

END/TC

Input

Output

Input

Connect to GND via resistor

Open

Output

Input

Connect to GND via resistor

Individually connect to VDD via resistor

I/O

Notes 1. V50HL only

2. V40HL only

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive

current higher than the latch invert current is necessary.

(1) Output pin

Output buffer

Latch

Output pin

address bus,

control bus

Hi-Z

control

(2) I/O pin

Output buffer

Latch

I/O pin

(data bus)

Hi-Z

control

Input buffer

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

2. MEMORY AND I/O CONFIGURATION

2.1 MEMORY SPACE

The V40HL and V50HL can access a 1M-byte (512K-word) memory space.

Figure 2-1. Memory Map

FFFFFH

Reserved

FFFFCH

FFFFBH

Dedicated

FFFF0H

FFFEFH

General Use

00400H

003FFH

Interrupt Vector Table

00000H

Figure 2-2. Interface with Memory (1/2)

(a) V40HL

A0-A19

Address Bus (20)

Memory

1M Byte

D0-D7

Data Bus (8)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Figure 2-2. Interface with Memory (2/2)

(b) V50HL

A1-A19

Address Bus (19)

UBE

BSEL

Memory

Upper Bank

512K Byte

Memory

Lower Bank

512K Byte

D8-D15

D0-D7

D0-D15

Data Bus (16)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

2.2 I/O SPACE

In the V40HL and V50HL, I/Os up to 64K bytes (32K words) can be accessed in an area independent of the memory.

The various on-chip peripheral LSIs are set by accessing the system I/O area.

Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved

area.

The I/O map is shown in Figure 2-3.

Figure 2-3. I/O Map

FFFFH

Area used for setting of I/O boundary,

WCU, REFU, baud rate generator, etc.,

and DMAU, ICU, TCU and SCU allocation.

System I/O Area

FFE0H

FFDFH

Reserved Area

FF00H

FEFFH

DMAU

ICU

The DMAU, ICU, TCU and SCU

are allocated within any 256 bytes.

256 Bytes

TCU

SCU

Internal I/O Area

External I/O Area

0000H

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

3. CPU

The CPU has the same functions as the V20HL^TMand V30HL^TM. In hardware terms, there are some changes regarding

the use of the bus with on-chip peripherals, but in software terms the CPU is fully compatible.

The internal block diagram of the CPU is shown in Figure 3-1.

Figure 3-1. Internal Block Diagram of CPU (1/2)

(a) V40HL

Internal Address/Data Bus (20)

To BIU

ADM

T-STATE

CONTROL

DS0

DS1

PFP

NMI

CYCLE

DECISION

INTERRUPT

CONTROL

INT

(From ICU)

TEMP

QUEUE

CONTROL

STANDBY

CONTROL

CLOCK

(From CG)

BCU

EXU

EFFECTIVE ADDRESS

GENERATOR

µINSTRUCTION

Micro Data Bus

ROM

SEQUENCE

CONTROL

SHIFTER

INSTRUCTION DECODER

ALU

PSW

Sub Data Bus

(16)

Main Data Bus

(16)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Figure 3-1. Internal Block Diagram of CPU (2/2)

(b) V50HL

Internal Address/Data Bus (20)

To BIU

ADM

DS0

DS1

T-STATE

CONTROL

PFP

NMI

CYCLE

DECISION

INTERRUPT

CONTROL

INT

(From ICU)

TEMP

QUEUE

CONTROL

STANDBY

CONTROL

CLOCK

(From CG)

BCU

EXU

EFFECTIVE ADDRESS

GENERATOR

INSTRUCTION

ROM

Micro Data Bus

SEQUENCE

CONTROL

SHIFTER

INSTRUCTION DECODER

ALU

PSW

Sub Data Bus

(16)

Main Data Bus

(16)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

4. CG (CLOCK GENERATOR)

The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1

and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output.

The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a

system I/O area register.

Figure 4-1. Internal Block Diagram of CG

Divide-by-2

Scaler

Divide-by-1-to-8

Scaler

Oscillator

CPU, DMAU, REFU, SCU

CLKOUT

Baud Rate Counter (BRC)

Divide-by-2-to-16

Scaler

TCU

5. BIU (BUS INTERFACE UNIT)

The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control

unit) and REFU (refresh control unit).

The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock

generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also

output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU.

Figure 5-1. RESET and READY Signal Synchronization

CLOCK

CK ↓

RESET

READY

RESOUT

To Internal Units

CK ↑

CK ↓

To Internal Units

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

6. BAU (BUS ARBITRATION UNIT)

The BAU performs bus arbitration among bus masters.

A list of bus masters (units which can acquire the bus) is shown below.

Table 6-1. Bus Masters

Bus Master

Bus Cycle

CPU

Program fetch, data read/write

DMA cycle

DMAU

REFU

Refresh cycle

External bus master

(HLDRQ pin input)

Bus cycle driven by external device

The relative priorities of the bus masters are shown below.

High

CPU (when BUSLOCK prefix is used)

REFU (highest priority: when given number of requests are reached)

DMAU

HLDRQ pin

CPU (normal CPU cycle)

REFU (lowest priority: cycle steal)

Low

BAU bus arbitration is performed as follows.

A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at

the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected

to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2. The V40HL

and V50HL request return of the bus by inactivating the acknowledge signal (HLDAK), and on receiving this request, the

external bus master holding the bus should release the bus by dropping the bus hold request signal (HLDRQ). The V40HL

and V50HL-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. This

is called a bus wait operation.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Figure 6-1. Internal Bus Cycles

Bus Cycle

CPU

DMA

Refresh Refresh Refresh

Internal DMA Request

Internal Refresh Request

(Highest Priority)

Figure 6-2. Bus Wait Operation

Bus Wait

Bus Release^Note

Refresh

Bus Cycle

HLDRQ Pin

HLDAK Pin

Internal Refresh Request

(Highest Priority)

Note The period in which the external bus master which has been given the bus after its release by the V40HL and

V50HL can use the bus.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

7. WCU (WAIT CONTROL UNIT)

The WCU has the function of automatically inserting a wait state (TW) of 0 to 3 clock cycles in a CPU, DMAU or REFU

bus cycle.

7.1

FEATURES

Automatic setting of 0 to 3 waits for a CPU memory bus cycle

1M-byte memory space can be divided into 5

•

64K-byte I/O space can be divided into 3

Automatic setting of 0 to 3 waits for an external I/O cycle

Automatic setting of 0 to 3 waits for a DMA cycle

Automatic setting of 0 to 3 waits for a refresh cycle

Same as V40 and V50 directly after a reset (memory space divided into 3, no division of I/O space)

Figure 7-1. Example of Memory Space Division

Upper Sub

Memory Block

FFFFFH

Upper Memory Block

1 M-Byte

Memory Area

Middle Memory Block

Lower Memory Block

Lower Sub

Memory Block

00000H

Remark The division specification and the size of each block are set by means of a system I/O area register.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Figure 7-2. Example of I/O Space Division

FFFFH

Upper I/O Block

64K-Byte I/O Area

Middle I/O Block

Lower I/O Block

0000H

Remark The division specification and the size of each block are set by means of a system I/O area register.

7.2 RELATION BETWEEN WCU AND READY PIN

When wait cycles exceeding 3 clock cycles are necessary, the WCU and the READY signal pin can be used in

combination. The number of wait cycles specified by the WCU set value or the number of wait cycles under READY control,

whichever is larger, is inserted.

Figure 7-3. WCU and READY Control

V40HL/V50HL

WCU

Bus Control

READY

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

8. REFU (REFRESH CONTROL UNIT)

The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh

interval can be set programmably.

8.1 FEATURES

Lowest-priority refreshing/highest-priority refreshing

•

7-refresh queue

•

16-bit refresh address

•

REFRQ extended timing supported (REFRQ active from T1 state)

8.2 REFRESH OPERATIONS

The REFU has two priorities. Normally, it has the lowest priority, and a refresh cycle cannot be started unless the bus

is completely idle. However, if there are 7 or more pending refresh requests, it is given the highest priority, and it requests

the bus master holding the bus to relinquish it. (See 6. BAU.)

The refresh address is output on A0 to A15. Every refresh cycle the refresh address is incremented by 1 (for the V40HL)

or by 2 (for the V50HL), and the next refresh address is generated.

In a refresh cycle, a low-level signal is output on the low address pins (A16 to A19).

This refresh address is not affected by a reset. When the device is powered on, the refresh address is undefined.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

9. TCU (TIMER/COUNTER UNIT)

The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a

subset of the µPD71054.

9.1

FEATURES

3 × 16-bit counters

•

Six programmable count modes

Binary/BCD count

•

Multiple latch command

Choice of two input clocks: internal/external

9.2 TCU INTERNAL BLOCK DIAGRAM

TCTL1=High

TOUT1 (External) TCTL2 (External)

TOUT2 (External)

TCLK

(External)

CLOCK

TCU

Selection

Signal

TCTL0=High

TOUT0 (To INTL0)

Note 2

Note 1

IORD IOWR

Prescaler

To INTL2/SCU

TCT #0

Read/Write Control

Control Logic

Status

TCT #1

TCT #2

Down Counter (16)

(8)

(16)

TMD

(Mode

H(8) L(8)

Count

H(8) L(8)

Count

Latch

Status

Latch

(8)

Internal Data Bus

Notes 1. A0 or A1 (Set by a system I/O area register)

2. A1 or A2 (Set by a system I/O area register)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

10. SCU (SERIAL CONTROL UNIT)

The SCU performs control of serial communication (asynchronous). Its functions are a subset of the µPD71051 excluding

synchronous communication. Also, what was the control word register in the µPD71051 has been divided into two: a

command register and a mode register.

10.1 FEATURES

Dedicated baud rate generator incorporated (using internal clock)

•

Asynchronous serial communication

•

Clock rate: baud rate × 16, × 64

•

Baud rate: DC – 500 kbps

•

Character length: 7/8 bits

•

Transmit stop bits: 1/2 bits

•

Break transmission

•

Automatic break detection

•

Full-duplex double-buffer system

•

Parity addition/checking

•

Error detection: parity, overrun, framing

•

Interrupt generation maskable

•

10.2 SCU INTERNAL BLOCK DIAGRAM

Baud Rate

From CG

Generator

From TCU

(TOUT1 Output)

RESET

CLOCK

Selector

IORD

IOWR

Note 1

Note 2

Read/Write

Control

SST

Status Register

SCU Selection Signal

SCM

Command Register

Receiver

(Including Receive Buffer)

SRDY (External)

D (External)

SRB

(8)

Receive Data Buffer

STB

Transmit Data Buffer

Transmitter

(Including Transmit Buffer)

RTCLK

SMD

Mode Register

SIMK

Interrupt Mask Register

Interrupt

Generation Logic

SINT (To INTL1)

Notes 1. A0 or A1 (Set by a system I/O area register)

2. A1 or A2 (Set by a system I/O area register)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

11. ICU (INTERRUPT CONTROL UNIT)

The ICU arbitrates among up to 8 interrupt requests (maskable interrupts) generated inside and outside the V40HL and

V50HL, and transfers one of them to the CPU. The ICU functions comprise the functions of the V40HL and V50HL minus

those functions not required by the V40HL and V50HL.

11.1 FEATURES

8 interrupt inputs

•

µPD71059 cascading possible

•

Edge- or level-triggered request input

•

(input from internally connected TCU is edge-triggered only)

Interrupt requests individually maskable

•

Programmable interrupt request priority order

•

Polling operation capability

•

11.2 ICU INTERNAL BLOCK DIAGRAM

SA0

SA1

SA2

Initialize &

Command Word

To BIU

A10

Slave Control

IORD

IOWR

Note 1

Note 2

Read/Write

Control

INTAK (From CPU)

INT (To CPU)

Control Logic

ICU Selection Signal

TOUT0 (From TCU)

SINT (From SCU)

INTL0

INTL1

TOUT1 (From TCU)

Priority

Determina-

tion Logic

INTP1

INTP2

INTP3

INTL2

INTL3

INTL4

INTL5

INTL6

INTL7

Interrupt

Request

(IRQ)

Interrupt

In-Service

(IIS)

External Pins

INTP4

INTP5

INTP6

INTP7

Interrupt

Mask

(IMK)

Internal Data Bus

Notes 1. A0 or A1 (Set by a system I/O area register)

2. A1 or A2 (Set by a system I/O area register)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

12. DMAU (DMA CONTROL UNIT)

The DMAU has 4 DMA channels, and provides the functions (subset) of two LSIs, the µPD71071 and µPD71037.

12.1 FEATURES

Two operating modes (µPD71071 mode, µPD71037 mode)

•

20-bit address register

•

16-bit count register

•

Four independent DMA channels

•

Byte transfer/word transfer selectable

•

Three transfer modes (settable on an individual channel basis)

•

Single transfer mode, demand transfer mode, block transfer mode

Two bus modes (common to all channels: in µPD71037 mode, bus release mode only)

•

Bus release mode

Bus hold mode

DMA requests maskable on an individual channel basis

•

Auto initialization function

•

Transfer address increment/decrement

•

Two channel priority systems (fixed priority/rotating priority)

•

TC output at end of transfer

•

Forced termination of service by END input

•

Cascading capability

•

12.2 DMAU INTERNAL BLOCK DIAGRAM

Address Increment/

DMAU Address Bus (20)

Decrement

(20)

(8)

Internal Address Bus

Internal Data Bus

Address

Registers

Internal Bus

Interface

Control Register Group

Current Address (20 × 4)

Base Address (20 × 4)

Channel^{Note 1}

Device Control

Status

(4)

(10)

(8)

Internal Control Bus

BUSRQ

DMAU Data Bus

BAU

BUSAK

(7 × 4)

(4)

Mode Control

Mask

Count

Registers

Base Count (16 × 4)

Request^{Note 2}

Current Count (16 × 4)

(4)

DMARQ0-

DMARQ3

External

DMAAK0-

pins

Priority Control

DMAAK3

Terminal Count

Count Decrementer

(16)

END/TC

Notes 1. In µPD71071 mode

2. In µPD71037 mode

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

13. STANDBY FUNCTIONS

The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions.

(1) HALT mode

When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit)

is stopped.

(2) STOP mode

When the HALT instruction is executed, all clocks to the CPU and internal I/Os are stopped.

STOP mode should be used when a resonator is connected to the X1 and X2 pins.

Remark Switching between HALT mode and STOP mode is performed by setting a system I/O area register.

14. RESET OPERATION

When the RESET pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the CPU

and on-chip peripheral LSIs are reset.

When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address

FFFF0H.

When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50.

Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved

area.

Table 14-1 shows the main statuses of the on-chip peripheral LSIs when a reset is performed.

Table 14-1. Main Statuses of On-Chip Peripheral LSIs After Reset

Memory, external I/O, DMA & refresh

Upper & lower memory blocks

3-wait insertion

set to 512 KB

WCU

Refresh cycle

set to 72 clock cycles

not affected by reset

REFU

Refresh enabling/disabling

Baud rate

Character

Parity

x 64

7 bits

None

1 bit

SCU

Stop bits

Break detection

None

µPD71071 mode

Demand mode

Auto initialization disabled

Verify transfer, byte transfer

Bus release mode

DMAU

DMA enabled

Caution When a reset is performed, the SCU, TCU, ICU and DMAU cannot be used.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

15. INSTRUCTION SET

Table 15-1. Operand Type Legend

Identifier

Description

reg

8/16-bit general register

(destination register in an instruction using two 8/16-bit general registers)

Source register in an instruction using two 8/16-bit general registers

8-bit general register

reg’

reg8

(destination register in an instruction using two 8-bit general registers)

Source register in an instruction using two 8-bit general registers

16-bit general register

reg8’

reg16

(destination register in an instruction using two 16-bit general registers)

Source register in an instruction using two 16-bit general registers

8/16-bit memory location

reg16’

dmem

mem

8/16-bit memory location

mem8

8-bit memory location

mem16

mem32

imm

16-bit memory location

32-bit memory location

Constant in range 0 to FFFFH

imm3

Constant in range 0 to 7

imm4

Constant in range 0 to FH

imm8

Constant in range 0 to FFH

imm16

acc

Constant in range 0 to FFFFH

Accumulator AW or AL

sreg

Segment register

src-table

src-block

dst-block

near-proc

far-proc

near-label

short-label

far-label

memptr16

Name of 256-byte conversion translation table

Name of block addressed by register IX

Name of block addressed by register IY

Procedure in current program segment

Procedure in a different program segment

Label in current program segment

Label in range –128 to +127 bytes from end of instruction

Label in a different program segment

Word containing location offset in a different program segment to which control is to be shifted and segment

base address

memptr32

Doubleword containing location offset in a different program segment to which control is to be shifted and

segment base address

regptr16

pop-value

fp-op

General register containing location offset in a different program segment to which control is to be shifted

Number of bytes to be removed from stack (0 to 64K, normally an even number)

Immediate value which identifies external floating-point operation coprocessor operation code

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Table 15-2. Operation Code Legend

Identifier

Description

Byte/word specification bit (0: byte, 1: word). However, when s =1, byte data of sign extension is 16-bit

operand if W = 1.

reg

reg’

mem

mod

Memory field (000 to 111)

Mode field (00 to 10)

Sign-extended specification bit (0: without sign extension, 1: with sign extension)

Data used to determine external floating-point coprocessor operation code

X, XXX, YYY, ZZZ

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Table 15-3. Operand Description Legend

Identifier

Description

Accumulator (16-bit)

Accumulator (high-order byte)

Accumulator (low-order byte)

PSW

Base pointer (16-bit)

Stack pointer (16-bit)

Program counter (16-bit)

Program status word (16-bit)

Index register (source) (16-bit)

Index register (destination) (16-bit)

Program segment register (16-bit)

Stack segment register (16-bit)

Data segment 0 register (16-bit)

Data segment 1 register (16-bit)

Auxiliary carry flag

DS0

DS1

Carry flag

Parity flag

Sign flag

Zero flag

DIR

Direction flag

Interrupt enable flag

Overflow flag

BRK

Break flag

Mode flag

...

(

)

Contents of memory indicated by contents of ( )

Displacement (8/16-bit)

16 bits with 8-bit displacement sign-extended

Temporary register (8/16/32-bit)

Temporary register A (16-bit)

Temporary register B (16-bit)

Temporary register C (16-bit)

Temporary carry flag (1-bit)

Immediate segment data (16-bit)

Immediate offset data (16-bit)

Transfer direction

disp

ext-disp8

temp

tmpcy

seg

offset

←

Addition

–

Subtraction

Multiplication

Division

Modulo

Logical product

Logical sum

Exclusive logical sum

Two-digit hexadecimal number

Four-digit hexadecimal number

××H

××××H

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Table 15-4. Flag Operation Legend

Identifier

Description

(Blank)

No change

Cleared to 0

Set to 1

Set or cleared depending upon result

Undefined

Previously saved value is restored

Table 15-5. Memory Addressing

mod

mem

000

BW + IX

BW + IX + disp 8

BW + IY + disp 8

BP + IX + disp 8

BP + IY + disp 8

IX + disp 8

BW + IX + disp 16

BW + IY + disp 16

BP + IX + disp 16

BP + IY + disp 16

IX + disp 16

001

010

011

100

101

110

111

BW + IY

BP + IX

BP + IY

IY + disp 8

IY + disp 16

DIRECT ADDRESS

BP + disp 8

BW + disp 8

BP + disp 16

BW + disp 16

Table 15-6. 8/16-Bit General Register Selection

Table 15-7. Segment Register Selection

sreg

reg, reg’

000

W=0

W=1

DS1

001

010

DS0

011

100

101

110

111

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

The instruction set is shown in tabular form on the following pages.

Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the

following conditions.

• Prefetch time and wait time for using bus, etc. are not included.

• 0 wait is assumed for memory access. That is, the clock number of one bus cycle is four clock cycle.

• 0 wait is assumed for I/O access.

• Primitive block transfer instruction and primitive input/output instruction is included repeat prefixes.

The number of clock cycle of instruction with byte processing and word processing (with W bit) is shown as the followings.

(1) V40HL

On the left of "/"

The value corresponding to byte processing (W= 0) or word processing (W = 1) of even

address

On the right of "/": The value corresponding to word processing (W =1) of odd address

For the clock of block transfer related instruction of V40HL, see Table 15-8.

Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL)

Number of Clock Cycles

Instruction

Byte Processing (W = 0)

Word Processing (W = 1)

MOVBK

CMPBK

CMPM

LDM

9 + 8 × rep

9 + 16 × rep

(9)

(17)

7 + 14 × rep

7 + 22 × rep

(13)

(21)

7 + 10 × rep

7 + 14 × rep

(7)

(11)

7 + 9 × rep

7 + 13 × rep

(7)

(11)

STM

5 + 4 × rep

5 + 8 × rep

(5)

(9)

INM

9 + 8 × rep

9 + 16 × rep

(10)

(18)

OUTM

9 + 8 × rep

9 + 16 × rep

(10)

(18)

Remark The figures in parentheses apply to one-time processing only.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) V50HL

On the left of "/"

The value corresponding to byte processing (W= 0) or word processing (W = 1) of even

address

On the right of "/" : The value corresponding to word processing (W =1) of odd address

For the clock of block transfer related instruction of V50HL, see Table 15-9.

Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction V50HL (1/2)

Number of Clock Cycles

Instruction

Byte Processing

(W = 0)

Word Processing (W = 1)

Odd/Even Address

Odd/Odd Address

Even/Even Address

MOVBK

CMPBK

INM

9 + 8 × rep

9 + 16 × rep

9 + 12 × rep

9 + 8 × rep

(9)

(17)

(13)

(9)

7 + 14 × rep

7 + 22 × rep

7 + 18 × rep

7 + 14 × rep

(13)

(21)

(17)

(13)

9 + 8 × rep

9 + 16 × rep

9 + 12 × rep

9 + 8 × rep

(10)

(18)

(14)

(10)

OUTM

9 + 8 × rep

9 + 16 × rep

9 + 12 × rep

9 + 8 × rep

(10)

(18)

(14)

(10)

Remark The figures in parentheses apply to one-time processing only.

Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction (V50HL) (2/2)

Number of Clock Cycles

Instruction

Byte Processing

(W = 0)

Word Processing (W = 1)

Odd Address

Even Address

CMPM

LDM

7 + 10 × rep

7 + 14 × rep

7 + 10 × rep

(7)

(11)

(7)

7 + 9 × rep

7 + 13 × rep

7 + 9 × rep

(7)

(11)

(7)

STM

5 + 4 × rep

5 + 8 × rep

5 + 4 × rep

(5)

(9)

(5)

Remark The figures in parentheses apply to one-time processing only.

Data Sheet U13225EJ4V0DS00

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Clock Cycles

Flags

Mnemonic Operand(s)

Bytes

Operation

V40HL V50HL

AC CY V

MOV

reg, reg’

1 0 0 0 1 0 1 W 1 1 reg reg’

1 0 0 0 1 0 0 W mod reg mem

1 0 0 0 1 0 1 W mod reg mem

1 1 0 0 0 1 1 W mod 0 0 0 mem

1 0 1 1 W reg

reg ← reg’

mem, reg

reg, mem

mem, imm

reg, imm

acc, dmem

2-4

3-6

2-3

7/11

7/11 (mem) ← reg

10/14 10/14 reg ← (mem)

9/13

9/13 (mem) ← imm

reg ← imm

1 0 1 0 0 0 0 W

10/14 10/14 If W=0: AL ← (dmem)

If W=1: AH ← (dmem + 1), AL ← (dmem)

dmem, acc

1 0 1 0 0 0 1 W

9/13

9/13 If W=0: (dmem) ←AL

If W=1: (dmem + 1) ← AH, (dmem) ←AL

sreg, reg16

1 0 0 0 1 1 1 0

1 1 0 sreg reg

sreg mem

sreg ← reg16

10/14 sreg ← (mem16)

reg16 ← sreg

sreg:SS, DS0, DS1

sreg, mem16 1 0 0 0 1 1 1 0

reg16, sreg 1 0 0 0 1 1 0 0

mem16, sreg 1 0 0 0 1 1 0 0

mod

2-4

1 1 0 sreg reg

mod 0 sreg mem

mod reg mem

2-4

8/12 (mem16) ← sreg

DS0, reg16,

mem32

1 1 0 0 0 1 0 1

17/25 reg16← (mem32)

DS0 ← (mem32 + 2)

DS1, reg16,

mem32

1 1 0 0 0 1 0 0

mod reg mem

2-4

17/25 reg16 ← (mem32)

DS1 ← (mem32 + 2)

AH, PSW

PSW, AH

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

AH ← S, Z, ×, AC, ×, P, ×, CY

S, Z, ×, AC, ×, P, ×, CY← AH

reg16 ←mem16

LDEA

TRANS

XCH

reg16, mem16 1 0 0 0 1 1 0 1

mod reg mem

2-4

src-table

reg, reg’

1 1 0 1 0 1 1 1

AL← (BW + AL)

1 0 0 0 0 1 1 W 1 1 reg reg’

1 0 0 0 0 1 1 W mod reg mem

reg ↔ reg’

mem, reg

reg, mem

2-4

13/21 13/21 (mem) ↔ reg

AW, reg16

reg16, AW

1 0 0 1 0 reg

AW ↔ reg16

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

REPC

Operation

Bytes

AC CY V

7 6 5 4 3 2 1 0

V40HL V50HL

0 1 1 0 0 1 0 1

While CW ≠ 0, the following byte primitive block transfer

instruction is executed and CW is decremented (–1).

If there is a pending interrupt, it is serviced.

If CY ≠ 1 the loop is exited.

REPNC

0 1 1 0 0 1 0 0

1 1 1 1 0 0 1 1

Same as above

If CY ≠ 0 the loop is exited.

REP

While CW ≠ 0, the following byte primitive block transfer

instruction is executed and CW is decremented (–1).

If there is a pending interrupt, it is serviced.

REPE

REPZ

If the primitive block transfer instruction is CMPBK or

CMPM and Z ≠ 1 the loop is exited.

REPNE

REPNZ

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 W

Same as above

If Z ≠ 0 the loop is exited.

MOVBK

dst-block,

src-block

See

If W = 0: (IY) ← (IX)

DIR = 0 : IX ← IX + 1, IY ← IY + 1

DIR = 1 : IX ← IX – 1, IY ← IY – 1

Table Table

15-8

15-9

If W = 1: (IY + 1, IY) ← (IX + 1, IX)

DIR = 0 : IX ← IX + 2, IY ← IY + 2

DIR = 1 : IX ← IX – 2, IY ← IY – 2

src-block,

dst-block

See

Table Table

See

CMPBK

If W = 0: (IX) – (IY)

1 0 1 0 0 1 1 W

DIR = 0 : IX ← IX + 1, IY ← IY + 1

DIR = 1 : IX ← IX – 1, IY ← IY – 1

15-8

15-9

If W = 1: (IX + 1, IX) – (IY + 1, IY)

DIR = 0 : IX ← IX + 2, IY ← IY + 2

DIR = 1 : IX ← IX – 2, IY ← IY – 2

CMPM

LDM

dst-block

src-block

dst-block

1 0 1 0 1 1 1 W

1 0 1 0 1 1 0 W

1 0 1 0 1 0 1 W

See

If W = 0: AL – (IY)

Table Table

15-8

DIR = 0 : IY ← IY + 1; DIR = 1 : IY ← IY – 1

15-9

If W = 1: AW – (IY + 1, IY)

DIR = 0 : IY ← IY + 2; DIR = 1 : IY ← IY – 2

See

If W = 0: AL ← (IX)

Table Table

15-8

DIR = 0 : IX ← IX + 1; DIR = 1 : IX ← IX – 1

15-9

If W = 1: AW ← (IX + 1, IX)

DIR = 0 : IX + 2; DIR = 1 : IX ← IX – 2

STM

See

If W = 0: (IY) ← AL

Table Table

15-8 15-9

DIR = 0 : IY ← IY + 1; DIR = 1 : IY ← IY – 1

If W = 1: (IY + 1, IY) ← AW

DIR = 0 : IY ← IY + 2; DIR = 1 : IY ← IY – 2

Instruc-

tion

Group

Operation Code

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

0 0 1 1 0 0 0 1

V40HL V50HL

INS

reg8, reg8’

reg8, imm4

reg8, reg8’

reg8, imm4

0 0 0 0 1 1 1 1

1 1 reg’ reg

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

1 1 reg’ reg

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

1 1 1 0 0 1 0 W

35-133 31-117/ 16-bit field ← AW

35-133

0 0 1 1 1 0 0 1

0 0 1 1 0 0 1 1

0 0 1 1 1 0 1 1

35-133 31-117/ 16-bit field ← AW

35-133

EXT

34-59 26-55/ AW ← 16-bit field

34-59

34-59 26-55/ AW ← 16-bit field

34-59

acc, imm8

acc, DW

9/13 9/13^NoteIf W = 0: AL ← (imm8)

If W = 1: AH ← (imm8 + 1), AL ← (imm8)

8/12 8/12^NoteIf W = 0: AL ← (DW)

If W = 1: AH ← (DW + 1), AL ← (DW)

8/12 8/12^NoteIf W = 0: (imm8) ← AL

If W = 1: (imm8 + 1) ← AH, (imm8) ← AL

8/12 8/12^NoteIf W = 0: (DW) ← AL

1 1 1 0 1 1 0 W

1 1 1 0 0 1 1 W

1 1 1 0 1 1 1 W

0 1 1 0 1 1 0 W

OUT

INM

OUTM

imm8, acc

DW, acc

If W = 1: (DW + 1) ← AH, (DW) ← AL

dst-block,

See

If W = 0: (IY) ← (DW)

Table Table DIR = 0 : IY ← IY + 1 ; DIR = 1 : IY ← IY – 1

15-8 15-9

If W = 1: (IY + 1, IY) ← (DW + 1, DW)

DIR = 0 : IY ← IY + 2 ; DIR = 1 : IY ← IY – 2

DW,

0 1 1 0 1 1 1 W

See

If W = 0: (DW) ← (IX )

src-block

Table Table DIR = 0 : IX ← IX + 1 ; DIR = 1 : IX ← IX – 1

15-8 15-9

If W = 1: (DW + 1, DW) ← (IX + 1, IX)

DIR = 0 : IX ← IX + 2 ; DIR = 1 : IX ← IX – 2

Note In case of IN/OUT instruction to internal DMAU, the number of word processing clock cycles applied is always that to the right of "/".

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

AC CY V

V40HL V50HL

ADD

reg, reg’

0 0 0 0 0 0 1 W 1 1 reg reg’

0 0 0 0 0 0 0 W mod reg mem

0 0 0 0 0 0 1 W mod reg mem

1 0 0 0 0 0 s W 1 1 0 0 0 reg

1 0 0 0 0 0 s W mod 0 0 0 mem

0 0 0 0 0 1 0 W

reg ← reg + reg’

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

13/21

10/14

13/21 (mem) ← (mem) + reg

10/14 reg ← reg + (mem)

reg ← reg + imm

15/23

15/23 (mem) ← (mem) + imm

If W = 0: AL ← AL + imm

If W = 1: AW ← AW + imm

ADDC

reg, reg’

0 0 0 1 0 0 1 W 1 1 reg reg’

0 0 0 1 0 0 0 W mod reg mem

0 0 0 1 0 0 1 W mod reg mem

1 0 0 0 0 0 s W 1 1 0 1 0 reg

1 0 0 0 0 0 s W mod 0 1 0 mem

0 0 0 1 0 1 0 W

reg ← reg + reg’+ CY

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

13/21

10/14

13/21 (mem) ← (mem) + reg + CY

10/14 reg ← reg + (mem) + CY

reg ← reg + imm + CY

15/23

15/23 (mem) ← (mem) + imm + CY

If W = 0: AL ← AL + imm + CY

If W = 1: AW ← AW + imm + CY

SUB

reg, reg’

0 0 1 0 1 0 1 W 1 1 reg reg’

0 0 1 0 1 0 0 W mod reg mem

0 0 1 0 1 0 1 W mod reg mem

1 0 0 0 0 0 s W 1 1 1 0 1 reg

1 0 0 0 0 0 s W mod 1 0 1 mem

0 0 1 0 1 1 0 W

reg ← reg – reg’

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

13/21

10/14

13/21 (mem) ← (mem) – reg

10/14 reg ← reg – (mem)

reg ← reg – imm

15/23

15/23 (mem) ← (mem) – imm

If W = 0: AL ← AL – imm

If W = 1: AW ← AW – imm

SUBC

reg, reg’

0 0 0 1 1 0 1 W 1 1 reg reg’

0 0 0 1 1 0 0 W mod reg mem

0 0 0 1 1 0 1 W mod reg mem

1 0 0 0 0 0 s W 1 1 0 1 1 reg

1 0 0 0 0 0 s W mod 0 1 1 mem

0 0 0 1 1 1 0 W

reg ← reg – reg’– CY

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

13/21

10/14

13/21 (mem) ← (mem) – reg – CY

10/14 reg ← reg – (mem) – CY

reg ← reg – imm – CY

15/23 (mem) ← (mem) – imm – CY

15/23

If W = 0: AL ← AL – imm – CY

If W = 1: AW ← AW imm– CY

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

ADD4S

Operation

Bytes

7 6 5 4 3 2 1 0

AC CY V

7 6 5 4 3 2 1 0

0 0 1 0 0 0 0 0

V40HL V50HL

0 0 0 0 1 1 1 1

19 × n 19 × n dst BCD string ← dst BCD string + src BCD string*

+ 7 + 7

SUB4S

CMP4S

0 0 1 0 0 0 1 0

0 0 1 0 0 1 1 0

0 0 1 0 1 0 0 0

19 × n 19 × n dst BCD string ← dst BCD string – src BCD string*

+ 7 + 7

19 × n 19 × n dst BCD string – src BCD string*

+ 7

reg

ROL4

reg8

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

mod 0 0 0 mem

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

mod 0 0 0 mem

1 1 1 1 1 1 1 0

AL^L

ALL

AL^L

Lower

Upper

mem

Lower

mem8

reg8

0 0 1 0 1 0 0 0

0 0 1 0 1 0 1 0

1 1 0 0 0 reg

3-5

Upper

reg

Lower

ROR4

Upper

mem

Lower

mem8

3-5

ALL

Upper

INC

reg8

2-4

reg8 ← reg8 + 1

mem

reg16

reg8

1 1 1 1 1 1 1 W mod 0 0 0 mem

0 1 0 0 0 reg

13/21 13/21 (mem) ← (mem) + 1

reg16 ← reg16 + 1

reg8 ← reg8 – 1

DEC

1 1 1 1 1 1 1 0

1 1 0 0 1 reg

mem

reg16

1 1 1 1 1 1 1 W mod 0 0 1 mem

0 1 0 0 1 reg

2-4

13/21 13/21 (mem) ← (mem) – 1

reg16 ← reg16 – 1

n: 1/2 the number of BCD digits

The number of BCD digits is given by the CL register: a value between 1 and 254 can be set.

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 1 0 0 reg

AC CY V

V40HL V50HL

MULU

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

0 1 1 0 1 0 1 1

0 1 1 0 1 0 0 1

21-22 21-22 AW ← AL × reg8

AH = 0: CY ← 0, V ← 0

AH ≠ 0: CY ← 1, V ← 1

26-27 26-27 AW ← AL × (mem8)

mem8

reg16

mem16

reg8

mod 1 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 reg reg’

mod reg mem

1 1 reg reg’

mod reg mem

2-4

AH = 0: CY ← 0, V ← 0

AH ≠ 0: CY ← 1, V ← 1

29-30 29-30 DW, AW ← AW × reg16

DW = 0: CY ← 0, V ← 0

DW ≠ 0: CY ← 1, V ← 1

2-4

38-39 34-35/ DW, AW ← AW × (mem16)

38-39

DW = 0: CY ← 0, V ← 0

DW ≠ 0: CY ←1, V ← 1

MUL

33-39 33-39 AW ←AL × reg8

AH = AL sign extension: CY ← 0, V ← 0

AH ≠ AL sign extension: CY ← 1, V ← 1

38-44 38-44 AW ← AL × (mem8)

mem8

reg16

mem16

2-4

AH = AL sign extension: CY ← 0, V ← 0

AH ≠ AL sign extension: CY ← 1, V ← 1

41-47 41-47 DW, AW ← AW × reg16

DW = AW sign extension: CY ← 0, V ← 0

DW ≠ AW sign extension: CY ← 1, V ← 1

2-4

50-56 46-52/ DW, AW ← AW × (mem16)

50-56

DW = AW sign extension: CY ← 0, V ← 0

DW ≠ AW sign extension: CY ← 1, V ← 1

reg16,

(reg16’,)

imm8

28-34 28-34 reg16 ← reg16’ × imm8

Product ≤ 16 bits : CY ← 0, V ← 0

Product > 16 bits : CY ← 1, V ← 1

37-43 33-39/ reg16 ← (mem16) × imm8

Note

reg16,

mem16,

imm8

3-5

37-43

Product ≤ 16 bits : CY ← 0, V ← 0

Product > 16 bits : CY ← 1, V ← 1

reg16,

(reg16’,)

imm16

reg16,

mem16,

imm16

36-42 36-42 reg16 ← reg16’ × imm16

Product ≤ 16 bits : CY ← 0, V ← 0

Product > 16 bits : CY ← 1, V ← 1

45-51 41-47/ reg16 ← (mem16) × imm16

Note

4-6

45-51

Product ≤ 16 bits : CY ← 0, V ← 0

Product > 16 bits : CY ← 1, V ← 1

Note The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified.

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 1 1 0 reg

AC CY V

V40HL V50HL

DIVU

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

temp ← AW

If temp ÷ reg8 ≤ FFH

AH ← temp%reg8, AL ←temp ÷ reg8

If temp ÷ reg8 > FFH

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

mem8

reg16

mem16

mod 1 1 0 mem

1 1 1 1 0 reg

mod 1 1 0 mem

2-4

temp ← AW

If temp ÷ (mem8) ≤ FFH

AH ← temp%(mem8), AL ←temp ÷ (mem8)

If temp ÷ (mem8) > FFH

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

temp ← DW, AW

If temp ÷ reg16 ≤ FFFFH

DW ← temp%reg16, AW ←temp ÷ reg16

If temp ÷ reg16 > FFFFH

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

2-4

30/34 temp ← DW, AW

If temp ÷ (mem16) ≤ FFFFH

DW ← temp%(mem16), AW ←temp ÷ (mem16)

If temp ÷ (mem16) > FFFFH

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 1 1 1 reg

V40HL V50HL

AC CY V

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

29-34 29-34 temp ← AW

DIV

If temp ÷ reg8 > 0 and temp ÷ reg8 ≤ 7FH

or temp ÷ reg8 < 0 and temp ÷ reg8 > 0 – 7FH –1

AH ← temp%reg8, AL ← temp ÷ reg8

If temp ÷ reg8 > 0 and temp ÷ reg8 > 7FH

or temp ÷ reg8 < 0 and temp ÷ reg8 ≤ 0 – 7FH –1

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

mem8

reg16

mem16

mod 1 1 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

2-4

temp ← AW

34-39 34-39

If temp ÷ (mem8) > 0 and temp ÷ (mem8) ≤ 7FH

or temp ÷ (mem8) < 0 and temp ÷ (mem8) > 0 – 7FH –1

AH ← temp%(mem8), AL ← temp ÷(mem8)

If temp ÷ (mem8) > 0 and temp ÷ (mem8) > 7FH

or temp ÷ (mem8) < 0 and temp ÷ (mem8) ≤ 0 – 7FH –1

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

temp ← DW, AW

38-43 38-43

If temp ÷ reg16 > 0 and temp ÷ reg16 ≤ 7FFFH

or temp ÷ reg16 < 0 and temp ÷ reg16 > 0 – 7FFFH –1

DW ← temp%reg16, AW ← temp ÷ reg16

If temp ÷ reg16 > 0 and temp ÷ reg16 > 7FFFH

or temp ÷ reg16 < 0 and temp ÷ reg16 ≤ 0 – 7FFFH –1

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

2-4

temp ← DW, AW

47-52 43-48/

47-52

If temp ÷ (mem16) > 0 and temp ÷ (mem16) ≤ 7FFFH

or temp ÷ (mem16) < 0 and temp ÷ (mem16) > 0 – 7FFFH

–1

DW ← temp%(mem16), AW ← temp ÷ (mem16)

If temp ÷ (mem16) > 0 and temp ÷ (mem16) > 7FFFH

or temp ÷ (mem16) < 0 and temp ÷ (mem16) ≤ 0 – 7FFFH

–1

TA ← (001H, 000H), TC ← (003H, 002H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

ADJBA

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

AC CY V

0 0 1 1 0 1 1 1

If AL 0FH > 9 or AC = 1: AL ← AL + 6

AH ← AH + 1, AC ← 1, CY ← AC, AL ← AL 0FH

ADJ4A

0 0 1 0 0 1 1 1

If AL 0FH > 9 or AC = 1

AL ← AL + 6, CY ← CY AC , AC← 1

If AL > 9FH or CY = 1

AL ← AL + 60H, CY ← 1

ADJBS

ADJ4S

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

If AL 0FH > 9 or AC = 1

AL ← AL – 6, AH ← AH – 1 , AC← 1

CY ← AC, AL ← AL 0FH

If AL 0FH > 9 or AC = 1

AL ← AL –6, CY ← CY AC , AC← 1

If AL > 9FH or CY = 1

AL ← AL – 60H, CY ← 1

CVTBD

CVTDB

CVTBW

CVTWL

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

AH ← AL ÷ 0AH, AL ← AL%0AH

AL ← AH × 0AH + AL, AH ← 0

If AL < 80H: AH ← 0, otherwise: AH ← FFH

If AW < 8000H: DW ← 0, otherwise: DW ← FFFFH

reg – reg’

4-5

CMP

reg, reg’

0 0 1 1 1 0 1 W 1 1 reg reg’

0 0 1 1 1 0 0 W mod reg mem

0 0 1 1 1 0 1 W mod reg mem

1 0 0 0 0 0 s W 1 1 1 1 1 reg

1 0 0 0 0 0 s W mod 1 1 1 mem

0 0 1 1 1 1 0 W

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

10/14 10/14 (mem) – reg

10/14 10/14

reg – (mem)

reg – imm

12/16 12/16

(mem) – imm

If W = 0: AL – imm

If W = 1: AW – imm

NOT

NEG

reg

1 1 1 1 0 1 1 W 1 1 01 0 reg

1 1 1 1 0 1 1 W mod 0 1 0 mem

1 1 1 1 0 1 1 W 1 1 0 1 1 reg

reg ← reg

13/21 13/21

mem

reg

2-4

(mem) ← (mem)

reg ← reg + 1

(mem) ← (mem) + 1

13/21 13/21

mem

1 1 1 1 0 1 1 W mod 0 1

mem

2-4

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

V40HL V50HL

AC CY V

TEST

reg, reg’

1 0 0 0 0 1 0 W 1 1 reg’ reg

1 0 0 0 0 1 0 W mod reg mem

reg reg’

9/13

mem, reg

reg, mem

2-4

(mem) reg

reg, imm

mem, imm

acc, imm

1 1 1 1 0 1 1 W 1 1 0 0 0 reg

1 1 1 1 0 1 1 W mod 0 0 0 mem

1 0 1 0 1 0 0 W

3-4

3-6

2-3

reg imm

10/14 10/14

(mem) imm

If W = 0: AL imm8

If W = 1: AW imm16

AND

reg, reg’

0 0 1 0 0 0 1 W 1 1 reg reg’

0 0 1 0 0 0 0 W mod reg mem

0 0 1 0 0 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 1 0 0 reg

1 0 0 0 0 0 0 W mod 1 0 0 mem

0 0 1 0 0 1 0 W

reg ← reg reg’

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

13/21 13/21 (mem) ← (mem) reg

10/14 10/14

reg ← reg (mem)

reg ← reg imm

15/23 15/23 (mem) ← (mem) imm

If W = 0: AL ← AL imm8

If W = 1: AW ← AW imm16

reg, reg’

0 0 0 0 1 0 1 W 1 1 reg reg’

0 0 0 0 1 0 0 W mod reg mem

0 0 0 0 1 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 0 0 1 reg

1 0 0 0 0 0 0 W mod 0 0 1 mem

0 0 0 0 1 1 0 W

reg ← reg reg’

13/21 13/21

10/14 10/14

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

(mem) ← (mem) reg

reg ← reg (mem)

reg ← reg imm

15/23 15/23

(mem) ← (mem) imm

If W = 0: AL ← AL imm8

If W = 1: AW ← AW imm16

XOR

reg, reg’

0 0 1 1 0 0 1 W 1 1 reg reg’

0 0 1 1 0 0 0 W mod reg mem

0 0 1 1 0 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 1 1 0 reg

1 0 0 0 0 0 0 W mod 1 1 0 mem

0 0 1 1 0 1 0 W

reg ← reg reg’

13/21 13/21

10/14 10/14

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

2-4

3-4

3-6

2-3

(mem) ← (mem) reg

reg ← reg (mem)

reg ← reg imm

15/23 15/23 (mem) ← (mem) imm

If W = 0: AL ← AL imm8

If W = 1: AW ← AW imm16

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 0 0 0 reg

V40HL V50HL

AC CY V

TEST1

reg8, CL

0 0 0 1 0 0 0 0

reg8 bit NO.CL = 0 : Z ← 1

reg8 bit NO.CL = 1 : Z ← 0

mem8, CL

reg16, CL

0 0 0 0

mod 0 0 0 mem

1 1 0 0 0 mem

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

3-5

(mem8) bit NO.CL = 0 : Z← 1

(mem8) bit NO.CL = 1 : Z← 0

0 0 0 1

reg16 bit NO.CL = 0 : Z ← 1

reg16 bit NO.CL = 1 : Z ← 0

7/11

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

0 0 0 1

3-5

(mem16) bit NO.CL = 0 : Z← 1

(mem16) bit NO.CL = 1 : Z← 0

1 0 0 0

reg8 bit NO.imm3 = 0 : Z ← 1

reg8 bit NO.imm3 = 1 : Z ← 0

1 0 0 0

4-6

(mem8) bit NO.imm3 = 0 : Z← 1

(mem8) bit NO.imm3 = 1 : Z← 0

1 0 0 1

reg16 bit NO.imm4 = 0 : Z ← 1

reg16 bit NO.imm4 = 1 : Z ← 0

8/12

1 0 0 1

4-6

(mem16) bit NO.imm4 = 0 : Z← 1

(mem16) bit NO.imm4 = 1 : Z← 0

NOT1

reg8, CL

0 1 1 0

0 1 1 1

1 1 1 0

1 1 1 1

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

3-5

reg8 bit NO.CL← reg8 bit NO.CL

(mem8) bit NO.CL← (mem8) bit NO.CL

reg16 bit NO.CL← reg16 bit NO.CL

mem8, CL

reg16, CL

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

3-5

10/18 (mem16) bit NO.CL← (mem16) bit NO.CL

reg8 bit NO.imm3← reg8 bit NO.imm3

4-6

(mem8) bit NO.imm3← (mem8) bit NO.imm3

reg16 bit NO.imm4← reg16 bit NO.imm4

(mem16) bit NO.imm4← (mem16) bit NO.imm4

11/19

4-6

2nd byte*

3rd byte*

* 1st byte = 0FH

CY← CY

NOT1

1 1 1 1 0 1 0 1

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 mem

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

V40HL V50HL

CLR1

reg8, CL

0 0 0 1 0 0 1 0

0 0 1 0

0 0 1 1

1 0 1 0

1 0 1 1

0 1 0 0

0 1 0 1

1 1 0 0

1 1 0 1

3-5

reg8 bit NO.CL ← 0

mem8, CL

reg16, CL

(mem8) bit NO.CL ← 0

reg16 bit NO.CL ← 0

(mem16) bit NO.CL ← 0

reg8 bit NO.imm3 ← 0

11/19

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

reg8, CL

3-5

4-6

(mem8) bit NO.imm3 ← 0

reg16 bit NO.imm4 ← 0

(mem16) bit NO.imm4 ← 0

reg8 bit NO.CL ← 1

12/20

4-6

SET1

mem8, CL

reg16, CL

3-5

(mem8) bit NO.CL ← 1

reg16 bit NO.CL ← 1

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

3-5

10/18 (mem16) bit NO.CL ← 1

reg8 bit NO.imm3 ← 1

(mem8) bit NO.imm3 ← 1

reg16 bit NO.imm4 ← 1

(mem16) bit NO.imm4 ← 1

4-6

11/19

4-6

2nd byte*

3rd byte*

* 1st byte = 0FH

CLR1

SET1

1 1 1 1 1 0 0 0

1 1 1 1 1 1 0 0

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 1

CY ← 0

DIR ← 0

CY ← 1

DIR ← 1

DIR

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Bytes

Operation

V40HL V50HL

AC CY V

SHL

reg, 1

1 1 0 1 0 0 0 W 1 1 1 0 0 reg

1 1 0 1 0 0 0 W mod 1 0 0 mem

1 1 0 1 0 0 1 W 1 1 1 0 0 reg

1 1 0 1 0 0 1 W mod 1 0 0 mem

1 1 0 0 0 0 0 W 1 1 1 0 0 reg

CY ← reg MSB, reg ← reg × 2

If reg MSB ≠ CY: V ← 1

If reg MSB = CY: V ← 0

mem, 1

reg, CL

mem, CL

reg, imm8

2-4

13/21 13/21 CY ← (mem) MSB, (mem) ← (mem) × 2

If (mem) MSB ≠ CY: V ← 1

If (mem) MSB = CY: V ← 0

7 + n 7 + n temp ← CL, while temp ≠0 the following operation are repeated:

CY ← reg MSB, reg ← reg × 2

temp ← temp – 1

2-4

16/24 16/24 temp ← CL, while temp ≠0 the following operation are repeated:

+ n

CY ← (mem) MSB, (mem) ← (mem) × 2

temp ← temp – 1

7 + n 7 + n temp ← imm8, while temp ≠ 0 the following operations are

repeated:

CY ← reg MSB, reg← reg × 2

temp ← temp – 1

mem, imm8

1 1 0 0 0 0 0 W mod 1 0 0 mem

3-5

16/24 16/24 temp ← imm8, while temp ≠ 0 the following operations are

+ n

repeated:

CY ← (mem) MSB, (mem) ← (mem) × 2

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

AC CY V

7 6 5 4 3 2 1 0

V40HL V50HL

SHR

reg, 1

1 1 0 1 0 0 0 W 1 1 1 0 1 reg

1 1 0 1 0 0 0 W mod 1 0 1 mem

1 1 0 1 0 0 1 W 1 1 1 0 1 reg

CY ← reg LSB, reg ← reg ÷ 2

If reg MSB ≠ bit after reg MSB : V ← 1

If reg MSB = bit after reg MSB : V ← 0

mem, 1

reg, CL

2-4

13/21 13/21 CY ← (mem) LSB, (mem) ← (mem) ÷ 2

If (mem) MSB ≠ bit after (mem) MSB : V ← 1

If (mem) MSB = bit after (mem) MSB : V ← 0

7 + n 7 + n temp ← CL, while temp ≠ 0 the following operations are

repeated:

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

mem, CL

1 1 0 1 0 0 1 W mod 1 0 1 mem

2-4

16/24 16/24 temp ← CL, while temp ≠ 0 the following operations are

+ n

repeated:

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1

reg, imm8

mem, imm8

1 1 0 0 0 0 0 W 1 1 1 0 1 reg

7 + n 7 + n temp ← imm8, while temp ≠ 0 the following operations are

repeated:

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

1 1 0 0 0 0 0 W

3-5

16/24 16/24 temp ← imm8, while temp ≠ 0 the following operations are

mod 1 0 1 mem

+ n

repeated:

CY ← (mem) LSB,(mem) ← (mem) ÷ 2

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

AC CY V

7 6 5 4 3 2 1 0

V40HL V50HL

SHRA

reg, 1

1 1 0 1 0 0 0 W 1 1 1 1 1 reg

1 1 0 1 0 0 0 W mod 1 1 1 mem

1 1 0 1 0 0 1 W 1 1 1 1 1 reg

CY ← reg LSB, reg ← reg ÷ 2, V ← 0

MSB of operand is unchanged.

mem, 1

reg, CL

2-4

13/21

7 + n

CY ← (mem) LSB,(mem) ← (mem) ÷ 2, V ← 0

MSB of operand is unchanged.

13/21

7 + n

temp ← CL, while temp ≠ 0 the following operations are

repeated:

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1, MSB of operand is unchanged.

mem, CL

1 1 0 1 0 0 1 W mod 1 1 1 mem

1 1 0 0 0 0 0 W 1 1 1 1 1 reg

1 1 0 0 0 0 0 W mod 1 1 1 mem

2-4

16/24

+ n

temp ← CL, while temp ≠ 0 the following operations are

repeated:

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1, MSB of operand is unchanged.

16/24

+ n

reg, imm8

mem, imm8

7 + n

temp ← imm8, while temp ≠ 0 the following operations are

repeated:

7 + n

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1, MSB of operand is unchanged.

3-5

16/24

+ n

temp ← imm8, while temp ≠ 0 the following operations are

repeated:

16/24

+ n

CY ← (mem) LSB,(mem) ← (mem) ÷ 2

temp ← temp – 1, MSB of operand is unchanged.

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

ROL

reg, 1

1 1 0 1 0 0 0 W 1 1 0 0 0 reg

1 1 0 1 0 0 0 W mod 0 0 0 mem

1 1 0 1 0 0 1 W 1 1 0 0 0 reg

CY ← reg MSB, reg ← reg × 2 + CY

reg MSB ≠ CY : V ← 1

reg MSB = CY : V ← 0

13/21

7 + n

mem, 1

reg, CL

2-4

13/21

7 + n

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

(mem) MSB ≠ CY : V ← 1

(mem) MSB = CY : V ← 0

temp ← CL, while temp ≠ 0 the following operations are

repeated:

CY ← reg MSB, reg ← reg × 2 + CY

temp ← temp – 1

16/24

+ n

mem, CL

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

2-4

16/24

+ n

temp ← CL, while temp ≠ 0 the following operations are

repeated:

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

temp ← temp – 1

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 + n

reg, imm8

mem, imm8

7 + n

temp ← imm8, while temp ≠ 0 the following operations are

repeated:

CY ← reg MSB, reg ← reg × 2 + CY

temp ← temp – 1

16/24

+ n

3-5

16/24

+ n

temp ← imm8, while temp ≠ 0 the following operations are

repeated:

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

CY ← reg LSB, reg← reg ÷ 2

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

ROR

reg, 1

1 1 0 1 0 0 0 W 1 1 0 0 1 reg

1 1 0 1 0 0 0 W mod 0 0 1 mem

1 1 0 1 0 0 1 W 1 1 0 0 1 reg

1 1 0 1 0 0 1 W mod 0 0 1 mem

1 1 0 0 0 0 0 W 1 1 0 0 1 reg

reg MSB ← CY

reg MSB ≠ bit after reg MSB : V ← 1

reg MSB = bit after reg MSB : V ← 0

13/21

7 + n

mem, 1

reg, CL

mem, CL

reg, imm8

2-4

13/21

7 + n

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

(mem) MSB ← CY

(mem) MSB ≠ bit after (mem) MSB : V ← 1

(mem) MSB = bit after (mem) MSB : V ← 0

temp←CL, whileCL ≠ 0thefollowingoperationsarerepeated:

CY ← reg LSB, reg ← reg ÷ 2

reg MSB ← CY

temp ← temp – 1

16/24

+ n

2-4

16/24

+ n

temp←CL, whileCL ≠ 0thefollowingoperationsarerepeated:

CY ← (mem) LSB,(mem) ← (mem) ÷ 2

(mem) MSB ← CY

temp ← temp – 1

7 + n

temp ← imm8, while CL ≠ 0 the following operations are

repeated:

CY ← reg LSB,reg ← reg ÷ 2

reg MSB ← CY

temp ← temp – 1

16/24

+ n

mem, imm8

1 1 0 0 0 0 0 W mod 0 0 1 mem

3-5

16/24

+ n

temp ← imm8, while CL ≠ 0 the following operations are

repeated:

CY ← (mem) LSB,(mem) ← (mem) ÷ 2

(mem) MSB ← CY

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

1 1 0 1 0 0 0 W 1 1 0 1 0 reg

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

ROLC

reg, 1

tmpcy ← CY, CY ← reg MSB

reg ← reg × 2 + tmpcy

reg MSB ≠ CY : V ← 1

reg MSB = CY : V ← 0

mem, 1

reg, CL

1 1 0 1 0 0 0 W

mod 0 1 0 mem

2-4

tmpcy ← CY, CY ← (mem) MSB

(mem)← (mem) × 2 + tmpcy

(mem) MSB ≠ CY : V ← 1

(mem) MSB = CY : V ← 0

13/21 13/21

1 1 0 1 0 0 1 W 1 1 0 1 0 reg

temp ← CL, while CL ≠ 0 the following operations are re-

peated:

7 + n 7 + n

tmpcy← CY, CY ← reg MSB

reg ← reg × 2 + tmpcy

temp ← temp – 1

mem, CL

reg, imm8

1 1 0 1 0 0 1 W

mod 0 1 0 mem

2-4

temp←CL, whileCL≠ 0thefollowingoperationsarerepeated:

tmpcy ← CY, CY ← (mem) MSB

(mem) ← (mem) × 2 + tmpcy

16/24 16/24

+ n

temp ← temp – 1

1 1 0 0 0 0 0 W 1 1 0 1 0 reg

temp ← imm8, while CL ≠ 0 the following operations are

repeated:

7 + n 7 + n

tmpcy ← CY, CY ← reg MSB

reg ← reg × 2 + tmpcy

temp ← temp – 1

mem, imm8

1 1 0 0 0 0 0 W

mod 0 1 0 mem

3-5

temp ← imm8, while CL ≠ 0 the following operations are

repeated:

16/24 16/24

+ n + n

tmpcy ← CY, CY ← (mem) MSB

(mem) ← (mem) × 2 + tmpcy

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

1 1 0 1 0 0 0 W 1 1 0 1 1 reg

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

RORC

reg, 1

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

reg MSB ≠ bit after reg MSB : V ← 1

reg MSB = bit after reg MSB : V ← 0

13/21

7 + n

mem, 1

reg, CL

mem, CL

reg, imm8

1 1 0 1 0 0 0 W

mod 0 1 1 mem

2-4

13/21

7 + n

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

(mem) MSB ≠ bit after (mem) MSB : V ← 1

(mem) MSB = bit after (mem) MSB : V ← 0

1 1 0 1 0 0 1 W 1 1 0 1 1 reg

temp← CL, whileCL≠ 0thefollowingoperationsarerepeated:

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

temp ← temp – 1

16/24

+ n

1 1 0 1 0 0 1 W

mod 0 1 1 mem

2-4

16/24

+ n

temp← CL, whileCL≠ 0thefollowingoperationsarerepeated:

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

temp ← temp – 1

7 + n

1 1 0 0 0 0 0 W 1 1 0 1 1 reg

7 + n

temp ←imm8, while CL ≠ 0 the following operations are

repeated:

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

temp ← temp – 1

16/24

+ n

mem, imm8

1 1 0 0 0 0 0 W

mod 0 1 1 mem

3-5

16/24

+ n

temp ← imm8, while CL ≠ 0 the following operations are

repeated:

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

temp ← temp – 1

n: Number of shifts

Instruc-

tion

Group

Operation Code

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

CALL

16/20

near-proc

regptr16

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

1 1 1 1 1 1 1 1

SP ← SP – 2, (SP + 1, SP) ← PC

PC ← PC + disp

14/18

1 1 0 1 0 reg

mod 0 1 0 mem

SP ← SP – 2, (SP + 1, SP) ← PC

PC ← regptr16

memptr16

far-proc

2-4

23/31 TA ← (memptr16)

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

21/29

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← seg

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← offset

memptr32

mod 0 1 1 mem

2-4

31/47 TA ← (memptr32),TB ← (memptr32 + 2)

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TB

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

RET

15/19

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

PC ← (SP + 1, SP)

SP ← SP + 2

20/24

pop-value

PC ← (SP + 1, SP)

SP ← SP + 2, SP ← SP + pop-value

21/29 PC ← (SP + 1, SP)

PS ← (SP + 3, SP + 2)

PS ← SP + 4

24/32

1 1 0 0 1 0 1 0

PC ← (SP + 1, SP)

PS ← (SP + 3, SP + 2)

SP ← SP + 4, SP ← SP + pop-value

Instruc-

tion

Group

Operation Code

Flags

AC CY V P

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

2-4

7 6 5 4 3 2 1 0

mod 1 1 0 mem

V40HL V50HL

PUSH

15/23

mem16

reg16

sreg

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 sreg 1 1 0

1 0 0 1 1 1 0 0

SP ← SP – 2

(SP + 1, SP) ← (mem16)

6/10 SP ← SP – 2

(SP + 1, SP) ← reg16

6/10

SP ← SP – 2

(SP + 1, SP) ← sreg

6/10

PSW

SP ← SP – 2

(SP + 1, SP) ← PSW

33/65

5/9

0 1 1 0 0 0 0 0

0 1 1 0 1 0 1 0

Push registers on the stack

imm8

SP ← SP – 2

(SP + 1, SP) ← imm8, sign of extension

imm16

0 1 1 0 1 0 0 0

6/10 SP ← SP – 2

(SP + 1, SP) ← imm16

(mem16) ← (SP + 1, SP)

SP ← SP + 2

2-4

mem16

reg16

sreg

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 sreg 1 1 1

mod 0 0 0 mem

16/24

8/12

POP

reg16← (SP + 1, SP)

SP ← SP + 2

sreg← (SP + 1, SP)

SP ← SP + 2

sreg : SS, DS0, DS1

PSW← (SP + 1, SP)

SP ← SP + 2

PSW

1 0 0 1 1 1 0 1

0 1 1 0 0 0 0 1

Pop registers from the stack

Prepare New Stack Frame

Dispose of Stack Frame

43/75

Note 2

6/10

Note 1

imm16, imm8 1 1 0 0 1 0 0 0

1 1 0 0 1 0 0 1

PREPARE

DISPOSE

Notes1. If imm8 = 0 16

If imm8 ≥ 1

21 + 16 (imm8 – 1)

2. If imm8 = 0 12/16

If imm8 ≥ 1

{17 + 8 (imm8 – 1)} / {21 + 16 (imm8 – 1)}

Instruc-

tion

Group

Operation Code

Flags

AC CY V

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

near-label

short-label

regptr16

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

PC ← PC+ dsip

PC ← PC+ ext-disp8

PC ← regptr16

1 1 1 0 0 reg

mod 1 0 0 mem

memptr16

far-label

2-4

19/23 PC ← (memptr16)

PS ← seg

PC ← offset

26/34

memptr32

1 1 1 1 1 1 1 1

mod 1 0 1 mem

2-4

PS ← (memptr32 + 2)

PC ← (memptr32)

Clock Cycles^Note

V40HL V50HL

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

AC CY V

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

14/4

short-label

0 1 1 1 0 0 0 0

0 0 0 1

14/4

if V = 1

if V = 0

if CY = 1

PC ← PC + ext-disp8

BNV

PC ← PC + ext-disp8

0 0 1 0

BNC

BNL

14/4

short-label

0 0 1 1

0 1 0 0

0 1 0 1

14/4

if CY = 0

if Z = 1

if Z = 0

PC ← PC + ext-disp8

BNE

BNZ

BNH

14/4

14/5

short-label

0 1 1 0

0 1 1 1

14/4

14/5

if CY Z = 1

if CY Z = 0

if S = 1

PC ← PC + ext-disp8

1 0 0 0

1 0 0 1

if S = 0

BPE

BPO

BLT

1 0 1 0

if P = 1

1 0 1 1

if P = 0

1 1 0 0

if S V = 1

if S V = 0

if (S V) Z = 1

if (S V) Z = 0

BGE

BLE

BGT

DBNZNE

1 1 0 1

1 1 1 0

1 1 1 1

1 1 1 0 0 0 0 0

CW = CW – 1

if Z = 0 and CW ≠ 0

DBNZE

DBNZ

14/5

13/5

short-label

1 1 1 0 0 0 0 1

1 1 1 0 0 0 1 0

1 1 1 0 0 0 1 1

14/5

13/5

CW = CW – 1

PC ← PC + ext-disp8

if Z = 1 and CW ≠ 0

CW = CW – 1

if CW ≠ 0

BCWZ

if CW = 0

Note Condition determination: true/false

Instruc-

tion

Group

Operation Code

Flags

AC CY V P

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

7 6 5 4 3 2 1 0

V40HL V50HL

BRK

38/50

1 1 0 0 1 1 0 0

1 1 0 0 1 1 0 1

1 1 0 0 1 1 1 0

TA ← (00DH, 00CH), TC ← (00FH, 00EH)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

imm8

( = 3)

38/50 TA ← (4 n + 1, 4n), TC ← (4n + 3, 4n + 2) n = imm8

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

BRKV

Note 2

Note 1

If V = 1

TA ← (011H, 010H), TC ← (013H, 012H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

RETI

27/39

38/50

1 1 0 0 1 1 1 1

0 0 0 0 1 1 1 1

PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2),

PSW ← (SP + 5, SP + 4), SP ← SP + 6

BRKEM

imm8

1 1 1 1 1 1 1 1

TA ← (4 n + 1, 4n), TC ← (4n + 3, 4n + 2) n = imm8

SP ← SP – 2, (SP + 1, SP) ← PSW, MD ← 0

MD is set to write enabled

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

CHKIND

Note 4

reg16, mem32 0 1 1 0 0 0 1 0

mod reg mem

2-4

Note 3

If (mem32) > reg16 or (mem32 + 2) < reg16

TA ← (015H, 014H), TC ← (017H, 016H)

SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

Notes 1. When V = 1: 52

When V = 0: 3

2. When V = 1: 40/52

When V = 0: 3

3. When interrupt condition is established

: 72 to 75

: 25

When interrupt condition is not established

4. When interrupt condition is established

When interrupt condition is not established

: (52 to 55)/(72 to 75)

: 17/25

Instruc-

tion

Group

Operation Code

7 6 5 4 3 2 1 0

Flags

Clock Cycles

Mnemonic Operand(s)

Operation

Bytes

AC CY V

7 6 5 4 3 2 1 0

V40HL V50HL

HALT

POLL

1 1 1 1 0 1 0 0

1 0 0 1 1 0 1 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 0 0 0

CPU Halt

2 + 5n

Poll and wait n: Number of times POLL pin is sampled

IE ← 0

IE ← 1

BUSLOCK

Bus Lock Prefix

No Operation

FPO1

FPO2

NOP

fp-op

1 1 0 1 1

1 1

mod

1 1

mod

fp-op, mem

fp-op

mem

2-4

10/14 data bus ← (mem)

10/14

0 1 1 0 0 1 1

No Operation

fp-op, mem

mem

2-4

data bus ← (mem)

No Operation

1 0 0 1 0 0 0 0

0 0 1 sreg 1 1 0

Segment override prefix

DS0:, DS1:, PS:, and SS:.

Instruc-

tion

Group

Operation Code

Flags

Clock Cycles

Mnemonic Operand(s)

RETEM

Operation

Bytes

7 6 5 4 3 2 1 0

1 1 1 0 1 1 0 1

V40HL V50HL

AC CY V

7 6 5 4 3 2 1 0

1 1 1 1 1 1 0 1

27/39 PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2),

PSW ← (SP + 5, SP + 4), SP ← SP + 6, MD is set to write

disabled

CALLN

38/58

imm8

1 1 1 0 1 1 0 1

TA ← (4n + 1, 4n), TC ← (4n + 3, 4n + 2)

n = imm8

SP ← SP – 2, (SP + 1, SP) ← PSW, MD ← 1

SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC

SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA

µPD70208H, 70216H

16. ELECTRICAL SPECIFICATIONS

Applied standard

The electrical characteristics shown below are applied to devices other than the old models conforming

to K mask.

Therefore, these characteristics are different from those conforming to the K mask. For the electrical

characteristics of the K mask, consult NEC.

“Others” in the table below means products conforming to the masks other than E, P, X, and M (but

conforming to the L, F mask).

16.1 AT 5 V OPERATION

OPERATING RANGE

E, P, X, M Mask Model

VDD = 5 V ±10%

—

Others

µPD70208H, 70216H-10/12/16

µPD70208H, 70216H-20

VDD = 5 V ±5%

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Supply voltage

Symbol

Test Conditions

Rating

Unit

V^DD

–0.5 to +7.0

VDD = 5 V ±10%

Input voltage

–0.5 to V^DD+ 0.3

–0.5 to VDD + 1.0

–0.5 to VDD + 0.3

–40 to +85

(µPD70208H, 70216H-10/12/16)

VDD = 5 V ±5%

Clock input voltage

Output voltage

(µPD70208H, 70216H-20)

Operating ambient temperature

Storage temperature

°C

Tstg

–65 to +150

Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect

the output pins to V^DDor VCC and GND. However, open-drain pins or open-collector pins may be

connected directly. Moreover, an external circuit whose timing is designed to avoid output

collision can be connected to pins that go into a high-impedance state.

2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the

quality of the program may be degraded. Absolute maximum ratings, therefore, are the values

exceeding which the product may be physically damaged. Use the program keeping all the

parameters within these rated values.

The standards and conditions shown in DC and AC Characteristics below specify the range within

which the normal operation of the product is guaranteed.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DC CHARACTERISTICS

(T^A= –40 to +85 °C, VDD = 5 V ±10% (µPD70208H, 70216H-10/12/16), VDD = 5 V ±5% (µPD70208H, 70216H-20))

Parameter

Input voltage high

Symbol

Test Conditions

Except RESET

MIN.

2.2

TYP.

MAX.

Unit

VIH

E, P, X, M

masks

VDD+0.3

V^DD+0.3

RESET

0.8 VDD

2.2

Others

Except RESET,

INTP1 to INTP7

RESET

0.8 VDD

2.4

VDD+0.3

+0.8

INTP1 to INTP7

Input voltage low

VIL

Except RESET

RESET

–0.5

0.2VDD

VDD+1.0

+0.6

Clock input voltage high

Clock input voltage low

Output voltage high

VKH

VKL

VOH

3.9

–0.5

IOH = –2.5 mA

0.7 VDD

VDD – 0.4

IOH = –100 µA

Output voltage low

VOL

Except END/TC : IOL = 2.5 mA

0.4

END/TC

: IOL = 5.0 mA

Input leak current high

Input leak current low

ILIH

ILIL

VI = VDD

–10

µA

Except INTP:VI = 0 V

INTP input:VI = 0 V

VO = VDD

INTP input current low

Output leak current high

Output leak current low

Latch leak current high

Latch leak current low

ILIPL

ILOH

ILOL

ILLH

ILLL

IILH

IILL

–300

VO = 0 V

–10

VI = 3.0 V

–50

–300

300

VI = 0.8 V

Latch inversion current (L → H)

Latch inversion current (H → L)

400

–400

9.0 fX

2.5 fX

Note

Supply current

IDD

E, P, X, M

masks

On operation

5.5 fX

1.5 fX

On standby (HALT)

On standby (STOP)

On operation

µA

Others

4.5 fX

1.5 fX

6.0 fX

2.2 fX

On standby (HALT)

On standby (STOP)

µA

Note The unit of constant values (1.5, 2.2, 2.5, 4.5, 5.5, 6.0 and 9.0) is mA/MHz.

CAPACITANCE (TA = 25 ˚C, VDD = 0 V)

Parameter

Input capacitance

Input/output capacitance

Symbol

Test Conditions

fC = 1 MHz

MIN.

TYP.

MAX.

Unit

CIO

0 V other than test pin.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

AC CHARACTERISTICS

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 5 V ±10%) (1/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-10

µPD70208H-12

µPD70216H-12

µPD70208H-16

µPD70216H-16

Parameter

Symbol

µPD70216H-10

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

31.25

MAX.

External clock input cycle

tCYX

tXXH

tXXL

tXR

<1>

<2>

<3>

<4>

<5>

<6>

<7>

<8>

<9>

<10>

<11>

<12>

<13>

<14>

External clock input high-level width (VKH=3.0 V)

External clock input low-level width (VKL=1.5 V)

External clock input rise time (1.5→3.0 V)

External clock input fall time (3.0→1.5 V)

Clock output cycle

tXF

tCYK

tKKH

tKKL

tKR

100

62.5

Clock output high-level width (VOH=3.0 V)

Clock output low-level width (VOL=1.5 V)

Clock output rise time (1.5→3.0 V)

0.5tCYK–5

Clock output fall time (3.0→1.5 V)

tKF

CLKOUT delay time (vs. external clock)

Input rise time (except external clock) (0.8→2.2 V)

Input fall time (except external clock) (2.2→0.8 V)

tDXK

tIR

tIF

Output rise time

E, P, X, M masks

Others

tOR

(except CLKOUT) (0.8→2.2 V)

Output fall time (except CLKOUT) (2.2→0.8 V)

tOF

<15>

<16>

<17>

<18>

<19>

<20>

<21>

<22>

<23>

<24>

<25>

<26>

<27>

<28>

<29>

<30>

<31>

<32>

<33>

Note 1

RESET setup time (vs. CLKOUT↓)

tSRESK

tHKRES

tDKRES

tSRYLK

tHKRYL

tSRYHK

tHKRYH

tSNMIK

tSPOLK

tSDK

Note 1

RESET hold time (vs. CLKOUT↓)

RESOUT output delay time (vs. CLKOUT↓)

READY inactive setup time (vs. CLKOUT↑)

READY inactive hold time (vs. CLKOUT↑)

READY active setup time (vs. CLKOUT↑)

READY active hold time (vs. CLKOUT↑)

NMI setup time (vs. CLKOUT↑)

POLL setup time (vs. CLKOUT↑)

Data setup time (vs. CLKOUT↓)

Data hold time (vs. CLKOUT↓)

tHKD

Note 2

CLKOUT → address delay time

tDKA

CLKOUT → address hold time

CLKOUT↓ → PS delay time

tHKA

tDKP

CLKOUT↓ → PS float delay time

Address setup time (vs. ASTB↓)

tFKP

tSAST

tFKA

tKKL–20

tHKA

tKKL–10

tHKA

tKKL–10

tHKA

Note 3

CLKOUT↓ → address float delay time

CLKOUT↓ → ASTB↑ delay time

tDKSTH

Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.

2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,

BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,

IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 5 V ±10%) (2/3)

µPD70208H-10

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-12

µPD70216H-12

µPD70208H-16

µPD70216H-16

Parameter

Symbol

µPD70216H-10

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

CLKOUT↑ → ASTB↓ delay time

<34> tDKSTL

<35> tSTST

<36> tHSTA

<37> tDKCT1

<38> tDKCT2

<39> tDAFRL

<40> tDKRL

<41> tDKRH

<42> tDRHA

<43> tRR

ASTB high-level width

tKKL–10

ASTB↓ → address hold time

tKKH–20

tKKH–10

Note 1

CLKOUT → control 1

CLKOUT → control 2

delay time

Note 2

delay time

Address float → RD↓ delay time

CLKOUT↓ → RD↓ delay time

CLKOUT↓ → RD↑ delay time

RD↑ → address delay time

tCYK–40

tCYK–20

tCYK–10

RD low-level width

2tCYK–40

2tCYK–20

BUFEN↑ → BUFR/W delay time (read cycle)

CLKOUT↓ → data output delay time

CLKOUT↓ → data float delay time

WR low-level width

<44> tDBECT

<45> tDKD

tKKL–20

tKKL–10

<46> tFKD

<47> tWW

2tCYK–40

2tCYK–20

WR↑ → BUFEN↑ or BUFR/W↓ (write cycle)

CLKOUT↑ → BS↓ delay time

<48> tDWCT

<49> tDKBL

<50> tDKBH

<51> tSHQK

<52> tDKHA

<53> tDKHDA

<54> tDKLDA

<55> tWW1

<56> tWW2

<57> tDDARW

tKKL–20

tKKL–10

CLKOUT↓ → BS↑ delay time

HLDRQ setup time (vs. CLKOUT↓)

CLKOUT↓ → HLDAK delay time

CLKOUT↑ → DMAAK delay time

CLKOUT↓ → DMAAK delay time (cascade mode)

WR low-level width

(DMA cycle)

DMA extended write

DMA normal write

2tCYK–40

tCYK–40

tKKH–30

tKKL–30

2tCYK–20

tCYK–20

tKKH–20

tKKL–20

2tCYK–20

tCYK–15

tKKH–15

tKKL–15

RD↓, WR↓ delay time (vs. DMAAK↓)

DMAAK↑ delay time (vs. RD↑)

RD↑ delay time (vs. WR↑)

<58>

tDRHDAH

<59> tDWHRH

<60> tDKTCL

<61> tDKTCF

<62> tTCTCL

<63> tDKTCH

<64> tSEDK

<65> tEDEDL

<66> tSDQK

<67> tIPIPL

<68> tSRX

TC output delay time (vs. CLKOUT↑)

TC OFF delay time (vs. CLKOUT↑)

TC low-level width

tCYK–15

tCYK–10

TC pull-up delay time (vs. CLKOUT↑)

END setup time (vs. CLKOUT↑)

END low-level width

Note 3

Note 4

Note 4 ns

DMARQ setup time (vs. CLKOUT↑)

INTPn low-level width

RXD setup time (vs. SCU internal clock↓)

500

Notes 1. MWR and IOWR signals in DMA cycle

2. MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals.

3. tKKH + 2tCYK – 10 (Reference value when a 1.1-kΩ pull-up resistor is connected.)

4. tKKH + 2tCYK – 5 (Reference value when a 1.1-kΩ pull-up resistor is connected.)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 5 V ±10%) (3/3)

µPD70208H-10

Output Pin Load Capacitance: C^L= 100 pF

µPD70208H-12

µPD70216H-12

µPD70208H-16

µPD70216H-16

Parameter

Symbol

Unit

µPD70216H-10

MIN.

500

MAX.

MIN.

500

MAX.

MIN.

500

MAX.

RXD hold time (vs. SCU internal clock↓)

CLKOUT↓ → SRDY delay time

TOUT1↓ → TXD delay time

TCTL2 setup time (vs. CLKOUT↓)

TCTL2 setup time (vs. TCLK↑)

TCTL2 hold time (vs. CLKOUT↓)

TCTL2 hold time (vs. TCLK↑)

TCTL2 high-level width

tHRX

<69>

<70>

<71>

<72>

<73>

<74>

<75>

<76>

<77>

<78>

<79>

<80>

<81>

<82>

<83>

<84>

<85>

<86>

<87>

<88>

tDKSR

tDTX

100

200

100

200

100

200

tSGK

tSGTK

tHKG

tHTKG

tGGH

tGGL

TCTL2 low-level width

TOUT output delay time (vs. CLKOUT↓)

TOUT output delay time (vs. TCLK↓)

TOUT output delay time (vs. TCTL2↓)

TCLK rise time

tDKTO

tDTKTO

tDGTO

tTKR

150

100

150

100

150

100

TCLK fall time

tTKF

TCLK high-level width

TKTKH

TCLK low-level width

tTKTKL

tCYTK

tAI

TCLK cycle

100

62.5

Note 1

Access interval

2tCYK–40

tKKL–30

4tCYK

2tCYK–25

tKKL–15

4tCYK

2tCYK–20

tKKL–10

4tCYK

Note 2

REFRQ↑ delay time (vs. MRD↑)

DRQHRH

Note 3

RESET pulse width

tWRESL

Notes 1. Specification to guarantee read/write recovery time for I/O device.

2. Specification to guarantee that REFRQ↑ is always later than MRD↑.

Only guaranteed when the EREF bit of the SCTL register is 0.

3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation

stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending

on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the

resonator and oscillator actually used.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (1/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

tCYX

tXXH

External clock input cycle

<1>

<2>

External clock input high-level width (VKH=3.0 V)

External clock input low-level width (VKL=1.5 V)

External clock input rise time (1.5→3.0 V)

External clock input fall time (3.0→1.5 V)

Clock output cycle

tXXL

<3>

tXR

<4>

tXF

<5>

tCYK

tKKH

<6>

0.5tCYK–5

Clock output high-level width (VOH=3.0 V)

Clock output low-level width (VOL=1.5 V)

Clock output rise time (1.5→3.0 V)

<7>

tKKL

<8>

tKR

<9>

tKF

Clock output fall time (3.0→1.5 V)

<10>

<11>

<12>

<13>

<14>

<15>

<16>

<17>

<18>

<19>

<20>

<21>

<22>

<23>

<24>

<25>

<26>

<27>

<28>

<29>

<30>

<31>

<32>

<33>

<34>

<35>

tDXK

tIR

CLKOUT delay time (vs. external clock)

Input rise time (except external clock) (0.8→2.2 V)

Input fall time (except external clock) (2.2→0.8 V)

Output rise time (except CLKOUT) (0.8→2.2 V)

Output fall time (except CLKOUT) (2.2→0.8 V)

tIF

tOR

tOF

Note 1

tSRESK

tHKRES

tDKRES

tSRYLK

tHKRYL

tSRYHK

tHKRYH

tSNMIK

tSPOLK

tSDK

RESET setup time (vs. CLKOUT↓)

Note 1

RESET hold time (vs. CLKOUT↓)

RESOUT output delay time (vs. CLKOUT↓)

READY inactive setup time (vs. CLKOUT↑)

READY inactive hold time (vs. CLKOUT↑)

READY active setup time (vs. CLKOUT↑)

READY active hold time (vs. CLKOUT↑)

NMI setup time (vs. CLKOUT↑)

POLL setup time (vs. CLKOUT↑)

Data setup time (vs. CLKOUT↓)

tHKD

tDKA

Data hold time (vs. CLKOUT↓)

Note 2

CLKOUT → address delay time

tHKA

CLKOUT → address hold time

CLKOUT ↓ → PS delay time

CLKOUT ↓ → PS float delay time

Address setup time (vs. ASTB↓)

tDKP

tFKP

tSAST

tFKA

tKKL–10

tHKA

Note 3

CLKOUT ↓ → address float delay time

tDKSTH

tDKSTL

tSTST

CLKOUT ↓ → ASTB ↑ delay time

CLKOUT ↑ → ASTB ↓ delay time

ASTB high-level width

tKKL–10

Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.

2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,

BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,

IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (2/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

<36>

ASTB ↓ → address hold time

tHSTA

tDKCT1

tDKCT2

tDAFRL

tDKRL

tDKRH

tDRHA

tRR

tKKH–10

Note 1

<37>

<38>

<39>

<40>

<41>

<42>

<43>

<44>

<45>

<46>

<47>

<48>

<49>

<50>

<51>

<52>

<53>

<54>

<55>

<56>

<57>

<58>

<59>

<60>

<61>

<62>

<63>

<64>

<65>

<66>

<67>

<68>

<69>

<70>

CLKOUT → control 1

CLKOUT → control 2

delay time

Note 2

Address float → RD ↓ delay time

CLKOUT ↓ → RD ↓ delay time

CLKOUT ↓ → RD ↑ delay time

RD ↑ → address delay time

tCYK–5

RD low-level width

2tCYK–15

BUFEN ↑ → BUFR/W delay time (read cycle)

CLKOUT ↓ → data output delay time

CLKOUT ↓ → data float delay time

WR low-level width

tDBECT

tDKD

tKKL–10

tFKD

tWW

2tCYK–15

WR ↑ → BUFEN ↑ or BUFR/W ↓ (write cycle)

CLKOUT ↑ → BS ↓ delay time

CLKOUT ↓ → BS ↑ delay time

HLDRQ setup time (vs. CLKOUT ↓)

CLKOUT ↓ → HLDAK delay time

CLKOUT ↑ → DMAAK delay time

CLKOUT ↓ → DMAAK delay time (cascade mode)

WR low-level width (DMA cycle)

tDWCT

tDKBL

tDKBH

tSHQK

tDKHA

tDKHDA

tDKLDA

tWW1

tKKL–10

DMA extended write

DMA normal write

2tCYK–15

tCYK–15

tKKH–10

tKKL–10

tWW2

RD ↓, WR ↓ delay time (vs. DMAAK ↓)

DMAAK ↑ delay time (vs. RD ↑)

RD ↑ delay time (vs. WR ↑)

tDDARW

DRHDAH

tDWHRH

tDKTCL

tDKTCF

tTCTCL

tDKTCH

tSEDK

tEDEDL

tSDQK

tIPIPL

TC output delay time (vs. CLKOUT ↑)

TC OFF delay time (vs. CLKOUT ↑)

TC low-level width

tCYK–10

TC pull-up delay time (vs. CLKOUT ↑)

END setup time (vs. CLKOUT ↑)

END low-level width

Note 3 ns

DMARQ setup time (vs. CLKOUT ↑)

INTPn low-level width

RxD setup time (vs. SCU internal clock ↓)

RxD hold time (vs. SCU internal clock ↓)

CLKOUT ↓ → SRDY delay time

tSRX

500

tHRX

tDKSR

100

Notes 1. MWR and IOWR signals in DMA cycle

2. MWR and IOWR signals in BUFEN, BUFR/W, INTAK, REFRQ, and CPU cycles

3. tKKH + 2tCYK – 5 (reference value when a 1.1-kΩ pull-up resistor is connected)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (3/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

200

TOUT1 ↓ → TxD delay time

TCTL2 setup time (vs. CLKOUT ↓)

TCTL2 setup time (vs. TCLK ↑)

TCTL2 hold time (vs. CLKOUT ↓)

TCTL2 hold time (vs. TCLK ↑)

TCTL2 high-level width

tDTX

<71>

<72>

<73>

<74>

<75>

<76>

<77>

<78>

<79>

<80>

<81>

<82>

<83>

<84>

<85>

<86>

<87>

<88>

tSGK

tSGTK

tHKG

tHTKG

tGGH

tGGL

TCTL2 low-level width

TOUT output delay time (vs. CLKOUT ↓)

TOUT output delay time (vs. TCLK ↓)

TOUT output delay time (vs. TCTL2 ↓)

TCLK rise time

tDKTO

tDTKTO

tDGTO

tTKR

150

100

TCLK fall time

tTKF

TCLK high-level width

TKTKH

TCLK low-level width

tTKTKL

tCYTK

tAI

TCLK cycle

Note 1

Access interval

2tCYK–15

tKKL–10

4tCYK

Note 2

REFRQ ↑ delay time (vs. MRD ↑)

DRQHRH

Note 3

RESET pulse width

tWRESL

Notes 1. This rating is to guarantee the read/write recovery time for the I/O device.

2. This rating is to guarantee that REFRQ ↑ is always behind MRD ↑, and guaranteed only when the EREF

bit of the STCL register is 0.

3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation

stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending

on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the

resonator and oscillator actually used.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

RECOMMENDED OSCILLATOR

The clock input circuits (1) and (2) shown below are recommended.

(1) Ceramic resonator connection (T^A= –40 to +85 °C, VDD = 5 V ±10% (µPD70208H, 70216H-10/12/16), VDD = 5 V ±5%

(µPD70208H, 70216H-20))

Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.

2. No other signal lines should pass through the area enclosed in dashed line.

3. For matching between V40HL, V50HL and resonator, the efficient evaluation should be carried

out.

4. The values of the oscillator constants C1 and C2 depend on the characteristics of the

resonator used. Evaluate them with the resonator actually used.

Recommended

Frequency

Constant

Product Name

Manufacturer

(fXX) [MHz]

C1 [pF]

C2 [pF]

CSA40.00MXZ040

CSA32.00MXZ040

CSA25.00MXZ040

CSA20.00MXZ040

FCR32.0M2G

Murata Mfg.

Co., Ltd.

TDK Corp.

FCR25.0M2G

FCR20.0M2G

(2) External clock input

Open

High-speed

CMOS

Inverter

High-speed

CMOS

Inverter

External Clock

Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

16.2 AT 3 V OPERATION

OPERATING RANGE

E, P, X, M Masks

VDD = 3 V ±10%

Others

µPD70208H, 70216H-10/12/16

µPD70208H, 70216H-20

—

VDD = 3 V ±10%

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Supply voltage

Symbol

Test Conditions

Rating

Unit

V^DD

–0.5 to +7.0

Input voltage

–0.5 to VDD + 0.3

–0.5 to VDD + 1.0

–0.5 to V^DD+ 0.3

–40 to +85

Clock input voltage

Output voltage

VDD = 3 V ±10%

Operating ambient temperature

Storage temperature

°C

Tstg

–65 to +150

Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect

the output pins to V^DDor VCC and GND. However, open-drain pins or open-collector pins may be

connected directly. Moreover, an external circuit whose timing is designed to avoid output

collision can be connected to pins that go into a high-impedance state.

2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the

quality of the program may be degraded. Absolute maximum ratings, therefore, are the values

exceeding which the product may be physically damaged. Use the program keeping all the

parameters within these rated values.

The standards and conditions shown in DC and AC Characteristics below specify the range within

which the normal operation of the product is guaranteed.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3 V ±10%)

Parameter

Input voltage high

Symbol

Test Conditions

Except RESET

MIN.

0.7 VDD

0.8 VDD

–0.5

TYP.

MAX.

Unit

VIH

VDD+0.3

0.2 VDD

RESET

Input voltage low

VIL

Except RESET

RESET

Clock input voltage high

Clock input voltage low

Output voltage high

VKH

VKL

VOH

0.8 VDD

–0.5

VDD+0.5

0.2 VDD

IOH = –2.5 mA

0.7 VDD

VDD – 0.4

IOH = –100 µA

Output voltage low

VOL

Except END/TC : IOL = 2.5 mA

0.4

END/TC

VI = VDD

VI = 0 V

VO = VDD

VO = 0 V

VI = 3.0 V

VI = 0.8 V

: IOL = 5.0 mA

Input leak current high

Input leak current low

ILIH

ILIL

–10

µA

: Except INTP

: INTP input

INTP input current low

Output leak current high

Output leak current low

Latch leak current high

Latch leak current low

ILIPL

ILOH

ILOL

ILLH

ILLL

IILH

IILL

–300

–10

–50

–300

300

Latch inversion current (L → H)

Latch inversion current (H → L)

400

–400

5.5 fX

1.5 fX

Note

Supply current

IDD

E, P, X, M

masks

On Operation

3.0 fX

0.9 fX

On standby (HALT)

On standby (STOP)

On Operation

µA

Others

2.5 fX

0.9 fX

4.0 fX

1.5 fX

On standby (HALT)

On standby (STOP)

µA

Note The unit of constant values (0.9, 1.5, 2.5, 3.0, 4.0 and 5.5) is mA/MHz.

CAPACITANCE (TA = 25˚C, VDD = 0 V)

Parameter

Input capacitance

Input/output capacitance

Symbol

Test Conditions

fC = 1 MHz

MIN.

TYP.

MAX.

Unit

CIO

0 V other than test pin.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

AC CHARACTERISTICS

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 3 V ±10%) (1/3)

µPD70208H-10

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-12

µPD70216H-12

µPD70208H-16

µPD70216H-16

Parameter

Symbol

µPD70216H-10

Unit

MIN.

100

MAX.

MIN.

MAX.

MIN.

62.5

MAX.

<1> tCYX

<2> tXXH

<3> tXXL

<4> tXR

External clock input cycle

External clock input high-level width (VKH=0.8 VDD)

External clock input low-level width (VKL=0.2 VDD)

External clock input rise time (0.2 VDD→0.8 VDD)

External clock input fall time (0.8 VDD→0.2 VDD)

Clock output cycle

<5> tXF

<6> tCYK

<7> tKKH

<8> tKKL

<9> tKR

200

166

125

0.5tCYK–7

Clock output high-level width (VOH=0.7 VDD)

Clock output low-level width (VOL=0.2 VDD)

Clock output rise time (0.2 VDD→0.7 VDD)

<10> tKF

Clock output fall time (0.7 VDD→0.2 VDD)

<11> tDXK

<12> tIR

CLKOUT delay time (vs. external clock)

Input rise time (except external clock) (0.2 VDD→0.7 VDD)

Input fall time (except external clock) (0.7 VDD→0.2 VDD)

Output rise time (except CLKOUT) (0.2 VDD→0.7 VDD)

Output fall time (except CLKOUT) (0.7 VDD→0.2 VDD)

<13> tIF

<14> tOR

<15> tOF

Note 1

<16> tSRESK

<17> tHKRES

<18> tDKRES

<19> tSRYLK

<20> tHKRYL

<21> tSRYHK

<22> tHKRYH

<23> tSNMIK

<24> tSPOLK

<25> tSDK

<26> tHKD

<27> tDKA

<28> tHKA

<29> tDKP

<30> tFKP

<31> tSAST

<32> tFKA

<33> tDKSTH

<34> tDKSTL

<35> tSTST

RESET setup time (vs. CLKOUT↓)

Note 1

RESET hold time (vs. CLKOUT↓)

RESOUT output delay time (vs. CLKOUT↓)

READY inactive setup time (vs. CLKOUT↑)

READY inactive hold time (vs. CLKOUT↑)

READY active setup time (vs. CLKOUT↑)

READY active hold time (vs. CLKOUT↑)

NMI setup time (vs. CLKOUT↑)

POLL setup time (vs. CLKOUT↑)

Data setup time (vs. CLKOUT↓)

Data hold time (vs. CLKOUT↓)

Note 2

CLKOUT → address delay time

CLKOUT → address hold time

CLKOUT↓ → PS delay time

CLKOUT↓ → PS float delay time

Address setup time (vs. ASTB↓)

tKKL–30

Note 3

CLKOUT↓ → address float delay time

CLKOUT↓ → ASTB↑ delay time

CLKOUT↑ → ASTB↓ delay time

ASTB high-level width

tKKL–10

Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.

2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,

BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,

IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 3 V ±10%) (2/3)

µPD70208H-10

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-12

µPD70216H-12

µPD70208H-16

µPD70216H-16

Parameter

Symbol

µPD70216H-10

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

ASTB↓ → address hold time

<36> tHSTA

<37> tDKCT1

<38> tDKCT2

<39> tDAFRL

<40> tDKRL

<41> tDKRH

<42> tDRHA

<43> tRR

tKKH–30

tKKH–20

Note 1

CLKOUT → control 1

CLKOUT → control 2

delay time

Note 2

Address float → RD↓ delay time

CLKOUT↓ → RD↓ delay time

CLKOUT↓ → RD↑ delay time

RD↑ → address delay time

tCYK–70

tCYK–60

tCYK–50

RD low-level width

2tCYK–70

2tCYK–60

2tCYK–50

BUFEN↑ → BUFR/W delay time (read cycle)

CLKOUT↓ → data output delay time

CLKOUT↓ → data float delay time

WR low-level width

<44> tDBECT

<45> tDKD

tKKL–30

tKKL–20

<46> tFKD

<47> tWW

2tCYK–50

2tCYK–40

WR↑ → BUFEN↑ or BUFR/W↓ (write cycle)

CLKOUT↑ → BS↓ delay time

<48> tDWCT

<49> tDKBL

<50> tDKBH

<51> tSHQK

<52> tDKHA

<53> tDKHDA

<54> tDKLDA

<55> tWW1

<56> tWW2

<57> tDDARW

tKKL–30

tKKL–20

CLKOUT↓ → BS↑ delay time

HLDRQ setup time (vs. CLKOUT↓)

CLKOUT↓ → HLDAK delay time

CLKOUT↑ → DMAAK delay time

CLKOUT↓ → DMAAK delay time (cascade mode)

110

100

WR low-level width

(DMA cycle)

DMA extended write

DMA normal write

2tCYK–50

tCYK–50

tKKH–40

tKKL–40

2tCYK–50

tCYK–50

tKKH–40

tKKL–40

2tCYK–40

tCYK–40

tKKH–30

tKKL–30

RD↓ WR↓ delay time (vs. DMAAK↓)

DMAAK↑ delay time (vs. RD↑)

RD↑ delay time (vs. WR↑)

<58>

DRHDAH

<59> tDWHRH

<60> tDKTCL

<61> tDKTCF

<62> tTCTCL

<63> tDKTCH

<64> tSEDK

<65> tEDEDL

<66> tSDQK

<67> tIPIPL

<68> tSRX

TC output delay time (vs. CLKOUT↑)

TC OFF delay time (vs. CLKOUT↑)

TC low-level width

tCYK–25

tCYK–15

TC pull-up delay time (vs. CLKOUT↑)

END setup time (vs. CLKOUT↑)

END low-level width

Note 3

Note 4

Note 4 ns

140

120

100

DMARQ setup time (vs. CLKOUT↑)

INTPn low-level width

100

1000

100

1000

100

1000

RXD setup time (vs. SCU internal clock↓)

RXD hold time (vs. SCU internal clock↓)

CLKOUT↓ → SRDY delay time

<69> tHRX

<70> tDKSR

150

Notes 1. MWR and IOWR signals in DMA cycle

2. MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals.

3. tKKH + 2tCYK – 20 (Reference value when a 1.1-kΩ pull-up resistor is connected)

4. tKKH + 2tCYK – 10 (Reference value when a 1.1-kΩ pull-up resistor is connected)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(1) µPD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, VDD = 3 V ±10%) (3/3)

µPD70208H-10

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-12

µPD70216H-12

µPD70208H-16

Parameter

Symbol

µPD70216H-10

µPD70216H-16 Unit

MIN.

MAX.

500

MIN.

MAX.

500

MIN.

MAX.

500

TOUT1↓→ TXD delay time

<71>

tDTX

TCTL2 setup time (vs. CLKOUT↓)

TCTL2 setup time (vs. TCLK↑)

TCTL2 hold time (vs. CLKOUT↓)

TCTL2 hold time (vs. TCLK↑)

TCTL2 high-level width

<72>

<73>

<74>

<75>

<76>

<77>

<78>

<79>

<80>

<81>

<82>

<83>

<84>

<85>

<86>

<87>

<88>

tSGK

tSGTK

tHKG

tHTKG

tGGH

tGGL

100

TCTL2 low-level width

TOUT output delay time (vs. CLKOUT↓)

TOUT output delay time (vs. TCLK↓)

TOUT output delay time (vs. TCTL2↓)

TCLK rise time

tDKTO

tDTKTO

tDGTO

tTKR

200

150

120

200

150

120

200

150

120

TCLK fall time

tTKF

TCLK high-level width

TKTKH

TCLK low-level width

tTKTKL

tCYTK

tAI

TCLK cycle

200

166

125

Note 1

Access interval

2tCYK–70

tKKL–50

4tCYK

2tCYK–60

tKKL–40

4tCYK

2tCYK–50

tKKL–30

4tCYK

Note 2

REFRQ↑ delay time (vs. MRD↑)

DRQHRH

Note 3

RESET pulse width

tWRESL

Notes 1. Specification to guarantee read/write recovery time for I/O device.

2. Specification to guarantee that REFRQ↑ is always later than MRD↑ .

Only guaranteed when the EREF bit of the SCTL register is 0.

3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation

stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending

on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the

resonator and oscillator actually used.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (1/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

External clock input cycle

tCYX

tXXH

<1>

<2>

External clock input high-level width (VKH=0.8 VDD)

External clock input low-level width (VKL=0.2 VDD)

External clock input rise time (0.2 VDD→0.8 VDD)

External clock input fall time (0.8 VDD→0.2 VDD)

Clock output cycle

tXXL

<3>

tXR

<4>

tXF

<5>

tCYK

tKKH

100

<6>

Clock output high-level width (VOH=0.7 VDD)

Clock output low-level width (VOL=0.2 VDD)

Clock output rise time (0.2 VDD→0.7 VDD)

Clock output fall time (0.7 VDD→0.2 VDD)

0.5tCYK–7

<7>

tKKL

<8>

tKR

<9>

tKF

<10>

<11>

<12>

<13>

<14>

<15>

<16>

<17>

<18>

<19>

<20>

<21>

<22>

<23>

<24>

<25>

<26>

<27>

<28>

<29>

<30>

<31>

<32>

<33>

<34>

<35>

CLKOUT delay time (vs. external clock)

tDXK

tIR

Input rise time (except external clock) (0.2 VDD→0.7 VDD)

Input fall time (except external clock) (0.7 VDD→0.2 VDD)

Output rise time (except CLKOUT) (0.2 VDD→0.7 VDD)

Output fall time (except CLKOUT) (0.7 VDD→0.2 VDD)

tIF

tOR

tOF

Note 1

RESET setup time (vs. CLKOUT↓)

tSRESK

tHKRES

tDKRES

tSRYLK

tHKRYL

tSRYHK

tHKRYH

tSNMIK

tSPOLK

tSDK

Note 1

RESET hold time (vs. CLKOUT↓)

RESOUT output delay time (vs. CLKOUT↓)

READY inactive setup time (vs. CLKOUT↑)

READY inactive hold time (vs. CLKOUT↑)

READY active setup time (vs. CLKOUT↑)

READY active hold time (vs. CLKOUT↑)

NMI setup time (vs. CLKOUT↑)

POLL setup time (vs. CLKOUT↑)

Data setup time (vs. CLKOUT↓)

Data hold time (vs. CLKOUT↓)

tHKD

tDKA

Note 2

CLKOUT → address delay time

CLKOUT → address hold time

CLKOUT ↓ → PS delay time

CLKOUT ↓ → PS float delay time

Address setup time (vs. ASTB↓)

tHKA

tDKP

tFKP

tSAST

tFKA

tKKL–20

tHKA

Note 3

CLKOUT ↓ → address float delay time

CLKOUT ↓ → ASTB ↑ delay time

CLKOUT ↑ → ASTB ↓ delay time

ASTB high-level width

tDKSTH

tDKSTL

tSTST

tKKL–10

Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.

2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,

BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,

IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (2/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

ASTB ↓ → address hold time

tHSTA

tDKCT1

tDKCT2

tDAFRL

tDKRL

tDKRH

tDRHA

tRR

tKKH–20

<36>

<37>

<38>

<39>

<40>

<41>

<42>

<43>

<44>

<45>

<46>

<47>

<48>

<49>

<50>

<51>

<52>

<53>

<54>

<55>

<56>

<57>

<58>

<59>

<60>

<61>

<62>

<63>

<64>

<65>

<66>

<67>

<68>

<69>

<70>

Note 1

CLKOUT → control 1

CLKOUT → control 2

delay time

Note 2

Address float → RD ↓ delay time

CLKOUT ↓ → RD ↓ delay time

CLKOUT ↓ → RD ↑ delay time

RD ↑ → address delay time

tCYK–40

RD low-level width

2tCYK–40

BUFEN ↑ → BUFR/W delay time (read cycle)

CLKOUT ↓ → data output delay time

CLKOUT ↓ → data float delay time

WR low-level width

tDBECT

tDKD

tKKL–20

tFKD

tWW

2tCYK–40

WR ↑ → BUFEN ↑ or BUFR/W ↓ (write cycle)

CLKOUT ↑ → BS ↓ delay time

CLKOUT ↓ → BS ↑ delay time

HLDRQ setup time (vs. CLKOUT ↓)

CLKOUT ↓ → HLDAK delay time

CLKOUT ↑ → DMAAK delay time

CLKOUT ↓ → DMAAK delay time (cascade mode)

WR low-level width (DMA cycle)

tDWCT

tDKBL

tDKBH

tSHQK

tDKHA

tDKHDA

tDKLDA

tWW1

tKKL–20

DMA extended write

DMA normal write

2tCYK–40

tCYK–40

tKKH–30

tKKL–30

tWW2

RD ↓, WR ↓ delay time (vs. DMAAK ↓)

DMAAK ↑ delay time (vs. RD ↑)

RD ↑ delay time (vs. WR ↑)

tDDARW

DRHDAH

tDWHRH

tDKTCL

tDKTCF

tTCTCL

tDKTCH

tSEDK

tEDEDL

tSDQK

tIPIPL

TC output delay time (vs. CLKOUT ↑)

TC OFF delay time (vs. CLKOUT ↑)

TC low-level width

tCYK–15

TC pull-up delay time (vs. CLKOUT ↑)

END setup time (vs. CLKOUT ↑)

END low-level width

Note 3 ns

DMARQ setup time (vs. CLKOUT ↑)

INTPn low-level width

RxD setup time (vs. SCU internal clock ↓)

RxD hold time (vs. SCU internal clock ↓)

CLKOUT ↓ → SRDY delay time

tSRX

500

tHRX

tDKSR

100

Notes 1. MWR and IOWR signals in DMA cycle

2. MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals.

3. tKKH + 2tCYK – 10 (reference value when a 1.1-kΩ pull-up resistor is connected)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

(2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (3/3)

Output Pin Load Capacitance: CL = 100 pF

µPD70208H-20

Parameter

Symbol

µPD70216H-20

Unit

MIN.

MAX.

200

<71> tDTX

<72> tSGK

<73> tSGTK

<74> tHKG

<75> tHTKG

<76> tGGH

<77> tGGL

<78> tDKTO

<79> tDTKTO

<80> tDGTO

<81> t^TKR

<82> tTKF

TOUT1 ↓ → TxD delay time

TCTL2 setup time (vs. CLKOUT ↓)

TCTL2 setup time (vs. TCLK ↑)

TCTL2 hold time (vs. CLKOUT ↓)

TCTL2 hold time (vs. TCLK ↑)

TCTL2 high-level width

TCTL2 low-level width

150

100

TOUT output delay time (vs. CLKOUT ↓)

TOUT output delay time (vs. TCLK ↓)

TOUT output delay time (vs. TCTL2 ↓)

TCLK rise time

TCLK fall time

<83>

TKTKH

TCLK high-level width

<84> tTKTKL

<85> tCYTK

<86> tAI

TCLK low-level width

100

TCLK cycle

Note 1

2tCYK–40

tKKL–30

4tCYK

Access interval

Note 2

<87>

DRQHRH

REFRQ ↑ delay time (vs. MRD ↑)

Note 3

<88> tWRESL

RESET pulse width

Notes 1. This rating is to guarantee the read/write recovery time for the I/O device.

2. This rating is to guarantee that REFRQ ↑ is always behind MRD ↑, and is guaranteed only when the EREF

bit of the STCL register is 0.

3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation

stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending

on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the

resonator and oscillator actually used.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

RECOMMENDED OSCILLATOR

The clock input circuits (1) and (2) shown below are recommended.

(1) Ceramic resonator connection (T^A= –40 to +85 °C, VDD = 3 V ±10%^Note

)

Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.

2. No other signal lines should pass through the area enclosed in dashed line.

3. V40HL, V50HL and resonator matching requires careful evaluation.

4. The values of the oscillator constants C1 and C2 depend on the characteristics of the

resonator used. Evaluate them with the resonator actually used.

Recommended

Frequency

Constant

Product Name

Manufacturer

(fXX) [MHz]

C1 [pF]

C2 [pF]

Note

–

CSA20.00MXZ040

Murata Mfg.

Co., Ltd.

CSA16.00MXZ040

CSA16.00MXW0C3

CSA12.5MTZ

CSA12.5MTW

CSA10.0MTZ

CST10.0MXW

FCR20.0M2G

FCR16.0M2G

FCR10.0MC

–

12.5

–

TDK Corp.

Note Use the CAS20.00MXZ040 within the range of VDD = 2.9 to 3.3 V.

(2) External clock input

Open

High-speed

CMOS

Inverter

High-speed

CMOS

Inverter

External Clock

Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

AC Test Input Waveform (Except X1 and X2) (at 5 V operation)

2.4 V

2.2 V

Test

2.2 V

0.8 V

points

0.8 V

0.4 V

AC Test Output Test Points (at 5 V operation)

2.2 V

0.8 V

2.2 V

0.8 V

Test

points

AC Test Input Waveform (Except X1 and X2) (at 3 V operation)

0.8 VDD

0.7 V^DD

Test

0.7 V^DD

0.2 VDD

points

0.2 VDD

0.4 V

AC Test Output Waveform (at 3 V operation)

0.7 VDD

0.2 VDD

0.7 VDD

0.2 VDD

Test

points

Load Conditions

DUT

= 100pF

Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, the load capacitance

of this device should be reduced to 100 pF or less by insertion of a buffer, etc.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Clock Timing

<1>

<2>

<4>

<5>

External Clock (Input)

(X1)

<11>

<3>

<11>

<6>

<9>

<10>

<7>

CLKOUT (Output)

<8>

Reset Timing

CLKOUT (Output)

RESET (Input)

<16>

<17>

<16>

<88>

Note

<18>

RESOUT (Output)

Ready Timing (1)

CLKOUT (Output)

<22>

<21>

READY (Input)

Variation Range

Ready Timing (2)

CLKOUT (Output)

READY (Input)

<22>

<19>

<21>

Variation Range

Note

Variation Range

<20>

Note Variation range

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Read Timing

CLKOUT (Output)

<27>

<28>

<30>

A16/PS0-

A19/PS3

(Output)

A16-A19

PS0-PS3

<29>

<27>

<31>

A8-A15 (Output): V40HL

UBE (Output): V50HL

<25>

<31>

<28>

<32>

AD0-AD7 (I/O): V40HL

AD0-AD15 (I/O): V50HL

A0-A7(Output)

A0-A15(Output): V50HL

V40HL

D0-D7(Intput) : V40HL

D0-D15(Intput): V50HL

<33>

<36>

<35>

<26>

ASTB (Output)

BUFEN (Output)

BUFR/W (Output)

<34>

<38>

<44>

Note

<38>

<39>

<40>

<41>

MRD (Output)

IORD (Output)

Note

<43>

<42>

BS0-BS2 (Output)

Bus Status

<49>

<50>

Note High-level signal is output in case of internal access.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Write Timing

CLKOUT (Output)

<27>

<28>

<30>

A16/PS0-

A19/PS3

(Output)

A16-A19

PS0-PS3

<27>

<29>

<45>

<31>

A8-A15 (Output): V40HL

UBE (Output): V50HL

<46>

AD0-AD7 (I/O): V40HL

AD0-AD15 (I/O): V50HL

A0-A7 (Output) : V40HL

A0-A15 (Output): V50HL

D0-D7 (Output) : V40HL

D0-D15 (Output): V50HL

<28>

<31>

<35>

ASTB (Output)

<34>

<38>

<33>

<36>

<38>

BUFEN (Output)

BUFR/W (Output)

Note

<48>

<38>

MWR (Output)

IOWR (Output)

Note

<47>

BS0-BS2 (Output)

Bus Status

<49>

<50>

Note High-level signal is output in case of internal access.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Status Timing

CLKOUT (Output)

<28>

<30>

<27>

<29>

A16/PS0-

A19/PS3

(Output)

A16-A19

PS0-PS3

<27>

<31>

A8-A15 (Output): V40HL

UBE (Output): V50HL

<25>

<27>

<33>

<28>

<32>

<26>

<31>

AD0-AD7 (I/O): V40HL

AD0-AD15 (I/O): V50HL

A0-A7 (Output) : V40HL

A0-A15 (Output): V50HL

D0-D7 (Input) : V40HL

D0-D15 (Input): V50HL

<36>

<42>

<35>

ASTB (Output)

BS0-BS2 (Output)

Note 1

<34>

<50>

Bus Status

<39>

<49>

<27>

<41>

Note 2

<40>

<43>

QS0, QS1 (Output)

Notes 1. MRD, IORD, MWR, IOWR (all output)

2. High-level signal is output in case of internal access.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Interrupt Acknowledge Timing (V40HL)

CLKOUT (Output)

A8-A15 (Output)

Note 1

<26>

<25>

<27>

<32>

Note 2

Note 1

AD0-AD7 (I/O)

Vector Number

ASTB (Output)

<38>

INTAK (Output)

<38>

Note 3

BUFEN (Output)

BUFR/W (Output)

<27>

BUSLOCK (Output)

Notes 1. Slave address in case of interrupt from external µPD71059.

Invalid data in case of interrupt from internal ICU.

2. Data read as vector address in case of interrupt from external µPD71059.

High impedance in case of interrupt from internal ICU.

3. Low-level output in case of interrupt from external µPD71059.

High-level output in case of interrupt from internal ICU.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Interrupt Acknowledge Timing (V50HL)

TI×3

CLKOUT (Output)

AD0-AD15 (I/O)

<27>

<25>

<26>

<32>

Note 2

Note 1

Vector Number

ASTB (Output)

INTAK (Output)

BUFEN (Output)

BUFR/W (Output)

<38>

Note 3

<27>

BUSLOCK (Output)

Notes 1. Slave address in case of interrupt from external µPD71059.

Invalid data in case of interrupt from internal ICU.

2. Data read as vector address in case of interrupt from external µPD71059.

High impedance in case of interrupt from internal ICU.

3. Low-level output in case of interrupt from external µPD71059.

High-level output in case of interrupt from internal ICU.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

HLDRQ/HLDAK Timing (1)

CLKOUT (Output)

<51>

HLDRQ (Input)

<52>

<32>

HLDAK (Output)

<27>

Note

<27>

<32>

BS0-BS2 (Output)

Note A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL

A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL

Remark A dashed line indicates high impedance.

HLDRQ/HLDAK Timing (2)

CLKOUT (Output)

HLDRQ (Input)

<51>

Variation Range

<52>

<6> or longer

HLDAK (Output)

<27>

Highest-Priority Refresh

Cycle or DMA Cycle

Note

<49>

BS0-BS2 (Output)

Highest-Priority Refresh

Cycle or DMA Cycle

Note A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL

A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

POLL, NMI Input Timing

CLKOUT (Output)

<24>

<23>

POLL (Input)

NMI (Input)

BUSLOCK Output Timing

CLKOUT (Output)

<27>

BUSLOCK (Output)

Access Interval

<86>

MRD (Output)

IORD (Output)

<86>

MWR (Output)

IOWR (Output)

<86>

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Refresh Timing (V40HL)

CLKOUT (Output)

<28>

<29>

<27>

A16/PS0-

A19/PS3

(Output)

Invalid

<27>

Refresh Address

A8-A15 (Output)

AD0-AD7 (I/O)

<28>

<32>

<27>

<33>

<31>

Refresh Address

<36>

<35>

ASTB (Output)

BUFEN (Output)

MRD (Output)

<34>

<41>

<39>

<40>

<43>

<38>

REFRQ (Output)

BS0-BS2 (Output)

<49>

<50>

BS2 = 1, BS1 = 0, BS0 = 1

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

Refresh Timing (V50HL)

CLKOUT (Output)

<28>

<29>

<27>

A16/PS0-

A19/PS3

(Output)

Invalid

<27>

<33>

UBE (Output)

<28>

<32>

<31>

AD0-AD15 (I/O)

Refresh Address

<36>

<35>

ASTB (Output)

BUFEN (Output)

MRD (Output)

<34>

<39>

<41>

<40>

<43>

<50>

<38>

REFRQ (Output)

<49>

BS0-BS2 (Output)

BS2 = 1, BS1 = 0, BS0 = 1

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

TCU Timing (1)

CLKOUT (Output)

<72>

<74>

<77>

<76>

<74>

TCTL2 (Input)

<80>

Note

<78>

TOUTn (Output)

(n=1, 2)

Note Applies to TOUT2 output.

TCU Timing (2)

<82>

<81>

<83>

<85>

TCLK (Input)

<84>

<75>

<73>

<76>

<75>

<73>

TCTL2 (Input)

<77>

<80>

Note

<79>

TOUTn (Output)

(n=1, 2)

Note Applies to TOUT2 output.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

SCU Timing

RxD (Input)

<68>

<69>

TOUT1 (Output)

16 Cycles or 64 Cycles

TxD (Output)

<71>

CLKOUT (Output)

SRDY (Output)

<70>

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DMAU Timing (1)

CLKOUT (Output)

<49>

<50>

BS0-BS2 (Output)

ASTB (Output)

Bus Status

<36>

<33>

<35>

<34>

<29>

<27>

<28>

A16/PS0-

A19/PS3

(Output)

A8-A15 (Output): V40HL

UBE (Output): V50HL

<28>

<32>

AD0-AD7 (I/O): V40HL

AD0-AD15 (I/O): V50HL

<53>

DMAAK (Output)

<39>

<58>

<59>

<41>

<40>

<43>

<57>

MRD (Output)

IORD (Output)

<37>

<57>

<37>

<55>

<56>

MWR (Output)

IOWR (Output)

Note

Note Low-level signal is output in extended write mode.

Remark A dashed line indicates high impedance.

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DMAU Timing (2)

CLKOUT (Output)

<61>

<63>

<60>

TC (Input/Output)

END (Input/Output)

<64>

<62>

<65>

CLKOUT (Output)

<66>

DMARQn (Input)

(n=0-3)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

DMAU Timing (3) (Cascade Mode)

In Normal Operation:

CLKOUT (Output)

<66>

DMARQ (Input)

DMAAK (Output)

<54>

When Refresh Cycle is Inserted:

CLKOUT (Output)

DMARQ (Input)

DMAAK (Output)

<54>

ICU Timing

<67>

INTPn (Input)

(n=1-7)

Data Sheet U13225EJ4V0DS00

µPD70208H, 70216H

17. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14x20)

detail of lead end

C D

NOTE

1. Controlling dimension

millimeter.

ITEM MILLIMETERS

INCHES

23.6±0.4

0.929±0.016

2. Each lead centerline is located within 0.15 mm (0.006 inch) of

its true position (T.P.) at maximum material condition.

+0.009

0.795

20.0±0.2

–0.008

+0.009

0.551

14.0±0.2

–0.008

17.6±0.4

1.0

0.693±0.016

0.039

0.8

0.031

+0.08

0.37

+0.003

0.015

–0.07

–0.004

0.15

0.006

0.8 (T.P.)

0.031 (T.P.)

+0.008

0.071

1.8±0.2

0.8±0.2

–0.009

+0.009

0.031

–0.008

+0.08

0.17

+0.003

0.007

–0.07

–0.004

0.10

0.004

+0.005

0.106

2.7±0.1

–0.004

0.1±0.1

5°±5°

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

P80GF-80-3B9-4

Data Sheet U13225EJ4V0DS00

100

µPD70208H, 70216H

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

detail of lead end

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.10 mm (0.004 inch) of

its true position (T.P.) at maximum material condition.

14.0±0.2

12.0±0.2

0.551±0.008

+0.009

0.472

–0.008

+0.009

0.472

12.0±0.2

–0.008

0.551±0.008

0.049

14.0±0.2

1.25

0.049

+0.002

0.009

0.22±0.05

–0.003

0.004

0.10

0.5 (T.P.)

0.020 (T.P.)

+0.009

0.039

1.0±0.2

0.5±0.2

–0.008

+0.008

0.020

–0.009

+0.002

0.006

0.145±0.05

0.10

–0.003

0.004

+0.002

0.040

1.0±0.05

–0.003

0.1±0.05

0.004±0.002

+7°

3°

+7°

3°

–3°

1.2 MAX.

0.048 MAX.

S80GK-50-9EU

Data Sheet U13225EJ4V0DS00

101

µPD70208H, 70216H

68 PIN PLASTIC QFJ (950 x 950 mil)

C D

ITEM MILLIMETERS

INCHES

25.2±0.2

0.992±0.008

+0.004

0.953

24.20±0.1

−0.005

+0.004

0.953

24.20±0.1

−0.005

25.2±0.2

0.992±0.008

NOTES

1. Controlling dimension

+0.007

0.076

1.94±0.15

−0.006

millimeter.

0.6

0.024

+0.009

0.173

2. Each lead centerline is located within 0.12 mm of

its true position (T.P.) at maximum material condition.

4.4±0.2

−0.008

+0.009

2.8±0.2

0.110

−0.008

0.9 MIN.

0.035 MIN.

+0.004

0.134

3.4±0.1

−0.005

1.27 (T.P.)

0.050 (T.P.)

+0.003

0.42±0.08

0.017

−0.004

0.12

0.005

+0.009

23.12±0.2

0.910

−0.008

0.006

0.15

R 0.8

R 0.031

+0.08

0.22

+0.003

0.009

−0.07

−0.004

P68L-50A1-3

Data Sheet U13225EJ4V0DS00

102

µPD70208H, 70216H

18. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended in the table below.

For the details of recommended soldering conditions for the surface mounting type, refer to the information document

Semiconductor Device Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 18-1. Soldering Conditions

(1) µPD70208HGF-×-3B9 : 80-pin plastic QFP (14 × 20 mm)

µPD70216HGF-×-3B9 : 80-pin plastic QFP (14 × 20 mm)

(a) K, E, X masks

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Conditions Symbol

Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.),

IR30-107-1

Note

Number of times: 1, Number of days

: 7 days (after this, prebaking is necessary

at 125 °C for 10 hours)

VPS

Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.),

VP15-107-1

WS60-107-1

—

Note

Number of times: 1, Number of days

: 7 days (after this, prebaking is necessary

at 125 °C for 10 hours)

Wave soldering

Solder bath temperature: 260 °C max. Time: 10 sec. max., Number of times: 1,

Preheating temperature: 120 °C max. (Package surface temperature), Number of

Note

days

: 7 days (after this, prebaking is necessary at 125 °C for 10 hours).

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

(b) P, M masks

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Conditions Symbol

Package peak temperature: 235 °C, Time: 30 sec. max. (210 °C min.),

IR35-207-2

Note

Number of times: 2 max., Number of days

: 7 days (after this, prebaking is

necessary at 125 °C for 20 hours).

VPS

Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.)

VP15-207-2

Note

Number of times: 2 max., Number of days

: 7 days (after this prebaking is

necessary at 125 °C for 20 hours).

Wave soldering

Solder bath temperature: 260 °C max., Time: 10 sec. max.,

WS60-207-1

Number of times: 1, Preheating temperature: 120 °C max. (Package surface

Note

temperature). Number of days

: 7 days (after this, prebaking is necessary at

125 °C for 20 hours).

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

—

Note This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH

max.

Data Sheet U13225EJ4V0DS00

103

µPD70208H, 70216H

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Conditions Symbol

Package peak temperature: 235 °C, Time: 30 sec. max. (210 ˚C min.),

IR35-00-3

VP15-00-3

WS60-00-1

Number of times: 3 max.

VPS

Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.)

Number of times: 3 max.

Wave soldering

Solder bath temperature: 260 °C max., Time: 10 sec. max.,

Number of times: 1, Preheating temperature: 120 °C max. (Package surface

temperature)

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

—

Caution Do not use one soldering method in combination with another. (however, partial pin heating can

be performed with other soldering methods).

Data Sheet U13225EJ4V0DS00

104

µPD70208H, 70216H

(2) µPD70208HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µPD70216HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

(a) K, E, X masks

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Conditions Symbol

Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.),

IR30-101-1

VP15-101-1

—

Note

Number of timers: 1, Number of days

: 1 day (after this, prebaking is necessary

at 125 °C for 10 hours)

VPS

Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.),

Note

Number of times: 1, Number of days

: 1 day (after this, prebaking is necessary

at 125 °C for 10 hours)

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

(b) P, M, L, F masks

Recommended

Soldering Method

Soldering Conditions

Conditions Symbol

Infrared reflow

Package peak temperature: 235 °C, Time: 30 sec. max. (210 °C min.),

IR35-107-2

Note

Number of times: 2 max., Number of days

: 7 days (after this, prebaking is

necessary at 125 °C for 10 hours).

VPS

Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.), Number of times:

VP15-107-2

—

Note

2 max., Number of days

for 10 hours).

: 7 days (after this prebaking is necessary at 125 °C

Partial heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

Note This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH

max.

Caution Do not use one soldering method in combination with another. (however, partial pin heating can

be performed with other soldering methods).

Data Sheet U13225EJ4V0DS00

105

µPD70208H, 70216H

(3) µPD70208HLP-× : 68-pin plastic QFJ (950 × 950 mil)

µPD70216HLP-× : 68-pin plastic QFJ (950 × 950 mil)

(a) K, E, X masks

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Conditions Symbol

Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.),

IR30-367-1

VP15-367-1

—

Note

Number of timers: 1, Number of days

: 7 days (after this, prebaking is necessary

at 125 °C for 36 hours)

VPS

Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.),

Note

Number of times: 1, Number of days

: 7 days (after this, prebaking is necessary

at 125 °C for 36 hours)

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

(b) P, M, L, F masks

Recommended

Soldering Method

Soldering Conditions

Conditions Symbol

Infrared reflow

Package peak temperature: 235 °C, Time: 30 sec. max. (210 ˚C min.),

IR35-367-3

Note

Number of times: 3 max., Number of days

: 7 days (after this, prebaking is

necessary at 125 °C for 36 hours).

VPS

Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.),

VP15-367-3

—

Note

Number of times: 3 max., Number of days

: 7 days (after this prebaking is

necessary at 125 °C for 36 hours).

Partial pin heating

Pin temperature: 300 °C max., Time: 3 sec. max. (per device side)

Note This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH

max.

Caution Do not use one soldering method in combination with another. (however, partial pin heating can

be performed with other soldering methods).

Data Sheet U13225EJ4V0DS00

106

µPD70208H, 70216H

[MEMO]

Data Sheet U13225EJ4V0DS00

107

µPD70208H, 70216H

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet U13225EJ4V0DS00

108

µPD70208H, 70216H

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 91-504-2787

Fax: 01908-670-290

Fax: 91-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Italiana s.r.l.

Milano, Italy

NEC Electronics (Germany) GmbH

Scandinavia Office

Tel: 02-66 75 41

Fax: 02-2719-5951

Taeby, Sweden

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Fax: 08-63 80 388

Electron Devices Division

Rodovia Presidente Dutra, Km 214

07210-902-Guarulhos-SP Brasil

Tel: 55-11-6465-6810

Fax: 55-11-6465-6829

J99.1

Data Sheet U13225EJ4V0DS00

109

µPD70208H, 70216H

[MEMO]

V20, V20HL, V30, V30HL, V40, V40HL, V50, V50HL and V series are trademarks of NEC Corporation.

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated “quality assurance program“ for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98.8

UPD70216HLP-12 [NEC]

相关型号：

UPD70216HLP-16

UPD70216HLP-20

UPD70216HR-16

UPD70216L(A)-10

UPD70216L(A)-8

UPD70216L-8

UPD70216L10

UPD70216L8

UPD70216LA-10

UPD70216LA-8

UPD70216R

UPD70216R-10