UPD703033AGF [NEC]
V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS; V850 / SB1TM 32位/ 16位单芯片微控制器
| 型号： | UPD703033AGF |
| 厂家： | 
NEC |
| 描述： | V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS |
| 文件： | 总56页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703031A, 703031AY, 703033A,
703033AY, 70F3033A, 70F3033AY
V850/SB1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY (V850/SB1) are 32-/16-bit
single-chip microcontrollers of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.
The µPD70F3033A and 70F3033AY have flash memory in place of the internal mask ROM of the µPD703033A
and 703033AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SB1, V850/SB2TM User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 50 ns (@ internal 20 MHz operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 128 KB (µPD703031A, 703031AY: mask ROM)
256 KB (µPD703033A, 703033AY: mask ROM)
256 KB (µPD70F3033A, 70F3033AY: flash memory)
RAM: 12 KB (µPD703031A, 703031AY)
16 KB (µPD703033A, 703033AY, 70F3033A, 70F3033AY)
{ Interrupt/exception: µPD703031A, 703033A, 70F3033A (external: 8, internal: 30 sources, exception: 1 source)
µPD703031AY, 703033AY, 70F3033AY (external: 8, internal: 31 sources, exception: 1 source)
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14734EJ1V0DS00 (1st edition)
Date Published April 2000 N CP(K)
Printed in Japan
©
2000
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
{ Serial interface
• Asynchronous serial interface (UART0, UART1)
• Clocked serial interface (CSI0 to CSI3)
• 3-wire variable length serial interface (CSI4)
• I2C bus interface (I2C0, I2C1) (µPD703031AY, 703033AY, 70F3033AY only)
{ 10-bit resolution A/D converter: 12 channels
{ DMA controller: 6 channels
{ Real-time output port: 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction: 4 places can be corrected
{ Power-saving function: HALT/IDLE/STOP modes
{ Packages: 100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
{ µPD70F3033A, 70F3033AY
• Can be replaced with µPD703033A and 703033AY (internal mask ROM) in mass production
APPLICATIONS
{ AV equipment (audio, car audio, VCR, TV, etc.)
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD703031AGC-×××-8EU
µPD703031AYGC-×××-8EU
µPD703031AGF-×××-3BA
µPD703031AYGF-×××-3BA
µPD703033AGC-×××-8EU
µPD703033AYGC-×××-8EU
µPD703033AGF-×××-3BA
µPD703033AYGF-×××-3BA
µPD70F3033AGC-8EUNote
µPD70F3033AYGC-8EUNote
µPD70F3033AGF-3BANote
µPD70F3033AYGF-3BANote
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
Flash memory (256 KB)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
Note Under development
Remarks 1. ××× indicates ROM code suffix.
2. ROMless versions are not provided.
2
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN CONFIGURATION (Top View)
100-pin plastic LQFP (fine pitch) (14 × 14)
• µPD703031AGC-×××-8EU
• µPD70F3033AGC-8EU
• µPD70F3033AYGC-8EU
• µPD703031AYGC-×××-8EU
• µPD703033AGC-×××-8EU
• µPD703033AYGC-×××-8EU
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P21/SO2
P22/SCK2/SCL1Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EVDD
P71/ANI1
P70/ANI0
AVREF
2
3
4
AVSS
5
AVDD
6
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
7
EVSS
8
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/VPP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Notes 1. IC: Connect directly to VSS (µPD703031A, 703031AY, 703033A, 703033AY).
VPP: Connect to VSS in normal operation mode (µPD70F3033A, 70F3033AY).
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703033AY,
and 70F3033AY.
3
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-pin plastic QFP (14 × 20)
• µPD703031AGF-×××-3BA
• µPD703031AYGF-×××-3BA
• µPD703033AGF-×××-3BA
• µPD703033AYGF-×××-3BA
• µPD70F3033AGF-3BA
• µPD70F3033AYGF-3BA
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P21/SO2
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AVREF
2
3
4
P22/SCK2/SCL1Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EVDD
5
6
AVSS
7
AVDD
8
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
EVSS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
IC/VPP
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
Notes 1. IC: Connect directly to VSS (µPD703031A, 703031AY, 703033A, 703033AY).
VPP: Connect to VSS in normal operation mode (µPD70F3033A, 70F3033AY).
2. SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703033AY,
and 70F3033AY.
4
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN IDENTIFICATION
A1 to A21:
AD0 to AD15:
ADTRG:
Address Bus
P80 to P83:
P90 to P96:
P100 to P107:
P110 to P113:
RD:
Port 8
Address/Data Bus
AD Trigger Input
Analog Input
Port 9
Port 10
ANI0 to ANI11:
ASCK0, ASCK1:
ASTB:
Port 11
Asynchronous Serial Clock
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
Power Supply for Bus Interface
Ground for Bus Interface
Clock Output
Read
REGC:
Regulator Clock
Reset
AVDD:
RESET:
AVREF:
RTP0 to RTP7:
RTPTRG:
R/W:
Real-time Output Port
RTP Trigger Input
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Input
AVSS:
BVDD:
BVSS:
RXD0, RXD1:
SCK0 to SCK4:
SCL0, SCL1:
SDA0, SDA1:
SI0 to SI4:
SO0 to SO4:
TI00, TI01, TI10, :
TI11, TI2 to TI5
TO0 to TO5:
TXD0, TXD1:
UBEN:
CLKOUT:
DSTB:
Data Strobe
EVDD:
Power Supply for Port
Ground for Port
Hold Acknowledge
Hold Request
EVSS:
HLDAK:
HLDRQ:
IC:
Internally Connected
Interrupt Request from Peripherals
Key Return
INTP0 to INTP6:
KR0 to KR7:
LBEN:
Timer Output
Transmit Data
Lower Byte Enable
Non-Maskable Interrupt Request
Port 0
Upper Byte Enable
Power Supply
NMI:
VDD:
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
VPP:
Programming Power Supply
Ground
Port 1
VSS:
Port 2
WAIT:
Wait
Port 3
WRH:
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main Clock
Crystal for Sub-clock
Port 4
WRL:
Port 5
X1, X2:
Port 6
XT1, XT2:
Port 7
5
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
INTERNAL BLOCK DIAGRAM
ROM
CPU
NMI
INTC
HLDRQ (P96)
HLDAK (P95)
ROM
correction
Instruction
queue
INTP0 to INTP6
PC
Note 1
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT (P110)
TI00, TI01,
32-bit barrel
shifter
Multiplier
Timer/counters
TI10, TI11
16 × 16 → 32
TO0, TO1
16-bit timer
System
registers
BCU
: TM0, TM1
RAM
TI2/TO2
8-bit timer
TI3/TO3
TI4/TO4
TI5/TO5
ALU
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
: TM2 to TM7
General registers
32 bits
× 32
Note 2
SIO
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
SO0
SI0/SDA0Note 3
CSI0/I2C0Note 3
SCK0/SCL0Note 3
SO2
SI2/SDA1Note 3
CSI2/I2C1Note 3
CSI1/UART0
CSI3/UART1
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
CLKOUT
X1
Ports
A/D
converter
RTP
X2
XT1
CG
SO4
SI4
SCK4
Variable length
CSI4
XT2
RESET
Key return
function
KR0 to KR7
DMAC: 6ch
Watch timer
Watchdog timer
3.3 V
Regulator
V
V
DD
SS
BVDD
BVSS
EVDD
EVSS
Note 4
V
PP
ICNote 5
Notes 1. µPD703031A, 703031AY:
µPD703033A, 703033AY:
128 KB (mask ROM)
256 KB (mask ROM)
µPD70F3033A, 70F3033AY: 256 KB (flash memory)
2. µPD703031A, 703031AY:
12 KB
µPD703033A, 703033AY, 70F3033A, 70F3033AY: 16 KB
3. I2C bus interface and SDAn and SCLn pins are available only in the µPD703031AY, 703033AY,
and 70F3033AY.
4. µPD70F3033A, 70F3033AY
5. µPD703031A, 703031AY, 703033A, 703033AY
6
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
CONTENTS
1. DIFFERENCES AMONG PRODUCTS............................................................................................... 8
1.1 Differences of µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY................. 8
2. PIN FUNCTIONS.................................................................................................................................. 9
2.1 Port Pins..................................................................................................................................................... 9
2.2 Non-Port Pins........................................................................................................................................... 11
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 15
3. PROGRAMMING FLASH MEMORY (µPD70F3033A, 70F3033AY ONLY) ................................... 19
3.1 Selecting Communication Mode ............................................................................................................ 19
3.2 Function of Flash Memory Programming.............................................................................................. 20
3.3 Connecting Dedicated Flash Programmer............................................................................................ 20
4. ELECTRICAL SPECIFICATIONS...................................................................................................... 22
4.1 Flash Memory Programming Mode (µPD70F3033A, 70F3033AY only) ............................................... 47
5. PACKAGE DRAWINGS..................................................................................................................... 48
6. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 50
Data Sheet U14734EJ1V0DS00
7
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
1. DIFFERENCES AMONG PRODUCTS
1.1 Differences of µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY
Part Number µPD703031A µPD703031AY µPD703033A µPD703033AY µPD70F3033A µPD70F3033AY
Item
Internal ROM
128 KB (mask ROM)
None
256 KB (mask ROM)
256 KB (flash memory)
Provided (VPP)
Flash memory
programming pin
Flash memory
None
Provided (VPP = 7.8 V)
programming mode
I2C bus interface
pins (SCL0, SCL1,
SDA0, SDA1)
None
Provided
None
Provided
None
Provided
Electrical
Current consumption, etc. differs.
specifications
Others
Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient
evaluations for the commercial samples (not engineering samples) of the mask ROM
version.
2. When replacing the flash memory versions with mask ROM versions, write the same code
in the empty area of the internal ROM.
8
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
PULL
Yes
Function
Alternate Function
NMI
Port 0
8-bit I/O port
P01
INTP0
Input/output can be specified in 1-bit units.
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
INTP5/RTPTRG
INTP6
P06
P07
P10
I/O
Yes
Port 1
SI0/SDA0
SO0
6-bit I/O port
P11
Input/output can be specified in 1-bit units.
P12
SCK0/SCL0
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
P13
P14
P15
P20
I/O
Yes
Port 2
8-bit I/O port
P21
Input/output can be specified in 1-bit units.
P22
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2
P23
P24
P25
P26
P27
TI3/TO3
P30
I/O
Yes
Port 3
TI00
8-bit I/O port
P31
TI01
Input/output can be specified in 1-bit units.
P32
TI10/SI4
P33
TI11/SO4
TO0/A13/SCK4
TO1/A14
TI4/TO4/A15
TI5/TO5
P34
P35
P36
P37
P40 to P47
I/O
I/O
No
No
Port 4
AD0 to AD7
8-bit I/O port
Input/output can be specified in 1-bit units.
P50 to P57
Port 5
AD8 to AD15
8-bit I/O port
Input/output can be specified in 1-bit units.
Remark PULL: On-chip pull-up resistor
9
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/2)
Pin Name
I/O
I/O
PULL
No
Function
Alternate Function
A16 to A21
P60 to P65
Port 6
6-bit I/O port
Input/output can be specified in 1-bit units.
P70 to P77
P80 to P83
Input
Input
I/O
No
No
No
Port 7
ANI0 to ANI7
ANI8 to ANI11
8-bit input port
Port 8
4-bit input port
P90
Port 9
LBEN/WRL
UBEN
7-bit I/O port
P91
Input/output can be specified in 1-bit units.
P92
R/W/WRH
DSTB/RD
ASTB
P93
P94
P95
HLDAK
P96
HLDRQ
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
I/O
Yes
Port 10
RTP0/A5/KR0
RTP1/A6/KR1
RTP2/A7/KR2
RTP3/A8/KR3
RTP4/A9/KR4
RTP5/A10/KR5
RTP6/A11/KR6
RTP7/A12/KR7
A1/WAIT
8-bit I/O port
Input/output can be specified in 1-bit units.
I/O
Yes
Port 11
4-bit I/O port
A2
Input/output can be specified in 1-bit units.
A3
A4
Remark PULL: On-chip pull-up resistor
10
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.2 Non-Port Pins
(1/4)
Alternate Function
Pin Name
I/O
PULL
Yes
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
Output
Low-order address bus used for external memory expansion
P110/WAIT
P111
P112
P113
P100/RTP0/KR0
P101/RTP1/KR1
P102/RTP2/KR2
P103/RTP3/KR3
P104/RTP4/KR4
P105/RTP5/KR5
P106/RTP6/KR6
P107/RTP7/KR7
P34/TO0/SCK4
P35/TO1
A10
A11
A12
A13
A14
A15
P36/TO4/TI4
P60 to P65
A16 to A21
AD0 to AD7
AD8 to AD15
ADTRG
ANI0 to ANI7
ANI8 to ANI11
ASCK0
ASCK1
ASTB
Output
I/O
No
No
High-order address bus used for external memory expansion
16-bit multiplexed address/data bus used for external memory P40 to P47
expansion
P50 to P57
Input
Input
Yes
No
A/D converter external trigger input
Analog input to A/D converter
P05/INTP4
P70 to P77
P80 to P83
P15/SCK1
P25/SCK3
P94
Input
Yes
Baud rate clock input for UART0
Baud rate clock input for UART1
Output
No
−
External address strobe output
AVDD
−
Positive power supply for A/D converter and alternate port
Reference voltage input for A/D converter
Ground potential for A/D converter and alternate port
Positive power supply for bus interface and alternate port
Ground potential for bus interface and alternate port
Internal system clock output
−
−
−
−
−
−
AVREF
Input
−
AVSS
−
−
BVDD
−
−
−
BVSS
−
CLKOUT
DSTB
Output
Output
−
−
No
−
External data strobe output
P93/RD
EVDD
Positive power supply for I/O ports and alternate-function pins
(except bus interface alternate port)
−
−
EVSS
−
−
Ground potential for I/O ports and alternate-function pins
(except bus interface alternate port)
HLDAK
HLDRQ
IC
Output
Input
−
No
No
−
Bus hold acknowledge output
Bus hold request input
P95
P96
Internally connected
−
(µPD703031A, 703031AY, 703033A, 703033AY only)
Remark PULL: On-chip pull-up resistor
11
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/4)
Pin Name
INTP0
I/O
PULL
Yes
Function
Alternate Function
P01
Input
External interrupt request input (analog noise elimination)
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
P02
P03
P04
Input
Yes
External interrupt request input (digital noise elimination)
P05/ADTRG
P06/RTPTRG
P07
Input
Input
Yes
Yes
External interrupt request input (digital noise elimination
supporting remote controller)
KR0
Key return input
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11
P107/RTP7/A12
P90/WRL
KR1
KR2
KR3
KR4
KR5
KR6
KR7
LBEN
NMI
Output
Input
Output
−
No
Yes
No
−
External data bus’s low-order byte enable output
Non-maskable interrupt request input
Read strobe output
P00
RD
P93/DSTB
REGC
RESET
RTP0
RTP1
RTP2
RTP3
RTP4
RTP5
RTP6
RTP7
RTPTRG
R/W
Regulator output stabilization capacitance connection
System reset input
−
Input
Output
−
−
Yes
Real-time output port
P100/KR0/A5
P101/KR1/A6
P102/KR2/A7
P103/KR3/A8
P104/KR4/A9
P105/KR5/A10
P106/KR6/A11
P107/KR7/A12
P06/INTP5
P92/WRH
Input
Output
Input
Yes
No
Real-time output port external trigger input
External read/write status output
RXD0
RXD1
SCK0
SCK1
SCK2
SCK3
SCK4
Yes
Serial receive data input for UART0 and UART1
P13/SI1
P23/SI3
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI3
P12/SCL0
P15/ASCK0
P22/SCL1
P25/ASCK1
P34/TO0/A13
I/O
Yes
Serial clock I/O (3-wire type) for variable length CSI4
Remark PULL: On-chip pull-up resistor
12
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(3/4)
Pin Name
SCL0
I/O
I/O
PULL
Yes
Function
Serial clock I/O for I2C0 and I2C1
Alternate Function
P12/SCK0
P22/SCK2
P10/SI0
(µPD703031AY, 703033AY, 70F3033AY only)
SCL1
SDA0
SDA1
SI0
I/O
Yes
Yes
Serial transmit/receive data I/O for I2C0 and I2C1
(µPD703031AY, 703033AY, 70F3033AY only)
P20/SI2
Input
Serial receive data input (3-wire type) for CSI0 to CSI3
P10/SDA0
P13/RXD0
P20/SDA1
P23/RXD1
P32/TI10
P11
SI1
SI2
SI3
SI4
Input
Yes
Yes
Serial receive data input (3-wire type) for variable length CSI4
Serial transmit data output (3-wire type) for CSI0 to CSI3
SO0
SO1
SO2
SO3
SO4
TI00
Output
P14/TXD0
P21
P24/TXD1
P33/TI11
P30
Output
Input
Yes
Yes
Serial transmit data output (3-wire type) for variable length CSI4
External count clock input for TM0/external capture trigger
input for TM0
TI01
TI10
External capture trigger input for TM0
P31
External count clock input for TM1/external capture trigger
input for TM1
P32/SI4
TI11
TI2
External capture trigger input for TM1
P33/SO4
P26/TO2
P27/TO3
P36/TO4/A15
P37/TO5
P34/A13/SCK4
P35/A14
P26/TI2
P27/TI3
P36/TI4/A15
P37/TI5
P14/SO1
P24/SO3
P91
Input
Yes
External count clock input for TM2 to TM5
TI3
TI4
TI5
Output
Output
Yes
Yes
Pulse signal output for TM0 and TM1
Pulse signal output for TM2 to TM5
TO0
TO1
TO2
TO3
TO4
TO5
TXD0
TXD1
UBEN
VDD
Output
Yes
Serial transmit data output for UART0 and UART1
Output
No
−
High-order byte enable output for external data bus
Positive power supply pin
−
−
−
VPP
−
High voltage apply pin for program write/verify
−
(µPD70F3033A, 70F3033AY only)
VSS
−
−
Ground potential
−
P110/A1
WAIT
WRH
Input
Output
Yes
No
Control signal input for inserting wait in bus cycle
High-order byte write strobe signal output for external data
bus
P92/R/W
Remark PULL: On-chip pull-up resistor
13
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4/4)
Pin Name
WRL
I/O
Output
Input
−
PULL
No
Function
Alternate Function
Low-order byte write strobe signal output for external data bus P90/LBEN
Resonator connection for main clock
X1
No
−
−
−
−
X2
XT1
XT2
Input
−
No
Resonator connection for subsystem clock
Remark PULL: On-chip pull-up resistor
14
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For
the input/output schematic circuit diagram of each type, refer to Figure 2-1.
Table 2-1. Types of Pin I/O Circuits (1/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Recommended Connection of Unused Pins
Power Supply
P00
NMI
8-A
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
INTP0
Output state: Leave open.
INTP1
INTP2
INTP3
INTP4/ADTRG
INTP5/RTPTRG
INTP6
SI0/SDA0
SO0
10-A
26
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
SCK0/SCL0
SI1/RXD0
SO0/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
10-A
8-A
26
10-A
10-A
26
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2
10-A
26
10-A
8-A
TI3/TO3
TI00
8-A
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
TI01
Output state: Leave open.
TI10/SI4
TI11/SO4
TO0/A13/SCK4
TO1/A14
TI4/TO4/A15
TI5/TO5
5-A
8-A
P40 to
P47
AD0 to AD7
5
5
5
BVDD
BVDD
BVDD
Input state: Independently connect to BVDD or
BVSS via a resistor.
Output state: Leave open.
P50 to
P57
AD8 to AD15
A16 to A21
P60 to
P65
15
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 2-1. Types of Pin I/O Circuits (2/2)
Pin
Alternate Function
ANI0 to ANI7
I/O Circuit
Type
I/O Buffer
Recommended Connection of Unused Pins
Power Supply
P70 to
P77
9
9
5
AVDD
AVDD
BVDD
Independently connect to AVDD or AVSS via
resistor.
a
P80 to
P83
ANI8 to ANI11
P90
LBEN WRL
/
Input state: Independently connect to BVDD or
BVSS via a resistor.
P91
UBEN
Output state: Leave open.
P92
R/W WRH
/
P93
DSTB RD
/
P94
ASTB
P95
HLDAK
26
P96
HLDRQ
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
CLKOUT
RESET
XT1
RTP0/A5/KR0
RTP1/A6/KR1
RTP2/A7/KR2
RTP3/A8/KR3
RTP4/A9/KR4
RTP5/A10/KR5
RTP6/A11/KR6
RTP7/A12/KR7
10-A
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
WAIT
5-A
EVDD
Input state: Independently connect to EVDD or
EVSS via a resistor.
A1/
A2
A3
A4
Output state: Leave open.
–
–
–
–
–
–
–
4
2
BVDD
Leave open.
EVDD
–
16
16
–
–
–
–
–
–
Connect to VSS via a resistor.
Leave open.
XT2
AVREF
ICNote 1
VPPNote 2
Connect to AVSS via a resistor.
Connect directly to VSS.
Connect to VSS.
–
–
Notes 1. µPD703031A, 703031AY, 703033A, 703033AY
2. µPD70F3033A, 70F3033AY
Caution Three power supply systems are available to supply power to the I/O buffers of the V850/SB1’s
pins: EVDD, BVDD, and AVDD. The voltage ranges that can be used for these I/O buffer power
supplies are shown below.
EVDD, BVDD: 3.0 V to 5.5 V
AVDD: 4.5 V to 5.5 V
The electrical specifications differ depending on whether the power supply voltage range is 3.0
V to under 4.0 V, or 4.0 V to 5.5 V.
16
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup
enable
P-ch
VDD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 8-A
Type 4
VDD
VDD
Pullup
enable
P-ch
Data
P-ch
VDD
OUT
Data
P-ch
N-ch
Output
disable
N-ch
IN/OUT
Output
disable
Push-pull output that can be set for high-impedance output
(both P-ch and N-ch off)
Type 5
Type 9
VDD
Data
P-ch
N-ch
P-ch
Comparator
+
–
IN
IN/OUT
Output
disable
N-ch
VREF (threshold voltage)
Input enable
Input
enable
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
17
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (2/2)
Type 10-A
Type 26
VDD
V
DD
Pullup
enable
Pullup
enable
P-ch
P-ch
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
IN/OUT
Open drain
Open drain
N-ch
Output disable
N-ch
Output
disable
Type 16
Feedback cut-off
P-ch
XT1
XT2
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
18
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3. PROGRAMMING FLASH MEMORY (µPD70F3033A, 70F3033AY ONLY)
There are the following two methods for writing a program to the flash memory.
(1) On-board programming
Write a program to the flash memory using a dedicated flash programmer after the µPD70F3033A and
70F3033AY have been mounted on the target board. Also mount a connector, etc. on the target board to
communicate with the dedicated flash programmer.
(2) Off-board programming
Write a program using a dedicated adapter before the µPD70F3033A and 70F3033AY have been mounted on
the target board.
3.1 Selecting Communication Mode
To write the flash memory, use a dedicated flash programmer and serial communication. Select a serial
communication mode from those listed in Table 3-1 in the format shown in Figure 3-1. Each communication mode is
selected by the number of VPP pulses shown in Table 3-1.
Table 3-1. Communication Modes
Communication Mode
CSI0
Pins Used
Number of VPP Pulses
0
SO0 (serial data output)
SI0 (serial data input)
SCK0 (serial clock input)
CSI0 + HS
SO0 (serial data output)
SI0 (serial data input)
SCK0 (serial clock input)
3
8
P15 (3-wire + handshake signal output of handshake communication)
UART0
TXD0 (serial data output)
RXD0 (serial data input)
Figure 3-1. Communication Mode Selecting Format
7.8 V
V
PP
V
V
DD
SS
V
V
DD
SS
RESET
19
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. The major functions are shown below.
Table 3-2. Major Functions of Flash Memory Programming
Function
Description
Category
Verify
Command
Batch verify
Compares the contents of the entire memory and the input data.
Erases the contents of the entire memory.
Erase
Batch erase
Write back
Writes back the contents which is overerased.
Checks the erase state of the entire memory.
Blank check
Data write
Batch blank check
High-speed write
Writes data by the specification of the write start address and the
number of bytes to be written, and executes verify check.
Continuous write
Status read out
Writes data from the address following the high-speed write command
executed immediately before, and executes verify check.
System
Reads out the status of operations.
Sets the oscillation frequency.
setting/control
Oscillation frequency
setting
Erase time setting
Write time setting
Write back time setting
Baud rate setting
Silicon signature
Reset
Sets the erase time of batch erase.
Sets the write time of data write.
Sets the write back time.
Sets the baud rate when using UART0.
Reads out the silicon signature information.
Restarts the system of flash programmer.
3.3 Connecting Dedicated Flash Programmer
The connection of the dedicated flash programmer and the µPD70F3033A and 70F3033AY differs according to
the communication mode. The connections for each communication mode are shown below.
Figure 3-2. Connection of Dedicated Flash Programmer in CSI0 Mode
µ
Dedicated flash programmer
PD70F3033A, 70F3033AY
V
PP
V
V
V
PP
DD
SS
V
DD
GND
RESET
SI
RESET
SO0
SO
SI0
SCK
SCK0
20
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 3-3. Connection of Dedicated Flash Programmer in CSI0 + HS Mode
Dedicated flash programmer
PD70F3033A, 70F3033AY
VPP
VDD
VPP
VDD
GND
RESET
SI
VSS
RESET
SO0
SI0
SO
SCK
HS
SCK0
P15
Figure 3-4. Connection of Dedicated Flash Programmer in UART0 Mode
µ
Dedicated flash programmer
PD70F3033A, 70F3033AY
V
PP
V
PP
DD
SS
V
DD
V
GND
RESET
RxD
V
RESET
TXD0
TxD
RXD0
21
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +0.5
–0.5 to +0.5
–0.5 to +0.5
–0.5 to BVDD + 0.5Note 4
–0.5 to EVDD + 0.5Note 4
–0.5 to +8.5
–0.5 to AVDD + 0.5Note 4
–0.5 to AV
Unit
V
VDD pin
AVDD
BVDD
EVDD
AVSS
BVSS
EVSS
VI1
AVDD pin
BVDD pin
EVDD pin
AVSS pin
BVSS pin
EVSS pin
Note 1 (BV
Note 2 (EV
V
V
V
V
V
V
Input voltage
DD pin)
DD pin)
V
VI2
V
VI3
VPP pin (µPD70F3033A, 70F3033AY only)
V
Analog input voltage
VIAN
Note 3 (AVDD pin)
AVREF pin
V
Analog reference input voltage
Output current, low
AVREF
IOL
DD + 0.5Note 4
V
Per pin
4.0
mA
mA
Total for P00 to P07, P10 to P15, P20 to
P25
25
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, CLKOUT
Total for P50 to P57, P60 to P65
Per pin
25
25
mA
mA
mA
mA
Output current, high
IOH
–4.0
–25
Total for P00 to P07, P10 to P15, P20 to
P25
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
–25
mA
Total for P40 to P47, P90 to P96, CLKOUT
Total for P50 to P57, P60 to P65
Note 1 (BV
–25
–25
mA
mA
V
Output voltage
VO1
VO2
TA
DD pin)
–0.5 to BVDD + 0.5Note 4
–0.5 to EVDD + 0.5Note 4
–40 to +85
Note 2 (EV
DD pin)
V
Operating ambient temperature
Normal operation mode
°C
°C
Flash memory programming mode
10 to 85
(µPD70F3033A, 70F3033AY only)
Storage temperature
Tstg
µPD703031A, 703031AY
µPD703033A, 703033AY
µPD70F3033A, 70F3033AY
–65 to +150
°C
°C
–40 to +125
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins
2. Ports 0, 1, 2, 3, 10, 11, RESET, and their alternate-function pins
3. Ports 7, 8, and their alternate-function pins
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
22
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
(1) Operating frequency
Operating Frequency (fXX)
2 to 20 MHz
VDD
AVDD
BVDD
EVDD
Remark
4.0 to 5.5 V
4.0 to 5.5 V
4.0 to 5.5 V
3.5 to 5.5 V
4.5 to 5.5 V
4.5 to 5.5 V
4.5 to 5.5 V
4.5 to 5.5 V
4.0 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
4.0 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
Note 1
Note 1
–
2 to 17 MHz
32.768 kHz
Other than IDLE mode
IDLE mode
Note 2
Notes 1. During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or
restoring from STOP mode must be performed at VDD = 4.0 V min.
2. Shifting to IDLE mode or restoring from IDLE mode must be performed at VDD = 4.0 V min.
(2) CPU operating frequency
Parameter
Symbol
fCPU
Conditions
Main system clock operation
Subsystem clock operation
MIN.
0.25
TYP.
MAX.
20
Unit
MHz
kHz
CPU operating frequency
32.768
23
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Recommended Oscillator
(1) Main system clock oscillator (TA = –40 to +85°C)
(a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter
Symbol
Conditions
MIN.
2
TYP.
MAX.
20
Unit
MHz
s
Oscillation frequency
Oscillation stabilization time
fXX
–
Upon reset release
Upon STOP mode release
219/fXX
–
Note
s
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Cautions 1. Main system clock oscillator operates on the output voltage of the on-chip regulator.
External clock input is prohibited.
2. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5.
4. Sufficiently evaluate the matching between the µPD703031A, 703031AY, 703033A, 703033AY,
70F3033A, 70F3033AY and the resonator.
24
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Subsystem clock oscillator (TA = –40 to +85°C)
(a) Connection of crystal resonator
XT1
XT2
Parameter
Symbol
Conditions
MIN.
32
TYP.
32.768
10
MAX.
35
Unit
kHz
s
Oscillation frequency
Oscillation stabilization time
fXT
–
Cautions 1. Subsystem clock oscillator operates on the output voltage of the on-chip regulator.
External clock input is prohibited.
2. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
3. Sufficiently evaluate the matching between the µPD703031A, 703031AY, 703033A, 703033AY,
70F3033A, 70F3033AY and the resonator.
25
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
VIH1
Conditions
4.0 V ≤ BVDD ≤ 5.5 V
MIN.
0.7BVDD
0.8BVDD
0.7EVDD
0.8EVDD
0.7EVDD
0.8EVDD
0.7AVDD
BVSS
TYP.
MAX.
BVDD
Unit
V
Input voltage, high
Note 1
Note 2
Note 3
BVDD
V
3.0 V ≤ BVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.5 V ≤ AVDD ≤ 5.5 V
VIH2
EVDD
V
EVDD
V
VIH3
EVDD
V
EVDD
V
VIH4
VIL1
VIL2
VIL3
VIL4
VOH1
Note 4
Note 1
Note 2
Note 3
Note 4
Note 1
AVDD
V
Input voltage, low
0.3BVDD
0.3EVDD
0.3EVDD
0.3AVDD
V
EVSS
V
EVSS
V
AVSS
V
Output voltage, high
BVDD–0.5
V
3.0 V ≤ BVDD ≤ 5.5 V,
IOH = –100 µA
BVDD–1.0
EVDD–0.5
EVDD–1.0
V
V
V
V
V
4.0 V ≤ BVDD ≤ 5.5 V,
IOH = –3 mA
VOH2
Notes 2, 3
3.0 V ≤ EVDD ≤ 5.5 V,
IOH = –100 µA
(except RESET)
4.0 V ≤ EVDD ≤ 5.5 V,
IOH = –3 mA
Output voltage, low
VOL
0.5
0.4
IOL = 3 mA,
3.0 V ≤ BVDD, EVDD ≤ 5.5 V
IOL = 3 mA,
4.0 V ≤ BVDD, EVDD ≤ 5.5 V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
ILIH
ILIL
ILOH
ILOL
VI = VDD = BVDD = EVDD = AVDD
VI = 0 V
5
–5
5
µA
µA
µA
µA
–5
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins
2. P11, P14, P21, P24, P34, P35, P110 to P113, and their alternate-function pins
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P100 to P107,
RESET, and their alternate-function pins
4. Ports 7, 8, and their alternate-function pins
26
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
IDD1
Conditions
In normal operation modeNote 1
In HALT modeNote 1
MIN.
TYP.
25
MAX.
40
Unit
mA
mA
mA
Supply current
µPD703031A,
µPD703031AY,
µPD703033A,
µPD703033AY
IDD2
10
20
IDD3
In IDLE
Watch timer operating
1
4
modeNote 2
IDD4
In STOP
mode
Watch timer, subsystem
oscillator operating
13
8
70
70
µA
µA
µA
µA
Subsystem oscillator
stopped, XT1 = VSS
IDD5
In normal mode (subsystem
operation)Note 3
50
13
150
70
IDD6
In IDLE mode (subsystem
operation)Note 3
µPD70F3033A,
µPD70F3033AY
IDD1
IDD2
IDD3
In normal operation modeNote 1
In HALT modeNote 1
33
10
1
60
20
4
mA
mA
mA
In IDLE
Watch timer operating
modeNote 2
IDD4
In STOP
mode
Watch timer, subsystem
oscillator operating
13
8
100
100
600
180
100
µA
µA
µA
µA
kΩ
Subsystem oscillator
stopped, XT1 = VSS
IDD5
IDD6
RL
In normal mode (subsystem
operation)Note 3
200
90
30
In IDLE mode (subsystem
operation)Note 3
Pull-up resistance
VIN = 0 V
10
Notes 1. fCPU = fXX = 20 MHz, all peripheral functions operating, output buffer: OFF
2. fXX = 20 MHz
3. fCPU = fXT = 32.768 kHz, main system clock oscillator stopped
Remark TYP. values are reference values for when TA = 25°C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current
consumed by the output buffer is not included.
27
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Conditions
MIN.
TYP.
8
MAX.
5.5
Unit
V
STOP mode
VDD = VDDDR, µPD703031A,
3.0Note
70
µA
XT1 = VSS
(subsystem
stopped)
µPD703031AY,
µPD703033A,
µPD703033AY
µPD70F3033A,
µPD70F3033AY
8
100
µA
Supply voltage rise time
Supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
µs
Supply voltage hold time
(from STOP mode setting)
ms
STOP release signal input time
tDREL
VIHDR
VILDR
0
0.9VDDDR
0
ms
V
Data retention high-level input voltage
Data retention low-level input voltage
All input ports
All input ports
VDDDR
0.1VDDDR
V
Note During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or
restoring from STOP mode must be performed at VDD = 4.0 V min.
Remark TYP. values are reference values for when TA = 25°C.
Setting STOP mode
V
DDDR
V
DD
t
FVD
t
RVD
t
HVD
t
DREL
V
V
IHDR
RESET (input)
NMI, INTPn (input)
IHDR
(Released by falling edge)
NMI, INTPn (input)
(Released by rising edge)
V
ILDR
28
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
AC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS =
AVSS = BVSS = EVSS = 0 V)
AC Test Input Waveform (VDD: EVDD, BVDD, AVDD)
V
DD
V
IH
IL
V
IH
Test points
Input signal
0 V
V
V
IL
AC Test Output Test Points (EVDD, BVDD)
V
V
OH
V
OH
Output signal
Test points
OL
V
OL
Load Conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance
of the device to 50 pF or less by inserting a buffer or by some other means.
29
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(1) Clock timing
(a) TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V
Parameter
CLKOUT output cycle
Symbol
Conditions
MIN.
MAX.
Unit
<1>
tCYK
tWKH
tWKL
tKR
50 ns
31.2 µs
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<2>
<3>
<4>
<5>
0.4tCYK – 12
0.4tCYK – 12
ns
ns
ns
ns
12
12
CLKOUT fall time
tKF
(b) TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V
Parameter
CLKOUT output cycle
Symbol
Conditions
MIN.
MAX.
Unit
<1>
tCYK
tWKH
tWKL
tKR
58.8 ns
31.2 µs
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<2>
<3>
<4>
<5>
0.4tCYK – 15
0.4tCYK – 15
ns
ns
ns
ns
15
15
CLKOUT fall time
tKF
<1>
<2>
<3>
CLKOUT (output)
<5>
<4>
30
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Output waveform (other than port 4, port 5, port 6, port 9, X1, and CLKOUT)
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = BVSS = EVSS = 0 V)
Parameter
Output rise time
Symbol
<6>
Conditions
MIN.
MAX.
20
Unit
ns
tOR
tOF
Output fall time
<7>
20
ns
<7>
<6>
Output signal
(3) Reset timing
Parameter
Symbol
Conditions
MIN.
500
500
MAX.
Unit
ns
RESET pin high-level width
RESET pin low-level width
<8>
<9>
tWRSH
tWRSL
ns
<8>
<9>
RESET (input)
31
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4) Bus timing
(a) Clock asynchronous (TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float from DSTB↓
<10>
tSAST
tHSTA
0.5T – 16
0.5T – 15
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<36>
<37>
tFDA
0
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ to ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
tSAID
(2 + n)T – 40
(1 + n)T – 40
tSDID
tDSTD
0.5T – 15
0
tHDID
tDDA
(1 + i)T – 15
0.5T – 15
(1.5 + i)T – 15
(1 + n)T – 22
T – 15
tDDST1
tDDST2
tWDL
ASTB high-level width
tWSTH
tDDOD
tSODD
tHDOD
tSAWT1
tSAWT2
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
tHSTWT1
tHSTWT2
tWHQH
tWHAL
tDHAC
tDHQHA1
tDHQHA2
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
10
(1 + n)T – 25
T – 20
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
1.5T – 40
(1.5 + n)T – 40
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
(0.5 + n)T
(1.5 + n)T
T – 32
(1 + n)T – 32
nT
(1 + n)T
T + 10
T – 15
–6
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
(2n + 7.5)T + 25
1.5T + 25
0.5T
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
32
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(b) Clock asynchronous (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float from DSTB↓
<10>
tSAST
tHSTA
0.5T – 20
0.5T – 20
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<36>
<37>
tFDA
0
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ to ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
tSAID
(2 + n)T – 50
(1 + n)T – 50
tSDID
tDSTD
0.5T – 15
0
tHDID
tDDA
(1 + i)T – 15
0.5T – 15
(1.5 + i)T – 15
(1 + n)T – 35
T – 15
tDDST1
tDDST2
tWDL
ASTB high-level width
tWSTH
tDDOD
tSODD
tHDOD
tSAWT1
tSAWT2
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
tHSTWT1
tHSTWT2
tWHQH
tWHAL
tDHAC
tDHQHA1
tDHQHA2
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
10
(1 + n)T – 35
T – 25
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
1.5T – 55
(1.5 + n)T – 55
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
(0.5 + n)T
(1.5 + n)T
T – 45
(1 + n)T – 45
nT
(1 + n)T
T + 10
T – 25
–6
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
(2n + 7.5)T + 25
1.5T + 25
0.5T
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
33
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(c) Clock synchronous (TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
0
MAX.
19
Unit
ns
Delay time from CLKOUT↑ to address
<38>
tDKA
tFKA
Delay time from CLKOUT↑ to address
<39>
–12
10
ns
float
Delay time from CLKOUT↓ to ASTB
Delay time from CLKOUT↑ to DSTB
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Data output delay time from CLKOUT↑
WAIT setup time (to CLKOUT↓)
<40>
<41>
<42>
<43>
<44>
<45>
<46>
<47>
<48>
<49>
tDKST
tDKD
0
0
19
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSIDK
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKF
20
5
19
20
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
20
5
Delay time from CLKOUT↑ to address
19
19
float (during bus hold)
Delay time from CLKOUT↑ to HLDAK
<50>
tDKHA
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
(d) Clock synchronous (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
0
MAX.
22
Unit
ns
Delay time from CLKOUT↑ to address
<38>
tDKA
tFKA
Delay time from CLKOUT↑ to address
<39>
–16
10
ns
float
Delay time from CLKOUT↓ to ASTB
Delay time from CLKOUT↑ to DSTB
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Data output delay time from CLKOUT↑
WAIT setup time (to CLKOUT↓)
<40>
<41>
<42>
<43>
<44>
<45>
<46>
<47>
<48>
<49>
tDKST
tDKD
0
0
19
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSIDK
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKF
20
5
22
24
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
24
5
Delay time from CLKOUT↑ to address
19
19
float (during bus hold)
Delay time from CLKOUT↑ to HLDAK
<50>
tDKHA
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
34
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
<38>
A1 to A15 (output)
A16 to A21 (output)
Note (output)
<42>
<43>
<13>
<39>
Address
Data
AD0 to AD15 (I/O)
<40>
<10>
<11>
<40>
<16>
ASTB (output)
<21>
<
41
12
15
>
<
41
>
<
18
>
<
>
<
17>
<
>
<14>
<19>
DSTB, RD (output)
<20>
<
29><45> <46
>
<45>
<46>
<31>
<30>
<32>
WAIT (input)
<25>
<27>
<26>
<28>
Note R/W, UBEN, LBEN
Remark The broken lines indicate high impedance.
35
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
<38>
A1 to A15 (output)
A16 to A21 (output)
Note (output)
<44>
Address
Data
AD0 to AD15 (I/O)
<40>
<10>
<11>
<40>
ASTB (output)
<21>
<41>
<41>
<18>
<22>
<15>
<24>
<23>
DSTB, WRL, WRH (output)
<20>
<
29><45> <46
>
<45>
<46>
<31>
<30>
<32>
WAIT (input)
<25>
<27>
<26>
<28>
Note R/W, UBEN, LBEN
Remark The broken lines indicate high impedance.
36
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(g) Bus hold timing
TH
TH
TH
TH
TI
CLKOUT (output)
<47>
<47> <48>
<33>
HLDRQ (input)
HLDAK (output)
<50>
<50>
<37>
<36>
<34>
<49>
<35>
A16 to A19 (output)
Note (output)
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
ASTB (output)
DSTB, RD (output)
WRL, WRH (output)
Note R/W, UBEN, LBEN
Remark The broken lines indicate high impedance.
37
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(5) Interrupt timing
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
NMI high-level width
Symbol
Conditions
MIN.
500
500
500
MAX.
Unit
ns
<51>
tWNIH
tWNIL
tWITH
NMI low-level width
<52>
<53>
ns
INTPn high-level width
n = 0 to 3, analog noise
elimination
ns
n = 4, 5, digital noise
elimination
3T + 20
3Tsmp + 20
500
ns
ns
ns
ns
ns
n = 6, digital noise
elimination
INTPn low-level width
<54>
tWITL
n = 0 to 3, analog noise
elimination
n = 4, 5, digital noise
elimination
3T + 20
n = 6, digital noise
elimination
3Tsmp + 20
Remarks 1. T = 1/fXX
2. Tsmp = Noise elimination sampling clock cycle
<51>
<52>
<54>
NMI (input)
<53>
INTPn (input)
Remark n = 0 to 6
38
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(6) RPU timing (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
TIn0, TIn1 high-level width
TIn0, TIn1 low-level width
TIn high-level width
Symbol
Conditions
n = 0, 1
MIN.
MAX.
Unit
ns
<55>
tTIHn
tTILn
tTIHn
tTILn
2T
2T
sam + 20Note
sam + 20Note
3T + 20
3T + 20
<56>
<57>
<58>
n = 0, 1
ns
n = 2 to 5
n = 2 to 5
ns
TIn low-level width
ns
Note Tsam can select the following count clocks by setting the PRMn2 to PRMn0 bits of prescaler mode registers
n0, n1 (PRMn0, PRMn1).
When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle
When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T.
Remark T = 1/fXX
<55>
<57>
<56>
<58>
TIn0, TIn1 (input)
TIn (input)
Remark n = 0 to 5
39
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(7) Asynchronous serial interface (UART0, UART1) timing
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
ASCKn cycle time
Symbol
Conditions
MIN.
200
80
MAX.
Unit
ns
<59>
tKCY13
tKH13
ASCKn high-level width
ASCKn low-level width
<60>
<61>
ns
tKSO13
80
ns
Remark n = 0, 1
<59>
<60>
<61>
ASCKn (input)
Remark n = 0, 1
40
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(8) 3-wire serial interface (CSI0 to CSI3) timing
(a) Master mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
SCKn cycle
<62>
<63>
<64>
<65>
<66>
<67>
tKCY1
tKH1
SCKn high-level width
SCKn low-level width
tKL1
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
Delay time from SCKn↓ to SOn output
tSIK1
tKSI1
tKSO1
50
60
Remark n = 0 to 3
(b) Slave mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
<62>
<63>
<64>
<65>
<66>
<67>
tKCY2
tKH2
SCKn high-level width
SCKn low-level width
tKL2
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
Delay time from SCKn↓ to SOn output
tSIK2
tKSI2
tKSO2
50
60
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
100
Remark n = 0 to 3
<62>
<64>
<63>
SCKn (I/O)
SIn (input)
<65>
<66>
Input data
<67>
SOn (output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
41
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(9) 3-wire variable length serial interface (CSI4) timing
(a) Master mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
<68>
Conditions
MIN.
200
400
60
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK4 cycle
tKCY1
tKH1
tKL1
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
SCK4 high-level width
<69>
<70>
<71>
140
60
SCK4 low-level width
140
25
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
tSIK1
50
<72>
<73>
tKSI1
20
Delay time from SCK4↓ to SO4
tKSO1
55
output
(b) Slave mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
<68>
Conditions
MIN.
200
400
60
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK4 cycle
tKCY2
tKH2
tKL2
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
SCK4 high-level width
<69>
<70>
<71>
140
60
SCK4 low-level width
140
25
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
tSIK2
50
<72>
<73>
tKSI2
20
Delay time from SCK4↓ to SO4
tKSO2
4.0 V ≤ EVDD ≤ 5.5 V
3.0 V ≤ EVDD < 4.0 V
55
output
100
42
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<68>
<69>
<70>
SCK4 (I/O)
<71> <72>
SI4 (input)
Input data
<73>
SO4 (output)
Output data
Remark The broken lines indicate high impedance.
43
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(10)I2C bus mode (µPD703031AY, 703033AY, 70F3033AY only)
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Normal Mode
High-Speed Mode
MIN. MAX.
Unit
MIN.
MAX.
SCLn clock frequency
–
fCLK
0
100
–
0
400
–
kHz
Bus-free time (between
stop/start conditions)
<74> tBUF
4.7
1.3
µs
Hold timeNote 1
<75> tHD:STA
<76> tLOW
<77> tHIGH
<78> tSU:STA
4.0
4.7
4.0
4.7
–
–
–
–
0.6
1.3
0.6
0.6
–
–
–
–
s
µ
SCLn clock low-level width
SCLn clock high-level width
µs
µs
µs
Setup time for start/restart
conditions
Data hold
time
CBUS
<79> tHD:DAT
5.0
–
–
–
µs
compatible
master
I2C mode
0Note 2
250
–
–
–
0Note 2
0.9Note 3
–
µs
ns
ns
Data setup time
<80> tSU:DAT
<81> tR
100Note 4
SDAn and SCLn signal rise
time
1000
20 + 0.1CbNote 5
300
SDAn and SCLn signal fall
time
<82> tF
–
300
20 + 0.1CbNote 5
300
ns
Stop condition setup time
<83> tSU:STO
<84> tSP
4.0
–
–
–
0.6
0
–
µs
Pulse width of spike
50
ns
suppressed by input filter
Capacitance load of each
bus line
–
Cb
–
400
–
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin.. of SCLn
signal) in order to occupy the undefined area at the falling edge of SCLn.
3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time
(tHD:DAT) needs to be satisfied.
4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions.
• If the system does not extend the SCLn signal’s low state hold time:
tHD:DAT ≥ 250 ns
• If the system extends the SCLn signal’s low state hold time:
Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000
+ 250 = 1250 ns: Normal mode I2C bus specification).
5. Cb: Total capacitance of one bus line (unit: pF)
Remark n = 0, 1
44
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<76> <77>
SCLn (I/O)
<78>
<82> <81>
<79>
<80>
<75>
<84>
<83>
<75>
SDAn (I/O)
<74>
Stop
condition
Start
condition
Restart
condition
Stop
condition
Remark n = 0, 1
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF, VSS = AVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
–
–
Overall errorNote 1
ADM2 = 00H
ADM2 = 01H
±0.6
±1.0
10
%FSR
%FSR
µs
Conversion time
tCONV
AINL
AINL
5
Zero-scale errorNote 1
Full-scale errorNote 1
±0.4
±0.4
±0.6
±4.0
±6.0
±4.0
±6.0
5.5
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
ADM2 = 00H
ADM2 = 01H
ADM2 = 00H
ADM2 = 01H
ADM2 = 00H
ADM2 = 01H
AVREF =AVDD
Integral linearity errorNote 2
INL
Differential linearity errorNote 2
DNL
Analog reference voltage
Analog power supply voltage
Analog input voltage
AVREF input current
AVREF
AVDD
VIAN
4.5
4.5
5.5
V
AVSS
AVREF
2
V
AIREF
AIDD
1
3
4
mA
AVDD current
ADM2 = 00H
ADM2 = 01H
6
mA
8
mA
Notes 1. Excluding quantization error (±0.05 %FSR)
2. Excluding quantization error (±0.5 LSB)
Remarks 1. LSB: Least Significant Bit
FSR: Full Scale Range
2. ADM2: A/D converter mode register 2
45
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regulator (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter
Symbol
<85> tREG
Conditions
MIN.
1
TYP.
MAX.
Unit
ms
Output stabilization time
Stabilization capacitance C = 1 µF
(Connected to REGC pin)
V
DD
<85>
BVDD, EVDD
RESET (input)
Cautions 1. Be sure to start inputting supply voltage (VDD) when RESET = VSS = EVSS = BVSS = 0 V
(the above state), and make RESET high level after the tREG period has elapsed.
2. If supply voltage (BVDD or EVDD) is input before the tREG period has elapsed following the
input of supply voltage (VDD), data may be driven from the pins until the tREG period has
elapsed because the I/O buffers’ power supply was turned on while the circuit was in an
undefined state. To avoid this situation, it is recommended to input supply voltage
(BVDD or EVDD) after the tREG period has elapsed following the input of supply voltage
(VDD).
46
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4.1 Flash Memory Programming Mode (µPD70F3033A, 70F3033AY only)
Basic characteristics (TA = 10 to 85°C)
Parameter
Operating frequency
Power supply voltage
Write current
Symbol
fX
Conditions
MIN.
2
TYP.
MAX.
20
Unit
MHz
V
VDD
4.5
5.5
63
IDDW
IPPW
IDDE
IPPE
When VPP = VPP1
VDD pin
VPP pin
VDD pin
VPP pin
mA
mA
mA
mA
V
50
Erase current
When VPP = VPP1
63
100
0.6
8.1
20
VPP power supply voltage
VPP0
VPP1
CWRT
tER
During normal operation
0
During flash memory programming
7.5
20
0.2
7.8
20
V
Write countNote
Unit erase time
Total erase time
Times
s
0.2
0.2
5.8
tERT
s
Note Erase/write are regarded as 1 cycle.
47
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
5. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
16.00±0.20
14.00±0.20
14.00±0.20
16.00±0.20
1.00
G
1.00
+0.05
0.22
H
−0.04
I
J
0.08
0.50 (T.P.)
1.00±0.20
0.50±0.20
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.40±0.05
0.10±0.05
+7°
3°
R
S
−3°
1.60 MAX.
S100GC-50-8EU-1
48
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
R
Q
31
30
100
1
F
P
G
J
M
H
I
K
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
23.6±0.4
20.0±0.2
14.0±0.2
17.6±0.4
0.8
0.6
0.30±0.10
0.15
J
0.65 (T.P.)
1.8±0.2
0.8±0.2
K
L
+0.10
0.15
M
−0.05
N
P
Q
R
S
0.10
2.7±0.1
0.1±0.1
5°±5°
3.0 MAX.
P100GF-65-3BA1-4
49
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
6. RECOMMENDED SOLDERING CONDITIONS
The µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY should be soldered and mounted
under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 6-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD703031AGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703031AYGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703033AGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703033AYGC-×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
IR35-107-2
VP15-107-2
–
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD70F3033AGC-8EU:
µPD70F3033AYGC-8EU:
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
IR35-103-2
VP15-103-2
–
Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
50
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 6-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD703031AGF-×××-3BA: 100-pin plastic QFP (14 × 20)
µPD703031AYGF-×××-3BA: 100-pin plastic QFP (14 × 20)
µPD703033AGF-×××-3BA: 100-pin plastic QFP (14 × 20)
µPD703033AYGF-×××-3BA: 100-pin plastic QFP (14 × 20)
µPD70F3033AGF-3BA:
µPD70F3033AYGF-3BA:
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
IR35-207-2
VP15-207-2
WS60-207-1
–
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours)
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours)
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once
Preheating temperature: 120°C max. (package surface temperature)
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 hours)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
51
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
52
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
53
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
Reference document Electrical Characteristics for Microcomputer (IEI-601)Note
Note This document number is that of the Japanese version.
V850/SB1, V850/SB2, and V850 Family are trademarks of NEC Corporation.
54
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
55
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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