UPD703041GM-XXX-UEU-A [NEC]
Microcontroller, 32-Bit, MROM, 20MHz, MOS, PQFP176, 24 X 24 MM, FINE PITCH, LEAD FREE, PLASTIC, LQFP-176;
| 型号： | UPD703041GM-XXX-UEU-A |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 32-Bit, MROM, 20MHz, MOS, PQFP176, 24 X 24 MM, FINE PITCH, LEAD FREE, PLASTIC, LQFP-176 时钟 微控制器 外围集成电路 |
| 文件： | 总49页 (文件大小：762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703038, 703038Y, 703039, 703039Y, 703040, 703040Y,
703041, 703041Y
V850/SV1
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the
V850/SV1) are products in the low-power series of V850 Series products, which are NEC Electronics’ single-chip
microcontrollers for real-time control.
The V850/SV1 employs the CPU core of the V850 Series, and has on-chip peripheral functions such as large
capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a
Vsync/Hsync separation circuit.
The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but
also has an extremely high cost performance.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware:
U14462E
V850 Series User’s Manual Architecture: U10243E
FEATURES
{ 10-bit resolution A/D converter: 16 channels
{ Timer/counter
{ Number of instructions: 74
{ Minimum instruction execution time:
50 ns (@ 20 MHz operation with main system clock)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set (signed multiplication, saturation
operations, 32-bit shift instructions, bit manipulation
instructions, load/store instructions)
{ Memory space:
24-bit: 2 channels, 16-bit: 2 channels
8-bit: 8 channels
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ DMA controller: 6 channels
{ Interrupts and exceptions
Non-maskable interrupts: 2 sources
Maskable interrupts:
16 MB linear address space
Memory block allocation function: 2 MB per block
{ External bus: 16-bit multiplexed bus
{ Internal memory:
µPD703038, 703039, 703040, 703041 (51 sources)
µPD703038Y, 703039Y, 703040Y, 703041Y (52
sources)
µPD703038, 703038Y
Software exceptions: 32 sources
Exception trap: 1 source
(ROM: 384 KB, RAM: 16 KB)
µPD703039, 703039Y
{ Serial interface (SIO)
(ROM: 256 KB, RAM: 8 KB)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
3-wire variable-length serial interface (CSI4)
I2C bus interface (I2C) (µPD703039Y, 703040Y,
703041Y)
µPD703040, 703040Y
(ROM: 256 KB, RAM: 16 KB)
µPD703041, 703041Y
(ROM: 192 KB, RAM: 8 KB)
{ I/O lines Total: 151
{ RTP: 8 bits × 2 channels or 4 bits × 4 channels
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U13953EJ2V1DS00 (2nd edition)
Date Published August 2005 NS CP(K)
Printed in Japan
The mark shows major revised points.
© NEC Electronics Corporation 2000
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
{ PWM output: 4 channels
{ Vsync/Hsync separation circuit
{ On-chip key return function
{ On-chip clock generator
{ Power saving function: HALT/IDLE/STOP modes
{ ROM correction: 4 points
{ Package: 176-pin plastic LQFP (24 × 24)
APPLICATIONS
{ Camcorders (including DVC)
ORDERING INFORMATION
Part Number
Package
µPD703038F1-×××-EN2
180-pin plastic FBGA (13 × 13)
µPD703038F1-×××-EN2-A
µPD703038YF1-×××-EN2
µPD703038YF1-×××-EN2-A
µPD703039GM-×××-UEU
µPD703039GM-×××-UEU-A
µPD703039F1-×××- EN2
µPD703039F1-×××- EN2-A
µPD703039YGM-×××-UEU
µPD703039YGM-×××-UEU-A
µPD703039YF1-×××-EN2
µPD703039YF1-×××-EN2-A
µPD703040GM-×××-UEU
µPD703040GM-×××-UEU-A
µPD703040F1-×××-EN2
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
180-pin plastic FBGA (13 × 13)
µPD703040F1-×××-EN2-A
µPD703040YGM-×××-UEU
µPD703040YGM-×××-UEU-A
µPD703040YF1-×××-EN2
µPD703040YF1-×××-EN2-A
µPD703041GM-×××-UEU
µPD703041GM-×××-UEU-A
µPD703041YGM-×××-UEU
µPD703041YGM-×××-UEU-A
180-pin plastic FBGA (13 × 13)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
Remarks1. Products with -A at the end of the part number are lead-free products.
Remarks2. ××× indicates ROM code suffix.
2
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM
Internal RAM
I2C
VPP Pin
None
µPD703038
384 KB (mask ROM)
16 KB
8 KB
None
µPD703038Y
µPD703039
Provided
None
256 KB (mask ROM)
µPD703039Y
µPD703040
Provided
None
16 KB
8 KB
µPD703040Y
µPD703041
Provided
None
192 KB (mask ROM)
384 KB (flash memory)
256 KB (flash memory)
µPD703041Y
µPD70F3038
µPD70F3038Y
µPD70F3040
µPD70F3040Y
Provided
None
16 KB
16 KB
Provided
Provided
None
Provided
3
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN CONFIGURATION
176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703039GM-×××-UEU
µPD703039GM-×××-UEU-A
µPD703039YGM-×××-UEU-A
µPD703040GM-×××-UEU-A
µPD703040YGM-×××-UEU-A
µPD703041GM-×××-UEU-A
µPD703041YGM-×××-UEU-A
µPD703039YGM-×××-UEU
µPD703040GM-×××-UEU
µPD703040YGM-×××-UEU
µPD703041GM-×××-UEU
µPD703041YGM-×××-UEU
P12/SCK0/SCL0Note 2
P13/SI1/RXD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P21/SO2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
P87/ANI15
2
P86/ANI14
3
P85/ANI13
4
P84/ANI12
5
P83/ANI11
6
P82/ANI10
P22/SCK2/SCL1Note 2
P23/SI3/RXD1
P24/SO3/TXD1
P25/SCK3/ASCK1
P26/TI2/TO2
7
P81/ANI9
8
P80/ANI8
9
P77/ANI7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P76/ANI6
P75/ANI5
P27/TI3/TO3
P74/ANI4
V
DD
SS
P73/ANI3
V
P72/ANI2
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P34/TO0
P35/TO1
P36/TI4/TO4
P37/TI5/TO5
P120/SI4
P121/SO4
P122/SCK4
P123/CLO
P124/TI6/TO6
P125/TI7/TO7
P126/TI10/TO10
P127/TI11/TO11
P180
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
P181
P182
V
SS
DD
P183
V
P184
98
P07/INTP6
P185
97
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P186
96
P187
95
V
DD
94
P03/INTP2
VSS
93
P02/INTP1
P190
P191
P192
P193
92
P01/INTP0
91
P00/NMI
90
P157/RTP17
P156/RTP16
89
Notes 1. Connect directly to VSS.
2. SCL0, SCL1, SDA0, and SDA1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
4
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
180-pin plastic FBGA (13 × 13)
µ PD703038F1-×××-EN2
µ PD703038YF1-×××-EN2
µ PD703039F1-×××-EN2
µ PD703039YF1-×××-EN2
µ PD703040F1-×××-EN2
µ PD703040YF1-×××-EN2
µ PD703038F1-×××-EN2-A
µ PD703038YF1-×××-EN2-A
µ PD703039F1-×××-EN2-A
µ PD703039YF1-×××-EN2-A
µ PD703040F1-×××-EN2-A
µ PD703040YF1-×××-EN2-A
Top View
Bottom View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R
R
P N M L K J H G F E D C B A
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Number
Number
Number
C1
Number
A1
A2
NCNote 1
B1
B2
P13/SI1/RXD0
P12/SCK0/SCL0Note 2
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P14/SO1/TXD0
P111
D1
D2
P23/SI3/RXD1
P21/SO2
P11/SO0
P10/SI0/SDA0Note 2
P112
C2
A3
B3
P113
C3
D3
P22/SCK2/SCL1Note 2
P24/SO3/TXD1
WAIT
A4
B4
P110
C4
D4
A5
CLKOUT
P62/A18
P57/AD15
P53/AD11
BVSS
B5
P64/A20
P60/A16
P54/AD12
P50/AD8
P46/AD6
P42/AD2
P94/ASTB
P91/UBEN
AVDD
C5
P65/A21
D5
A6
B6
C6
P63/A19
D6
P61/A17
A7
B7
C7
P56/AD14
P52/AD10
BVDD
D7
P55/AD13
A8
B8
C8
D8
P51/AD9
A9
B9
C9
D9
P47/AD7
A10
A11
A12
A13
A14
A15
P45/AD5
P41/AD1
VSS
B10
B11
B12
B13
B14
B15
C10
C11
C12
C13
C14
C15
P44/AD4
D10
D11
D12
D13
D14
D15
P43/AD3
P40/AD0
P96/HLDRQ
P90/LBEN/WRL
P81/ANI9
P93/DSTB/RD
P82/ANI10
P86/ANI14
P85/ANI13
AVSS
AVREF
NCNote 1
VDD
P84/ANI12
P83/ANI11
P87/ANI15
Notes 1. Leave the NC pin open.
2. SCL0, SCL1, SDA0, and SDA1 are valid only for µPD703038Y, 703039Y, and 703040Y.
5
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Number
Number
Number
Number
E1
E2
P27/TI3/TO3
P25/SCK3/ASCK1
P26/TI2/TO2
VSS
H12
H13
H14
H15
J1
P144/TI9/INTTI9
P143/INTCP93
P146
M1
M2
VDD
P1
P2
P193
P195
P196
P186
E3
M3
P170/KR0
P174/KR4
P177/KR7
P163/PWM3
P167/HSOUT1
RESET
P3
E4
P141/INTCP91
P125/TI7/TO7
P124/TI6/TO6
P126/TI10/TO10
P127/TI11/TO11
P140/INTCP90
P137/TO81
P142/INTCP92
P135/TCLR8/INTTCLR8
P181
M4
P4
P176/KR6
P160/PWM0
P164/CSYNCIN
ICNote 1
E5
VDD
M5
P5
E11
E12
E13
E14
E15
F1
P95/HLDAK
P92/R/W/WRH
P76/ANI6
P77/ANI7
P80/ANI8
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P74/ANI4
P72/ANI2
P75/ANI5
P70/ANI0
P35/TO1
J2
M6
P6
J3
M7
P7
J4
M8
P8
X2
J12
J13
J14
J15
K1
M9
VSS
P9
P100/RTP00
P104/RTP04
P107/RTP07
P150/RTP10
P152/RTP12
P153/RTP13
P156/RTP16
NCNote 2
M10
M11
M12
M13
M14
M15
N1
P103/RTP03
P01/INTP0
P04/INTP3
P05/INTP4/ADTRG
P03/INTP2
P06/INTP5/RTPTRG0
P191
P10
P11
P12
P13
P14
P15
R1
F2
F3
F4
K2
P180
F12
F13
F14
F15
G1
K3
P182
K4
P183
K12
K13
K14
K15
L1
P134/TI8/INTTI8
P133/INTCP83
P136/TO80
P132/INTCP82
P185
N2
P192
R2
P194
N3
P197
R3
P171/KR1
P172/KR2
P161/PWM1
P165/VSOUT
XT1
N4
P173/KR3
P175/KR5
P162/PWM2
P166/HSOUT0
VDD
R4
G2
P34/TO0
N5
R5
G3
P36/TI4/TO4
P37/TI5/TO5
P73/ANI3
P147
N6
R6
G4
L2
P184
N7
R7
G12
G13
G14
G15
H1
L3
P187
N8
R8
XT2
L4
VSS
N9
X1
R9
P101/RTP01
P105/RTP05
VSS
P71/ANI1
P145/RTPTRG1
P121/SO4
P120/SI4
L5
P190
N10
N11
N12
N13
N14
N15
P102/RTP02
P106/RTP06
VDD
R10
R11
R12
R13
R14
R15
L11
L12
L13
L14
L15
VDD
VSS
P151/RTP11
P154/RTP14
P155/RTP15
NCNote 2
H2
P07/INTP6
P131/INTCP81
P130/INTCP80
P157/RTP17
P00/NMI
H3
P122/SCK4
P123/CLO
H4
P02/INTP1
Notes 1. Connect the IC pin directly to VSS.
2. Leave the NC pin open.
•
6
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
PIN IDENTIFICATION
A16 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI15:
ASCK0, ASCK1:
ASTB:
Address bus
P110 to P113:
P120 to P127:
P130 to P137:
P140 to P147:
P150 to P157:
P160 to P167:
P170 to P177:
P180 to P187:
P190 to P197:
PWM0 to PWM3:
RD:
Port 11
Address/data bus
AD trigger input
Port 12
Port 13
Analog input
Port 14
Asynchronous serial clock
Address strobe
Port 15
Port 16
AVDD:
Analog power supply
Analog reference voltage
Analog ground
Port 17
AVREF:
Port 18
AVSS:
Port 19
BVDD:
Bus interface power supply
Bus interface ground
Clock output
Pulse width modulation
Read
BVSS:
CLKOUT:
CLO:
RESET:
Reset
Clock output (divided)
Csync input
RTP00 to RTP07,:
RTP10 to RTP17
Real-time output port
CSYNCIN:
DSTB:
Data strobe
RTPTRG0, RTPTRG1: RTP trigger input
HLDAK:
HLDRQ:
Hold acknowledge
Hold request
R/W:
Read/write status
Receive data
Serial clock
Serial clock
Serial data
RXD0, RXD1:
SCK0 to SCK4:
SCL0, SCL1:
SDA0, SDA1:
SI0 to SI4:
SO0 to SO4:
TCLR8:
HSOUT0, HSOUT1: Hsync output
IC:
Internally connected
INTCP80 to INTPC83,: Interrupt request from peripherals
INTCP90 to INTCP93,
INTP0 to INTP6,
INTTCLR8,
Serial input
Serial output
Timer clear
INTTI8, INTTI9
TI000, TI001, TI010,: Timer input
TI011, TI2 to TI11
KR0 to KR7:
LBEN:
Key return
Lower byte enable
TO0 to TO7, TO80,: Timer output
TO81, TO10, TO11
NMI:
Non-maskable interrupt request
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P87:
P90 to P96:
P100 to P107:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
TXD0,TXD1:
UBEN:
VDD:
Transmit data
Upper byte enable
Power supply
VSOUT:
VSS:
Vsync output
Ground
WAIT:
Wait
WRH:
Write strobe high level data
Write strobe low level data
Crystal for main system clock
Crystal for subsystem clock
WRL:
X1, X2:
XT1, XT2:
7
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
ROM
CPU
INTC
HLDRQ
HLDAK
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
Instruction
queue
ROM correction
PC
Note 1
ASTB
INTTI8, INTTI9
TI000, TI001,
32-bit barrel
shifter
Timer/counter
16-bit timers:
TM0, TM1
8-bit timers:
TM2 to TM7,
TM10, TM11
24-bit timers:
TM8, TM9
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
Multiplier
16 × 16 → 32
TI010, TI011
TO0, TO1
System
registers
BCU
RAM
TO80, TO81
TI8, TI9
ALU
General registers
32 bits × 32
TCLR8
Note 2
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CSYNCIN
Vsync/Hsync
SIO
HSOUT0, HSOUT1,
VSOUT
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
CSI0/I2C0Note 4
CSI2/I2C1Note 4
CSI1/UART0
CSI3/UART1
CLKOUT
Ports
A/D
converter
CLO
X1
X2
XT1
XT2
RESET
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
CG
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
V
V
BVDD
BVSS
IC
DD
SS
Variable-
length CSI4
SI4
SCK4
Watch timer
KR0 to KR7
Key return function
DMAC: 6 ch
PWM
Watchdog timer
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTP
PWM0 to PWM3
RTPTRG1
Notes 1. µPD703038, 703038Y: 384 KB
µPD703039, 703039Y, 703040, 703040Y: 256 KB
µPD703041, 703041Y: 192 KB
2. µPD703039, 703039Y, 703041, 703041Y: 8 KB
µPD703038, 703038Y, 703040, 703040Y: 16 KB
3. SDA0, SDA1, SCL0, and SCL1 are valid for the µPD703038Y, 703039Y, 703040Y, and 703041Y only.
4. The I2C function is valid for the µPD703038Y, 703039Y, 703040Y, and 703041Y only.
8
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................10
1.1 Port Pins..................................................................................................................................................10
1.2 Non-Port Pins...........................................................................................................................................14
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins .......................17
2. ELECTRICAL SPECIFICATIONS ......................................................................................................21
3. PACKAGE DRAWING........................................................................................................................43
4. RECOMMENDED SOLDERING CONDITIONS................................................................................45
Data Sheet U13953EJ2V1DS00
9
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1. PIN FUNCTIONS
1.1 Port Pins
(1/4)
Pin Name
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
I/O
I/O
PULL
Yes
Function
Alternate Function
Port 0
8-bit I/O port
NMI
INTP0
Input/output mode can be specified in 1-bit units.
INTP1
INTP2
INTP3
INTP4/ADTRG
INTP5/RTPTRG0
INTP6
I/O
I/O
Yes
Yes
Port 1
6-bit I/O port
SI0/SDA0
SO0
Input/output mode can be specified in 1-bit units.
SCK0/SCL0
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
Port 2
8-bit I/O port
Input/output mode can be specified in 1-bit units.
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2
TI3/TO3
TI000
I/O
Yes
Port 3
8-bit I/O port
TI001
Input/output mode can be specified in 1-bit units.
TI010
TI011
TO0
TO1
TI4/TO4
TI5/TO5
AD0
I/O
No
Port 4
8-bit I/O port
AD1
Input/output mode can be specified in 1-bit units.
AD2
AD3
AD4
Remark PULL: On-chip pull-up resistor
10
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/4)
Pin Name
P45
I/O
I/O
PULL
No
Function
Alternate Function
Port 4
AD5
8-bit I/O port
Input/output mode can be specified in 1-bit units.
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
AD6
AD7
I/O
No
Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A16
I/O
No
No
Port 6
6-bit I/O port
Input/output mode can be specified in 1-bit units.
A17
A18
A19
A20
A21
Input
Port 7
8-bit input port
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Input
No
Port 8
8-bit input port
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
LBEN/WRL
UBEN
R/W/WRH
DSTB/RD
I/O
No
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark PULL: On-chip pull-up resistor
Data Sheet U13953EJ2V1DS
11
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/4)
Pin Name
P94
I/O
I/O
PULL
No
Function
Alternate Function
Port 9
ASTB
7-bit I/O port
Input/output mode can be specified in 1-bit units.
P95
HLDAK
HLDRQ
RTP00
RTP01
RTP02
RTP03
RTP04
RTP05
RTP06
RTP07
P96
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P120
P121
P122
P123
P124
P125
P126
P127
P130
P131
P132
P133
P134
P135
P136
P137
P140
P141
P142
P143
P144
P145
P146
P147
I/O
Yes
Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
I/O
I/O
No
No
Port 11
4-bit I/O port
Input/output mode can be specified in 1-bit units.
–
–
–
–
Port 12
8-bit I/O port
Input/output mode can be specified in 1-bit units.
SI4
SO4
SCK4
CLO
TI6/TO6
TI7/TO7
TI10/TO10
TI11/TO11
INTCP80
INTCP81
INTCP82
INTCP83
TI8/INTTI8
TCLR8/INTTCLR8
TO80
I/O
No
Port 13
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TO81
I/O
No
Port 14
8-bit I/O port
Input/output mode can be specified in 1-bit units.
INTCP90
INTCP91
INTCP92
INTCP93
TI9/INTTI9
RTPTRG1
–
–
Remark PULL: On-chip pull-up resistor
12
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(4/4)
Pin Name
P150
I/O
I/O
PULL
No
Function
Alternate Function
Port 15
RTP10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
P151
P152
P153
P154
P155
P156
P157
P160
P161
P162
P163
P164
P165
P166
P167
P170
P171
P172
P173
P174
P175
P176
P177
P180
P181
P182
P183
P184
P185
P186
P187
P190
P191
P192
P193
P194
P195
P196
P197
RTP11
RTP12
RTP13
RTP14
RTP15
RTP16
RTP17
PWM0
PWM1
PWM2
PWM3
CSYNCIN
VSOUT
HSOUT0
HSOUT1
KR0
I/O
I/O
I/O
I/O
No
Yes
No
Port 16
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Port 17
8-bit I/O port
Input/output mode can be specified in 1-bit units.
KR1
KR2
KR3
KR4
KR5
KR6
KR7
Port 18
8-bit I/O port
Input/output mode can be specified in 1-bit units.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
No
Port 19
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark PULL: On-chip pull-up resistor
Data Sheet U13953EJ2V1DS
13
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.2 Non-Port Pins
(1/3)
Pin Name
A16 to A21
AD0 to AD7
AD8 to AD15
ADTRG
I/O
Output
I/O
PULL
No
Function
Alternate Function
Address bus 16 to 21
P60 to P65
P40 to P47
P50 to P57
P05/INTP4
P70 to P77
P80 to P87
P15/SCK1
P25/SCK3
P94
No
Address/data multiplexed bus 0 to 15
Input
Input
Input
Input
Yes
No
A/D converter external trigger input
Analog input to A/D converter
ANI0 to ANI7
ANI8 to ANI15
ASCK0
No
Yes
Baud rate clock input for UART0 and UART1
ASCK1
ASTB
Output
–
No
–
External address strobe signal output
AVDD
Positive power supply for A/D converter and ports used for
alternate functions
–
AVREF
AVSS
Input
–
–
–
Reference voltage input for A/D converter
–
–
Ground potential for A/D converter and ports used for alternate
functions
BVDD
BVSS
–
–
–
–
Positive power supply for bus interface and ports used for
alternate functions
–
–
Ground potential for bus interface and ports used for alternate
functions
CLKOUT
CLO
Output
Output
Input
–
Internal system clock output
CLO output signal
–
P123
No
No
No
No
No
No
CSYNCIN
DSTB
Csync signal input
P164
Output
Output
Input
External data strobe signal output
Bus hold acknowledge output
Bus hold request input
P93/RD
P95
HLDAK
HLDRQ
HSOUT0
HSOUT1
IC
P96
Output
Hsync signal output before revision
Hsync signal output after revision
Internal connection (connect directly to VSS)
External capture input for CC80 to CC83
P166
P167
–
–
–
INTCP80 to
INTCP83
Input
No
P130 to P133
INTCP90 to
INTCP93
Input
Input
No
External capture input for CP90 to CP93
P140 to P143
INTP0 to INTP3
INTP4
Yes
External interrupt request input (analog noise elimination)
External interrupt request input (digital noise elimination)
P01 to P04
P05/ADTRG
P06/RTPTRG0
P07
INTP5
INTP6
External interrupt request input (digital noise elimination
supporting remote controller)
Remark PULL: On-chip pull-up resistor
14
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2/3)
Pin Name
INTTCLR8
INTTI8
I/O
PULL
No
Function
Alternate Function
P135/TCLR8
P134/TI8
P144/TI9
P170 to P177
P90/WRL
P00
Input
Input
External interrupt request input (digital noise elimination)
No
INTTI9
KR0 to KR7
LBEN
Input
Output
Input
Yes
No
Yes
No
No
–
Key return input
Lower byte enable signal output for external data bus
Non-maskable interrupt request input
Output of PWM channels 0 to 3
Bus read strobe signal output
System reset input
NMI
PWM0 to PWM3 Output
P160 to P163
P93/DSTB
–
RD
Output
Input
RESET
RTP00 to RTP07 Output
RTP10 to RTP17
Yes
No
Yes
No
No
Yes
Real-time output port
P100 to P107
P150 to P157
P06
RTPTRG0
RTPTRG1
R/W
Input
RTP external trigger input
P145
Output
Input
External read/write status output
P92/WRH
P13/SI1
RXD0
RXD1
SCK0
SCK1
SCK2
SCK3
SCK4
SCL0
SCL1
SDA0
SDA1
SI0
Serial receive data input for UART0 and UART1
P23/SI3
I/O
Yes
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
P12/SCL0
P15/ASCK0
P22/SCL1
P25/ASCK1
P122
No
Variable-length CSI4 serial clock I/O
Serial clock I/O for I2C0 and I2C1
(µPD703038Y, 703039Y, 703040Y and 703041Y)
I/O
I/O
Yes
P12/SCK0
P22/SCK2
P10/SI0
Yes
Yes
Serial transmit/receive data I/O for I2C0 and I2C1
(µPD703038Y, 703039Y, 703040Y and 703041Y)
P20/SI2
Input
Serial receive data input for CSI0 to CSI3 (3-wire mode)
P10/SDA0
P13/RXD0
P20/SDA1
P23/RXD1
P120
SI1
SI2
SI3
SI4
No
Variable-length CSI4 serial receive data input
Serial transmit data output for CSI0 to CSI3
SO0
Output
Yes
P11
SO1
P14/TXD0
P21
SO2
SO3
P24/TXD1
P121
SO4
No
No
Variable-length CSI4 serial transmit data output
External clear input for TM8
TCLR8
TI000
Input
Input
P135/INTTCLR8
P30
Yes
External count clock input/external capture trigger input for TM0
Remark PULL: On-chip pull-up resistor
Data Sheet U13953EJ2V1DS
15
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(3/3)
Pin Name
TI001
I/O
PULL
Yes
Function
External capture trigger input for TM0
External count clock input/external capture trigger input for TM1
External capture trigger input for TM1
External count clock input for TM2
External count clock input for TM3
External count clock input for TM4
External count clock input for TM5
External count clock input for TM6
External count clock input for TM7
External count clock input for TM8
External count clock input for TM9
External count clock input for TM10
External count clock input for TM11
Pulse signal output for TM0
Alternate Function
P31
Input
TI010
TI011
TI2
P32
P33
P26/TO2
P27/TO3
P36/TO4
P37/TO5
P124/TO6
P125/TO7
P134/INTTI8
P144/INTTI9
P126/TO10
P127/TO11
P34
TI3
TI4
TI5
TI6
No
TI7
TI8
TI9
TI10
TI11
TO0
TO1
TO2
TO3
TO4
TO5
TO6
TO7
TO80
TO81
TO10
TO11
TXD0
TXD1
UBEN
VDD
Output
Yes
Pulse signal output for TM1
P35
Pulse signal output for TM2
P26/TI2
P27/TI3
P36/TI4
P37/TI5
P124/TI6
P125/TI7
P136
Pulse signal output for TM3
Pulse signal output for TM4
Pulse signal output for TM5
No
Pulse signal output for TM6
Pulse signal output for TM7
Pulse signal output 0 for TM8
Pulse signal output 1 for TM8
P137
Pulse signal output for TM10
P126/TI10
P127/TI11
P14/SO1
P24/SO3
P91
Pulse signal output for TM11
Output
Yes
Serial transmit data output for UART0 and UART1
Output
–
No
–
Higher byte enable signal output for external data bus
Positive power supply pin
–
VSOUT
VSS
Output
–
No
–
Vsync signal output
P165
Ground potential
–
WAIT
WRH
WRL
X1
Input
Output
–
External WAIT signal input
–
No
Higher byte write strobe signal output for external data bus
Lower byte write strobe signal output for external data bus
Resonator connection for main system clock
P92/R/W
P90/LBEN
–
Input
–
–
–
X2
–
XT1
XT2
Input
–
Resonator connection for subsystem clock
–
–
Remark PULL: On-chip pull-up resistor
16
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins
Table 1-1 shows the I/O circuit type of each pin and the recommended connection of unused pins.
For the I/O circuit configuration of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Recommended Connection Method
Power Supply
P00
NMI
5-W
VDD
Input:
Independently connect to VDD or VSS
via a resistor
P01 to P04
P05
INTP0 to INTP3
INTP4/ADTRG
INTP5/RTPTRG0
INTP6
Output: Leave open
P06
P07
P10
SI0/SDA0
SO0
10-F
10-E
10-F
5-W
10-E
10-F
10-F
10-E
10-F
5-W
10-E
10-F
5-W
5-W
VDD
P11
P12
SCK0/SCL0
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2/SDA1
SO2
P13
P14
P15
P20
VDD
P21
P22
SCK2/SCL1
SI3/RXD1
SO3/TXD1
SCK3/ASCK1
TI2/TO2, TI3/TO3
TI000, TI001
TI010, TI011
TO0, TO1
TI4/TO4
P23
P24
P25
P26, P27
P30, P31
P32, P33
P34, P35
P36
VDD
5-A
5-W
P37
TI5/TO5
P40 to P47
P50 to P57
P60 to P65
P70 to P77
P80 to P87
P90
AD0 to AD7
AD8 to AD15
A16 to A21
ANI0 to ANI7
ANI8 to ANI15
LBEN/WRL
UBEN
5
5
5
9
9
5
BVDD
BVDD
BVDD
AVDD
AVDD
BVDD
Input:
Independently connect to BVDD or BVSS
via a resistor
Output: Leave open
Connect to AVSS
Input:
Independently connect to BVDD or BVSS
via a resistor
Output: Leave open
P91
P92
R/W/WRH
DSTB/RD
ASTB
P93
P94
P95
HLDAK
P96
HLDRQ
P100 to P107
P110 to P113
P120
RTP00 to RTP07
–
10-E
5
VDD
VDD
VDD
Input:
Independently connect to VDD or VSS
via a resistor
Output: Leave open
SI4
5-K
Data Sheet U13953EJ2V1DS
17
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Table 1-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Recommended Connection Method
Power Supply
P121
P122
P123
P124
P125
P126
P127
SO4
10-G
VDD
Input:
Independently connect to VDD or VSS
via a resistor
SCK4
10-H
5
Output: Leave open
CLO
TI6/TO6
5-K
TI7/TO7
TI10/TO10
TI11/TO11
P130 to P133
P134
INTCP80 to INTCP83
5-K
VDD
TI8/INTTI8
P135
TCLR8/INTTCLR8
P136, P137
P140 to P143
P144
TO80, TO81
5
INTCP90 to INTCP93
5-K
VDD
TI9/INTTI9
P145
RTPTRG1
P146, P147
P150 to P157
P160 to P163
P164
–
5
RTP10 to RTP17
5
VDD
PWM0 to PWM3
5
VDD
CSYNCIN
5-K
5
P165
VSOUT
P166
HSOUT0
P167
HSOUT1
P170 to P177
P180 to P187
P190 to P197
CLKOUT
WAIT
KR0 to KR7
5-K
5
VDD
VDD
VDD
BVDD
BVDD
VDD
VDD
VDD
VDD
VDD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
4
Leave open
Connect to VDD via a resistor
–
1
RESET
X1
2
–
–
–
X2
Leave open
Connect to VSS
Leave open
Connect to AVSS
Connect directly to VSS
–
XT1
16-A
16-A
XT2
AVREF
–
–
–
–
–
–
–
–
IC
–
VDD
–
VSS
–
–
AVDD
–
Connect to VDD
Connect to VSS
Connect to VDD
Connect to VSS
AVSS
–
BVDD
–
BVSS
–
18
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin I/O Circuits (1/2)
Type 1
Type 5
V
DD
V
DD
Data
P-ch
P-ch
IN/OUT
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 5-A
V
DD
Pullup
enable
P-ch
VDD
Data
P-ch
N-ch
IN
IN/OUT
Output
disable
Input
Schmitt-triggered input with hysteresis characteristics
Type 4
enable
Type 5-K
V
DD
V
DD
Data
P-ch
N-ch
Data
P-ch
IN/OUT
OUT
Output
disable
Output
disable
N-ch
Input
enable
Push-pull output that can be set for high impedance output
(both P-ch and N-ch are off)
Data Sheet U13953EJ2V1DS
19
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Figure 1-1. Pin I/O Circuits (2/2)
Type 5-W
Type 10-G
Data
V
DD
V
DD
Pullup
enable
P-ch
P-ch
VDD
IN/OUT
Data
P-ch
Open drain
N-ch
Output
disable
IN/OUT
Output
disable
N-ch
Input
enable
Input
enable
Type 9
Type 10-H
Data
V
DD
P-ch
N-ch
P-ch
N-ch
Comparator
+
–
IN
IN/OUT
Open drain
Output
V
REF (Threshold voltage)
disable
Input enable
Input
enable
Type 10-E
Type 16-A
V
DD
Pullup
enable
P-ch
V
DD
Data
P-ch
IN/OUT
Open
Output
disable
N-ch
XT1
XT2
Input
enable
Type 10-F
V
DD
Pullup
enable
P-ch
VDD
Data
P-ch
IN/OUT
Open
Output
N-ch
disable
Input
enable
20
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
Unit
V
–0.5 to +4.6
AVDD
BVDD
VSS
–0.5 to +4.6
V
–0.5 to +4.6
V
–0.5 to +0.5
V
AVSS
BVSS
VI1
–0.5 to +0.5
V
–0.5 to +0.5
–0.5 to VDD + 0.5Note 4
–0.5 to BVDD + 0.5Note 4
V
Input voltage
Note 1, RESET (VDD)
V
VI2
Note 2, WAIT (BVDD)
V
Clock input voltage
VK
X1, VDD = 2.7 to 3.6 V
–0.5 to VDD + 1.0Note 4
–0.5 to AVDD + 0.5Note 4
–0.5 to AVDD + 0.5Note 4
Analog input voltage
Analog reference input voltage
Output current, low
VIAN
AVREF
IOL
Note 3 (AVDD)
V
AVREF pin
V
Per pin
4.0
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
Total for P00 to P07, P150 to P157
Total for P100 to P107, P160 to P167
Total for P170 to P177, P190 to P197
Total for P124 to P127, P180 to P187
Total for P30 to P37, P120 to P123
Total for P12 to P15, P20 to P27, P110 to
P113
Total for P50 to P57, P60 to P65, CLKOUT
Total for P40 to P47, P90 to P96
Total for P130 to P137, P140 to P147
Per pin
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25
Output current, high
IOH
–4.0
–25
–25
–25
–25
–25
–25
Total for P00 to P07, P150 to P157
Total for P100 to P107, P160 to P167
Total for P170 to P177, P190 to P197
Total for P124 to P127, P180 to P187
Total for P30 to P37, P120 to P123
Total for P12 to P15, P20 to P27, P110 to
P113
Total for P50 to P57, P60 to P65, CLKOUT
Total for P40 to P47, P90 to P96
Total for P130 to P137, P140 to P147
Note 1, VDD = 2.7 to 3.6 V
–25
–25
mA
mA
mA
V
–25
Output voltage
VO1
VO2
TA
–0.5 to VDD + 0.5Note 4
–0.5 to BVDD + 0.5Note 4
–40 to +85
Note 2, CLKOUT, BVDD = 2.7 to 3.6 V
V
Operating ambient temperature
Storage temperature
°C
°C
Tstg
–65 to +150
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 (includes alternate function pins)
2. Ports 4, 5, 6, and 9 (includes alternate function pins)
Data Sheet U13953EJ2V1DS
21
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3. Ports 7 and 8 (includes alternate function pins)
4. Be sure not to exceed each absolute maximum rating (MAX.).
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or Vcc
and GND. However, direct connections among open-drain and open-collector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output contention with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C, VDD = AVDD = BVDD = VSS = AVSS = BVSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
(1) CPU operating frequency
Parameter
Symbol
Conditions
MIN.
0.5
TYP.
MAX.
16
Unit
MHz
MHz
CPU operating frequency
fCPU
V
DD = 2.7 to 3.6 V
DD = 3.1 to 3.6 V
0.5
20
V
(2) Operating frequency for each supply voltage
Operating Frequency
4 MHz ≤ fXX ≤ 16 MHz
Supply Voltage (VDD = AVDD = BVDD)
2.7 to 3.6 V
3.1 to 3.6 V
2.7 to 3.6 V
4 MHz ≤ fXX ≤ 20 MHz
fXT = 32.768 kHz (watch operation only)
22
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Recommended Oscillator
(1) Main clock oscillator (TA = −40 to +85°C)
(a) Ceramic oscillator or crystal resonator connection
X2
X1
Parameter
Symbol
Conditions
VDD = 2.7 to 3.6 V
MIN.
TYP.
MAX.
16
Unit
MHz
MHz
s
Oscillation frequency
fXX
4
4
VDD = 3.1 to 3.6 V
20
Oscillation stabilization
time
After reset release
After STOP mode release
219/fXX
Note
s
Note Values vary depending on the settings of the oscillation stabilization time selection register (OSTS).
Remarks 1. Place the oscillator as close as possible to X1 and X2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
16
Unit
MHz
MHz
Input frequency
fXX
VDD = 2.7 to 3.6 V
VDD = 3.1 to 3.6 V
4
4
20
Cautions 1. Place the high-speed CMOS inverter as close as possible to the X1 pin.
2. Perform a sufficient evaluation to determine whether the µPD703038, 703038Y, 703039,
703039Y, 703040, 703040Y, 703041, or 703041Y matches the high-speed CMOS inverter.
Data Sheet U13953EJ2V1DS
23
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2) Subclock oscillator (TA = −40 to +85°C)
XT1
XT2
Parameter
Symbol
Conditions
MIN.
32
TYP.
32.768
10
MAX.
35
Unit
kHz
s
Oscillation frequency
Oscillation stabilization time
fXT
VDD = 2.7 to 3.6 V
Remarks 1. Place the oscillator as close as possible to XT1 and XT2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
24
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
DC Characteristics
(1) 16 MHz operation
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
VIH1
VIH2
VIH3
VIH4
VIH5
VIL1
Conditions
Pins in Note 1 , WAIT
MIN.
0.7BVDD
0.7VDD
0.75VDD
0.7AVDD
0.8VDD
BVSS
TYP.
MAX.
BVDD
Unit
V
Input voltage, high
Pins in Note 2
Pins in Note 3, RESET
Pins in Note 4
X1
VDD
V
VDD
V
AVDD
V
VDD
V
Input voltage, low
Pins in Note 1 , WAIT
Pins in Note 2
Pins in Note 3, RESET
Pins in Note 4
X1
0.3BVDD
0.3VDD
0.2VDD
0.3AVDD
0.2VDD
V
VIL2
VSS
V
VIL3
VSS
V
VIL4
AVSS
V
VIL5
VSS
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
Note 1, CLKOUT
Notes 2, 3
IOH = –3 mA
0.8BVDD
0.8VDD
V
IOH = –1 mA
IOL = 1.6 mA
IOL = 1.6 mA
V
Note 1, CLKOUT
0.4
0.4
V
Notes 2, 3 (except
V
P10, P12, P20, P22)
VOL3
ILIH1
ILIH2
ILIL1
ILIL2
ILOH
ILOL
IDD1
IDD2
IDD3
IDD4
P10, P12, P20, P22
IOL = 3 mA
Other than X1
X1
0.4
5
V
Input leakage current, high
Input leakage current, low
VI = VDD = AVDD =
BVDD
µA
µA
µA
µA
µA
µA
mA
mA
mA
µA
20
–5
–20
5
VI = 0 V
Other than X1
X1
Output leakage current, high
Output leakage current, low
Supply currentNote 5
VO = VDD = AVDD = BVDD
VO = 0 V
–5
40
27
4
Normal operation mode (fXX = 16 MHz)
HALT mode (fXX = 16 MHz)
IDLE mode (fXX = 16 MHz)
22
13
1.2
10
STOP mode (subclock operation: fXT = 32.768
kHz, watch timer operation)
70
STOP mode (subclock stopped, XT1 = VSS)
VIN = 0 V
1
60
µA
kΩ
Pull-up resistor
RL
10
30
100
Notes 1. Ports 4, 5, 6, and 9 (includes alternate function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,
P150 to P157, P160 to P163, P165 to P167, P180 to P187, and P190 to P197 (includes alternate
function pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, and P170 to P177 (includes alternate function pins)
4. Ports 7 and 8 (includes alternate function pins)
Caution The typical values listed are those when VDD = 3.3 V. The current that is consumed at output
buffers is not included.
Data Sheet U13953EJ2V1DS
25
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
(2) 20 MHz operation
(TA = –40 to +85°C, VDD = AVDD = BVDD = 3.1 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter
Symbol
Conditions
Pins in Note 1 , WAIT
MIN.
TYP.
MAX.
Unit
VIH1
VIH2
VIH3
VIH4
0.7BVDD
0.7VDD
BVDD
VDD
V
V
V
V
Input voltage, high
Pins in Note 2
Pins in Note 3, RESET
0.75VDD
0.7AVDD
VDD
AVDD
Pins in Note 4
X1
VIH5
VIL1
0.8VDD
BVSS
VSS
VDD
V
V
V
V
V
V
V
V
V
V
Input voltage, low
Pins in Note 1 , WAIT
Pins in Note 2
Pins in Note 3, RESET
Pins in Note 4
X1
0.3BVDD
0.3VDD
0.2VDD
0.3AVDD
0.2VDD
VIL2
VIL3
VSS
VIL4
AVSS
VSS
VIH5
VOH1
VOH2
VOL1
VOL2
Output voltage, high
Output voltage, low
Note 1, CLKOUT
Notes 2, 3
IOH = −3 mA
IOH = −1 mA
IOL = 1.6 mA
0.8BVDD
0.8VDD
Note 1, CLKOUT
0.4
0.4
Notes 2, 3 (except P10, IOL = 1.6 mA
P12, P20, P22)
VOL3
ILIH1
ILIH2
ILIL1
ILIL2
ILOH
P10, P12, P20, P22 IOL = 3 mA
0.4
5
V
Input leakage current,
high
VI = VDD = AVDD =
BVDD
Other than X1
µA
µA
µA
µA
µA
X1
20
−5
−20
5
Input leakage current, low
VI = 0 V
Other than X1
X1
Output leakage current,
VO = VDD = AVDD = BVDD
VO = 0 V
high
Output leakage current,
low
ILOL
−5
µA
Supply current
IDD1
IDD2
IDD3
IDD4
Normal operation mode (fXX = 20 MHz)
HALT mode (fXX = 20 MHz)
IDLE mode (fXX = 20 MHz)
STOP mode (subclock operation: fXT =
32.768 kHz, watch timer operation)
STOP mode (subclock stopped,
XT1 = VSS)
25
14
1.4
10
45
30
4.5
70
mA
mA
mA
µA
1
60
µA
kΩ
Pull-up resistor
RL
VIN = 0 V
10
30
100
Notes 1. Ports 4, 5, 6, and 9 (includes alternate function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147,
P150 to P157, P160 to P163, P165 to P167, P180 to P187, and P190 to P197 (includes alternate
function pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, and P170 to P177 (includes alternate function pins)
4. Ports 7 and 8 (includes alternate function pins)
Caution The typical values listed are those when VDD = 3.3 V. The current that is consumed at output
buffers is not included.
26
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Data Retention Characteristics
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Data retention voltage
Data retention current
Supply voltage rise time
Supply voltage fall time
Symbol
VDDDR
IDDDR
tRVD
Conditions
STOP mode
MIN.
1.8
TYP.
MAX.
3.6
Unit
V
VDDDR [V], XT1 = VSS
1
60
µA
µs
200
200
0
tFVD
µs
Supply voltage hold time
(from STOP mode setting)
tHVD
ms
STOP release signal input time
tDREL
VIHDR
VILDR
0
VIHn
0
ms
V
Data retention high-level input voltage
Data retention low-level input voltage
All input ports
All input ports
VDDDR
VILn
V
Remark n = 1 to 5
Setting STOP mode
2.7 V
t
FVD
t
RVD
V
DD
V
DDDR
t
HVD
t
DREL
VIHDR
RESET (input)
VIHDR
STOP release interrupt (NMI, etc.)
(when STOP mode is released
at falling edge)
STOP release interrupt (NMI, etc.)
(when STOP mode is released
at rising edge)
V
ILDR
Cautions 1. Be sure to shift to and return from STOP mode when VDD is 2.7 V or higher (when FXX = 16
MHz) and VDD = 3.1 V or higher (when FXX = 20 MHz).
2. VDD = 2.7 V is the lowest operation voltage (when FXX = 16 MHz) of the V850/SV1.
Data Sheet U13953EJ2V1DS
27
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
AC Characteristics
AC test input measurement points (VDD, BVDD, AVDD)
V
DD
V
IH
IL
V
IH
Measurement
points
V
V
IL
0 V
AC test output measurement points (BVDD)
V
V
OH
OL
V
OH
Measurement
points
V
OL
Load conditions
DUT
(Device Under Test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
28
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Clock Timing
(1) 16 MHz operation
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
X1 input cycle
Symbol
Conditions
MIN.
62.5
28.2
31.2
MAX.
250
Unit
ns
tCYX
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
X1 input high-level width
X1 input low-level width
X1 input rise time
tWXH
tWXL
tXR
ns
ns
ns
0.5(<1> – <2> – <3>)
0.5(<1> – <2> – <3>)
2 µs
X1 input fall time
tXF
ns
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
tCYK
tWKH
tWKL
tKR
62.5 ns
0.4tCYK − 10
0.4tCYK − 10
ns
ns
ns
ns
10
10
CLKOUT fall time
tKF
Remark T = tCYK
(2) 20 MHz operation
(TA = –40 to +85°C, VDD = AVDD = BVDD = 3.1 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
X1 input cycle
Symbol
Conditions
MIN.
50.0
22.5
22.5
MAX.
250
Unit
ns
tCYX
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
X1 input high-level width
X1 input low-level width
X1 input rise time
tWXH
tWXL
tXR
ns
ns
ns
0.5(<1> – <2> – <3>)
0.5(<1> – <2> – <3>)
2 µs
X1 input fall time
tXF
ns
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
tCYK
tWKH
tWKL
tKR
50 ns
0.4tCYK − 10
0.4tCYK − 10
ns
ns
ns
ns
10
10
CLKOUT fall time
tKF
Data Sheet U13953EJ2V1DS
29
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Clock Timing
<1>
<2>
<3>
X1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
<10>
Output Timing of Pins Other Than CLKOUT, P4, P5, P6, and P9
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Output rise time
Output fall time
Symbol
<11>
<12>
Conditions
MIN.
MAX.
20
Unit
ns
tOR
tOF
20
ns
<11>
<12>
Output signal
30
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float delay time from DSTB↓
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
tSAST
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<36>
<37>
<38>
<39>
<40>
0.5T – 20
0.5T – 15
tHSTA
tFDA
2
tSAID
(2 + n)T – 30
(1 + n)T – 30
tSDID
tDSTD
0.5T – 15
0
tHDID
tDDA
(1 + i)T – 15
0.5T – 15
(1.5 + i)T – 15
(1 + n)T – 15
T – 15
tDDST1
tDDST2
tWDL
ASTB high-level width
tWSTH
tDDOD
tSODD
tHDOD
tSAWT1
tSAWT2
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
tHSTWT1
tHSTWT2
tWHQH
tWHAL
tDHAC
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
15
(1 + n)T – 20
T – 15
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
1.5T – 30
(1 + n)T – 30
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
(0.5 + n)T
(1.5 + n)T
T – 25
(1 + n)T – 25
nT + 5
(1 + n)T + 5
T + 10
T – 15
0
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
tDHQHA1
tDHQHA2
(2n + 7.5)T + 25
1.5T + 25
0.5T
Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The specifications described above are the values of when a clock with a duty ratio of 1:1 is input
from X1.
Data Sheet U13953EJ2V1DS
31
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
0
MAX.
19
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address delay time from CLKOUT↑
Address float delay time from CLKOUT↑
Delay time from CLKOUT↓ to ASTB↓
Delay time from CLKOUT↑ to DSTB↑
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Data output delay time from CLKOUT↑
WAIT setup time (to CLKOUT↓)
tDKA
<41>
<42>
<43>
<44>
<45>
<46>
<47>
<48>
<49>
<50>
<51>
<52>
<53>
tFKA
tDKST
tDKD
–12
–12
–5
7
14
tSIDK
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKF
15
5
19
15
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
Float delay time from CLKOUT↑
Delay time from CLKOUT↑ to HLDAK
15
5
19
19
tDKHA
Remark The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from
X1.
32
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output), Note
<16>
<45> <46>
Data
<42>
Hi-Z
AD0 to AD15 (I/O)
ASTB (output)
Address
<43>
<43>
<14>
<13>
<19>
<24>
<44>
<18>
<21>
<15>
<17>
<20>
<22>
<44>
DSTB (output),
RD (output)
<23>
<48> <49>
<32> <48> <49>
<34>
<33>
<35>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Data Sheet U13953EJ2V1DS
33
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output), Note
<47>
AD0 to AD15 (I/O)
ASTB (output)
Address
<43>
Data
<43>
<13>
<14>
<24>
<21>
<44>
<18>
<44>
<25>
<26>
<27>
DSTB (output),
WRL (output),
WRH (output)
<23>
<48> <49>
<32> <48> <49>
<34>
<33>
<35>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
34
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Bus Hold
TH
TH
TH
TI
CLKOUT (output)
HLDRQ (input)
<50>
<50> <51>
<36>
<53>
<53>
<39>
<40>
HLDAK (output)
<52>
<37>
<38>
Hi-Z
A16 to A21 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
Data
Hi-Z
Hi-Z
Hi-Z
DSTB (output), RD (output),
WRL (output), WRH (output)
Note R/W (output), UBEN (output), LBEN (output)
Data Sheet U13953EJ2V1DS
35
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Reset/Interrupt Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V,
CL = 50 pF)
Parameter
RESET high-level width
RESET low-level width
NMI high-level width
NMI low-level width
Symbol
Conditions
MIN.
500
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWRSH
<54>
<55>
<56>
<57>
<58>
tWRSL
tWNIH
tWNIL
tWITH
500
500
500
INTPn high-level width
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
n = 0 to 3, analog noise elimination
n = 4, 5, digital noise elimination
n = 6, digital noise elimination
500
3T + 20
3Tsmp + 20
500
INTPn low-level width
tWITL
<59>
3T + 20
3Tsmp + 20
Remarks 1. T = 1/fXX
2. Tsmp = Noise elimination sampling clock frequency
Reset
<54>
<55>
RESET (input)
Interrupt
<56>
<57>
NMI (input)
<58>
<59>
INTPn (input)
Remark n = 0 to 6
36
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
TIn Input Timing
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
TI0n0, TI0n1 (n = 00, 01)
high-level width
tTIH
<60>
2Tsam + 20Note
TIn (n = 2 to 7, 10, 11)
high-level width
3T + 20
2Tsam + 20Note
3T + 20
ns
ns
ns
TI0n0, TI0n1 (n = 00, 01)
low-level width
tTIL
<61>
TIn (n = 2 to 7, 10, 11)
low-level width
Note Tsam can be selected by setting bits PRMn2 to PRMn0 of prescaler mode registers n0, n1 (PRMn0, PRMn1)
(n = 0, 1).
TM0 (PRM00, PRM01 registers): Tsam = 2T, 4T, 16T, 64T, 256T, 1/INTWTN period
TM1 (PRM10, PRM11 registers): Tsam = 2T, 4T, 16T, 32T, 128T, 256T
However, when the TI0n0 valid edge is selected as the count clock, Tsam = 2T (n = 0, 1).
Remark T: 1/fXX
<61>
<60>
TIn (input)
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
Data Sheet U13953EJ2V1DS
37
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire SIO Timing
(1) Master mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
SCKn cycle time
Symbol
Conditions
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY1
<62>
<63>
<64>
<65>
<66>
<67>
SCKn high-level width
tKH1
tKL1
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
SOn output delay time from SCKn↓
tSIK1
tKSI1
tKSO1
50
60
Remark n = 0 to 3
(2) Slave mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
SCKn cycle time
Symbol
Conditions
MIN.
400
180
180
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY2
<62>
<63>
<64>
<65>
<66>
<67>
SCKn high-level width
tKH2
tKL2
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↓)
SOn output delay time from SCKn↓
tSIK2
tKSI2
tKSO2
50
60
Remark n = 0 to 3
<62>
<63>
<64>
<65>
SCKn (I/O)
SIn (input)
<66>
<67>
SOn (output)
Remark n = 0 to 3
38
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3-Wire Variable-Length CSI Timing
(1) Master mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
SCK4 cycle time
Symbol
Conditions
MIN.
400
140
140
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY1
<68>
<69>
<70>
<71>
<72>
<73>
SCK4 high-level width
tKH1
tKL1
SCK4 low-level width
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
SO4 output delay time from SCK4↓
tSIK1
tKSI1
tKSO1
50
60
(2) Slave mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
SCK4 cycle time
Symbol
Conditions
MIN.
400
180
180
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY2
<68>
<69>
<70>
<71>
<72>
<73>
SCK4 high-level width
tKH2
tKL2
SCK4 low-level width
SI4 setup time (to SCK4↑)
SI4 hold time (from SCK4↑)
SO4 output delay time from SCK4↓
tSIK2
tKSI2
tKSO2
50
60
<68>
<69>
<70>
<71>
SCK4 (I/O)
SI4 (input)
<72>
<73>
SO4 (output)
Data Sheet U13953EJ2V1DS
39
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
UART Timing
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
ASCKn cycle time
Symbol
Conditions
MIN.
200
80
MAX.
Unit
ns
tKCY13
<74>
<75>
<76>
ASCKn high-level width
ASCKn low-level width
tKH13
tKL13
ns
80
ns
Remark n = 0, 1
<74>
<75>
<76>
ASCKn (input)
Remark n = 0, 1
40
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I2C Bus Mode (Only for µPD703038Y, 703039Y, 703040Y, and 703041Y)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, CL = 50 pF)
Parameter
Symbol
Standard Mode
High-Speed Mode
MIN. MAX.
400
Unit
MIN.
MAX.
100
SCLn clock frequency
fCLK
tBUF
0
0
kHz
Bus free time
<77>
4.7
1.3
µs
(between stop and start conditions)
Hold timeNote 1
tHD : STA
tLOW
<78>
<79>
<80>
<81>
<82>
4.0
4.7
0.6
1.3
0.6
0.6
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
SCLn clock low-level width
SCLn clock high-level width
Setup time of start/restart conditions
tHIGH
4.0
tSU : STA
4.7
Data hold
time
CBUS-compatible master tHD : DAT
I2C bus mode
5.0
0Note 2
0Note 2
100Note 4
20 + 0.1CbNote 5
20 + 0.1CbNote 5
0.6
0.9Note 3
Data setup time
tSU : DAT
<83>
<84>
<85>
<86>
<87>
250
Rise time of SDAn and SCLn signals
Fall time of SDAn and SCLn signals
Setup time of stop condition
tR
1000
300
300
300
tF
tSU : STO
tSP
4.0
Pulse width of spike suppressed by
input filter
0
50
Load capacitance of bus lines
Cb
400
400
pF
Notes 1. The first clock pulse in the start condition is generated after the hold time.
2. The system must internally provide at least 300 ns hold time for the SDAn signal (at VIHmin. of the SCLn
signal) in order to fill the undefined area that appears at the SCLn falling edge.
3. If the system does not extend the low hold time (tLOW), only the maximum data hold time (tHD: DAT) needs
to be satisfied.
4. The high-speed I2C bus is available in a standard mode I2C bus system. In this case, the following
conditions should be satisfied.
•
When the system does not extend the low-state hold time of the SCLn signal
tSU: DAT ≥ 250 ns
•
When the system extends the low-state hold time of the SCLn signal
Send the next data bit to the SDAn line before the SCLn line is released (tRmax. + tSU: DAT = 1000 +
250 = 1250 ns: Standard mode I2C bus specification).
5. Cb: Total capacitance of one bus line (Unit: pF)
Remarks 1. N = 0, 1
2. The maximum operating frequency of I2C is fXX = 17 MHz. However, when 16 MHz < fXX ≤ 17 MHz,
use a system with VDD = 3.1 V to 3.6 V.
Data Sheet U13953EJ2V1DS
41
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
I2C Bus Mode (Only for µPD703039Y, 703040Y, and 703041Y)
<79> <80>
SCLn (I/O)
<85>
<84>
<82>
<81>
<87>
<86>
<83>
<78>
<78>
SDAn (I/O)
<77>
<85>
<84>
Stop
Start
Restart
condition
Stop
condition
condition condition
Remark n = 0, 1
A/D Converter (TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, AVSS = VSS = 0 V, CL = 50 pF)
Parameter
Resolution
Overall errorNote 1
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
Unit
bit
10
0.8
100
0.4
0.4
4.0
4.0
3.6
AVREF
500
3
%FSR
µs
Conversion time
tCONV
5
Zero-scale error Note 1
Full-scale error Note 1
Integral linearity error Note 2
Differential linearity error Note 2
Analog reference voltage
Analog input voltage
AVREF current
%FSR
%FSR
LSB
LSB
V
AVREF
VIAN
AVREF = AVDD
2.7
AVSS
V
AIREF
AIDD
360
1
µA
Supply current
In normal operation mode
In STOP mode
mA
AIDDS
1
10
µA
Notes 1. Excluding quantization error ( 0.05%FSR)
2. Excluding quantization error ( 0.5LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
42
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
3. PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
A
B
132
133
89
88
detail of lead end
S
P
T
C
D
R
L
U
Q
176
1
45
44
F
M
J
G
H
I
K
S
S
M
N
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
26.0 0.2
24.0 0.2
24.0 0.2
26.0 0.2
1.25
1.25
0.22 0.05
0.08
J
0.5 (T.P.)
1.0 0.2
0.5
K
L
+0.03
M
0.17
−0.07
0.08
N
P
Q
1.4
0.1 0.05
+4°
3°
R
S
−3°
1.5 0.1
S176GM-50-UEU
Data Sheet U13953EJ2V1DS
43
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
180-PIN PLASTIC FBGA (13x13)
D
w
S
B
ZD
B
15
14
13
12
11
10
9
ZE
A
8
E
7
6
5
4
3
2
1
R P N M L K J H G F E D C B A
w
S
A
INDEX MARK
A
y1
A2
S
S
ITEM MILLIMETERS
13.00 0.10
13.00 0.10
0.2
D
E
y
e
A1
B
w
S
A
1.48 0.10
0.35 0.06
1.13
A1
A2
e
φ
b
φ
x
M
S
A
0.80
b
0.50 0.05
0.08
x
y
0.10
0.20
y1
ZD
ZE
0.90
0.90
P180F1-80-EN2
44
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
4. RECOMMENDED SOLDERING CONDITIONS
The µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, and 703041Y should be soldered and
mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, consult an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 4-1. Surface Mounting Type Soldering Conditions(1/2)
(a) µPD703039GM-×××-UEU:
µPD703039YGM-×××-UEU:
µPD703040GM-×××-UEU:
µPD703040YGM-×××-UEU:
µPD703041GM-×××-UEU:
µPD703041YGM-×××-UEU:
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 sec. max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10
hours)
IR35-103-2
VP15-103-2
Package peak temperature: 215°C, Time: 40 sec. max. (at 200°C or higher),
Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10
hours)
Partial heating
Pin temperature: 300°C max., Time: 3 sec. max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(b) µPD703038F1-×××-EN2:
µPD703038YF1-×××-EN2:
µPD703039F1-×××-EN2:
µPD703039YF1-×××-EN2:
µPD703040F1-×××-EN2:
µPD703040YF1-×××-EN2:
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 sec. max. (at 210°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10
hours)
IR35-107-2
Package peak temperature: 215°C, Time: 25 to 40 sec. (at 200°C or higher),
Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10
hours)
VP15-107-2
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U13953EJ2V1DS
45
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Table 4-1. Surface Mounting Type Soldering Conditions(2/2)
(c) µPD703039GM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703039YGM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703040GM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703040YGM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703041GM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703041YGM-×××-UEU-A: 176-pin plastic LQFP (fine pitch) (24 × 24)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less,
IR60-207-3
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 to 72 hours)
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products with -A at the end of the part number are lead-free products.
(d) µPD703038F1-×××-EN2-A:
µPD703038YF1-×××-EN2-A: 180-pin plastic FBGA (13 × 13)
µPD703039F1-×××-EN2-A: 180-pin plastic FBGA (13 × 13)
µPD703039YF1-×××-EN2-A: 180-pin plastic FBGA (13 × 13)
µPD703040F1-×××-EN2-A: 180-pin plastic FBGA (13 × 13)
µPD703040YF1-×××-EN2-A: 180-pin plastic FBGA (13 × 13)
180-pin plastic FBGA (13 × 13)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less,
IR60-203-3
Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 to 72 hours)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products with -A at the end of the part number are lead-free products.
46
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet U13953EJ2V1DS
47
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
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Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
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United Kingdom Branch
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J05.6
48
Data Sheet U13953EJ2V1DS
µPD703038, 703038Y, 703039, 703039Y, 703040, 703040Y, 703041, 703041Y
Related document
µPD70F3038, 70F3038Y, 70F3040, 70F3040Y Data Sheet (U14622E)
Note
Reference document Electrical Characteristics for Microcomputer (U15170J)
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
These commodities, technology or software, must be exported in accordance
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The information in this document is current as of August, 2005. The information is subject to
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M8E 02. 11-1
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