UPD703134AF1-XXX-EN4 [NEC]
32-Bit Single-Chip Microcontrollers; 32位单芯片微控制器产品
| 型号： | UPD703134AF1-XXX-EN4 |
| 厂家： | 
NEC |
| 描述： | 32-Bit Single-Chip Microcontrollers |
| 文件： | 总99页 (文件大小：888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Application Note
V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2
32-Bit Single-Chip Microcontrollers
PCI Host Bridge Macro
V850E/MA1: V850E/MA2: V850E/MA3: V850E/ME2:
µPD703103A µPD703108
µPD703105A
µPD703106A
µPD703131A µPD703111A
µPD703131AY
µPD703132A
µPD703106A(A)
µPD703107A
µPD703132AY
µPD703133A
µPD703107A(A)
µPD70F3107A
µPD703133AY
µPD703134A
µPD70F3107A(A)
µPD703134AY
µPD70F3134A
µPD70F3134AY
Document No. U17121EJ1V1AN00 (1st edition)
Date Published September 2004 N CP(K)
2004
Printed in Japan
[MEMO]
2
Application Note U17121EJ1V1AN
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
Application Note U17121EJ1V1AN
The copyright of the PCI host bridge macro described in this document is held by the System Interface Module
Development Department, Device Solutions Division, NEC Engineering, Ltd.
Green Hills Software and MULTI are trademarks of Green Hills Software, Inc.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of March, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics
(as defined above).
M8E 02. 11-1
4
Application Note U17121EJ1V1AN
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
•
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2445845
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J04.1
5
Application Note U17121EJ1V1AN
INTRODUCTION
Readers
This application note is intended for users who wish to understand the functions of the
V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2, and PCI bus to design application
systems using these products.
Purpose
The purpose of this application note is to help the user understand the PCI host bridge
macro and its composition using the V850E/MA1, V850E/MA2, V850E/MA3,
V850E/ME2, and PCI host bridge macro as a system example.
Organization
This application note is broadly divided into the following sections.
• Overview of each product
• Overview of PCI host bridge macro
• Specifications of PCI host bridge macro
• Configuration examples of FPGA integration
• Application examples
How to Read This Manual It is assumed that the readers of this application note have general knowledge in the
fields of electrical engineering, logic circuits, and microcontrollers.
For details of the hardware functions and electrical specifications of the V850E/MA1,
V850E/MA2, V850E/MA3, and V850E/ME2
→ Refer to the Hardware User’s Manual of each product.
For details of the instruction functions of the V850E/MA1, V850E/MA2, V850E/MA3, and
V850E/ME2
→ Refer to the V850E1 Architecture User’s Manual.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name) or /xxx (“/” before
signal name)
Memory map address:
Higher addresses on the top and lower addresses on the
bottom
Note:
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numeric representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2 (address space, memory capacity):
K (kilo) ... 210 = 1,024
M (mega) ... 220 = 1,0242
G (giga) ... 230 = 1,0243
6
Application Note U17121EJ1V1AN
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2
Document Name
Document No.
U14559E
V850E1 Architecture User’s Manual
V850E/MA1 Hardware User’s Manual
U14359E
V850E/MA1 Hardware Application Note
U15179E
V850E/MA2 Hardware User’s Manual
U14980E
V850E/MA3 Hardware User’s Manual
U16397E
V850E/ME2 Hardware User’s Manual
U16031E
V850E/ME2 Hardware Application Note
U16794E
V850E/ME2 USB Function Driver Application Note
V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 PCI Host Bridge Macro Application Note
U17069E
This manual
Documents related to development tools (user’s manuals)
Document Name
Document No.
U14487E
U14481E
U16647E
U16053E
U16054E
U16042E
U16934E
U16217E
U16454E
U15182E
IE-V850E-MC, IE-V850E-MC-A In-Circuit Emulator
IE-703107-MC-EM1 In-Circuit Emulator Option Board
IE-V850E1-CD-NW PCMCIA Card Type On-Chip Debug Emulator
CA850 Ver.2.50 C Compiler Package
Operation
C Language
Assembly Language
PM plus Ver.5.20
ID850 Ver.2.50 Integrated Debugger
ID850NW Ver.2.51 Integrated Debugger
SM850 Ver.2.40 System Simulator
SM850 Ver.2.00 or Later System Simulator
RX850 Ver.3.13 or Later Real-Time OS
Operation
Operation
Operation
External Part User Open Interface Specifications U14873E
Basics
U13430E
U13410E
U13431E
U13773E
U13774E
U13772E
U13737E
U13916E
U14410E
U15260E
Installation
Technical
Basics
RX850 Pro Ver.3.15 Real-Time OS
Installation
Technical
RD850 Ver.3.01 Task Debugger
RD850 Pro Ver.3.01 Task Debugger
AZ850 Ver.3.10 System Performance Analyzer
PG-FP4 Flash Memory Programmer
7
Application Note U17121EJ1V1AN
CONTENTS
CHAPTER 1 OVERVIEW OF EACH PRODUCT..................................................................................10
1.1 Outline ...........................................................................................................................................10
1.2 Features.........................................................................................................................................11
1.3 Ordering Information....................................................................................................................12
1.4 Pin Configuration..........................................................................................................................14
1.5 Internal Block Diagram ................................................................................................................25
CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO..............................................................29
2.1 Outline ...........................................................................................................................................29
2.2 Features.........................................................................................................................................30
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO...................................................31
3.1 Internal Blocks of PCI Host Bridge Macro .................................................................................31
3.2 Relationship Between Internal Blocks and Signals..................................................................32
3.3 Pin Functions................................................................................................................................33
3.3.1 External bus slave interface pins .......................................................................................................33
3.3.2 SDRAM bus interface pins.................................................................................................................33
3.3.3 PCI bus interface pins........................................................................................................................34
3.4 Registers .......................................................................................................................................35
3.4.1 PCI_CONFIG_DATA register.............................................................................................................35
3.4.2 PCI_CONFIG_ADD register...............................................................................................................36
3.4.3 PCI_CONTROL register.....................................................................................................................37
3.4.4 PCI_IO_BASE register.......................................................................................................................38
3.4.5 PCI_MEM_BASE register ..................................................................................................................38
3.4.6 PCI_INT_CTL register........................................................................................................................39
3.4.7 PCI_ERR_ADD register.....................................................................................................................40
3.4.8 SYSTEM_MEM_BASE register .........................................................................................................41
3.4.9 SYSTEM_MEM_RANGE register ......................................................................................................41
3.4.10 SDRAM_CTL register ........................................................................................................................42
3.5 Address Map .................................................................................................................................44
3.6 Initializing PCI Host Bridge Macro..............................................................................................45
3.7 Bus Width of External Bus Interface ..........................................................................................46
3.8 Timing............................................................................................................................................47
3.8.1 External bus interface timing..............................................................................................................47
3.8.2 PCI bus interface timing.....................................................................................................................50
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION..........................................57
4.1 Conditions for Configuration Examples of FPGA Integration .................................................57
4.2 Points to Remember When Creating Top Layer of FPGA ........................................................57
4.3 Reference Diagram for FPGA Top Connection .........................................................................58
4.4 FPGA Top Pin Functions .............................................................................................................59
4.4.1 CPU bus slave interface pins.............................................................................................................59
4.4.2 SDRAM bus interface pins.................................................................................................................59
4.4.3 PCI bus interface pins........................................................................................................................60
4.5 FPGA Top Pin Configuration.......................................................................................................61
8
Application Note U17121EJ1V1AN
4.5.1 Internal connection diagram of external bus interface .......................................................................61
4.5.2 Internal connection diagram of PCI bus interface ..............................................................................62
4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2)....63
4.5.4 External connection diagram of PCI bus interface.............................................................................64
4.6 Cautions on Designing FPGA.....................................................................................................65
4.6.1 FPGA fitting design............................................................................................................................65
4.6.2 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz).......................................65
4.6.3 SDRAM interface timing ....................................................................................................................66
CHAPTER 5 APPLICATION EXAMPLES..............................................................................................67
5.1 Block Diagram of Evaluation Board...........................................................................................67
5.2 Specifications of Evaluation Board............................................................................................68
5.3 Example of Evaluation Board Connection Circuit....................................................................69
5.4 Evaluation Board Memory Space ...............................................................................................70
5.5 Sample Program Examples.........................................................................................................72
5.5.1 Development tools.............................................................................................................................72
5.5.2 Program configuration .......................................................................................................................72
5.5.3 V850E/ME2 PCI host bridge macro initialization sample program list ...............................................73
5.5.4 PCI configuration space access sample program list ........................................................................76
5.5.5 IDE HDD access sample program list................................................................................................79
9
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are products in NEC Electronics’ V850 Series of
single-chip microcontrollers. This chapter gives a simple outline of each product.
1.1 Outline
The V850E/MA1, V850E/MA2, V850E/MA3, and V850E/ME2 are 32-bit single-chip microcontrollers that integrate
the V850E1 CPU, which is a 32-bit RISC-type CPU core for ASIC, newly developed as the CPU core central to
system LSI in the current age of system-on-chip. These devices incorporate memory and various peripheral functions
such as memory controllers, a DMA controller, timer/counters, serial interfaces, and an A/D converter for realizing
high-capacity data processing and sophisticated real-time control.
10
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
1.2 Features
Commercial Name
V850E/MA1
50 MHz
V850E/MA2
40 MHz
V850E/MA3
V850E/ME2
150 MHz
Maximum operating
frequency
80 MHz
Internal Mask ROM
−
128
256
10
−
−
−
4
256
512
−
−
−
memory
Flash memory
−
256
−
512
(KB)
RAM
4
16 32 16
32
Instruction RAM: 128
Data RAM: 16
Cache (KB)
−
Instruction cache: 8
Separate
26 bits
External Bus type
Separate
26 bits
8/16 bits
8
Separate
25 bits
8/16 bits
4
Separate/multiplexed
bus
Address bus
26 bits
8/16 bits
8
Data bus
Chip select signals
Memory controller
16/32 bits
8
SDRAM, EDO DRAM, SDRAM, SRAM, etc.
SRAM, etc.
Interrupts ExternalNote 1
Internal
17 (17)
4 (4)
26 (26)
49
40 (31)
59
41
27
DSP
32 × 32 → 64
20 to 40 ns (50 MHz)
25 to 50 ns (40 MHz)
12.5 to 25 ns (80 MHz) 6.7 to 13.3 ns (150 MHz)
function
32 × 32 + 32 → 32 60 ns (50 MHz)
75 ns (40 MHz)
37.5 ns (80 MHz)
20 ns (150 MHz)
16-bit
timer
TMC
4 ch
2 ch
−
3 ch
1 ch
4 ch
1 ch
1 ch
−
6 ch
TMP
−
−
−
−
TMQ
−
−
Interval timer
Up/down counter
4 ch
4 ch
4 ch
2 ch
−
−
−
−
Watchdog timer
−
Serial
CSI
1 ch
1 ch
2 ch
−
1 ch
1 ch
1 ch
−
interface
UART
−
−
CSI/UART
UART/I2C
2 ch
3 ch
1 chNote 2
8 ch
2 ch
4 ch
11
−
−
−
10-bit A/D converter
8-bit D/A converter
DMA controller
8 ch
4 ch
8 ch
−
−
4 ch
9
4 ch
5
4 ch
7
Ports
CMOS input
CMOS I/O
106
74
101
77
Debug functions
−
−
Provided (RUN, break) Provided (RUN, break,
trace)
Other peripheral functions
Power supply voltage
PWM × 2 ch
3.0 to 3.6 V
528 mW
−
ROM correction function USB function, SSCG,
PWM × 2 ch
2.3 to 2.7 V (internal)
3.0 to 3.6 V (external)
1.5 V (internal)
3.3 V (external)
Power consumption
(mask version TYP.)
416 mW
575 mW
200 mW
Package
144-pin LQFP (20 × 20) 100-pin LQFP (14 × 14) 144-pin LQFP (20 × 20) 176-pin LQFP (20 × 20)
161-pin FBGA (13 × 13)
161-pin FBGA (13 × 13) 240-pin FBGA (16 × 16)
Operating ambient
temperature
TA = −40 to +85°C
TA = −40 to +85°C
(@133 MHz)
TA = −40 to +70°C
(@150 MHz)
Notes 1. The figure in parentheses indicates the number of external interrupts that can release STOP mode.
2. Available only in on-chip I2C products (Y products).
11
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
1.3 Ordering Information
(1) V850E/MA1
Part Number
Package
Internal ROM
ROMless
µPD703103AGJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
µPD703105AGJ-xxx-UEN
µPD703106AGJ-xxx-UEN
µPD703106AGJ(A)-xxx-UEN
µPD703106AF1-xxx-EN4
µPD703107AGJ-xxx-UEN
µPD703107AGJ(A)-xxx-UEN
µPD703107AF1-xxx-EN4
µPD70F3107AGJ-UEN
µPD70F3107AGJ(A)-UEN
µPD70F3107AF1-EN4
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (128 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Flash memory (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
(2) V850E/MA2
Part Number
Package
Internal ROM
ROMless
µPD703108GC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
12
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(3) V850E/MA3
Part Number
Package
Internal ROM
µPD703131AGJ-xxx-UEN
µPD703131AF1-xxx-EN4
µPD703131AYGJ-xxx-UEN
µPD703131AYF1-xxx-EN4
µPD703132AGJ-xxx-UEN
µPD703132AF1-xxx-EN4
µPD703132AYGJ-xxx-UEN
µPD703132AYF1-xxx-EN4
µPD703133AGJ-xxx-UEN
µPD703133AF1-xxx-EN4
µPD703133AYGJ-xxx-UEN
µPD703133AYF1-xxx-EN4
µPD703134AGJ-xxx-UEN
µPD703134AF1-xxx-EN4
µPD703134AYGJ-xxx-UEN
µPD703134AYF1-xxx-EN4
µPD70F3134AGJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (256 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Mask ROM (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
µPD70F3134AF1-EN4
µPD70F3134AYGJ-UEN
µPD70F3134AYF1-EN4
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
(4) V850E/ME2
Maximum Operating
Frequency
100 MHz
Part Number
Package
µPD703111AGM-10-UEU
µPD703111AGM-13-UEU
µPD703111AGM-15-UEU
µPD703111AF1-10-GA3
µPD703111AF1-13-GA3
µPD703111AF1-15-GA3
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
176-pin plastic LQFP (fine pitch) (24 × 24)
240-pin plastic FBGA (16 × 16)
133 MHz
150 MHz
100 MHz
240-pin plastic FBGA (16 × 16)
133 MHz
240-pin plastic FBGA (16 × 16)
150 MHz
13
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
1.4 Pin Configuration
(1) V850E/MA1
• 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703103AGJ-UEN
µPD703106AGJ(A)-xxx-UEN
µPD703107AGJ-xxx-UEN
µPD703107AGJ(A)-xxx-UEN
µPD70F3107AGJ-UEN
µPD703105AGJ-xxx-UEN
µPD703106AGJ-xxx-UEN
µPD70F3107AGJ(A)-UEN
Top View
D14/PDL14
D13/PDL13
1
108
107
106
105
104
103
102
101
100
99
PCD3/UBE/SDRAS
PCS0/CS0
2
D12/PDL12
3
PCS1/CS1/RAS1
PCS2/CS2/IOWR
PCS3/CS3/RAS3
PCS4/CS4/RAS4
PCS5/CS5/IORD
PCS6/CS6/RAS6
PCS7/CS7
D11/PDL11
4
D10/PDL10
5
D9/PDL9
6
D8/PDL8
7
V
8
VDSDS
9
D7/PDL7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D6/PDL6
98
VDSSD
V
D5/PDL5
97
PCT0/LCAS/LWR/LDQM
PCT1/UCAS/UWR/UDQM
PCT4/RD
D4/PDL4
96
D3/PDL3
95
D2/PDL2
94
PCT5/WE
D1/PDL1
93
PCT6/OE
D0/PDL0
92
PCT7/BCYST
PCM0/WAIT
PCM1/CLKOUT/BUSCLK
PCM2/HLDAK
PCM3/HLDRQ
PCM4/REFRQ
PCM5/SELFREF
P50/INTP030/TI030
P51/INTP031
P52/TO03
MODE2 (V /MODE2)
DMARQ3/INPTPP103/P07
DMARQ2/INTP102/P06
DMARQ1/INTP101/P05
DMARQ0/INTP100/P04
TO00/P03
91
90
89
88
87
86
INTP001/P02
TI000/INTP000/P01
PWM0/P00
85
84
83
V
VDSDS
82
V
81
VDSSD
DMAAK3/PBD3
DMAAK2/PBD2
DMAAK1/PBD1
DMAAK0/PBD0
TO01/P13
80
P70/ANI0
79
P71/ANI1
78
P72/ANI2
77
P73/ANI3
76
P74/ANI4
INTP011/P12
TI010/INTP010/P11
PWM1/P10
75
P75/ANI5
74
P76/ANI6
73
P77/ANI7
Remark Items in parentheses are pin names in the µPD70F3107A.
14
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
• 161-pin plastic FBGA (13 × 13)
µPD703106AF1-xxx-EN4
µPD703107AF1-xxx-EN4
µPD70F3107AF1-EN4
Top View
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P
Index mark
P N M L K J H G F E D C B A
Index mark
(1/2)
Pin No.
A1
Name
Pin No.
B9
Name
Pin No.
Name
−
A18/PAH2
D3
D4
D14/PDL14
A3/PAL3
A2
D15/PDL15
A2/PAL2
B10
B11
B12
B13
B14
C1
A21/PAH5
A25/PAH9
A3
D5
A6/PAL6
A4
A5/PAL5
SDCLK/PCD1
CS1/RAS1/PCS1
−
D6
A10/PAL10
A14/PAL14
A16/PAH0
A20/PAH4
A23/PAH7
A5
−
D7
A6
A9/PAL9
D8
A7
A12/PAL12
A15/PAL15
A17/PAH1
−
D9
A8
C2
D9/PDL9
D13/PDL13
A1/PAL1
A7/PAL7
VDD
D10
D11
D12
D13
D14
E1
A9
C3
SDCKE/PCD0
CS0/PCS0
CS5/IORD/PCS5
−
A10
A11
A12
A13
A14
B1
−
C4
A24/PAH8
C5
VDD
C6
LBE/SDCAS/PCD2
UBE/SDRAS/PCD3
−
C7
A11/PAL11
VDD
D5/PDL5
C8
E2
D7/PDL7
C9
A19/PAH3
A22/PAH6
VSS
E3
D8/PDL8
B2
D12/PDL12
A0/PAL0
A4/PAL4
VSS
C10
C11
C12
C13
C14
D1
E4
D11/PDL11
−
B3
E5
B4
CS3/RAS3/PCS3
CS2/IOWR/PCS2
−
E11
E12
E13
E14
F1
CS6/RAS6/PCS6
CS4/RAS4/PCS4
CS7/PCS7
VSS
B5
B6
A8/PAL8
A13/PAL13
VSS
B7
VSS
B8
D2
D10/PDL10
D2/PDL2
15
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(2/2)
Pin No.
F2
Name
Pin No.
K2
Name
Pin No.
M12
M13
M14
N1
Name
D3/PDL3
D4/PDL4
VDD
VSS
ANI6/P76
ANI5/P75
F3
K3
DMAAK1/PBD1
DMAAK3/PBD3
ANI1/P71
ANI0/P70
VSS
F4
K4
−
−
F11
F12
F13
F14
G1
RD/PCT4
VDD
K11
K12
K13
K14
L1
N2
PWM1/P10
LCAS/LWR/LDQM/PCT0
UCAS/UWR/UDQM/PCT1
MODE2 (MODE2/VPP)
DMARQ3/INTP103/P07
D0/PDL0
N3
TC3/INTP113/P27
VDD
N4
TC0/INTP110/P24
−
N5
NMI/P20
G2
L2
DMAAK2/PBD2
TI010/INTP010/P11
DMAAK0/PBD0
TO02/P23
N6
ADTRG/INTP123/P37
G3
L3
N7
TXD2/INTP133/P33
G4
D6/PDL6
L4
N8
SO2/INTP130/P30
G11
G12
G13
G14
H1
WAIT/PCM0
L5
N9
X2
WE/PCT5
L6
VDD
N10
N11
N12
N13
N14
P1
CVSS
BCYST/PCT7
L7
INTP122/P36
SI2/INTP131/P31
RESET
SCK0/P42
OE/PCT6
L8
AVDD/AVREF
DMARQ2/INTP102/P06
DMARQ1/INTP101/P05
DMARQ0/INTP100/P04
D1/PDL1
L9
AVSS
H2
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
TXD1/SO1/P43
ANI7/P77
−
H3
VDD
H4
ANI4/P74
P2
VSS
H11
H12
H13
H14
J1
REFRQ/PCM4
HLDRQ/PCM3
HLDAK/PCM2
ANI3/P73
P3
TC1/INTP111/P25
ANI2/P72
P4
INTP021/P22
−
P5
−
CLKOUT/BUSCLK/PCM1
TO00/P03
INTP011/P12
TO01/P13
P6
INTP121/P35
P7
SCK2/INTP132/P32
J2
TI000/INTP000/P01
VDD
TC2/INTP112/P26
TI020/INTP020/P21
VSS
P8
MODE1
J3
P9
CVDD
J4
INTP001/P02
P10
P11
P12
P13
P14
X1
J11
J12
J13
J14
K1
TO03/P52
RXD2/INTP120/P34
MODE0
−
RXD1/SI1/P44
RXD0/SI0/P41
−
TI030/INTP030/P50
SELFREF/PCM5
INTP031/P51
CKSEL
SCK1/P45
PWM0/P00
TXD0/SO0/P40
Remarks 1. Leave the A1, A5, A10, B1, B14, C1, C14, D14, E5, L1, M1, M14, N1, N14, P5, P11, and P14 pins
open.
2. Items in parentheses are pin names in the µPD70F3107A.
16
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(2) V850E/MA2
• 100-pin plastic LQFP (fine pitch) (14 × 14)
µPD703108GC-8EU
Top View
A1/PAL1
A0/PAL0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PAH7/A23
2
PAH8/A24
D15/PDL15
D14/PDL14
D13/PDL13
D12/PDL12
D11/PDL11
D10/PDL10
D9/PDL9
3
PCD0/SDCKE
PCD1/SDCLK
PCD2/LBE/SDCAS
PCD3/UBE/SDRAS
PCS0/CS0
4
5
6
7
8
PCS3/CS3
9
PCS4/CS4
D8/PDL8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PCS7/CS7
V
DD
PCT0/LWR/LDQM
PCT1/UWR/UDQM
PCT4/RD
VSS
D7/PDL7
D6/PDL6
PCT5/WE
PCM0/WAIT
D5/PDL5
D4/PDL4
PCM1/CLKOUT
PCM2/HLDAK
PCM3/HLDRQ
PCM4/REFRQ
D3/PDL3
D2/PDL2
D1/PDL1
D0/PDL0
V
V
SS
MODE2
DD
DMARQ1/INTP101/P05
DMARQ0/INTP100/P04
TO00/P03
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
INTP001/P02
17
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(3) V850E/MA3
• 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703131AGJ-xxx-UEN
µPD703133AGJ-xxx-UEN
µPD703133AYGJ-xxx-UEN
µPD703134AGJ-xxx-UEN
µPD703134AYGJ-xxx-UEN
µPD70F3134AGJ-UEN
µPD70F3134AYGJ-UEN
µPD703131AYGJ-xxx-UEN
µPD703132AGJ-xxx-UEN
µPD703132AYGJ-xxx-UEN
Top View
AD14/PDL14
AD13/PDL13
1
108
107
106
105
104
103
102
101
100
99
PCD3/SDRAS
PCS0/CS0
2
AD12/PDL12
3
PCS1/CS1
AD11/PDL11
4
PCS2/CS2/IOWR
PCS3/CS3
AD10/PDL10
5
AD9/PDL9
6
PCS4/CS4
AD8/PDL8
7
PCS5/CS5/IORD
PCS6/CS6
EV
8
EVDSDS
9
PCS7/CS7
AD7/PDL7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
EV
AD6/PDL6
98
EVSS
AD5/PDL5
97
PCDTD0/LBE/LWR/LDQM
PCT1/UBE/UWR/UDQM
PCT4/RD
AD4/PDL4
96
AD3/PDL3
95
AD2/PDL2
94
PCT5/WR/WE
PCT6/ASTB
AD1/PDL1
93
AD0/PDL0
92
PCT7/BCYST
INTP001/TOP01/INTPP01/P01
INTP000/TOP00/EVTP0/TIP0/INTPP00/P00
INTP115/TOQB3/EVTQ/P15
INTP114/TOQB2/TIQ/P14
INTP013/TOQT3/INTPQ3/TOQ3/P13
V
91
PCM0/WAIT
90
PCM1/BUSCLK
PCM2/HLDAK
PCM3/HLDRQ
PCM4/REFRQ
P50/INTP050/INTPP20/TOP20/EVTP2/TIP2
P51/INTP051/INTPP21/TOP21
P20/NMI
89
88
87
86
VDSDS
85
INTP012/TOQT2/INTPQ2/TOQ2/P12
INTP011/TOQT1/INTPQ1/TOQ1/P11
INTP010/TOQB1/INTPQ0/TOQ0/P10
TDO/TC3/P27
84
83
P37/INTP137/ADTRG
82
81
VSS
V
TDI/INTP126/TC2/P26
INTP125/TC1/TIUD10/TO10/P25
INTP124/TC0/P24
80
P7DD0/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
79
78
TRST
77
INTP004/DMARQ0/TCLR10/INTP11/P04
INTP005/DMARQ1/TCUD10/INTP10/P05
TMS/INTP106/DMARQ2/P06
TCK/INTP107/DMARQ3/P07
76
75
74
73
Note SCL and SDA are available only in the µPD703131Y, 703132Y, 703133Y, 703134Y, 703137Y, and
70F3134Y.
18
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
• 161-pin plastic FBGA (13 × 13)
µPD703131AF1-EN4
µPD703133AF1-xxx-EN4
µPD703133AYF1-xxx-EN4
µPD703134AF1-xxx-EN4
µPD703134AYF1-xxx-EN4
µPD70F3134AF1-EN4
µPD70F3134AYF1-EN4
µPD703131AYF1-xxx-EN4
µPD703132AF1-xxx-EN4
µPD703132AYF1-xxx-EN4
Top View
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P
Index mark
P N M L K J H G F E D C B A
Index mark
(1/2)
Pin No.
A1
Name
Pin No.
B8
Name
Pin No.
Name
EVSS
VSS
D1
D2
EVSS
A2
AD15/PDL15
A2/PAL2
A5/PAL5
EVSS
B9
A18/PAH2
A21/PAH5
A25/PAH9
AD10/PDL10
AD14/PDL14
A3/PAL3
A3
B10
B11
B12
B13
B14
C1
D3
A4
D4
A5
SDCLK/PCD1
CS1/PCS1
EVSS
D5
A6/PAL6
A6
A9/PAL9
A12/PAL12
A15/PAL15
A17/PAH1
D6
A10/PAL10
A14/PAL14
A16/PAH0
A20/PAH4
A23/PAH7
SDCKE/PCD0
CS0/PCS0
CS5/IORD/PCS5
EVSS
A7
D7
A8
EVSS
D8
A9
C2
AD9/PDL9
AD13/PDL13
A1/PAL1
A7/PAL7
EVDD
D9
A10
A11
A12
A13
A14
B1
−
C3
D10
D11
D12
D13
D14
E1
A24/PAH8
EVDD
C4
C5
SDCAS/PCD2
SDRAS/PCD3
EVSS
C6
C7
A11/PAL11
VDD
C8
AD5/PDL5
AD7/PDL7
AD8/PDL8
AD11/PDL11
−
B2
AD12/PDL12
A0/PAL0
A4/PAL4
EVSS
C9
A19/PAH3
A22/PAH6
EVSS
E2
B3
C10
C11
C12
C13
C14
E3
B4
E4
B5
CS3/PCS3
CS2/IOWR/PCS2
EVSS
E5
B6
A8/PAL8
A13/PAL13
E11
E12
CS6/PCS6
CS4/PCS4
B7
19
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(2/2)
Pin No.
E13
E14
F1
Name
Pin No.
J14
K1
Name
Pin No.
M11
M12
M13
M14
N1
Name
CS7/PCS7
EVSS
NMI/P20
AVSS0
TOQT1/INTP011/INTPQ1/TOQ1/P11
ANI6/P76
ANI5/P75
AD2/PDL2
AD3/PDL3
AD4/PDL4
EVDD
K2
TC3/TDO/P27
F2
K3
TC0/INTP124/P24
−
F3
K4
TC2/TDI/INTP126/P26
EVSS
F4
K11
K12
K13
K14
L1
ANI1/P71
N2
DMARQ3/TCK/INTP107/P07
DMAAK3/PBD3
F11
F12
F13
F14
G1
RD/PCT4
EVDD
ANI0/P70
N3
VSS
N4
DMAAK0/PBD0
LBE/LWR/LDQM/PCT0
VDD
N5
TXD3/SDANote/INTP133/P33
TXD2/SO2/INTP130/P30
ASCK0/SCK0/P42
VSS
UBE/UWR/UDQM/PCT1
TOP01/INTP001/INTPP01/P01
EVSS
N6
L2
TC1/TIUD10/TO10/INTP125/P25
DMARQ2/TMS/INTP106/P06
N7
G2
TOP00/INTP000/EVTP0/TIP0/
INTPP00/P00
L3
N8
G3
G4
AD0/PDL0
L4
L5
TRST
N9
N10
N11
N12
N13
N14
P1
X2
AD6/PDL6
TOP11/INTPP11/INTP022/P22
ASCK2/SCK2/INTP132/P32
ASCK1/SCK1/P45
TXD0/SO0/P40
MODE0
CVSS
G11
G12
G13
G14
H1
WAIT/PCM0
L6
ANO1/P81
AVSS1
WR/WE/PCT5
L7
BCYST/PCT7
L8
AVDD1
ASTB/PCT6
L9
−
TOQB3/INTP115/EVTQ/P15
TOQB2/INTP114/TIQ/P14
TOQT3/INTP013/INTPQ3/TOQ3/P13
AD1/PDL1
L10
L11
L12
L13
AVDD0
EVDD
H2
ANI7/P77
P2
EVSS
H3
ANI4/P74
P3
DMAAK1/PBD1
H4
ANI3/P73
P4
TOP10/INTPP10/EVTP1/TIP1/
INTP021/P21
H11
H12
H13
REFRQ/PCM4
HLDRQ/PCM3
HLDAK/PCM2
L14
M1
M2
ANI2/P72
P5
P6
P7
EVSS
EVSS
RXD1/SI1/P44
RXD0/SI0/P41
DMARQ1/TCUD10/INTP10/
INTP005/P05
H14
BUSCLK/PCM1
M3
DMARQ0/INTP11/TCLR10/
INTP004/P04
P8
PSEL
J1
J2
VDD
M4
M5
M6
M7
M8
M9
M10
DMAAK2/PBD2
RXD3/SCLNote/INTP134/P34
RXD2/SI2/INTP131/P31
TXD1/SO1/P43
VDD
P9
CVDD
TOQT2/INTP012/INTPQ2/TOQ2/P12
TOQB1/INTP010/INTPQ0/TOQ0/P10
VSS
P10
P11
P12
P13
P14
X1
J3
−
J4
RESET
J11
J12
J13
ADTRG/INTP137/P37
TOP21/INTPP21/INTP051/P51
ANO0/P80
−
CKSEL
TOP20/INTPP20/EVTP2/TIP2/
INTP050/P50
MODE1
Note SCL and SDA are available only in the µPD703131AY, 703132AY, 703133AY, 703134AY, and 70F3134AY.
Remark Leave the A10, E5, M14, N14, P11, and P14 pins open.
20
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(4) V850E/ME2
• 176-pin plastic LQFP (fine pitch) (24 × 24)
µPD703111AGM-10-UEU
µPD703111AGM-13-UEU
µPD703111AGM-15-UEU
Top View
JIT1
JIT0
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
TRCDATA3
2
PDH15/D31/INTPD15/PWM1
AVDD
3
PDH14/D30/INTPD14/PWM0
EVSS
EVDD
PDH13/D29/INTPD13/TIUD11
PDH12/D28/INTPD12/TO11
PDH11/D27/INTPD11/INTP111/TCLR11
PDH10/D26/INTPD10/INTP110/TCUD11
PDH9/D25/INTPD9/TIUD10
PDH8/D24/INTPD8/TO10
PDH7/D23/INTPD7/INTP101/TCLR10
PDH6/D22/INTPD6/INTP100/TCUD10
PDH5/D21/INTPD5/TOC5
PDH4/D20/INTPD4
PDH3/D19/INTPD3
EVSS
EVDD
PDH2/D18/INTPD2/TOC4
PDH1/D17/INTPD1
PDH0/D16/INTPD0
AVREFP
4
ANI0
5
ANI1
6
ANI2
7
ANI3
8
ANI4
9
ANI5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ANI6
ANI7
AVREFM
AVSS
MODE1
MODE0
INTP67/TOC1/P67
INTP66/INTPC11/P66
INTP65/TIC1/INTPC10/P65
TOC0/TC1/P55
INTPC01/DMAAK1/P54
INTPC00/TIC0/DMARQ1/P53
INTP52/TC0/P52
INTP51/DMAAK0/P51
INTP50/DMARQ0/P50
IVDD
D15
D14
D13
D12
D11
D10
D9
IVSS
RESET
ADTRG/SELFREF/PCM5
REFRQ/PCM4
HLDRQ/PCM3
HLDAK/PCM2
PCM1
D8
IVSS
IVDD
EVSS
EVDD
D7
WAIT/PCM0
CS7/PCS7
CS6/PCS6
IORD/CS5/PCS5
EVDD
98
D6
97
D5
96
D4
95
D3
EVSS
94
D2
CS4/PCS4
CS3/PCS3
IOWR/CS2/PCS2
CS1/PCS1
CS0/PCS0
93
D1
92
D0
91
SDCKE/PCD0
EVSS
EVDD
90
89
21
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
• 240-pin plastic FBGA (16 × 16)
µPD703111AF1-10-GA3
µPD703111AF1-13-GA3
µPD703111AF1-15-GA3
18
17
16
15
14
13
12
11
10
9
Bottom View
Top View
8
7
6
5
4
3
2
1
P N M L K J H G F E D C B A
E F G H J K L M N P R T U V
A B C D
V U T R
Index mark
22
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(1/2)
Pin No.
A1
Name
Pin No.
C12
C13
C14
C15
C16
C17
C18
D1
Name
Pin No.
G3
Name
−
IVDD
EVSS
D7
A2
IVSS
PAH2/A18
PAH4/A20
PAH6/A22
G4
A3
PCT0/LLWR/LLBE/LLDQM
G15
G16
G17
G18
H1
PCM1
A4
−
PCM3/HLDRQ
A5
PCT4/RD
−
−
PCM4/REFRQ
A6
−
PCS0/CS0
PCM5/ADTRG/SELFREF
A7
−
−
A8
EVDD
D0
H2
D8
A9
A9
D2
EVSS
H3
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
−
D3
PCD0/SDCKE
H4
D10
A14
D4
EVDD
H5
IVSS
IVSS
D5
PCT1/LUWR/LUBE/LUDQM
H14
H15
H16
H17
H18
J1
−
EVDD
D6
−
RESET
−
D7
PAL0/INTPL0/A0
IVSS
PAH5/A21
D8
A4
−
PAH7/A23
D9
A6
IVDD
PAH9/A25
D10
D11
D12
D13
D14
D15
D16
D17
D18
E1
−
−
−
A13
J2
D11
−
EVSS
J3
D12
B2
PCD1/BUSCLK
PAH3/A19
J4
−
B3
PCD2/SDCAS
−
J5
D13
B4
−
−
J14
J15
J16
J17
J18
K1
−
B5
PCT3/UUWR/UUBE/UUDQM
PCS2/CS2/IOWR
P50/INTP50/DMARQ0
P51/INTP51/DMAAK0
P52/INTP52/TC0
B6
PCT7/BCYST
PCS3/CS3
B7
A2
EVDD
B8
−
D3
P53/INTPC00/TIC0/DMARQ1
B9
A8
E2
D2
D14
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
A12
E3
D1
K2
D15
PAH0/A16
E4
−
K3
PDH0/D16/INTPD0
−
E8
A3
K4
PDH1/D17/INTPD1
−
E9
A5
K5
PDH2/D18/INTPD2/TOC4
−
E10
E11
E15
E16
E17
E18
F1
A10
K14
K15
K16
K17
K18
L1
P55/TOC0/TC1
−
PAH1/A17
P54/INTPC01/DMAAK1
PAH8/A24
PCS4/CS4
P65/INTP65/INTPC10/TIC1
−
EVSS
P66/INTP66/INTPC11
PCS1/CS1
PCS5/CS5/IORD
−
−
PCS6/CS6
EVDD
C2
−
D6
L2
−
C3
PCD3/SDRAS
F2
D5
L3
EVSS
C4
IVDD
F3
D4
L4
PDH3/D19/INTPD3
C5
PCT2/ULWR/ULBE/ULDQM
F4
−
−
L5
PDH4/D20/INTPD4
C6
PCT5/WE/WR
F15
F16
F17
F18
G1
L14
L15
L16
L17
L18
M1
MODE1
C7
PAL1/INTPL1/A1
PCS7/CS7
PCM0/WAIT
PCM2/HLDAK
IVDD
−
C8
EVSS
A7
MODE0
C9
−
P67/INTP67/TOC1
−
C10
C11
A11
A15
G2
EVDD
23
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(2/2)
Pin No.
M2
Name
Pin No.
R7
Name
Pin No.
U4
Name
PDH5/D21/INTPD5/TOC5
DCK
−
M3
PDH6/D22/INTPD6/INTP100/
TCUD10
R8
EVDD
U5
TRCCLK
DRST
M4
M15
M16
M17
M18
N1
−
R9
P11/INTP11/SCK0
U6
U7
ANI6
R10
R11
R12
R13
R14
IVSS
P25/INTP25/SO1
AVREFM
ANI7
UDM
X2
U8
P22/INTP22/TXD1
U9
EVSS
IVDD
−
AVSS
PLLVDD
SSEL0
U10
U11
PDH7/D23/INTPD7/INTP101/
TCLR10
N2
N3
N4
PDH8/D24/INTPD8/TO10
PDH9/D25/INTPD9/TIUD10
R15
R16
R17
−
U12
U13
U14
OSCVDD
AVREFP
−
−
PDH10/D26/INTPD10/
INTP110/TCUD11
AVDD
N15
N16
N17
N18
P1
ANI2
ANI3
ANI4
ANI5
−
R18
T1
T2
T3
T4
T5
−
U15
U16
U17
U18
V1
P76/INTPC31/DMAAK3
P73/INTPC21/DMAAK2
EVDD
TRCDATA3
−
P72/INTPC20/TIC2/DMARQ2
−
−
TRCDATA1
TRCEND
P2
PDH11/D27/INTPD11/
INTP111/TCLR11
V2
TRCDATA2
P3
P4
PDH13/D29/INTPD13/TIUD11
T6
T7
DDI
V3
V4
IVSS
−
−
TRCDATA0
P8
P23/INTP23/SCK1
T8
P21/INTP21/RXD1
V5
−
P9
P12/SI0/RXD0
T9
P20/NMI
V6
DMS
P10
P11
P15
P16
P17
P18
R1
−
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
−
V7
P24/INTP24/SI1
UVDD
UDP
V8
−
−
X1
V9
P13/SO0/TXD0
ANI0
OSCVSS
V10
V11
V12
V13
V14
V15
V16
V17
V18
PLLSEL
ANI1
SSEL1
P10/INTP10/UCLK
−
P75/INTPC30/TIC3/DMARQ3
−
PDH12/D28/INTPD12/TO11
−
−
R2
EVSS
JIT1
−
R3
PDH14/D30/INTPD14/PWM0
JIT0
PLLVSS
R4
IVDD
PDH15/D31/INTPD15/PWM1
P77/TOC3/TC3
P74/TOC2/TC2
−
R5
−
U2
−
−
R6
DDO
U3
Remark Leave the A1, A4, A6, A7, A10, A14, A18, B1, B4, B8, B12 to B15, B17, C1, C2, C16, C18, D6, D10, D14,
D15, E4, F4, F15, H1, H14, H17, J1, J4, J14, K18, L2, L15, L17, M1, M4, P1, P4, P10, P15, P18, R5, R15,
R18, T3, T7, T10, T16, U2 to U4, U11, U13, U14, U18, V1, V5, V8, V12 to V14, and V18 pins open.
24
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
1.5 Internal Block Diagram
(1) V850E/MA1
NMI
HLDRQ
BCU
MEMC
CPU
HLDAK
INTP100 to INTP103,
INTC
CS0, CS7
CS1/RAS1, CS3/RAS3
CS4/RAS4, CS6/RAS6
CS2/IORD
CS5/IOWR
SELFREF
REFRQ
INTP110 to INTP113,
ROM
INTP120 to INTP123,
INTP130 to INTP133
Instruction
queue
DRAMC
PC
Note 1
INTP000, INTP001,
INTP010, INTP011,
INTP020, INTP021,
Multiplier
(32 × 32 → 64)
BCYST
32-bit
barrel shifter
INTP030, INTP031
RPU
LBE/SDCAS
UBE/SDRAS
SDCLK
TO00 to TO03
SDCKE
TI000, TI010,
TI020, TI030
WE
System
registers
RD
OE
RAM
SIO
UWR/UCAS/UDQM
LWR/LCAS/LDQM
WAIT
ROMC
DMAC
SO0/TXD0
SI0/RXD0
SCK0
ALU
UART0/CSI0
General-
purpose
registers
A0 to A25
D0 to D15
BUSCLK
Note 2
SO1/TXD1
SI1/RXD1
SCK1
(32 bits × 32)
UART1/CSI1
UART2
CSI2
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
TXD2
RXD2
SO2
SI2
SCK2
PWM0
PWM1
PWM0
PWM1
CKSEL
CLKOUT
X1
Ports
CG
X2
CVDD
CVSS
ANI0 to ANI7
AVREF/AVDD
AVSS
ADC
MODE0, MODE1
MODE2/VPP
RESET
ADTRG
Note 3
System
controller
V
V
DD
SS
Notes 1. µPD703103A:
µPD703105A, 703106A:
ROMless
128 KB (mask ROM)
256 KB (mask ROM)
256 KB (flash memory)
4 KB
µPD703107A:
µPD70F3107A:
2. µPD703103A, 703105A:
µPD703106A, 703107A, 70F3107A: 10 KB
3. Available only in the µPD70F3107A.
25
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(2) V850E/MA2
NMI
BCU
MEMC
CPU
HLDRQ
INTP100, INTP101,
INTP110
INTC
RPU
HLDAK
CS0, CS3, CS4, CS7
REFRQ
Instruction
queue
SDRAMC
PC
LBE/SDCAS
UBE/SDRAS
SDCLK
INTP000, INTP001,
INTP010, INTP011
Multiplier
(32 × 32 → 64)
32-bit
barrel shifter
SDCKE
WE
TO00
RD
TI000, TI010
UWR/UDQM
LWR/LDQM
WAIT
System
registers
RAM
4 KB
SIO
ROMC
DMAC
TXD0/SO0
RXD0/SI0
SCK0
ALU
A0 to A24
D0 to D15
UART0/CSI0
General-
purpose
registers
TXD1/SO1
RXD1/SI1
SCK1
(32 bits × 32)
UART1/CSI1
DMARQ0, DMARQ1
DMAAK0, DMAAK1
TC0
ANI0 to ANI3
AVREF/AVDD
AVSS
ADC
CKSEL
CLKOUT
X1
Ports
Prescaler
CG
X2
CVDD
CVSS
MODE0 to MODE2
RESET
System
controller
VDD
VSS
26
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(3) V850E/MA3
NMI
INTP000, INTP001, INTP004, INTP005
INTP010 to INTP013, INTP114, INTP115
INTP021, INTP022, INTP124 to INTP126
INTP130 to INTP134, INTP137, INTP050,
INTP051, INTP106, INTP107
WAIT
MEMC
CPU
HLDRQ
HLDAK
INTC
BCU
ROM
BUSCLK
A0 to A25
AD0 to AD15
CS0 to CS7
BCYST
Instruction
queue
PC
SRAM
ROM
Note 1
TMENC
× 1 ch
TCLR10, TIUD10, TCUD10
INTP10, INTP11
Multiplier
RD
(32 × 32 → 64)
UWR, LWR/UBE, LBE
WR
TO10
32-bit
barrel shifter
ASTB
IORD
TMD
× 4 ch
IOWR
SDCLK
System
registers
SDCKE
SDRAS
SDCAS
WE
SDRAM
TIQ, EVTQ, INTPQ0 to INTPQ3
TOQ0 to TOQ3,
ALU
TMQ0
× 1 ch
LDQM, UDQM
REFRQ
TOQT1 to TOQT3,
TOQB1 to TOQB3
RAM
General-
purpose
registers
(32 bits × 32)
EVTP0 to EVTP2, TIP0 to TIP2, INTPP00, INTPP01
INTPP10, INTPP11, INTPP20, INTPP21
Note 2
TMP
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
× 3 ch
TOP00, TOP01, TOP10,
TOP11, TOP20, TOP21
DMAC
WDT
TXD0/SO0
RXD0/SI0
ASCK0/SCK0
UARTA0/CSIB0
CKSEL
X1
CG
Ports
TXD1/SO1
RXD1/SI1
ASCK1/SCK1
UARTA1/CSIB1
UARTA2/CSIB2
UARTA3/I2CNote 3
PLL
X2
PSEL
CVDD
CVSS
TXD2/SO2
RXD2/SI2
ASCK2/SCK2
RESET
MODE0, MODE1
VDD
VSS
EVDD
System
controller
TXD3/SDANote 3
RXD3/SCLNote 3
EVSS
ANI0 to ANI7
ADTRG
ADC
× 8 ch
TCK
TMS
TRST
TDO
TDI
AVDD0
AVSS0
DCU
ANO0, ANO1
DAC
AVDD1
AVSS1
× 2 ch
Notes 1. µPD703131A, 703131AY, 703132A, 703132AY: 256 KB (mask ROM)
µPD703133A, 703133AY, 703134A, 703134AY: 512 KB (mask ROM)
µPD70F3134A, 70F3134AY:
512 KB (flash memory)
2. µPD703131A, 703131AY, 703133A, 703133AY: 16 KB
µPD703132A, 703132AY, 703134A, 703134AY,
70F3134A, 70F3134AY:
32 KB
3. Available only in the µPD703131AY, 703132AY, 703133AY, 703134AY, 703137AY, and 70F3134AY.
27
Application Note U17121EJ1V1AN
CHAPTER 1 OVERVIEW OF EACH PRODUCT
(4) V850E/ME2
DRST, DCK,
DMS, DDI,
DCU
INTC
MEMC
SRAM
WAIT
HLDRQ
HLDAK
CPU
DDO, TRCCLK,
TRCDATA0 to TRCDATA3
,
TRCEND
BCU
A0 to A25
D0 to D31
NMI
INTP10, INTP11
INTP21 to INTP25
INTP50 to INTP52
INTP65 to INTP67
INTPD0 to INTPD15
INTPL0, INTPL1
PC
Instruction
queue
CS0, CS1, CS3,
CS4, CS6, CS7
Multiplier
(32 × 32 → 64)
Instruction cache
ROM
CS2/IOWR
CS5/IORD
BCYST
RD
8 KB
32-bit
barrel shifter
TCLR10, TCLR11
TIUD10, TIUD11
TCUD10, TCUD11
xxWR/xxBE
ALU
SDRAM
WR
Instruction RAM
TMENC1
BUSCLK
SDCKE
SDRAS
SDCAS
WE
INTP100, INTP110
INTP101, INTP111
128 KB
System
registers
TO10, TO11
TIC0 to TIC3
xxDQM
REFRQ
SELFREF
Data RAM
General-
INTPC00, INTPC01,
INTPC10, INTPC11,
INTPC20, INTPC21,
INTPC30, INTPC31
TOC0 to TOC3
purpose
TMC
16 KB
registers
(32 bits × 32)
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
DMA
TOC4, TOC5
TMC
TMD
BBR
SI0/RXD0
SO0/TXD0
SCK0
PWM
ADC
PWM0, PWM1
CSI30/UARTB0
Ports
ANI0 to ANI7
ADTRG
SI1
SO1
CSI31
AVREFP, AVREFM
AVDD
SCK1
AVSS
RXD1
TXD1
UARTB1
UDP
UDM
UCLK
UVDD
USBF
SSEL0, SSEL1
JIT0, JIT1
PLLSEL
X1
RESET
X2
CG
MODE0, MODE1
OSCVDD
OSCVSS
PLLVDD
PLLVSS
System
controller
IVDD
IVSS
EVDD
EVSS
Remark xx: LL, LU, UL, UU
28
Application Note U17121EJ1V1AN
CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO
The PCI host bridge macro enables connection of V850E/MA1, V850E/MA2, V850E/MA3, V850E/ME2 external
bus interfaces to the PCI bus interface. This chapter gives an outline of the PCI host bridge macro.
2.1 Outline
The PCI host bridge macro is a bridge control macro that connects V850E/MA1, V850E/MA2, V850E/MA3,
V850E/ME2 external bus interfaces (memory controller (MEMC)) to the PCI bus interface.
The main memory (SDRAM) can be directly controlled when SDRAM is accessed from a PCI device.
29
Application Note U17121EJ1V1AN
CHAPTER 2 OVERVIEW OF PCI HOST BRIDGE MACRO
2.2 Features
The features of the PCI host bridge macro are as follows.
• PCI bus master cycle control
PCI configuration register read/write single cycle
PCI I/O register read/write single cycle
PCI memory read/write single cycle
• PCI bus slave cycle control
PCI memory read/write cycle (burst transfer up to 8 doublewords (32 bits × 8 bursts))
• PCI bus arbiter control
Up to 8 masters can be controlled (one of them is occupied by the PCI host bridge macro)
Bus parking master: Limited to PCI host bridge macro/selectable from the last accessed master
• PCI bus error processing
An error interrupt is generated for master abort/target abort/PERR# reception/SERR# reception
The address immediately before an error occurs is retained
• PCI bus address conversion control
PCI I/O address and PCI memory address registers are supported to convert the physical addresses from
the CPU to addresses for the PCI bus
• CPU interface control
External bus interface (MEMC)
Data bus width: 32 bits/16 bits
Cycle control by hardware wait control
• SDRAM control
SDRAM is controlled in response to main memory (SDRAM) access from the PCI device
Data bus width: 16 bits/32 bits are supported
• PCI clock
33 MHz supported
SDRAM control and PCI control clocks are designed to be asynchronous
30
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
This chapter describes the block diagram, signals, register specifications, and operation specifications of the PCI
host bridge macro.
3.1 Internal Blocks of PCI Host Bridge Macro
The PCI host bridge macro consists of the four blocks shown in Figure 3-1 General Block Diagram of PCI Host
Bridge Macro. The functions of each block are described below.
(1) LM_BRIDGE: External bus interface master controller
This controller is connected to the external bus interface, responds to accesses from the CPU, and issues an
access request to the PH_FLIP_BRIDGE block of the PCI bus controller. A bus width of 16 bits or 32 bits can
be accessed from the CPU.
(2) LS_BRIDGE: External bus interface slave controller
This controller responds to accesses from the PH_FLIP_BRIDGE block of the PCI bus controller in response
to a memory data transfer request from the PCI device and issues an access request to SDRAMC.
(3) SDRAMC: External bus interface SDRAM controller
This controller is connected to the SDRAM bus. A memory request from the PCI device via the LS_BRIDGE
block is transferred by activating the SDRAM bus.
When the bus width of SDRAM is 16 bits, memory cycles of up to 8 bursts are started. When the bus width is
32 bits, memory cycles of up to 4 bursts are started.
(4) PH_FLIP_BRIDGE: External bus interface host controller
This controller is connected to the PCI bus and operates as the PCI host device.
A PCI configuration register read/write cycle, PCI IO register read/write cycle, and PCI memory read/write
cycle are started in response to a request from the LM_BRIDGE block.
Moreover, a request is issued to the LS_BRIDGE block in response to a memory data transfer request from
the PCI device connected to the PCI bus.
Figure 3-1. General Block Diagram of PCI Host Bridge Macro
PCI host bridge macro
External bus
LM_BRIDGE
interface
PCI bus
interface
PH_FLIP_BRIDGE
SDRAM bus
SDRAMC
LS_BRIDGE
interface
31
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.2 Relationship Between Internal Blocks and Signals
The I/O signals for each block of the PCI host bridge macro are as follows.
Figure 3-2. Blocks and Pin Signals of PCI Host Bridge Macro
External bus interface
I_SRST_B
PCI bus interface
I_PCLK
O_PCIRST_B
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
I_CPU_CS0_B
I_CPU_CS1_B
I_CPU_CS2_B
I_CPU_ADR0 to I_CPU_ADR19
I_CPU_DATA0 to I_CPU_DATA31
O_CPU_DATA0 to O_CPU_DATA31
EN_CPU_DATA
I_CBE0 to I_CBE3
O_CBE0 to O_CBE3
EN_CBE
LM_BRIDGE
I_FRAME_B
O_FRAME_B
EN_FRAME
I_IRDY_B
I_CPU_BE_B0 to I_CPU_BE_B3
I_CPU_WE_B
I_CPU_OE_B
O_CPU_WAIT_B
O_IRDY_B
O_PCIHOST_INT
EN_IRDY
I_MODE16
I_DEVSEL_B
O_DEVSEL_B
EN_DEVSEL
I_TRDY_B
LS_BRIDGE
PH_FLIP_BRIDGE
SDRAM bus interface
O_TRDY_B
EN_TRDY
O_HOLDREQ_B
I_HOLDACK_B
I_STOP_B
I_SDCLK
O_STOP_B
EN_STOP
O_SD_DATA0 to O_SD_DATA31
I_SD_DATA0 to I_SD_DATA31
EN_SD_DATA0, EN_SD_DATA1
O_SD_DQM_B0 to O_SD_DQM_B3
O_SD_ADR1 to O_SD_ADR25
O_SD_CKE
I_PAR
O_PAR
SDRAMC
EN_PAR
I_PERR_B
O_PERR_B
EN_PERR
O_SD_CS_B
O_SD_RAS_B
I_SERR_B
O_SD_CAS_B
I_REQ_B1 to I_REQ_B7
O_GNT_B1 to O_GNT_B7
O_SD_WR_B
EN_SD_CTL
32
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.3 Pin Functions
The pin functions of each interface are described below.
3.3.1 External bus slave interface pins
Pin Name
I/O
Input
Function
Active
I_SRST_B
System reset input
Low
Low
Low
Low
I_CPU_CS0_B
Input
PCI host bridge register chip select input
PCI I/O area chip select input
PCI memory area chip select input
CPU address input
I_CPU_CS1_B
Input
I_CPU_CS2_B
Input
I_CPU_ADR0 to I_CPU_ADR19
I_CPU_DATA0 to I_CPU_DATA31
O_CPU_DATA0 to O_CPU_DATA31
EN_CPU_DATA
Input
−
−
−
Input
CPU data input
Output
Output
Input
CPU data output
CPU data output enable output
CPU data byte enable input
CPU write data enable input
CPU read data output enable input
CPU data wait output
High
I_CPU_BE_B0 to I_CPU_BE_B3
I_CPU_WE_B
−
Input
Low
Low
Low
Low
I_CPU_OE_B
Input
O_CPU_WAIT_B
Output
Output
Input
O_PCIHOST_INT
PCI host bridge interrupt output
CPU data bus width select input
I_MODE16
Low: 32-bit width
High: 16-bit width
3.3.2 SDRAM bus interface pins
Pin Name
O_HOLDREQ_B
I/O
Output
Input
Function
SDRAM bus hold request output
SDRAM bus hold acknowledge input
SDRAM clock input
Active
Low
Low
−
I_HOLDACK_B
I_SDCLK
Input
O_SD_DATA0 to O_SD_DATA31
I_SD_DATA0 to I_SD_DATA31
EN_SD_DATA0, EN_SD_DATA1
Output
Input
SDRAM data output
−
SDRAM data input
−
Output
SDRAM data enable output
←
Low: Lower 16 bits (O_SD_DATA0 to O_SD_DATA15)
High: Higher 16 bits (O_SD_DATA16 to O_SD_DATA31)
O_SD_DQM_B0 to O_SD_DQM_B3
O_SD_ADR1 to O_SD_ADR25
O_SD_CKE
Output
Output
Output
Output
Output
Output
Output
Output
SDRAM data mask output
Low
−
SDRAM address output
SDRAM clock enable output
SDRAM chip select output
High
Low
Low
Low
Low
High
O_SD_CS_B
O_SD_RAS_B
SDRAM row address strobe output
SDRAM column address strobe output
SDRAM read/write output
O_SD_CAS_B
O_SD_WR_B
EN_SD_CTL
SDRAM control signal output enable output
(Output buffer enable of O_SD_ADR1 to O_SD_ADR25,
O_SD_CKE, O_SD_CS_B, O_SD_RAS_B,
O_SD_CAS_B, and O_SD_WR_B pins)
33
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.3.3 PCI bus interface pins
Pin Name
I/O
Input
Function
Active
I_PCLK
PCI clock input
−
O_PCIRST_B
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
Output
Input
PCI reset output
Low
PCI address/data input
PCI address/data output
−
−
Output
Output
PCI address/data output enable output
High
(Output buffer enable of O_AD0 to O_AD31)
I_CBE0 to I_CBE3
O_CBE0 to O_CBE3
EN_CBE
Input
PCI command/byte enable input
PCI command/byte enable output
Low
Low
High
Output
Output
PCI command/byte enable output enable output
(Output buffer enable of O_CBE0 to O_CBE3)
I_FRAME_B
O_FRAME_B
EN_FRAME
Input
PCI frame input
PCI frame output
Low
Low
High
Output
Output
PCI frame output enable output
(Output buffer enable of O_FRAME_B)
I_IRDY_B
O_IRDY_B
EN_IRDY
Input
PCI initiator ready input
PCI initiator ready output
Low
Low
High
Output
Output
PCI initiator ready output enable output
(Output buffer enable of O_IRDY_B)
I_DEVSEL_B
O_DEVSEL_B
EN_DEVSEL
Input
PCI device select input
PCI device select output
Low
Low
High
Output
Output
PCI device select output enable output
(Output buffer enable of O_DEVSEL_B)
I_TRDY_B
O_TRDY_B
EN_TRDY
Input
PCI target ready input
PCI target ready output
Low
Low
High
Output
Output
PCI target ready output enable output
(Output buffer enable of O_TRDY_B)
I_STOP_B
O_STOP_B
EN_STOP
Input
PCI stop input
PCI stop output
Low
Low
High
Output
Output
PCI stop output enable output
(Output buffer enable of O_STOP_B)
I_PAR
Input
PCI parity input
PCI parity output
−
−
O_PAR
EN_PAR
Output
Output
PCI parity output enable output
(Output buffer enable of O_PAR)
High
I_PERR_B
O_PERR_B
EN_PERR
Input
PCI parity error input
PCI parity error output
Low
Low
High
Output
Output
PCI parity error output enable output
(Output buffer enable of O_PERR_B)
I_SERR_B
Input
PCI system error input
PCI request input
PCI grant output
Low
Low
Low
I_REQ_B1 to I_REQ_B7
O_GNT_B1 to O_GNT_B7
Input
Output
34
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4 Registers
The registers of the PCI host bridge macro are listed below. The bit width of all registers is 32 bits.
The offset address of each register is the offset value from the base address in the area in which the
I_CPU_CS0_B pin becomes active.
Offset Address
Register Name
PCI_CONFIG_DATA
PCI_CONFIG_ADD
PCI_CONTROL
Reserved
R/W
R/W
Function
PCI configuration register access data setting
PCI configuration register access address setting
PCI bus control
00H
04H
08H
R/W
R/W
0CH
10H
PCI_IO_BASE
R/W
R/W
Sets base address of PCI bus I/O space accessed from PCI I/O
area on CPU memory map
14H
PCI_MEM_BASE
Sets base address of PCI bus memory space accessed from PCI
memory area on CPU memory map
18H
PCI_INT_CTL
R/W
R
PCI error interrupt control
1CH
PCI_ERR_ADD
Reserved
PCI error generation address retention
20H to 3FH
40H
SYSTEM_MEM_BASE
R/W
R/W
R/W
Sets base address of system memory area mapped to PCI bus
memory space
44H
SYSTEM_MEM_RANGE
Sets range of system memory area mapped to PCI bus memory
space
48H
SDRAM_CTL
Reserved
SDRAM access control
4CH to FFH
3.4.1 PCI_CONFIG_DATA register
After reset: Undefined
31
R/W
Offset address: 00H
0
CDATA
Bit Name
CDATA
R/W
Function
R/W PCI configuration register write access is executed by writing data to this field, and the data written
to this field is written to the access target register.
PCI configuration register read access is executed by reading this field, and the data of the access
target register is read.
35
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.2 PCI_CONFIG_ADD register
After reset: 00000000H
31
R/W
Offset address: 04H
0
CADD
Bit Name
CADD
R/W
Function
R/W Sets PCI configuration register address of access target.
(1) How to set PCI_CONFIG_ADD register
(a) Type 0 (PCI device)
31
11 10
8
7
2
1
0
0
0
IDSEL specification
Function
number
Register number
IDSEL specification: Selects the IDSEL signal corresponding to the access target PCI device.
Because this PCI host bridge macro uses the AD31 to AD11 signals as the IDSEL
signal for each PCI device, the AD signal connected to the IDSEL pin of each PCI
device is specified in this field. For example, if the AD31 signal is connected to the
IDSEL pin of a PCI device, access is enabled by setting bit 31 of CADD to 1.
Function number:
Register number:
Specifies the function number for a multifunction device.
Specifies the number of the access target PCI configuration register.
(b) Type 1 (PCI-PCI bridge)
31
24 23
16 15
11 10
8
7
2
1
0
0
1
Bus number
Device number
Function
number
Register number
Bus number:
Specifies the number of the PCI bus connected to the access target PCI device.
Specifies the device number of the access target PCI device.
Specifies the function number for a multifunction device.
Device number:
Function number:
Register number:
Specifies the number of the access target PCI configuration register.
36
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(2) How to access PCI configuration register
• Write access
Set the access target register address to the PCI_CONFIG_ADD register
↓
Write the access target register setting value to the PCI_CONFIG_DATA register
• Read access
Set the access target register address to the PCI_CONFIG_ADD register
↓
Read the PCI_CONFIG_DATA register
3.4.3 PCI_CONTROL register
After reset: 07000100H
31
R/W
24 23
Offset address: 08H
17 16 15
8
7
0
5
0
4
3
0
2
1
0
PCI_PARKCNT
0
0
0
0
0
0
0
PCI_REQ
Function
0
Bit Name
R/W
R/W Sets the time for shifting to bus parking.
PCI_PARKCNT
At the default value, bus parking is performed seven clocks after the bus status becomes IDLE.
The counter is started when FRAME# = High and IRDY# = High.
PCI_BPMODE
PCI_REQ
R/W Sets the bus parking master.
0: Limited to this macro
1: Master accessed last
R/W Enables/disables the REQ# signal (I_REQ_B1 to I_REQ_B7 pins) from the bus master.
Bit 0 of this field (bit 8 of the PCI_CONTROL register) is assigned to the PCI host bridge macro,
and is always 1.
0: Disabled
1: Enabled
PCI_RESET
TARGET_EN
MEM_EN
R/W Sets the reset status of the PCI bus.
0: Reset status
1: Reset released
R/W Sets the operation of the PCI bus target of the PCI host bridge macro.
0: Do not respond to main memory (SDRAM) access from the PCI device
1: Respond to main memory (SDRAM) access from the PCI device
R/W Enables/disables access from the CPU to the PCI memory area.
0: Access disabled
1: Access enabled
IO_EN
R/W Enables/disables access from the CPU to the PCI I/O area.
0: Access disabled
1: Access enabled
37
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.4 PCI_IO_BASE register
When I/O accessing the PCI bus I/O space via the PCI I/O area (area in which the I_CPU_CS1_B pin becomes
active: 64 KB), any area of the 4 GB PCI bus I/O space can be accessed by setting this register.
After reset: 00000000H
31
R/W
Offset address: 10H
16 15
0
0
0
IO_BASE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
IO_BASE
R/W
Function
R/W Sets the higher 16 bits (bits 16 to 31) of the PCI bus I/O space base address when accessing the
PCI I/O area (area in which the I_CPU_CS1_B pin becomes active) from the CPU.
3.4.5 PCI_MEM_BASE register
When memory accessing the PCI bus memory space via the PCI memory area (area in which the I_CPU_CS2_B
pin becomes active: 1 MB), any area of the 4 GB PCI bus memory space can be accessed by setting this register.
However, because the main memory (SDRAM) is mapped on the PCI bus memory space, do not overlap the area
set by the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register described later.
After reset: 80000000H
31
R/W
Offset address: 14H
20 19
0
0
M_BASE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
M_BASE
R/W
Function
R/W Sets the higher 12 bits (bits 20 to 31) of the PCI bus memory space base address when accessing
the PCI memory area (area in which the I_CPU_CS2_B pin becomes active) from the CPU.
38
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.6 PCI_INT_CTL register
The PCI_INT_CTL register shows the interrupt sources of the PCI bus error interrupt (O_PCIHOST_INT) and
controls masking and clearing of these interrupts.
This function is used only for debugging and is not used in normal operation.
After reset: 000x0F00H
31
R/W
Offset address: 18H
20 19 18 17 16 15
12 11 10
9
8
7
0
4
0
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
W
Function
CLR_SERR
CLR_PERR
CLR_MAB
CLR_TAB
Clears the PCI bus system error (SERR# reception) interrupt.
1: Cleared
W
W
W
Clears the PCI bus parity error (PERR# reception) interrupt.
1: Cleared
Clears the PCI bus master abort interrupt.
1: Cleared
Clears the PCI bus target abort interrupt.
1: Cleared
MSK_SERR
R/W Sets the mask status of the PCI bus system error (SERR# reception) interrupt.
0: Not masked
1: Masked
MSK_PERR
MSK_MAB
MSK_TAB
R/W Sets the mask status of the PCI bus parity error (PERR# reception) interrupt.
0: Not masked
1: Masked
R/W Sets the mask status of the PCI bus master abort interrupt.
0: Not masked
1: Masked
R/W Sets the mask status of the PCI bus target abort interrupt.
0: Not masked
1: Masked
SERR
R
R
R
R
Detects the occurrence status of a PCI bus system error (SERR# reception).
1: System error occurred
PERR
Detects the occurrence status of the PCI bus parity error (PERR# reception).
1: Parity error occurred
MABORT
TABORT
Detects the occurrence status of the PCI bus master abort.
1: Master abort occurred
Detects the occurrence status of the PCI bus target abort.
1: Target abort occurred
39
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.7 PCI_ERR_ADD register
The PCI_ERR_ADD register retains the PCI bus address when the following errors occur.
• System error (SERR# reception)
• Parity error (PERR# reception)
• Master abort
• Target abort
When the PCI_ERR_ADD register is read, all the bits are cleared. Once an error occurs and a value is set to the
PCI_ERR_ADD register, the first value is retained until read access is performed or a new error occurs and the value
is updated.
This function is used only for debugging and is not used in normal operation.
After reset: 00000000H
31
R
Offset address: 1CH
0
ERR_ADR
Bit Name
R/W
Function
Retains the address when a PCI bus error occurs.
ERR_ADR
R
40
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.8 SYSTEM_MEM_BASE register
When the main memory is accessed from the PCI device by setting the SYSTEM_MEM_BASE register and
SYSTEM_MEM_RANGE register, the register responds to an access of a matching address.
After reset: 00000000H
31
R/W
Offset address: 40H
16 15
0
0
0
S_BASE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
S_BASE
R/W
Function
R/W Sets the higher 16 bits (bits 16 to 31) of the base address on the PCI bus memory space in which
the main memory (SDRAM) is mapped.
3.4.9 SYSTEM_MEM_RANGE register
After reset: 0000FFFFH
31
R/W
Offset address: 44H
16 15
1
0
1
S_RANGE
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit Name
R/W
Function
S_RANGE
R/W Sets the range of the PCI bus memory space in which the main memory (SDRAM) is mapped.
It can be set in 64 KB units.
0000H: 64 KB
0001H: 128 KB
:
000FH: 1 MB
:
00FFH: 16 MB
:
0FFFH: 256 MB
:
FFFFH: 4 GB
41
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.10 SDRAM_CTL register
After reset: 00070230H
31
R/W
Offset address: 48H
CYCLE_LATENCY
24 23
16 15
13 12 11 10
9
8
7
0
6
0
5
4
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
Function
CYCLE_LATENCY
R/W Sets the latency for successive main memory (SDRAM) accesses from the PCI device.
A latency of up to 7,650 ns can be set.
00H: No latency
01H: 1 PCI clock (30 ns)
:
FFH: 255 PCI clocks (7,650 ns)
BUS_SIZE
R/W Sets the bit width of the data bus.
0: 16-bit width
1: 32-bit width
CAS_LATENCY
R/W Sets the CAS latency.
00: Setting prohibited
01: 1
10: 2
11: 3
WAIT_STATE
R/W Sets the wait interval of ACT → CMD, PRE → ACT, and CMD → ACT.
00: Setting prohibited
01: 1 clock
10: 2 clocks
11: 3 clocks
COLUMN_SIZE
R/W Sets the bit width of the column address.
00: 8-bit width
01: 9-bit width
10: 10-bit width
11: 11-bit width
42
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
The correspondence between the output address signals when the main memory (SDRAM) is accessed and the
PCI bus address signals is shown below.
Table 3-1. Row Address Output
COLUMN_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
Field Setting Value
25 to 18
25 to 18
25 to 18
25 to 18
25 to 18
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
9
00 (8 bits)
01 (9 bits)
10 (10 bits)
11 (11 bits)
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
17 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
17 16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
17 16 15 25 24 23 22 21 20 19 18 17 16 15 14 13 12
Table 3-2. Column Address Output (Precharge Command)
BUS_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
Bit Setting Value
25 to 18
25 to 18
25 to 18
17 16 15 14 13 12 11 10
17 16 15 14 12 11 10
17 16 15 14 12 11 10
9
9
9
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0 (16 bits)
1 (32 bits)
H
H
Remark H: High level
Table 3-3. Column Address Output (Read/Write Command)
BUS_SIZE
Correspondence Between PCI Bus Address Signal and Main Memory (SDRAM) Address Pins
(O_SD_ADR1 to O_SD_ADR25)
Bit Setting Value
25 to 18
17 16 15 14 13 12 11 10
17 16 15 14 12 11 10
17 16 15 14 12 11 10
9
9
9
8
8
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0 (16 bits)
1 (32 bits)
25 to 18
25 to 18
L
L
Remark L: Low level
43
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.5 Address Map
The address maps of the CPU memory space and PCI bus I/O or memory space are shown below.
Figure 3-3. CPU Memory Space/PCI Bus I/O Space Address Map
CPU memory space
PCI bus I/O space
FFFF FFFFH
IO_BASE[31:16] + FFFFH
IO_BASE[31:16] + 0000H
FFFFH
0000H
PCI I/O area
64 KB
PCI bus I/O space
64 KB
I_CPU_CS1_B area
0000 0000H
Figure 3-4. CPU Memory Space/PCI Bus Memory Space Address Map
CPU memory space
PCI bus memory space
FFFF FFFFH
M_BASE[31:16] + FFFFFH
M_BASE[31:16] + 00000H
FFFFFH
00000H
PCI memory area
1 MB
PCI memory space
1 MB
I_CPU_CS2_B area
S_BASE[31:16] + S_RANGE[31:16] + FFFFH
S_BASE[31:16] + S_RANGE[31:16] + 0000H
O_SD_CS_B output
when accessing from
PCI host bridge
Main memory
(SDRAM) area
Main memory space
0000 0000H
44
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.6 Initializing PCI Host Bridge Macro
The PCI host bridge macro must be initialized according to the following procedure to acknowledge memory
access and I/O access to the PCI bus and main memory (SDRAM) access from the PCI device.
Figure 3-5. Initializing PCI Host Bridge Macro
Internal PCI bus
reset released
PCI_CONTROL register
Set PCI_RESET bit to 1
PCI_MEM_BASE register
Set any address to M_BASE field
PCI_I/O_BASE register
PCI I/O area setting
Set any address to I/O_BASE field
PCI_CONTROL register
PCI memory area setting
Set MEM_EN and IO_EN bits to 11
SYSTEM_MEM_BASE register
Set any address to S_BASE field
SYSTEM_MEM_RANGE register
Set any value to S_RANGE field
Main memory (SDRAM)
area setting
SDRAM_CTL register
Set bit width of column address to COLUMN_SIZE field
Set number of wait clocks to WAIT_STATE field
Set CAS latency to CAS_LATENCY field
Set BUS_SIZE bit to bit width of data bus
Set latency between successive accesses to CYCLE_LATENCY field
SDRAM control setting
PCI bus control setting
PCI_CONTROL register
Set TARGET_EN bit to 1
Set required bit of PCI_REQ field to 1
45
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.7 Bus Width of External Bus Interface
The operation mode of the data bus with respect to the external bus interface can be changed via the I_MODE16
pin status.
Cautions 1. Do not change the status of the I_MODE16 pin during operation.
2. The I_MODE16 pin can only be used to change the operation mode of the data bus with
respect to the external bus slave interface.
To change the data bus width of the SDRAM bus interface, use the BUS_SIZE bit in 3.4.10
SDRAM_CTL register.
3. The setting of the I_MODE16 pin should correspond with the external bus interface operation
mode of the CPU.
4. When 16-bit mode is set, the access cycle is divided for 32-bit access on the external bus
interface. Accordingly, access is divided similarly on the PCI bus interface. Therefore, when
16-bit mode is set, because a 32-bit access cycle is not generated on the PCI bus interface, a
PCI device whose registers are only valid for 32-bit access cannot be accessed.
Table 3-4. I_MODE16 Pin Status and Operation Mode of Data Bus
I_MODE16 Pin
Low level
High level
Data Bus Operation Mode
32-bit mode
Remark
32-bit data bus
16-bit data bus
16-bit mode
46
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.8 Timing
The timing for each interface of the PCI host bridge macro is shown below.
3.8.1 External bus interface timing
CPU write/CPU read access is performed from the CPU using the bus interface (Figures 3-6 and 3-7).
When accessing SDRAM from the PCI host bridge macro, bus hold is performed and the main memory is
write/read accessed (Figures 3-8 to 3-10).
Figure 3-6. CPU Write Access
I_PCLK
I_CPU_CSx_B
I_CPU_ADR0 to
Valid
I_CPU_ADR19
I_CPU_BE_B0 to
0000
1111
1111
I_CPU_BE_B3
I_CPU_WE_B
I_CPU_WAIT_B
I_CPU_DATA0 to
I_CPU_DATA31
Valid
Remark x = 0 to 2
Figure 3-7. CPU Read Access
I_PCLK
I_CPU_CSx_B
I_CPU_ADR0 to
I_CPU_ADR19
Valid
0000
I_CPU_BE_B0 to
I_CPU_BE_B3
1111
1111
I_CPU_OE_B
I_CPU_WAIT_B
I_CPU_DATA0 to
I_CPU_DATA31
Valid
EN_CPU_DATA
Remark x = 0 to 2
47
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Figure 3-8. Hold Request/Hold Acknowledge
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
EN_SD_CTL
SDRAM control
signal output
Figure 3-9. Main Memory (SDRAM) Write Access (8-Burst)
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
O_SD_WR_B
O_SD_ADR1 to
O_SD_ADR25
RA
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7
O_SD_DATA0 to
O_SD_DATA31
O_SD_DQM_B0 to
O_SD_DQM_B3
1111
1111
Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10
48
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Figure 3-10. Main Memory (SDRAM) Read Access (8-Burst)
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
O_SD_WR_B
O_SD_ADR1 to
O_SD_ADR25
RA
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
I_SD_DATA0 to
I_SD_DATA31
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
O_SD_DQM_B0 to
O_SD_DQM_B3
0000
1111
1111
Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10
49
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.8.2 PCI bus interface timing
The PCI host bridge macro supports the following PCI bus interface timing.
(1) PCI bus master cycle timing
The timing of access from the CPU to the PCI device is shown below.
(a) Configuration read/write cycle, I/O read/write cycle, and memory read/write cycle
(i) Read cycle
Timing type: Configuration register read, internal I/O register read, memory read
Figure 3-11. Read Cycle
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
H
STOP#
(ii) Write cycle
Timing type: Configuration register write, internal I/O register write, memory write
Figure 3-12. Write Cycle
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
H
STOP#
50
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(b) Target abort cycle
Timing type: Target abort
Figure 3-13. Target Abort Cycle
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
H
TRDY#
STOP#
(c) Master abort cycle
Timing type: Master abort cycle
Figure 3-14. Master Abort Cycle
PCICLK
AD
FRAME#
IRDY#
H
H
H
DEVSEL#
TRDY#
STOP#
PAR
51
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(d) Data parity error
Timing type: Single read & write cycle data parity error
Figure 3-15. Data Parity Error
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
H
PERR#
(2) PCI bus slave cycle timing
The timing of access from the PCI device to SDRAM is shown below.
(a) Memory single read cycle
Timing type: Memory single read cycle
Figure 3-16. Single Read Cycle
PCICLK
REQ#
GNT#
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
52
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(b) Memory single write cycle
Timing type: Memory single write cycle
Figure 3-17. Single Write Cycle
PCICLK
REQ#
GNT#
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
(c) Burst read cycle
Timing type: Memory burst read cycle − Not disconnect
Figure 3-18. Burst Read Cycle
PCICLK
REQ#
GNT#
AD
0
1
2
3
4
5
6
7
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
H
53
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(d) Burst write cycle
Timing type: Memory burst write cycle − Not disconnect
Figure 3-19. Burst Write Cycle
PCICLK
REQ#
GNT#
AD
0
1
2
3
4
5
6
7
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
H
(e) Abort cycle
Timing type: Target abort cycle & master abort cycle
Figure 3-20. Abort Cycle
PCICLK
REQ#
GNT#
AD
FRAME#
IRDY#
DEVSEL#
H
TRDY#
STOP#
SERR#
54
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(f) Data parity error
(i) Read data parity error 1
Timing type: Single read cycle data parity error
Figure 3-21. Read Data Parity Error
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
H
PERR#
(ii) Read data parity error 2
Timing type: Burst read cycle data parity error
Figure 3-22. Read Data Parity Error 2
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
PERR#
55
Application Note U17121EJ1V1AN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
(iii) Write data parity error 1
Timing type: Single write cycle data parity error
Figure 3-23. Write Data Parity Error 1
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
H
PERR#
SERR#
(iv) Write data parity error 2
Timing type: Burst write cycle data parity error
Figure 3-24. Write Data Parity Error 2
PCICLK
AD
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
PERR#
SERR#
56
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
This chapter describes configuration examples in which the PCI host bridge macro is integrated in an FPGA
(Altera’s EP20K200EQC240-1X).
4.1 Conditions for Configuration Examples of FPGA Integration
The conditions in the configuration examples are as follows.
(1) CPU:
V850E/ME2
(2) Bus width of external bus interface: 32 bits
(3) CS space of PCI host bridge:
(4) CS space of SDRAM:
(5) SDRAM:
CSZ6
CSZ3
Connecting two 16 M × 16 SDRAMs (4 M × 16 × 4 banks)
(6) PCI connection:
2 devices
4.2 Points to Remember When Creating Top Layer of FPGA
Points to remember when integrating the PCI host bridge macro with an FPGA are indicated below.
(1) First decode the chip select from the address before creation.
• I_CPU_CS0_B: PCI host bridge register chip select
(Offset address in 3.4 Registers)
• I_CPU_CS1_B: PCI I/O area chip select
(See Figure 3-3 CPU Memory Space/PCI Bus I/O Space Address Map)
• I_CPU_CS2_B: PCI memory area chip select
(See Figure 3-4 CPU Memory Space/PCI Bus Memory Space Address Map)
(2) Because the buffers of the address bus and data bus for the expansion bus interface are output when the PCI
host bridge controls SDRAM, they become bidirectional pins via the selector.
The following pins that control SDRAM become 3-state output.
• DQM0 to DQM3, SDCKE, SDCS, SDRAS, SDCAS, SDWEZ
(3) The following PCI bus interface pins become bidirectional pins.
• AD, CBE, FRAME, IRDY, DEVSEL, TRDY, STOP, PAR, PERR
(4) There are three interrupt request output signals: one is output from the PCI host bridge; the remaining two are
INTA and INTB signals from the external PCI slot and are directly connected to the CPU.
57
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.3 Reference Diagram for FPGA Top Connection
The reference diagram for connecting the PCI host bridge macro with the FPGA top layer is shown below.
FPGA top
PCI host bridge macro
VBRESETZ
CSZ6
I_SRST_B
I_PCLK
PCLK
I_CPU_CS0_B
I_CPU_CS1_B
I_CPU_CS2_B
O_PCIRST_B
PCIRST
Address
decoder
RA21 to
RA25
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
AD0 to
AD31
RA0
I_CPU_ADR0
I_CPU_ADR1 to I_CPU_ADR19
I_CBE0 to I_CBE3
CBE0 to
CBE3
RA1 to RA25
O_SD_ADR1 to O_SD_ADR25 O_CBE0 to O_CBE3
EN_CBE
I_CPU_DATA0 to I_CPU_DATA31
I_FRAME_B
I_SD_DATA0 to I_SD_DATA31
O_FRAME_B
FRAME
IRDY
RD0 to RD31
O_CPU_DATA0 to O_CPU_DATA31
Selector
EN_FRAME
O_SD_DATA0 to O_SD_DATA31
I_IRDY_B
EN_CPU_DATA
O_IRDY_B
EN_SD_DATA0, EN_SD_DATA1
EN_IRDY
BENZ0 to
BENZ3
I_CPU_BE_B0 to I_CPU_BE_B3
I_DEVSEL_B
WRZ0
RDZ
I_CPU_WE_B
O_DEVSEL_B
DEVSEL
TRDY
STOP
PAR
I_CPU_OE_B
EN_DEVSEL
WAITZ
O_CPU_WAIT_B
I_TRDY_B
O_TRDY_B
HLDRQZ
HLDAKZ
SDCLK
O_HOLDREQ_B
EN_TRDY
I_HOLDACK_B
I_STOP_B
I_SDCLK
O_STOP_B
DQM0 to
DQM3
EN_STOP
O_SD_DQM_B0 to O_SD_DQM_B3
I_PAR
SDCKE
SDCS
O_SD_CKE
O_PAR
EN_PAR
O_SD_CS_B
I_PERR_B
SDRASZ
SDCASZ
SDWEZ
O_SD_RAS_B
O_SD_CAS_B
O_PERR_B
EN_PERR
PERR
SERR
I_SERR_B
O_SD_WR_B
EN_SD_CTL
EN_SDCLK
I_REQ_B1
I_REQ_B2
REQ1
REQ2
Open
I_REQ_B3 to I_REQ_B7
Internal H
fixed input
O_GNT_B1
O_GNT_B2
GNT1
GNT2
O_GNT_B3 to O_GNT_B7
Open
O_PCIHOST_IN
INT0
INT1
INT2
INTA
INTB
58
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.4 FPGA Top Pin Functions
The pin information when integrating the PCI host bridge macro with an FPGA is shown below.
4.4.1 CPU bus slave interface pins
Pin Name
VBRESETZ
I/O
Input
Function
System reset input
CSZ6
Input
I/O
PCI host bridge chip select input
CPU address I/O
RA0 to RA25
RD0 to RD31
BENZ0 to BENZ3
WRZ
I/O
CPU data I/O
Input
Input
Input
Output
Output
CPU data byte enable input
CPU data write enable input
CPU data read enable input
CPU data wait output
RDZ
WAITZ
INT0
PCI host bridge interrupt output
4.4.2 SDRAM bus interface pins
Pin Name
HLDREQZ
I/O
Output
Input
Function
SDRAM bus hold request output
SDRAM bus hold acknowledge input
SDRAM clock input
HLDACKZ
SDCLK
Input
SDCKE
Output
Output
Output
Output
Output
Output
SDRAM clock enable output
SDRAM chip select output
SDCS
SDRASZ
SDCASZ
SDWEZ
SDRAM row address strobe output
SDRAM column address strobe output
SDRAM read/write output
DQM0 to DQM3
SDRAM output disable output
59
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.4.3 PCI bus interface pins
Pin Name
I/O
Input
Function
PCLK
PCI clock input
PCI reset output
PCIRST
AD0 to AD31
CBE0 to CBE3
FRAME
Output
I/O
PCI address/data I/O
PCI command/byte enable I/O
PCI frame I/O
I/O
I/O
IRDY
I/O
PCI initiator ready I/O
PCI device select I/O
PCI target ready I/O
PCI stop I/O
DEVSEL
TRDY
I/O
I/O
STOP
I/O
PAR
I/O
PCI parity I/O
PERR
I/O
PCI parity error I/O
PCI system error input
PCI request input
SERR
Input
Input
Output
Output
REQ1, REQ2
GNT1, GNT2
INT1, INT2
PCI grant output
PCI INTA, INTB output
60
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5 FPGA Top Pin Configuration
The connection diagram of the PCI host bridge macro pins in an FPGA is shown below.
4.5.1 Internal connection diagram of external bus interface
FPGA top
VBRESETZ
RESET
CS6
PCI host
bridge macro
I_SRST_B
CS6
I_CPU_CS0_B
Address
I_CPU_CS1_B
decoder
I_CPU_CS2_B
RA0
A0
I_SRST_B
I_CPU_ADR1 to I_CPU_ADR19
RA1 to RA25
A1 to A25
O_SD_ADR1 to O_SD_ADR25
I_CPU_DATA0 to I_CPU_DATA31
I_SD_DATA0 to I_SD_DATA31
O_CPU_DATA0 to O_CPU_DATA31
O_SD_DATA0 to O_SD_DATA31
EN_CPU_DATA
RD0 to RD31
D0 to D31
Selector
Selector
EN_SD_DATA0, EN_SD_DATA1
BENZ0 to BENZ3
I_CPU_BE_B0 to I_CPU_BE_B3
DQM0 to DQM3 xxBE/xxDQM
O_SD_DQM_B0 to O_SD_DQM_B3
I_CPU_WE_B
O_SD_WR_B
WRZ
WE/WR
RDZ
RD
WAIT
I_CPU_OE_B
O_CPU_WAIT_B
O_PCIHOST_INT
O_HOLDRQ_B
I_HOLDACK_B
O_SD_CKE
WAITZ
INT0
INTP10
HLDRQ
HLDAK
SDCKE
HLDRQZ
HLDAKZ
SDCKE
SDCSZ
CS3
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
SDRASZ
SDRAS
SDCASZ
SDCLK
SDCAS
BUSCLK
I_SDCLK
EN_SD_CTL
I/O buffer
61
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5.2 Internal connection diagram of PCI bus interface
FPGA top
PCLK
CLK
PCI host
bridge macro
I_PCLK
PCIRST
RST#
O_PCIRST_B
I_AD0 to I_AD31
O_AD0 to O_AD31
EN_AD
AD0 to AD31
AD0 to AD31
I_CBE0 to I_CBE3
O_CBE0 to O_CBE3
EN_CBE
CBE0 to CBE3 C/BE0# to C/BE3#
I_FRAME_B
O_FRAME_B
EN_FRAME
FRAME
IRDY
FRAME#
IRDY#
I_IRDY_B
O_IRDY_B
EN_IRDY
I_DEVSEL_B
O_DEVSEL_B
EN_DEVSEL
DEVSEL
TRDY
STOP
PAR
DEVSEL#
TRDY#
STOP#
PAR
I_TRDY_B
O_TRDY_B
EN_TRDY
I_STOP_B
O_STOP_B
EN_STOP
I_PAR
O_PAR
EN_PAR
I_PERR_B
O_PERR_B
EN_PERR
PERR
PERR#
SERR#
SERR
I_SERR_B
REQ1, REQ2
GNT1, GNT2
REQ1#, REQ2#
GNT1#, GNT2#
I_REQ_B1, I_REQ_B2
I_REQ_B3 to I_REQ_B7
H fixed
Open
O_GNT_B1, O_GNT_B2
O_GNT_B3 to O_GNT_B7
I/O buffer
62
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5.3 External connection diagram of external bus interface (example of connection with V850E/ME2)
System reset
FPGA
SDRAM1
A0 to A12
(PCI host bridge)
SDRAM2
VBRESETZ
RA2 to RA14
RA24, RA25
RD0 to RD31
BA0, BA1
DQ0 to DQ31
DQM0, DQM1
/WE
BENZ0 to BENZ3
WRZ
DQM2, DQM3
SDCKE
SDCS
CKE
/CS
SDRASZ
SDCASZ
SDCLK
RDZ
/RAS
/CAS
CLK
WAITZ
INT0
HLDRQZ
HLDAKZ
V850E/ME2
RESET
HLDAK
HLDRQ
INTPxxx
WAIT
RD
A0 to A22
A24, A25
D0 to D31
xxBE/xxDQM
WR/WE
SDCKE
CSx
SDRAS
SDCAS
BUSCLK
Remarks 1. This is an example using two SDRAMs of 4 M words × 16 bits × 4 banks (row address: 13 bits,
column address: 9 bits).
2. xx: LL, LU, UL, UU
63
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.5.4 External connection diagram of PCI bus interface
PCI bus clock
PCI host bridge
PCI device 1
AD00 to AD31
IDSELNote
PCLK AD00 to AD31
CLK
CBE0 to CBE3
PCIRST
FRAME
IRDY
C/BE0# to C/BE3#
RST#
FRAME#
IRDY#
DEVSEL
TRDY
DEVSEL#
TRDY#
STOP#
PAR
STOP
PAR
PERR
PERR#
SERR#
REQ#
SERR
REQ1
GNT1
GNT#
PCI device
AD00 to AD31
IDSELNote
C/BE0# to C/BE3#
RST#
CLK
FRAME#
IRDY#
DEVSEL#
TRDY#
STOP#
PAR
PERR#
SERR#
REQ2
GNT2
REQ#
GNT#
Note Connect one of the AD31 to AD11 signals to the IDSEL pin of each PCI device.
64
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
4.6 Cautions on Designing FPGA
Cautions when fitting an FPGA using Altera’s “Quartusll Design Software” are shown below.
4.6.1 FPGA fitting design
(1) Set the “I/O Standard” buffer type to “3.3-V PCI” for the following PCI bus interface pins.
Pin Name/Usage
INTA
Dir
I/O Standard
3.3-V PCI
input
input
bidir
INTB
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
3.3-V PCI
FRAME
DEVSEL
REQ1
bidir
input
input
output
output
bidir
REQ2
GNT1
GNT2
IRDY
TRDY
bidir
STOP
bidir
PCIRST
AD0 to AD31
CBE0 to CBE3
PAR
output
bidir
bidir
bidir
PERR
bidir
SERR
input
(2) Determine the pin assignment taking equal length wiring into consideration for the PCI bus interface pins.
(3) Specify the “PCLK” and “SDCLK” signals as Global CLK.
4.6.2 PCI bus interface timing parameters (as constraint of PCI CLK = 33 MHz)
Adjust the timing so that the following PCI specification values are satisfied.
(1) Input setup time to CLK point to point
Pin
REQ1, REQ2
Other PCI pins
Setup
Hold
10 ns
7 ns
0 ns
0 ns
65
Application Note U17121EJ1V1AN
CHAPTER 4 CONFIGURATION EXAMPLES OF FPGA INTEGRATION
(2) CLK to signal valid delay signals
Pin
All PCI pins
MIN.
MAX.
2 ns
11 ns
The following specification values apply to the PCI bus timing (PCI CLK = 33 MHz).
Figure 4-1. Output Timing
CLK
T
VAL
Output delay
Figure 4-2. Input Timing
CLK
TSU
TH
Inputs
valid
Input
Table 4-1. 33 MHz Timing Parameters
Symbol
Parameter
MIN. (ns)
MAX. (ns)
TVAL
CLK to signal valid delay bused signals
2
2
11
12
TVAL (ptp)
TSU
CLK to signal valid delay point to point signals
Input setup time to CLK bused signals
Input setup time to CLK point to point signals
Input hold time from CLK
7
TSU (ptp)
TH
10
0
4.6.3 SDRAM interface timing
The timing for interfacing with SDRAM depends on the external bus interface and the SDRAM to be connected.
Adjust the timing to suit the system.
66
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
This chapter introduces the configuration of an evaluation board that mounts the V850E/ME2, as well as program
examples.
This is an example of an application used to operate a HDD with an IDE controller mounted on the PCI connecter.
5.1 Block Diagram of Evaluation Board
A block diagram of the evaluation board is shown below.
Figure 5-1. Block Diagram of Evaluation Board
N-Wire
connector
PCI host evaluation board
V850E/ME2
(176-pin LQFP)
MEMC bus
SDRAM
(64 MB)
SRAM
(1 MB)
PCI bus
PCI host
bridge macro
Flash
memory
PCI-IDE
controller
7-segment/
SW
Hard disk drive
ROM socket
(for emulation)
67
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.2 Specifications of Evaluation Board
The specifications of the evaluation board are as follows.
Table 5-1. Specifications of Evaluation Board
Item
Description
CPU
V850E/ME2
30 MHz
CPU operating frequency
MEMC bus operating frequency
30 MHz
Evaluation board memory
Flash memory
SRAM
CSZ0 area (32-bit width): 8 MB
CSZ1 area (32-bit width): 1 MB
CSZ3 area (32-bit width): 64 MB
SDRAM
Evaluation board peripheral I/O
PCI host bridge
Other
CSZ6 area (32-bit width): PCI Rev.2.1 compliant host interface (33 MHz)
7-segment display
7-segment display × 2 can be controlled by V850E/ME2 general-purpose port
The device numbers of the PCI bus are assigned as follows.
Table 5-2. IDSEL Connection
Slot
Device Number
Remark
PCI Slot 1 (J2)
PCI Slot 2 (J3)
AD31
AD30
Connect AD31 to IDSEL
Connect AD30 to IDSEL
68
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.3 Example of Evaluation Board Connection Circuit
A circuit example of connection of the V850E/ME2 with SDRAM, FPGA, and a PCI device (slot) is shown below.
Figure 5-2. Example of Evaluation Board Connection Circuit
System reset
PCI bus clock
V850E/ME2
RESET
FPGA
(PCI host bridge)
PCI device
CLK
VBESTZ
PCLK
PCIRST
CS6
CSZ6
RST#
CS3
A0 to A25
RD
AD0 to AD31
AD0 to AD31
IDSEL#
RA0 to RA25
RD0 to RD25 CBE0 to CBE3
C/BE#0 to C/BE#3
FRAME#
IRDY#
xxBE
BENZ0 to BENZ3
WRZ0 to WRZ3
RDZ
FRAME
IRDY
xxWR
RD
DEVSEL
TRDY
STOP
PAR
DEVSEL#
TRDY#
WAIT
WAITZ
INT0
INT0
STOP#
PAR
INT1
INT1
INT2
INT2
PERR
SERR
REQ1
GNT1
INTA
PERR#
SERR#
REQ#
HLDRQ
HLDAK
HLDRQZ
HLDAKZ
DQM0 to DQM3
SDCLK
GNT#
BUSCLK
SDCKE
INT#
SDCKE
SDCS
PCI device
SDRAS
SDCAS
WE
SDRASZ
SDCASZ
SDWEZ
CLK
RST#
AD0 to AD31
IDSEL#
C/BE#0 to C/BE#3
FRAME#
IRDY#
SDRAM
SDRAM
A0 to A12 A2 to A14
DEVSEL#
TRDY#
A24, A25
BA0, BA12
STOP#
D0 to D31
DQM2,
DQM3
PAR
DQM0, DQM1
CLK
PERR#
SERR#
CKE
REQ2
GNT2
INTB
REQ#
CS
GNT#
RAS
INT#
CAS
WE
Remark xx: LL, LU, UL, UU
69
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.4 Evaluation Board Memory Space
The evaluation board memory space is shown below.
Figure 5-3. Evaluation Board Memory Space
FFF FFFFH
On-chip peripheral
I/O area (4 KB)
On-chip data RAM area
(16 KB)
FFF F000H
FFF EFFFH
FFF B000H
FFF AFFFH
Access-prohibited area
FFF 8000H
FFF 7FFFH
Area 3
(64 MB)
PCI host bridge
CS area
CFF FFFFH
C80 0000H
CSZ6
PCI host
bridge area
(8 MB)
(63.9 MB)
C00 0000H
BFF FFFFH
Reserved area
(area 2 = 64 MB)
Area 2
(64 MB)
800 0000H
7FF FFFFH
256 MB
7FF FFFFH
CSZ3
External
SRAM area
(64 MB)
Area 1
(64 MB)
SDRAM area
(area 1 = 64 MB)
400 0000H
400 0000H
3FF FFFFH
On-chip peripheral
I/O mirror (4 KB)
On-chip data RAM mirror
(16 KB)
3FF F000H
3FF EFFFH
3FF B000H
3FF AFFFH
Access-prohibited area
3FF 8000H
3FF 7FFFH
SRAM area
(56 MB)
Area 0
(64 MB)
08F FFFFH
CSZ1
External SRAM area
(1 MB)
080 0000H
07F FFFFH
080 0000H
07F FFFFH
CSZ0
ROM area
(7 MB)
Flash memory area
(7 MB)
010 0000H
00F FFFFH
000 0000H
On-chip instruction
RAM area (1 MB)
70
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
The PCI memory I/O space is assigned to the CSZ6 area.
The base address of the PCI memory space is set to CC0 0000H.
The base address of the PCI I/O space is set to C80 0000H.
Figure 5-4. Comparison Between CPU Memory Space and PCI Memory Space
PCI memory space
PCI memory area
CPU memory space
PCI memory area
FFFF FFFFH
CFF FFFFH
CS6 area (4 MB)
CC0 0000H
PCI_MEM_BASE[31:22] + 3F FFFFH
PCI_MEM_BASE[31:22] + 00 0000H
Main memory area
(SDRAM)
Main memory area
(SDRAM)
SYSTEM_MEM_BASE
SYSTEM_MEM_BASE
0000 0000H
SYSTEM_MEM_BASE
SYSTEM_MEM_BASE
Figure 5-5. Comparison Between CPU Memory Space and PCI I/O Space
PCI I/O space
CPU memory space
FFFF FFFFH
CBF FFFFH
PCI bridge I/O area
PCI I/O area
CA0 0000H
CS6 area (4 MB)
C80 0000H
PCI_MEM_BASE[31:21] + 1F FFFFH
PCI_MEM_BASE[31:21] + 00 0000H
PCI I/O area
(2 MB)
0000 0000H
71
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.5 Sample Program Examples
This sample program is assumed to be used in an environment with the PCI-IDE board connected to the
V850E/ME2 evaluation board as the PCI device.
The PCI-IDE board is connected to the IDE HDD, and the sample program accesses the IDE HDD.
5.5.1 Development tools
(1) MULTITM 1.8.9
Integrated development environment made by Green Hills SoftwareTM, Inc.
(2) PCI-IDE board
IDE card of PCI interface connected to evaluation board.
Used by connecting IDE HDD in this application.
5.5.2 Program configuration
The sample program configuration is shown below.
(1) PCI host bridge macro initialization sample program list
First the PCI host bridge macro must be initialized for the CPU to access the PCI area.
The correspondence between the PCI memory space and CPU memory space, the interrupts from PCI, and
access control from the CPU to the PCI memory space are set by the PCI host bridge macro registers.
(2) PCI configuration space access sample program list
When initialization of the PCI host bridge macro ends, initialization of each PCI device connected to the PCI
bus is performed. Initialization is performed mainly by setting the configuration space registers existing in
each PCI device. The configuration space registers can be accessed only by executing a configuration cycle
using the PCI_CONFIG_ADD and PCI_CONFIG_DATA registers described in the register descriptions.
(3) IDE HDD access sample program list
When initialization of the PCI host bridge macro and PCI devices ends, the PCI device can actually be
operated. The PCI device is operated by setting the registers assigned to the configuration space and PCI I/O
area.
The IDE bus setting is performed and the IDE HDD is actually accessed by operating the PCI-IDE board
registers in this sample code.
72
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.5.3 V850E/ME2 PCI host bridge macro initialization sample program list
/////////////////////////////////////////////////////////////////
// V850E/ME2 - PCI Host Bridge Macro initialization sample
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Overview: Initializes PCI Host Bridge Macro by setting
PCI Bridge IO area register group.
Specific initialization is described in
function PCI_HBM_Init().
PCI_HBM_Init() is called after functions required for
accessing Host Bridge Macro, such as CPU and peripheral //
I/O, are initialized.
//
//
/////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
// Defines base address of PCI area and SDRAM area.
// Start address of PCI area is 0C80_0000H, and start address //
// of SDRAM area is 0400_0000H in this application. //
/////////////////////////////////////////////////////////////////
//
#define BASE_ADDRESS_ME2PCIIF
(0x0C800000)
#define BASE_ADDRESS_PCI_IO
#define BASE_ADDRESS_PCI_BRIDGE_IO
#define BASE_ADDRESS_PCI_MEM
(BASE_ADDRESS_ME2PCIIF)
(BASE_ADDRESS_ME2PCIIF + 0x00200000)
(BASE_ADDRESS_ME2PCIIF + 0x00400000)
#define BASE_ADDRESS_SDRAM
#define RANGE_SDRAM
(0x04000000)
(0x03FFFFFF) // 64MB
////////////////////////////////////////////////////////
// PCI Host Bridge Macro register address definition //
////////////////////////////////////////////////////////
#define PHBMR_PCI_CONFIG_DATA
#define PHBMR_PCI_CONFIG_ADD
#define PHBMR_PCI_CONTROL
#define PHBMR_PCI_IO_BASE
#define PHBMR_PCI_MEM_BASE
#define PHBMR_PCI_INT_CTL
#define PHBMR_PCI_ERR_ADD
#define PHBMR_SYSTEM_MEM_BASE
#define PHBMR_SYSTEM_MEM_RANGE
#define PHBMR_SDRAM_CTL
(BASE_ADDRESS_PCI_BRIDGE_IO+0x00)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x04)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x08)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x10)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x14)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x18)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x1C)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x40)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x44)
(BASE_ADDRESS_PCI_BRIDGE_IO+0x48)
///////////////////////////////////////////
// Macro definition for register access //
///////////////////////////////////////////
#define V850EME2_REGW(x)
*((volatile unsigned int *)((int)x))
73
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
/////////////////////////////////////////////////////////////////////////
// Function name: PCI_HBM_Init
// Function: Initializes PCI Host Bridge Macro.
// Argument: None
//
//
//
//
// Return value: None
// Remark: Base addresses of this initialization sample are as follows.//
//
//
//
//
//
//
//
//
- Base address of PCI I/O space:
0C80_0000H
//
//
//
//
//
//
//
//
- Base address of PCI memory space: 0CC0_0000H
- Base address on PCI bus memory space in which
main memory (SDRAM) is mapped:
0400_0000H
- Range of PCI bus memory space in which
main memory (SDRAM) is mapped:
Other settings are required according to system
requirements and mounting.
03FF_FFFFH
/////////////////////////////////////////////////////////////////////////
void PCI_HBM_Init(void)
{
V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000110;
// PCI_CONTROL register
// bit 31-24: PCI_PARKCNT = 1
//
// bit 15-08: PCI_REQ = 1
// bit 4: PCI_RESET bit = 1 (Release PCI bus reset)
(Set time for shifting to bus parking to 7)
(Enable I_REQ_B0)
V850EME2_REGW(PHBMR_PCI_IO_BASE) = BASE_ADDRESS_PCI_IO;
// PCI_IO_BASE register
// Set PCI I/O space base address to C800000H.
V850EME2_REGW(PHBMR_PCI_MEM_BASE) = BASE_ADDRESS_PCI_MEM;
// PCI_MEM_BASE register
// Set PCI memory space base address to CC00000H.
V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000113;
// PCI_CONTROL register
//
//
//
//
//
//
//
//
bit 31-24: PCI_PARKCNT = 1
(Set time for shifting to bus parking to 7)
bit 15-08: PCI_REQ = 1 (Enable I_REQ_B0)
bit
bit
4: PCI_RESET bit = 1 (Release PCI bus reset)
1: PCI_MEM_EN bit = 1
(Enable access from CPU to PCI memory area)
0: PCI_IO_EN bit = 1
bit
(Enable access from CPU to PCI I/O area)
V850EME2_REGW(PHBMR_SYSTEM_MEM_BASE) = BASE_ADDRESS_SDRAM;
// SYSTEM_MEM_BASE register
// Set base address on PCI bus memory space in which main
// memory (SDRAM) is mapped to 4000000H.
74
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
V850EME2_REGW(PHBMR_SYSTEM_MEM_RANGE) = RANGE_SDRAM;
// SYSTEM_MEM_RANGE register
// Set range of PCI bus memory space in which main
// memory (SDRAM) is mapped to 3FFFFFFH (64 MB).
V850EME2_REGW(PHBMR_SDRAM_CTL) = 0x00071211;
// SDRAM_CTL register
// bit 23-16: CYCLE_LATENCY = 07H
//
(Set latency for successive main memory
(SDRAM) access from PCI device to 210 ns)
//
// bit
//
12: BUS_SIZE = 1B
(Set bit width of data bus to 32 bits)
// bit 09-08: CAS_LATENCY = 10B (Set CAS latency to 2)
// bit 05-04: WAIT_STATE = 01B
//
//
(Set wait interval of ACT → CMD, PRE → ACT,
and CMD → ACT to 1 clock)
// bit 01-00: COLUMN_SIZE = 01B
//
(Set bit width of column address to 9 bits)
V850EME2_REGW(PHBMR_PCI_CONTROL) = 0x07000717;
// bit 31-24: PCI_PARKCNT = 1
//
(Set time for shifting to bus parking to 7)
// bit 15-08: PCI_REQ = 1
(Enable I_REQ_B0)
// bit
// bit
//
4: PCI_RESET bit = 1 (Release PCI bus reset)
1: PCI_MEM_EN bit = 1
(Enable access from CPU to PCI memory area)
0: PCI_IO_EN bit = 1
// bit
//
(Enable access from CPU to PCI I/O area)
return;
}
/////////////////////////////////////////////////////////////////
// Function name: main
//
//
//
//
// Function: Initializes PCI Host Bridge Macro.
// Argument: None
// Return value: 0: Normal end
/////////////////////////////////////////////////////////////////
int main(void)
{
// Initializes PCI Host Bridge Macro.
PCI_HBM_Init();
return 0;
}
75
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.5.4 PCI configuration space access sample program list
/////////////////////////////////////////////////////////////////////////
// PCI configuration space access sample
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Overview: Configuration space is accessed using procedure
shown below.
1) Write 32-bit value indicating PCI device, function
number, and register number to be accessed to
PCI_CONFIG_ADD register of PCI Host Bridge Macro.
2) When reading configuration space register, read
(word access) 32-bit value in PCI_CONFIG_DATA
register of PCI Host Bridge Macro.
When writing to configuration space register, write
(word access) 32-bit value to PCI_CONFIG_DATA register //
of PCI Host Bridge Macro.
//
//
//
//
//
//
//
//
This procedure is combined in functions PCI_ConfigRead
and PCI_ConfigWrite shown below.
Function PCI_Config_BaseAddressInit uses function
PCI_ConfigWrite to set base address register in
configuration space.
/////////////////////////////////////////////////////////////////////////
//////////////////////
// Type declaration //
//////////////////////
typedef char
BYTE;
typedef short int
HWORD;
WORD;
typedef int
typedef unsigned char
typedef unsigned short int
typedef unsigned int
UBYTE;
UHWORD;
UWORD;
VUBYTE;
VUHWORD;
VUWORD;
typedef volatile unsigned char
typedef volatile unsigned short int
typedef volatile unsigned int
/////////////////////////////////////////////////////////////////
// Function name: PCI_ConfigRead
//
//
// Function: Reads 32-bit value in PCI configuration space.
// Argument: ConfigAdd: Register address of configuration space//
// Return value: Read configuration space register data //
/////////////////////////////////////////////////////////////////
UWORD PCI_ConfigRead(UWORD ConfigAdd)
{
V850EME2_REGW(PHBMR_PCI_CONFIG_ADD) = ConfigAdd;
return V850EME2_REGW(PHBMR_PCI_CONFIG_DATA);
}
76
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
/////////////////////////////////////////////////////////////////
// Function name: PCI_ConfigWrite
//
//
// Function: Writes 32-bit value to PCI configuration space.
// Argument: ConfigAdd: Register address of configuration space//
// ConfigData: Register data of configuration space //
// Return value: None //
/////////////////////////////////////////////////////////////////
void PCI_ConfigWrite(UWORD ConfigAdd, UWORD ConfigData)
{
V850EME2_REGW(PHBMR_PCI_CONFIG_ADD) = ConfigAdd;
V850EME2_REGW(PHBMR_PCI_CONFIG_DATA) = ConfigData;
return;
}
/////////////////////////////////////////////////////////////////////////
// Function name: PCI_Config_BaseAddressInit
// Function: Sets base address of configuration space.
// Argument: None
//
//
//
//
//
//
//
//
//
//
//
//
// Return value: None
// Details: Sets base address register of offset 10H to 24H in
//
//
//
//
//
//
//
configuration space of PCI device connected to AD30
signal by IDSEL as follows.
ATA Command Register Base Address (10H)
ATA Control Register Base Address (14H)
:
:
0C80_0000H
0C80_0008H
Bus Master Control Register Base Address(18H) : 0C80_0010H
/////////////////////////////////////////////////////////////////////////
void PCI_Config_BaseAddressInit(void)
{
UWORD ConfigAddress;
UWORD ConfigData;
///////////////////////////////////////
// ATA Command Register Base Address //
///////////////////////////////////////
ConfigAddress = 0x40000010;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 4 (000100b),
//
//
-> ATA Command Register Base Address
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite(ConfigAddress, 0x0C800000);
77
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
///////////////////////////////////////
// ATA Control Register Base Address //
///////////////////////////////////////
ConfigAddress = 0x40000014;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 5 (000101b),
//
//
-> ATA Control Register Base Address
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite(ConfigAddress, 0x0C800008);
//////////////////////////////////////////////
// Bus Master Control Register Base Address //
//////////////////////////////////////////////
ConfigAddress = 0x40000018;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 6 (000110b)
//
//
-> Bus Master Control Register Base Address
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite(ConfigAddress, 0x0C800010);
return;
}
/////////////////////////////////////////////////////////////////
// Function name: main
//
//
//
//
// Function: Sets base address of configuration space.
// Argument: None
// Return value: 0: Normal end
/////////////////////////////////////////////////////////////////
int main(void)
{
// Initializes PCI Host Bridge Macro.
PCI_HBM_Init();
// Sets base address of configuration space.
PCI_Config_BaseAddressInit();
return 0;
}
78
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
5.5.5 IDE HDD access sample program list
///////////////////////////////////////////////////////////////////////////////
// IDE HDD access sample //
Overview: Issues ATA commands to HDD, which is ATA device, via PCI-IDE //
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
ASIC board connected to PCI slot of evaluation board.
ATA commands to be issued are as follows.
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE,
READ SECTOR(S), WRITE SECTOR(S), READ DMA, WRITE DMA
ATA command is executed by executing device selection
protocol to determine that command is issued to either
Master Device or Slave Device. ATA command is issued
and data is transferred using transfer protocol
corresponding to each ATA command. Four transfer
protocols, PIO datain transfer, PIO dataout transfer,
PIO nondata transfer, and DMA transfer, are available.
This sample program is provided with device selection
protocol and four transfer protocols as functions.
Corresponding transfer protocol function is called
from function processing each ATA command.
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// PCI-IDE ASIC board register address definition //
/////////////////////////////////////////////////////
//////////////////////
// IDE Command Area //
//////////////////////
#define IDEREG_DATA
((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x00))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x01))
(0x01)
#define IDEREG_ERROR
#define IDEREG_ERROR_ERR_BIT
#define IDEREG_FEATURES
#define IDEREG_SECTOR_COUNT
#define IDEREG_SECTOR_NUMBER
#define IDEREG_CYLINDER_LOW
#define IDEREG_CYLINDER_HIGH
#define IDEREG_DEVICE_HEAD
#define IDEREG_STATUS
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x01))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x02))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x03))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x04))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x05))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x06))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x07))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x07))
#define IDEREG_COMMAND
//////////////////////
// IDE Control Area //
//////////////////////
79
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
#define IDEREG_ALTERNATE_STATUS
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E))
((VUBYTE*)(BASE_ADDRESS_PCI_IO + 0x0E))
#define IDEREG_DEVICE_CONTROL
/////////////////////////
// Bus Master I/O Area //
/////////////////////////
#define IDEREG_BUSMASTER_START_STOP
#define IDEREG_DSCTBL_START_ADDRESS
#define IDEREG_INTERRUPT_CONTROL
((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x10))
((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x14))
((VUWORD*)(BASE_ADDRESS_PCI_IO + 0x18))
///////////////////////////
// Error code definition //
///////////////////////////
#define STATUS_SUCCESS
0
1
1
2
3
4
5
#define STATUS_TIMEOUT_BSY0_DRQ0
#define STATUS_TIMEOUT_DEVICE_SELECTION
#define STATUS_TIMEOUT_DRDY1
#define STATUS_TIMEOUT_BSY0
#define STATUS_TIMEOUT_INTRQ
#define STATUS_TIMEOUT_BMEND
#define STATUS_IDE_ERROR(IDE_ERROR_REG) (0x10000000 | (UWORD)(IDE_ERROR_REG))
///////////////////////////////////////////////////
// Transfer mode timing setting value definition //
///////////////////////////////////////////////////
// See IDE specifications for details of transfer mode timing setting values shown below.
// Setting value passed to SET_FEATURES command in Set_Transfer_mode()
#define PIO_MODE0
#define UDMA_MODE0
0x08
0x40
// Setting value of timing register (when IDE operation clock is 33 MHz)
#define IDE_PIO_TIMING_IDE33MHz_MODE0 (0x00020906)
#define IDE_UDMA_TIMING1_IDE33MHz_MODE0 (0x00000202)
#define IDE_UDMA_TIMING2_IDE33MHz_MODE0 (0x00000005)
////////////////////////////
// Structure declaration //
////////////////////////////
///////////////////////////////////////
// Structure for issuing ATA command //
///////////////////////////////////////
typedef struct{
UBYTE features;
// Features register
UBYTE sector_count;
UBYTE sector_number;
// Sector Count register
// Sector Number register
80
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
UBYTE cylinder_low;
UBYTE cylinder_high;
UBYTE device_head;
UBYTE command;
// Cylinder Low register
// Cylinder High register
// Device/Head register
// Command register
} ATA_COMMAND;
////////////////////////////////////////////
// Descriptor table for UltraDMA transfer //
////////////////////////////////////////////
typedef struct{
UWORD transfer_address;
UWORD transfer_byte;
// Transfer address
// Number of transfer bytes
// Next table address
UWORD next_table_address;
} DISCRIPTOR_TABLE;
/////////////////////////////
// Initialization function //
/////////////////////////////
/////////////////////////////////////////////////////////////////
// Function name: PCI_Config_ModeInit
// Function: Sets initialization of PCI-IDE ASIC board.
// Argument: None
//
//
//
//
// Return value: None
// Details: Sets handling of interrupts and errors, coding and //
//
//
then resets IDE bus.
//
//
/////////////////////////////////////////////////////////////////
void PCI_Config_ModeInit(void)
{
UWORD ConfigAddress;
UWORD ConfigData;
//////////////////////////////
// Setting of PCI functions //
//////////////////////////////
ConfigAddress = 0x40000004;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 1 (000001b)
//
-> Status / Command
// bit 01-00 : 00b (fixed)
ConfigData = 0x02000145;
// bit 26-25 : DEVSEL timing = 01b (medium fixed)
// bit
// bit
8 : SERR Enable = 1b : Output pci_serr.
6 : Parity Error Response = 1b : Output pci_serr
81
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
//
when Parity Error is detected.
// bit
// bit
2 : Bus Master = 1b : Enable PCI Bus Master transfer
0 : IO Space = 1b : Enable IO access to PCI-IDE ASIC board
PCI_ConfigWrite(ConfigAddress, ConfigData);
////////////////////////////
// Setting DES to disable //
////////////////////////////
ConfigAddress = 0x40000058;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 22 (010110b),
//
//
-> IDE Bus Master Control
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
// IDE Bus Master Control
//
Disable DES (Set bit16 des_on to 0)
ConfigData = PCI_ConfigRead(ConfigAddress);
PCI_ConfigWrite(ConfigAddress, ConfigData & 0xFFFEFFFF);
///////////////////////////////////////////
// Setting of Interrupt Control register //
///////////////////////////////////////////
*IDEREG_INTERRUPT_CONTROL &= 0xFFFCFFFF;
// bit
// bit
17 : PCI Bus Master End Interrupt Mask = 0b (Interrupt enabled)
16 : PCI I/F Interrupt Mask = 0b (Interrupt enabled)
////////////////////////////////////////
// Setting of Device Command register //
////////////////////////////////////////
*IDEREG_DEVICE_CONTROL = 0x00;
// bit
2 : nIEN = 0b (Set INTRQ signal to enable)
///////////////////
// IDE Bus reset //
///////////////////
ConfigAddress = 0x40000044;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 17 (010001b),
//
//
-> IDE Reset Register
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
82
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
ConfigData = 0x00000001;
// bit
0 : IDE I/F RESET Port
= 1b :
//
Output IDE RESETX signal output to IDE I/F.
PCI_ConfigWrite(ConfigAddress, ConfigData);
return;
}
////////////////////////////////////
// Transfer mode setting function //
////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// Function name: Set_Transfer_Mode
//
//
//
//
//
//
//
//
//
//
//
// Function: Setting of transfer mode
// Argument: dev_num : Device selection (0:Master/1:Slave)
//
mode : Transfer mode
// Return value:
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int Set_Transfer_Mode(int dev_num, UBYTE mode)
{
status = ATA_Set_Features(dev_num, 0x03, mode);
return status;
}
/////////////////////////////////////////////////////////////////
// Function name: Set_PIO_Timing
// Function: Setting of PIO Timing register
// Argument: pio_timing : Value set to PIO Timing register
// Return value: None
//
//
//
//
//
//
/////////////////////////////////////////////////////////////////
void Set_PIO_Timing(UWORD pio_timing)
{
UWORD ConfigAddress;
UWORD ConfigData;
ConfigAddress = 0x40000048;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
83
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
// bit 07-02 : Register number = 18 (010010b)
// -> PIO Timing (In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite( ConfigAddress, pio_timing );
return;
}
/////////////////////////////////////////////////////////////////////////
// Function name: Set_UDMA_Timing
//
//
//
//
//
//
// Function: Setting of UltraDMA Timing1, 2 registers
// Argument: udma_timing1 : Value set to UltraDMA Timing1 register
//
udma_timing2 : Value set to UltraDMA Timing2 register
// Return value: None
//
/////////////////////////////////////////////////////////////////////////
void Set_UDMA_Timing(UWORD udma_timing1, UWORD udma_timing2)
{
UWORD ConfigAddress;
UWORD ConfigData;
ConfigAddress = 0x4000004C;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 19 (010011b)
//
//
-> UltraDMA Timing1
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite( ConfigAddress, udma_timing11 );
ConfigAddress = 0x40000050;
// bit 31-11 : IDSEL specification = 010000000000000000000b
//
Select PCI device connected to AD30
// bit 10-08 : Function number = 00b
// bit 07-02 : Register number = 20 (010100b)
//
//
-> UltraDMA Timing2
(In the case of PCI-IDE ASIC board used in this application)
// bit 01-00 : 00b (fixed)
PCI_ConfigWrite( ConfigAddress, udma_timing2 );
return;
}
////////////////////////////////////
84
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
// ATA command execution function //
////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_Set_Features
//
// Function: Executes SET FEATURES command (Protocol:ND, Command:EFh). //
// Argument: dev_num : Device selection (0:Master/1:Slave)
// Return value:
//
//
//
//
//
//
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_Set_Features(int dev_num, int sub_cmd, int mode)
{
int status;
ATA_COMMAND ac;
ac.features
= sub_cmd;
// Features register
ac.sector_count = mode;
ac.sector_number = 0x00;
ac.cylinder_low = 0x00;
ac.cylinder_high = 0x00;
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
// Device/Head register
// Command register
ac.device_head
ac.command
= dev_num<<4;
= 0xEF;
status = ATA_PIO_nondata(&ac);
return status;
}
//////////////////////////////////////////////////////////////////////////
// Function name: ATA_Idle_Immediate //
// Function: Executes IDLE IMMEDIATE command (Protocol:ND, Command:E1h).//
// Argument: dev_num : Device selection (0:Master/1:Slave)
// Return value:
//
//
//
//
//
//
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
//////////////////////////////////////////////////////////////////////////
int ATA_Idle_Immediate(int dev_num)
{
ATA_COMMAND ac;
85
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
ac.features
= 0x00;
// Features register
ac.sector_count
ac.sector_number
ac.cylinder_low
ac.cylinder_high
ac.device_head
ac.command
= 0x00;
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
// Device/Head register
// Command register
= 0x00;
= 0x00;
= 0x00;
= dev_num<<4;
= 0xE1;
status = ATA_PIO_nondata(&ac);
return status;
}
///////////////////////////////////////////////////////////////////////////
// Function name: ATA_Identify_Device //
// Function: Executes IDENTIFY DEVICE command (Protocol:PI, Command:ECh).//
// Argument: dev_num : Device selection (0:Master/1:Slave)
// buff : Buffer pointer
// Return value:
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
///////////////////////////////////////////////////////////////////////////
int ATA_Identify_Device(int dev_num, void *buff)
{
ATA_COMMAND ac;
int status;
ac.features
= 0x00;
= 0x00;
= 0x00;
= 0x00;
= 0x00;
// Features register
ac.sector_count
ac.sector_number
ac.cyliner_low
ac.cylinder_high
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
ac.dev_head
ac.command
= dev_num << 4;
= 0xEC;
// Device/Head register
// Command register
status = ATA_PIO_datain(&ac, 1, buff);
return status;
}
//////////////////////////////////////////////////////////////////////////
// Function name: ATA_Read_Sector
//
86
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
// Function: Executes READ SECTOR(S) command (Protocol:PI, Command:20h).//
// Argument: dev_num : Device selection (0:Master/1:Slave)
//
//
//
//
//
//
//
//
//
//
//
//
//
//
lba : LBA
sec_cnt : Number of sectors
buff : Buffer pointer
// Return value:
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
//////////////////////////////////////////////////////////////////////////
int ATA_Read_Sector(int dev_num, UWORD lba, UHWORD sec_cnt, void *buff)
{
int status;
ATA_COMMAND ac;
ac.features
= 0x00;
// Features register
ac.sector_count = sector_count;
ac.sector_number = (lba & 0xFF);
ac.cylinder_low = (lba>>8 & 0xFF);
ac.cylinder_high = (lba>>16 & 0xFF);
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
ac.device_head
ac.command
= 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register
= 0x20; // Command register
status = ATA_PIO_datain(&ac, sec_cnt, buff);
return status;
}
///////////////////////////////////////////////////////////////////////////
// Function name: ATA_Write_Sector //
// Function: Executes WRITE SECTOR(S) command (Protocol:PO, Command:30h).//
// Argument: dev_num : Device selection (0:Master/1:Slave)
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
lba : LBA
sec_cnt : Number of sectors
buff : Buffer pointer
// Return value:
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
///////////////////////////////////////////////////////////////////////////
int ATA_Write_Sector(int dev_num, UWORD lba, UHWORD sec_cnt, void *buff)
{
87
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
int status;
ATA_COMMAND ac;
ac.features
= 0x00;
// Features register
ac.sector_count = sector_count;
ac.sector_number = (lba & 0xFF);
ac.cylinder_low = (lba>>8 & 0xFF);
ac.cylinder_high = (lba>>16 & 0xFF);
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
ac.device_head
ac.command
= 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register
= 0x30; // Command register
status = ATA_PIO_dataout(&ac, sec_cnt, buff);
return status;
}
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_Read_DMA
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// Function: Executes READ DMA command (Protocol:DM, Command:C8h).
// Argument: dev_num : Device selection (0:Master/1:Slave)
//
//
lba : LBA
sec_cnt : Number of sectors
// Return value:
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_TIMEOUT_BMEND : BM timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_Read_DMA(int dev_num, UWORD lba, UHWORD sec_cnt)
{
int status;
ATA_COMMAND ac;
ac.features
= 0x00;
// Features register
ac.sector_count = sector_count;
ac.sector_number = (lba & 0xFF);
ac.cylinder_low = (lba>>8 & 0xFF);
ac.cylinder_high = (lba>>16 & 0xFF);
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
ac.device_head
ac.command
= 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register
= 0xC8; // Command register
status = ATA_DMA(&ac);
return status;
}
88
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_Write_DMA
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// Function: Executes WRITE DMA command (Protocol:DM, Command:CAh).
// Argument: dev_num : Device selection (0:Master/1:Slave)
//
//
lba : LBA
sec_cnt : Number of sectors
// Return value:
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_TIMEOUT_BMEND : BM timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_Write_DMA(int dev_num, UWORD lba, UHWORD sec_cnt)
{
int status;
ATA_COMMAND ac;
ac.features
= 0x00;
// Features register
ac.sector_count = sector_count;
ac.sector_number = (lba & 0xFF);
ac.cylinder_low = (lba>>8 & 0xFF);
ac.cylinder_high = (lba>>16 & 0xFF);
// SectorCount register
// SectorNumber register
// CylinderLow register
// CylinderHigh register
ac.device_head
ac.command
= 0x40|(dev_num<<4)|(lba>>24 & 0x0F); // Device/Head register
= 0xCA; // Command register
status = ATA_DMA(&ac);
return status;
}
/////////////////////////////////
// Protocol execution function //
/////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_Device_Selection
// Function: Executes device selection protocol.
// Argument: dev_num : (0:Master / 1:Slave)
// Return value:
//
//
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
/////////////////////////////////////////////////////////////////////////
int ATA_Device_Selection(int dev_num)
{
89
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
int status;
status = Wait_IDE_BSY0_DRQ0();
if ( status != 0 ) {
return STATUS_TIMEOUT_BSY0_DRQ0;
}
// Wait until BSY=0, DRQ=0
// Timeout error end
*IDEREG_DEVICE_HEAD = dev_num << 4;
wait(TIMER400ns);
// Device selection
// Wait 400 ns
status = Wait_IDE_BSY0_DRQ0();
if ( status != 0 ) {
return STATUS_TIMEOUT_BSY0_DRQ0;
}
// Wait until BSY=0, DRQ=0
// Timeout error end
return STATUS_SUCCESS;
// Normal end
}
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_PIO_datain
//
//
//
//
//
//
//
//
//
//
//
//
// Function: Executes PIO data in command protocol.
// Argument: atacom : ATA_COMMAND structure pointer
//
//
sector_count : Number of sectors
buff : Buffer pointer
// Return value:
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_PIO_datain(ATA_COMMAND *atacom, UHWORD sector_count, void *buff)
{
UBYTE dev, idestat;
UWORD *buffp;
int i, j, status;
buffp = (UWORD*)buff;
dev = ( atacom->device_head >> 4 ) & 1;
status = ATA_Device_Selection(dev);
if ( status != 0 ) {
// DEVICE SELECTION
return STATUS_TIMEOUT_DEVICE_SELECTION;
}
// DEVICE SELECTION timeout
*IDEREG_FEATURES
= atacom->features;
// Features register
*IDEREG_SECTOR_COUNT = atacom->sector_count; // SectorCount register
90
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
*IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register
*IDEREG_CYLINDER_LOW = atacom->cylinder_low; // CylinderLow register
*IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register
status = Wait_IDE_DRDY1();
if ( status != 0 ) {
return STATUS_TIMEOUT_DRDY1
}
// Loop until DRDY=1
// DRDY1 timeout
*IDEREG_COMMAND = atacom->command;
wait(TIMER400ns);
// Command register
// Wait 400 ns
for ( i=0; i<sector_count; i++ ) {
status = Wait_IDE_INTRQ();
if ( status != 0 ) {
return STATUS_TIMEOUT_INTRQ;
}
// Wait for INTRQ assert
// INTRQ timeout error
idestat = *IDEREG_STATUS;
// Status register read (INTRQ clear)
// Data read
for ( j=0; j<128; j++ ) {
*buffp = *IDEREG_DATA;
buffp++;
}
}
idestat = *IDEREG_ALTERNATE_STATUS;
idestat = *IDEREG_STATUS;
// Alt Status register empty read
// Status register read
if ( idestat & IDEREG_ERROR_ERR_BIT ) {
return STATUS_IDE_ERROR(*IDEREG_ERROR);
}
// Error end (after command execution)
// Normal end
return STATUS_SUCCESS;
}
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_PIO_dataout
//
//
//
//
//
//
//
//
//
//
//
//
// Function: Executes PIO data out command protocol.
// Argument: atacom : ATA_COMMAND structure pointer
//
//
sector_count : Number of sectors
buff : Buffer pointer
// Return value:
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
91
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
//
//
/////////////////////////////////////////////////////////////////////////
int ATA_PIO_dataout(ATA_COMMAND *atacom, UHWORD sector_count, void *buff)
{
UBYTE dev, idestat;
UWORD *buffp;
int i, j, status;
buffp = (UWORD*)buff;
dev = ( atacom->device_head >> 4 ) & 1;
status = ATA_Device_Selection(dev);
if ( status != 0 ) {
// DEVICE SELECTION
return STATUS_TIMEOUT_DEVICE_SELECTION;
}
// DEVICE SELECTION timeout
*IDEREG_FEATURES
= atacom->features;
// Features register
*IDEREG_SECTOR_COUNT = atacom->sector_count; // SectorCount register
*IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register
*IDEREG_CYLINDER_LOW = atacom->cylinder_low; // CylinderLow register
*IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register
status = Wait_IDE_DRDY1();
if ( status != 0 ) {
return STATUS_TIMEOUT_DRDY1;
}
// Loop until DRDY=1
// DRDY timeout
*IDEREG_COMMAND = atacom->command;
wait(TIMER400ns);
// Command register
// Wait 400 ns
status = Wait_IDE_BSY0_DRQ0();
if ( status != 0 ) {
return STATUS_TIMEOUT_BSY0_DRQ0;
}
// Wait until BSY=0, DRQ=0
// BSY timeout error end
for ( i=0; i<sector_count; i++ ) {
for ( j=0; j<128; j++ ) {
// Data write
*IDEREG_DATA = *buffp;
buffp++;
}
status = Wait_IDE_INTRQ();
// Wait for INTRQ assert
if ( status != 0 ) {
return STATUS_TIMEOUT_INTRQ;
// INTRQ timeout error
}
idestat = *IDEREG_STATUS;
}
// Status register read (INTRQ clear)
if ( idestat & IDEREG_ERROR_ERR_BIT ) {
92
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
return STATUS_IDE_ERROR(*IDEREG_ERROR);
return STATUS_SUCCESS;
// Error end (after command execution)
// Normal end
}
}
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_PIO_nondata
//
//
//
//
//
//
//
//
//
//
// Function: Executes PIO non data command protocol.
// Argument: atacom : ATA_COMMAND structure pointer
// Return value:
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_PIO_nondata(ATA_COMMAND *atacom)
{
int status;
UBYTE dev, idestat;
dev = ( atacom->device_head >> 4 ) & 1;
status = ATA_Device_Selection(dev);
if ( status != 0 ) {
// DEVICE SELECTION
return STATUS_TIMEOUT_DEVICE_SELECTION;
}
// DEVICE SELECTION timeout
*IDEREG_FEATURES
= atacom->features;
// Features register
*IDEREG_SECTOR_COUNT = atacom->sector_count; // SectorCount register
*IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register
*IDEREG_CYLINDER_LOW = atacom->cylinder_low; // CylinderLow register
*IDEREG_CYLINDER_HIGH = atacom->cylinder_high; // CylinderHigh register
status = Wait_IDE_DRDY1();
if ( status != 0 ) {
return STATUS_TIMEOUT_DRDY1;
}
// Loop until DRDY=1
// DRDY timeout
*IDEREG_COMMAND = atacom->command;
wait(TIMER400ns);
// Command register
// Wait 400 ns
status = Wait_IDE_INTRQ();
if ( status != 0 ) {
return STATUS_TIMEOUT_INTRQ;
}
// Wait for INTRQ assert
// INTRQ timeout error
93
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
idestat = *IDEREG_ALT_STATUS;
// Alt Status register empty read
// Status register read
idestat = *IDEREG_STATUS;
if ( idestat & IDEREG_ERROR_ERR_BIT ) {
return STATUS_IDE_ERROR(*IDEREG_ERROR);
}
// Error end (after command execution)
// Normal end
return STATUS_SUCCESS;
}
/////////////////////////////////////////////////////////////////////////
// Function name: ATA_DMA
//
//
//
//
//
//
//
//
//
//
//
//
// Function: Executes DMA command protocol.
// Argument: atacom : ATA_COMMAND structure pointer
// Return value:
//
//
//
//
//
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_DEVICE_SELECTION : DEVICE SELECTION error end
STATUS_TIMEOUT_BSY0_DRQ0 : BSY=0,DRQ=0 timeout error end
STATUS_TIMEOUT_DRDY1 : DRDY=1 timeout error end
STATUS_TIMEOUT_INTRQ : INTRQ timeout error end
STATUS_TIMEOUT_BMEND : BM timeout error end
STATUS_IDE_ERROR : Error end after command execution
/////////////////////////////////////////////////////////////////////////
int ATA_DMA(ATA_COMMAND *atacom)
{
int status;
UBYTE dev, idestat;
dev = ( atacom->device_head >> 4 ) & 1;
status = ATA_Device_Selection(dev);
if ( status != 0 ) {
// DEVICE SELECTION
return STATUS_TIMEOUT_DEVICE_SELECTION;
}
// DEVICE SELECTION timeout
*IDEREG_FEATURES
= atacom->features;
// Features register
*IDEREG_SECTOR_COUNT = atacom->sector_count; // SectorCount register
*IDEREG_SECTOR_NUMBER = atacom->sector_number; // SectorNumber register
*IDEREG_CYL_LOW
*IDEREG_CYL_HIGH
= atacom->cylinder_low; // CylinderLow register
= atacom->cylinder_high; // CylinderHigh register
status = Wait_IDE_DRDY1();
if ( status != 0 ) {
return STATUS_TIMEOUT_DRDY1;
}
// Loop until DRDY=1
// DRDY timeout
*IDEREG_COMMAND = atacom->command;
// Command register
94
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
wait(TIMER400ns);
// Wait 400 ns
idestat = *IDEREG_ALT_STATUS;
// Alt Status register empty read
*IDEREG_BUSMASTER_START_STOP |= 0x01;
status = Wait_IDE_BMEND();
if ( status != 0 ) {
// Bus Master Start
return STATUS_TIMEOUT_BMEND;
}
// BMEND timeout error end
status = Wait_IDE_INTRQ();
if ( status != 0 ) {
return STATUS_TIMEOUT_INTRQ;
}
// Wait for INTRQ assert
// INTRQ timeout error end
idestat = *IDEREG_ALT_STATUS;
idestat = *IDEREG_STATUS;
// Alt Status register empty read
// Status register read
if ( idestat & IDEREG_ERROR_ERR_BIT ) {
return STATUS_IDE_ERROR(*IDEREG_ERROR);
}
// Error end (after command execution)
// Normal end
return STATUS_SUCCESS;
}
/////////////////////////////////////////////////////////////////
// Function name: ATA_Soft_Reset
// Function: Performs software reset.
// Argument: None
//
//
//
//
//
//
//
// Return value:
//
//
//
STATUS_SUCCESS : Normal end
STATUS_TIMEOUT_BSY0 : BSY=0 timeout error end
/////////////////////////////////////////////////////////////////
int ATA_soft_reset(void)
{
int status;
*IDEREG_DEVICE_CONTROL = 0x04;
wait(TIMER5ms);
// Reset execution
// Wait 5 ms
*IDEREG_DEVICE_CONTROL = 0x00;
wait(TIMER5ms);
// Reset release
// Wait 5 ms
status = Wait_IDE_BSY0();
if ( status != 0 ) {
return STATUS_TIMEOUT_BSY0;
}
// Wait until BSY=0
// Timeout error end
return STATUS_SUCCESS;
}
95
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
/////////////////////////////////////////////////////////////////////////////////
// Function name: main
//
//
//
//
//
//
//
// Function: Accesses IDE HDD via PCI bus and PCI-IDE ASIC board.
// Argument: None
// Return value: 0: Normal end
// Overview: Issues IDLE IMMEDIATE, IDENTIFY DEVICE, SET FEATURE, READ
//
//
SECTOR(S), WRITE SECTOR(S), READ DMA, and WRITE DMA commands.
/////////////////////////////////////////////////////////////////////////////////
int main(void)
{
int status;
UBYTE wbuff[4096], rbuff[4096];
DISCRIPTOR_TABLE* dsc_tbl;
///////////////////////////
// System initialization //
///////////////////////////
// Initializes PCI Host Bridge Macro.
PCI_HBM_Init();
// Sets initialization of PCI-IDE ASIC board.
PCI_Config_BaseAddressInit();
PCI_Config_ModeInit();
ATA_soft_reset(void);
// Soft reset
//////////////////////////////////
// Issue ATA command to IDE HDD //
//////////////////////////////////
////////////////////
// IDLE IMMEDIATE //
////////////////////
ATA_Idle_Immediate(0);
// Issues IDLE IMMEDIATE command.
/////////////////////
// IDENTIFY DEVICE //
/////////////////////
ATA_Identify_Device(
// Issues IDENTIFY DEVICE command.
// Master Device
0,
buff
);
// Buffer storing results
//////////////////////////////
// PIO transfer preparation //
//////////////////////////////
96
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
// Sets transfer mode to PIO transfer Mode0 using SET_FEATURE command.
Set_Transfer_Mode(0, PIO_MODE0);
// Sets PIO Timing register of configuration register of
// PCI-IDE ASIC board.
Set_PIO_Timing(IDE_PIO_TIMING_IDE33MHz_MODE0);
// Buffer initialization
InitBuffer(wbuff, 4096);
//////////////////
// PIO transfer //
//////////////////
ATA_Write_Sector(
// Issues WRITE SECTOR command.
// Master Device
0,
0,
// LBA 0
1,
// 1 Sector
wbuff
);
// Buffer storing written contents
ATA_Read_Sector(
// Issues READ SECTOR command.
// Master Device
0,
0,
// LBA 0
1,
// 1 Sector
rbuff
);
// Buffer storing read results
status = memcmp(wbuff, rbuff, 512);
if ( status != 0 ) {
printf("Verify Error!: WRITE SECTOR(S), READ SECTOR(S)\n");
}
///////////////////////////////////
// UltraDMA transfer preparation //
///////////////////////////////////
// Sets transfer mode to UltraDMA transfer Mode0 using SET_FEATURE command.
Set_Transfer_Mode(0, UDMA_MODE0);
// Sets UltraDMA Timing1 and UltraDMA Timing2 registers of configuration
// register of PCI-IDE ASIC board.
Set_UDMA_Timing(IDE_UDMA_TIMING1_IDE33MHz_MODE0, IDE_UDMA_TIMING2_IDE33MHz_MODE0);
////////////////////////////////
// PCI->IDE UltraDMA transfer //
////////////////////////////////
// Sets descriptor table referenced by PCI-IDE ASIC board during UltraDMA transfer.
dsc_tbl = (DISCRIPTOR_TABLE*)(BASE_ADDRESS_SDRAM + 0x02000000)
97
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
dsc_tbl->transfer_address
dsc_tbl->transfer_byte
= BASE_ADDRESS_SDRAM;
= 0x1000;
// = 4096byte = 8Sector
dsc_tbl->next_table_address = 0x00000001;
*IDEREG_DSCTBL_START_ADDRESS = dsc_tbl;
// Last table
// Sets transfer direction of UltraDMA transfer.
*IDEREG_BUSMASTER_START_STOP &= 0xFFFFFEFF;
// Ultra DMA (PCI->IDE)
// Buffer initialization
InitBuffer((UBYTE*)dsc_tbl->transfer_address, 512*8);
// Issues command of UltraDMA transfer.
ATA_Write_DMA(
0,
0,
8,
// Master Device
// LBA 0
// 8 Sector
);
////////////////////////////////
// PCI<-IDE UltraDMA transfer //
////////////////////////////////
// Sets descriptor table referenced by device during UltraDMA transfer.
dsc_tbl->transfer_address
dsc_tbl->transfer_byte
= BASE_ADDRESS_SDRAM + 0x01000000;
= 0x1000; // = 4096byte = 8Sector
dsc_tbl->next_table_address = 0x00000001;
*IDEREG_DSCTBL_START_ADDRESS = dsc_tbl;
// Last table
// Sets transfer direction of UltraDMA transfer.
*IDEREG_BUSMASTER_START_STOP |= 0x00000100;
// Ultra DMA (PCI<-IDE)
// Issues command of UltraDMA transfer.
ATA_Read_DMA(
0,
0,
8,
// Master Device
// LBA 0
// 8 Sector
);
status = memcmp(
(UBYTE*)(BASE_ADDRESS_SDRAM),
(UBYTE*)(BASE_ADDRESS_SDRAM+0x01000000),
512*8);
if ( status != 0 ) {
printf("Verify Error!: WRITE DMA, READ DMA\n");
}
return 0;
}
98
Application Note U17121EJ1V1AN
CHAPTER 5 APPLICATION EXAMPLES
Figure 5-6. IDE_Write_DMA Function
WRITE DMA (Data transfer from SDRAM to IDE HDD)
Bus master transfer of 8 sectors (4096 bytes)
is performed from 400 0000H (SDRAM area)
to LBA0 of IDE HDD.
700 0000H
6FF FFFFH
:
Number of transfer bytes 0000 1000H
Descriptor table
Transfer address
0400 0000H
600 0000H
5FF FFFFH
IDE HDD
500 0000H
4FF FFFFH
4096 bytes
400 0000H
3FF FFFFH
000 0000H
Figure 5-7. IDE_Read_DMA Function
READ DMA (Data transfer from IDE HDD to SDRAM)
Bus master transfer of 8 sectors (4096 bytes)
is performed from LBA0 of IDE HDD to
500 0000H (SDRAM area).
700 0000H
6FF FFFFH
:
Number of transfer bytes 0000 1000H
Descriptor table
4096 bytes
Transfer address
0500 0000H
600 0000H
5FF FFFFH
500 0000H
4FF FFFFH
IDE HDD
400 0000H
3FF FFFFH
000 0000H
99
Application Note U17121EJ1V1AN
相关型号：
UPD703134AGJ-XXX-UEN
32-Bit Single-Chip MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703134AGJ-XXX-UEN-A
RISC Microcontroller, 32-Bit, MROM, 80MHz, CMOS, PQFP144, 20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703134AY
32-Bit Single-Chip MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703134AYF1-XXX-EN4
32-Bit Single-Chip MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703134AYGJ-XXX-UEN
32-Bit Single-Chip MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703134AYGJ-XXX-UEN-A
RISC Microcontroller, 32-Bit, MROM, 80MHz, CMOS, PQFP144, 20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
NEC
UPD703166
V850 Series Pamphlet | Pamphlet[02/2002]Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703166Y
V850 Series Pamphlet | Pamphlet[02/2002]Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
UPD703175(A)-32/24
RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
UPD703175GC-24-XXX
RISC Microcontroller, 32-Bit, MROM, 32MHz, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
UPD703176(A)-32/24
RISC MICROCONTROLLER, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
UPD703176GC-24-XXX
RISC Microcontroller, 32-Bit, MROM, 32MHz, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
RENESAS
©2020 ICPDF网 联系我们和版权申明