UPD70320L [NEC]

V25TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER; V25TM八分之一十六位单芯片微控制器


型号：	UPD70320L
厂家：	NEC
描述：	V25TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER V25TM八分之一十六位单芯片微控制器微控制器和处理器外围集成电路装置时钟
文件：	总74页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD70320

V25^TM

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD70320 (V25) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA

controller, interrupt controller, etc. are all integrated. The µPD70320 is compatible with the 8/16-bit microprocessor

µPD70108/70116 (V20^TM/V30^TM) on the software level.

The details of the functions are described in the following User's Manuals. Be sure to read it before starting

design.

• V25, V35^TMUser's Manual — Hardware

• V25, V35 Family User's Manual — Instructions : U12120J (Japanese version)

: IEM-1220

FEATURES

• Internal 16-bit architecture and external 8-bit data bus

• Compatible with µPD70108/70116 (in native mode) on software level (some instructions added)

• Minimum instruction cycle : 400 ns/5 MHz (µPD70320)

250 ns/8 MHz (µPD70320-8)

• On-chip RAM : 256 words × 8 bits

• Input port (port T) with comparator : 8 bits

• I/O lines (input port : 4 bits, input/output port : 20 bits)

• Serial interface (internal dedicated baud rate generator) : 2 channels

Asynchronous mode and I/O interface mode

• Interrupt controller

•

Programmable priority (8 levels)

Vectored interrupt function

Macro service function

• DRAM and pseudo SRAM refreshing functions

• DMA controller : 2 channels

• 16-bit timer : 2 channels

• Time base counter

• On-chip clock generator

• Programmable wait function

• Standby function (STOP/HALT)

The information in this document is subject to change without notice.

Document No. U10090EJ8V0DS00 (8th edition)

Date Published November 1997 N

Printed in Japan

The mark

shows major revised points.

1996

1995

µPD70320

ORDERING INFORMATION

Part Number

µPD70320L

Package

Max. Operating Frequency (MHz)

84-pin plastic QFJ (1150 × 1150 mils)

94-pin plastic QFP (20 × 20 mm)

µPD70320L-8

µPD70320GJ-5BG

µPD70320GJ-8-5BG

Remark The plastic QFJ is a new name of the PLCC.

µPD70320

PIN CONFIGURATION (Top View)

84-Pin Plastic QFJ (1150 × 1150 mils)

µPD70320L

µPD70320L-8

11 10

1 84 83 82 81 80 79 78 77 76 75

P07/CLKOUT

PT7

A10

A11

PT6

PT5

PT4

PT3

PT2

PT1

PT0

P17/READY

P16/SCK0

P15/TOUT

P14/INT/POLL

P13/INTP2/INTAK

P12/INTP1

P11/INTP0

P10/NMI

P27/HLDRQ

P26/HLDAK

P25/TC1

P24/DMAAK1

P23/DMARQ1

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

IC: Internally Connected

Cautions 1. Connect IC pin individually to VDD via a resistor (3 to 10 kΩ).

Connect EA pin to GND via a resistor (3 to 10 kΩ).

µPD70320

94-Pin Plastic QFP (20 × 20 mm)

µPD70320GJ-5BG

µPD70320GJ-8-5BG

94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75

74 73 72

P05

A12

A13

P04

A14

P03

A15

P02

A16

P01

A17

P00

A18

A19

MREQ

IOSTB

MSTB

R/W

REFRQ

RESET

RxD0

GND

CTS0

TxD0

RxD1

CTS1

TxD1

P20/DMARQ0

VDD

GND

VDD

P21/DMAAK0

P22/TC0

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

24 25 26 27 28 29 30 31 32

IC: Internally Connected

NC: Non-Connection

Cautions 1. Connect IC pin individually to VDD via a resistor (3 to 10 kΩ).

2. Connect EA pin to GND via a resistor (3 to 10 kΩ).

A0 to A19

P20/DMARQ0

P21/DMAAK0

P22/TC0

P23/DMARQ1

P24/DMAAK1

P25/TC1

etc.

ALU

PFP

INC

PROGRAMMABLE

DMA

CONTROLLER

RESET

HLDAK/P26

HLDRQ/P27

READY/P17

MREQ

PSW

TxD0

RxD0

Note

SERIAL

INTERFACE

INTERNAL ROM

8 Kbyte

INTERNAL RAM

256 byte

P16/SCK0

CTS0

MSTB

(reserved)

TxD1

• GR

BAUD RATE

GENERATOR

R/W

RxD1

• MACRO SERVICE

CHANNEL

CTS1

IOSTB

POLL/INT/P14

P10/NMI

P11/INTP0

PROGRAMMABLE

INTERRUPT

CONTROLLER

INSTRUCTION DECODER

MICRO SEQUENSER

MICRO ROM

QUEUE

(6 byte)

P12/INTP1

P13/INTP2/INTAK

P14/INT/POLL

D0 to D7

TIME BASE

COUNTER

PORT with

COMPARATOR

16-BIT TIMER

TOUT/P15

PORT

REFRQ CLKOUT/PO7

PT0 to 7

VTH

GND

Note Not user-accessible.

µPD70320

CONTENTS

1. PIN FUNCTIONS..................................................................................................................................7

1.1 Port Pins....................................................................................................................................................... 7

1.2 Non-port Pins............................................................................................................................................... 8

2. INSTRUCTION SETS...........................................................................................................................9

2.1 Instructions Added to µPD70108/70116 .................................................................................................... 9

2.2 Instruction Set Operation ......................................................................................................................... 11

2.3 Instruction Set Table................................................................................................................................. 15

3. ELECTRICAL SPECIFICATIONS......................................................................................................47

4. CHARACTERISTIC CURVES............................................................................................................66

5. PACKAGE DRAWINGS.....................................................................................................................69

6. RECOMMENDED SOLDERING CONDITIONS................................................................................71

µPD70320

1. PIN FUNCTIONS

1.1 Port Pins

Pin Name

P00 to P06

P07/CLKOUT

P10/NMI

Input/Output

Input & output

Input & output/output

Input

Port Function

Control Function

8-bit input/output ports, each to

be specified bit-by-bit

—

System clock output

—

Used as non-maskable interrupt

request input (input port)

P11/INTP0

Used as both external interrupt

request input and input port

P12/INTP1

P13/INTP2/INTAK

Input/input/output

INT acknowledge signal output

P14/POLL/INT

Input & output/input/input

Used as both specifiable input/ External interrupt request input

output port and POLL input

P15/TOUT

Input & output/output

Input/output port specifiable

bit-by-bit

Timer output

P16/SCK0

Serial clock output

READY input

P17/READY

P20/DMARQ0

P21/DMAAK0

P22/TC0

Input & output/input

Input & output/output

8-bit input/output port specifiable DMA request input (CH0)

bit-by-bit

DMA acknowledge output (CH0)

DMA end output (CH0)

DMA request input (CH1)

DMA acknowledge output (CH1)

DMA end output (CH1)

HOLD acknowledge output

HOLD input

P23/DMARQ1

P24/DMAAK1

P25/TC1

Input & output/input

Input & output/output

P26/HLDAK

P27/HLDRQ

PT0 to PT7

Input & output/output

Input & output/input

Input

8-bit input port with comparator

—

Remark All port pins become input ports after reset is released.

When using P13/INTP2/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external

interrupt controller after reset is released.

µPD70320

1.2 Non-port Pins

Pin Name

TxD0

TxD1

RxD0

RxD1

CTS0

CTS1

REFRQ

V^TH

Input/Output

Function

Output

Serial data output

Serial data input

Input

Input & output

Input

CTS input in asynchronous mode, receive clock input/output in I/O interface mode

CTS input

Output

DRAM refresh pulse output

Input

Comparator reference voltage input

Reset signal input

RESET

External memory access (connect to GND via a resistor (3 to 10 kΩ))

Input

Used to connect crystal resonator/ceramic resonator for oscillating system clock.

External clock is entered by entering reverse phase clock to both X1 and X2 pins.

D0 to D7

A0 to A19

MREQ

MSTB

R/W

Input & output

Output

8-bit data bus

20-bit address output

Output used to indicate that memory bus cycle has been started

Memory read/memory write strobe output

Read cycle/write cycle ID signal output

IOSTB

V^DD

I/O read/I/O write strobe output

Positive power supply pins (all pins should be connected)

GND pins (all pins should be connected)

Internally connected (connect individually to VDD via a resistor (3 to 10 kΩ))

GND

µPD70320

2. INSTRUCTION SETS

The µPD70320 instruction sets are upward-compatible with those of µPD70108/70116 in native mode.

2.1 Instructions Added to µPD70108/70116

The following instructions are newly added to the µPD70108/70116.

(1) Conditional branch instruction

•

BTCLR ······· Bit test instruction used for special function registers

If, when this BTCLR is executed, the target special function register bit status is “1”, the bit is

reset (0) and the program is branched to short-label described in the operand. If the target bit

status is “0”, the program is moved to the next instruction. PSW is not changed in this instruction.

(Descriptive format)

Operand

Mnemonic

BTCLR

Special Function

Branch Address

short-label

sfr

imm3

(2) Interrupt instructions

•

RETRBI ······Return instruction used for register banks

This instruction is used to return the program from the interrupt service routine in which the

servicing.

(Descriptive format)

Mnemonic

RETRBI

Operand

None

•

FINT ··········· This instruction is used to report the interrupt controller that interrupt servicing has ended.

If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be

executed prior to the instruction for returning from interrupt servicing. It should not be used for

NMI, INT and software interrupts.

(Descriptive format)

Mnemonic

FINT

Operand

None

(3) CPU instruction

•

STOP ········· Instruction for transition to STOP state

(Descriptive format)

Mnemonic

STOP

Operand

None

µPD70320

(4) Register bank switch instructions

• BRKCS ······ Used to switch register banks

A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register

described in the operand. The program is also branched with this instruction to the address

obtained from the PS stored in advance in the new register bank and the vector PC.

The RETRBI instruction is used to return the program from the new register bank.

(Descriptive format)

Mnemonic

BRKCS

Operand

reg16

•

TSKSW ······ Used to switch register banks

Just like the BRKCS instruction, this instruction is also executed to select a register bank. The

program is branched to the address obtained from the PS stored in advance in the new register

bank and the address obtained from the PC save area.

(Descriptive format)

Mnemonic

TSKSW

Operand

reg16

(5) Data transfer instructions

• MOVSPA ··· Used to transfer SS and SP values

This instruction is executed to transfer both SS and SP values before the register bank is switched

to SS and SP of the current (post-switching) register bank.

(Descriptive format)

Mnemonic

MOVSPA

Operand

None

•

MOVSPB ··· Used to transfer SS and SP values

This instruction is executed to transfer the SS and SP values of the current (pre-switching)

bit register described in the operand.

(Descriptive format)

Mnemonic

MOVSPB

Operand

reg16

Some µPD70108/70116 instructions should be much cared as shown below when used for the µPD70320.

•

I/O instruction, primitive I/O instruction

If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1)

the IBRK flag when using the I/O instruction.

•

FPO instruction

An interrupt is generated without executing this instruction.

µPD70320

2.2 Instruction Set Operation

Table 2-1. Operand Identifier

Identifier

Description

reg

8-/16-bit general register

reg8

8-bit general register

16-bit general register

reg16

dmem

mem

8-/16-bit memory location

mem8

mem16

mem32

sfr

8-bit memory location

16-bit memory location

32-bit memory location

8-bit special function register location

Constant within 0 to FFFFH

Constant within 0 to 7

imm

imm3

imm4

Constant within 0 to FH

imm8

Constant within 0 to FFH

imm16

acc

Constant within 0 to FFFFH

sreg

Segment register

src-table

src-block

dst-block

near-proc

far-proc

near-label

short-label

far-label

memptr16

memptr32

256-byte conversion table name

Procedure in the current program segment

Procedure in another program segment

Label in the current program segment

Label within end of instruction to –128 to +127 bytes

Label in another program segment

Word including location offset in the current program segment to which control is to be passed

Double-word including location offset in another program segment to which control is to be passed

and segment base address

regptr16

16-bit general register including location offset in another program segment to which control is to be

passed

pop-value

fp-op

Number of bytes to be abandoned from stack (0 to 64K, normally even number)

Immediate value to judge instruction code of external floating point operation chip

µPD70320

Table 2-2. Operation Code Identifier

Identifier

Description

Byte/word specification bit (0: byte, 1: word). However, when s = 1, the sign extended byte data

should be 16-bit operand even when W is 1.

reg

mem

mod

Memory field (000 to 111)

Mode field (00 to 10)

Sign extension specification bit (0: Sign is not extended, 1: Sign is extended)

Data used to judge instruction code of external floating-point operation chip

X, XXX, YYY, ZZZ

Table 2-3. Operation Identifier (1/2)

Identifier

Description

Accumulator (16 bits)

Accumulator (upper byte)

Accumulator (lower byte)

Stack pointer (16 bits)

Program counter (16 bits)

Program status word (16 bits)

Index register (source) (16 bits)

Index register (destination) (16 bits)

Program segment register (16 bits)

Data segment 1 register (16 bits)

Data segment 0 register (16 bits)

Stack segment register (16 bits)

Auxiliary carry flag

PSW

DS1

DS0

Carry flag

Parity flag

Sign flag

Zero flag

DIR

Direction flag

Interrupt enable flag

Overflow flag

BRK

(···)

disp

ext-disp8

Break flag

Mode flag

Contents in memory shown in ( )

Displacement (8/16 bits)

16 bits obtained by extending sign of 8-bit displacement

µPD70320

Table 2-3. Operation Identifier (2/2)

Identifier

Description

temp

tmpcy

seg

offset

←

Temporary register (8/16/32 bits)

Temporary carry flag (1 bit)

Immediate segment data (16 bits)

Immediate offset data (16 bits)

Transfer direction

Addition

–

Subtraction

Multiplication

Division

Modulo

AND

Exclusive OR

××H

2-digit hexadecimal number

××××H

4-digit hexadecimal number

Table 2-4. Flag Operation Identifier

Identifier

Description

(Blank)

No change

Cleared to 0

Set to 1

Set or cleared according to the result

Not defined

The previously saved value is restored.

Table 2-5. 8/16-Bit General Register Selection

reg

000

001

010

011

100

101

110

111

W = 0

W = 1

µPD70320

Table 2-6. Segment Register Selection

sreg

DS1

DS0

The number of clocks, for memory operand, differs among addressing modes. So, use the following values for

“EA” items shown in Table 2-8 Number of Clocks.

Table 2-7. Number of Clocks for Each Memory Addressing

mod

mem

000

001

010

011

100

101

110

111

Clocks

BW + IX

BW + IY

BP + IX

BP + IY

BW + IX + disp8

BW + IY + disp8

BP + IX + disp8

BP + IY + disp8

IX + disp8

BW + IX + disp16

BW + IY + disp16

BP + IX + disp16

BP + IY + disp16

IX + disp16

IY + disp8

IY + disp16

Direct address

BP + disp8

BP + disp16

BW + disp8

BW + disp16

“T” indicates the number of wait states. Use any number of waits starting at “0” (no wait).

The instruction fetch cycle is not counted as the number of clocks.

There are some branch instructions for which such description as the example below is provided.

The description indicates as follows:

Example 15/8 ···15: the number of clock cycles when branched

8: the number of clock cycles when not branched

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Mnemonic

MOV

Operand

Bytes

Operation

AC CY

Data

transfer

reg,reg

1 0 0 0 1 0 1 W 1 1 reg reg

1 0 0 0 1 0 0 W mod reg mem

1 0 0 0 1 0 1 W mod reg mem

1 1 0 0 0 1 1 W mod 0 0 0 mem

1 0 1 1 W reg

2 to 4

3 to 6

2 to 3

reg ← reg

mem,reg

(mem) ← reg

reg ← (mem)

(mem) ← imm

reg,mem

mem,imm

reg,imm

reg ← imm

When W = 0, AL ← (dmem)

acc,dmem

dmem,acc

sreg,reg16

sreg,mem16

reg16,sreg

mem16,sreg

1 0 1 0 0 0 0 W

When W = 1, AH ← (dmem + 1), AL ← (dmem)

When W = 0, (dmem) ← AL

When W = 1, (dmem + 1) ← AH, (dmem) ← AL

1 0 1 0 0 0 1 W

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 0 1

1 1 0 1 0 1 1 1

1 1 0 sreg reg

mod 0 sreg mem

1 1 0 sreg reg

mod 0 sreg mem

mod reg mem

sreg ← reg16

sreg : SS, DS0, DS1

2 to 4

sreg ← (mem16)

reg16 ← sreg

2 to 4

(mem16) ← sreg

DS0,reg16,

mem32

DS1,reg16,

mem32

reg16 ← (mem32)

DS0 ← (mem32 + 2)

reg16 ← (mem32)

DS1 ← (mem32 + 2)

AH,PSW

PSW,AH

reg16,mem16

src-table

reg,reg

AH ← S, Z, F1, AC, F0, P, IBRK, CY

S, Z, F1, AC, F0, P, IBRK, CY ← AH

reg16 ← mem16

mod reg mem

2 to 4

LDEA

TRANS

XCH

AL ← (BW + AL)

1 0 0 0 0 1 1 W 1 1 reg reg

1 0 0 0 0 1 1 W mod reg mem

1 0 0 1 0 reg

reg ↔ reg

mem,reg

reg,mem

AW,reg16

reg16,AW

2 to 4

(mem) ↔ reg

AW ↔ reg16

MOVSPA^Note

MOVSPB^Note

0 0 0 0 1 1 1 1

1 1 1 1 1 reg

0 0 1 0 0 1 0 1

1 0 0 1 0 1 0 1

New register bank SS and SP ← old register bank SS and SP

reg16

SS and SP of reg16-indicated new register bank ← old register bank

SS and SP

Note These instructions are newly added to the

PD70108/70116.

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Mnemonic

REPC

Operand

Bytes

Operation

AC CY

Executes the primitive block transfer instruction in the continued

byte while CW ≠ 0, and decrements CW by one. If any interruption

is held at this time, it is processed. The program exits the loop

when CY ≠ 1.

0 1 1 0 0 1 0 1

Repeat

prefix

Same as above.

The program exits the loop when CY ≠ 0.

0 1 1 0 0 1 0 0

1 1 1 1 0 0 1 1

REPNC

REP

Executes the primitive block transfer instruction in the continued

byte while CW ≠ 0, and decrements CW by one. If any interruption

is held at this time, it is processed. The program exits the loop

when the primitive block transfer instruction is CMPBK or CMPM,

and when Z ≠ 1.

REPE

REPZ

1 1 1 1 0 0 1 0

Same as above.

The program exits the loop when Z ≠ 0.

REPNE

REPNZ

When W = 0, (IY) ← (IX)

dst-block,

1 0 1 0 0 1 0 W

Primitive MOVBK

block

DIR = 0: IX ← IX + 1, IY ← IY + 1

DIR = 1: IX ← IX – 1, IY ← IY – 1

When W = 1, (IY + 1, IY) ← (IX + 1, IX)

DIR = 0: IX ← IX + 2, IY ← IY + 2

DIR = 1: IX ← IX – 2, IY ← IY – 2

When W = 0, (IX) – (IY)

DIR = 0: IX ← IX + 1, IY ← IY + 1

DIR = 1: IX ← IX – 1, IY ← IY – 1

When W = 1, (IX + 1, IX) – (IY + 1, IY)

DIR = 0: IX ← IX + 2, IY ← IY + 2

DIR = 1: IX ← IX – 2, IY ← IY – 2

When W = 0, AL – (IY)

DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1

When W = 1, AW – (IY + 1, IY)

DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2

When W = 0, AL ← (IX)

DIR = 0: IX ← IX + 1; DIR = 1: IX ← IX – 1

When W = 1, AW ← (IX + 1, IX)

DIR = 0: IX + 2; DIR = 1: IX ← IX – 2

When W = 0, (IY) ← AL

DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1

When W = 1, (IY + 1, IY) ← AW

DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2

transfer

src-block

src-block,

dst-block

1 0 1 0 0 1 1 W

CMPBK

dst-block

src-block

dst-block

1 0 1 0 1 1 1 W

1 0 1 0 1 1 0 W

1 0 1 0 1 0 1 W

CMPM

LDM

STM

Operation Code

Flags

Group

Mnemonic

INS

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

0 0 1 1 0 0 0 1

AC CY

reg8,reg8

0 0 0 0 1 1 1 1

1 1 reg reg

16-bit field ← AW

AW ← 16-bit field

Bit field

opera-

tion

reg8,imm4

reg8,reg8

reg8,imm4

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

1 1 reg reg

0 0 1 1 1 0 0 1

0 0 1 1 0 0 1 1

0 0 1 1 1 0 1 1

EXT

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

1 1 1 0 0 1 0 W

1 1 1 0 1 1 0 W

1 1 1 0 0 1 1 W

1 1 1 0 1 1 1 W

0 1 1 0 1 1 0 W

AW ← 16-bit field

When W = 0, AL ← (imm8)

Note

acc,imm8

acc,DW

I/O

When W = 1, AH ← (imm8 + 1), AL ← (imm8)

When W = 0, AL ← (DW)

When W = 1, AH ← (DW + 1), AL ← (DW)

When W = 0, (imm8) ← AL

When W = 1, (imm8 + 1) ← AH, (imm8) ← AL

When W = 0, (DW) ← AL

When W = 1, (DW + 1) ← AH, (DW) ← AL

When W = 0, (IY) ← (DW)

DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1

When W = 1, (IY + 1, IY) ← (DW + 1, DW)

DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2

When W = 0, (DW) ← (IX)

DIR = 0: IX ← IX + 1; DIR = 1: IX ← IX – 1

When W = 1, (DW + 1, DW) ← (IX + 1, IX)

DIR = 0: IX ← IX + 2; DIR = 1: IX ← IX – 2

Note

imm8,acc

DW,acc

OUT

Note

dst-block,DW

Primitive INM

I/O

Note

DW,src-block

0 1 1 0 1 1 1 W

OUTM

Note When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed.

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Mnemonic

ADD

Operand

Bytes

Operation

AC CY

reg,reg

0 0 0 0 0 0 1 W 1 1 reg reg

0 0 0 0 0 0 0 W mod reg mem

0 0 0 0 0 0 1 W mod reg mem

reg ← reg + reg

Addi-

tion/

subtrac-

tion

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) + reg

reg ← reg + (mem)

reg ← reg + imm

1 0 0 0 0 0 s W

0 0 0 0 0 1 0 W

1 1 0 0 0 reg

mod 0 0 0 mem

(mem) ← (mem) + imm

When W = 0, AL ← AL + imm

When W = 1, AW ← AW + imm

0 0 0 1 0 0 1 W 1 1 reg reg

0 0 0 1 0 0 0 W mod reg mem

0 0 0 1 0 0 1 W mod reg mem

reg ← reg + reg + CY

ADDC

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) + reg + CY

reg ← reg + (mem) + CY

reg ← reg + imm + CY

1 0 0 0 0 0 s W

0 0 0 1 0 1 0 W

1 1 0 1 0 reg

mod 0 1 0 mem

(mem) ← (mem) + imm + CY

When W = 0, AL ← AL + imm + CY

When W = 1, AW ← AW + imm + CY

0 0 1 0 1 0 1 W 1 1 reg reg

0 0 1 0 1 0 0 W mod reg mem

0 0 1 0 1 0 1 W mod reg mem

reg ← reg – reg

SUB

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) – reg

reg ← reg – (mem)

reg ← reg – imm

1 0 0 0 0 0 s W

0 0 1 0 1 1 0 W

1 1 1 0 1 reg

mod 1 0 1 mem

(mem) ← (mem) – imm

When W = 0, AL ← AL – imm

When W = 1, AW ← AW – imm

0 0 0 1 1 0 1 W 1 1 reg reg

0 0 0 1 1 0 0 W mod reg mem

0 0 0 1 1 0 1 W mod reg mem

reg ← reg – reg – CY

SUBC

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) – reg – CY

reg ← reg – (mem) – CY

reg ← reg – imm – CY

1 0 0 0 0 0 s W

0 0 0 1 1 1 0 W

1 1 0 1 1 reg

mod 0 1 1 mem

(mem) ← (mem) – imm – CY

When W = 0, AL ← AL – imm – CY

When W = 1, AW ← AW – imm – CY

Operation Code

Flags

Group

Mnemonic

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

0 0 1 0 0 0 0 0

AC CY

Note

BCD

opera-

tion

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

mod 0 0 0 mem

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

dst BCD string ← dst BCD string + src BCD string

dst BCD string ← dst BCD string – src BCD string

dst BCD string – src BCD string

ADD4S

SUB4S

CMP4S

ROL4

0 0 1 0 0 0 1 0

0 0 1 0 0 1 1 0

0 0 1 0 1 0 0 0

reg

reg8

Upper Lower

Byte

mem

Upper Lower

Byte Byte

mem8

reg8

0 0 1 0 1 0 0 0

0 0 1 0 1 0 1 0

1 1 0 0 0 reg

3 to 5

reg

Upper Lower

Byte Byte

ROR4

mem

Upper Lower

Byte Byte

mem8

0 0 0 0 1 1 1 1

mod 0 0 0 mem

1 1 1 1 1 1 1 0

3 to 5

Incre-

ment/

decre-

ment

reg8

2 to 4

reg8 ← reg8 + 1

INC

mem

reg16

reg8

1 1 1 1 1 1 1 W mod 0 0 0 mem

0 1 0 0 0 reg

(mem) ← (mem) + 1

reg16 ← reg16 + 1

reg8 ← reg8 – 1

1 1 1 1 1 1 1 0

1 1 0 0 1 reg

DEC

mem

reg16

1 1 1 1 1 1 1 W mod 0 0 1 mem

0 1 0 0 1 reg

2 to 4

(mem) ← (mem) – 1

reg16 ← reg16 – 1

n: 1/2 of the number of BCD digits

Note The number of BCD digits is given in the CL register. The value can be set within 1 to 254.

Operation Code

Flags

Group

Mnemonic

MULU

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 1 0 0 reg

AC CY

Multipli-

cation

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

0 1 1 0 1 0 1 1

0 1 1 0 1 0 0 1

AW ← AL × reg8

AH = 0: CY ← 0, V ← 0

AH ≠ 0: CY ← 1, V ← 1

mem8

reg16

mem16

reg8

mod 1 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 reg reg

AW ← AL × (mem8)

AH = 0: CY ← 0, V ← 0

AH ≠ 0: CY ← 1, V ← 1

2 to 4

DW, AW ← AW × reg16

DW = 0: CY ← 0, V ← 0

DW = 1: CY ← 1, V ← 1

DW, AW ← AW × (mem16)

DW = 0: CY ← 0, V ← 0

DW = 1: CY ← 1, V ← 1

2 to 4

AW ← AL × reg8

MUL

Extension of AH = AL sign: CY ← 0, V ← 0

Extension of AH ≠ AL sign: CY ← 1, V ← 1

mem8

reg16

mem16

AW ← AL × (mem8)

2 to 4

Extension of AH = AL sign: CY ← 0, V ← 0

Extension of AH ≠ AL sign: CY ← 1, V ← 1

DW, AW ← AW × reg16

Extension of DW = AW sign: CY ← 0, V ← 0

Extension of DW ≠ AW sign: CY ← 1, V ← 1

DW, AW ← AW × (mem16)

2 to 4

Extension of DW = AW sign: CY ← 0, V ← 0

Extension of DW ≠ AW sign: CY ← 1, V ← 1

reg16,

reg16 ← reg16 × imm8

(reg16,)^Note

imm8

Product ≤ 16 bits: CY ← 0, V ← 0

Product > 16 bits: CY ← 1, V ← 1

reg16,

mem16,

imm8

mod reg mem

1 1 reg reg

reg16 ← (mem16) × imm8

3 to 5

Product ≤ 16 bits: CY ← 0, V ← 0

Product > 16 bits: CY ← 1, V ← 1

reg16,

reg16 ← reg16 × imm16

(reg16,)^Note

imm16

Product ≤ 16 bits: CY ← 0, V ← 0

Product > 16 bits: CY ← 1, V ← 1

reg16,

mem16,

imm16

mod reg mem

reg16 ← (mem16) × imm16

4 to 6

Product ≤ 16 bits: CY ← 0, V ← 0

Product > 16 bits: CY ← 1, V ← 1

Note The 2nd operand is omissible. If omitted, the 1st operand is assumed.

Operation Code

Flags

Group

Mnemonic

DIVU

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 1 1 0 reg

AC CY

Unsign-

division

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

temp ← AW

When temp ÷ reg8 ≤ FFH

AH ← temp%reg8, AL ← temp ÷ reg8

When temp ÷ reg8 > FFH

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

mem8

mod 1 1 0 mem

1 1 1 1 0 reg

mod 1 1 0 mem

2 to 4

temp ← AW

When temp ÷ (mem8) ≤ FFH

AH ← temp%(mem8), AL ← temp ÷ (mem8)

When temp ÷ (mem8) > FFH

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

reg16

temp ← DW, AW

When temp ÷ reg16 ≤ FFFFH

DW ← temp%reg16, AW ← temp ÷ reg16

When temp ÷ reg16 > FFFFH

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

mem16

2 to 4

temp ← DW, AW

When temp ÷ (mem16) ≤ FFFFH

DW ← temp%(mem16), AW ← temp ÷ (mem16)

When temp ÷ (mem16) > FFFFH

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

Operation Code

Flags

Group

Mnemonic

DIV

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 1 1 1 reg

AC CY

Signed

division

reg8

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

temp ← AW

When temp ÷ reg8 > 0 and temp ÷ reg8 ≤ 7FH or

temp ÷ reg8 < 0 and temp ÷ reg8 > 0 – 7FH – 1

AH ← temp%reg8, AL ← temp ÷ reg8

When temp ÷ reg8 > 0 and temp ÷ reg8 > 7FH or

temp ÷ reg8 > 0 and temp ÷ reg8 < 0 – 7FH – 1

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

mem8

mod 1 1 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

2 to 4

temp ← AW

When temp ÷ (mem8) > 0 and temp ÷ (mem8) ≤ 7FH or

temp ÷ (mem8) < 0 and temp ÷ (mem8) > 0 – 7FH – 1

AH ← temp%(mem8), AL ← temp ÷ (mem8)

When temp ÷ (mem8) > 0 and temp ÷ (mem8) > 7FH or

temp ÷ (mem8) > 0 and temp ÷ (mem8) < 0 – 7FH – 1

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

reg16

temp ← DW, AW

When temp ÷ reg16 > 0 and temp ÷ reg16 ≤ 7FFFH or

temp ÷ reg16 < 0 and temp ÷ reg16 > 0 – 7FFFH – 1

DW ← temp%reg16, AW ← temp ÷ reg16

When temp ÷ reg16 > 0 and temp ÷ reg16 > 7FFFH or

temp ÷ reg16 > 0 and temp ÷ reg16 < 0 – 7FFFH – 1

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

mem16

2 to 4

temp ← DW, AW

When temp ÷ (mem16) > 0 and temp ÷ (mem16) ≤ 7FFFH or

temp ÷ (mem16) < 0 and temp ÷ (mem16) > 0 – 7FFFH – 1

DW ← temp%(mem16), AW ← temp ÷ (mem16)

When temp ÷ (mem16) > 0 and temp ÷ (mem16) > 7FFFH or

temp ÷ (mem16) > 0 and temp ÷ (mem16) < 0 – 7FFFH – 1

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0)

Operation Code

Flags

Group

Mnemonic

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

AC CY

When AL 0FH > 9 or AC = 1, AL ← AL + 6

AH ← AH + 1, AC ← 1, CY ← AC, AL ← AL 0FH

When AL 0FH > 9 or AC = 1,

AL ← AL + 6, AC ← 1

BCD

adjust-

ment

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

ADJBA

ADJ4A

When AL > 9FH or CY = 1,

AL ← AL + 60H, CY ← 1

0 0 1 1 1 1 1 1

When AL 0FH > 9 or AC = 1,

AL ← AL – 6, AH ← AH – 1, AC ← 1

CY ← AC, AL ← AL 0FH

ADJBS

ADJ4S

When AL 0FH > 9 or AC = 1,

AL ← AL – 6, AC ← 1

0 0 1 0 1 1 1 1

When AL > 9FH or CY = 1,

AL ← AL – 60H, CY ← 1

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 0 0 1 0 1 0

AH ← AL ÷ 0AH, AL ← AL%0AH

Data

conver-

sion

CVTBD

CVTDB

CVTBW

CVTWL

AL ← AH × 0AH + AL, AH ← 0

When AL < 80H, AH ← 0. In other cases, AH ← FFH.

When AW < 8000H, DW ← 0. In other cases, DW ← FFFFH.

reg,reg

0 0 1 1 1 0 1 W 1 1 reg reg

0 0 1 1 1 0 0 W mod reg mem

0 0 1 1 1 0 1 W mod reg mem

reg – reg

Compare CMP

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) – reg

reg – (mem)

reg – imm

1 0 0 0 0 0 s W

0 0 1 1 1 1 0 W

1 1 1 1 1 reg

mod 1 1 1 mem

(mem) – imm

When W = 0, AL – imm

When W = 1, AW – imm

1 1 1 1 0 1 1 W 1 1 0 1 0 reg

1 1 1 1 0 1 1 W mod 0 1 0 mem

1 1 1 1 0 1 1 W 1 1 0 1 1 reg

1 1 1 1 0 1 1 W mod 0 1 1 mem

reg ← reg

Comple- NOT

ment

opera-

mem

2 to 4

(mem) ← (mem)

reg ← reg + 1

(mem) ← (mem) + 1

tion

reg

NEG

mem

2 to 4

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Mnemonic

TEST

Operand

Bytes

Operation

AC CY

Logical

opera-

tion

reg,reg

1 0 0 0 0 1 0 W 1 1 reg reg

1 0 0 0 0 1 0 W mod reg mem

1 1 1 1 0 1 1 W 1 1 0 0 0 reg

1 1 1 1 0 1 1 W mod 0 0 0 mem

1 0 1 0 1 0 0 W

reg reg

mem,reg

reg,mem

2 to 4

3 to 4

3 to 6

2 to 3

(mem) reg

reg imm

reg,imm

mem,imm

acc,imm

reg,reg

(mem) imm

When W = 0, AL imm8

When W = 1, AW imm16

0 0 1 0 0 0 1 W 1 1 reg reg

0 0 1 0 0 0 0 W mod reg mem

0 0 1 0 0 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 1 0 0 reg

1 0 0 0 0 0 0 W mod 1 0 0 mem

0 0 1 0 0 1 0 W

reg ← reg reg

AND

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) reg

reg ← reg (mem)

reg ← reg imm

(mem) ← (mem) imm

When W = 0, AL ← AL imm8

When W = 1, AW ← AW imm16

0 0 0 0 1 0 1 W 1 1 reg reg

0 0 0 0 1 0 0 W mod reg mem

0 0 0 0 1 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 0 0 1 reg

1 0 0 0 0 0 0 W mod 0 0 1 mem

0 0 0 0 1 1 0 W

reg ← reg reg

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) reg

reg ← reg (mem)

reg ← reg imm

(mem) ← (mem) imm

When W = 0, AL ← AL imm8

When W = 1, AW ← AW imm16

0 0 1 1 0 0 1 W 1 1 reg reg

0 0 1 1 0 0 0 W mod reg mem

0 0 1 1 0 0 1 W mod reg mem

1 0 0 0 0 0 0 W 1 1 1 1 0 reg

1 0 0 0 0 0 0 W mod 1 1 0 mem

0 0 1 1 0 1 0 W

reg ← reg reg

XOR

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

2 to 4

3 to 4

3 to 6

2 to 3

(mem) ← (mem) reg

reg ← reg (mem)

reg ← reg imm

(mem) ← (mem) imm

When W = 0, AL ← AL imm8

When W = 1, AW ← AW imm16

Operation Code

Flags

Group

Mnemonic

TEST1

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 0 0 0 reg

AC CY

reg8 bit No. CL = 0: Z ← 1

reg8 bit No. CL = 1: Z ← 0

(mem8) bit No. CL = 0: Z ← 1

(mem8) bit No. CL = 1: Z ← 0

reg16 bit No. CL = 0: Z ← 1

reg16 bit No. CL = 1: Z ← 0

Bit

manipu-

lation

reg8,CL

0 0 0 1 0 0 0 0

0 0 0 0

0 0 0 1

1 0 0 0

1 0 0 1

0 1 1 0

0 1 1 1

1 1 1 0

1 1 1 1

3 to 5

mem8,CL

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

reg16,CL

(mem16) bit No. CL = 0: Z ← 1

(mem16) bit No. CL = 1: Z ← 0

reg8 bit No. imm3 = 0: Z ← 1

reg8 bit No. imm3 = 1: Z ← 0

(mem8) bit No. imm3 = 0: Z ← 1

(mem8) bit No. imm3 = 1: Z ← 0

reg16 bit No. imm4 = 0: Z ← 1

reg16 bit No. imm4 = 1: Z ← 0

(mem16) bit No. imm4 = 0: Z ← 1

(mem16) bit No. imm4 = 1: Z ← 0

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

reg8,CL

3 to 5

4 to 6

reg8 bit No. CL ← reg8 bit No. CL

NOT1

mem8,CL

3 to 5

(mem8) bit No. CL ← (mem8) bit No. CL

reg16 bit No. CL ← reg16 bit No. CL

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

3 to 5

(mem16) bit No. CL ← (mem16) bit No. CL

reg8 bit No. imm3 ← reg8 bit No. imm3

(mem8) bit No. imm3 ← (mem8) bit No. imm3

reg16 bit No. imm4 ← reg16 bit No. imm4

(mem16) bit No. imm4 ← (mem16) bit No. imm4

4 to 6

2nd byte ^Note

3rd byte ^Note

1st byte = 0FH

Note

NOT1

1 1 1 1 0 1 0 1

CY ← CY

Operation Code

Flags

Group

Mnemonic

CLR1

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 0 0 0 reg

AC CY

Bit

manipu-

lation

reg8,CL

0 0 0 1 0 0 1 0

0 0 1 0

0 0 1 1

1 0 1 0

1 0 1 1

0 1 0 0

0 1 0 1

1 1 0 0

1 1 0 1

3 to 5

reg8 bit No. CL ← 0

mem8,CL

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

(mem8) bit No. CL ← 0

reg16 bit No. CL ← 0

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

reg8,CL

3 to 5

(mem16) bit No. CL ← 0

reg8 bit No. imm3 ← 0

(mem8) bit No. imm3 ← 0

reg16 bit No. imm4 ← 0

(mem16) bit No. imm4 ← 0

reg8 bit No. CL ← 1

4 to 6

SET1

mem8,CL

3 to 5

(mem8) bit No. CL ← 1

reg16 bit No. CL ← 1

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

3 to 5

(mem16) bit No. CL ← 1

reg8 bit No. imm3 ← 1

(mem8) bit No. imm3 ← 1

reg16 bit No. imm4 ← 1

(mem16) bit No. imm4 ← 1

4 to 6

2nd byte ^Note

3rd byte ^Note

Note 1st byte = 0FH

CLR1

SET1

1 1 1 1 1 0 0 0

1 1 1 1 1 1 0 0

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 1

CY ← 0

DIR ← 0

CY ← 1

DIR ← 1

DIR

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Shift

Mnemonic

SHL

Operand

Bytes

Operation

AC CY

reg,1

1 1 0 1 0 0 0 W 1 1 1 0 0 reg

1 1 0 1 0 0 0 W mod 1 0 0 mem

1 1 0 1 0 0 1 W 1 1 1 0 0 reg

1 1 0 1 0 0 1 W mod 1 0 0 mem

1 1 0 0 0 0 0 W 1 1 1 0 0 reg

1 1 0 0 0 0 0 W mod 1 0 0 mem

CY ← reg MSB, reg ← reg × 2

When reg MSB ≠ CY, V ← 1

When reg MSB = CY, V ← 0

mem,1

2 to 4

CY ← (mem) MSB, (mem) ← (mem) × 2

When (mem) MSB ≠ CY, V ← 1

When (mem) MSB = CY, V ← 0

The following operations are repeated while temp ← CL

and temp ≠ 0.

reg,CL

CY ← reg MSB, reg ← reg × 2

temp ← temp – 1

The following operations are repeated while temp ← CL

and temp ≠ 0.

CY ← (mem) MSB, (mem) ← (mem) × 2

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

mem,CL

reg,imm8

mem,imm8

2 to 4

CY ← reg MSB, reg ← reg × 2

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

3 to 5

CY ← (mem) MSB, (mem) ← (mem) × 2

temp ← temp – 1

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Shift

Mnemonic

SHR

Operand

Bytes

Operation

AC CY

reg,1

1 1 0 1 0 0 0 W 1 1 1 0 1 reg

1 1 0 1 0 0 0 W mod 1 0 1 mem

1 1 0 1 0 0 1 W 1 1 1 0 1 reg

1 1 0 1 0 0 1 W mod 1 0 1 mem

1 1 0 0 0 0 0 W 1 1 1 0 1 reg

1 1 0 0 0 0 0 W mod 1 0 1 mem

CY ← reg LSB, reg ← reg ÷ 2

reg MSB ≠ bit following reg MSB: V ← 1

reg MSB = bit following reg MSB: V ← 0

mem,1

2 to 4

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

(mem) MSB ≠ bit following (mem) MSB: V ← 1

(mem) MSB = bit following (mem) MSB: V ← 0

The following operations are repeated while temp ← CL

and temp ≠ 0.

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

The following operations are repeated while temp ← CL

and temp ≠ 0.

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

reg,CL

mem,CL

reg,imm8

mem,imm8

2 to 4

The following operations are repeated while temp ← imm8

and temp ≠ 0.

3 to 5

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1

CY ← reg LSB, reg ← reg ÷ 2, V ← 0

The operand MSB remains the same status.

CY ← (mem) LSB, (mem) ← (mem) ÷ 2, V ← 0

The operand MSB remains the same status.

The following operations are repeated while temp ← CL

and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

reg,1

1 1 0 1 0 0 0 W 1 1 1 1 1 reg

1 1 0 1 0 0 0 W mod 1 1 1 mem

1 1 0 1 0 0 1 W 1 1 1 1 1 reg

2 to 4

SHRA

mem,1

reg,CL

The operand MSB remains the same status.

The following operations are repeated while temp ← CL

and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1

The operand MSB remains the same status.

The following operations are repeated while temp ← imm8

and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2

temp ← temp – 1

The operand MSB remains the same status.

The following operations are repeated while temp ← imm8

and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2

temp ← temp – 1

mem,CL

1 1 0 1 0 0 1 W mod 1 1 1 mem

1 1 0 0 0 0 0 W 1 1 1 1 1 reg

1 1 0 0 0 0 0 W mod 1 1 1 mem

2 to 4

reg,imm8

mem,imm8

3 to 5

The operand MSB remains the same status.

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Rotate

Mnemonic

ROL

Operand

Bytes

Operation

AC CY

reg,1

1 1 0 1 0 0 0 W 1 1 0 0 0 reg

1 1 0 1 0 0 0 W mod 0 0 0 mem

1 1 0 1 0 0 1 W 1 1 0 0 0 reg

1 1 0 1 0 0 1 W mod 0 0 0 mem

1 1 0 0 0 0 0 W 1 1 0 0 0 reg

1 1 0 0 0 0 0 W mod 0 0 0 mem

1 1 0 1 0 0 0 W 1 1 0 0 1 reg

1 1 0 1 0 0 0 W mod 0 0 1 mem

1 1 0 1 0 0 1 W 1 1 0 0 1 reg

1 1 0 1 0 0 1 W mod 0 0 1 mem

1 1 0 0 0 0 0 W 1 1 0 0 1 reg

1 1 0 0 0 0 0 W mod 0 0 1 mem

CY ← reg MSB, reg ← reg × 2 + CY

reg MSB ≠ CY: V ← 1

reg MSB = CY: V ← 0

mem,1

2 to 4

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

(mem) MSB ≠ CY: V ← 1

(mem) MSB = CY: V ← 0

The following operations are repeated while temp ← CL

and temp ≠ 0.

CY ← reg MSB, reg ← reg × 2 + CY

temp ← temp – 1

The following operations are repeated while temp ← CL

and temp ≠ 0.

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

CY ← reg MSB, reg ← reg × 2 + CY

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

CY ← (mem) MSB, (mem) ← (mem) × 2 + CY

temp ← temp – 1

reg,CL

mem,CL

reg,imm8

mem,imm8

reg,1

2 to 4

3 to 5

CY ← reg LSB, reg ← reg ÷ 2

reg MSB ← CY

ROR

reg MSB ≠ bit following reg MSB: V ← 1

reg MSB = bit following reg MSB: V ← 0

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

(mem) MSB ← CY

(mem) MSB ≠ bit following (mem) MSB: V ← 1

(mem) MSB = bit following (mem) MSB: V ← 0

The following operations are repeated while temp ← CL and temp ≠ 0.

CY ← reg LSB, reg ← reg ÷ 2

mem,1

2 to 4

reg,CL

reg MSB ← CY

temp ← temp – 1

The following operations are repeated while temp ← CL and temp ≠ 0.

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

(mem) MSB ← CY

mem,CL

reg,imm8

mem,imm8

2 to 4

temp ← temp – 1

The following operations are repeated while temp ← imm8 and temp ≠ 0.

CY ← reg LSB, reg ← reg ÷ 2

reg MSB ← CY

temp ← temp – 1

The following operations are repeated while temp ← imm8 and temp ≠ 0.

CY ← (mem) LSB, (mem) ← (mem) ÷ 2

(mem) MSB ← CY

3 to 5

temp ← temp – 1

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Rotate

Mnemonic

ROLC

Operand

Bytes

Operation

AC CY

tmpcy ← CY, CY ← reg MSB

reg ← reg × 2 + tmpcy

reg MSB ≠ CY: V ← 1

reg MSB = CY: V ← 0

reg,1

1 1 0 1 0 0 0 W 1 1 0 1 0 reg

1 1 0 1 0 0 0 W mod 0 1 0 mem

1 1 0 1 0 0 1 W 1 1 0 1 0 reg

1 1 0 1 0 0 1 W mod 0 1 0 mem

1 1 0 0 0 0 0 W 1 1 0 1 0 reg

tmpcy ← CY, CY ← (mem) MSB

(mem) ← (mem) × 2 + tmpcy

mem,1

2 to 4

(mem) MSB ≠ CY: V ← 1

(mem) MSB = CY: V ← 0

The following operations are repeated while temp ← CL and temp ≠ 0.

tmpcy ← CY, CY ← reg MSB

reg,CL

reg ← reg × 2 + tmpcy

temp ← temp – 1

The following operations are repeated while temp ← CL and temp ≠ 0.

tmpcy ← CY, CY ← (mem) MSB

(mem) ← (mem) × 2 + tmpcy

mem,CL

reg,imm8

2 to 4

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

tmpcy ← CY, CY ← reg MSB

reg ← reg × 2 + tmpcy

temp ← temp – 1

mem,imm8

1 1 0 0 0 0 0 W mod 0 1 0 mem

3 to 5

The following operations are repeated while temp ← imm8

and temp ≠ 0.

tmpcy ← CY, CY ← (mem) MSB

(mem) ← (mem) × 2 + tmpcy

temp ← temp – 1

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Rotate

Mnemonic

RORC

Operand

Bytes

Operation

AC CY

reg,1

1 1 0 1 0 0 0 W 1 1 0 1 1 reg

1 1 0 1 0 0 0 W mod 0 1 1 mem

1 1 0 1 0 0 1 W 1 1 0 1 1 reg

1 1 0 1 0 0 1 W mod 0 1 1 mem

1 1 0 0 0 0 0 W 1 1 0 1 1 reg

1 1 0 0 0 0 0 W mod 0 1 1 mem

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

reg MSB ≠ bit following reg MSB: V ← 1

reg MSB = bit following reg MSB: V ← 0

mem,1

2 to 4

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

(mem) MSB ≠ bit following (mem) MSB: V ← 1

(mem) MSB = bit following (mem) MSB: V ← 0

reg,CL

The following operations are repeated while temp ← CL and temp ≠ 0.

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

temp ← temp – 1

mem,CL

reg,imm8

mem,imm8

2 to 4

The following operations are repeated while temp ← CL and temp ≠ 0.

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

tmpcy ← CY, CY ← reg LSB

reg ← reg ÷ 2

reg MSB ← tmpcy

temp ← temp – 1

The following operations are repeated while temp ← imm8

and temp ≠ 0.

3 to 5

tmpcy ← CY, CY ← (mem) LSB

(mem) ← (mem) ÷ 2

(mem) MSB ← tmpcy

temp ← temp – 1

Operation Code

Flags

Group

Mnemonic

CALL

Operand

Bytes

Operation

(SP – 1, SP – 2) ← PC, SP ← SP – 2

PC ← PC + disp

(SP – 1, SP – 2) ← PC, PC ← regptr16

SP ← SP – 2

7 6 5 4 3 2 1 0

AC CY

Sub-

routine

control

near-proc

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

regptr16

memptr16

far-proc

1 1 0 1 0 reg

(SP – 1, SP – 2) ← PC, SP ← SP – 2

PC ← (memptr16)

mod 0 1 0 mem

2 to 4

(SP – 1, SP – 2) ← PS, (SP – 3, SP – 4) ← PC

SP ← SP – 4

PS ← seg, PC ← offset

memptr32

pop-value

1 1 1 1 1 1 1 1

mod 0 1 1 mem

2 to 4

(SP – 1, SP – 2) ← PS, (SP – 3, SP – 4) ← PC

SP ← SP – 4

PS ← (memptr32 + 2), PC ← (memptr32)

PC ← (SP + 1, SP)

SP ← SP + 2

PC ← (SP + 1, SP)

SP ← SP + 2, SP ← SP + pop-value

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

RET

PC ← (SP + 1, SP)

PS ← (SP + 3, SP + 2)

SP ← SP + 4

1 1 0 0 1 0 1 0

PC ← (SP + 1, SP)

PS ← (SP + 3, SP + 2)

SP ← SP + 4, SP ← SP + pop-value

Operation Code

Flags

Group

Mnemonic

PUSH

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

mod 1 1 0 mem

AC CY

(SP – 1, SP – 2) ← (mem16)

SP ← SP – 2

(SP – 1, SP – 2) ← reg16

SP ← SP – 2

(SP – 1, SP – 2) ← sreg

SP ← SP – 2

mem16

2 to 4

Stack

manipu-

lation

reg16

sreg

0 1 0 1 0 reg

0 0 0 sreg 1 1 0

1 0 0 1 1 1 0 0

0 1 1 0 0 0 0 0

0 1 1 0 1 0 1 0

0 1 1 0 1 0 0 0

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 sreg 1 1 1

1 0 0 1 1 1 0 1

0 1 1 0 0 0 0 1

1 1 0 0 1 0 0 0

1 1 0 0 1 0 0 1

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

1 1 1 1 1 1 1 1

(SP – 1, SP – 2) ← PSW

SP ← SP – 2

PSW

Push registers on the stack

(SP – 1, SP – 2) ← imm8 sign extension

SP ← SP – 2

(SP – 1, SP – 2) ← imm16

SP ← SP – 2

SP ← SP + 2

(mem16) ← (SP – 1, SP – 2)

SP ← SP + 2

reg16 ← (SP – 1, SP – 2)

SP ← SP + 2

sreg ← (SP – 1, SP – 2)

SP ← SP + 2

imm8

imm16

mem16

reg16

sreg

mod 0 0 0 mem

2 to 4

POP

sreg: SS, DS0, DS1

PSW

PSW ← (SP – 1, SP – 2)

Pop registers from the stack

Prepare New Stack Frame

Dispose of Stack Frame

PC ← PC + disp

imm16,imm8

PREPARE

DISPOSE

near-label

short-label

regptr16

Branch

PC ← PC + ext-disp8

PC ← regptr16

1 1 1 0 0 reg

mod 1 0 0 mem

memptr16

far-label

2 to 4

PC ← (memptr16)

PS ← seg

PC ← offset

PS ← (memptr32 + 2)

PC ← (memptr32)

mod 1 0 1 mem

memptr32

2 to 4

Operation Code

Flags

Group

Mnemonic

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

AC CY

Condi-

tional

branch

short-label

0 1 1 1 0 0 0 0

0 0 0 1

if V = 1

PC ← PC + ext-disp8

if V = 0

BNV

BNC

BNL

BNE

BNZ

0 0 1 0

if CY = 1

0 0 1 1

if CY = 0

0 1 0 0

if Z = 1

0 1 0 1

if Z = 0

0 1 1 0

if CY Z = 1

if CY Z = 0

if S = 1

BNH

0 1 1 1

1 0 0 0

1 0 0 1

if S = 0

1 0 1 0

if P = 1

BPE

1 0 1 1

if P = 0

BPO

BLT

1 1 0 0

if S V = 1

if S V = 0

if (S V) Z = 1

if (S V) Z = 0

1 1 0 1

BGE

BLE

1 1 1 0

1 1 1 1

BGT

DBNZNE

DBNZE

DBNZ

BCWZ

CW = CW – 1

if Z = 0 and CW ≠ 0

CW = CW – 1

if Z = 1 and CW ≠ 0

CW = CW – 1

if CW ≠ 0

1 1 1 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

if CW = 0

Note

sfr,

imm3,

short-label

0 0 0 0 1 1 1 1

1 0 0 1 1 1 0 0

When (sfr) bit No. imm3 = 1, PC ← PC + ext-disp8 and (sfr)

bit No. imm3 ← 0.

BTCLR

Note This instruction is newly added to the

PD70108/70116.

Operation Code

Flags

Group

Mnemonic

BRK

Operand

Bytes

Operation

7 6 5 4 3 2 1 0

AC CY

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS,

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0

Interrupt

1 1 0 0 1 1 0 0

1 1 0 0 1 1 0 1

1 1 0 0 1 1 1 0

PS ← (15, 14), PC ← (13, 12)

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS,

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0

imm8

( ≠ 3)

PS ← (n × 4 + 3, n × 4 + 2), PC ← (n × 4 + 1, n × 4) n = imm8

When V = 1,

BRKV

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS,

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0

PS ← (19, 18), PC ← (17, 16)

PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2),

PSW ← (SP + 5, SP + 4), SP ← SP + 6

1 1 0 0 1 1 1 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 1 0

RETI

RETRBI^Note

FINT ^Note

CHKIND

1 0 0 1 0 0 0 1

1 0 0 1 0 0 1 0

mod reg mem

PC ← Save PC, PSW ← Save PSW

Reports the CPU internal interrupt controller that interrupt service

routine operation has ended.

reg16,mem32

2 to 4

When (mem32) > reg16 or (mem32 + 2) < reg16,

(SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS,

(SP – 5, SP – 6) ← PC, SP ← SP – 6

IE ← 0, BRK ← 0

PS ← (23, 22), PC ← (21, 20)

bank

switch

reg16

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

1 1 1 1 1 reg

0 0 1 0 1 1 0 1

RB2 – 0 ← lower 3 bits of reg16, IE ← 0, BRK ← 0

Save PSW ← PSW, Save PC ← PC, PC ← Vector PC

TSKSW ^Note

1 0 0 1 0 1 0 0

RB2 – 0 ← lower 3 bits of reg16,

Old register bank Save PSW and Save PC ← PSW and PC,

PSW and PC ← New register bank Save PSW and Save PC

Note These instructions are newly added to the µPD70108/70116.

Operation Code

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Flags

Group

Mnemonic

HALT

Operand

Bytes

Operation

AC CY

CPU

1 1 1 1 0 1 0 0

0 0 0 0 1 1 1 1

1 0 0 1 1 0 1 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 0 0 0

1 1 0 1 1 X X X

0 1 1 0 0 1 1 X

1 0 0 1 0 0 0 0

0 0 1 sreg 1 1 0

CPU Halt

control

1 0 0 1 1 1 1 0

CPU Stop

STOP

Note 2

Poll and wait

IE ← 0

POLL

IE ← 1

Bus Lock Prefix

No Operation

data bus ← (mem)

No Operation

data bus ← (mem)

No Operation

Segment override prefix

BUSLOCK

FPO1

Note 3

fp-op

1 1 Y Y Y Z Z Z

mod Y Y Y mem

1 1 Y Y Y Z Z Z

mod Y Y Y mem

2 to 4

fp-op,mem

fp-op

FPO2

Note 3

fp-op,mem

2 to 4

NOP

Note 1

Notes 1.DS0:, DS1:, PS: and SS:

2. This instruction is newly added to the µPD70108/70116.

3. In the µPD70320, an interrupt is generated without executing these instructions.

µPD70320

Table 2-8. Number of Clocks (1/10)

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Data

MOV

reg, reg

transfer

mem, reg

EA + 4 + T

EA + 2

EA + 6 + 2·T

EA + 8 + 2·T

EA + 5 + 2·T

EA + 2

reg, mem

EA + 6 + T

EA + 8 + 2·T

mem, imm

reg, imm

EA + 5 + T

9 + T

7 + T

—

9 + T

acc, dmem

dmem, acc

sreg, reg16

sreg, mem16

reg16, sreg

mem16, sreg

11 + 2·T

9 + 2·T

11 + 2·T

—

EA + 10 + 2·T

—

EA + 7 + 2·T

EA + 19 + 4·T

EA + 3

DS0, reg16,

mem32

—

EA + 19 + 4·T

DS1, reg16,

mem32

—

EA + 19 + 4·T

AH, PSW

PSW, AH

reg16, mem16

src-table

—

LDEA

TRANS

XCH

—

10 + T

—

10 + T

EA + 2

—

reg, reg

mem, reg/

reg, mem

EA + 10 + 2·T

EA + 8 + 2·T

EA + 14 + 2·T

EA + 10 + 2·T

AW, reg16/

reg16, AW

—

MOVSPA

MOVSPB

REPC

—

reg16

Repeat

prefix

REPNC

REP/REPE/

REPZ

REPNE/

REPNZ

Primitive

block

MOVKB^Note

dst-block,

src-block

20 + 2·T

16 + (16 + 2·T)·n

23 + 2·T

16 + T

16 + (12 + T)·n

19 + T

24 + 4·T

20 + 2·T

16 + (20 + 4·T)·n 16 + (12 + 2·T)·n

27 + 4·T 21 + 4·T

transfer

CMPKB^Note

dst-block,

src-block

16 + (21 + 2·T)·n 16 + (21 + 2·T)·n 16 + (25 + 4·T)·n 16 + (25 + 2·T)·n

Note n ≥ 1

µPD70320

Table 2-8. Number of Clocks (2/10)

Byte Processing

Word Processing

On-chip RAM On-chip RAM

Group

Mnemonic

CMPM^{Note 1}

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

19 + 2·T

Access Disable

19 + 2·T

Primitive

block

dst-block

17 + T

16 + (15 + T)·n

12 + T

17 + T

16 + (15 + T)·n

12 + T

src-block

16 + (17 + 2·T)·n 16 + (17 + 2·T)·n

14 + 2·T 14 + 2·T

16 + (12 + 2·T)·n 16 + (12 + 2·T)·n

14 + 2·T 10

16 + (10 + 2·T)·n 16 + (6 + 2·T)·n

transfer

LDM^{Note 1}

STM^{Note 1}

INS

src-block

16 + (10 + T)·n

12 + T

16 + (10 + T)·n

dst-block

16 + (8 + T)·n

16 + (6+ T)·n

Bit field

manipula-

tion

reg8, reg8

reg8, imm4

reg8, reg8

reg8, imm4

acc, imm8

acc, DW

63 to 155 (The processing differs among bit lengths.)

64 to 156 (The processing differs among bit lengths.)

41 to 121 (The processing differs among bit lengths.)

42 to 122 (The processing differs among bit lengths.)

EXT

I/O

IN^{Note 2}

14 + T

13 + T

10 + T

9 + T

14 + T

13 + T

10 + T

9 + T

16 + 2·T

15 + 2·T

10 + 2·T

9 + 2·T

16 + 2·T

15 + 2·T

10 + 2·T

9 + 2·T

OUT^{Note 2}

INM^{Note 2}

OUTM^{Note 2}

ADD

imm8, acc

DW, acc

Primitive

I/O

dst-block, DW

19 + 2·T

17 + 2·T

21 + 4·T

17 + 4·T

18 + (13 + 2·T)·n 18 + (11 + 2·T)·n 18 + (15 + 4·T)·n 18 + (11 + 4·T)·n

19 + 2·T 17 + 2·T 21 + 4·T 17 + 4·T

18 + (13 + 2·T)·n 18 + (11 + 2·T)·n 18 + (15 + 4·T)·n 18 + (11 + 4·T)·n

DW, src-block

Addition/

reg, reg

subtraction

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

reg, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

EA + 6 + T

EA + 8 + 2·T

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

ADDC

EA + 8 + 2·T

EA + 6 + T

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

EA + 12 + 4·T

EA + 8 + 2·T

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

Notes 1. n ≥ 1

2. When IBRK = 1

µPD70320

Table 2-8. Number of Clocks (3/10)

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Addition/

SUB

reg, reg

subtraction

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

reg, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

EA + 6 + T

EA + 8 + 2·T

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

SUBC

EA + 8 + 2·T

EA + 6 + T

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

EA + 12 + 4·T

EA + 8 + 2·T

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

BCD

ADD4S^Note

SUB4S^Note

CMP4S^Note

ROL4

22 + (27 + 3·T)·n 22 + (25 + 3·T)·n

22 + (23 + 3·T)·n 22 + (23 + 3·T)·n

—

operation

—

reg8

—

mem8

reg8

EA + 18 + 2·T

EA + 16 + 2·T

—

ROR4

—

mem8

reg8

EA + 24 + 2·T

EA + 22 + 2·T

—

Increment/ INC

decrement

—

mem8

reg16

reg8

EA + 11 + 2·T

EA + 9 + 2·T

EA + 15 + 4·T

EA + 11 + 4·T

—

DEC

—

mem8

reg16

reg8

EA + 11 + 2·T

EA + 9 + 2·T

EA + 15 + 4·T

EA + 11 + 4·T

—

Multiplica- MULU

tion

—

mem8

reg16

mem16

EA + 26 + T

—

EA + 34 + 2·T

Note n: 1/2 of the number of BCD digits.

µPD70320

Table 2-8. Number of Clocks (4/10)

Byte Processing

Word Processing

On-chip RAM On-chip RAM

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Multiplica- MUL

tion

reg8

31 to 40

—

mem8

EA + 33 + T to

EA + 42 + T

EA + 33 + T to

EA + 42 + T

reg16

—

39 to 48

mem16

EA + 43 + 2·T to EA + 43 + 2·T to

EA + 52 + 2·T

39 to 49

EA + 52 + 2·T

39 to 49

reg16, (reg16,)

imm8

—

reg16, mem16,

imm8

EA + 43 + 2·T to EA + 43 + 2·T to

EA + 53 + 2·T

40 to 50

EA + 53 + 2·T

40 to 50

reg16, (reg16,)

imm16

reg16, mem16,

imm16

EA + 44 + 2·T to EA + 44 + 2·T to

EA + 54 + 2·T

Unsigned DIVU

division

reg8

EA + 33 + T

—

EA + 33 + T

—

mem8

reg16

mem16

reg8

—

EA + 43 + 2·T

Signed

division

DIV

46 to 56

—

mem8

EA + 48 + T to

EA + 58 + T

EA + 48 + T to

EA + 58 + T

reg16

—

54 to 64

mem16

EA + 58 + 2·T to EA + 58 + 2·T to

EA + 68 + 2·T

BCD

ADJBA

ADJ4A

ADJBS

ADJ4S

CVTBD

CVTDB

CVTBW

CVTWL

—

adjustment

—

Data

—

conversion

—

Compare CMP

reg, reg

mem, reg

reg, mem

reg, imm

mem, imm

acc, imm

EA + 6 + T

EA + 8 + 2·T

EA + 7 + T

EA + 10 + 2·T

µPD70320

Table 2-8. Number of Clocks (5/10)

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Comple

ment

NOT

reg

mem

reg

EA + 11 + 2·T

EA + 9 + T

EA + 15 + 4·T

EA + 11 + 2·T

operation

NEG

mem

reg, reg

EA + 11 + 2·T

EA + 9 + T

EA + 15 + 4·T

EA + 11 + 2·T

Logical

TEST

operation

mem, reg/

reg, mem

EA + 8 + T

EA + 10 + 2·T

reg, imm

mem, imm

acc, imm

reg, reg

EA + 11 + T

EA + 11 + 2·T

AND

mem, reg

reg, mem

reg, imm

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

EA + 6 + T

EA + 8 + 2·T

mem, imm

acc, imm

reg, reg

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

mem, reg

reg, mem

reg, imm

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

EA + 6 + T

EA + 8 + 2·T

mem, imm

acc, imm

reg, reg

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

XOR

mem, reg

reg, mem

reg, imm

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

EA + 6 + T

EA + 8 + 2·T

mem, imm

acc, imm

reg8, CL

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

Bit

TEST1

—

manipula-

tion

mem8, CL

reg16, CL

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

reg8, CL

EA + 11 + T

—

EA + 13 + 2·T

—

EA + 8 + T

—

EA + 10 + 2·T

NOT1

EA + 13 + 2·T

—

EA + 11 + T

—

mem8, CL

reg16, CL

µPD70320

Table 2-8. Number of Clocks (6/10)

Byte Processing

Word Processing

On-chip RAM On-chip RAM

Group

Mnemonic

NOT1

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Bit

mem16, CL

—

EA + 17 + 4·T

EA + 13 + 2·T

manipula-

tion

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

—

EA + 10 + 2·T

EA + 8 + T

—

EA + 14 + 4·T

EA + 10 + 2·T

NOT1

CLR1

Bit

reg8, CL

—

manipula-

tion

mem8, CL

reg16, CL

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

reg8, CL

EA + 14 + 2·T

EA + 12 + T

—

EA + 18 + 4·T

EA + 14 + 2·T

—

EA + 11 + 2·T

EA + 9 + T

—

EA + 15 + 4·T

EA + 10 + 2·T

SET1

—

mem8, CL

reg16, CL

mem16, CL

reg8, imm3

mem8, imm3

reg16, imm4

mem16, imm4

EA + 13 + 2·T

EA + 11 + T

—

EA + 17 + 4·T

EA + 13 + 2·T

—

EA + 10 + 2·T

EA + 8 + T

—

EA + 14 + 4·T

EA + 10 + 2·T

CLR1

SET1

SHL

DIR

Shift

reg,1

Note

mem, 1

EA + 14 + 2·T

11 + 2·n

EA + 12 + T

11 + 2·n

EA + 18 + 4·T

11 + 2·n

EA + 14 + 2·T

11 + 2·n

reg, CL

mem, CL

reg, imm8

mem, imm8

reg, 1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

SHR

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

Note n: Shift count

µPD70320

Table 2-8. Number of Clocks (7/10)

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Shift

SHR

reg, CL

11 + 2·n

Note

mem, CL

reg, imm8

mem, imm8

reg,1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

SHRA

Note

mem, 1

EA + 14 + 2·T

11 + 2·n

EA + 12 + T

11 + 2·n

EA + 18 + 4·T

11 + 2·n

EA + 14 + 2·T

11 + 2·n

reg, CL

mem, CL

reg, imm8

mem, imm8

reg,1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

Rotate

ROL

mem, 1

EA + 14 + 2·T

11 + 2·n

EA + 12 + T

11 + 2·n

EA + 18 + 4·T

11 + 2·n

EA + 14 + 2·T

11 + 2·n

reg, CL

mem, CL

reg, imm8

mem, imm8

reg,1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

ROR

mem, 1

EA + 14 + 2·T

11 + 2·n

EA + 12 + T

11 + 2·n

EA + 18 + 4·T

11 + 2·n

EA + 14 + 2·T

11 + 2·n

reg, CL

mem, CL

reg, imm8

mem, imm8

reg,1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

ROLC

mem, 1

EA + 14 + 2·T

11 + 2·n

EA + 12 + T

11 + 2·n

EA + 18 + 4·T

11 + 2·n

EA + 14 + 2·T

11 + 2·n

reg, CL

mem, CL

reg, imm8

mem, imm8

reg,1

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

RORC

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

Note n: Shift count

µPD70320

Table 2-8. Number of Clocks (8/10)

Byte Processing

Word Processing

On-chip RAM On-chip RAM

Group

Rotate

Mnemonic

RORC

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

11 + 2·n

Access Disable

11 + 2·n

reg, CL

11 + 2·n

Note

mem, CL

reg, imm8

mem, imm8

near-proc

regptr16

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

Subroutine CALL

control

—

22 + 2·T

18 + 2·T

EA + 24 + 4·T

34 + 4·T

EA + 24 + 8·T

20 + 2·T

29 + 4·T

30 + 4·T

EA + 14 + 4·T

memptr16

far-proc

EA + 26 + 4·T

38 + 4·T

memptr32

EA + 36 + 8·T

20 + 2·T

RET

pop-value

20 + 2·T

29 + 4·T

pop-value

mem16

reg16

sreg

30 + 4·T

Stack

PUSH

EA + 18 + 4·T

10 + 2·T

manipula-

tion

11 + 2·T

PSW

10 + 2·T

82 + 16·T

13 + 2·T

imm8

imm16

mem16

reg16

sreg

14 + 2·T

POP

EA + 16 + 4·T

12 + 2·T

EA + 12 + 2·T

12 + 2·T

13 + 2·T

14 + 2·T

13 + 2·T

PSW

14 + 2·T

82 + 16·T

PREPARE

DISPOSE

imm16, imm8

When imm8 = 0, 27 + 2·T

When imm8 = 1, 39 + 4·T

When imm8 = n, n > 1, 46 + 19(n – 1) + 4·T

12 + 2·T

—

12 + 2·T

Note n: Shift count

µPD70320

Table 2-8. Number of Clocks (9/10)

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Branch

near-label

—

29/21

—

29/21

short-label

regptr16

memptr16

far-label

EA + 17 + 2·T

memptr32

short-label

EA + 25 + 4·T

15/8

EA + 25 + 4·T

15/8

Conditional BV

branch

BNV

15/8

BC/BL

BNC/BNL

BE/BZ

BNE/BNZ

BNH

15/8

BPE

15/8

BPO

15/8

BLT

15/8

BGE

15/8

BLE

15/8

BGT

15/8

DBNZNE

DBNZE

DBNZ

BCWZ

BTCLR

17/8

15/8

sfr, imm3,

short-label

—

Interrupt

BRK

—

55 + 10·T

56 + 10·T

55 + 10·T

45 + 6·T

43 + 10·T

44 + 10·T

43 + 10·T

37 + 2·T

imm8 (≠3)

BRKV

RETI

RETRBI

FINT

CHKIND

reg16, mem32

—

EA + 26 + 4·T

µPD70320

Table 2-8. Number of Clocks (10/10)

Byte Processing

Word Processing

On-chip RAM On-chip RAM

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

BRKCS

TSKSW

HALT

STOP

POLL

reg16

—

bank switch

reg16

CPU

—

control

—

BUSLOCK

FPO1

fp-op

—

60 + 10·T

48 + 10·T

fp-op, mem

fp-op

FPO2

fp-op, mem

NOP

Segment override prefix

(DS0:, DS1:, PS: and SS:)

µPD70320

3. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Parameter

Supply Voltage

Symbol

VDD

VTH

Test Conditions

Rating

– 0.5 to +7.0

– 0.5 to VDD + 0.5

4.0

Unit

Input Voltage

Output Voltage

Output Current Low

IOL

Each output pin

Total

°C

Output Current High

IOH

Each output pin

Total

–2.0

–20

Operating Ambient Temperature

Storage Temperature

–40 to +85

– 65 to +150

T^stg

Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each

other, and also avoid direct connections to V^DD, VCC or GND. However, the open drain pins or

the open collector pins can be directly connected with each other. For the external circuit

designed with the timing specifications so that any collision of the outputs from the pins subject

to high-impedance state may be prevented, direct connection can be also made.

2. Product quality may suffer if the absolute maximum ratings are exceeded for even a single

parameter, or even momentarily. In other words, the absolute maximum ratings are rated values

at which the product is on the verge of suffering physical damage, and therefore the product

must be used under conditions which ensure that the absolute maximum ratings are not

exceeded. The normal operation and reliability of the product can be only assured with the

specifications and the conditions indicated as the DC and AC characteristics.

µPD70320

OSCILLATOR CHARACTERISTICS

(T^A= –40 to +85°C, VDD = +5.0 V ±10%, VSS = 0 V, 0 V ≤ VTH ≤ VDD + 0.1 V)

µPD70320

MIN. MAX.

µPD70320-8

Resonator

Recommended Circuit

Parameter

Oscillation

Unit

MIN.

MAX.

Ceramic or Crystal

Resonator

MHz

frequency (fXX)

External Clock

X1 input

MHz

frequency (fX)

X1 rise/fall time

(tXR, tXF)

HCMOS

Inverter

X1 input high-/

low-level width

(tWXH, tWXL)

250

Open

HCMOS

Inverter

Cautions 1. Mount the oscillation circuit as close to pins X1 and X2 as possible.

2. Do not route other signal lines through the area within the dotted line.

µPD70320

RECOMMENDED OSCILLATOR CONSTANT

Ceramic resonator

Recommended Constants

Manufacturer

Part Number

KBR-10.0M^{Note 1}

C1 [pF]

C2 [pF]

Kyocera Corp.

Murata Mfg. Co., Ltd.

CSA7.37MT040^{Note 2}

CSA10.0MT^{Note 1}

100

CSA11.0MT^{Note 2}

CSA16.0MX040^{Note 1}

FCR10.0M2S^{Note 2}

FCR16.0M2S^{Note 2}

FCR16.0M2G^{Note 2}

TDK

Notes 1. The operating ambient temperature (TA) is –10°C to +70°C when this resonator is used.

2. The operating ambient temperature (T^A) is –20°C to +80°C when this resonator is used.

Crystal resonator

Recommended Constants

Manufacturer

Part Number

C1 [pF]

C2 [pF]

Kinseki Co., Ltd.

HC-49/U(KR-100)

HC-49/U(KR-160)

Remark For more details on the characteristics of the resonators, please contact the manufacturer.

µPD70320

CAPACITANCE (TA = 25°C, VDD = 0 V)

Parameter

Input Capacitance

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

fC = 1 MHz

Unmeasured pins returned to 0 V.

Output Capacitance

Input/output Capacitance

CIO

DC CHARACTERISTICS (TA = –40°C to +85°C, VDD = +5.0 V ±10%)

Parameter

Input Voltage Low

Input Voltage High

Symbol

Test Conditions

MIN.

TYP.

MAX.

0.8

Unit

VIL

VIH1

VIH2

VOL

VOH

Except RESET, P10/NMI, X1, X2

RESET, P10/NMI, X1, X2

IOL = 1.6 mA

2.2

VDD

0.8VDD

VDD

Output Voltage Low

Output Voltage High

Input Current

0.45

IOH = –0.4 mA

VDD – 1.0

EA, P10/NMI; 0 ≤ VI ≤ VDD

Except EA, P10/NMI; 0 ≤ VI ≤ VDD

0 ≤ VO ≤ VDD

±20

±10

1.0

100

120

µA

Input Leakage Current

Output Leakage Current

VTH Current

ILI

ILO

ITH

0 V ≤ VTH ≤ VDD

0.5

VDD Supply Current

IDD1

Operating mode

µPD70320

µPD70320-8

µPD70320

µPD70320-8

IDD2

IDD3

HALT mode

STOP mode

AC CHARACTERISTICS (TA = –40 to +85°C, VDD = +5.0 V ±10%)

µPD70320

µPD70320-8

Parameter

X1 Input Cycle Time

Symbol

Test Conditions

Unit

MIN.

MAX.

250

MIN.

MAX.

250

tCYX

X1 Input High-/Low-Level Width

X1 Input Rise/Fall Time

tWXH, tWXL

tXR, tXF

tCYK

CLKOUT Output Cycle Time

fX /2, T = tCYK

200

2000

125

2000

CLKOUT Output High-/Low-Level Width tWKH, tWKL

0.5T – 15

CLKOUT Output Rise/Fall Time

Input Rise/Fall Time

tKR, tKF

t^IR, tIF

Except RESET, NMI,

X1 and X2

tIRS, tIFS

tOR, tOF

RESET, NMI

Output Rise/Fall Time

Except CLKOUT

µPD70320

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

Address Delay Time from CLKOUT

Data Input Delay Time from Address

Data Delay Time from MREQ ↓

Data Delay Time from MSTB ↓

MSTB ↓ Delay Time from MREQ ↓

MREQ Low-Level Width

tDKA

tDADR

tDMRD

tDMSD

tDMRMS

tWMRL

tHMA

(n + 1.5)T – 90

(n + 1)T – 75

(n+ 0.5)T – 75

0.5T + 35

0.5T – 35

(n + 1)T – 30

0.5T – 30

(n + 1)T + 30

Address Hold Time (from MREQ ↑)

Data Input Hold Time (from MREQ ↑)

Control Signal Recovery Time

Data Output Delay Time from Address

Address Setup Time (to MREQ ↓)

Address Setup Time (to MSTB ↓)

MSTB Low-Level Width

tHMDR

tRVC

T – 25

tDADW

tDAMR

tDAMS

tWMSL

tSDM

0.5T + 50

0.5T – 30

T – 30

(n + 0.5)T – 30 (n + 0.5)T + 30

(n + 1)T – 50

0.5T – 30

(n + 1)T – 90

(n + 1)T – 30

0.5T – 30

Data Output Setup Time (to MSTB ↑)

Data Output Hold Time (from MSTB ↑)

Address Setup Time (to IOSTB ↓)

Data Delay Time from IOSTB ↓

IOSTB Low-Level Width

tHMDW

tDAIS

tDISD

tWISL

Address Hold Time (from IOSTB ↑)

Data Input Hold Time (from IOREQ ↑)

Data Output Setup Time (to IOSTB ↑)

Data Output Hold Time (from IOSTB ↑)

DMARQ Setup Time (to MREQ ↓)

DMARQ Hold Time (from DMAAK ↓)

DMAAK Output Low-Level Width

TC ↓ Delay Time from DMAAK ↓

TC Low-Level Width

tHISA

tHISDR

tSDIS

(n + 1)T – 50

0.5T – 30

tHISDW

tSDADQ

tHDADQ

tWDMRL

tDDATC

tWTCL

tWDMWL

tDARF

tWRFL

tHRFA

tWRSL1

Demand release mode

Read mode

(n + 1.5)T – 30

0.5T + 50

2T – 30

DMAAK Output Low-Level Width

Address Setup Time (to REFRQ ↓)

REFRQ Low-Level Width

Write mode

(n + 1)T – 30

0.5T – 30

(n + 1)T – 30

0.5T – 30

Address Hold Time (from REFRQ ↑)

RESET Low-Level Width

STOP mode release/

power-ON reset

tWRSL2

tSCRY0

tSCRY

System reset

n ≥ 2

µs

READY Setup Time

T – 100

(to MREQ ↓, IOSTB ↓)

n ≥ 3

(n – 1)T – 100

µPD70320

Parameter

READY Hold Time

Symbol

tHCRY0

tHCRY

Test Conditions

n = 2

MIN.

MAX.

Unit

(from MREQ ↓, IOSTB ↓)

n ≥ 3

(n – 1)T

(n – 2)T

tHCRY1

tSHQK

HLDRQ Setup Time (to CLKOUT ↑)

HLDAK ↓ Delay Time from CLKOUT ↑

HLDAK ↓ Delay Time from Bus Float

Bus Output Delay Time from HLDAK ↑

HLDAK ↑ Delay Time from HLDRQ ↓

Bus Output Delay Time from HLDRQ ↓

HLDRQ Low-Level Width

tDKHA

tCFHA

1T – 50

tDHAC

tDHQHA

tDHQC

tWHQL

tWHAL

3T + 160

3T + 30

1.5T

HLDAK Low-Level Width

INT, DMARQ Setup Time (to CLKOUT ↑) tSIQK

INT, DMARQ High-/Low-Level Width

POLL Setup Time (to CLKOUT ↑)

NMI High-/Low-Level Width

CTS Low-Level Width

tWIQH, tWIQL

tSPLK

µs

tWNIH, tWNIL

tWCTL

INT Setup Time (to CLKOUT ↑)

INTAK ↓ Delay Time from CLKOUT ↓

INT Hold Time (from INTAK ↓)

INTAK Low-Level Width

tSIRK

tDKIA

tHIAIQ

tWIAL

2T – 30

1T – 30

INTAK High-Level Width

tWIAH

Data Delay Time from INTAK ↓

Data Hold Time (from INTAK ↑)

SCK0 Cycle Time

tDIAD

2T – 130

0.5T

tHIAD

tCYTK

1000

450

SCK0 High-/Low-Level Width

TxD Delay Time from SCK0 ↓

TxD Hold Time (from SCK0 ↓)

CTS0 Cycle Time

tWSTH, tWSTL

tDTKD

210

tHTKD

1000

420

tCYRK

CTS0 High-/Low-Level Width

RxD Setup/Hold Time (to/from CTS0 ↑)

tWSRH, tWSRL

tSRDK, tHKRD

Remark n indicates the number of wait states. No wait is “n = 0”.

µPD70320

COMPARATOR CHARACTERISTICS (TA = –40°C to +85°C, VDD = +5.0 V ±10%)

Parameter

Comparator Accuracy

Threshold Voltage

Compare Time

Symbol

Test Conditions

MIN.

TYP.

MAX.

±100

Unit

VACOMP

VTH

VDD + 0.1

tCOMP

VIPT

tCYK

PT Input Voltage

VDD

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS

(T^A= –40 to +85°C)

Parameter

Symbol

Test Conditions

MIN.

2.5

MAX.

5.5

Unit

Data Hold Supply Voltage

VDD Rise/Fall Time

VDDDR

tRVD, tFVD

200

µs

DATA HOLDING TIMING

90%

10%

DDDR

FVD

RVD

AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2)

2.2 V

0.8 V

Test Points

0.8 V

tIR

AC TEST INPUT WAVEFORM (RESET, NMI, X1 and X2)

0.8 VDD

Test Points

0.8 V

0.8 V^DD

0.8 V

IFS

tIRS

AC TEST OUTPUT TEST POINTS

Output load condition: 100 pF

2.2 V

0.8 V

2.2 V

0.8 V

Test Points

µPD70320

CLOCK TIMING

tCYX

0.8 VDD

0.8 V

tWXH

tWXL

tXR

tXF

tCYK

2.2 V

0.8 V

CLKOUT

tWKH

tWKL

tKR

tKF

POLL INPUT TIMING

CLKOUT

tSPLK

POLL

CTS0 AND CTS1 INPUT TIMING

WCTL

CTS0 and CTS1

µPD70320

INTERRUPT INPUT/DMA INPUT TIMING

CLKOUT

WNIH

WNIL

NMI

SIQK

Note

WIQH

WIQL

Note INTP0 to INTP2, DMARQ0 to DMARQ1

RESET INPUT TIMING

When STOP mode is released/at power-on reset:

CLKOUT^Note

WRSL1

RESET

Note CLKOUT signal is output after CLKOUT output is set.

When system is reset:

CLKOUT^Note

WRSL2

RESET

Note CLKOUT output is set to input port by RESET input.

µPD70320

READY TIMING

When 2 wait states are inserted:

TAW

MREQ^{Note 1}

IOSTB^{Note 2}

HCRY0

SCRY0

READY

When (n – 2) extra wait states are inserted [n ≥ 3]:

TAW

TW × (n – 2)

MREQ^{Note 1}

IOSTB^{Note 2}

HCRY

HCRY1

SCRY

SCRY0

READY

Notes 1. In case of memory cycle

2. In case of I/O cycle

µPD70320

SERIAL OPERATION

When transmitting data in I/O interface mode

CYTK

WSTL

WSTH

SCK0

TxD

DTKD

HTKD

When receiving data in I/O interface mode

CYRK

WSRL

WSRH

CTS0

RxD

SRDK

HKRD

µPD70320

READ OPERATION

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

DADR

HMA

DMRD

HMDR

R/W

DAMR

WMRL

RVC

MREQ

DMRMS

DMSD

MSTB

DAMS

WMSL

IOSTB

REFRQ

DMAAK1 to

DMAAK0

µPD70320

WRITE OPERATION

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

DADW

HMA

SDM

HMDW

R/W

DAMR

WMRL

RVC

MREQ

DMRMS

MSTB

DAMS

WMSL

IOSTB

REFRQ

DMAAK1 to

DMAAK0

µPD70320

I/O READ TIMING

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

DADR

HISA

DISD

HISDR

R/W

MREQ

MSTB

DAIS

WISL

RVC

IOSTB

REFRQ

DMAAK1 to

DMAAK0

µPD70320

I/O WRITE TIMING

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

DADW

HISA

SDIS

HISDW

R/W

MREQ

MSTB

DAIS

WISL

RVC

IOSTB

REFRQ

DMAAK1 to

DMAAK0

µPD70320

DMA (I/O → MEMORY) TIMING

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

R/W

DAMR

WMRL

HMA

MREQ

DMRMS

RVC

MSTB

IOSTB

DAMS

WMSL

SDADQ

DMARQ1 to

DMARQ0

HDADQ

DMAAK1 to

DMAAK0

WDMRL

TC1 to TC0

DDATC

WTCL

µPD70320

DMA (MEMORY → I/O) TIMING

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

R/W

DAMR

WMRL

HMA

MREQ

RVC

MSTB

IOSTB

DAMS

WMSL

SDADQ

DMARQ1 to

DMARQ0

HDADQ

DMAAK1 to

DMAAK0

WDMWL

TC1 to TC0

DDATC

WTCL

µPD70320

REFRESH TIMING

CYK

CLKOUT

DKA

A19 to A0

D7 to D0

R/W

MREQ

MSTB

IOSTB

REFRQ

DARF

WRFL

HRFA

RVC

DMAAK1 to

DMAAK0

µPD70320

HOLD REQUEST/ACKNOWLEDGE TIMING

Normal mode

CLKOUT

SHQK

HLDRQ

DKHA

WHQL

Note

DHAC

CFHA

DHQHA

HLDAK

WHAL

Releasing HOLD mode at refreshing time

CLKOUT

SHQK

HLDRQ

WHQL

Note

DKHA

DHQC

HLDAK

Note A19 to A0, D7 to D0, MREQ, MSTB, IOSTB, R/W

EXTERNAL INTERRUPT REQUEST/ACKNOWLEDGE TIMING

CLKOUT

SIRK

INT

DKIA

HIAIQ

INTAK

WIAL

WIAH

DIAD

HIAD

D0 to D7

RVC

MREQ

IOSTB

µPD70320

4. CHARACTERISTIC CURVES

IDD1 vs fCLK

(TA = 25°C, VDD = 5 V)

140

120

100

System Clock Frequency fCLK (MHz)

DD2 vs fCLK

(TA = 25°C, VDD = 5 V)

System Clock Frequency fCLK (MHz)

µPD70320

DD1 vs VDD

(TA = 25°C)

120

100

CLK = 8 MHz

CLK = 5 MHz

CLK = 2 MHz

CLK = 1 MHz

CLK = 0.5 MHz

Supply Voltage VDD (V)

DD2 vs VDD

(TA = 25°C)

CLK = 8 MHz

CLK = 5 MHz

CLK = 2 MHz

fCLK = 0.5 MHz

CLK = 1 MHz

Supply Voltage V^DD(V)

µPD70320

OH vs VOH

(T = 25°C, VDD = 5 V)

–3

–2

–1

0.2

0.4

0.6

Output Voltage VDD – VOH (V)

IOL vs VOL

(T = 25°C, VDD = 5 V)

0.2

0.4

0.6

Output Voltage V^OL(V)

µPD70320

5. PACKAGE DRAWINGS

84 PIN PLASTIC QFJ ( 1150 mil)

P84L-50A3-2

INCHES

NOTE

ITEM

MILLIMETERS

Each lead centerline is located within 0.12

mm (0.005 inch) of its true position (T.P.) at

maximum material condition.

30.2 0.2

1.189 0.008

29.28

1.153

1.189 0.008

30.2 0.2

+0.007

–0.006

1.94 0.15

0.076

0.6

0.024

+0.009

4.4 0.2

0.173

–0.008

+0.009

–0.008

2.8 0.2

0.110

0.9 MIN.

3.4

0.035 MIN.

0.134

0.050 (T.P.)

1.27 (T.P.)

+0.004

0.40 0.10

0.016

–0.005

0.12

0.005

+0.009

–0.008

28.20 0.20

1.110

0.15

0.006

R 0.8

R 0.031

+0.10

–0.05

+0.004

–0.002

0.20

0.008

µPD70320

94 PIN PLASTIC QFP ( 20)

detail of lead end

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.15 mm (0.006 inch) of

its true position (T.P.) at maximum material condition.

+0.017

23.2±0.4

20.0±0.2

23.2±0.4

0.913

–0.016

+0.009

–0.008

0.787

0.913

+0.009

–0.008

+0.017

–0.016

1.6

0.8

1.6

0.8

0.063

0.031

0.063

0.031

+0.004

–0.005

0.35±0.10

0.014

0.006

0.15

0.8 (T.P.)

1.6±0.2

0.031 (T.P.)

0.063±0.008

+0.009

0.031

0.8±0.2

–0.008

+0.004

0.006

+0.10

0.15

–0.003

–0.05

0.10

0.004

3.7

0.146

0.1±0.1

5°±5°

0.004±0.004

5°±5°

4.0 MAX.

0.158 MAX.

S94GJ-80-5BG-3

µPD70320

6. RECOMMENDED SOLDERING CONDITIONS

The following conditions must be met when soldering this product.

For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”

(C10535E).

Please consult with our sales office when using other soldering process or under different soldering conditions.

Table 6-1. Surface Mount Type Soldering Conditions

(1) µPD70320L : 84-pin plastic QFJ (1150 × 1150 mils)

µPD70320L-8 : 84-pin plastic QFJ (1150 × 1150 mils)

Soldering Process

VPS

Soldering Conditions

Symbol

Package peak temperature: 215°C, Reflow time: 40 seconds or less,

Number of reflow processes: 1

VP15-162-1

Exposure limit: 2 days^Note(16 hours pre-baking is required at 125°C afterwards)

Partial heating

method

Pin temperature: 300°C or below,

—

Flow time: 3 seconds or less (per side of device)

Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25°C and relative

humidity at 65% or less.

(2) µPD70320GJ-5BG : 94-pin plastic QFP (20 × 20 mm)

µPD70320GJ-8-5BG : 94-pin plastic QFP (20 × 20 mm)

Soldering Process

Infrared ray reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Reflow time: 30 seconds or less,

Number of reflow processes: 3 or less

IR35-367-3

Exposure limit: 7 days^Note(36 hours pre-baking is required at 125°C afterwards)

VPS

Package peak temperature: 215°C, Reflow time: 40 seconds or less,

Number of reflow processes: 3 or less

Exposure limit: 7 days^Note(36 hours pre-baking is required at 125°C afterwards)

VP15-367-3

WS60-367-1

Wave soldering

Package peak temperature: 260°C, Reflow time: 10 seconds or less,

Number of reflow processes: 1

Pre-heating temperature: 120°C max. (package surface temperature)

Exposure limit: 7 days^Note(36 hours pre-baking is required at 125°C afterwards)

Partial heating

method

Pin temperature: 300°C or below,

—

Flow time: 3 seconds or less (per side of device)

Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25°C and relative

humidity at 65% or less.

Caution

Use of more than one soldering process should be avoided (except for partial heating method).

µPD70320

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V^DDor GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

µPD70320

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 250-3583

Tel: 01-504-2787

Fax: 01908-670-290

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics Italiana s.r.1.

Milano, Italy

NEC Electronics (Germany) GmbH

Scandinavia Office

Tel: 02-66 75 41

Fax: 02-719-5951

Taeby, Sweden

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil

Tel: 011-6465-6810

Fax: 08-63 80 388

Fax: 011-6465-6829

J97. 8

µPD70320

UPD70320L [NEC]

相关型号：

UPD70320L-8

UPD703210

UPD703210A

UPD703210GC-XXX-8BT

UPD703210GC-XXX-8BT-A

UPD703210GCA-XXX-8BT

UPD703210GK-XXX-9EU

UPD703210GKA-XXX-9EU

UPD703210Y

UPD703210YA

UPD703210YGC-XXX-8BT

UPD703210YGC-XXX-8BT-A