UPD70F3017AS1-YJC [NEC]
Microcontroller, 32-Bit, FLASH, 20MHz, MOS, PBGA121, 12 X 12 MM, PLASTIC, FBGA-121;
| 型号： | UPD70F3017AS1-YJC |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 32-Bit, FLASH, 20MHz, MOS, PBGA121, 12 X 12 MM, PLASTIC, FBGA-121 微控制器 |
| 文件： | 总48页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD70F3017A, 70F3017AY
V850/SA1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD70F3017A, 70F3017AY are products with on-chip flash memory. Because the devices can be
programmed by the user on-board, they are ideal for the evaluation stages of system development, small-scale
production of a variety of products, and rapid development of new products.
The V850/SA1 provides a high-level cost performance ideal for applications ranging from low-power camcorders
and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone
systems (PHS).
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SA1 User's Manual Hardware:
V850 Family User's Manual Architecture:
U12768E
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time:
59 ns (@ 17 MHz operation with main system
clock (fXX))
{ Interrupts and exceptions
External: 8, internal: 23, exceptions: 1
{ I/O lines Total: 85
{ Timer/counters
50 ns (@ 20 MHz operation with main system
clock (fXX))
16-bit timer: 2 channels
8-bit timer:
4 channels
30.5 µs (@ 32.768 kHz operation with subsystem
clock (fXT))
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set:
{ Serial interface (SIO)
Asynchronous serial interface (UART)
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
Clocked serial interface (CSI)
I2C bus interface (µPD70F3017AY)
{ A/D converter: 12 channels
{ Memory space:
{ DMA controller: 3 channels
16 MB linear address space
Memory block division function: 2 MB per block
{ External bus interface: 16-bit data bus
Address bus: Separate output enabled
{ Internal memory
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels
{ Power-saving functions: HALT/IDLE/STOP modes
{ Packages: 100-pin plastic LQFP (14 × 14 mm)
121-pin plastic FBGA (12 × 12 mm)
Flash memory: 256 KB
RAM: 8 KB
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14527EJ1V0DS00 (1st edition)
Date Published February 2000 N CP(K)
Printed in Japan
©
2000
µPD70F3017A, 70F3017AY
APPLICATIONS
{ Low-power portable devices
Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD70F3017AGC-8EU
µPD70F3017AS1-YJC
µPD70F3017AYGC-8EU
µPD70F3017AYS1-YJC
100-pin plastic LQFP (fine-pitch) (14 × 14 mm)
121-pin plastic FBGA (12 × 12 mm)
100-pin plastic LQFP (fine-pitch) (14 × 14 mm)
121-pin plastic FBGA (12 × 12 mm)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
2
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
PIN CONFIGURATION
100-pin plastic LQFP (fine-pitch) (14 × 14 mm)
µPD70F3017AGC-8EU
µPD70F3017AYGC-8EU
P21/SO2
P22/SCK2
P23/RXD1
P24/TXD1
P25/ASCK1
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
AVREF
AVSS
AVDD
V
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
V
SS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P31/TI01
P32/TI10
P33/TI11
P34/TO0/A13
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
Note 1
PP
V
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Notes 1. Connect the VPP pin to VSS in the normal operating mode.
2. Applies to the µPD70F3017AY only.
3
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
121-pin plastic FBGA (12 × 12 mm)
µPD70F3017AS1-YJC
µPD70F3017AYS1-YJC
Top View
Bottom View
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
N
M
L
K
J
H
G F E D C B A
Pin
Pin
Pin
Pin
Pin
Pin
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Pin Name
Number
Number
Number
Number
G11
G12
G13
H1
Number
K13
L1
Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
P20
P15
VSS
B8
P83
P80
P75
AVSS
AVSS
P71
P22
P23
VSS
D2
VDD
P60
P56
P57
P34
P37
P35
P55
P53
P54
V
BVDD
P104
P105
RESET
VDD
M7
M8
VSS
VSS
B9
D3
VSS
B10
B11
B12
B13
C1
D11
D12
D13
E1
AVDD
AVDD
AVDD
P25
VDD
L2
M9
P92
P95
P41
P45
P44
P107
P110
P112
V
P13
P11
P06
P03
P00
P81
P76
P73
P72
AVSS
P21
P14
VSS
L3
M10
M11
M12
M13
N1
H2
L4
H3
L5
VSS
E2
H11
H12
H13
J1
L6
X2
C2
E3
P30
AVDD
P64
P65
P26
P27
P33
P63
P61
P62
P31
P32
P36
L7
P90
C3
E11
E12
E13
F1
L8
P120
P93
N2
PPNote
C4
P24
P07
P04
P01
P82
P77
P74
AVSS
P70
AVREF
VDD
L9
N3
V
PPNote
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
P96
N4
DD
C5
J2
C6
J3
P100
P52
P50
P51
P101
P102
P103
P46
P47
BVSS
BVSS
BVSS
P106
P111
P113
VDD
N5
XT1
VSS
C7
F2
J11
J12
J13
K1
N6
C8
F3
N7
VSS
C9
F11
F12
F13
G1
N8
CLKOUT
P91
P94
P40
P42
P43
C10
C11
C12
C13
D1
N9
P12
P10
P05
P02
K2
N10
N11
N12
N13
K3
G2
K11
K12
XT2
X1
G3
Note Connect the VPP pin to VSS in the normal operating mode.
Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic
LQFP.
2. Connect the D4 pin directly to VSS.
4
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
PIN IDENTIFICATION
A1 to A21:
AD0 to AD15:
ADTRG:
Address Bus
P100 to P107:
Port 10
Address/Data Bus
AD Trigger Input
Analog Input
P110 to P114:
P120:
Port 11
Port 12
ANI0 to ANI11:
ASCK0, ASCK1:
ASTB:
RD:
Read
Asynchronous Serial Clock
Address Strobe
Analog VDD
RESET:
Reset
RTP0 to RTP7:
RTPTRG:
R/W:
Real-Time Port
RTP Trigger
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Input
AVDD:
AVREF:
Analog Reference Voltage
Analog VSS
AVSS:
RXD0, RXD1:
SCK0 to SCK2:
BVDD:
Power Supply for Bus Interface
Ground for Bus Interface
Clock Output
BVSS:
SCLNote
SDANote
:
CLKOUT:
DSTB:
:
Data Strobe
SI0 to SI2:
SO0 to SO2:
TI00, TI01, TI10, :
TI11, TI2 to TI5
TO0 to TO5:
TXD0,TXD1:
UBEN:
HLDAK:
Hold Acknowledge
Hold Request
Interrupt Request From Peripherals
Lower Byte Enable
Non-maskable Interrupt Request
Port 0
HLDRQ:
INTP0 to INTP6:
LBEN:
Timer Output
NMI:
Transmit Data
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P83:
P90 to P96:
Upper Byte Enable
Power Supply
Port 1
VDD:
Port 2
VPP:
Programming Power Supply
Ground
Port 3
VSS:
Port 4
WAIT:
Wait
Port 5
WRH:
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main System Clock
Crystal for Subsystem Clock
Port 6
WRL:
Port 7
X1, X2:
Port 8
XT1, XT2:
Port 9
Note Applies to the µPD70F3017AY only.
5
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
INTERNAL BLOCK DIAGRAM
Flash
memory
CPU
NMI
INTC
INTP0 to INTP6
HLDRQ (P96)
HLDAK (P95)
Instruction
queue
PC
ASTB (P94)
256 KB
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT
TI00, TI01,
32-bit
Multiplier
16 x 16 32
Timer/counters
TI10, TI11
barrel shifter
TO0, TO1
16-bit timer:
System
registers
TM0, TM1
8-bit timer:
TM2 to TM5
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
BCU
RAM
8 KB
ALU
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
General-purpose
registers
32 bits x 32
SIO
A16 to A21 (P60 to P65)
SO0
SI0/SDANote
AD0 to AD15
(P40 to P47, P50 to P57)
CSI0/I2CNote
SCK0/SCLNote
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
CSI1/UART0
CSI2
CLKOUT
X1
Port
SO2
SI2
A/D
converter
RTP
SCK2
X2
CG
XT1 (P114)
XT2
TXD1
RXD1
UART1
ASCK1
RESET
DMAC: 3 ch
Watch timer
V
DD
SS
V
BVDD
BVSS
Watchdog
timer
VPP
Note Applies to the µPD70F3017AY only.
6
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
CONTENTS
1. PIN FUNCTIONS.................................................................................................................................. 8
1.1 Port Pins..................................................................................................................................................... 8
1.2 Non-Port Pins........................................................................................................................................... 11
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14
2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3. PACKAGE DRAWINGS..................................................................................................................... 43
4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 45
Preliminary Data Sheet U14527EJ1V0DS00
7
µPD70F3017A, 70F3017AY
1. PIN FUNCTIONS
1.1 Port Pins
(1/3)
Pin Name
P00
I/O
I/O
PULL
Yes
Function
Alternate Function
Port 0
NMI
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
INTP0
Input/output can be specified in 1-bit units.
INTP1
INTP2
INTP3
INTP4/ADTRG
INTP5/RTPTRG
INTP6
I/O
Yes
Port 1
SI0/SDANote
6-bit I/O port
SO0
Input/output can be specified in 1-bit units.
SCK0/SCLNote
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2
I/O
Yes
Port 2
8-bit I/O port
SO2
Input/output can be specified in 1-bit units.
SCK2
RXD1
TXD1
ASCK1
TI2/TO2
TI3/TO3
TI00
I/O
Yes
Port 3
8-bit I/O port
TI01
Input/output can be specified in 1-bit units.
TI10
TI11
TO0/A13
TO1/A14
TI4/TO4/A15
TI5/TO5
Note Applies to the µPD70F3017AY only.
Remark PULL: On-chip pull-up resistor
8
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(2/3)
Pin Name
P40
I/O
I/O
PULL
No
Function
Alternate Function
Port 4
AD0
AD1
8-bit I/O port
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P70
P71
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
Input/output can be specified in 1-bit units.
AD2
AD3
AD4
AD5
AD6
AD7
I/O
No
Port 5
AD8
8-bit I/O port
AD9
Input/output can be specified in 1-bit units.
AD10
AD11
AD12
AD13
AD14
AD15
A16
I/O
No
Port 6
6-bit I/O port
A17
Input/output can be specified in 1-bit units.
A18
A19
A20
A21
Input
No
Port 7
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
8-bit input port
Input
No
Port 8
4-bit input port
Remark PULL: On-chip pull-up resistor
9
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(3/3)
Pin Name
P90
I/O
I/O
PULL
No
Function
Alternate Function
Port 9
LBEN/WRL
UBEN
7-bit I/O port
P91
Input/output can be specified in 1-bit units.
P92
R/W/WRH
DSTB/RD
ASTB
P93
P94
P95
HLDAK
HLDRQ
RTP0/A5
RTP1/A6
RTP2/A7
RTP3/A8
RTP4/A9
RTP5/A10
RTP6/A11
RTP7/A12
A1
P96
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P114
P120
I/O
Yes
Port 10
8-bit I/O port
Input/output can be specified in 1-bit units.
I/O
Yes
Port 11
5-bit I/O port
A2
Input/output can be specified in 1-bit units.
P114 is fixed as input only.
A3
A4
Input
I/O
No
No
XT1
Port 12
WAIT
1-bit I/O port
Remark PULL: On-chip pull-up resistor
10
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
1.2 Non-Port Pins
(1/3)
Pin Name
A1 to A4
I/O
PULL
Yes
Function
Low-order address bus used for external memory expansion
Alternate Function
Output
P110 to P113
A5 to A12
P100/RTP0 to
P107/RTP7
A13
P34/TO0
A14
P35/TI1
A15
P36/TI4/TO4
P60 to P65
A16 to A21
AD0 to AD7
AD8 to AD15
ADTRG
ANI0 to ANI7
ANI8 to ANI11
ASCK0
ASCK1
ASTB
Output
I/O
No
No
High-order address bus used for external memory expansion
16-bit multiplexed address/data bus used for external memory P40 to P47
expansion
P50 to P57
Input
Input
Input
Input
Yes
No
A/D converter external trigger input
Analog input to A/D converter
P05/INTP4
P70 to P77
P80 to P83
P15/SCK1
P25
No
Yes
Serial clock input for UART0 and UART1
Output
−
No
−
External address strobe signal output
Positive power supply for A/D converter
Reference voltage input for A/D converter
Ground potential for A/D converter
Positive power supply for bus interface
Ground potential for bus interface
P94
AVDD
−
−
−
−
−
−
AVREF
Input
−
−
AVSS
−
BVDD
−
−
BVSS
−
−
CLKOUT
DSTB
Output
Output
Output
Input
Input
−
Internal system clock output
No
No
No
Yes
External data strobe signal output
P93/RD
P95
HLDAK
HLDRQ
INTP0 to INTP3
INTP4
Bus hold acknowledge output
Bus hold request input
P96
External interrupt request input (analog noise elimination)
External interrupt request input (digital noise elimination)
P01 to P04
P05/ADTRG
P06/RTPTRG
P07
INTP5
INTP6
LBEN
Output
Input
No
Yes
No
−
External data bus’s low-order byte enable signal output
Non-maskable interrupt request input
Read strobe signal output
P90/WRL
P00
NMI
RD
Output
Input
P93/DSTB
−
RESET
RTP0 to RTP7
System reset input
Output
Yes
Real-time output port
P100/A5 to P107/A12
Remark PULL: On-chip pull-up resistor
11
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(2/3)
Pin Name
RTPTRG
I/O
PULL
Yes
No
Function
Alternate Function
Input
Output
Input
RTP external trigger input
External read/write status output
P06/INTP5
P92/WRH
R/W
RXD0
RXD1
SCK0
SCK1
SCK2
SCL
SDA
SI0
Yes
Serial receive data input for UART0 and UART1
P13/SI1
P23
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI2
P12
P15/ASCK0
P22
I2C serial clock I/O (µPD70F3017AY only)
P12/SCK0
P10/SI0
P10
I2C serial transmit/receive data I/O (µPD70F3017AY only)
Input
Output
Input
Yes
Yes
Yes
Serial receive data input (3-wire type) for CSI0 to CSI2
SI1
P13/RXD0
P20
SI2
SO0
SO1
SO2
TI00
Serial transmit data output (3-wire type) for CSI0 to CSI2
P11
P14/TXD0
P21
External capture trigger input and external count clock input
for TM0
P30
TI01
TI10
External capture trigger input for TM0
P31
P32
External capture trigger input and external count clock input
for TM1
TI11
TI2
External capture trigger input for TM1
External count clock input for TM2
External count clock input for TM3
External count clock input for TM4
External count clock input for TM5
Pulse signal output for TM0, TM1
Pulse signal output for TM2
P33
P26/TO2
P27/TO3
P36/TO4/A15
P37/TO5
P34/A13, P35/A14
P26/TI2
P27/TI3
P36/TI4/A15
P37/TI5
P14/SO1
P24
TI3
TI4
TI5
TO0, TO1
TO2
TO3
TO4
TO5
TXD0
TXD1
UBEN
VDD
Output
Yes
Pulse signal output for TM3
Pulse signal output for TM4
Pulse signal output for TM5
Output
Yes
Serial transmit data output for UART0 and UART1
Output
No
−
High-order byte enable signal output for external data bus
Positive power supply pin
P91
−
−
−
VSS
−
GND potential
−
Remark PULL: On-chip pull-up resistor
12
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(3/3)
Pin Name
WAIT
I/O
PULL
No
Function
Alternate Function
Input
Control signal input for inserting wait in bus cycle
P120
WRH
Output
No
High-order byte write strobe signal output for external data
bus
P92/R/W
WRL
X1
Low-order byte write strobe signal output for external data bus P90/LBEN
Resonator connection for main clock
Input
No
No
−
−
−
X2
−
Input
−
XT1
XT2
VPP
Resonator connection for subsystem clock
P114
−
−
−
Pin to which high voltage is applied during program write/verify
Remark PULL: On-chip pull-up resistor
13
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For the
input/output schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/2)
Pin
P00
Alternate Function
I/O Circuit Type
8-A
Recommended Connection of Unused Pins
Connect to VSS
NMI
Input:
Output: Leave open
P01 to
P04
INTP0 to INTP3
P05
INTP4/ADTRG
INTP5/RTPTRG
INTP6
P06
P07
P10
SI0/SDANote
10-A
26
Input:
Connect to VDD or VSS
Output: Leave open
P11
SO0
P12
SCK0/SCLNote
SI1/RXD0
SO1/TXD0
SCK1/ASCK0
SI2
10-A
8-A
26
P13
P14
P15
10-A
8-A
26
P20
P21
SO2
P22
SCK2
10-A
8-A
5-A
8-A
P23
RXD1
P24
TXD1
P25
ASCK1
P26, P27
P30, P31
P32, P33
P34, P35
P36
TI2/TO2, TI3/TO3
TI00, TI01
TI10, TI11
TO0/A13, TO1/A14
TI4/TO4/A15
TI5/TO5
5-A
8-A
P37
P40 to
P47
AD0 to AD7
5
Input:
Connect to BVDD or BVSS
Output: Leave open
P50 to
P57
AD8 to AD15
A16 to A21
P60 to
P65
P70 to
P77
ANI0 to ANI7
ANI8 to ANI11
9
Connect to AVSS or AVDD
P80 to
P83
Note Applies to the µPD70F3017AY only.
14
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin
P90
Alternate Function
LBEN/WRL
I/O Circuit Type
5
Recommended Connection of Unused Pins
Connect to BVDD or BVSS
Input:
Output: Leave open
P91
P92
P93
P94
P95
P96
UBEN
R/W/WRH
DSTB/RD
ASTB
HLDAK
HLDRQ
P100 to
P107
RTP0/A5 to RTP7/A12
26
Input:
Connect to VDD or VSS
Output: Leave open
P110 to
P113
A1 to A4
5-A
P114
P120
XT1
16
5
WAIT
Input:
Connect to BVDD or BVSS
Output: Leave open
AVREF
CLKOUT
RESET
X2
−
−
−
−
−
–
−
4
Connect to AVSS
Leave open
2
−
−
Leave open (when external clock is input to X1 pin)
XT2
16
–
Leave open
VPP
Connect to VSS
15
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup
enable
P-ch
V
DD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 8-A
Type 4
VDD
VDD
Pullup
enable
P-ch
Data
P-ch
VDD
OUT
Data
P-ch
N-ch
Output
disable
N-ch
IN/OUT
Output
disable
Push-pull output that can be set for high-impedance output
(both P-ch and N-ch off)
Type 5
Type 9
VDD
Data
P-ch
N-ch
P-ch
Comparator
+
–
IN
IN/OUT
Output
disable
N-ch
VREF (threshold voltage)
Input enable
Input
enable
16
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 10-A
Type 26
VDD
V
DD
Pullup
enable
Pullup
enable
P-ch
P-ch
VDD
VDD
Data
Data
P-ch
P-ch
IN/OUT
IN/OUT
Open drain
Open drain
N-ch
Output disable
N-ch
Output
disable
Type 16
Feedback cut-off
P-ch
XT1
XT2
17
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0V)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
Unit
V
–0.5 to +4.6
–0.5 to +4.6
–0.5 to +4.6
–0.5 to +0.5
–0.5 to +0.5
AVDD
BVDD
AVSS
BVSS
VI1
V
V
V
V
Input voltage
Note 1
Note 2
VPP
–0.5 to V
DD + 0.5Note 4
V
VI2
–0.5 to BV
DD + 0.5Note 4
V
VI3
–0.5 to +8.5
DD + 1.0Note 4
V
Clock input voltage
VK
X1, XT1, VDD = 2.7 to 3.6 V
–0.5 to V
V
Analog input voltage
Analog reference input voltage
Output current, low
VIAN
AVREF
IOL
Note 3 (AVDD)
–0.5 to AVDD + 0.5Note 4
V
AVREF
–0.5 to AV
DD + 0.5Note 4
V
Per pin
4.0
25
25
mA
mA
mA
Total for P00 to P07, P10 to P15, P20 to 25
Total for P26, P27, P30 to 37, P100 to
P107, P110 to P113
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Total for P50 to P57, P60 to P65
Per pin
25
mA
mA
mA
mA
Output current, high
IOH
–4.0
–25
–25
Total for P00 to P07, P10 to P15, P20 to 25
Total for P26, P27, P30 to 37, P100 to
P107, P110 to P113
Total for P40 to P47, P90 to P96, P120,
CLKOUT
–25
mA
Total for P50 to P57, P60 to P65
Note 1, V
–25
mA
V
Output voltage
VO1
VO2
TA
DD = 2.7 to 3.6 V
–0.5 to VDD + 0.5Note 4
–0.5 to BVDD + 0.5Note 4
–40 to +85
Note 2, BV
DD = 2.7 to 3.6 V
V
Operating ambient temperature
Normal operating mode
Flash memory programming mode
°C
°C
°C
10 to 40
Storage temperature
Tstg
–40 to +125
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins.
2. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins.
3. Ports 7, 8, and their alternate-function pins.
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-connector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
18
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Internal Operation Clock Frequency (φ)
2 MHz ≤ fXX ≤ 17 MHz
2 MHz ≤ fXX ≤ 20 MHz
fXT = 32.768 kHz
Supply Voltage (VDD)
2.7 to 3.6 V
Operating Ambient Temperature (TA)
–40 to +85°C
3.0 to 3.6 V
–40 to +85°C
2.7 to 3.6 V
–40 to +85°C
19
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Recommended Oscillator
(1) Main system clock oscillator (TA = –40 to +85°C)
(a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter
Symbol
fXX
Conditions
MIN.
2
TYP.
MAX.
20
Unit
MHz
s
Oscillation frequency
Oscillation stabilization time
Upon reset release
Upon STOP mode release
219/fXX
Note
s
Note The TYP value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Caution Ensure that the duty of oscillation waveform is between 45% and 55%.
Remarks 1. Connect the oscillator as close as possible to the X1 and X2 pins.
2. Do not route the wiring near broken lines.
3. Sufficiently evaluate the matching between the oscillator and resonator.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Connect the high-speed CMOS inverter as close as possible to the X1 pin.
2. Sufficiently evaluate the matching between the µPD70F3017A, 70F3017AY and the high-
speed CMOS inverter.
20
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(2) Subsystem clock oscillator (TA = –40 to +85°C)
(a) Connection of crystal resonator
XT1
XT2
Parameter
Symbol
fXT
Conditions
MIN.
32
TYP.
32.768
10
MAX.
35
Unit
kHz
s
Oscillation frequency
Oscillation stabilization time
Remarks 1. Connect the oscillator as close as possible to the XT1 and XT2 pins.
2. Do not route the wiring near broken lines.
3. Sufficiently evaluate the matching between the oscillator and resonator.
(b) External clock input
XT1
XT2
High-speed CMOS inverter
Cautions 1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin.
2. Sufficiently evaluate the matching between the µPD70F3017A, 70F3017AY and the high-
speed CMOS inverter.
21
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
DC Characteristics
(1) Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter
Symbol
VIH1
Conditions
Pins other than below
MIN.
0.7VDD
0.7AVDD
0.75VDD
0.8VDD
VSS
TYP.
MAX.
VDD
Unit
V
Input voltage, high
VIH2
Note 1
AVDD
V
VIH3
Note 2
VDD
V
VIH4
X1, XT1 (P114), XT2
Pins other than below
Note 1
VDD
V
Input voltage, low
VIL1
0.3VDD
0.3AVDD
0.2VDD
0.2VDD
V
VIL2
AVSS
V
VIL3
Note 2
VSS
V
VIL4
X1, XT1 (P114), XT2
VSS
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
Note 3
Note 4
Note 3
IOH = –3 mA
0.8VDD
0.8VDD
V
IOH = –1 mA
IOL = 1.6 mA
IOL = 1.6 mA
V
0.4
0.4
V
Note 4
V
(Except pins P10
and P12)
VOL3
ILIH
P10, P12
IOL = 3 mA
0.4
5
V
Input leakage current, high
Input leakage current, low
VI = VDD = AVDD =
BVDD
µA
µA
µA
µA
µA
µA
mA
X1, XT1, XT2
X1, XT1, XT2
20
–5
–20
5
ILIL
VI = 0 V
Output leakage current, high
Output leakage current, low
Supply currentNote 5
ILOH
ILOL
IDD1
VO = VDD = AVDD = BVDD
VO = 0 V
–5
60
Normal operation
fXX = 17 MHz
30
10
All peripheral
functions operating
IDD2
HALT mode
fXX = 17 MHz
25
mA
All peripheral
functions operating
IDD3
IDLE mode
fXX = 17 MHz Watch
timer operating
4
8
mA
IDD4
STOP mode (subsystem oscillator, watch
timer operating)
10
100
µA
STOP mode (subsystem oscillator
stopped (XT1 = VSS))
2
100
µA
22
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(1) Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter
Supply currentNote 5
Symbol
IDD5
Conditions
MIN.
TYP.
250
MAX.
600
Unit
Subsystem clock normal operation mode
fXT = 32.768 kHz (main system clock
stopped)
µA
130
30
360
100
µA
kΩ
IDD6
Subsystem clock IDLE mode
fXT = 32.768 kHz (main system clock
stopped, watch timer operating)
Pull-up resistance
RL
VIN = 0V
10
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-
function pins.
5. The TYP value of VDD is 3.3 V. The current consumed by the output buffer is not included.
23
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(2) Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (1/2)
Parameter
Symbol
VIH1
Conditions
Pins other than below
MIN.
0.7VDD
0.7AVDD
0.75VDD
0.8VDD
VSS
TYP.
MAX.
VDD
Unit
V
Input voltage, high
VIH2
Note 1
AVDD
V
VIH3
Note 2
VDD
V
VIH4
X1, XT1 (P114), XT2
Pins other than below
Note 1
VDD
V
Input voltage, low
VIL1
0.3VDD
0.3AVDD
0.2VDD
0.2VDD
V
VIL2
AVSS
V
VIL3
Note 2
VSS
V
VIL4
X1, X2, XT1 (P114), XT2
VSS
V
Output voltage, high
Output voltage, low
VOH1
VOH2
VOL1
VOL2
Note 3
Note 4
Note 3
IOH = –3 mA
0.8VDD
0.8VDD
V
IOH = –1 mA
IOL = 1.6 mA
IOL = 1.6 mA
V
0.4
0.4
V
Note 4
V
(Except pins P10
and P12)
VOL3
ILIH
P10, P12
IOL = 3 mA
0.4
5
V
Input leakage current, high
Input leakage current, low
VI = VDD = AVDD =
BVDD
µA
µA
µA
µA
µA
µA
mA
X1, XT1, XT2
X1, XT1, XT2
20
–5
–20
5
ILIL
VI = 0 V
Output leakage current, high
Output leakage current, low
Supply currentNote 5
ILOH
ILOL
IDD1
VO = VDD
VO = 0 V
–5
64
Normal operation
fXX = 20 MHz All
peripheral functions
operating
32
11
IDD2
HALT mode
IDLE mode
fXX = 20 MHz All
peripheral functions
operating
26
9
mA
mA
IDD3
fXX = 20 MHz Watch
timer operating
4.5
IDD4
STOP mode (watch timer operating)
10
2
100
100
µA
µA
STOP mode (subsystem oscillator
stopped (XT1 = VSS))
24
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
(2) Operating Conditions (TA = –40 to +85°C, VDD = AVDD = BVDD = 3.0 to 3.6 V, VSS = AVSS = BVSS = 0 V) (2/2)
Parameter
Symbol
IDD5
Conditions
MIN.
TYP.
250
MAX.
600
Unit
Supply currentNote 5
Subsystem clock normal operation mode
fXT = 32.768 kHz (main system clock
stopped)
µA
IDD6
Subsystem clock IDLE mode
130
30
360
100
µA
kΩ
fXT = 32.768 kHz (main system clock
stopped, watch timer operating)
Pull-up resistance
RL
VIN = 0 V
10
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-
function pins.
5. The TYP value of VDD is 3.3 V. The current consumed by the output buffer is not included.
25
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Conditions
STOP mode
MIN.
1.8
TYP.
2
MAX.
3.6
Unit
V
VDDDR [V]
100
µA
Supply voltage rise time
Supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
µs
Supply voltage hold time
(from STOP mode setting)
ms
STOP release signal input time
tDREL
VIHDR
VILDR
0
VIHn
0
ms
V
Data retention high-level input voltage
Data retention low-level input voltage
All input ports
All input ports
VDDDR
VILn
V
Remarks 1. TYP. values are reference values for when TA = 25°C.
2. n = 1 to 4
Setting STOP mode
t
FVD
t
RVD
V
DD
V
DDDR
t
HVD
t
DREL
RESET
(input)
V
V
IHDR
NMI, INTP0 to INTP3
(input)
IHDR
NMI, INTP0 to INTP3 (input)
(when STOP mode is released
at rising edge)
V
ILDR
Caution Shifting to STOP mode and restoring from STOP mode must be performed at VDD = 2.7 V min.
(fXX = 17 MHz) and VDD = 3.0 V min. (fXX = 20 MHz), respectively.
26
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
AC Characteristics
AC Test Input Waveforms
(1) RESET, P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, and their alternate-function pins
V
DD
0.7VDD
0.3VDD
0.7VDD
0.3VDD
Point of measurement
0 V
(2) P70 to P77, P80 to P83, and their alternate-function pins
AVDD
0.7AVDD
0.7AVDD
0.3AVDD
Point of measurement
0.3AVDD
0 V
(3) P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, and their alternate-
function pins
V
DD
0.75VDD
0.2VDD
0.75VDD
0.2VDD
Point of measurement
0 V
(4) X1, XT1 (P114), XT2
V
DD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of measurement
0 V
AC Test Output Measurement Points
0.8VDD
0.8VDD
0.4 V
Point of measurement
0.4 V
27
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Load conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance
of the device to 50 pF or less by inserting a buffer or by some other means.
28
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Clock Timing
(1) Operating Conditions (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
Symbol
tCYX
Conditions
MIN.
58.8
28.5
26.4
12.8
26.4
12.8
MAX.
Unit
ns
µs
ns
µs
ns
µs
ns
X1 input cycle
<1>
<2>
<3>
XT1 input cycle
X1 input high-level width
XT1 input high-level width
X1 input low-level width
XT1 input low-level width
X1 input rise time
tWXH
tWXL
tXR
<4>
<5>
0.5 (tCYX –
tWXH – tWXL)
X1 input fall time
tXF
0.5 (tCYX –
tWXH – tWXL)
ns
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
tCYK
tWKH
tWKL
tKR
<6>
<7>
<8>
<9>
<10>
58.8 ns
31.2 µs
0.4tCYK – 10
0.4tCYK – 10
ns
ns
ns
ns
10
10
CLKOUT fall time
tKF
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
(2) Operating Conditions (TA = –40 to +85°C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
Symbol
tCYX
Condition
MIN.
50.0
28.5
22.5
12.8
22.5
12.8
MAX.
Unit
ns
µs
ns
µs
ns
µs
ns
X1 input cycle
<1>
<2>
<3>
XT1 input cycle
X1 input high-level width
XT1 input high-level width
X1 input low-level width
XT1 input low-level width
X1 input rise time
tWXH
tWXL
tXR
<4>
<5>
0.5 (tCYX –
tWXH – tWXL)
X1 input fall time
tXF
0.5 (t
CYX –
ns
tWXH – tWXL)
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
tCYK
tWKH
tWKL
tKR
<6>
<7>
<8>
<9>
<10>
50.0 ns
31.2 µs
0.4tCYK – 10
0.4tCYK – 10
ns
ns
ns
ns
10
10
CLKOUT fall time
tKF
Remarks 1. T = tCYK
2. Ensure that the duty is between 45% and 55%.
29
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Clock Timing
<1>
<2>
<3>
X1, XT1 (input)
<4>
<5>
<6>
<7>
<8>
CLKOUT (output)
<9>
<10>
(1) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
20
Unit
ns
Output rise time
Output fall time
tOR
tOF
<11>
<12>
20
ns
(2) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9
(TA = –40 to +85°C, VDD = BVDD = 3.0 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
20
Unit
ns
Output rise time
Output fall time
tOR
<11>
<12>
tOF
20
ns
0.8VDD
0.8VDD
Output signal
0.4 V
0.4 V
<12>
<11>
30
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float from DSTB↓
tSAST
tHSTA
tFDA
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<36>
<37>
<38>
<39>
<40>
0.5T – 15
0.5T – 15
2
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ to ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
tSAID
(2 + n)T – 25
(1 + n)T – 25
tSDID
tDSTD
0.5T – 15
0
tHDID
tDDA
(1 + i)T – 15
0.5T – 15
(1.5 + i)T – 15
(1 + n)T – 15
T – 15
tDDST1
tDDST2
tWDL
ASTB high-level width
tWSTH
tDDOD
tSODD
tHDOD
tSAWT1
tSAWT2
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
tHSTWT1
tHSTWT2
tWHQH
tWHAL
tDHAC
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
15
(1 + n)T – 20
T – 15
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
1.5T – 25
(1.5 + n)T – 25
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
(0.5 + n)T
(1.5 + n)T
T – 25
(1 + n)T – 25
nT
(1 + n)T
T + 10
T – 15
0
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
tDHQHA1
tDHQHA2
(2n + 7.5)T + 25
1.5T + 25
0.5T
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
31
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Condition
MIN.
0
MAX.
19
Unit
ns
Delay time from CLKOUT↑ to address
tDKA
<41>
<42>
Delay time from CLKOUT↑ to address
t
FKA
–12
7
ns
float
Delay time from CLKOUT↓ to ASTB
Delay time from CLKOUT↑ to DSTB
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Data output delay time from CLKOUT↑
WAIT setup time (to CLKOUT↓)
tDKST
tDKD
<43>
<44>
<45>
<46>
<47>
<48>
<49>
<50>
<51>
<52>
<53>
–12
–5
15
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
tSIDK
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKF
19
15
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
Delay time from CLKOUT↑ to bus float
Delay time from CLKOUT↑ to HLDAK
15
5
19
19
tDKHA
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
32
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output),
A1 to A15 (output), Note
<16>
<45> <46>
Data
<42>
Hi-Z
AD0 to AD15 (I/O)
ASTB (output)
Address
<43>
<43>
<14>
<13>
<19>
<24>
<44>
<18>
<21>
<15>
<17>
<20>
<22>
<44>
DSTB (output),
RD (output)
<23>
<48> <49>
<32> <48> <49>
<34>
<33>
<35>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
33
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output)
<41>
A16 to A21 (output),
A1 to A15 (output), Note
<47>
AD0 to AD15 (I/O)
ASTB (output)
Address
<43>
Data
<43>
<13>
<14>
<24>
<21>
<44>
<18>
<44>
<27>
<25>
<26>
DSTB (output),
WRL (output),
WRH (output)
<23>
<48> <49>
<32> <48> <49>
<34>
<33>
<35>
WAIT (input)
<28>
<30>
<29>
<31>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
34
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Bus Hold
TH
TH
TH
TI
CLKOUT (output)
HLDRQ (input)
<50>
<50> <51>
<36>
<53>
<53>
<39>
<40>
HLDAK (output)
<37>
<38>
<52>
Hi-Z
A16 to A19 (output), Note
A1 to A15 (output)
AD0 to AD15 (I/O)
ASTB (output)
Data
Hi-Z
Hi-Z
Hi-Z
DSTB (output), RD (output),
WRL (output), WRH (output)
Remark R/W (output), UBEN (output), LBEN (output)
35
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Reset/Interrupt Timing
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
RESET high-level width
RESET low-level width
NMI high-level width
NMI low-level width
Symbol
Condition
MIN.
500
500
500
500
500
MAX.
Unit
ns
tWRSH
<54>
<55>
<56>
<57>
<58>
tWRSL
tWNIH
tWNIL
tWITH
ns
ns
ns
INTPn high-level width
n = 0 to 3 (analog noise
elimination)
ns
n = 4 to 6 (digital noise
elimination)
3T + 20
ns
INTPn low-level width
tWITL
<59>
n = 0 to 3 (analog noise
elimination)
500
ns
ns
n = 4 to 6 (digital noise
elimination)
3T + 20
Remark T = 1/fXX
Reset
<54>
<55>
RESET (input)
Interrupt
<56>
<58>
<57>
<59>
NMI (input)
INTPn (input)
Remark n = 0 to 6
36
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
TIn Input Timing
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
TIn0, TIn1 high-level width
TIn high-level width
Symbol
Conditions
n = 0, 1
MIN.
MAX.
Unit
ns
t
TIHn
<60>
2T
sam + 20Note
3T + 20
sam + 20Note
3T + 20
n = 2 to 5
n = 0, 1
ns
TIn0, TIn1 low-level width
TIn low-level width
t
TILn
<61>
2T
ns
n = 2 to 5
ns
Note Tsam can be selected by setting the PRMn2 to PRMn0 bits of prescaler mode register n, n1 (PRMn, PRMn1)
(n = 0 and 1).
For TM0 (using PRM0 and PRM01 registers): Tsam = 2T, 4T, 16T, 64T, 256T or 1/INTWTI cycle
For TM1 (using PRM1 and PRM11 registers): Tsam = 2T, 4T, 16T, 32T, 128T, or 256T
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T.
Remark T= 1/fXX
<60>
<61>
Tln
Remark n = 00, 01, 10, 11, 2 to 5
37
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
CSI Timing
(1) Master mode (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
SCKn cycle time
Symbol
tKCY1
tKH1, tKL1
tSIK1
Conditions
MIN.
400
140
50
MAX.
Unit
ns
<62>
<63>
<64>
<65>
<66>
SCKn high-/low-level width
ns
SIn setup time (to SCKn↑)
ns
SIn hold time (from SCKn↑)
Delay time from SCKn↓ to SOn output
tKSI1
50
ns
tKSO1
60
ns
Remark n = 0 to 2
(2) Slave mode (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
SCKn cycle time
Symbol
tKCY2
tKH2, tKL2
tSIK2
Conditions
MIN.
400
140
50
MAX.
Unit
ns
<62>
<63>
<64>
<65>
<66>
SCKn high-/low-level width
ns
SIn setup time (to SCKn↑)
ns
SIn hold time (from SCKn↑)
Delay time from SCKn↓ to SOn output
tKSI2
50
ns
tKSO2
60
ns
Remark n = 0 to 2
<62>
<63>
<63>
SCKn (I/O)
<64>
<65>
SIn (input)
Input data
<66>
SOn (output)
Output data
Remark n = 0 to 2
38
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
UART Timing (TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
ASCKn cycle time
Symbol
Conditions
MIN.
200
80
MAX.
Unit
ns
tKCY13
tKH13
tKL13
<67>
<68>
<69>
ASCKn high-level width
ASCKn low-level width
ns
80
ns
Remark n = 0, 1
<67>
<68>
<69>
ASCKn (input)
Remark n = 0 or 1
39
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
I2C Bus Mode (µPD70F3017AY only)
(TA = –40 to +85°C, VDD = 2.7 to 3.6 V, VSS = 0 V)
Parameter
Symbol
Normal Mode
MIN.
High-Speed Mode
MIN. MAX.
Unit
MAX.
100
–
SCL clock frequency
fCLK
tBUF
0
0
400
–
kHz
Bus-free time (between
stop/start conditions)
<70>
4.7
1.3
µs
Hold timeNote 1
tHD:STA
tLOW
<71>
<72>
<73>
<74>
4.0
4.7
4.0
4.7
–
–
–
–
0.6
1.3
0.6
0.6
–
–
–
–
µs
µs
µs
µs
SCL clock low-level width
SCL clock high-level width
tHIGH
Setup time for start/restart
condition
tSU:STA
Data hold
time
CBUS
tHD:DAT
<75>
5.0
–
–
–
µs
compatible
master
I2C mode
0Note 2
250
–
–
–
0Note 2
0.9Note 3
–
µs
ns
ns
Data setup time
tSU:DAT
tR
<76>
<77>
100Note 4
SDA and SCL signal rise
time
1000
20 + 0.1CbNote 5
300
SDA and SCL signal fall
time
tF
<78>
<79>
–
300
20 + 0.1CbNote 5
300
ns
Stop condition setup time
tSU:STO
Cb
4.0
–
–
0.6
–
–
µs
Capacitance load of each
bus line
400
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDA signal in order to occupy the
undefined area at the falling edge of SCL.
3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:
DAT) needs to be satisfied.
4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions.
• If the system does not extend the SCL signal's low state hold time:
tSU:DAT ≥ 250 ns
• If the system extends the SCL signal's low state hold time:
Transmit the following data bit to the SDA line prior to the SCL line release (tRmax. + tSU:DAT = 1000 +
250 = 1250 ns: Normal mode I2C bus specification).
5. Cb: Total capacitance of one bus line (unit: pF)
Remark The maximum operating frequency of the µPD70F3017AY is 17 MHz.
40
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
I2C Bus Mode (µPD70F3017AY only)
<72>
<77>
SCL
SDA
<74>
<73>
<75>
<78>
<79>
<76>
<71>
<71>
<70>
Restart
condition
Stop
condition
Stop
Start
condition condition
A/D Converter
(TA = –40 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6 V, VSS = AVSS = 0 V, Output pin load capacitance:
CL = 50 pF)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Overall errorNote 1
±0.8
100
±0.4
±0.4
±4
%FSR
µs
Conversion time
tCONV
5
Zero-scale errorNote 1
Full-scale errorNote 1
Integral linearity errorNote 2
Differential linearity errorNote 2
Analog reference voltage
Analog input voltage
AVREF current
%FSR
%FSR
LSB
LSB
V
±4
AVREF
VIAN
AVREF =AVDD
2.7
3.6
AVSS
AVREF
500
3
V
AIREF
AIDD
360
1
µA
Power supply current
mA
Notes 1. Excluding quantization error (±0.05% FSR).
2. Excluding quantization error (±0.5 LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
41
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Flash Memory Programming Mode
Write/erase characteristics (TA = 10 to 40°C, VDD = 3.0 to 3.6 V)
Parameter
Write current
Symbol
IDDW
IPPW
IDDE
Condition
When VPP = VPP1
MIN.
TYP.
MAX.
67
Unit
mA
mA
mA
mA
s
VDD pin
VPP pin
VDD pin
VPP pin
100
67
Erase current
When VPP = VPP1
IPPE
200
0.2
Unit erase time
tER
0.2
0.2
20
Total erase time
tERT
20
s
Number of rewritesNote
20
0
20
Times
V
VPP supply voltage
VPP0
VPP1
During normal operation
0.2VDD
8.1
In flash memory programming mode
7.5
2
7.8
V
Operating frequency
20
MHz
Note Write/erase is regarded as one cycle.
42
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
3. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
16.00±0.20
14.00±0.20
14.00±0.20
16.00±0.20
1.00
G
1.00
+0.05
0.22
H
−0.04
I
J
0.08
0.50 (T.P.)
1.00±0.20
0.50±0.20
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.40±0.05
0.10±0.05
+7°
3°
R
S
−3°
1.60 MAX.
S100GC-50-8EU-1
43
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
121-PIN PLASTIC FBGA (12x12)
S
B
D
w
D1
B
ZD
13
12
11
10
9
ZE
A
8
7
E1
E
6
5
4
3
2
1
N M L K J H G F E D C B A
w
S
A
INDEX MARK
4-R0.3
4-C1.0
A
y1
25°
S
x
A2
S
S
y
e
b
S
A1
M
121-
φ
φ
A B
ITEM MILLIMETERS
12.00±0.10
11.4
D
D1
E
12.00±0.10
11.4
E1
w
0.20
e
0.80
1.31±0.15
0.35±0.10
0.96
A
A1
A2
+0.05
0.50
b
−0.10
x
0.08
y
0.10
0.20
y1
ZD
ZE
1.2
1.2
P121F1-80-EA3-1
44
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
4. RECOMMENDED SOLDERING CONDITIONS
The µPD70F3017A and 70F3017AY should be soldered and mounted under the following recommended
conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your sales representative.
Table 4-1. Surface Mounting Type Soldering Conditions
(1) µPD70F3017AGC-8EU: 100-pin plastic LQFP (14 × 14 mm)
µPD70F3017AYGC-8EU: 100-pin plastic LQFP (14 × 14 mm)
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher).
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
IR35-107-2
VP15-107-2
–
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher).
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Cautions Do not use different soldering methods together (except for partial heating).
(2) µPD70F3017AS1-YJC: 121-pin plastic FBGA (12 × 12 mm)
µPD70F3017AYS1-YJC: 121-pin plastic FBGA (12 × 12 mm)
Soldering Method
Infrared reflow
Partial heating
Soldering Conditions
Recommended
Condition
Symbol
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or higher).
Count: Once
Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours)
IR30-103-1
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
45
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
46
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
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Tel: 02-2719-2377
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Tel: 02-66 75 41
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J99.1
47
Preliminary Data Sheet U14527EJ1V0DS00
µPD70F3017A, 70F3017AY
Reference document Electrical Characteristics for Microcomputer (IEI-601)Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
V850 Family and V850/SA1 are trademarks of NEC Corporation.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
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