UPD70F3102AGJ-33-8EU [NEC]
Microcontroller, 32-Bit, FLASH, 33MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144;型号: | UPD70F3102AGJ-33-8EU |
厂家: | NEC |
描述: | Microcontroller, 32-Bit, FLASH, 33MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144 时钟 微控制器 外围集成电路 |
文件: | 总88页 (文件大小:667K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUITS
µPD70F3102A-33
V850E/MS1TM
32-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD70F3102A-33 is a product that substitutes the internal mask ROM of the µPD703102A-33 with flash
memory. This enables users to perform on-board program writing and erasure, enabling effective evaluation during
system development, small-lot production of multiple devices, and rapid production start, and quick development and
time-to-market.
A version using a 5.0 V power supply for external pins, the µPD70F3102-33, is also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS1 User’s Manual Hardware:
U12688E
V850E/MS1, V850E/MS2TM User’s Manual Architecture: U12197E
FEATURES
• µPD703102A-33 compatible
Can be replaced by the µPD703102A-33 with internal mask ROM for mass production
• Internal flash memory: 128 KB
ORDERING INFORMATION
Part Number
Package
µPD70F3102AF1-33-FA1
µPD70F3102AGJ-33-8EU
µPD70F3102AGJ-33-UENNote
157-pin plastic FBGA (14 × 14)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
Note Under development
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13845EJ5V0DS00 (5th edition)
Date Published June 2002 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1998
µPD70F3102A-33
PIN CONFIGURATION (TOP VIEW)
157-pin plastic FBGA (14 × 14)
•
µPD70F3102AF1-33-FA1
Top view
Bottom view
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B C D E F G H
Index mark
J
K
L M N P R
T
T
R P N M L
K
J
H G F E D C B
Index mark
A
(1/2)
Pin No.
Name
Pin No.
B1
Name
Pin No.
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
—
INTP103/DMARQ3/P07
D1/P41
C1
C2
C3
C4
C5
C6
C7
C8
C9
INTP101/DMARQ1/P05
D0/P40
D2/P42
D4/P44
D6/P46
D8/P50
D10/P52
D13/P55
A0/PA0
A2/PA2
A5/PA5
A8/PB0
A10/PB2
A13/PB5
A15/PB7
—
B2
INTP102/DMARQ2/P06
B3
D3/P43
VSS
B4
D5/P45
VSS
B5
D7/P47
HVDD
B6
D9/P51
VSS
B7
D11/P53
D14/P56
A1/PA1
D12/P54
D15/P57
HVDD
B8
B9
A10
A11
A12
A13
A14
A15
A16
B10
B11
B12
B13
B14
B15
B16
A3/PA3
C10
C11
C12
C13
C14
C15
C16
A4/PA4
A7/PA7
VSS
A6/PA6
A9/PB1
A11/PB3
A14/PB6
A17/P61
A16/P60
A12/PB4
A18/P62
A19/P63
—
2
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(2/2)
Pin No.
Name
TI10/P03
Pin No.
Name
TI12/P103
Pin No.
Name
D1
D2
D3
D4
K1
K2
K3
P14
P15
P16
R1
RESET
INTP100/DMARQ0/P04
HVDD
INTP120/TC0/P104
INTP121/TC1/P105
HLDAK/P96
OE/P95
INTP151/P125
INTP150/P124
AVSS
—
K14
K15
K16
L1
D14
D15
D16
E1
VSS
R2
ANI0/P70
P21
A21/P65
BCYST/P94
TO120/P100
TO121/P101
TCLR12/P102
VSS
R3
A20/P64
R4
SCK0/P24
SCK1/P27
INTP132/SI2/P36
TI13/P33
TO101/P01
L2
R5
E2
TCLR10/P02
VSS
L3
R6
E3
L14
L15
L16
M1
M2
M3
M14
M15
M16
N1
R7
E14
E15
E16
F1
HVDD
REFRQ/PX5
HLDRQ/P97
ANI5/P75
R8
TO130/P30
INTP141/SO3/P115
TCLR14/P112
TO140/P110
MODE0
A23/P67
R9
A22/P66
R10
R11
R12
R13
R14
R15
R16
T1
INTP113/DMAAK3/P17
TO100/P00
ANI6/P76
F2
ANI7/P77
F3
VDD
TO150/P120
WAIT/PX6
MODE1
F14
F15
F16
G1
CS2/RAS2/P82
CS1/RAS1/P81
CS0/RAS0/P80
INTP110/DMAAK0/P14
INTP111/DMAAK1/P15
INTP112/DMAAK2/P16
CS5/RAS5/IORD/P85
CS4/RAS4/IOWR/P84
CS3/RAS3/P83
TO111/P11
MODE2
CLKOUT/PX7
ANI2/P72
INTP153/ADTRG/P127
INTP152/P126
—
N2
ANI3/P73
G2
N3
ANI4/P74
T2
AVREF
G3
N14
N15
N16
P1
TI15/P123
T3
NMI/P20
G14
G15
G16
H1
TCLR15/P122
TO151/P121
AVDD
T4
RXD0/SI0/P23
RXD1/SI1/P26
INTP131/SO2/P35
TCLR13/P32
INTP143/SCK3/P117
INTP140/P114
CVDD
T5
T6
P2
ANI1/P71
T7
H2
TCLR11/P12
TI11/P13
P3
TXD0/SO0/P22
TXD1/SO1/P25
VDD
T8
H3
P4
T9
H14
H15
H16
J1
LCAS/LWR/P90
CS7/RAS7/P87
CS6/RAS6/P86
INTP122/TC2/P106
INTP123/TC3/P107
TO110/P10
P5
T10
T11
T12
T13
T14
T15
T16
—
P6
INTP133/SCK2/P37
INTP130/P34
TO131/P31
INTP142/SI3/P116
TI14/P113
X2
P7
X1
P8
CVSS
J2
P9
MODE3/VPP
—
J3
P10
P11
P12
P13
J14
J15
J16
WE/P93
TO141/P111
CKSEL
—
RD/P92
—
UCAS/UWR/P91
HVDD
—
—
Remark Leave pins A1, A16, C16, D4, T1, T15, and T16 open.
3
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
144-pin plastic LQFP (fine pitch) (20 × 20)
•
•
µPD70F3102AGJ-33-8EU
µPD70F3102AGJ-33-UEN
INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04
TI10/P03
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
TCLR10/P02
TO101/P01
TO100/P00
VSS
9
HVDD
INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14
TI11/P13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CS0/RAS0/P80
CS1/RAS1/P81
CS2/RAS2/P82
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
CS6/RAS6/P86
CS7/RAS7/P87
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
WE/P93
BCYST/P94
OE/P95
HLDAK/P96
HLDRQ/P97
VSS
REFRQ/PX5
WAIT/PX6
CLKOUT/PX7
TO150/P120
TO151/P121
TCLR15/P122
TI15/P123
INTP150/P124
INTP151/P125
INTP152/P126
TCLR11/P12
TO111/P11
TO110/P10
INTP123/TC3/P107
INTP122/TC2/P106
INTP121/TC1/P105
INTP120/TC0/P104
TI12/P103
TCLR12/P102
TO121/P101
TO120/P100
ANI7/P77
ANI6/P76
ANI5/P75
ANI4/P74
ANI3/P73
ANI2/P72
ANI1/P71
ANI0/P70
AVDD
AVSS
AVREF
74
73
4
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
PIN IDENTIFICATION
A0 to A23:
ADTRG:
ANI0 to ANI7:
AVDD:
Address bus
P50 to P57:
P60 to P67:
P70 to P77:
P80 to P87:
P90 to P97:
P100 to P107:
P110 to P117:
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
Port 12
Port A
Port B
Port X
A/D trigger input
Analog input
Analog power supply
Analog reference voltage
Analog ground
AVREF:
AVSS:
BCYST:
CKSEL:
Bus cycle start timing
Clock generator operating mode P120 to P127:
Select
PA0 to PA7:
PB0 to PB7:
PX5 to PX7:
RAS0 to RAS7:
RD:
CLKOUT:
CS0 to CS7:
CVDD:
Clock output
Chip select
Clock generator power supply
Clock generator
Data bus
Row address strobe
Read strobe
CVSS:
D0 to D15:
REFRQ:
Refresh request
Reset
DMAAK0 to DMAAK3: DMA acknowledge
DMARQ0 to DMARQ3: DMA request
RESET:
RXD0, RXD1:
SCK0 to SCK3:
SI0 to SI3:
SO0 to SO3:
TC0 to TC3:
Receive data
Serial clock
HLDAK:
Hold acknowledge
HLDRQ:
Hold request
Serial input
HVDD:
Power supply for external pins
Serial output
Terminal count signal
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
TCLR10 to TCLR15: Timer clear
TI10 to TI15:
Timer input
TO100, TO101,
TO110, TO111,
INTP150 to INTP153: Interrupt request from peripherals TO120, TO121,
IORD:
I/O read strobe
TO130, TO131,
TO140, TO141,
TO150, TO151:
TXD0, TXD1:
UCAS:
IOWR:
I/O write strobe
Lower column address strobe
Lower write strobe
Mode
LCAS:
Timer output
LWR:
Transmit data
MODE0 to MODE3:
NMI:
Upper column address strobe
Upper write strobe
Power supply for internal unit
Programming power supply
Ground
Non-maskable interrupt request UWR:
OE:
Output enable
Port 0
VDD:
P00 to P07:
P10 to P17:
P20 to P27:
P30 to P37:
P40 to P47:
VPP:
Port 1
VSS:
Port 2
WAIT:
WE:
Wait
Port 3
Write enable
Port 4
X1, X2:
Crystal
5
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
INTERNAL BLOCK DIAGRAM
NMI
HLDRQ
CPU
BCU
Flash memory
128 KB
HLDAK
INTP100 to INTP103,
INTC
INTP110 to INTP113,
CS0 to CS7/RAS0 to RAS7
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153
IOWR
Instruction queue
PC
IORD
Multiplier
(32 × 32 → 64)
DRAMC
REFRQ
BCYST
WE
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
RD
Barrel
shifter
OE
Page ROM
controller
RPU
RAM
4 KB
System registers
UWR/UCAS
LWR/LCAS
WAIT
General-purpose
registers
(32 bits × 32)
TCLR10 to TCLR15
TI10 to TI15
ALU
A0 to A23
D0 to D15
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
DMAC
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
UART1/CSI1
BRG1
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
CLKOUT
X1
Ports
CG
X2
CVDD
SO2
SI2
CVSS
CSI2
SCK2
MODE0 to MODE3
RESET
BRG2
System
controller
SO3
SI3
V
PP
CSI3
SCK3
V
V
DD
SS
ANI0 to ANI7
AVREF
AVSS
ADC
AVDD
ADTRG
6
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
CONTENTS
1. DIFFERENCES AMONG PRODUCTS....................................................................................................8
1.1 Differences Between µPD70F3102A-33 and µPD703102A-33....................................................8
1.2 Differences Between µPD70F3102A-33 and µPD70F3102-33 ....................................................8
2. PIN FUNCTIONS......................................................................................................................................9
2.1 Port Pins.........................................................................................................................................9
2.2 Non-Port Pins...............................................................................................................................12
2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins.................................16
3. FLASH MEMORY PROGRAMMING.....................................................................................................19
3.1 Selection of Communication Mode ...........................................................................................19
3.2 Flash Memory Programming Functions....................................................................................20
3.3 Connecting Dedicated Flash Programmer................................................................................20
4. ELECTRICAL SPECIFICATIONS .........................................................................................................21
4.1 Normal Operation Mode..............................................................................................................21
4.2 Flash Memory Programming Mode............................................................................................76
5. PACKAGE DRAWINGS.........................................................................................................................79
6. RECOMMENDED SOLDERING CONDITIONS ....................................................................................82
APPENDIX NOTES ON DESIGNING TARGET SYSTEM..........................................................................83
7
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
1. DIFFERENCES AMONG PRODUCTS
1.1 Differences Between µPD70F3102A-33 and µPD703102A-33
Product
µPD70F3102A-33
µPD703102A-33
Item
Internal ROM
Flash memory
Mask ROM
None
Flash memory programming pin
Flash memory programming mode
Provided (VPP)
Provided (MODE0 = L, MODE1 = H,
MODE2 = L, MODE3/VPP = 7.8 V)
None
Electrical specifications
Others
Consumption current etc. differs (see individual data sheets).
Circuit scale and mask layout differ, thus noise immunity, noise radiation, etc. differ.
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory
version and mask ROM version. When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluation for commercial samples (not engineering samples) of the mask ROM
version.
2. When switching from the flash memory version to the mask ROM version, write the same
code to the free area of the internal ROM.
1.2 Differences Between µPD70F3102A-33 and µPD70F3102-33
Product
µPD70F3102A-33
µPD70F3102-33
Item
HVDD
3.0 to 3.6 V
4.5 to 5.5 V
Electrical specifications
Package
See individual data sheets.
• 157-pin plastic FBGA (14 × 14)
• 144-pin plastic LQFP (fine pitch) (20 × 20)
• 144-pin plastic LQFP (fine pitch) (20 × 20)
8
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
2. PIN FUNCTIONS
2.1 Port Pins
(1/3)
Alternate Function
TO100
Pin Name
P00
I/O
I/O
Function
Port 0
8-bit I/O port
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
TO101
Input/output can be specified in 1-bit units.
TCLR10
TI10
INTP100/DMARQ0
INTP101/DMARQ1
INTP102/DMARQ2
INTP103/DMARQ3
TO110
I/O
Port 1
8-bit I/O port
TO111
Input/output can be specified in 1-bit units.
TCLR11
TI11
INTP110/DMAAK0
INTP111/DMAAK1
INTP112/DMAAK2
INTP113/DMAAK3
NMI
Input
I/O
Port 2
P20 is an input-only port.
—
When a valid edge is input, it operates as an NMI input. The status of
the NMI input is shown by bit 0 of register P2.
P21 to P27 is a 7-bit I/O port.
TXD0/SO0
RXD0/SI0
SCK0
Input/output can be specified in 1-bit units.
TXD1/SO1
RXD1/SI1
SCK1
I/O
Port 3
TO130
8-bit I/O port
TO131
Input/output can be specified in 1-bit units.
TCLR13
TI13
INTP130
INTP131/SO2
INTP132/SI2
INTP133/SCK2
D0 to D7
I/O
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
9
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(2/3)
Alternate Function
D8 to D15
Pin Name
I/O
I/O
Function
P50 to P57
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units.
P60 to P67
P70 to P77
I/O
Port 6
A16 to A23
8-bit I/O port
Input/output can be specified in 1-bit units.
Input
I/O
Port 7
ANI0 to ANI7
8-bit input-only port
P80
Port 8
CS0/RAS0
CS1/RAS1
CS2/RAS2
CS3/RAS3
CS4/RAS4/IOWR
CS5/RAS5/IORD
CS6/RAS6
CS7/RAS7
LCAS/LWR
UCAS/UWR
RD
8-bit I/O port
P81
Input/output can be specified in 1-bit units.
P82
P83
P84
P85
P86
P87
P90
I/O
I/O
I/O
Port 9
8-bit I/O port
P91
Input/output can be specified in 1-bit units
P92
P93
WE
P94
BCYST
P95
OE
P96
HLDAK
P97
HLDRQ
P100
P101
P102
P103
P104
P105
P106
P107
P110
P111
P112
P113
P114
P115
P116
P117
Port 10
TO120
8-bit I/O port
TO121
Input/output can be specified in 1-bit units.
TCLR12
TI12
INTP120/TC0
INTP121/TC1
INTP122/TC2
INTP123/TC3
TO140
Port 11
8-bit I/O port
TO141
Input/output can be specified in 1-bit units.
TCLR14
TI14
INTP140
INTP141/SO3
INTP142/SI3
INTP143/SCK3
10
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(3/3)
Pin Name
P120
I/O
I/O
Function
Alternate Function
Port 12
TO150
TO151
TCLR15
TI15
8-bit I/O port
P121
P122
P123
P124
P125
P126
P127
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PX5
PX6
PX7
Input/output can be specified in 1-bit units.
INTP150
INTP151
INTP152
INTP153/ADTRG
A0
I/O
I/O
I/O
Port A
8-bit I/O port
A1
Input/output can be specified in 1-bit units.
A2
A3
A4
A5
A6
A7
Port B
A8
8-bit I/O port
A9
Input/output can be specified in 1-bit units.
A10
A11
A12
A13
A14
A15
Port X
REFRQ
WAIT
CLKOUT
3-bit I/O port
Input/output can be specified in 1-bit units.
11
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
2.2 Non-Port Pins
(1/4)
Alternate Function
P00
Pin Name
TO100
I/O
Function
Pulse signal output of timers 10 to 15
Output
TO101
TO110
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TO150
TO151
TCLR10
TCLR11
TCLR12
TCLR13
TCLR14
TCLR15
TI10
P01
P10
P11
P100
P101
P30
P31
P110
P111
P120
P121
Input
External clear signal input of timers 10 to 15
P02
P12
P102
P32
P112
P122
Input
External count clock input of timers 10 to 15
P03
TI11
P13
TI12
P103
TI13
P33
TI14
P113
TI15
P123
INTP100
INTP101
INTP102
INTP103
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
Input
Input
Input
External maskable interrupt request input, or timer 10 external capture
trigger input
P04/DMARQ0
P05/DMARQ1
P06/DMARQ2
P07/DMARQ3
P14/DMAAK0
P15/DMAAK1
P16/DMAAK2
P17/DMAAK3
P104/TC0
P105/TC1
P106/TC2
P107/TC3
External maskable interrupt request input, or timer 11 external capture
trigger input
External maskable interrupt request input, or timer 12 external capture
trigger input
12
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(2/4)
Pin Name
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
INTP150
INTP151
INTP152
INTP153
SO0
I/O
Function
Alternate Function
Input
External maskable interrupt request input, or timer 13 external capture
trigger input
P34
P35/SO2
P36/SI2
P37/SCK2
P114
Input
Input
Output
Input
I/O
External maskable interrupt request input, or timer 14 external capture
trigger input
P115/SO3
P116/SI3
P117/SCK3
P124
External maskable interrupt request input, or timer 15 external capture
trigger input
P125
P126
P127/ADTRG
P22/TXD0
P25/TXD1
P35/INTP131
P115/INTP141
P23/RXD0
P26/RXD1
P36/INTP132
P116/INTP142
P24
CSI0 to CSI3 serial transmission data output (3-wire)
CSI0 to CSI3 serial reception data input (3-wire)
CSI0 to CSI3 serial clock input/output (3-wire)
SO1
SO2
SO3
SI0
SI1
SI2
SI3
SCK0
SCK1
P27
SCK2
P37/INTP133
P117/INTP143
P22/SO0
P25/SO1
P23/SI0
SCK3
TXD0
Output
Input
I/O
UART0 and UART1 serial transmission data output
UART0 and UART1 serial reception data input
16-bit data bus for external memory
TXD1
RXD0
RXD1
P26/SI1
D0 to D7
D8 to D15
A0 to A7
A8 to A15
A16 to A23
LWR
P40 to P47
P50 to P57
PA0 to PA7
PB0 to PB7
P60 to P67
P90/LCAS
P91/UCAS
P92
Output
24-bit address bus for external memory
Output
Output
Output
Output
Output
External data bus lower byte write enable signal output
External data bus upper byte write enable signal output
External data bus read strobe signal output
Write enable signal output for DRAM
UWR
RD
WE
P93
OE
Output enable signal output for DRAM
P95
13
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(3/4)
Alternate Function
P90/LWR
Pin Name
LCAS
I/O
Function
Output
Output
Output
Column address strobe signal output for lower data of DRAM
Column address strobe signal output for higher data of DRAM
Row address strobe signal output for DRAM
UCAS
P91/UWR
RAS0 to RAS3
RAS4
P80/CS0 to P83/CS3
P84/CS4/IOWR
P85/CS5/IORD
P86/CS6
RAS5
RAS6
RAS7
P87/CS7
BCYST
CS0 to CS3
Output
Output
Strobe signal output indicating start of bus cycle
Chip select signal output
P94
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
P85/RAS5/IORD
P86/RAS6
CS5
CS6
CS7
P87/RAS7
WAIT
REFRQ
IOWR
IORD
Input
Output
Output
Output
Input
Control signal input that inserts a wait in the bus cycle
Refresh request signal output for DRAM
DMA write strobe signal output
PX6
PX5
P84/RAS4/CS4
P85/RAS5/CS5
DMA read strobe signal output
DMARQ0 to
DMARQ3
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
Output
Output
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
DMA termination (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
HLDRQ
ANI0 to ANI7
NMI
Output
Input
Bus hold acknowledge output
Bus hold request input
P96
P97
Input
Analog input to A/D converter
Non-maskable interrupt request input
System clock output
P70 to P77
P20
Input
CLKOUT
CKSEL
Output
Input
Input
PX7
—
Input that specifies the clock generator's operation mode
Operation mode specification
MODE0 to
MODE2
—
MODE3
RESET
X1
VPP
Input
Input
—
System reset input
—
Connecting system clock resonator. In the case of an external clock, it is
input to X1.
—
X2
—
ADTRG
AVREF
AVDD
Input
Input
—
A/D converter external trigger input
P127/INTP153
Reference voltage applied to A/D converter
Positive power supply for A/D converter
—
—
14
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(4/4)
Pin Name
AVSS
I/O
—
—
—
—
—
—
—
Function
Ground potential for A/D converter
Alternate Function
—
CVDD
CVSS
VDD
Positive power supply for dedicated clock generator
Ground potential for dedicated clock generator
Positive power supply (internal unit power supply)
Positive power supply (external pin power supply)
Ground potential
—
—
—
—
HVDD
VSS
—
VPP
High-voltage application pin during program write/verify
MODE3
15
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins, and Figure 2-1
shows the schematic circuit diagram for each I/O circuit type.
In the case of connection to VDD or VSS via a resistor, connection of a resistor of 1 to 10 kΩ is recommended.
Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit
Type
Recommended Connection of Unused Pins
P00/TO100, P01/TO101
P02/TCLR10, P03/TI10
5
Input: Independently connect to HVDD or VSS via a resistor.
Output: Leave open.
5-K
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110, P11/TO111
P12/TCLR11, P13/TI11
5
5-K
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P20/NMI
2
5
Connect directly to VSS.
P21
Input: Independently connect to HVDD or VSS via a resistor.
Output: Leave open.
P22/TXD0/SO0
P23/RXD0/SI0
5-K
P24/SCK0
P25/TXD1/SO1
P26/RXD1/SI1
5
5-K
P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13, P33/TI13
P34/INTP130
5
5-K
P35/INTP131/SO2
P36/INTP132/SI2
P37/INTP133/SCK2
P40/D0 to P47/D7
P50/D8 to P57/D15
P60/A16 to P67/A23
P70/ANI0 to P77/ANI7
5
9
Connect directly to VSS.
16
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2)
Pin
I/O Circuit
Type
Recommended Connection of Unused Pins
P80/CS0/RAS0 to P83/CS3/RAS3
5
Input: Independently connect to HVDD or VSS via a resistor.
Output: Leave open.
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P86/CS6/RAS6, P87/CS7/RAS7
P90/LCAS/LWR
P91/UCAS/UWR
P92/RD
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120, P101/TO121
P102/TCLR12, P103/TI12
5
Input: Independently connect to HVDD or VSS via a resistor.
Output: Leave open.
5-K
P104/INTP120/TC0 to
P107/INTP123/TC3
P110/TO140, P111/TO141
P112/TCLR14, P113/T114
P114/INTP140
5
5-K
P115/INTP141/SO3
P116/INTP142/SI3
P117/INTP143/SCK3
P120/TO150, P121/TO151
P122/TCLR15, P123/TI15
P124/INTP150 to P126/INTP152
P127/INTP153/ADTRG
PA0/A0 to PA7/A7
PB0/A8 to PB7/A15
PX5/REFRQ
5
5-K
5
PX6/WAIT
PX7/CLKOUT
CKSEL
1
2
–
RESET
MODE0 to MODE2
MODE3/VPP
Connect to VSS via a resistor (RVPP).
Connect directly to VSS.
AVREF, AVSS
–
–
AVDD
Connect directly to HVDD.
17
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Figure 2-1. Pin Input/Output Circuits
Type 1
Type 5-K
VDD
VDD
Data
P-ch
N-ch
IN/OUT
P-ch
IN
Output
disable
N-ch
Input
enable
Type 2
Type 9
P-ch
Comparator
IN
+
ñ
N-ch
IN
VREF (threshold voltage)
Input enable
Schmitt-triggered input with hysteresis characteristics
Type 5
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
Caution
Replace VDD in the circuit diagrams with HVDD.
18
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
3. FLASH MEMORY PROGRAMMING
The following two flash memory programming methods are available.
(1) On-board programming
The program is written to the flash memory using a dedicated flash programmer after the µPD70F3102A-33 is
mounted on the target board. Install the connectors, etc., required for communication with the dedicated flash
programmer, on the target board.
(2) Off-board programming
The program is written to the flash memory using a dedicated adapter before the µPD70F3102A-33 is mounted
on the target board.
3.1 Selection of Communication Mode
Writing to the flash memory is done via serial communication using the dedicated flash programmer. Select one of
the communication modes listed in Table 3-1. Base your selection of the communication mode on the selection
format shown in Table 3-1. Refer to the number of VPP pulses shown in Table 3-1 when selecting the communication
mode.
Table 3-1. Communication Modes
Communication Mode
CSI0
Pins Used
Number of VPP Pulses
SO0 (serial data output)
SI0 (serial data input)
SCK0 (serial clock input)
0
UART0
TXD0 (serial data output)
RXD0 (serial data input)
8
Figure 3-1. Communication Mode Selection Format
7.8 V
V
PP
V
DD
V
SS
V
DD
RESET
V
SS
19
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
3.2 Flash Memory Programming Functions
Flash memory programming is performed by sending and receiving commands and data according to the selected
communication mode. Table 3-2 shows the main flash memory programming functions.
Table 3-2. Main Flash Memory Programming Functions
Function
Batch erase
Description
Erases the contents of the entire memory.
Batch blank check
Data write
Checks whether the entire memory has been erased.
Writes data to flash memory based on the write start address and the number of bytes to be written.
Compares the contents of the entire memory with the input data.
Batch verify
3.3 Connecting Dedicated Flash Programmer
The connection of the dedicated flash programmer to the µPD70F3102A-33 differs depending on the
communication mode. Figures 3-2 and 3-3 show the various connection types.
Figure 3-2. Connection of Dedicated Flash Programmer for CSI0 Mode
Dedicated flash programmer
CLK
µ
CLK
PD70F3102A-33
V
PP
V
PP
DD
VDD
V
RESET
SCK
SO
RESET
SCK0
SI0
SI
SO0
VSS
VSS
Figure 3-3. Connection of Dedicated Flash Programmer for UART0 Mode
Dedicated flash programmer
CLK
µ
CLK
PD70F3102A-33
V
PP
V
V
PP
DD
V
DD
RESET
TxD
RESET
RXD0
TXD0
RxD
V
SS
V
SS
20
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
4. ELECTRICAL SPECIFICATIONS
4.1 Normal Operation Mode
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +4.6
Unit
V
VDD pin
HVDD
CVDD
CVSS
AVDD
AVSS
VI
HVDD pin, HVDD ≥ VDD
CVDD pin
–0.5 to +4.6
V
–0.5 to +4.6
V
CVSS pin
–0.5 to +0.5
V
AVDD pin
–0.5 to HVDD + 0.5Note
V
AVSS pin
–0.5 to +0.5
V
Input voltage
Except X1 pin, MODE3/VPP pin
MODE3/VPP pin
X1, VDD = 3.0 to 3.6 V
1 pin
–0.5 to HVDD + 0.5Note
–0.5 to 8.5
V
V
Clock input voltage
Output current, low
VK
IOL
–0.5 to VDD + 1.0Note
V
4.0
mA
mA
mA
mA
V
Total of all pins
1 pin
100
Output current, high
IOH
–4.0
Total of all pins
HVDD = 3.0 to 3.6 V
–100
Output voltage
VO
–0.5 to HVDD + 0.5Note
–0.5 to HVDD + 0.5Note
–0.5 to AVDD + 0.5Note
–0.5 to HVDD + 0.5Note
–0.5 to AVDD + 0.5Note
–40 to +85
Analog input voltage
VIAN
P70/ANI0 to
AVDD > HVDD
V
P77/ANI7 pins
HVDD ≥ AVDD
V
A/D converter reference input
voltage
AVREF
AVDD > HVDD
V
HVDD ≥ AVDD
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +125
Note The product must be used under conditions that ensure the absolute maximum ratings (max. values) of
each supply voltage are not exceeded.
Cautions 1. Do not directly connect output pins (or I/O pins) of IC products to each other, and do not
connect them directly to VDD, VCC, or GND. However, open-drain pins and open-collector
pins can be directly connected to each other. Moreover, external circuits that implement a
timing that avoids conflict with the output of pins that go into high-impedance can be
directly connected.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
21
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Capacitance (TA = 25°C, VDD = HVDD = CVDD = AVDD = VSS = CVSS = AVSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Operation Mode
Internal Operation Clock
Frequency (fX)
Operating Ambient Temperature
(TA)
Supply Voltage (VDD, HVDD)
Direct mode
2 to 33 MHz
–40 to +85°C
–40 to +85°C
3.0 to 3.6 V
3.0 to 3.6 V
PLL modeNote 1
20 to 33 MHzNote 2
Notes 1. The internal operation clock frequency in PLL mode is the value during ×5 operation. Operation at 20
MHz or lower is possible when using ×1 or ×1/2 operation by setting the CKDIVn (n = 0, 1) bit of the
CKC register.
2. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
22
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Recommended Oscillator
(a) Connection of ceramic resonator (TA = –40 to +85°C)
(i) Murata Mfg. Co., Ltd. (TA = –40 to +85°C)
X1
X2
R
d
C1
C2
Oscillation
Stabilization Time
(MAX.)
Type
Product Name
Oscillation
Frequency
fXX (MHz)
Recommended Circuit
Constant
Oscillation Voltage
Range
TOST (ms)
C1 (pF)
100
C2 (pF)
100
Rd (kΩ) MIN. (V) MAX. (V)
Surface
mount
CSAC4.00MGC040
CSTCC4.00MG0H6
CSAC5.00MGC040
CSTCC5.00MG0H6
CSAC6.60MT
4.0
4.0
5.0
5.0
6.6
6.6
4.0
4.0
5.0
5.0
6.6
6.6
0
0
0
0
0
0
0
0
0
0
0
0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.5
0.3
0.4
0.2
0.2
0.1
0.5
0.5
0.5
0.5
0.1
0.1
On-chip On-chip
100 100
On-chip On-chip
30 30
On-chip On-chip
100 100
On-chip On-chip
100 100
On-chip On-chip
30 30
On-chip On-chip
CSTCC6.60MG0H6
CSA4.00MG040
CSTC4.00MGW040
CSA5.00MG040
CSTC5.00MGW040
CSA6.60MTZ
Lead
CSA6.60MTW
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD70F3102A-33 and the resonator.
23
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(ii) TDK Corporation (TA = –40 to +85°C)
X1
X2
R
d
C1
C2
Oscillation
Stabilization Time
(MAX.)
Manufacturer
TDK
Product Name
Oscillation
Frequency
fXX (MHz)
Recommended Circuit
Constant
Oscillation Voltage
Range
TOST (ms)
C1 (pF)
C2 (pF)
Rd (kΩ) MIN. (V) MAX. (V)
CCR4.0MC3
CCR5.0MC3
4.0
5.0
On-chip On-chip
On-chip On-chip
0
0
3.0
3.0
3.6
3.6
0.17
0.15
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD70F3102A-33 and the resonator.
(iii) Kyocera Corporation (TA = –20 to +80°C)
X1
X2
R
d
C1
C2
Oscillation
Stabilization Time
(MAX.)
Manufacturer
Kyocera
Product Name
Oscillation
Frequency
fXX (MHz)
Recommended Circuit
Constant
Oscillation Voltage
Range
TOST (ms)
C1 (pF)
C2 (pF)
Rd (kΩ) MIN. (V) MAX. (V)
PBRC5.00BR-A
PBRC6.00BR-A
PBRC6.60BR-A
5.0
6.0
6.6
On-chip On-chip
On-chip On-chip
On-chip On-chip
0
0
0
3.0
3.0
3.0
3.6
3.6
3.6
0.06
0.06
0.06
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD70F3102A-33 and the resonator.
24
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(b) External clock input (TA = –40 to +85°C)
X1
X2
Open
External clock
Caution Input a CMOS level voltage to the X1 pin.
Cautions when turning on/off the power
The µPD70F3102A-33 is configured with power supply pins for the internal unit (VDD) and for the external pins
(HVDD).
The operation guaranteed range is VDD = HVDD = 3.0 to 3.6 V. The input and output state of ports may be
undefined when the voltage exceeds this range.
25
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
DC Characteristics (TA = –40 to 85°C, VDD = HVDD = CVDD = AVDD = 3.0 to 3.6 V, VSS = CVSS = AVSS = 0 V)
Parameter
Input voltage, high
Symbol
VIH
Conditions
Except Note 1
MIN.
0.65HVDD
0.8HVDD
–0.5
TYP.
MAX.
Unit
V
HVDD + 0.3
HVDD + 0.3
0.2HVDD
Note 1
V
Input voltage, low
VIL
VXH
VXL
Except Notes 1 and 2
Note 1
V
–0.5
0.15HVDD
VDD + 0.3
VDD + 0.3
0.15VDD
V
Clock input voltage, high
Clock input voltage, low
X1 pin
Direct mode
PLL mode
Direct mode
PLL mode
0.8VDD
0.8VDD
–0.3
V
V
X1 pin
V
–0.3
0.15VDD
V
Schmitt trigger input threshold
voltage
HVT+
HVT–
Note 1, rising edge
Note 1, falling edge
Note 1
2.0
1.0
V
V
Schmitt trigger input hysteresis
width
HVT+
–HVT–
0.3
V
Output voltage, high
VOH
VOL
ILIH
IOH = –1.0 mA
0.8HVDD
V
Output voltage, low,
IOL = 2.5 mA
0.15HVDD
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
VI = HVDD, except Note 2
VI = 0 V, except Note 2
VO = HVDD
µA
µA
µA
µA
mA
mA
mA
µA
µA
ILIL
–10
ILOH
ILOL
IDD1
IDD2
IDD3
IDD4
10
VO = 0 V
–10
Supply
currentNote 3
Normal
HALT
IDLE
2.7 × fX
1.2 × fX
3.0
4.5 × fX
3.0 × fX
10.0
50
STOP
–40°C ≤ TA ≤ +40°C
+40°C < TA ≤ +85°C
5.0
600
Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2,
P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3,
P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10,
P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11,
P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,
P27/SCK1, MODE0 to MODE2, RESET
2. When using the P70/AN10 to P77/AN17 pins as analog inputs.
3. VDD + HVDD + CVDD
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = HVDD = CVDD = 3.3 V.
2. Direct mode: fX (CPU operation frequency) = 2 to 33 MHz
PLL mode: fX (CPU operation frequency) = 20 to 33 MHz
3. The fX unit is MHz.
26
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Conditions
MIN.
1.5
TYP.
5.0
MAX.
3.6
Unit
V
STOP mode, VDD = VDDDR
VDD =
VDDDR
–40°C ≤ TA ≤ +40°C
+40°C < TA ≤ +85°C
50
µA
µA
µs
600
Supply voltage rise time
Supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
Supply voltage hold time
(from STOP mode setting)
ms
STOP release signal input time
tDREL
0
ns
V
Data retention high-level input
voltage
VIHDR
Note
Note
0.8VDDDR
VDDDR
Data retention low-level input
voltage
TILDR
0
0.2VDDDR
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2,
P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3,
P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10,
P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13,
P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1,
MODE0 to MODE2, RESET
Remark TYP. values are reference values for when TA = 25°C.
STOP mode setting
V
DDDR
V
DD
tFVD
t
RVD
t
HVD
t
DREL
V
V
IHDR
RESET (input)
IHDR
STOP mode release interrupt (NMI)
(released by falling edge)
STOP mode release interrupt (NMI)
(released by rising edge)
V
ILDR
27
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
AC Characteristics (TA = –40 to +85°C, VDD = HVDD = CVDD = AVDD = 3.0 to 3.6 V, VSS = CVSS = AVSS = 0 V,
Output Pin Load Capacitance: CL = 50 pF)
AC Test Input Measurement Points
(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HVDD
0.8HVDD
0.8HVDD
Measurement
points
Input signal
0.15HVDD
0.15HVDD
0 V
(b) Other than (a)
Input signal
V
DD
0.65HVDD
0.2HVDD
0.65HVDD
0.2HVDD
Measurement
points
0 V
AC Test Output Measurement Points
2.0 V
0.8 V
2.0 V
0.8 V
Measurement
points
Output signal
Load Conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
28
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(1) Clock timing
Parameter
Symbol
<1>
Conditions
In direct mode
MIN.
15
150
5
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X1 input cycle
tCYX
tWXH
tWXL
tXR
In PLL mode
In direct mode
In PLL mode
In direct mode
In PLL mode
In direct mode
In PLL mode
In direct mode
In PLL mode
250
X1 input high-level width
X1 input low-level width
X1 input rise time
<2>
<3>
<4>
<5>
50
5
50
4
10
4
X1 input fall time
tXF
10
100
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<6>
<7>
<8>
<9>
<10>
tCYK
tWKH
tWKL
tKR
30
0.5T – 7
0.5T – 4
5
5
CLKOUT fall time
tKF
Remark T = tCYK
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<3>
<2>
<4>
X1
(direct mode)
<5>
CLKOUT (output)
<9>
<10>
<7>
<8>
<6>
29
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(2) Output waveform (other than CLKOUT)
Parameter
Output rise time
Output fall time
Symbol
<12> tOR
<13> tOF
Conditions
MIN.
MAX.
Unit
ns
5
5
ns
<12>
<13>
Signals other than CLKOUT
30
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(3) Reset timing
Parameter
Symbol
<14> tWRSH
<15> tWRSL
Conditions
MIN.
500
MAX.
Unit
ns
RESET pin high-level width
RESET pin low-level width
At power ON, STOP mode release
500 + TOS
500
ns
Except at power ON, STOP mode
release
ns
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (input)
31
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(4) SRAM, external ROM, external I/O access timing
(a) Access timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
2
MAX.
10
Unit
ns
Address, CSn output delay time
<16>
tDKA
(from CLKOUT↓)
Address, CSn output hold time
<17>
<18>
<19>
<20>
<21>
<22>
<23>
tHKA
2
2
2
2
2
2
2
10
14
14
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
(from CLKOUT↓)
RD, IORD↓ delay time
(from CLKOUT↑)
tDKRDL
tHKRDH
tDKWRL
tHKWRH
tDKBSL
tHKBSH
RD, IORD↑ delay time
(from CLKOUT↑)
UWR, LWR, IOWR↓ delay time
(from CLKOUT↑)
UWR, LWR, IOWR↑ delay time
(from CLKOUT↑)
BCYST↓ delay time
(from CLKOUT↓)
BCYST↑ delay time
(from CLKOUT↓)
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
<24>
<25>
<26>
tSWK
tHKW
tSKID
10
2
ns
ns
ns
Data input setup time
10
(to CLKOUT↑)
Data input hold time
<27>
<28>
<29>
tHKID
tDKOD
tHKOD
2
2
2
ns
ns
ns
(from CLKOUT↑)
Data output delay time
10
10
(from CLKOUT↓)
Data output hold time
(from CLKOUT↓)
Remarks 1. Observe at least one of the data input hold times, tHKID or tHRDID.
2. n = 0 to 7
32
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(a) Access timing (SRAM, external ROM, external I/O) (2/2)
T1
TW
T2
CLKOUT (output)
<16>
<17>
A0 to A23 (output)
CSn (output)
<22>
<23>
BCYST (output)
<18>
<20>
<19>
<21>
RD, IORD (output)
[Read time]
UWR, LWR, IOWR (output)
[Write time]
<26>
<27>
D0 to D15 (I/O)
[Read time]
<28>
<29>
D0 to D15 (I/O)
[Write time]
<25>
<25>
<24>
<24>
WAIT (input)
Remarks 1. Timing when number of waits specified by registers DWC1 and DWC2 is 0.
2. Broken lines indicate high impedance.
3. n = 0 to 7
33
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(b) Read timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
Data input setup time (to address)
Data input setup time (to RD)
RD, IORD low-level width
RD, IORD high-level width
<30>
tSAID
tSRDID
tWRDL
tWRDH
tDARD
(1.5 + wD + w)T – 20
(1 + wD +w)T – 24
<31>
<32>
<33>
<34>
ns
(1 + wD + w)T – 10
T – 10
ns
ns
Delay time from address, CSn to
0.5T – 5
ns
RD, IORD↓
Delay time from RD, IORD↑ to
address
<35>
<36>
<37>
tDRDA
tHRDID
tDRDOD
(0.5 + i)T – 5
0
ns
ns
ns
Data input hold time
(from RD, IORD↑)
Delay time from RD, IORD↑ to
(0.5 + i)T – 10
data output
WAIT setup time (to address)
WAIT setup time (to BCYST↓)
WAIT hold time (from BCYST↑)
<38>
<39>
<40>
tSAW
tSBSW
tHBSW
Note
Note
Note
T – 20
T – 20
ns
ns
ns
0
Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wD: Number of waits specified by registers DWC1, DWC2
4. i: Number of idle states inserted when a write cycle follows the read cycle.
5. Observe at least one of the data input hold times, tHKID or tHRDID.
6. n = 0 to 7
34
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(b) Read timing (SRAM, external ROM, external I/O) (2/2)
T1
TW
T2
CLKOUT (output)
A0 to A23 (output)
CSn (output)
UWR, LWR, IOWR (output)
<33>
<32>
<35>
<37>
RD, IORD (output)
<34>
<31>
<30>
<36>
D0 to D15 (I/O)
<38>
WAIT (input)
<39>
<40>
BCYST (output)
Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0.
2. Broken lines indicate high impedance.
3. n = 0 to 7
35
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(c) Write timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
Note
MIN.
MAX.
T – 20
T – 20
Unit
ns
WAIT setup time (to address)
WAIT setup time (to BCYST↓)
WAIT hold time (from BCYST↑)
<38>
tSAW
tSBSW
tHBSW
tDAWR
<39>
<40>
<41>
Note
ns
Note
0
ns
Delay time from address, CSn to
0.5T – 5
ns
UWR, LWR, IOWR↓
Address setup time
<42>
<43>
tSAWR
(1.5 + wD + w)T – 10
0.5T – 5
ns
ns
(to UWR, LWR, IOWR↑)
Delay time from UWR, LWR,
tDWRA
IOWR↑ to address
UWR, LWR, IOWR high-level width
UWR, LWR, IOWR low-level width
<44>
<45>
<46>
tWWRH
tWWRL
tSODWR
T – 10
ns
ns
ns
(1 + wD + w)T – 10
(1.5 + wD + w)T – 10
Data output setup time (to UWR,
LWR, IOWR↑)
Data output hold time (from UWR,
<47>
tHWROD
0.5T – 5
ns
LWR, IOWR↑)
Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wD: Number of waits specified by registers DWC1 and DWC2
4. n = 0 to 7
36
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(c) Write timing (SRAM, external ROM, external I/O) (2/2)
T1
TW
T2
CLKOUT (output)
A0 to A23 (output)
CSn (output)
RD, IORD (output)
<42>
<43>
<41>
<44>
<45>
UWR, LWR, IOWR (output)
<46>
<47>
D0 to D15 (I/O)
<38>
WAIT (input)
<39>
<40>
BCYST (output)
Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0.
2. Broken lines indicate high impedance.
3. n = 0 to 7
37
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
RD low-level width
Symbol
<24> tSWK
tHKW
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
2
<25>
<32>
<33>
tWRDL
tWRDH
tDARD
tDRDA
tDRDOD
tSAW
(1 + wD + wF + w)T – 10
T – 10
RD high-level width
Delay time from address, CSn to RD↓ <34>
0.5T – 5
Delay time from RD↑ to address
Delay time from RD↑ to data output
WAIT setup time (to address)
WAIT setup time (to BCYST↓)
WAIT hold time (from BCYST↑)
Delay time from address to IOWR↓
Address setup time (to IOWR↑)
Delay time from IOWR↑ to address
IOWR high-level width
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
<44>
<45>
<48>
(0.5 + i)T – 5
(0.5 + i)T – 10
Note
Note
Note
T – 20
T – 20
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
tWWRH
tWWRL
tDWRRD
0
0.5T – 5
(1.5 + wD + w)T – 10
0.5T – 5
T – 10
IOWR low-level width
(1 + wD + w)T – 10
0
Delay time from IOWR↑ to RD↑
wF = 0
wF = 1
T – 10
Delay time from DMAAKm↓ to IOWR↓ <49>
Delay time from IOWR↑ to DMAAKm↑ <50>
tDDAWR
tDWRDA
0.5T – 10
(0.5 + wF)T – 10
Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wD: Number of waits specified by registers DWC1, DWC2
4. wF: Number of waits inserted to source-side access during DMA flyby transfer
5. i: Number of idle states inserted when a write cycle follows the read cycle
6. n = 0 to 7, m = 0 to 3
38
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (output)
A0 to A23 (output)
CSn (output)
<33>
<32>
<35>
RD (output)
UWR, LWR (output)
DMAAKm (output)
IORD (output)
<34>
<48>
<49>
<41>
<50>
<43>
<42>
<45>
<44>
IOWR (output)
<37>
D0 to D15 (I/O)
WAIT (input)
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (output)
Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0 and wF = 0.
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
39
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
IORD low-level width
Symbol
<24> tSWK
tHKW
Conditions
MIN.
MAX.
Unit
ns
10
<25>
<32>
<33>
<34>
2
(1 + wD + wF + w)T – 10
T – 10
ns
tWRDL
tWRDH
tDARD
ns
IORD high-level width
ns
Delay time from address, CSn to
0.5T – 5
ns
IORD↓
Delay time from IORD↑ to address
<35>
tDRDA
tDRDOD
tSAW
(0.5 + i)T – 5
(0.5 + i)T – 10
ns
ns
ns
ns
ns
ns
Delay time from IORD↑ to data output <37>
WAIT setup time (to address)
WAIT setup time (to BCYST↓)
WAIT hold time (from BCYST↑)
<38>
<39>
<40>
<41>
Note
Note
Note
T – 20
T – 20
tSBSW
tHBSW
tDAWR
0
Delay time from address to UWR,
0.5T – 5
LWR↓
Address setup time (to UWR, LWR↑)
<42>
<43>
tSAWR
tDWRA
(1.5 + wD + w)T – 10
0.5T – 5
ns
ns
Delay time from UWR, LWR↑ to
address
UWR, LWR high-level width
UWR, LWR low-level width
<44>
<45>
<48>
tWWRH
tWWRL
tDWRRD
T – 10
(1 + wD + w)T – 10
0
ns
ns
ns
ns
ns
ns
Delay time from UWR, LWR↑ to
IORD↑
wF = 0
wF = 1
T – 10
Delay time from DMAAKm↓ to IORD↓ <51>
Delay time from IORD↑ to DMAAKm↑ <52>
tDDARD
tDRDDA
0.5T – 10
0.5T – 10
Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0.
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wD: Number of waits specified by registers DWC1 and DWC2.
4. wF: Number of waits inserted to source-side access during DMA flyby transfer.
5. i: Number of idle states inserted when a write cycle follows the read cycle.
6. n = 0 to 7, m = 0 to 3
40
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (output)
A0 to A23 (output)
CSn (output)
<42>
<45>
<43>
<41>
<44>
UWR, LWR (output)
<48>
RD (output)
<51>
<52>
DMAAKm (output)
IOWR (output)
IORD (output)
D0 to D15 (I/O)
WAIT (input)
<34>
<33>
<32>
<35>
<37>
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (output)
Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0 and wF = 0.
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
41
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(5) Page ROM access timing (1/2)
Parameter
Symbol
<24> tSWK
tHKW
tSKID
Conditions
MIN.
10
MAX.
Unit
ns
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
<25>
<26>
2
ns
Data input setup time
10
ns
(to CLKOUT↑)
Data input hold time
<27>
<30>
<31>
tHKID
2
ns
ns
ns
(from CLKOUT↑)
Off-page data input setup time
(to address)
tSAID
(1.5 + wD +w)T – 20
(1 + wD + w)T – 24
Off-page data input setup time
(to RD)
tSRDID
Off-page RD low-level width
RD high-level width
<32>
<33>
<36>
<37>
<53>
<54>
tWRDL
tWRDH
tHRDID
tDRDOD
tWORDL
tSOAID
(1 + wD + w)T – 10
0.5T – 10
ns
ns
ns
ns
ns
ns
Data input hold time (from RD)
Delay time from RD↑ to data output
On-page RD low-level width
0
(0.5 + i)T – 10
(1.5 + wPR + w)T – 10
On-page data input setup time
(to address)
(1.5 + wPR + w)T – 20
(1.5 + wPR + w)T – 24
On-page data input setup time
(to RD)
<55>
tSORDID
ns
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wD: Number of waits specified by registers DWC1 and DWC2.
4. wPR: Number of waits specified by register PRC.
5. i: Number of idle states inserted when a write cycle follows the read cycle.
6. Observe at least one of the data input hold times, tHKID or tHRDID.
42
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1 TPRW
TW
TO2
CLKOUT (output)
Off-page addressNote
CSn (output)
On-page addressNote
UWR, LWR (output)
RD (output)
<26>
<30>
<31>
<54>
<33>
<53>
<55>
<32>
<37>
<36>
<27>
<36>
<27>
<26>
<25>
D0 to D15 (I/O)
WAIT (input)
<25>
<24>
<24>
<25>
<24>
<25>
<24>
BCYST (output)
Note On-page addresses and off-page addresses are as follows.
PRC Register
On-Page Address
Off-Page Address
MA5
MA4
MA3
0
0
0
1
0
0
1
1
0
1
1
1
A0, A1
A0 to A2
A0 to A3
A0 to A4
A2 to A23
A3 to A23
A4 to A23
A5 to A23
Remarks 1. These timings are for the following cases:
Number of waits (TDW) specified by registers DWC1 and DWC2: 1
Number of waits (TPRW) specified by register PRC: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
43
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
Conditions
MIN.
10
2
MAX.
Unit
ns
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
<24>
<25>
tSWK
tHKW
tSKID
tHKID
ns
Data input setup time (to CLKOUT↑) <26>
10
2
ns
Data input hold time (from
<27>
ns
CLKOUT↑)
Delay time from OE↑ to data output
Row address setup time
Row address hold time
<37>
<56>
<57>
<58>
<59>
<60>
tDRDOD
tASR
tRAH
tASC
tCAH
tRC
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
ns
ns
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w)T – 10
(3 + wRP + wRH + wDA +
w)T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 5
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
<68>
<69>
<70>
<71>
<72>
tRSH
tRAL
tCAS
tCRP
tCSH
tRCS
tRRH
tRCH
tCPN
tOEA
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wRP)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS to RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T – 10
(2 + wRP + wRH)T – 10
0.5T – 10
WE setup time
WE hold time (from RAS↑)
WE hold time (from CAS↑)
CAS precharge time
T – 10
(2 + wRP + wRH)T – 5
Output enable access time
(2 + wRP + wRH + wDA +
w)T – 20
RAS access time
<73>
<74>
<75>
tRAC
tAA
(2 + wRH + wDA + w)T – 20
(1.5 + wDA + w)T – 20
(1 + wDA + w)T – 20
ns
ns
ns
Access time from column address
CAS access time
tCAC
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. i: Number of idle states inserted when a write cycle follows the read cycle.
44
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
Symbol
Conditions
MIN.
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
MAX.
Unit
ns
RAS column address delay time
RAS to CAS delay time
<76>
tRAD
tRCD
tOEZ
<77>
<78>
ns
Output buffer turn off delay time
ns
(from OE↑)
Output buffer turn off delay time
<79>
tOFF
0
ns
(from CAS↑)
Remarks 1. T = tCYK
2. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
45
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<58>
<56>
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (output)
LCAS (output)
<69>
<70>
<71>
<68>
<73>
<75>
WE (output)
OE (output)
<79>
<74>
<27>
<37>
<72>
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (input)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
46
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
[MEMO]
47
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(b) Read timing (high-speed DRAM access: on-page) (1/2)
Parameter
Symbol
<26>
Conditions
MIN.
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT↑)
tSKID
tHKID
tDRDOD
tASC
tCAH
tRSH
tRAL
Data input hold time (from CLKOUT↑) <27>
2
Delay time from OE↑ to data output
Column address setup time
Column address hold time
RAS hold time
<37>
<58>
<59>
<63>
<64>
<65>
<68>
<69>
<70>
<72>
<74>
<75>
<78>
(0.5 + i)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
(1 + wCP)T – 10
0.5 T – 10
Column address read time for RAS
CAS pulse width
tCAS
tRCS
tRRH
tRCH
tOEA
tAA
WE setup time (to CAS↓)
WE hold time (from RAS↑)
WE hold time (from CAS↑)
Output enable access time
Access time from column address
CAS access time
T – 10
(1 + wCP + wDA)T – 20
(1.5 + wCP + wDA)T – 20
(1 + wDA)T – 20
tCAC
tOEZ
Output buffer turn-off delay time
0
0
(from OE↑)
Output buffer turn-off delay time
<79>
tOFF
ns
(from CAS↑)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<82>
<83>
tACP
tCP
(2 + wCP + wDA)T – 20
ns
ns
ns
ns
(1 + wCP)T – 5
High-speed page mode cycle time
RAS hold time from CAS precharge
tPC
(2 + wCP + wDA)T – 10
(2.5 + wCP + wDA)T – 10
tRHCP
Remarks 1. T = tCYK
2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. i: Number of idle states inserted when a write cycle follows the read cycle.
48
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(b) Read timing (high-speed DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
<82>
UCAS (output)
LCAS (output)
<69>
<70>
<68>
WE (output)
OE (output)
<75>
<79>
<37>
<72>
<26>
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (input)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
49
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
Symbol
<24>
Conditions
MIN.
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
Row address setup time
Row address hold time
tSWK
tHKW
tASR
tRAH
tASC
tCAH
tRC
<25>
<56>
<57>
<58>
<59>
<60>
2
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w)T – 10
(3 + wRP + wRH + wDA +
w)T – 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 5
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
tRSH
tRAL
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
ns
ns
Column address read time (from
RAS↑)
CAS pulse width
<65>
<66>
<67>
<71>
<76>
<77>
<84>
<85>
<86>
<87>
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tWCS
tWCH
tDS
(1 + wDA + w)T – 10
(1 + wRH)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS to RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T – 10
(2 + wRP + wRH)T – 5
(0.5+ wRH)T – 10
CAS precharge time
RAS column address delay time
RAS to CAS delay time
WE setup time (to CAS↓)
WE hold time (from CAS↓)
Data setup time (to CAS↓)
Data hold time (from CAS↓)
(1 + wRH)T – 10
(1 + wRP + wRH)T – 10
(1 + wDA + w)T – 10
(1.5 + wRP + wRH)T – 10
(1.5 + wDA + w)T – 10
tDH
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
50
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<58>
<56>
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (output)
LCAS (output)
<71>
OE (output)
WE (output)
<84>
<85>
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (input)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
51
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Column address setup time
Column address hold time
RAS hold time
Symbol
Conditions
MIN.
MAX.
Unit
ns
<58>
tASC
tCAH
tRSH
tRAL
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
<59>
<63>
<64>
ns
ns
Column address read time (from
ns
RAS↑)
CAS pulse width
<65>
<81>
<83>
<84>
<85>
<86>
<87>
<88>
<89>
<90>
<91>
<92>
tCAS
tCP
(1 + wDA)T – 10
(1 + wCP)T – 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS precharge time
RAS hold time for CAS precharge
WE setup time (to CAS↓)
WE hold time (from CAS↓)
Data setup time (to CAS↓)
Data hold time (from CAS↓)
WE read time (from RAS↑)
WE read time (from CAS↑)
Data setup time (to WE↓)
Data hold time (from WE↓)
WE pulse width
tRHCP
tWCS
tWCH
tDS
(2.5 + wCP + wDA)T – 10
wCPT – 10
wCP ≥ 1
(1 + wDA)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(1 + wDA)T – 10
0.5T – 10
tDH
tRWL
tCWL
tDSWE
tDHWE
tWP
wCP = 0
wCP = 0
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA)T – 10
(1 + wDA)T – 10
Remarks 1. T = tCYK
2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
52
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
UCAS (output)
LCAS (output)
<89>
<88>
OE (output)
WE (output)
<84>
<85>
<92>
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (input)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
53
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Conditions
MIN.
10
MAX.
Unit
ns
Data input setup time (to CLKOUT↑)
<26>
<27>
tSKID
tHKID
Data input hold time (from
2
ns
CLKOUT↑)
Data output delay time from OE↑
Row address setup time
Row address hold time
<37>
<56>
<57>
<58>
<59>
<61>
tDRDOD
tASR
tRAH
tASC
tCAH
tRP
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Column address setup time
Column address hold time
RAS precharge time
(0.5 + wDA)T – 10
(0.5 + wRP)T – 5
(2 + wCP + wDA)T – 10
(1 + wRP)T – 10
(1.5 + wRH + wDA)T – 10
(2 + wRP +wRH)T – 10
0.5T – 10
Column address read time (to RAS↑) <64>
tRAL
tCRP
tCSH
tRCS
tRRH
tRCH
tRAC
tAA
CAS to RAS precharge time
CAS hold time
<66>
<67>
<68>
<69>
<70>
<73>
<74>
<75>
<76>
WE setup time (to CAS↓)
WE hold time (from RAS↑)
WE hold time (from CAS↑)
RAS access time
1.5T – 10
(2 + wRH + wDA)T – 20
(1.5 + wDA)T – 20
(1 + wDA)T – 20
Access time from column address
CAS access time
tCAC
tRAD
Delay time from RAS to column
address
(0.5 + wRH)T – 10
RAS to CAS delay time
<77>
<78>
tRCD
tOEZ
(1 + wRH)T – 10
ns
ns
Output buffer turn-off delay time
(from OE)
0
Access time from CAS precharge
CAS precharge time
<80>
<81>
<83>
<93>
<94>
<95>
<96>
<97>
<98>
tACP
tCP
tRHCP
tHPC
(1.5 + wCP + wDA)T – 20
ns
ns
ns
ns
ns
ns
ns
ns
ns
(0.5 + wCP)T – 5
(2 + wCP + wDA)T – 10
(1 + wDA + wCP)T – 10
(2.5 + wRH + wDA)T – 10
(0.5 + wDA)T – 10
(2 + wRH + wDA)T – 10
(0.5 + wDA)T – 10
0
RAS hold time for CAS precharge
Read cycle time
RAS pulse width
tRASP
tHCAS
tOCH1
tOCH2
tDHC
CAS pulse width
CAS hold time
from OE
Off-page
On-page
Data input hold time (from CAS↓)
Remarks 1. T = tCYK
2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. i: Number of idle states inserted when a write cycle follows the read cycle.
54
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(e) Read timing (EDO DRAM) (2/3)
Parameter
Output enable
access time
Symbol
Conditions
MIN.
MAX.
Unit
ns
Off-page
On-page
<99>
tOEA1
(2 + wRP + wRH + wDA)T
– 20
<100>
tOEA2
(1 + wCP + wDA)T – 20
ns
Remarks 1. T = tCYK
2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
55
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (output)
<58>
<57>
<56>
<59>
A0 to A23 (output)
RASn (output)
Row address
<76>
Column address
Column address
<64>
<74>
<61>
<94>
<67>
<83>
<75>
<66>
<77>
<95>
<93>
<81>
UCAS (output)
LCAS (output)
<69>
<70>
<68>
<95>
<80>
WE (output)
OE (output)
<97>
<96>
<100> <26>
<37>
Note
<75>
<98>
<27>
<27>
<78>
<74>
<26>
D0 to D15 (I/O)
BCYST (output)
WAIT (input)
Data
Data
<73>
<99>
Note In case of on-page access from another cycle, while RASn is low level.
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
56
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
[MEMO]
57
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(f) Write timing (EDO DRAM) (1/2)
Parameter
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<56>
<57>
<58>
<59>
<61>
<63>
<64>
tASR
tRAH
tASC
tCAH
tRP
(0.5 + wRP)T – 10
(0.5 + wRH)T –10
0.5T – 10
(0.5 + wDA)T – 10
(0.5 + wRP)T – 5
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
RAS hold time
tRSH
tRAL
Column address read time
(to RAS↑)
CAS to RAS precharge time
CAS hold time
<66>
<67>
<76>
tCRP
tCSH
tRAD
(1 + wRP)T – 10
(1.5 + wRH + wDA)T – 10
(0.5 + wRH)T – 10
ns
ns
ns
Delay time from RAS to column
address
RAS to CAS delay time
<77>
<81>
<83>
<85>
<87>
<88>
tRCD
tCP
(1 + wRH)T – 10
(0.5 + wCP)T – 5
ns
ns
ns
ns
ns
ns
CAS precharge time
RAS hold time for CAS precharge
WE hold time (from CAS↓)
Data hold time (from CAS↓)
tRHCP
tWCH
tDH
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
(0.5 + wDA)T – 10
(1.5 + twDA)T – 10
WE read time (to
On-page
On-page
On-page
tRWL
wCP = 0
wCP = 0
wCP = 0
RAS↑)
WE read time (to
<89>
tCWL
(0.5 + wDA)T – 10
ns
CAS↑)
WE pulse width
Write cycle time
RAS pulse width
CAS pulse width
<92>
<93>
tWP
tHPC
(1 + wDA)T – 10
(1 + wDA + wCP)T – 10
(2.5 + wRH + wDA)T – 10
(0.5 + wDA)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
<94>
tRASP
tHCAS
tWCS1
tWCS2
tDS1
<95>
WE setup time
Off-page
On-page
Off-page
On-page
<101>
<102>
<103>
<104>
(1 + wRP + wRH)T – 10
wCPT – 10
(to CAS↓)
wCP ≥ 1
Data setup time
(1.5 + wRP + wRH)T – 10
(0.5 + wCP)T – 10
(to CAS↓)
tDS2
Remarks 1. T = tCYK
2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
58
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (output)
<58>
<57>
<56>
<59>
<58>
<59>
A0 to A23 (output)
RASn (output)
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<67>
<77>
<83>
<66>
<95>
<89>
<81>
<63>
UCAS (output)
LCAS (output)
<93>
<88>
<95>
RD (output)
OE (output)
<102>
<85>
<101>
<85>
<92>
WE (output)
D0 to D15 (I/O)
BCYST (output)
WAIT (input)
<103>
<87>
<104>
<87>
Data
Data
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
59
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
<24> tSWK
<25> tHKW
Conditions
MIN.
MAX.
Unit
ns
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
10
2
ns
Delay time from OE↑ to data output <37>
Delay time from address to IOWR↓ <41>
tDRDOD
tDAWR
tSAWR
(0.5 + i)T – 10
(0.5 + wRP)T – 5
ns
ns
Address setup time (to IOWR↑)
<42>
(2 + wRP + wRH + wDA +
ns
w)T –10
Delay time from IOWR↑ to address <43>
tDWRA
0.5T – 5
0
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from IOWR↑ to RD↑
<48>
tDWRRD
wF = 0
wF = 1
T – 10
IOWR low-level width
<50>
<56>
<57>
<58>
<59>
tWWRL
tASR
tRAH
tASC
tCAH
(2 + wRH + wDA + w)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address setup time
Row address hold time
Column address setup time
Column address hold time
(1.5 + wDA + wF + w)T
– 10
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA
ns
+ wF + w)T – 10
RAS precharge time
RAS hold time
<61>
<63>
tRP
(0.5 + wRP)T – 5
ns
ns
tRSH
(1.5 + wDA + wF + w)T
– 10
Column address read time for RAS <64>
tRAL
(2 + wCP + wDA + wF +
ns
w)T – 10
CAS pulse width
<65>
<66>
<67>
tCAS
tCRP
tCSH
(1 + wDA + wF + w)T – 10
(1 + wRP)T –10
ns
ns
ns
CAS to RAS precharge time
CAS hold time
(2 + wRH + wDA + wF +
w)T – 10
WE setup time (to CAS↓)
WE hold time (from RAS↑)
WE hold time (from CAS↑)
CAS precharge time
<68>
<69>
<70>
<71>
<76>
tRCS
tRRH
tRCH
tCPN
tRAD
(2 + wRP + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
ns
1.5T – 10
(2 + wRP + wRH)T – 5
(0.5 + wRH)T – 10
Delay time from RAS to column
address
RAS to CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
7. wF: Number of waits inserted to source-side access during DMA flyby transfer
8. i: Number of idle states inserted when a write cycle follows the read cycle.
60
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3)
Parameter
Symbol
<78> tOEZ
Conditions
MIN.
0
MAX.
Unit
ns
Output buffer turn-off delay time
(from OE↑)
Output buffer turn-off delay time
<79>
tOFF
0
ns
(from CAS↑)
CAS precharge time
<81>
<82>
tCP
tPC
(0.5 + wCP)T – 5
ns
ns
High-speed mode cycle time
(2 + wCP + wDA + wF +
w)T – 10
RAS hold time for CAS precharge
RAS pulse width
<83>
<94>
<96>
<97>
tRHCP
tRASP
tOCH1
tOCH2
(2.5 + wCP + wDA + wF +
ns
ns
ns
ns
w)T – 10
(2.5 + wRH + wDA + wF +
w)T – 10
CAS hold time
from OE
Off-page
On-page
(2.5 + wRP + wRH +
wDA + wF + w)T – 10
(from CAS↑)
(1.5 + wCP + wDA + wF +
w)T – 10
Delay time from DMAAKm↓ to CAS↓ <105> tDDACS
(1.5 + wRH)T – 10
(1 + wRH)T – 10
ns
ns
Delay time from IOWR↓ to CAS↓
<106> tDRDCS
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
7. wF: Number of waits inserted to source-side access during DMA flyby transfer
8. m = 0 to 3
61
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW T1 TRHW T2 TDAW TW
T3 TCPW TO1 TDAW TW TO2
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<58>
<57>
<56>
<59>
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<60>
<69>
<77>
<65>
<83>
<63>
<66>
<67>
<81>
UCAS (output)
LCAS (output)
<70>
<71>
<82>
<96>
<79>
RD (output)
OE (output)
<105>
<48>
<97>
DMAAKm (output)
WE (output)
<68>
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
<106>
<42>
<43>
<78>
<37>
<41>
<50>
<24>
Data
Data
<25>
<24>
<24>
<25>
<25>
BCYST (output)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
Number of waits inserted to source-side access during DMA flyby transfer: 0
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
62
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
WAIT setup time (to CLKOUT↓)
WAIT hold time (from CLKOUT↓)
IORD low-level width
Symbol
<24>
Conditions
MIN.
10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tWRDL
tWRDH
tDARD
tDRDA
tASR
tRAH
tASC
tCAH
tRC
<25>
<32>
<33>
<34>
<35>
<56>
<57>
<58>
<59>
<60>
<61>
<63>
<64>
<65>
<66>
<67>
<71>
<76>
2
(2 + wRH + wDA + wF + w)T – 10
T – 10
IORD high-level width
Delay time from address to IORD↑
Delay time from IORD↑ to address
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
0.5T – 5
(0.5 + i)T – 5
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
(1.5 + wDA + wF)T – 10
(3 + wRP + wRH + wDA + wF + w)T – 10
(0.5 + wRP)T – 5
RAS precharge time
tRP
RAS hold time
tRSH
tRAL
(1.5 + wDA + wF)T – 10
(2 + wCP + wDA + wF + w)T – 10
(1 + wDA + wF)T – 10
(1 + wRP)T – 10
Column address read time for RAS
CAS pulse width
tCAS
tCRP
tCSH
tCPN
tRAD
CAS to RAS precharge time
CAS hold time
(2 + wRH + wDA + wF + w)T – 10
(2 + wRP + wRH + w)T – 5
(0.5 + wRH)T – 10
CAS precharge time
Delay time from RAS to column
address
RAS to CAS delay time
CAS precharge time
<77>
<81>
<82>
<83>
<85>
<88>
<89>
<92>
<94>
tRCD
tCP
(1 + wRH + w)T – 10
(0.5 + wCP + w)T – 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
High-speed page mode cycle time
RAS hold time for CAS precharge
WE hold time (from CAS↓)
WE read time (to RAS↑)
WE read time (to CAS↑)
WE pulse width
tPC
(2 + wCP + wDA + wF + w)T – 10
(2.5 + wCP + wDA + w)T – 10
(1 + wDA )T – 10
tRHCP
tWCH
tRWL
tCWL
tWP
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wDA + w)T – 10
RAS pulse width
tRASP
(2.5 + wRH + wDA + wF + w)T – 10
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
7. wF: Number of waits inserted to source-side access during DMA flyby transfer.
8. i: Number of idle states inserted when a write cycle follows the read cycle.
9. n = 0 to 7
63
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
Symbol
<101> tWCS1
<102> tWCS2
Conditions
wCP = 0
MIN.
(1 + wRH + wRP + w)T – 10
wCPT – 10
MAX.
Unit
ns
ns
ns
ns
ns
ns
WE setup time
(to CAS↓)
Off-page
On-page
wCP ≥ 1
Delay time from DMAAKm↓ to CAS↓ <105>
tDDACS
tDRDCS
tDWERD
(1.5 + wRH + w)T – 10
(1 + wRH + w)T – 10
0
Delay time from IORD↓ to CAS↓
Delay time from WE↑ to IORD↑
<106>
<107>
wF = 0
wF = 1
T – 10
Remarks 1. T = tCYK
2. w: Number of waits due to WAIT
3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
4. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13)
6. m = 0 to 3
64
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW T1 TRHW TW
T2 TDAW T3 TCPW TW TO1 TDAW TO2
CLKOUT (output)
A0 to A23 (output)
RASn (output)
<56>
<57>
<58>
<59>
Row address
<76>
<61>
Column address
Column address
<64>
<94>
<60>
<77>
<65>
<66>
<67>
<81>
<63>
UCAS (output)
LCAS (output)
<71>
<82>
<83>
RD (output)
OE (output)
<102>
<88>
<89>
<101>
<105>
<85>
WE (output)
DMAAKm (output)
IOWR (output)
IORD (output)
<92>
<106>
<107>
<35>
<34>
<32>
<24>
<25>
<33>
Data
D0 to D15 (I/O)
WAIT (input)
Data
<24>
<24>
<25>
<25>
BCYST (output)
Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13):
Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1
Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1
Number of waits (TDAW) specified by DACxx bit of register DRCn: 1
Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1
Number of waits inserted to source-side access during DMA flyby transfer: 0
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
65
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(i) CBR refresh timing
Parameter
RAS precharge time
RAS pulse width
Symbol
Conditions
MIN.
MAX.
Unit
ns
<61>
tRP
tRAS
tCHR
tWRFL
(1.5 + wRRW)T – 5
(1.5 + wRCW Note)T – 10
(1.5 + wRCW Note)T – 10
<62>
<108>
<109>
ns
CAS hold time
ns
REFRQ pulse width
(3 +wRRW + wRCW Note)T
ns
– 10
RAS precharge CAS hold time
<110>
<111>
tRPC
(0.5 + wRRW)T – 10
ns
ns
REFRQ active delay time
tDKRF
2
10
10
(from CLKOUT↓)
REFRQ inactive delay time
<112>
<113>
tHKRF
2
ns
ns
(from CLKOUT↓)
CAS setup time
tCSR
T – 10
Note wRCW is inserted for at least 1 clock, regardless of the setting of bits RCW0 to RCW2 of register RWC.
Remarks 1. T = tCYK
2. wRRW: Number of waits specified by bits RRW0 and RRW1 of register RWC
3. wRCW: Number of waits specified by bits RCW0 to RCW2 of register RWC.
TRRW
T1
T2
TRCWNote
TRCW
T3
TI
CLKOUT (output)
REFRQ (output)
RASn (output)
<111>
<112>
<109>
<61>
<62>
<110>
<110>
<113>
<108>
UCAS (output)
LCAS (output)
Note This TRCW is always inserted, regardless of the setting of bits RCW0 to RCW2 of register RWC.
Remarks 1. These timings are for the following cases:
Number of waits specified by bits RRW0 and RRW1 of register RWC (TRRW): 1
Number of waits specified by bits RCW0 to RCW2 of register RWC (TRCW): 2
2. n = 0 to 7
66
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(j) CBR self refresh timing
Parameter
Symbol
<111> tDKRF
Conditions
MIN.
2
MAX.
10
Unit
ns
REFRQ active delay time
(from CLKOUT↓)
REFRQ inactive delay time
<112>
tHKRF
2
10
ns
(from CLKOUT↓)
CAS hold time
<114>
<115>
tCHS
tRPS
–5
ns
ns
RAS precharge time
(1 + 2wSRW)T – 10
Remarks 1. T = tCYK
2. wSRW: Number of waits specified by bits SRW0 to SRW2 of register RWC.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (output)
REFRQ (output)
RASn (output)
<111>
<112>
<115>
<114>
UCAS (output)
LCAS (output)
Output signals
other than above
Remarks 1. These timings are for the following cases:
Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1
Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 1
Number of waits (TSRW) specified by bits SRW0 to SRW2 of register RWC: 2
2. Broken lines indicate high impedance.
3. n = 0 to 7
67
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(7) DMAC timing
Parameter
Symbol
Conditions
MIN.
10
MAX.
Unit
ns
DMARQn setup time
<116>
tSDRK
(to CLKOUT↑)
DMARQn hold time
<117>
<118>
<119>
tHKDR1
tHKDR2
tDKDA
2
ns
ns
ns
(from CLKOUT↑)
Until DMAAKn↓
DMAAKn output delay time
2
10
10
10
10
(from CLKOUT↓)
DMAAKn output hold time
<120>
<121>
<122>
tHKDA
tDKTC
tHKTC
2
2
2
ns
ns
ns
(from CLKOUT↓)
TCn output delay time
(from CLKOUT↓)
TCn output hold time
(from CLKOUT↓)
Remark n = 0 to 3
CLKOUT (output)
<117>
<116>
<118>
DMARQn (input)
DMAAKn (output)
<116>
<119>
<120>
<122>
<121>
TCn (output)
Remark n = 0 to 3
68
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
[MEMO]
69
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(8) Bus hold timing (1/2)
Parameter
Symbol
<123>
<124>
Conditions
MIN.
10
MAX.
10
Unit
ns
ns
ns
ns
ns
ns
HLDRQ setup time (to CLKOUT↑)
HLDRQ hold time (from CLKOUT↑)
tSHRK
tHKHR
tDKHA
tWHQH
tWHAL
tDKCF
5
Delay time from CLKOUT↓ to HLDAK <125>
2
HLDRQ high-level width
HLDAK low-level width
<126>
<127>
<128>
T + 17
T – 8
Delay time from CLKOUT↓ to bus
10
float
Delay time from HLDAK↑ to bus
<129>
tDHAC
0
ns
output
Delay time from HLDRQ↓ to HLDAK↓ <130>
Delay time from HLDRQ↑ to HLDAK↑ <131>
tDHQHA1
tDHQHA2
2.5T
0.5T
ns
ns
1.5T
Remark T = tCYK
70
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
HLDRQ (input)
HLDAK (output)
A0 to A23 (output)
D0 to D15 (I/O)
CSn/RASn (output)
BCYST (output)
RD (output)
<125>
<128>
<125>
<131>
<130>
<127>
<129>
Address
Undefined
Data
WE (output)
UCAS (output)
LCAS (output)
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 7
71
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(9) Interrupt timing
Parameter
NMI high-level width
NMI low-level width
Symbol
Conditions
MIN.
500
MAX.
Unit
ns
<132>
tWNIH
tWNIL
tWITH
tWITL
<133>
<134>
<135>
500
ns
INTPn high-level width
INTPn low-level width
4T + 10
4T + 10
ns
ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153
2. T = tCYK
<132>
<134>
<133>
NMI (input)
<135>
INTPn (input)
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153
(10) RPU timing
Parameter
TI1n high-level width
TI1n low-level width
Symbol
Conditions
MIN.
MAX.
Unit
ns
<136> tWTIH
<137> tWTIL
<138> tWTCH
<139> tWTCL
3T + 18
3T + 18
3T + 18
3T + 18
ns
TCLR1n high-level width
TCLR1n low-level width
ns
ns
Remarks 1. n = 0 to 5
2. T = tCYK
<136>
<137>
<139>
TI1n (input)
<138>
TCLR1n (input)
Remark n = 0 to 5
72
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(11) UART0, UART1 timing (synchronized with clock, master mode only)
Parameter
Symbol
<140>
Conditions
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
tCYSK0
tWSK0H
tWSK0L
tSRXSK
tHSKRX
tDSKTX
tHSKTX
250
SCKn high-level width
<141>
<142>
<143>
<144>
Output
0.5tCYSK0 – 20
SCKn low-level width
Output
0.5tCYSK0 – 20
RXDn setup time (to SCKn↑)
RXDn hold time (from SCKn↑)
30
0
TXDn output delay time (from SCKn↓) <145>
20
TXDn output hold time (from SCKn↑)
<146>
0.5tCYSK0 – 5
Remark n = 0, 1
<140>
<142>
<141>
SCKn (output)
RXDn (input)
TXDn (output)
<143>
<144>
Input data
<145>
<146>
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0, 1
73
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
SCKn cycle
Symbol
Conditions
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<147>
tCYSK1
tWSK1H
tWSK1L
tSSISK
100
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
<148>
<149>
<150>
<151>
Output
0.5tCYSK1 – 20
Output
0.5tCYSK1 – 20
30
0
tHSKSI
tDSKSO
tHSKSO
SOn output delay time (from SCKn↓) <152>
20
SOn output hold time (from SCKn↑)
<153>
0.5tCYSK1 – 5
Remark n = 0 to 3
(b) Slave mode
Parameter
SCKn cycle
Symbol
Conditions
Input
MIN.
100
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
<147>
<148>
<149>
<150>
<151>
tCYSK1
tWSK1H
tWSK1L
tSSISK
SCKn high-level width
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
Input
Input
30
10
tHSKSI
tDSKSO
tHSKSO
10
SOn output delay time (from SCKn↓) <152>
30
SOn output hold time (from SCKn↑)
<153>
tWSK1H
Remark n = 0 to 3
<147>
<149>
<148>
SCKn (I/O)
Sln (input)
<150>
<151>
Input data
<152>
<153>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 3
74
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
A/D Converter Characteristics
(TA = –40 to +85°C, VDD = HVDD = CVDD = AVDD = AVREF = 3.0 to 3.6 V, VSS = CVSS = AVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Resolution
–
–
Overall error
5
1/2
10
LSB
LSB
µs
Quantization error
Conversion time
Sampling time
–
tCONV
tSAMP
5
Conversion
clockNote 1/6
ns
Zero scale error
Scale error
–
–
5
LSB
LSB
LSB
V
5
3
Linearity error
–
Analog input voltage
Analog input resistance
AVREF input voltage
AVREF input current
AVDD current
VIAN
RAN
AVREF
AIREF
AIDD
–0.3
AVREF + 0.3
1.0
MΩ
V
Note 2
Note 3
3.0
3.6
2.0
5.0
mA
mA
Notes 1. The conversion clock is the number of clocks converted via the ADM1 register.
2. Except in IDLE/software STOP mode
3. The current always flows regardless of the A/D converter operating status or standby mode. To further
reduce the power consumption in IDLE/software STOP mode, make the voltage of the AVREF pin the
same potential as VSS.
75
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
4.2 Flash Memory Programming Mode
Basic Characteristics
(TA = –40 to +85°C (Other Than When Rewriting), VDD = AVDD = 3.0 to 3.6 V, VSS = AVSS = 0 V) (1/2)
Parameter
Operating frequency
VPP power supply voltage
Symbol
fX
Conditions
MIN.
20
TYP.
7.8
MAX.
33
Unit
MHz
V
VPP1
During flash memory
programming
7.5
8.1
VPPL
VPPM
VPPH
VPP low-level detection
VPP, VDD level detection
0.8 VDD
0.65 VDD
7.5
1.2 VDD
VDD +0.3
8.1
V
V
V
VDD
7.8
VPP high-voltage level
detection
Power supply current
VPP supply current
Step erase time
IDD
IPP
tER
VPP = VPP1
2.7 × fX
4.5 × fX
mA
mA
s
VPP = 8.1 V
150
K, P rankNote 1
5
(Recommendation:
Step erase = 5 s)
M rankNote 1
0.2
s
(Recommendation:
Step erase = 0.2 s)
Total erase time
tERA
K, P rankNote 1
When step erase time =
5 s, Note 2
60
20
s
s
M rankNote 1
When step erase time =
0.2 s, Note 2
Writeback time
tWB
Note 3, K, P rankNote 1
19.99
0.99
20
1
20.01
1.01
10
ms
ms
M rankNote 1
Number of writebacks per
writeback command
CWB
K, P rankNote 1
When writeback time =
20 ms, Note 4
Times/
write-back
command
M rankNote 1
When writeback time =
1 ms, Note 4
60
16
Number of erases – writebacks
CERWB
Times
Notes 1. The rank is indicated by the fifth letter from the left of the lot number.
2. The prewrite time prior to erase and the erase verify time (writeback time) are not included.
3. The recommended set value for the writeback time is 1 ms (M rank) or 20 ms (K, P rank).
4. When the writeback command is issued, writeback is performed once. Therefore, set the retry count
setting value to a value that is this value minus the number of command issuances.
Caution The I rank applies to engineering samples only. The number of rewrites is not guaranteed for I
rank products.
Remark When the PG-FP3 or PG-FP4 is used, the time parameters required for write/erase are automatically
set by downloading the parameter file. Do not change the set values unless otherwise specified.
76
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Basic Characteristics
(TA = –40 to +85°C (Other Than When Rewriting), VDD = AVDD = 3.0 to 3.6 V, VSS = AVSS = 0 V) (2/2)
Parameter
Symbol
tWT
Conditions
MIN.
18
TYP.
20
MAX.
22
Unit
Step write time
Note 1
µs
Total write time per
word
tWTW
Step write time is set to 20 µs
(1 word = 4 bytes), Note 2
20
200
µs
/word
Number of rewrites
CERWR
One erase +
one write after
erase are taken
as one rewrite,
Note 3
K rankNote 4
5
Times
Times
Times
Times
°C
P rankNote 4
10
M rankNotes 4, 5
M rankNotes 4, 6
20
100
Temperature during
write
TPRG
K, P rankNote 4
M rankNote 4
10
10
40
85
°C
Notes 1. The recommended set value for the step write time is 20 µs.
2. The actual write time per word is longer than this value by 100 µs. This value does not include the
internal verify time during and after writing.
3. When a shipped product is written for the first time, both “write after erase” and “write only” are taken
as one write.
Example (P: write, E: erase)
Product
Product
→
→
P
P
→
→
E
E
→
→
P
P
→
→
E
E
→
→
P
P
Three rewrites
Three rewrites
→
E
4. The rank is indicated by the fifth letter from the left of the lot number.
5. Lot number 0120Mxxxx or earlier
6. Lot number 0121Mxxxx or later
Caution The I rank applies to engineering samples only. The number of rewrites is not guaranteed for I
rank products.
Remarks 1. When the PG-FP3 or PG-FP4 is used, the time parameters required for write/erase are
automatically set by downloading the parameter file. Do not change the set values unless specified.
2. In the lot number, the two digits from the left (“01” in Notes 5, 6) indicate the lower 2 digits of the
manufacture year and the 3rd and 4th digits from the left (“20” in Note 5 and “21” in Note 6) indicate
the week of manufacture.
For example, Note 6 corresponds to products manufactured in 21th week or later (21, 22, 23…) in
2001.
77
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Serial Write Operation Characteristics
Parameter
Symbol
Conditions
VPP = 7.8 V
MIN.
200
TYP.
MAX.
Unit
ns
Set time from VDD↑ to VPP↑
Set time from VPP↑ to RESET↑
RESET↑ to VPP count start time
Count execution time
<201>
<202>
<203>
<204>
<205>
<206>
<207>
<208>
tDRPSR
tPSRRF
tRFOF
tCOUNT
tCH
1
µs
µs
ms
µs
µs
µs
µs
5T + 500
10
VPP counter high-level width
VPP counter low-level width
VPP counter rise time
1
1
tCL
tR
3
3
VPP counter fall time
tF
VDD, HVDD
VDD, HVDD
0 V
<204>
<203>
<201>
<206>
<205>
<207>
VPPH
VPP
VDD
<208>
0 V
<202>
HVDD
0 V
RESET (input)
78
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
5. PACKAGE DRAWINGS
157-PIN PLASTIC FBGA (14x14)
B
D
w
S B
D1
SD
ZD
16
15
14
13
12
11
10
9
ZE
A
E1
E
8
7
6
5
SE
4
3
2
1
TRPNMLKJHGFEDCBA
INDEX MARK
w
S A
4-R0.3
4-C1.0
25°
A
y1
S
A2
S
y
S
e
A1
M
157-
φ
b
φ
x
S A B
ITEM MILLIMETERS
14.0 0.1
13.4
D
D1
E
14.0 0.1
13.4
E1
w
0.20
e
0.8
1.31 0.15
0.35 0.10
0.96
A
A1
A2
+0.05
0.5
b
−0.10
x
0.08
y
0.10
0.2
y1
SD
SE
ZD
ZE
0.4
0.4
1.0
1.0
S157F1-80-FA1
79
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
M
G
H
I
J
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
22.0 0.2
20.0 0.2
20.0 0.2
22.0 0.2
1.25
G
1.25
+0.05
0.22
H
−0.04
I
J
0.10
0.5 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.055
M
0.145
−0.045
N
P
Q
0.10
1.4 0.1
0.125 0.075
+7°
3°
R
S
−3°
1.7 MAX.
S144GJ-50-8EU-3
80
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
M
G
H
J
I
K
P
S
L
S
N
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
20.0 0.2
22.0 0.2
1.25
G
H
1.25
0.22 0.05
I
0.08
J
0.5 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.4
0.10 0.05
+4°
3°
R
S
−3°
1.5 0.1
S144GJ-50-UEN
81
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
6. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Caution The soldering conditions of the µPD70F3102AGJ-33-UEN are yet to be determined.
Table 6-1. Surface Mounting Type Soldering Conditions
(1) µPD70F3102AF1-33-FA1: 157-pin plastic FBGA (14 × 14)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended Condition Symbol
IR30-103-2
Package peak temperature: 230°C, Time: 30 seconds max. (at
210°C or higher), Count: Twice or less, Exposure limit: 3 daysNote
(after that, prebake at 125°C for 10 hours)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
(2) µPD70F3102AGJ-33-8EU: 144-pin plastic LQFP (Fine Pitch) (20 × 20)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended Condition Symbol
IR35-103-2
Package peak temperature: 235°C, Time: 30 seconds max. (at
210°C or higher), Count: Twice or less, Exposure limit: 3 daysNote
(after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: Within 25 to 40 seconds
(at 200°C or higher), Count: Twice or less, Exposure limit: 3 daysNote
(after that, prebake at 125°C for 10 hours)
VP15-103-2
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
82
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
APPENDIX NOTES ON DESIGNING TARGET SYSTEM
The following shows the connection condition diagrams between in-circuit emulator optional board and conversion
connector.
Side View
In-circuit emulator
optional board
IE-703102-MC-EM1 (for 5 V)
IE-703102-MC-EM1-A (for 3.3 V)
In-circuit emulator
IE-703102-MC
Conversion connector
191.5 mm
YQGUIDE
YQPACK144SD
Note
NQPACK144SD
Target system
Note YQSOCKET144SDN (separately available) can be inserted here to adjust the height (height: 3.2 mm).
Top View
IE-703102-MC
Target system
Position of pin 1
IE-703102-MC-EM1 (for 5 V)
IE-703102-MC-EM1-A (for 3.3 V)
YQPACK144SD, NQPACK144SD,
YQGUIDE
Connection Condition Diagram
IE-703102-MC-EM1 (for 5 V)
IE-703102-MC-EM1-A (for 3.3 V)
Connected to
IE-703102-MC
Position of pin 1
75 mm
YQGUIDE
YQPACK144SD
NQPACK144SD
13.3 mm
31.84 mm
19.74 mm
Target system
21.58 mm
27.0 mm
The following shows the conversion connector for the 157-pin FBGA package.
83
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
157-pin conversion connector for FBGA package
(CSPACK157A1614N01 + CSICE157A1614N01)
29.0
6.4
15.4
Remarks 1. The target device of the 157-pin conversion connector for FBGA package is V850E/MS1 only.
2. Unit: mm
84
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
[MEMO]
85
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related Documents µPD70F3102-33 Data Sheet (U13844E)
µPD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet (U13995E)
µPD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E)
The related documents in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
The V850E/MS1 and V850E/MS2 are trademarks of NEC Corporation.
86
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-244 58 45
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 040-244 45 80
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 11-6462-6829
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 021-6841-1137
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Fax: 0211-65 03 327
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Sucursal en España
Madrid, Spain
Fax: 02-2719-5951
Tel: 091-504 27 87
Fax: 091-504 28 60
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 250-3583
Fax: 01-30-67 58 99
J02.4
87
Data Sheet U13845EJ5V0DS
µPD70F3102A-33
•
The information in this document is current as of June, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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