UPD70F3235M1GC(A2)-8EA [NEC]
RISC Microcontroller, 32-Bit, FLASH, 20MHz, CMOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, LQFP-100;
| 型号： | UPD70F3235M1GC(A2)-8EA |
| 厂家： | 
NEC |
| 描述： | RISC Microcontroller, 32-Bit, FLASH, 20MHz, CMOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, LQFP-100 微控制器 |
| 文件： | 总941页 (文件大小：3907K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
V850ES/Fx2
32-Bit Single-Chip Microcontroller
Hardware
µPD703230(A)
µPD703230(A1)
µPD703230(A2)
µPD70(F)3231(A)
µPD70(F)3231(A1)
µPD70(F)3231(A2)
µPD70(F)3232(A) µPD70(F)3233(A)
µPD70(F)3232(A1) µPD70(F)3233(A1)
µPD70(F)3232(A2) µPD70(F)3233(A2)
µPD70(F)3234(A) µPD70(F)3235(A) µPD70F3236(A)
µPD70(F)3234(A1) µPD70(F)3235(A1) µPD70F3236(A1)
µPD70(F)3234(A2) µPD70(F)3235(A2) µPD70F3236(A2)
µPD70F3237(A)
µPD70F3238(A)
µPD70F3239(A)
µPD70F3237(A1) µPD70F3238(A1) µPD70F3239(A1)
µPD70F3237(A2) µPD70F3238(A2) µPD70F3239(A2)
Document No. U17830EE1V0UM00
Date Published November 2005-NS CP(K)
2005
Printed in Europe
[MEMO]
2
User’s Manual U17830EE1V0UM00
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
INPUT OF SIGNAL DURING POWER OFF STATE
5
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
User’s Manual U17830EE1V0UM00
•
The information in this document is current as of November, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
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(Note)
(1)
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majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U17830EE1V0UM00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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http://www.necel.com/en/support/support.html
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J04.1
5
User’s Manual U17830EE1V0UM00
PREFACE
Readers
For the whole document it shall be agreed that V850ES/Fx2 stands for V850ES/FE2,
V850ES/FF2, V850ES/FG2 and V850ES/FJ2.
This manual is intended for users who wish to understand the functions of the
V850ES/Fx2 and design application systems using these products.
The target products are as follows.
Purpose
This manual is intended to give users an understanding of the hardware functions of the
V850ES/Fx2 shown in the Organization below.
Organization
This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES
Architecture User’s Manual).
Hardware
Architecture
• Data types
• Pin functions
• CPU function
• Register set
• On-chip peripheral functions
• Flash memory programming
• Instruction format and instruction set
• Interrupts and exceptions
• Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the details of an instruction function
→ Refer to the V850ES Architecture User’s Manual.
Register format
→
The name of the bit whose number is in angle brackets (< >) in the figure of the
register format of each register is defined as a reserved word in the device file.
Regarding the pin functions and Internal peripheral functions of products, please
read and change the products as follows.
→
→
→
→
→
→
→
→
→
→
→
・µ PD703230 → µ PD703230(A), µ PD703230(A1), µ PD703230(A2)
・µ PD70F3231 → µ PD70(F)3231(A), µ PD70(F)3231(A1), µ PD70(F)3231(A2)
・µ PD70F3232 → µ PD70(F)3232(A), µ PD70(F)3232(A1), µ PD70(F)3232(A2)
・µ PD70F3233 → µ PD70(F)3233(A), µ PD70(F)3233(A1), µ PD70(F)3233(A2)
・µ PD70F3234 → µ PD70(F)3234(A), µ PD70(F)3235(A1), µ PD70(F)3234(A2)
・µ PD70F3235 → µ PD70(F)3235(A), µ PD70(F)3235(A1), µ PD70(F)3235(A2)
・µ PD70F3236 → µ PD70F3236(A), µ PD70F3236(A1), µ PD70F3236(A2)
・µ PD70F3237 → µ PD70F3237(A), µ PD70F3237(A1), µ PD70F3237(A2)
・µ PD70F3238 → µ PD70F3238(A), µ PD70F3238(A1), µ PD70F3238(A2)
・µ PD70F3239 → µ PD70F3239(A), µ PD70F3239(A1), µ PD70F3239(A2)
To understand the overall functions of the V850ES/Fx2
→ Read this manual according to the CONTENTS. The mark shows major revised
points.
6
User’s Manual U17830EE1V0UM00
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: xxx (over score over pin or signal name)
Memory map address:
Note:
Higher addresses on the top and lower addresses on the bottom
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numeric representation: Binary
Decimal
... xxxx or xxxxB
... xxxx
Hexadecimal
... xxxxH
Prefix indicating power of 2 (address space, memory capacity):
K (kilo):
210 = 1,024
M (mega): 220 = 1,0242
G (giga): 230 = 1,0243
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/Fx2 and sub series (V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2)
Document Name
V850ES Architecture User’s Manual
Document No.
U15943E
V850ES/Fx2 Hardware User’s Manual
V850ES/FE2 Data Sheet
U17830EE1V0UM00
U17834EE1V0DS00
U17832EE1V0DS00
U17833EE1V0DS00
U17831EE1V0DS00
V850ES/FG2 Data Sheet
V850ES/FF2 Data Sheet
V850ES/FJ2 Data Sheet
7
User’s Manual U17830EE1V0UM00
Documents related to development tools (user’s manuals)
Document Name
IE-V850ES-G1 (In-Circuit Emulator)
Document No.
U16313E
IE-703239-G1-EM1 (In-Circuit Emulator Option Board)
SUD-FT-04-0105
U16053E
CA850 Ver. 2.70 C Compiler Package
Operation
C Language
PM plus
U16054E
U16055E
Assembly Language
Operation
U16042E
ID850 Ver. 2.51 Integrated Debugger
RX850 Ver. 3.13 or Later Real-Time OS
U16217E
Fundamental
Installation
Technical
U13430E
U13410E
U13431E
RX850 Pro Ver. 3.15 Real-Time OS
Fundamental
Installation
Technical
U13773E
U13774E
U13772E
RD850 Ver. 3.01 Task Debugger
RD850 Pro Ver. 3.01 Task Debugger
AZ850 Ver. 3.2 System Performance Analyzer
PG-FP4 Flash Memory Programmer
IE-V850E1-CD-NW(N-wire)
U13737E
U13916E
U14410E
U15260E
U16647E
QB-V850ESFX2(IECUBE)
ZUD-BD-04-0085
U16906J
SM plus Ver1.00 System Simulation
8
User’s Manual U17830EE1V0UM00
CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................19
1.1
1.2
1.3
1.4
1.5
1.6
1.7
General .......................................................................................................................................19
Product Development of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2.........20
Features......................................................................................................................................21
Ordering Information ................................................................................................................23
Applications...............................................................................................................................26
Pin Configuration (Top View)...................................................................................................27
Function Block Configuration..................................................................................................33
1.7.1
1.7.2
Internal block diagram...................................................................................................................33
Internal units .................................................................................................................................38
CHAPTER 2 PIN FUNCTIONS................................................................................................................40
2.1
Pin Function List .......................................................................................................................40
2.1.1
2.1.2
2.1.3
2.1.4
V850ES/FE2.................................................................................................................................40
V850ES/FF2 .................................................................................................................................45
V850ES/FG2.................................................................................................................................50
V850ES/FJ2..................................................................................................................................55
2.2
2.3
Pin Status (V850ES/FJ2)...........................................................................................................63
Description of Pin Functions ...................................................................................................64
2.3.1
2.3.2
2.3.3
2.3.4
V850ES/FE2.................................................................................................................................64
V850ES/FF2 .................................................................................................................................71
V850ES/FG2.................................................................................................................................78
V850ES/FJ2..................................................................................................................................84
2.4
2.5
Pin I/O Circuit Types and Recommended Connection of Unused Pins ..............................94
2.4.1
2.4.2
2.4.3
2.4.4
V850ES/FE2.................................................................................................................................94
V850ES/FF2 .................................................................................................................................96
V850ES/FG2.................................................................................................................................98
V850ES/FJ2................................................................................................................................100
Pin I/O Circuits.........................................................................................................................104
CHAPTER 3 CPU FUNCTIONS ............................................................................................................106
3.1
3.2
Features....................................................................................................................................106
CPU Register Set.....................................................................................................................107
3.2.1
3.2.2
Program register set ...................................................................................................................108
System register set .....................................................................................................................109
3.3
3.4
Operation Modes.....................................................................................................................115
Address Space.........................................................................................................................116
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
CPU address space....................................................................................................................116
Image..........................................................................................................................................117
Wraparound of CPU address space ...........................................................................................118
Memory map...............................................................................................................................119
Areas ..........................................................................................................................................121
Recommended use of address space.........................................................................................134
Peripheral I/O registers...............................................................................................................137
Programmable peripheral I/O register.........................................................................................176
Special registers .........................................................................................................................177
3.4.10 Cautions......................................................................................................................................181
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User’s Manual U17830EE1V0UM00
CHAPTER 4 PORT FUNCTIONS......................................................................................................... 184
4.1
4.2
Features................................................................................................................................... 184
Basic Port Configuration ....................................................................................................... 184
4.2.1
4.2.2
4.2.3
4.2.4
Basic port configuration on V850ES/FE2 ....................................................................................184
Port configuration on V850ES/FF2..............................................................................................185
Port configuration on V850ES/FG2.............................................................................................186
Port configuration on V850ES/FJ2..............................................................................................187
4.3
Port Configuration.................................................................................................................. 188
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
Port 0 ..........................................................................................................................................194
Port 1 ..........................................................................................................................................201
Port 3 ..........................................................................................................................................206
Port 4 ..........................................................................................................................................216
Port 5 ..........................................................................................................................................219
Port 6 ..........................................................................................................................................226
Port 7 ..........................................................................................................................................236
Port 8 ..........................................................................................................................................239
Port 9 ..........................................................................................................................................244
4.3.10 Port 12 ........................................................................................................................................257
4.3.11 Port CD .......................................................................................................................................259
4.3.12 Port CM.......................................................................................................................................261
4.3.13 Port CS .......................................................................................................................................265
4.3.14 Port CT........................................................................................................................................269
4.3.15 Port DL........................................................................................................................................273
4.3.16 Port pins that function alternately as on-chip debug function ......................................................278
4.3.17 Register settings to use port pins as alternate-function pins .......................................................279
4.3.18 Operation of port function............................................................................................................286
Cautions .................................................................................................................................. 287
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Cautions of setting port pins........................................................................................................287
Cautions of bit manilulation instruction for port register (Pn).......................................................288
Cautions on on-chip debug pins..................................................................................................288
Cautions on P05/INTP2/DRST pin..............................................................................................288
CHAPTER 5 BUS CONTROL FUNCTION.......................................................................................... 289
5.1
5.2
Features................................................................................................................................... 289
Bus Control Pins..................................................................................................................... 290
5.2.1
5.2.2
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed ..................290
Pin status in each operation mode..............................................................................................290
5.3
5.4
Memory Block Function......................................................................................................... 291
5.3.1
5.3.2
Memory space.............................................................................................................................291
Chip select function.....................................................................................................................292
Bus Access ............................................................................................................................. 293
5.4.1
5.4.2
5.4.3
Number of clocks for access .......................................................................................................293
Bus size setting function .............................................................................................................293
Access according to bus size......................................................................................................294
5.5
Wait Function.......................................................................................................................... 300
5.5.1
5.5.2
5.5.3
Programmable wait function........................................................................................................300
External wait function..................................................................................................................301
Relationship between programmable wait and external wait.......................................................301
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User’s Manual U17830EE1V0UM00
5.5.4
Programmable address wait function..........................................................................................302
5.6
5.7
Idle State Insertion Function..................................................................................................303
Bus Hold Function ..................................................................................................................304
5.7.1
5.7.2
5.7.3
Functional outline........................................................................................................................304
Bus hold procedure.....................................................................................................................305
Operation in power save mode ...................................................................................................305
5.8
5.9
Bus Priority ..............................................................................................................................306
Boundary Operation Conditions............................................................................................306
5.9.1
5.9.2
Program space............................................................................................................................306
Data space..................................................................................................................................306
5.10 Bus Timing...............................................................................................................................307
5.10.1 Multiplexed bus...........................................................................................................................307
CHAPTER 6 CLOCK GENERATION FUNCTION ...............................................................................313
6.1
6.2
6.3
6.4
Overview...................................................................................................................................313
Configuration...........................................................................................................................314
Control Registers ....................................................................................................................316
Operation..................................................................................................................................319
6.4.1
6.4.2
Operation of each clock ..............................................................................................................319
Clock output function ..................................................................................................................320
6.5
PLL Function............................................................................................................................320
6.5.1
6.5.2
6.5.3
Overview.....................................................................................................................................320
Control registers..........................................................................................................................320
Usage .........................................................................................................................................323
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P .............................................................................324
7.1
7.2
7.3
7.4
7.5
Features....................................................................................................................................324
Functional Outline...................................................................................................................324
Configuration...........................................................................................................................325
Control Registers ....................................................................................................................330
Operation..................................................................................................................................339
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
Anytime write and reload ............................................................................................................339
Interval timer mode (TPnMD2 to TPnMD0 = 000).......................................................................344
External event count mode (TPnMD2 to TPnMD0 = 001)...........................................................347
External trigger pulse mode (TPnMD2 to TPnMD0 = 010)..........................................................351
One-shot pulse mode (TPnMD2 to TPnMD0 = 011)...................................................................354
PWM mode (TPnMD2 to TPnMD0 = 100)...................................................................................357
Free-running mode (TPnMD2 to TPnMD0 = 101).......................................................................362
Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) ..................................................367
7.6
7.7
7.8
Timer Synchronized Operation Function..............................................................................369
Selector Function....................................................................................................................373
Cautions ...................................................................................................................................377
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q.............................................................................380
8.1
8.2
8.3
8.4
Features....................................................................................................................................380
Functional Outline...................................................................................................................380
Configuration...........................................................................................................................381
Control Registers ....................................................................................................................388
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User’s Manual U17830EE1V0UM00
8.5
Operation................................................................................................................................. 398
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
Anytime write and reload.............................................................................................................398
Interval timer mode (TQnMD2 to TQnMD0 = 000)......................................................................403
External event count mode (TQnMD2 to TQnMD0 = 001) ..........................................................406
External trigger pulse mode (TQnMD2 to TQnMD0 = 010).........................................................410
One-shot pulse mode (TQnMD2 to TQnMD0 = 011)...................................................................413
PWM mode (TQnMD2 to TQnMD0 = 100)..................................................................................416
Free-running mode (TQnMD2 to TQnMD0 = 101) ...................................................................... 42"
Pulse width measurement mode (TQnMD2 to TQnMD0 = 110)..................................................422
Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111)........................................................431
8.6
8.7
Timer Synchronized Operation Function............................................................................. 433
Cautions .................................................................................................................................. 437
CHAPTER 9 16-BIT INTERVAL TIMER M......................................................................................... 440
9.1
9.2
9.3
9.4
Features................................................................................................................................... 440
Configuration .......................................................................................................................... 441
Control Register...................................................................................................................... 443
Operation................................................................................................................................. 445
9.4.1
Interval timer mode .....................................................................................................................445
9.5
Cautions .................................................................................................................................. 446
CHAPTER 10 WATCH TIMER FUNCTIONS ...................................................................................... 447
10.1 Functions................................................................................................................................. 447
10.2 Configuration .......................................................................................................................... 449
10.3 Control Registers.................................................................................................................... 450
10.4 Operation................................................................................................................................. 452
10.4.1 Operation as watch timer ............................................................................................................452
10.4.2 Operation as interval timer ..........................................................................................................452
10.4.3 Cautions......................................................................................................................................453
10.5 Prescaler 3............................................................................................................................... 454
10.5.1 Control registers..........................................................................................................................454
10.5.2 Generation of watch timer count clock ........................................................................................455
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2................................................................... 456
11.1 Functions................................................................................................................................. 456
11.2 Configuration .......................................................................................................................... 457
11.3 Control Registers.................................................................................................................... 457
CHAPTER 12 A/D CONVERTER ......................................................................................................... 461
12.1 Overview.................................................................................................................................. 461
12.2 Functions................................................................................................................................. 461
12.3 Configuration .......................................................................................................................... 463
12.4 Control Registers.................................................................................................................... 464
12.5 Operation................................................................................................................................. 473
12.5.1 Basic operation ...........................................................................................................................473
12.5.2 Trigger mode...............................................................................................................................475
12.5.3 Operation mode ..........................................................................................................................477
12.5.4 Power-fail compare mode ...........................................................................................................481
12
User’s Manual U17830EE1V0UM00
12.6 Cautions ...................................................................................................................................486
12.7 How to Read A/D Converter Characteristics Table..............................................................491
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)..............................................495
13.1 Features....................................................................................................................................496
13.2 Configuration...........................................................................................................................497
13.2.1 Control registers..........................................................................................................................499
13.3 Control Registers ....................................................................................................................500
13.4 Interrupt Request Signals.......................................................................................................508
13.5 Operation..................................................................................................................................509
13.5.1 Data format.................................................................................................................................509
13.5.2 SBF transmission/reception format.............................................................................................510
13.5.3 SBF transmission........................................................................................................................512
13.5.4 SBF reception.............................................................................................................................513
13.5.5 UART transmission.....................................................................................................................514
13.5.6 Procedure of continuous transmission........................................................................................515
13.5.7 UART reception ..........................................................................................................................517
13.5.8 Reception errors .........................................................................................................................518
13.5.9 Types and operation of parity......................................................................................................520
13.5.10 Noise filter of receive data..........................................................................................................521
13.6 Dedicated Baud Rate Generator............................................................................................522
13.7 Cautions ...................................................................................................................................528
CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB) .........................................................................529
14.1 Features....................................................................................................................................529
14.2 Configuration...........................................................................................................................530
14.3 Control Registers ....................................................................................................................533
14.4 Transfer Data Length Change Function................................................................................538
14.5 Interrupt Request Signals.......................................................................................................539
14.6 Operation..................................................................................................................................540
14.6.1 Single transfer mode (master mode, transmission/reception mode)...........................................540
14.6.2 Single transfer mode (master mode, reception mode)................................................................541
14.6.3 Continuous mode (master mode, transmission/reception mode)................................................542
14.6.4 Continuous mode (master mode, reception mode).....................................................................543
14.6.5 Continuous reception mode (error) .............................................................................................544
14.6.6 Continuous mode (slave mode, transmission/reception mode)...................................................545
14.6.7 Continuous mode (slave mode, reception mode)........................................................................546
14.6.8 Clock timing ................................................................................................................................547
14.7 Output Pins ..............................................................................................................................549
14.8 Operation Flow ........................................................................................................................550
14.9 Prescaler 3 ...............................................................................................................................556
14.9.1 Control registers of prescaler 3...................................................................................................556
14.9.2 Generation of count clock ...........................................................................................................557
14.10 Cautions ...................................................................................................................................558
CHAPTER 15 CAN CONTROLLER......................................................................................................559
15.1 Overview...................................................................................................................................559
15.1.1 Features......................................................................................................................................559
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User’s Manual U17830EE1V0UM00
15.1.2 Overview of Functions.................................................................................................................560
15.1.3 Configuration...............................................................................................................................561
15.2 CAN Protocol .......................................................................................................................... 562
15.2.1 Frame format...............................................................................................................................562
15.2.2 Frame types ................................................................................................................................563
15.2.3 Data frame and remote frame .....................................................................................................563
15.2.4 Error frame..................................................................................................................................571
15.2.5 Overload frame ...........................................................................................................................572
15.3 Functions................................................................................................................................. 573
15.3.1 Determining bus priority ..............................................................................................................573
15.3.2 Bit stuffing ...................................................................................................................................573
15.3.3 Multi masters...............................................................................................................................572
15.3.4 Multi cast.....................................................................................................................................573
15.3.5 CAN sleep mode/CAN stop mode function .................................................................................574
15.3.6 Error control function...................................................................................................................574
15.3.7 Baud rate control function ...........................................................................................................581
15.4 Connection with Target System............................................................................................ 585
15.5 Internal Registers of CAN controller .................................................................................... 586
15.5.1 CAN controller configuration .......................................................................................................586
15.5.2 Register access type...................................................................................................................588
15.5.3 Register bit configuration.............................................................................................................656
15.6 Control Registers.................................................................................................................... 660
15.7 Bit Set/Clear Function ............................................................................................................ 694
15.8 CAN Controller Initialization.................................................................................................. 696
15.8.1 Initialization of CAN module ........................................................................................................696
15.8.2 Initialization of message buffer....................................................................................................696
15.8.3 Redefinition of message buffer....................................................................................................695
15.8.4 Transition from initialization mode to operation mode .................................................................697
15.8.5 Resetting error counter CnERC of CAN module .........................................................................698
15.9 Message Reception................................................................................................................ 699
15.9.1 Message reception......................................................................................................................699
15.9.2 Receive history list function.........................................................................................................700
15.9.3 Mask function..............................................................................................................................702
15.9.4 Multi buffer receive block function...............................................................................................704
15.9.5 Remote frame reception..............................................................................................................705
15.10 Message Transmission.......................................................................................................... 706
15.10.1 Message transmission ................................................................................................................706
15.10.2 Transmit history list function........................................................................................................708
15.10.3 Automatic block transmission (ABT) ...........................................................................................710
15.10.4 Transmission abort process ........................................................................................................712
15.10.5 Remote frame transmission ........................................................................................................712
15.11 Power Saving Modes.............................................................................................................. 713
15.11.1 CAN sleep mode.........................................................................................................................713
15.11.2 CAN stop mode...........................................................................................................................714
15.11.3 Example of using power saving modes.......................................................................................715
15.12 Interrupt Function................................................................................................................... 716
15.13 Diagnosis Functions and Special Operational Modes........................................................ 717
15.13.1 Receive-only mode .....................................................................................................................717
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User’s Manual U17830EE1V0UM00
15.13.2 Single-shot mode........................................................................................................................718
15.13.3 Self-test mode.............................................................................................................................719
15.14 Time Stamp Function..............................................................................................................720
15.14.1 Time stamp function....................................................................................................................720
15.15 Baud Rate Settings .................................................................................................................722
15.15.1 Bit rate setting conditions............................................................................................................722
15.15.2 Representative examples of baud rate settings ..........................................................................726
15.16 Operation of CAN Controller..................................................................................................730
CHAPTER 16 DMA CONTROLLER (DMAC) ......................................................................................755
16.1 Features....................................................................................................................................755
16.2 Configuration...........................................................................................................................756
16.3 Registers ..................................................................................................................................757
16.4 DMA Bus States.......................................................................................................................766
16.4.1 Types of bus states.....................................................................................................................766
16.4.2 DMAC bus cycle state transition .................................................................................................767
16.5 Transfer Targets......................................................................................................................768
16.6 Transfer Modes........................................................................................................................768
16.7 Transfer Types.........................................................................................................................769
16.8 DMA Channel Priorities ..........................................................................................................770
16.9 Time Related to DMA Transfer...............................................................................................770
16.10 DMA Transfer Start Factors....................................................................................................771
16.11 DMA Abort Factors..................................................................................................................772
16.12 End of DMA Transfer...............................................................................................................772
16.13 Operation Timing.....................................................................................................................772
16.14 Cautions ...................................................................................................................................777
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................782
17.1 Features....................................................................................................................................782
17.2 Non-Maskable Interrupts ........................................................................................................787
17.2.1 Non-maskable interrupt request signal .......................................................................................787
17.2.2 Operation....................................................................................................................................789
17.2.3 Restore .......................................................................................................................................790
17.2.4 NP flag........................................................................................................................................792
17.2.5 Eliminating noise on NMI pin.......................................................................................................792
17.2.6 Function to detect edge of NMI pin .............................................................................................792
17.3 Maskable Interrupts ................................................................................................................794
17.3.1 Operation....................................................................................................................................794
17.3.2 Restore .......................................................................................................................................796
17.3.3 Priorities of maskable interrupts..................................................................................................797
17.3.4 Interrupt control registers (xxICn)................................................................................................801
17.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR4, IMR5L) ..............................................................804
17.3.6 In-service priority register (ISPR)................................................................................................806
17.3.7 ID flag .........................................................................................................................................807
17.3.8 Watchdog timer mode register 2 (WDTM2) ................................................................................807
17.3.9 Eliminating noise on INTP0 to INTP7 pins..................................................................................808
17.4 Software Exceptions...............................................................................................................818
17.4.1 Operation....................................................................................................................................818
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User’s Manual U17830EE1V0UM00
17.4.2 Restore .......................................................................................................................................819
17.4.3 EP flag ........................................................................................................................................820
17.5 Exception Trap........................................................................................................................ 821
17.5.1 Illegal opcode definition...............................................................................................................821
17.5.2 Debug trap ..................................................................................................................................823
17.6 Interrupt Acknowledgment Time of CPU ............................................................................. 825
17.7 Periods in Which Interrupts Are Not Acknowledged by CPU............................................ 826
CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 827
18.1 Function................................................................................................................................... 827
18.2 Control Register...................................................................................................................... 828
CHAPTER 19 STANDBY FUNCTION.................................................................................................. 829
19.1 Overview.................................................................................................................................. 829
19.2 HALT Mode.............................................................................................................................. 834
19.2.1 Setting and operation status........................................................................................................834
19.2.2 Releasing HALT mode................................................................................................................834
19.3 IDLE1 Mode ............................................................................................................................. 836
19.3.1 Setting and operation status........................................................................................................836
19.3.2 Releasing IDLE1 mode ...............................................................................................................836
19.4 IDLE2 Mode ............................................................................................................................. 838
19.4.1 Setting and operation status........................................................................................................838
19.4.2 Releasing IDLE2 mode ...............................................................................................................838
19.4.3 Securing setup time after release of IDLE2 mode.......................................................................840
19.5 Software STOP Mode ............................................................................................................. 841
19.5.1 Setting and operation status........................................................................................................841
19.5.2 Releasing software STOP mode.................................................................................................842
19.5.3 Securing setup time after release of software STOP mode.........................................................844
19.6 Subclock Operation Mode ..................................................................................................... 845
19.6.1 Setting and operation status........................................................................................................845
19.6.2 Releasing subclock operation mode............................................................................................845
19.7 Sub-IDLE Mode ....................................................................................................................... 847
19.7.1 Setting and operation status........................................................................................................847
19.7.2 Releasing sub-IDLE mode ..........................................................................................................847
19.8 Control Registers.................................................................................................................... 849
CHAPTER 20 RESET FUNCTION ....................................................................................................... 852
20.1 Overview.................................................................................................................................. 852
20.2 Register to Check Reset Source........................................................................................... 853
20.3 Operation................................................................................................................................. 854
20.3.1 Reset operation by RESET pin ..................................................................................................854
20.3.2 Reset operation by WDT2RES signal .........................................................................................856
CHAPTER 21 CLOCK MONITOR ........................................................................................................ 859
21.1 Function of Clock Monitor..................................................................................................... 859
21.2 Configuration of Clock Monitor............................................................................................. 859
21.3 Register Controlling Clock Monitor...................................................................................... 860
21.4 Operation of Clock Monitor ................................................................................................... 861
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User’s Manual U17830EE1V0UM00
CHAPTER 22 POWER-ON CLEAR CIRCUIT .....................................................................................864
22.1 Functions of Power-on Clear Circuit.....................................................................................864
22.2 Configuration of Power-on Clear Circuit ..............................................................................865
22.3 Operation of Power-on Clear Circuit.....................................................................................865
CHAPTER 23 LOW-VOLTAGE DETECTOR........................................................................................866
23.1 Functions of Low-Voltage Detector.......................................................................................866
23.2 Configuration of Low-Voltage Detector ................................................................................866
23.3 Registers Controlling Low-Voltage Detector .......................................................................867
23.4 Operation of Low-Voltage Detector.......................................................................................870
23.4.1 To use for internal reset signal....................................................................................................870
23.4.2 To use for interrupt......................................................................................................................871
23.5 RAM Retention Voltage Detection Operation.......................................................................872
CHAPTER 24 REGULATOR..................................................................................................................873
24.1 Overview...................................................................................................................................873
24.2 Operation..................................................................................................................................873
CHAPTER 25 FLASH MEMORY...........................................................................................................875
25.1 Features....................................................................................................................................875
25.1.1 Erasure unit ................................................................................................................................876
25.1.2 Functional outline........................................................................................................................877
25.2 Writing with Flash programmer .............................................................................................879
25.3 Programming Environment....................................................................................................879
25.4 Communication Mode.............................................................................................................880
25.5 Pin Connection ........................................................................................................................885
25.5.1 FLMD0 pin ..................................................................................................................................885
25.5.2 FLMD1 pin ..................................................................................................................................886
25.5.3 Serial interface pins ....................................................................................................................886
25.5.4 RESET pin..................................................................................................................................888
25.5.5 Port pins (including NMI).............................................................................................................888
25.5.6 Other signal pins.........................................................................................................................888
25.5.7 Power supply ..............................................................................................................................888
25.6 Programming Method .............................................................................................................889
25.6.1 Flash memory control .................................................................................................................889
25.6.2 Selecting communication mode ..................................................................................................890
25.6.3 Communication commands.........................................................................................................891
25.7 Rewriting by Self-Programming.............................................................................................892
25.7.1 Overview.....................................................................................................................................892
25.7.2 Features......................................................................................................................................893
25.7.3 Standard self-programming flow .................................................................................................894
25.7.4 Flash functions............................................................................................................................895
25.7.5 Pin processing ............................................................................................................................895
25.7.6 Internal resources used ..............................................................................................................896
CHAPTER 26 OPTION FUNCTION ......................................................................................................897
26.1 Mask Options...........................................................................................................................897
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User’s Manual U17830EE1V0UM00
CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT)........................................ 899
27.1 Functional Outline .................................................................................................................. 899
27.1.1 Type of on-chip debug unit..........................................................................................................899
27.1.2 Debug functions ..........................................................................................................................899
27.2 Connection Circuit Example.................................................................................................. 901
27.3 Interface Signals..................................................................................................................... 901
27.4 Register ................................................................................................................................... 903
27.5 Operation................................................................................................................................. 904
27.6 ROM Security Function.......................................................................................................... 906
27.6.1 Security ID ..................................................................................................................................906
27.6.2 Setting.........................................................................................................................................907
27.7 Connection to N-Wire Emulator ............................................................................................ 909
27.7.1 KEL connector.............................................................................................................................909
27.8 Cautions .................................................................................................................................. 913
APPENDIX A REGISTER INDEX ......................................................................................................... 914
APPENDIX B INSTRUCTION SET LIST............................................................................................. 927
B.1 Conventions............................................................................................................................ 927
B.2 Instruction Set (in Alphabetical Order) ................................................................................ 930
B.3 Description of Operating Precautions.................................................................................. 937
APPENDIX C REVISION HISTORY ..................................................................................................... 942
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
The V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 are products of NEC Electronics’ V850 Series of
single-chip microcontrollers for real-time control.
1.1 General
The V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 are 32-bit single-chip microcontroller that include the
V850ES CPU core and integrate peripheral functions such as timers/counters, serial interfaces, and an A/D converter.
These microcontrollers also incorporate a CAN (Controller Area Network) as an automotive LAN.
In addition to highly real-time responsive, 1-clock-pitch basic instructions, this microcontroller have instructions
ideal for digital servo applications, such as multiplication instructions using a hardware multiplier, sum-of-products
operation instructions, and bit manipulation instructions. This microcontroller can also realize a real-time control
system that is highly cost effective and can be used in automotive instrumentation fields.
V850ES/FE2, V850ES/FF2, V850ES/FG2, are models of the V850ES/FJ2 with reduced I/O, timer/counter, and
serial interface functions (See 1.2 Product Development of V850ES/FE2, V850ES/FF2, V850ES/FG2, and
V850ES/FJ2 and Table 1-1. Functional Outline of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2).
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
1.2 Product Development of V850ES/FE2,V850ES/FF2, V850ES/FG2, and V850ES/FJ2
V850ES/FJ2 144-pin plastic LQFP (fine pitch) (20 X 20)
PD70F3239
µ
Flash memory: 512 KB, RAM: 20 KB
Flash memory: 376 KB, RAM: 20 KB
µ
PD70F3238
PD70F3237
Flash memory: 256 KB, RAM: 12 KB
µ
V850ES/FG2 100-pin plastic LQFP (fine pitch) (14 X 14)
µ
PD70F3236
PD70F3235
Flash memory: 384 KB, RAM: 16 KB
µ
Flash memory: 256 KB, RAM: 12 KB
Mask ROM: 256 KB, RAM: 12 KB
Flash memory: 128 KB, RAM: 6 KB
Mask ROM: 128 KB, RAM: 6 KB
PD703235
PD70F3234
PD703234
µ
µ
µ
V850ES/FF2
80-pin plastic TQFP (fine pitch) (12 X 12)
PD70F3233
µ
Flash memory: 256 KB, RAM: 12 KB
Mask ROM: 256 KB, RAM: 12 KB
Flash memory: 128 KB, RAM: 12 KB
Mask ROM: 128 KB, RAM: 6 KB
PD703233
PD70F3232
PD703232
µ
µ
µ
V850ES/FE2
64-pin plastic LQFP (fine pitch) (10 X 10)
PD70F3231
µ
Flash memory: 128 KB, RAM: 6 KB
Mask ROM: 128 KB, RAM: 6 KB
PD703231
PD703230
µ
µ
Mask ROM: 64 KB, RAM: 4 KB
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
1.3 Features
Number of instructions: 83
Minimum instruction execution time: 50 ns (main clock (fXX) = 20 MHz)
General-purpose registers: 32 bits × 32
Power-on clear function
Low-voltage detection function
Ring-OSC: 200 kHz (TYP.)
Internal memory
RAM: 4/6/8/12/16/20 KB (see Table 1-1)
Flash memory: 64/128/256/376/384/512KB (see Table 1-1)
Interrupts/exceptions
Non-maskable interrupts (see Table 1-1)
Maskable interrupts (see Table 1-1)
Software exceptions： 2 sources
Exception trap： 1 sources
I/O lines
I/O ports: 128
Timer/counters
16-bit interval timer M (TMM): 1 ch
16-bit timer/event counter P (TMP): 4 ch
16-bit timer/event counter Q (TMQ): 1 to 3 ch (see Table 1-1)
Watch timer: 1 ch
Watchdog timer 2: 1 ch
Serial interface (SIO)
Asynchronous serial interface A (UART): 2 to 4 (see Table 1-1)
3-wire variable-length serial interface B (CSIB): 2 to 3ch (see Table 1-1)
1 to 4 ch (see Table 1-1)
CAN controller:
A/D converter
Clock generator
10-bit resolution: 10 to 24 ch (see Table 1-1)
Main clock/subclock operation
CPU clock in seven steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode selectable
Internal oscillator: 200 kHz（TYP.）
Power save function HALT/IDLE1/IDLE2/software STOP/subclock/sub-IDLE modes
Package
64-pin plastic LQFP (fine pitch) (10 × 10)
80-pin plastic TQFP (fine pitch) (12 × 12)
100-pin plastic LQFP (fine pitch) (14 × 14)
144-pin plastic LQFP (fine pitch) (20 × 20)
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
Table 1-1. Functional Outline of V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2
Series name
Part number
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
µ
PD70(F)3230
µPD70(F)3231
µ
PD703232
µPD70F3232
PD70(F)3233
µ
PD70(F)3234
µPD70(F)3235
PD70(F)3236
µPD70F)237
µ
PD70(3238
µPD70F3239
Internal
memory
Flash (bytes)
64K
128
K
128
K
256
K
128K
256K
384K
256K
376K
512K
Mask ROM
(bytes)
RAM (bytes)
64K 128K 128K
4K 6K 6K
None
256K
128K
6K
256K
12K
-
-
-
-
12K
12K
16K
12K
20K
20K
DMA
None
Provided
Provided
Operating Main
20 MHz
max.
20 MHz max.
20 MHz max.
20 MHz max.
clock
(internal)
Ring-OSC
200 kHz typ.
200 kHz typ.
RC or crystal
67
200 kHz typ.
RC or crystal
84
200 kHz typ.
RC or crystal
128
Subclock
RC or crystal
51
I/O ports
A/D converter
10 bits × 10
10 bits × 12 ch
10 bits × 16 ch
10 bits × 24 ch
ch
Timers
TMQ
1 ch
1 ch
4 ch
1 ch
1 ch
1 ch
2 ch
2 ch
1 ch
8 ch
35 ch
1 ch
8 ch
2 ch
4 ch
1 ch
1 ch
1 ch
2 ch
3 ch
2 ch
11 ch
50 ch
1 ch
8 ch
3 ch
4 ch
1 ch
1 ch
1 ch
3 ch
TMP
4 ch
1 ch
1 ch
1 ch
2 ch
2 ch
1 ch
8 ch
35 ch
1 ch
8 ch
TMM
WDT2
Watch
CSI
Serial
interfaces
UART
CAN
3 ch
2 ch
4 ch
4 ch
Interrupts
External
Internal
NMI
15 ch
67 ch
1 ch
57 ch
Other
functions
Key return
input
8 ch
Clock monitor
function
POC/LVI
function
Clock output
function
PCL output
function
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
Provided
On-chip
Provided
Provided
Provided
Provided
debug
(Note)
(Note)
(Note)
(Note)
function
External memory interface
None
None
None
Provided
Operating voltage
Package
3.5 V to 5.5
V
64-pin LQFP
3.5 V to 5.5 V
80-pin TQFP
3.5 V to 5.5 V
100-pin LQFP
3.5 V to 5.5 V
144-pin LQFP
Note
On Flash version only (µPD70F323x)
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CHAPTER 1 INTRODUCTION
1.4 Ordering Information
• V850ES/FJ2
Part Number Note
Package
On-Chip Flash CAN Buffer
Memory
Quality Grade
Remark
144-pin plastic
LQFP
256 KB
376 KB
512 KB
32 buffer/ch Special
Without power-on clear
function
µ PD70F3237M1GJ(A)-UEN
µ PD70F3237M1GJ(A1)-UEN
µ PD70F3237M1GJ(A2)-UEN
µ PD70F3237M2GJ(A)-UEN
µ PD70F3237M2GJ(A1)-UEN
µ PD70F3237M2GJ(A2)-UEN
µ PD70F3238M1GJ(A)-UEN
µ PD70F3238M1GJ(A1)-UEN
µ PD70F3238M1GJ(A2)-UEN
µ PD70F3238M2GJ(A)-UEN
µ PD70F3238M2GJ(A1)-UEN
µ PD70F3238M2GJ(A2)-UEN
µ PD70F3239M1GJ(A)-UEN
µ PD70F3239M1GJ(A1)-UEN
µ PD70F3239M1GJ(A2)-UEN
µ PD70F3239M2GJ(A)-UEN
µ PD70F3239M2GJ(A1)-UEN
µ PD70F3239M2GJ(A2)-UEN
(fine pitch)
(20 × 20)
With power-on clear
function
Without power-on clear
function
With power-on clear
function
Without power-on clear
function
With power-on clear
function
Note: The operating ambient temperature of each quality grades is as follows.
(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FG2
Part Number
Package
Internal Memory Number of CAN
Quality
Grade
Remark
Buffers
SpecialNote
−
100-pin plastic LQFP
128 KB
32 buffers/ch
µ PD703234GC(A)-xxx-8EA
µ PD703234GC(A1)-xxx-8EA
µ PD703234GC(A2)-xxx-8EA
µ PD703235GC(A)-xxx-8EA
µ PD703235GC(A1)-xxx-8EA
µ PD703235GC(A2)-xxx-8EA
µ PD70F3234M1GC(A)-8EA
µ PD70F3234M1GC(A1)-8EA
µ PD70F3234M1GC(A2)-8EA
µ PD70F3234M2GC(A)-8EA
µ PD70F3234M2GC(A1)-8EA
µ PD70F3234M2GC(A2)-8EA
µ PD70F3235M1GC(A)-8EA
µ PD70F3235M1GC(A1)-8EA
µ PD70F3235M1GC(A2)-8EA
µ PD70F3235M2GC(A)-8EA
µ PD70F3235M2GC(A1)-8EA
µ PD70F3235M2GC(A2)-8EA
µ PD70F3236M1GC(A)-8EA
µ PD70F3236M1GC(A1)-8EA
µ PD70F3236M1GC(A2)-8EA
µ PD70F3236M2GC(A)-8EA
µ PD70F3236M2GC(A1)-8EA
µ PD70F3236M2GC(A2)-8EA
(fine pitch) (14
×
14)
(Mask ROM)
256 KB
(Mask ROM)
128 KB
Without power-on clear function
With power-on clear function
Without power-on clear function
With power-on clear function
Without power-on clear function
With power-on clear function
(Flash Memory)
256 KB
(Flash Memory)
384 KB
(Flash Memory)
Note: The operating ambient temperature of each quality grades is as follows.
(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃
Remark xxx is ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
24
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FF2
Part Number
Package
Internal Memory Number of CAN
Quality
Grade
Remark
Buffers
SpecialNote
−
80-pin plastic TQFP
128 KB
32 buffers/ch
µ PD703232GK(A)-xxx-9EU
µ PD703232GK(A1)-xxx-9EU
µ PD703232GK(A2)-xxx-9EU
µ PD703233GK(A)-xxx-9EU
µ PD703233GK(A1)-xxx-9EU
µ PD703233GK(A2)-xxx-9EU
µ PD70F3232M1GK(A)-9EU
µ PD70F3232M1GK(A1)-9EU
µ PD70F3232M1GK(A2)-9EU
µ PD70F3232M2GK(A)-9EU
µ PD70F3232M2GK(A1)-9EU
µ PD70F3232M2GK(A2)-9EU
µ PD70F3233M1GK(A)-9EU
µ PD70F3233M1GK(A1)-9EU
µ PD70F3233M1GK(A2)-9EU
µ PD70F3233M2GK(A)-9EU
µ PD70F3233M2GK(A1)-9EU
µ PD70F3233M2GK(A2)-9EU
(fine pitch) (12
×
12)
(Mask ROM)
256 KB
(Mask ROM)
128 KB
Without power-on clear function
With power-on clear function
Without power-on clear function
With power-on clear function
(Flash Memory)
256 KB
(Flash Memory)
Note: The operating ambient temperature of each quality grades is as follows.
(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃
Remark xxx is ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
25
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FE2
Part Number
Package
Internal Memory Number of CAN
Quality
Grade
Remark
Buffers
SpecialNote
−
64-pin plastic LQFP
64 KB
32 buffers/ch
µ PD703230GB(A)-xxx-8EA
µ PD703230GB(A1)-xxx-8EA
µ PD703230GB(A2)-xxx-8EA
µ PD703231GB(A)-xxx-8EA
µ PD703231GB(A1)-xxx-8EA
µ PD703231GB(A2)-xxx-8EA
µ PD70F3231M1GB(A)-8EA
µ PD70F3231M1GB(A1)-8EA
µ PD70F3231M1GB(A2)-8EA
µ PD70F3231M2GB(A)-8EA
µ PD70F3231M2GB(A1)-8EA
µ PD70F3231M2GB(A2)-8EA
(fine pitch) (10
×
10)
(Mask ROM)
128KB
(Mask ROM)
128 KB
Without power-on clear function
With power-on clear function
(Flash Memory)
Note: The operating ambient temperature of each quality grades is as follows.
(A)：－40 to +85℃，(A1)：－40 to +110℃，(A2)：－40 to +125℃
Remark xxx is ROM code number.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
1.5 Applications
Automotive body electrical systems (CAN controller equipped general-purpose products)
26
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
1.6 Pin Configuration (Top View)
• V850ES/FJ2 (µPD70F3237)
144-pin plastic LQFP (fine pitch) (20 × 20)
AVREF0
AVSS
1
108
107
106
105
104
103
102
101
100
99
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BVDD
2
P10/INTP9
P11/INTP10
EVDD
3
4
5
P00/TIP31/TOP31
P01/TIP30/TOP30
FLMD0
6
BVSS
7
PCT7
8
PCT6/ASTB
PCT5
V
DD
9
REGC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PCT4/RD
PCT3
V
SS
98
X1
X2
97
PCT2
96
PCT1/WR1
PCT0/WR0
PCS7
RESET
95
XT1
94
XT2
93
PCS6
P02/NMI
92
PCS5
P03/INTP0/ADTRG
P04/INTP1
91
PCS4
90
PCM5
P05/INTP2/DRST
P06/INTP3
89
PCM4
88
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
P40/SIB0
87
P41/SOB0
86
P42/SCKB0
85
P30/TXDA0
84
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
P36/CTXD1
83
82
81
80
79
PCD2
78
PCD1
P37/CRXD1
77
PCD0
EVSS
76
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P912/SCKB2
EVDD
75
P38/TXDA2
74
P39/RXDA2/INTP8
73
Notes 1
Notes 2
IC: Connect to VSS directly（mask ROM products only ）
FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）
FLMD1: Flash memory versions only
REGC can be connect to VSS via capacitor of 4.7uF
27
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FJ2 (µPD70F3238, µPD70F3239)
144-pin plastic LQFP (fine pitch) (20 × 20)
AVREF0
AVSS
1
108
107
106
105
104
103
102
101
100
99
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BVDD
2
P10/INTP9
P11/INTP10
EVDD
3
4
5
P00/TIP31/TOP31
P01/TIP30/TOP30
FLMD0
6
BVSS
7
PCT7
8
PCT6/ASTB
PCT5
V
DD
9
REGC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PCT4/RD
PCT3
V
SS
98
X1
X2
97
PCT2
96
PCT1/WR1
PCT0/WR0
PCS7
RESET
95
XT1
94
XT2
93
PCS6
P02/NMI
92
PCS5
P03/INTP0/ADTRG
P04/INTP1
91
PCS4
90
PCM5
P05/INTP2/DRST
P06/INTP3
89
PCM4
88
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
P40/SIB0
87
P41/SOB0
86
P42/SCKB0
85
P30/TXDA0
84
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
P36/CTXD1
83
82
81
80
79
PCD2
78
PCD1
P37/CRXD1
77
PCD0
EVSS
76
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P912/SCKB2
EVDD
75
P38/TXDA2
74
P39/RXDA2/INTP8
73
Notes 1
Notes 2
IC: Connect to VSS directly
FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）
FLMD1: Flash memory versions only
REGC can be connect to VSS via capacitor of 4.7uF
28
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FG2 (µPD70F3234,µPD70F3235,µPD70F3236)
100-pin plastic LQFP (fine pitch) (14 × 14)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
P
P
P
P
P
D
D
D
D
D
L4
L3
L2
L1
L0
AV
REF0
2
AVSS
3
P
10/I
NTP9
4
P
11/I
N
TP10
EVDD
5
6
BVDD
BVSS
P
P
00/TIP31/TOP31
01/TIP30/TOP30
7
Note1
8
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
C
C
C
C
C
C
C
C
C
C
T
T
T
T
6
4
1
0
IC/[FLMD0]
9
V
DD
Note2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R
EGC
V
SS
M
M
M
M
3
2
1
0
X
1
2
X
/CLKOUT
R
ESET
XT
XT
1
2
I
S
S
1
0
P
02
/A
04/I
/
N
M
915/I
914/I
913/I
912
N
N
N
TP
TP
TP
6
5
4
P
03/I
N
TP
0
D
T
R
G
P
N
TP
1
/PCL
P
05/I
N
TP
2
/[DRST]
P
06/I
40/SIB
41/SOB
42/S KB
30/TX
N
TP
3
0
0
0
0
911
P
910
P
99/S
C
KB
1
P
P
C
98/SOB
1
D
A
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes 1
IC: Connect to VSS directly
FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）
FLMD1: Flash memory versions only
Notes 2
REGC can be connect to VSS via capacitor of 4.7uF
Remark
Pins in brackets are valid only in µ PD70F3234, 70F3235, 70F3236
29
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FF2 (µPD70F3232,µPD70F3233)
80-pin plastic TQFP (fine pitch) (12 × 12)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVREF0
AVSS
PDL3
2
PDL2
3
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
PDL1
4
PDL0
5
PCT6
P03/INTP0/ADTRG
P04/INTP1
6
PCT4
7
PCT1
Note1IC/[FLMD0]
8
PCT0
V
DD
9
PCM3
Note2REGC
10
11
12
13
14
15
16
17
18
19
20
PCM2
V
SS
PCM1/CLKOUT
PCM0
X1
X2
PCS1
RESET
PCS0
XT1
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P99/SCKB1
P98/SOB1
P97/SIB1/TIP20/TOP20
XT2
P05/INTP2/[DRST]
P06/INTP3
P40/SIB0
P41/SOB0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes 1
IC: Connect to VSS directly
FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）
FLMD1: Flash memory versions only
Notes 2
REGC can be connect to VSS via capacitor of 4.7uF
Remark
Pins in brackets are only valid for µ PD70F3232, µ 70F3233
30
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FE2 (µPD703230, µPD70F3231)
64-pin plastic LQFP (fine pitch) (10 × 10)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
PDL1
AVREF0
AVSS
2
PDL0
Note1IC/[FLMD0]
3
PCM1/CLKOUT
PCM0
4
V
DD
Note2REGC
5
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P99/SCKB1
P98/SOB1
6
V
SS
7
X1
X2
8
9
RESET
10
11
12
13
14
15
16
P97/SIB1/TIP20/TOP20
P96/TIP21/TOP21
P91/KR7/RXDA1
P90/KR6/TXDA1
P55/KR5/[DMS]
P54/KR4/[DCK]
EVDD
XT1
XT2
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
P03/INTP0/ADTRG
P04/INTP1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1
IC: Connect to VSS directly
FLMD0: Connect to VSS in the normal operation mode.（Flash memory versions only）
FLMD1: Flash memory versions only
Note 2
REGC can be connect to VSS via capacitor of 4.7uF
Pins in brackets are only valid for µ PD70F3231
Remark
31
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
Pin identification
AD0 to AD15:
ADTRG:
ANI0 to ANI23:
ASCKA0:
ASTB:
Address/data bus
A/D trigger input
P120 to P127:
Port 12
PCD0 to PCD3:
PCL:
Port CD
Analog input
Programmable clock output
Port CM
Asynchronous serial clock
Address strobe
PCM0 to PCM5:
PCS0 to PCS7:
PCT0 to PCT7:
PDL0 to PDL15:
RD:
Port CS
AVREF0:
Analog reference voltage
Analog VSS
Port CT
AVSS:
Port DL
BVDD:
Power supply for bus interface
Ground for bus interface
Clock output
Read strobe
Regulator control
Reset
BVSS:
REGC:
CLKOUT:
RESET:
CRXD0 to CRXD3: CAN receive data
CS0 to CS3: Chip select
CTXD0 to CTXD3: CAN transmit data
RXDA0 to RXDA3: Receive data
SCKB0 to SCKB2: Serial clock
SIB0 to SIB2:
Serial input
Serial output
Timer input
Timer input
Timer input
Timer input
Timer input
Timer input
Timer input
Timer output
Timer output
Timer output
Timer output
DCK:
Debug clock
SOB0 to SOB2:
TIP00, TIP01,
TIP10, TIP11,
DDI:
Debug data input
Debug data output
Debug mode select
Debug reset
DDO:
DMS:
TIP20, TIP21,
TIP30, TIP31,
TIQ00 to TIQ03,
TIQ10 to TIQ13,
TIQ20 to TIQ23:
TOP00, TOP01,
TOP10, TOP11,
TOP20, TOP21,
TOP30, TOP31,
DRST:
EVDD:
Power supply for port
Ground for port
EVSS:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
Flash programming mode
Hold acknowledge
Hold request
INTP0 to INTP14: Interrupt request from peripherals
KR0 to KR7:
NMI:
Key return
Non-maskable interrupt request
TOQ01 to TOQ03, Timer output
TOQ11 to TOQ13, Timer output
TOQ20 to TOQ23: Timer output
TXDA0 to TXDA3: Transmit data
P00 to P06:
P10, P11:
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
P30 to P39:
P40 to P42:
P50 to P55:
P60 to P615:
P70 to P715:
P80, P81:
VDD:
Power supply
VSS:
Ground
WAIT:
WR0:
Wait
Write strobe low level data
Write strobe high level data
Crystal for main clock
Crystal for subclock
WR1:
P90 to P915:
X1, X2:
XT1, XT2:
32
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
1.7 Function Block Configuration
1.7.1 Internal block diagram
• V850ES/FJ2 (µPD70F3237)
Flash memory
CPU
NMI
INTC
Instruction
queue
CS0 to CS3
AD0 to AD15
INTP0 to INTP14
PC
256 KB
TIQ00 to TIQ20
TIQ01 to TIQ21
TIQ02 to TIQ22
TIQ03 to TIQ23
32-bit barrel
shifter
Multiplier
16 16
HLDRQ
HLDAK
ASTB
RD
MEMC
32
RAM
16-bit timer/
counter Q:
3 ch
System
registers
BCU
TOQ00 to TOQ20
TOQ01 to TOQ21
TOQ02 to TOQ22
TOQ03 to TOQ23
WAIT
12 KB
ALU
WR0, WR1
General-
purpose registers
32 bits 32
TIP00 to TIP30
TIP01 to TIP31
DMAC
16-bit timer/
counter P:
4 ch
TOP00 to TOP30
TOP01 to TOP31
16-bit
interval
timer M:
1 ch
PCL
Ports
CLKOUT
XT1
CG
SOB0 to SOB2
SIB0 to SIB2
SCKB0 to SCKB2
XT2
X1
X2
CSIB: 3 ch
UARTA: 3 ch
CAN: 2 ch
PLL
RG
RESET
TXDA0 to TXDA2
RXDA0 to RXDA2
ASCKA0
FLMD0
FLMD1
BVDD
BVSS
CTXD0, CTXD1
CRXD0, CRXD1
EVDD
EVSS
ANI0 to ANI23
AVSS
V
V
DD
SS
A/D
converter
DRST
AVREF0
ADTRG
Regulator
RCU
RSU
DMS
DDO
DCK
DDI
REGC
Key return
function
KR0 to KR7
CLM
POC
ROMC
Watchdog
timer 2
On chip debug
Watch timer
Note
LVI
Note: only POC version
33
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FJ2 (µPD70F3238µPD70F3239)
Flash memory
CPU
NMI
INTP0 to INTP14
INTC
Instruction
queue
CS0 to CS3
AD0 to AD15
PC
Note 1
TIQ00 to TIQ20
TIQ01 to TIQ21
TIQ02 to TIQ22
TIQ03 to TIQ23
32-bit barrel
shifter
Multiplier
16 16
HLDRQ
HLDAK
ASTB
RD
MEMC
32
RAM
16-bit timer/
counter Q:
3 ch
System
registers
BCU
TOQ00 to TOQ20
TOQ01 to TOQ21
TOQ02 to TOQ22
TOQ03 to TOQ23
WAIT
20 KB
ALU
WR0, WR1
General-
purpose registers
32 bits 32
TIP00 to TIP30
TIP01 to TIP31
DMAC
16-bit timer/
counter P:
4 ch
TOP00 to TOP30
TOP01 to TOP31
16-bit
interval
timer M:
1 ch
PCL
Ports
CLKOUT
XT1
CG
SOB0 to SOB2
SIB0 to SIB2
SCKB0 to SCKB2
XT2
X1
X2
CSIB: 3 ch
UARTA: 4 ch
CAN: 4 ch
PLL
RG
RESET
TXDA0 to TXDA3
RXDA0 to RXDA3
ASCKA0
FLMD0
FLMD1
BVDD
BVSS
CTXD0 to CTXD3
CRXD0 to CRXD3
EVDD
EVSS
ANI0 to ANI23
AVSS
V
V
DD
SS
A/D
converter
DRST
AVREF0
ADTRG
Regulator
CLM
RCU
RSU
DMS
DDO
DCK
DDI
REGC
Key return
function
KR0 to KR7
ROMC
Watchdog
timer 2
On chip debug
Note 2
POC
Watch timer
LVI
Notes: 1
2.
376 KB/512 KB (Flash memory see Table1-1)
POC version
34
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FG2 (µPD70F3234, µPD70F3235, µPD70F3236)
ROM
CPU
NMI
INTC
Instruction
queue
INTP0 to INTP10
Note 1
PC
TIQ00 to TIQ10
TIQ01 to TIQ11
TIQ02 to TIQ12
TIQ03 to TIQ13
Multiplier
16 16 32
32-bit barrel
shifter
RAM
16-bit timer/
counter Q:
2 ch
System
registers
BCU
Note 2
TOQ00 to TOQ10
TOQ01 to TOQ11
TOQ02 to TOQ12
TOQ03 to TOQ13
ALU
General-
purpose register
32 bits 32
TIP00 to TIP30
TIP01 to TIP31
DMAC
16-bit timer/
counter P:
4 ch
TOP00 to TOP30
TOP01 to TOP31
16-bit
interval
timer M:
1 ch
PCL
Ports
CLKOUT
XT1
CG
SOB0, SOB1
SIB0, SIB1
SCKB0, SCKB1
XT2
X1
X2
CSIB: 2ch
UARTA: 3ch
CAN: 2ch
PLL
RG
RESET
TXDA0 to TXDA2
RXDA0 to RXDA2
ASCKA0
FLMD0
FLMD1
BVDD
BVSS
CTXD0, CTXD1
CRXD0, CRXD1
EVDD
EVSS
ANI0 to ANI15
AVSS
V
DD
SS
A/D
converter
DRST
AVREF0
ADTRG
V
Regulator
CLM
RCU
RSU
DMS
DDO
DCK
DDI
REGC
Key return
function
KR0 to KR7
ROMC
Watchdog
timer 2
On chip debug
POC Note 3
Watch timer
LVI
Notes:
1
128/256/384KB (Flash memory see Table1-1)
128/256KB (Mask ROM see Table1-1)
6/12/16KB (see Table1-1)
2
3
POC version only
35
User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FF2 (µPD70F3232, µPD70F3233)
ROM
CPU
NMI
INTC
Instruction
queue
INTP0 to INTP7
PC
Note 1
TIQ00
TIQ01
TIQ02
TIQ03
Multiplier
16 16 32
32-bit barrel
shifter
RAM
16-bit timer/
counter Q:
1 ch
System
registers
BCU
TOQ00
TOQ01
TOQ02
TOQ03
Note 2
ALU
General-
purpose registers
32 bits 32
TIP00 to TIP30
TIP01 to TIP31
16-bit timer/
counter P:
4 ch
TOP00 to TOP30
TOP01 to TOP31
16-bit
interval
timer M:
1 ch
PCL
Ports
CLKOUT
XT1
CG
SOB0, SOB1
SIB0, SIB1
SCKB0, SCKB1
XT2
X1
X2
CSIB: 2ch
UARTA: 2ch
CAN: 1ch
PLL
RG
RESET
TXDA0, TXDA1
RXDA0, RXDA1
ASCKA0
FLMD0
FLMD1
EVDD
CTXD0
CRXD0
EVSS
ANI0 to ANI11
AVSS
V
DD
SS
A/D
converter
DRST
AVREF0
ADTRG
V
Regulator
CLM
RCU
RSU
DMS
DDO
DCK
DDI
REGC
Key return
function
KR0 to KR7
ROMC
Watchdog
timer 2
On chip debug
POCNote 3
Watch timer
LVI
Notes: 1
128/256 (Flash memory see Table1-1)
128/256KB (Mask ROM see Table1-1)
6/12KB (see Table1-1)
2
3
POC version only
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
• V850ES/FE2 (µPD703230, µPD70F3231)
ROM
CPU
NMI
INTC
Instruction
queue
INTP0 to INTP7
PC
Note 1
TIQ00
TIQ01
TIQ02
TIQ03
Multiplier
16 16 32
32-bit barrel
shifter
RAM
16-bit timer/
counter Q:
1 ch
System
registers
BCU
TOQ00
TOQ01
TOQ02
TOQ03
Note 2
ALU
General-
purpose register
32 bits 32
TIP00 to TIP30
TIP01 to TIP31
16-bit timer/
counter P:
4 ch
TOP00 to TOP30
TOP01 to TOP31
16-bit
interval
timer M:
1 ch
PCL
Ports
CLKOUT
XT1
CG
SOB0, SOB1
SIB0, SIB1
SCKB0, SCKB1
XT2
X1
X2
CSIB: 2ch
UARTA: 2ch
CAN: 1ch
PLL
RG
RESET
TXDA0, TXDA1
RXDA0, RXDA1
ASCKA0
FLMD0
FLMD1
EVDD
CTXD0
CRXD0
EVSS
ANI0 to ANI9
AVSS
V
DD
SS
A/D
converter
DRST
DMS
DDO
DCK
DDI
AVREF0
ADTRG
V
Regulator
RCU
RSU
REGC
Key return
function
KR0 to KR7
CLM
POCNote 3
LVI
ROMC
Watchdog
timer 2
On chip debug
Watch timer
Notes: 1
128KB (Flash memory see Table1-1)
64/128KB (Mask ROM see Table1-1)
4/6KB (see Table1-1)
2
3
POC version only
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
1.7.2 Internal units
(1) CPU
The CPU can execute almost all instruction processing, such as address calculation, arithmetic and logic
operations, and data transfer, in one clock under control of a five-stage pipeline.
Dedicated hardware units such as a multiplier (16 bits × 16 bits Æ 32 bits) and a barrel shifter (32 bits) are
provided to speed up complicated instruction processing.
(2) External memory control unit (MEMC)
This unit starts necessary external bus cycles based on the physical addresses obtained by the CPU. If the
CPU does not request the start of a bus cycle when it fetches an instruction from an external memory area,
this unit generates a prefetch address and prefetches an instruction code. The prefetched instruction code is
sent to an internal instruction queue.
(3) ROM
This is
a
flash memory of 512/384/376/256/128/64 KB mapped to addresses 0000000H-
007FFFFH/0000000H-005FFFFH/0000000H-005DFFFH/0000000H-003FFFFH/0000000H-
001FFFFH/0000000H-000FFFFH. The CPU can access this memory in one clock when it fetches an
instruction.
(4) RAM
This is
a
RAM of 20/16/12/6/4 KB mapped to addresses 3FFA000H-3FFEFFFH/3FFB000H-
3FFEFFFH/3FFC000H-3FFEFFFH/3FFD8000H-3FFEFFFH/3FFE000H-3FFEFFFH. The CPU can access
this RAM in one clock when it accesses data.
(5) Interrupt controller (INTC)
The interrupt controller processes interrupt requests (NMI and INTP0 up to INTP14 refer to Table 1-1) from
the on-chip peripheral hardware and external sources. Eight levels of priorities can be specified for these
interrupt requests, and multiple servicing control can be performed on interrupt sources.
(6) Clock generator (CG)
Two types of oscillators, a main clock (fXX) and a subclock (fXT), are provided. The clock generator generates
seven types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT), of which one is supplied as the operating
clock of the CPU (fCPU).
(7) Ring-OSC
A Ring-OSC oscillator is provided. The oscillation frequency is 200 kHz (TYP.). This Ring-OSC oscillator
supplies a clock to watchdog timer 2 and timer M.
(8) Timers/counters
16-bit timer/event counter P (TMP), 16-bit timer/event counter Q (TMQ), and 16-bit interval timer M (TMM) are
provided (refer to Table 1-1).
(9) Watch timer
This timer counts the reference time for watch counting from the subclock or fBRG from prescaler 3. At the
same time, it can also be used as an interval timer that operates on the main clock.
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User’s Manual U17830EE1V0UM00
CHAPTER 1 INTRODUCTION
(10) Watchdog timer 2
This watchdog timer is used to detect a program loop and system errors.
As the source clock of this timer, Ring-OSC, or main clock can be selected.
When this watchdog timer overflows, it generates a non-maskable interrupt request signal (INTWDT2) or
system reset signal (WDT2RES).
(11) Serial interface (SIO)
The V850ES /FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 have asynchronous serial interface A (UARTA)
and 3-wire variable-length serial interface B (CSIB) as serial interfaces, and up to seven channels can be used
at the same time.
UARTA transfers data by using the TXDAn and RXDAn pins (n = 0 up to 3 refer to Table 1-1).
CSIB transfers data by using the SOBm, SIBm, and SCKBm pins (m = 0 up to 2 refer to Table 1-1).
UARTA has a dedicated baud rate generator.
(12) CAN controller
The CAN controller is a small-scale digital data transmission system that transfers data between units.
(13) A/D converter
This is a high-speed, high-resolution 10-bit A/D converter with up to 24 analog input pins (refer to Table 1-1).
This converter is a successive approximation type.
(14) DMA controller
The V850ES/FG2, V850ES/FJ2 has a four-channel DMA controller that transfers data between the internal
RAM, on-chip peripheral I/O, and external memory, in response to interrupt requests from the on-chip
peripheral I/O.
(15) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins of eight
channels.
(16) On-chip debug function (Flash memory product only)
An on-chip debug function (Flash memory product only) that uses the communication specifications of JTAG
(Joint Test Action Group) and that is used via an N-Wire in-circuit emulator is provided. The normal port
function and on-chip debug function are selected by using the input level of a control pin and on-chip debug
mode setting register (OCDM).
(17) Ports
General-purpose port functions and control pin functions are available. For details, refer to CHAPTER 4
PORT FUNCTIONS.
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User’s Manual U17830EE1V0UM00
CHAPTER 2 PIN FUNCTIONS
This section explains the names and functions of the pins of the V850ES/FE2, V850ES/FF2, V850ES/FG2,
V850ES/FJ2.
2.1 Pin Function List
2.1.1 V850ES/FE2
Two I/O buffer power supplies, AVREF0 and EVDD, are available.The relationship between the power supplies and the
pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies (V850ES/FE2)
Power Supply
Corresponding Pin
AVREF0
EVDD
Port 7
Port 0, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, Port CM, Port DL, RESET
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CHAPTER 2 PIN FUNCTIONS
(1) Port pins
Table 2-2. Pin List (Port Pins V850ES/FE2)
Pin Name
I/O
I/O
Function
Alternate Function
TIP31/TOP31
P00
Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
P01
P02
P03
P04
P05
P06
P30
P31
P32
P33
P34
P35
P40
P41
P42
P50
P51
P52
P53
P54
P55
P70 to P79
TIP30/TOP30
NMI
INTP0/ADTRG
INTP1
INTP2/DRST
INTP3
I/O
TXDA0
Port 3
RXDA0/INTP7
ASCKA0/TIP00/TOP00/TOP01
TIP01/TOP01/CTXD0
TIP10/TOP10/CRXD0
TIP11/TOP11
SIB0
6-bit I/O port
Input/output can be specified in 1-bit units.
I/O
I/O
Port 4
SOB0
3-bit I/O port
Input/output can be specified in 1-bit units.
SCKB0
KR0/TIQ01/TOQ01
KR1/TIQ02/TOQ02
KR2/TIQ03/TOQ03/DDI
KR3/TIQ00/TOQ00/DDO
KR4/DCK
Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
KR5/DMS
I/O
I/O
ANI0 to ANI9
Port 7
10-bit I/O port
Input/output can be specified in 1-bit units.
P90
KR6/TXDA1
KR7/RXDA1
TIP21/TOP21
SIB1/TIP20/TOP20
SOB1
Port 9
P91
9-bit I/O port
Input/output can be specified in 1-bit units.
P96
P97
P98
P99
SCKB1
P913
P914
P915
PCM0
PCM1
INTP4/PCL
INTP5
INTP6
I/O
I/O
-
Port CM
2-bit I/O port
CLKOUT
Input/output can be specified in 1-bit units.
PDL0 to PDL4
PDL5
-
Port DL
8-bit I/O port
FLMD1
Input/output can be specified in 1-bit units.
PDL6, PDL7
-
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User’s Manual U17830EE1V0UM00
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (1/3)
Pin Name
NMI
I/O
Function
Alternate Function
Input
P02 Note
External interrupt input
(non-maskable, with analog noise eliminated)
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
TIP00
TIP01
TIP10
TIP11
TIP20
TIP21
TIP30
TIP31
TOP00
TOP01
Input
P03/ADTRG
External interrupt request input
(maskable, with analog noise eliminated)
P04
P05/DRST
P06
P913/PCL
P914
P915
P31/RXDA0
Input
External event/clock input (TMP00)
External event input (TMP01)
External event/clock input (TMP10)
External event input (TMP11)
External event/clock input (TMP20)
External event input (TMP21)
External event/clock input (TMP30)
External event input (TMP31)
Timer output (TMP00)
P32/ASCKA0/TOP00/TOP01
P33/TOP01/CTXD0
P34/TOP10/CRXD0
P35/TOP11
P97/SIB1/TOP20
P96/TOP21
P01/TOP30
P00/TOP31
Output
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
P33/TIP01/CTXD0
P34/TIP10/CRXD0
P35/TIP11
Timer output (TMP01)
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
Timer output (TMP10)
Timer output (TMP11)
Timer output (TMP20)
Timer output (TMP21)
Timer output (TMP30)
Timer output (TMP31)
P97/SIB1/TIP20
P96/TIP21
P01/TIP30
P00/TIP31
Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been
reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge
detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.
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CHAPTER 2 PIN FUNCTIONS
Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (2/3)
Pin Name
TIQ00
I/O
Function
External event/clock input (TMQ00)
External event input (TMQ01)
External event input (TMQ02)
External event input (TMQ03)
Timer output (TMQ00)
Alternate Function
P53/KR3/TOQ00/DDO
P50/KR0/TOQ01
P51/KR1/TOQ02
P52/KR2/TOQ03/DDI
P53/KR3/TIQ00/DDO
P50/KR0/TIQ01
P51/KR1/TIQ02
P52/KR2/TIQ03/DDI
P40
Input
TIQ01
TIQ02
TIQ03
TOQ00
TOQ01
TOQ02
TOQ03
SIB0
Output
Timer output (TMQ01)
Timer output (TMQ02)
Timer output (TMQ03)
Input
Output
I/O
Serial receive data input (CSIB0)
Serial receive data input (CSIB1)
Serial transmit data output (CSIB0)
Serial transmit data output (CSIB1)
Serial clock I/O (CSIB0)
SIB1
P97/TIP20/TOP20
P41
SOB0
SOB1
P98
SCKB0
SCKB1
RXDA0
RXDA1
TXDA0
TXDA1
P42
Serial clock I/O (CSIB1)
P99
Input
Output
Serial receive data input (UARTA0)
Serial receive data input (UARTA1)
Serial transmit data output (UARTA0)
Serial transmit data output (UARTA1)
P31/INTP7
P91/KR7
P30
P90/KR6
ASCKA0
CRXD0
Input
Input
Baud rate clock input to UARTA0
P32/TIP00/TOP00/TOP01
P34/TIP10/TOP10
P33/TIP01/TOP01
P70 to P79
CAN receive data input (CAN0)
CTXD0
Output
Input
CAN transmit data output (CAN0)
Analog voltage input to A/D converter
Reference voltage input to A/D converter, and positive power supply
pin for port 7
ANI0 to ANI9
AVREF0
Input
−
AVSS
ADTRG
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
−
Ground potential for A/D converter (same potential as VSS)
A/D converter external trigger input
Key interrupt input
−
P03/INTP0
Input
Input
P50/TIQ01/TOQ01
P51/TIQ02/TOQ02
P52/TIQ03/TOQ03/DDI
P53/TIQ00/TOQ00/DDO
P54/DCK
P55/DMS
P90/TXDA1
P91/RXDA1
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CHAPTER 2 PIN FUNCTIONS
Table 2-3. Pin List (Non-Port Pins V850ES/FE2) (2/3)
Pin Name
DMS
I/O
Function
Debug mode select
Alternate Function
P55/KR5
Input
Input
Output
Input
Input
Output
Input
DDI
Debug data input
P52/KR2/TIQ03/TOQ03
DDO
DCK
Debug data output
P53/KR3/TIQ00/TOQ00
Debug clock input
P54/KR4
DRST
CS0 to CS3
FLMD0
FLMD1
CLKOUT
PCL
Debug reset input
P05/INTP2
Chip select signal output
Flash programming mode setting pins
PCS0 to PCS3
−
PDL5
Output
PCM1
Internal system clock output
Output
Clock output (timing output of X1 input clock and subclock)
P913/INTP4
REGC
RESET
X1
−
Regulator output stabilizing capacitor connection
System reset input
−
−
−
−
−
−
−
−
−
−
Input
Input
Main clock resonator connection
X2
−
XT1
Input
Subclock resonator connection
XT2
−
−
−
−
−
VDD
Positive power supply pin for internal circuitry
VSS
Ground potential for internal circuitry
EVDD
EVSS
Positive power supply pin for external circuitry (same potential as VDD)
Ground potential for external circuitry (same potential as VSS)
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CHAPTER 2 PIN FUNCTIONS
2.1.2 V850ES/FF2
Two I/O buffer power supplies, AVREF0 and EVDD, are available. The relationship between the power supplies and the
pins is shown below.
Table 2-4. Pin I/O Buffer Power Supplies (V850ES/FF2)
Power Supply
Corresponding Pin
AVREF0
Port 7
EVDD
Port 0, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, Port CM, Port CS, Port CT, Port DL,
RESET
(1) Port pins
Table 2-5. Pin List (Port Pins V850ES/FF2) (1/2)
Pin Name
I/O
I/O
Function
Alternate Function
TIP31/TOP31
P00
Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
P01
P02
P03
P04
P05
P06
P30
P31
P32
P33
P34
P35
P38
P39
P40
P41
P42
P50
P51
P52
P53
P54
P55
TIP30/TOP30
NMI
INTP0/ADTRG
INTP1
INTP2/DRST
INTP3
I/O
TXDA0
Port 3
RXDA0/INTP7
ASCKA0/TIP00/TOP00/TOP01
TIP01/TOP01/CTXD0
TIP10/TOP10/CRXD0
TIP11/TOP11
-
8-bit I/O port
Input/output can be specified in 1-bit units.
-
I/O
I/O
SIB0
Port 4
SOB0
3-bit I/O port
Input/output can be specified in 1-bit units.
SCKB0
KR0/TIQ01/TOQ01
KR1/TIQ02/TOQ02
KR2/TIQ03/TOQ03/DDI
KR3/TIQ00/TOQ00/DDO
KR4/DCK
Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
KR5/DMS
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CHAPTER 2 PIN FUNCTIONS
Table 2-5. Pin List (Port Pins V850ES/FF2) (2/2)
Pin Name
I/O
I/O
Function
Alternate Function
ANI0 to ANI11
P70 to P711
Port 7
12-bit I/O port
Input/output can be specified in 1-bit units.
P90
I/O
KR6/TXDA1
Port 9
P91
KR7/RXDA1
9-bit I/O port
Input/output can be specified in 1-bit units.
P96
TIP21/TOP21
P97
SIB1/TIP20/TOP20
P98
SOB1
P99
SCKB1
P913
INTP4/PCL
P914
INTP5
P915
INTP6
PCM0
PCM1
PCM2, PCM3
PCS0, PCS1
I/O
-
Port CM
4-bit I/O port
CLKOUT
Input/output can be specified in 1-bit units.
-
-
I/O
I/O
I/O
Port CS
2-bit I/O port
Input/output can be specified in 1-bit units.
PCT0, PCT1,
PCT4, PCT6
-
Port CT
4-bit I/O port
Input/output can be specified in 1-bit units.
PDL0 to PDL4
PDL5
-
Port DL
8-bit I/O port
FLMD1
Input/output can be specified in 1-bit units.
PDL6 to PDL11
-
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User’s Manual U17830EE1V0UM00
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (1/3)
Pin Name
NMI
I/O
Function
Alternate Function
Input
P02 Note
External interrupt input
(non-maskable, with analog noise eliminated)
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
TIP00
TIP01
TIP10
TIP11
TIP20
TIP21
TIP30
TIP31
TOP00
TOP01
Input
P03/ADTRG
External interrupt request input
(maskable, with analog noise eliminated)
P04
P05/DRST
P06
P913/PCL
P914
P915
P31/RXDA0
Input
External event/clock input (TMP00)
External event input (TMP01)
External event/clock input (TMP10)
External event input (TMP11)
External event/clock input (TMP20)
External event input (TMP21)
External event/clock input (TMP30)
External event input (TMP31)
Timer output (TMP00)
P32/ASCKA0/TOP00/TOP01
P33/TOP01/CTXD0
P34/TOP10/CRXD0
P35/TOP11
P97/SIB1/TOP20
P96/TOP21
P01/TOP30
P00/TOP31
Output
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
P33/TIP01/CTXD0
P34/TIP10/CRXD0
P35/TIP11
Timer output (TMP01)
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
Timer output (TMP10)
Timer output (TMP11)
Timer output (TMP20)
Timer output (TMP21)
Timer output (TMP30)
Timer output (TMP31)
P97/SIB1/TIP20
P96/TIP21
P01/TIP30
P00/TIP31
Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been
reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge
detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.
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CHAPTER 2 PIN FUNCTIONS
Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (2/3)
Pin Name
TIQ00
I/O
Function
External event/clock input (TMQ00)
External event input (TMQ01)
External event input (TMQ02)
External event input (TMQ03)
Timer output (TMQ00)
Alternate Function
P53/KR3/TOQ00/DDO
P50/KR0/TOQ01
P51/KR1/TOQ02
P52/KR2/TOQ03/DDI
P53/KR3/TIQ00/DDO
P50/KR0/TIQ01
P51/KR1/TIQ02
P52/KR2/TIQ03/DDI
P40
Input
TIQ01
TIQ02
TIQ03
TOQ00
TOQ01
TOQ02
TOQ03
SIB0
Output
Timer output (TMQ01)
Timer output (TMQ02)
Timer output (TMQ03)
Input
Output
I/O
Serial receive data input (CSIB0)
Serial receive data input (CSIB1)
Serial transmit data output (CSIB0)
Serial transmit data output (CSIB1)
Serial clock I/O (CSIB0)
SIB1
P97/TIP20/TOP20
P41
SOB0
SOB1
P98
SCKB0
SCKB1
RXDA0
RXDA1
TXDA0
TXDA1
P42
Serial clock I/O (CSIB1)
P99
Input
Output
Serial receive data input (UARTA0)
Serial receive data input (UARTA1)
Serial transmit data output (UARTA0)
Serial transmit data output (UARTA1)
P31/INTP7
P91/KR7
P30
P90/KR6
ASCKA0
CRXD0
Input
Input
Baud rate clock input to UARTA0
P32/TIP00/TOP00/TOP01
P34/TIP10/TOP10
P33/TIP01/TOP01
P70 to P711
CAN receive data input (CAN0)
CTXD0
Output
Input
CAN transmit data output (CAN0)
Analog voltage input to A/D converter
Reference voltage input to A/D converter , and positive power supply
pin for port 7
ANI0 to ANI11
AVREF0
Input
−
AVSS
ADTRG
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
−
Ground potential for A/D converter (same potential as VSS)
A/D converter external trigger input
Key interrupt input
−
P03/INTP0
Input
Input
P50/TIQ01/TOQ01
P51/TIQ02/TOQ02
P52/TIQ03/TOQ03/DDI
P53/TIQ00/TOQ00/DDO
P54/DCK
P55/DMS
P90/TXDA1
P91/RXDA1
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CHAPTER 2 PIN FUNCTIONS
Table 2-6. Pin List (Non-Port Pins V850ES/FF2) (2/3)
Pin Name
DMS
I/O
Input
Input
Output
Input
Input
Input
Function
Debug mode select
Alternate Function
P55/KR5
DDI
Debug data input
P52/KR2/TIQ03/TOQ03
DDO
DCK
DRST
FLMD0
FLMD1
CLKOUT
PCL
Debug data output
P53/KR3/TIQ00/TOQ00
Debug clock input
P54/KR4
Debug reset input
P05/INTP2
Flash programming mode setting pins
−
PDL5
Output
PCM1
Internal system clock output
Output
Clock output (timing output of X1 input clock and subclock)
P913/INTP4
REGC
RESET
X1
−
Regulator output stabilizing capacitor connection
System reset input
−
−
−
−
−
−
−
−
−
−
Input
Input
Main clock resonator connection
X2
−
XT1
Input
Subclock resonator connection
XT2
−
−
−
−
−
VDD
Positive power supply pin for internal circuitry
VSS
Ground potential for internal circuitry
EVDD
EVSS
Positive power supply pin for external circuitry (same potential as VDD)
Ground potential for external circuitry (same potential as VSS)
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CHAPTER 2 PIN FUNCTIONS
2.1.3 V850ES/FG2
Three I/O buffer power supplies, AVREF0, BVDD and EVDD, are available. The relationship between the power
supplies and the pins is shown below.
Table 2-7. Pin I/O Buffer Power Supplies (V850ES/FG2)
Power Supply
Corresponding Pin
AVREF0
Port 7
EVDD
BVDD
Port 0, Port 1, Port 3, Port 4, Port 5, Port 9, RESET
Port CM, Port CS, Port CT, Port DL
(1) Port pins
Table 2-8. Pin List (Port Pins V850ES/FG2) (1/2)
Pin Name
I/O
I/O
Function
Alternate Function
TIP31/TOP31
P00
Port 0
7-bit I/O port
P01
P02
P03
P04
P05
P06
P10
P11
TIP30/TOP30
NMI
Input/output can be specified in 1-bit units.
INTP0/ADTRG
INTP1
INTP2/DRST
INTP3
I/O
I/O
INTP9
Port 1
2-bit I/O port
INTP10
Input/output can be specified in 1-bit units.
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
TXDA0
Port 3
10-bit I/O port
RXDA0/INTP7
ASCKA0/TIP00/TOP00/TOP01
TIP01/TOP01/CTXD0
TIP10/TOP10/CRXD0
TIP11/TOP11
CTXD1
Input/output can be specified in 1-bit units.
CRXD1
TXDA2
RXDA2/INTP8
SIB0
I/O
Port 4
3-bit I/O port
SOB0
Input/output can be specified in 1-bit units.
SCKB0
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CHAPTER 2 PIN FUNCTIONS
Table 2-8. Pin List (Port Pins V850ES/FG2) (2/2)
Pin Name
I/O
I/O
Function
Alternate Function
KR0/TIQ01/TOQ01
P50
P51
P52
P53
P54
P55
Port 5
6-bit I/O port
KR1/TIQ02/TOQ02
KR2/TIQ03/TOQ03/DDI
KR3/TIQ00/TOQ00/DDO
KR4/DCK
Input/output can be specified in 1-bit units.
KR5/DMS
P70 to P715
I/O
I/O
ANI0 to ANI15
Port 7
16-bit I/O port
Input/output can be specified in 1-bit units.
P90
KR6/TXDA1
Port 9
16-bit I/O port
P91
KR7/RXDA1
Input/output can be specified in 1-bit units.
P92
TIQ11/TOQ11
P93
TIQ12/TOQ12
P94
TIQ13/TOQ13
P95
TIQ10/TOQ10
P96
TIP21/TOP21
P97
SIB1/TIP20/TOP20
P98
SOB1
P99
SCKB1
P910
P911
P912
P913
P914
P915
PCM0
PCM1
PCM2, PCM3
PCS0, PCS1
−
−
−
INTP4/PCL
INTP5
INTP6
I/O
I/O
I/O
I/O
−
Port CM
4-bit I/O port
CLKOUT
Input/output can be specified in 1-bit units.
−
−
Port CS
2-bit I/O port
Input/output can be specified in 1-bit units.
PCT0, PCT1,
PCT4, PCT6
−
−
Port CT
4-bit I/O port
Input/output can be specified in 1-bit units.
PDL0 to PDL4
PDL5
−
Port DL
14-bit I/O port
FLMD1
Input/output can be specified in 1-bit units.
PDL6 to PDL13
−
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (1/3)
Pin Name
NMI
I/O
Function
Alternate Function
Input
P02 Note
External interrupt input
(non-maskable, with analog noise eliminated)
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
INTP8
INTP9
INTP10
TIP00
TIP01
TIP10
TIP11
TIP20
TIP21
TIP30
TIP31
TOP00
TOP01
Input
P03/ADTRG
External interrupt request input
(maskable, with analog noise eliminated)
P04
P05/DRST
P06
P913/PCL
P914
P915
P31/RXDA0
P39/RXDA2
P10
P11
Input
External event/clock input (TMP00)
External event/clock input (TMP01)
External event/clock input (TMP10)
External event/clock input (TMP11)
External event/clock input (TMP20)
External event/clock input (TMP21)
External event/clock input (TMP30)
External event/clock input (TMP31)
Timer output (TMP00)
P32/ASCKA0/TOP00/TOP01
P33/TOP01/CTXD0
P34/TOP10/CRXD0
P35/TOP11
P97/SIB1/TOP20
P96/TOP21
P01/TOP30
P00/TOP31
Output
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
P33/TIP01/CTXD0
P34/TIP10/CRXD0
P35/TIP11
Timer output (TMP01)
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
TIQ00
TIQ01
TIQ02
TIQ03
Timer output (TMP10)
Timer output (TMP11)
Timer output (TMP20)
P97/SIB1/TIP20
P96/TIP21
Timer output (TMP21)
Timer output (TMP30)
P01/TIP30
Timer output (TMP31)
P00/TIP31
Input
External event/clock input (TMQ00)
External event input (TMQ01)
External event input (TMQ02)
External event input (TMQ03)
P53/KR3/TOQ00/DDO
P50/KR0/TOQ01
P51/KR1/TOQ02
P52/KR2/TOQ03/DDI
Note: The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has been
reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No edge
detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.
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CHAPTER 2 PIN FUNCTIONS
Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (2/3)
Pin Name
TIQ10
I/O
Function
External event input (TMQ10)
External event input (TMQ11)
External event input (TMQ12)
External event input (TMQ13)
Timer output (TMQ00)
Alternate Function
P95/TOQ10
Input
TIQ11
P92/TOQ11
P93/TOQ12
P94/TOQ13
P53/KR3/TIQ00/DDO
P50/KR0/TIQ01
P51/KR1/TIQ02
P52/KR2/TIQ03/DDI
P95/TIQ10
P92/TIQ11
P93/TIQ12
P94/TIQ13
P40
TIQ12
TIQ13
TOQ00
TOQ01
TOQ02
TOQ03
TOQ10
TOQ11
TOQ12
TOQ13
SIB0
Output
Timer output (TMQ01)
Timer output (TMQ02)
Timer output (TMQ03)
Timer output (TMQ10)
Timer output (TMQ11)
Timer output (TMQ12)
Timer output (TMQ13)
Input
Output
I/O
Serial receive data input (CSIB0)
Serial receive data input (CSIB1)
Serial transmit data output (CSIB0)
Serial transmit data output (CSIB1)
Serial clock I/O (CSIB0)
SIB1
P97/TIP20/TOP20
P41
SOB0
SOB1
P98
SCKB0
SCKB1
RXDA0
RXDA1
RXDA2
TXDA0
TXDA1
TXDA2
ASCKA0
CRXD0
CRXD1
CTXD0
CTXD1
ANI0 to ANI15
AVREF0
P42
Serial clock I/O (CSIB1)
P99
Input
Serial receive data input (UARTA0)
Serial receive data input (UARTA1)
Serial receive data input (UARTA2)
Serial transmit data output (UARTA0)
Serial transmit data output (UARTA1)
Serial transmit data output (UARTA2)
Baud rate clock input to UARTA0
CAN receive data input (CAN0)
CAN receive data input (CAN1)
CAN transmit data output (CAN0)
CAN transmit data output (CAN1)
Analog voltage input to A/D converter
Reference voltage input to A/D converter , and positive power supply
pin for port 7
P31/INTP7
P91/KR7
P39/INTP8
P30
Output
P90/KR6
P38
Input
Input
P32/TIP00/TOP00/TOP01
P34/TIP10/TOP10
P37
Output
P33/TIP01/TOP01
P36
Input
Input
P70 to P715
–
AVSS
ADTRG
KR0
KR1
KR2
KR3
KR4
KR5
KR6
–
Ground potential for A/D converter (same potential as VSS)
A/D converter external trigger input
Key interrupt input
–
P03/INTP0
Input
Input
P50/TIQ01/TOQ01
P51/TIQ02/TOQ02
P52/TIQ03/TOQ03/DDI
P53/TIQ00/TOQ00/DDO
P54/DCK
P55/DMS
P90/TXDA1
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CHAPTER 2 PIN FUNCTIONS
KR7
P91/RXDA1
Table 2-9. Pin List (Non-Port Pins V850ES/FG2) (3/3)
Pin Name
I/O
Input
Input
Output
Input
Input
Input
Function
Debug mode select
Alternate Function
DMS
DDI
P55/KR5
Debug data input
P52/KR2/TIQ03/TOQ03
DDO
DCK
DRST
FLMD0
FLMD1
CLKOUT
PCL
Debug data output
P53/KR3/TIQ00/TOQ00
Debug clock input
P54/KR4
Debug reset input
P05/INTP2
Flash programming mode setting pins
−
PDL5
Output
Internal system clock output
PCM1
Output
Clock output (timing output of X1 input clock and subclock)
Regulator output stabilizing capacitor connection
System reset input
P913/INTP4
REGC
RESET
X1
−
Input
Input
−
−
−
−
−
−
−
−
−
−
Main clock resonator connection
X2
XT1
Input
−
Subclock resonator connection
XT2
VDD
−
Positive power supply pin for internal circuitry
Ground potential for internal circuitry
VSS
−
EVDD
−
Positive power supply pin for external circuitry (same potential as
VDD)
EVSS
BVDD
−
−
Ground potential for external circuitry (same potential as VSS)
Positive power supply pin for external circuitry (same potential as
VDD)
−
−
BVSS
−
Ground potential for external circuitry (same potential as VSS)
−
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CHAPTER 2 PIN FUNCTIONS
2.1.4 V850ES/FJ2
Three I/O buffer power supplies, AVREF0, BVDD, and EVDD, are available. The relationship between the power
supplies and the pins is shown below.
Table 2-10. Pin I/O Buffer Power Supplies (V850ES/FJ2)
Power Supply
Corresponding Pin
AVREF0
Port 7, Port 12
BVDD
EVDD
Port CD, Port CM Port CS, Port CT, Port DL
Port 0, Port 1, Port 3, Port 4, Port 5, Port 6, Port 8, Port 9, RESET
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CHAPTER 2 PIN FUNCTIONS
(1) Port pins
Table 2-11. Pin List (Port Pins) (1/3)
Pin Name
I/O
I/O
Function
Alternate Function
TIP31/TOP31
P00
Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
P01
P02
P03
P04
P05
P06
P10
P11
TIP30/TOP30
NMI
INTP0/ADTRG
INTP1
INTP2/DRST
INTP3
I/O
I/O
INTP9
Port 1
INTP10
2-bit I/O port
Input/output can be specified in 1-bit units.
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P50
P51
P52
P53
P54
P55
TXDA0
Port 3
RXDA0/INTP7
ASCKA0/TIP00/TOP00/TOP01
TIP01/TOP01/CTXD0
TIP10/TOP10/CRXD0
TIP11/TOP11
CTXD1
10-bit I/O port
Input/output can be specified in 1-bit units.
CRXD1
TXDA2
RXDA2/INTP8
SIB0
I/O
I/O
Port 4
SOB0
3-bit I/O port
Input/output can be specified in 1-bit units.
SCKB0
KR0/TIQ01/TOQ01
KR1/TIQ02/TOQ02
KR2/TIQ03/TOQ03/DDI
KR3/TIQ00/TOQ00/DDO
KR4/DCK
Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
KR5/DMS
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CHAPTER 2 PIN FUNCTIONS
Table 2-11. Pin List (Port Pins) (2/3)
Pin Name
I/O
I/O
Function
Alternate Function
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
INTP11
INTP12
INTP13
Port 6
16-bit I/O port
Input/output can be specified in 1-bit units.
−
−
CTXD2Note 1
CRXD2Note 1
CTXD3Note 1
CRXD3Note 1
−
P610
TIQ20/TOQ20
TIQ21/TOQ21
TIQ22/TOQ22
TIQ23/TOQ23
P611
P612
P613
P614
−
−
P615
P70 to P715
I/O
I/O
ANI0 to ANI15
Port 7
16-bit I/O port
Input/output can be specified in 1-bit units.
P80
P81
RXDA3/INTP14Note 2
TXDA3Note 2
Port 8
2-bit I/O port
Input/output can be specified in 1-bit units.
P90
I/O
KR6/TXDA1
KR7/RXDA1
TIQ11/TOQ11
TIQ12/TOQ12
TIQ13/TOQ13
TIQ10/TOQ10
TIP21/TOP21
SIB1/TIP20/TOP20
SOB1
Port 9
P91
16-bit I/O port
Input/output can be specified in 1-bit units.
P92
P93
P94
P95
P96
P97
P98
P99
SCKB1
P910
P911
P912
P913
P914
P915
SIB2
SOB2
SCKB2
INTP4/PCL
INTP5
INTP6
Notes 1. In the µPD70F3237, alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and CRXD3)
are not available.
2. In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not
available. The alternate function of the P80 pin in the µPD70F3237 is INTP14 only.
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CHAPTER 2 PIN FUNCTIONS
Table 2-11. Pin List (Port Pins) (3/3)
Pin Name
I/O
I/O
Function
Alternate Function
ANI16 to ANI23
P120 to P127
Port 12
8-bit I/O port
Input/output can be specified in 1-bit units.
PCD0 to PCD3
I/O
I/O
−
Port CD
4-bit I/O port
Input/output can be specified in 1-bit units.
PCM0
WAIT
Port CM
6-bit I/O port
PCM1
CLKOUT
HLDAK
HLDRQ
Input/output can be specified in 1-bit units.
PCM2
PCM3
PCM4
−
−
PCM5
PCS0 to PCS3
PCS4 to PCS7
I/O
I/O
CS0 to CS3
Port CS
8-bit I/O port
−
Input/output can be specified in 1-bit units.
PCT0
WR0
WR1
Port CT
8-bit I/O port
PCT1
Input/output can be specified in 1-bit units.
PCT2
−
−
PCT3
PCT4
RD
PCT5
−
−
PCT6
ASTB
PCT7
PDL0 to PDL4
PDL5
I/O
AD0 to AD4
AD5/FLMD1
AD6 to AD15
Port DL
16-bit I/O port
Input/output can be specified in 1-bit units.
PDL6 to PDL15
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Table 2-12. Pin List (Non-Port Pins) (1/4)
Pin Name
NMI Note 1
I/O
Function
Alternate Function
P02 Note 1
Input
External interrupt input
(non-maskable, with analog noise eliminated)
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
INTP8
INTP9
INTP10
INTP11
INTP12
INTP13
INTP14
TIP00
TIP01
TIP10
TIP11
TIP20
TIP21
TIP30
TIP31
TOP00
TOP01
Input
P03/ADTRG
P04
External interrupt request input
(maskable, with analog noise eliminated)
P05/DRST
P06
P913/PCL
P914
P915
P31/RXDA0
P39/RXDA2
P10
P11
P60
P61
P62
P80/RXDA3Note 2
P32/ASCKA0/TOP00/TOP01
P33/TOP01/CTXD0
P34/TOP10/CRXD0
P35/TOP11
P97/SIB1/TOP20
P96/TOP21
P01/TOP30
P00/TOP31
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
P33/TIP01/CTXD0
P34/TIP10/CRXD0
P35/TIP11
Input
External event/clock input (TMP00)
External event input (TMP01)
External event/clock input (TMP10)
External event input (TMP11)
External event/clock input (TMP20)
External event input (TMP21)
External event/clock input (TMP30)
External event input (TMP31)
Timer output (TMP00)
Output
Timer output (TMP01)
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
Timer output (TMP10)
Timer output (TMP11)
Timer output (TMP20)
Timer output (TMP21)
Timer output (TMP30)
Timer output (TMP31)
P97/SIB1/TIP20
P96/TIP21
P01/TIP30
P00/TIP31
Notes 1. The NMI pin and P02 pin are an alternate-function pin. This pin functions as the P02 pin after if has
been reset. To enable the NMI pin, set the PMC0.PMC02 bit to 1.The initial setting of the NMI pin is "No
edge detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.
2. In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not
available. The alternate function of the P80 pin in the µPD70F3237 is only INTP14.
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CHAPTER 2 PIN FUNCTIONS
Table 2-12. Pin List (Non-Port Pins) (2/4)
Pin Name
TIQ00
I/O
Function
External event/clock input (TMQ00)
External event input (TMQ01)
External event input (TMQ02)
External event input (TMQ03)
External event input (TMQ10)
External event input (TMQ11)
External event input (TMQ12)
External event input (TMQ13)
External event/clock input (TMQ20)
External event input (TMQ21)
External event input (TMQ22)
External event input (TMQ23)
Timer output (TMQ00)
Alternate Function
P53/KR3/TOQ00/DDO
P50/KR0/TOQ01
P51/KR1/TOQ02
P52/KR2/TOQ03/DDI
P95/TOQ10
P92/TOQ11
P93/TOQ12
P94/TOQ13
P610/TOQ20
P611/TOQ21
P612/TOQ22
P613/TOQ23
P53/KR3/TIQ00/DDO
P50/KR0/TIQ01
P51/KR1/TIQ02
P52/KR2/TIQ03/DDI
P95/TIQ10
P92/TIQ11
P93/TIQ12
P94/TIQ13
P610/TIQ20
P611/TIQ21
P612/TIQ22
P613/TIQ23
P40
Input
TIQ01
TIQ02
TIQ03
TIQ10
TIQ11
TIQ12
TIQ13
TIQ20
TIQ21
TIQ22
TIQ23
TOQ00
TOQ01
TOQ02
TOQ03
TOQ10
TOQ11
TOQ12
TOQ13
TOQ20
TOQ21
TOQ22
TOQ23
SIB0
Output
Timer output (TMQ01)
Timer output (TMQ02)
Timer output (TMQ03)
Timer output (TMQ10)
Timer output (TMQ11)
Timer output (TMQ12)
Timer output (TMQ13)
Timer output (TMQ20)
Timer output (TMQ21)
Timer output (TMQ22)
Timer output (TMQ23)
Input
Output
I/O
Serial receive data input (CSIB0)
Serial receive data input (CSIB1)
Serial receive data input (CSIB2)
Serial transmit data output (CSIB0)
Serial transmit data output (CSIB1)
Serial transmit data output (CSIB2)
Serial clock I/O (CSIB0)
SIB1
P97/TIP20/TOP20
P910
SIB2
SOB0
P41
SOB1
P98
SOB2
P911
SCKB0
SCKB1
SCKB2
RXDA0
RXDA1
RXDA2
RXDA3Note
TXDA0
TXDA1
TXDA2
TXDA3Note
P42
Serial clock I/O (CSIB1)
P99
Serial clock I/O (CSIB2)
P912
Input
Serial receive data input (UARTA0)
Serial receive data input (UARTA1)
Serial receive data input (UARTA2)
Serial receive data input (UARTA3)
Serial transmit data output (UARTA0)
Serial transmit data output (UARTA1)
Serial transmit data output (UARTA2)
Serial transmit data output (UARTA3)
P31/INTP7
P91/KR7
P39/INTP8
P80/INTP14
P30
Output
P90/KR6
P38
P81
Note In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not available.
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CHAPTER 2 PIN FUNCTIONS
Table 2-12. Pin List (Non-Port Pins) (3/4)
Pin Name
ASCKA0
I/O
Function
Alternate Function
Input
Input
Baud rate clock input to UARTA0
P32/TIP00/TOP00/TOP01
CRXD0
CAN receive data input (CAN0)
CAN receive data input (CAN1)
CAN receive data input (CAN2)
CAN receive data input (CAN3)
P34/TIP10/TOP10
CRXD1
P37
CRXD2Note
CRXD3Note
CTXD0
P66
P68
Output CAN transmit data output (CAN0)
CAN transmit data output (CAN1)
CAN transmit data output (CAN2)
CAN transmit data output (CAN3)
P33/TIP01/TOP01
CTXD1
P36
CTXD2Note
CTXD3Note
ANI0 to ANI15
ANI16 to ANI23
AVREF0
P65
P67
Input
Analog voltage input to A/D converter
P70 to P715
P120 to P127
−
Input
Reference voltage input to A/D converter, and positive power supply
pin for port 7
AVSS
−
Ground potential for A/D converter（same potential as VSS）
A/D converter external trigger input
−
P03/INTP0
ADTRG
KR0
Input
Input
Key interrupt input
P50/TIQ01/TOQ01
P51/TIQ02/TOQ02
P52/TIQ03/TOQ03/DDI
P53/TIQ00/TOQ00/DDO
P54/DCK
KR1
KR2
KR3
KR4
KR5
P55/DMS
KR6
P90/TXDA1
P91/RXDA1
P55/KR5
KR7
DMS
Input
Input
Debug mode select
Debug data input
DDI
P52/KR2/TIQ03/TOQ03
P53/KR3/TIQ00/TOQ00
P54/KR4
DDO
Output Debug data output
DCK
Input
Input
Debug clock input
Debug reset input
DRST
CS0 to CS3
AD0 to AD4
AD5
P05/INTP2
Output Chip select signal output
PCS0 to PCS3
PDL0 to PDL4
PDL5/FLMD1
PDL6 to PDL15
PCT6
I/O
Address/data bus for external memory
AD6 to AD15
ASTB
HLDRQ
HLDAK
RD
Output Address strobe signal output to external memory
Input
Bus hold request input
PCM3
Output Bus hold acknowledge output
PCM2
Output Read strobe signal output to external memory
PCT4
WAIT
WR0
Input
External wait input
PCM0
Output Write strobe to external memory (lower 8 bits)
Write strobe to external memory (higher 8 bits)
PCT0
WR1
PCT1
Note In the µPD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and CRXD3)
are not available.
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Table 2-12. Pin List (Non-Port Pins) (4/4)
Pin Name
FLMD0
I/O
Function
Alternate Function
Input
Flash programming mode setting pins
−
FLMD1
CLKOUT
PCL
PDL5/AD5
Output
PCM1
Internal system clock output
Output
Clock output (timing output of X1 input clock and subclock)
P913/INTP4
REGC
RESET
X1
−
Regulator output stabilizing capacitor connection
System reset input
−
−
−
−
−
−
−
−
−
−
−
−
Input
Input
Main clock resonator connection
X2
−
XT1
Input
Subclock resonator connection
XT2
−
−
−
−
−
−
−
VDD
Positive power supply pin for internal circuitry
VSS
Ground potential for internal circuitry
BVDD
BVSS
EVDD
EVSS
Positive power supply for bus interface and port
Ground potential for bus interface and port
Positive power supply pin for external circuitry (same potential as VDD)
Ground potential for external circuitry (same potential as VSS)
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2.2 Pin Status (V850ES/FJ2)
The V850ES/FJ2 has an external bus interface function that enables connection of external memories, such as
ROM and RAM, and I/O.
Table 2-4 shows the operating status of each external bus interface pin in each operation mode.
Table 2-13. Pin Operating Status in Each Operation Mode
Bus Control Pin
Reset
HALT Mode and
DMA Transfer
IDLE1, IDLE2, and
Software STOP
Modes
Idle StateNote 2
Bus Hold
Hi-Z
AD0 to AD15
Hi-ZNote
Operating
Hi-Z
H
Held
CS0 to CS3
WAIT
−
−
Operating
H
−
CLKOUT
WR0, WR1
RD
L
Operating
Hi-Z
H
ASTB
HLDAK
HLDRQ
L
−
−
Operating
Notes 1. The bus control pins function alternately as port pins and are initialized to the input mode (port mode).
2. Pin status in the idle state that is inserted after the T3 state.
Remark Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
Low-level output
High-level output
Input without sampling (not acknowledged)
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2.3 Description of Pin Functions
2.3.1 V850ES/FE2
(1) P00 to P06 (port 0) … 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) … input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) … input
These pins input to timers P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) … output
These pins output from timers P3 (TMP3).
(v) ADTRG (A/D trigger input) … input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) … input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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(2) P30 to P35 (port 3) … 3-state output
P30 to P35 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.
The valid edge of each pin is specified by using INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P35 by using pull-up resistor option register 3 (PU3).
(a) Port mode
P30 to P35 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).
(b) Control mode
(i) RXDA0 (Receive data) … input
These pins input the serial receive data of UARTA0.
(ii) TXDA0 (Transmit data) … output
These pins output the serial transmit data of UARTA0.
(iii) ASCKA0 (Asynchronous serial clock) … input
This pin inputs UARTA0.
(iv) INTP7 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input
These pins input to timers P0 and P1 (TMP0, TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output
These pins output from timers P0 and P1 (TMP0, TMP1).
(vii) CRXD0 (CAN receive data) … input
These pins input the receive data of CAN0.
(viii) CTXD0 (CAN transmit data) … output
These pins output the transmit data of CAN0.
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(3) P40 to P42 (port 4) … 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) … input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) … output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
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(4) P50 to P55 (Port 5) … 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug
function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) … input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input
These pins input to timers Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output
These pins output from timers Q0 (TMQ0).
(iv) DDI (Debug data input) … input
This pin inputs debug data to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(v) DDO (Debug data output) … output
This pin outputs debug data from the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(iv) DCK (Debug clock input) … input
This pin inputs a debug clock to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(vii) DMS (Debug mode select) … input
This pin selects the debug mode of the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(5) P70 to P79 (Port 7) … 3-state I/O
P70 to P79 function as a 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P70 to P79 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,
PM7H)
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(b) Control mode
P70 to P79 function alternately as the ANI0 to ANI9 pins.
(i) ANI0 to ANI9 (Analog input 0 to 9) … input
These pins input an analog signal to the A/D converter.
(6) P90, P91, P96 to P99, P913 to P915 (Port 9) … 3-state I/O
P90, P91, P96 to P99, P913 to P915 function as a 9-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by using INTF9H register.
An on-chip pull-up resistor can be connected to P90, P91, P96 to P99, P913 to P915 by using pull-up resistor
option register 9 (PU9).
(a) Port mode
P90, P91, P96 to P99, P913 to P915 can be set in the input or output mode in 1-bit units, by using port 9
mode register (PM9).
(b) Control mode
(i) SIB1 (Serial input) … input
These pins input the serial receive data of CSIB1.
(ii) SOB1 (Serial output) … output
These pins output the serial receive data of CSIB1.
(iii) SCKB1 (Serial clock) … 3-state I/O
These pins input/output the serial clock of CSIB1.
(iv) RXDA1 (Receive data) … input
This pin inputs the serial receive data of UARTA1.
(v) TXDA1 (Transmit data) … output
This pin outputs the serial transmit data of UARTA1.
(vi) TIP20, TIP21 (Timer input) … input
These pins input to timers P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) … output
These pins output from timers P2 (TMP2).
(viii) PCL (Clock output) … output
This pin outputs a clock.
(ix) INTP4 to INTP6 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
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(x) KR6, KR7 (Key return) … input
These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in
the input port mode.
(7) PCM0, PCM1 (port CM) … 3-state I/O
PCM0, PCM1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, and bus clock output.
(a) Port mode
PCM0, PCM1 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) CLKOUT (Clock output) … output
This pin outputs an internally generated bus clock.
(8) PDL0 to PDL7 (port DL) … 3-state I/O
PDL0 to PDL7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to
FLD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL7 can be set in the input or output mode in 1-bit units, by using port mode register DL (PMDL).
(9) RESET (Reset) … input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
(10) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
(11) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(12) AVSS (Ground for analog)
This is a ground pin for the A/D converter, and alternate-function ports.
(13) AVREF0 (Analog reference voltage) … input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(14) EVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
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(15) EVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(16) VDD (Power supply)
This pin supplies positive power. Connect all the VDD pins to a positive power supply.
(17) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(18) FLMD0 (Flash programming mode) Input
This is a signal input pin for flash memory programming mode. Connect this pin to VSS in the normal operation
mode.
(19) REGC (Regulator control) … input
This pin connects a capacitor for the regulator.
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2.3.2 V850ES/FF2
(1) P00 to P06 (port 0) … 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) … input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) … input
These pins input to timers P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) … output
These pins output from timers P3 (TMP3).
(v) ADTRG (A/D trigger input) … input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) … input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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(2) P30 to P35, P38, P39 (port 3) … 3-state output
P30 to P35, P38, P39 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.
The valid edge of each pin is specified by using INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P35, P38, P39 by using pull-up resistor option register
3 (PU3).
(a) Port mode
P30 to P35, P38, P39 can be set in the input or output mode in 1-bit units, by using port mode register 3
(PM3).
(b) Control mode
(i) RXDA0 (Receive data) … input
These pins input the serial receive data of UARTA0.
(ii) TXDA0 (Transmit data) … output
These pins output the serial transmit data of UARTA0.
(iii) ASCKA0 (Asynchronous serial clock) … input
This pin inputs of UARTA0.
(iv) INTP7 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input
These pins input to timers P0, P1 (TMP0, TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output
These pins output from timers P0, P1 (TMP0, TMP1).
(vii) CRXD0 (CAN receive data) … input
These pins input the receive data of CAN0.
(viii) CTXD0 (CAN transmit data) … output
These pins output the transmit data of CAN0.
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(3) P40 to P42 (port 4) … 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) … input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) … output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
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(4) P50 to P55 (Port 5) … 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug
function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) … input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input
These pins input to timers Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output
These pins output from timers Q0 (TMQ0).
(iv) DDI (Debug data input) … input
This pin inputs debug data to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(v) DDO (Debug data output) … output
This pin outputs debug data from the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(iv) DCK (Debug clock input) … input
This pin inputs a debug clock to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(vii) DMS (Debug mode select) … input
This pin selects the debug mode of the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(5) P70 to P711 (Port 7) … 3-state I/O
P70 to P711 function as a 12-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P70 to P711 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,
PM7H).
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(b) Control mode
P70 to P711 function alternately as the ANI0 to ANI11 pins.
(i) ANI0 to ANI11 (Analog input 0 to 11) … input
These pins input an analog signal to the A/D converter.
(6) P90, P91, P96 to P99, P913 to P915 (Port 9) … 3-state I/O
P90, P91, P96 to P99, P913 to P915 function as a 9-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by using INTF9H register.
An on-chip pull-up resistor can be connected to P90, P91, P96 to P99, P913 to P915 by using pull-up resistor
option register 9 (PU9).
(a) Port mode
P90, P91, P96 to P99, P913 to P915 can be set in the input or output mode in 1-bit units, by using port 9
mode register (PM9).
(b) Control mode
(i) SIB1 (Serial input) … input
These pins input the serial receive data of CSIB1.
(ii) SOB1 (Serial output) … output
These pins output the serial receive data of CSIB1.
(iii) SCKB1 (Serial clock) … 3-state I/O
These pins input/output the serial clock of CSIB1.
(iv) RXDA1 (Receive data) … input
This pin inputs the serial receive data of UARTA1.
(v) TXDA1 (Transmit data) … output
This pin outputs the serial transmit data of UARTA1.
(vi) TIP20, TIP21 (Timer input) … input
These pins input to timers P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) … output
These pins output from timers P2 (TMP2).
(viii) PCL (Clock output) … output
This pin outputs a clock.
(ix) INTP4 to INTP6 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
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(x) KR6, KR7 (Key return) … input
These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in
the input port mode.
(7) PCM0 to PCM3 (port CM) … 3-state I/O
PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, and bus clock output.
(a) Port mode
PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) CLKOUT (Clock output) … output
This pin outputs an internally generated bus clock.
(13) PCS0, PCS1 (port CS) … 3-state I/O
PCS0, PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port.
(a) Port mode
PCS0, PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS (PMCS).
(14) PCT0, PCT1, PCT4, PCT6 (port CT) … 3-state I/O
PCT0, PCT1, PCT4, PCT6 function as an 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port.
(a) Port mode
PCT0, PCT1, PCT4, PCT6 can be set in the input or output mode in 1-bit units, by using port mode
register CT (PMCT).
(8) PDL0 to PDL11 (port DL) … 3-state I/O
PDL0 to PDL11 function as a 12-bit I/O port that can be set to input or output in 1-bit units.
PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to
FLD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL11 can be set in the input or output mode in 1-bit units, by using port mode register DL
(PMDL).
(9) RESET (Reset) … input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
(10) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
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(11) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(12) AVSS (Ground for analog)
This is a ground pin for the A/D converter, and alternate-function ports.
(13) AVREF0 (Analog reference voltage) … input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(14) EVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(15) EVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(16) VDD (Power supply)
This pin supplies positive power. Connect all the VDD pins to a positive power supply.
(17) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(18) FLMD0 (Flash programming mode) Input
This is a signal input pin for flash memory programming mode. Connect this pin to VSS in the normal operation
mode.
(19) REGC (Regulator control) … input
This pin connects a capacitor for the regulator.
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2.3.3 V850ES/FG2
(1) P00 to P06 (port 0) … 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) … input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) … input
These pins input an external count clock to timer P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) … output
These pins output a pulse signal from timer P3 (TMP3).
(v) ADTRG (A/D trigger input) … input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) … input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(2) P10, P11 (port 1) … 3-state I/O
P10 and P11 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input in the control
mode. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is
specified by INTR1 and INTF1 registers.
An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).
(a) Port mode
P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).
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(b) Control mode
(i) INTP9, INTP10 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(3) P30 to P39 (port 3) … 3-state I/O
P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.
The valid edge of each pin is specified by using INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).
(a) Port mode
P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).
(b) Control mode
(i) RXDA0, RXDA2 (Receive data) … input
This pin inputs the serial receive data of UARTA0.
(ii) TXDA0, TXDA2 (Transmit data) … output
This pin outputs the serial transmit data of UARTA0.
(iii) ASCKA0 (Asynchronous serial clock) … input
This pin inputs of UARTA0.
(iv) INTP7, INTP8 (Interrupt request from peripherals) … input
This pin inputs an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input
These pins input an external count clock to timers P0, P1 (TMP0, TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output
These pins output a pulse signal from timers P0, P1 (TMP0, TMP1).
(vii) CRXD0, CRXD1 (CAN receive data) … input
These pins input the receive data of CAN0 and CAN1.
(viii) CTXD0, CTXD1 (CAN transmit data) … output
These pins output the transmit data of CAN0 and CAN1.
(4) P40 to P42 (port 4) … 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
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(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) … input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) … output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
(5) P50 to P55 (Port 5) … 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug
function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) … input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input
These pins input an external count clock to timer Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output
These pins output a pulse signal from timer Q0 (TMQ0).
(iv) DDI (Debug data input) … input
This pin inputs debug data to the on-chip debug circuit.
For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(v) DDO (Debug data output) … output
This pin outputs debug data from the on-chip debug circuit.
For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(iv) DCK (Debug clock input) … input
This pin inputs a debug clock to the on-chip debug circuit.
For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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(vii) DMS (Debug mode select) … input
This pin selects the debug mode of the on-chip debug circuit.
For details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(6) P70 to P715 (Port 7) … 3-state I/O
P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,
PM7H).
(b) Control mode
P70 to P715 function alternately as the ANI0 to ANI15 pins.
(i) ANI0 to ANI15 (Analog input 0 to 15) … input
These pins input an analog signal to the A/D converter.
(7) P90 to P915 (Port 9) … 3-state I/O
P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by using INTR9H and INTF9H registers.
An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).
(a) Port mode
P90 to P915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (PM9).
(b) Control mode
(i) SIB1 (Serial input) … input
This pin inputs the serial receive data of CSIB1.
(ii) SOB1 (Serial output) … output
This pin outputs the serial receive data of CSIB1.
(iii) SCKB1 (Serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB1.
(iv) RXDA1 (Receive data) … input
This pin inputs the serial receive data of UARTA1.
(v) TXDA1 (Transmit data) … output
This pin outputs the serial transmit data of UARTA1.
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(vi) TIP20, TIP21 (Timer input) … input
These pins input timers P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) … output
These pins output a pulse signal from timers P2 (TMP2).
(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) … input
These pins input to timers Q1 (TMQ1), respectively.
(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) … output
These pins output a pulse signal from timers Q1 (TMQ1), respectively.
(x) PCL (Clock output) … output
This pin outputs a clock.
(xi) INTP4 to INTP6 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(xii) KR6, KR7 (Key return) … input
These pins input a key interrupt. Their operation is specified by key return mode register (KRM) in the
input port mode.
(8) PCM0 to PCM3 (port CM) … 3-state I/O
PCM0 to PCM3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as bus clock output.
(a) Port mode
PCM0 to PCM3 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) CLKOUT (Clock output) … output
This pin outputs an internally generated bus clock.
(9) PCS0, PCS1 (Port CS) … 3-state I/O
PCS0 and PCS1 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCS0 and PCS1 can be set in the input or output mode in 1-bit units, by using port mode register CS
(PMCS).
(10) PCT0, PCT1, PCT4, PCT6 (Port CT) … 3-state I/O
PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCT0, PCT1, PCT4, and PCT6 can be set in the input or output mode in 1-bit units, by using port mode
register CT (PMCT).
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(11) PDL0 to PDL13 (port DL) … 3-state I/O
PDL0 to PDL13 function as a 14-bit I/O port that can be set to input or output in 1-bit units.
PDL5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input to
FLMD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL13 can be set in the input or output mode in 1-bit units, by using port mode register DL
(PMDL).
(12) RESET (Reset) … input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
(13) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
(14) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(15) AVSS (Ground for analog)
This is a ground pin for the A/D converter, and alternate-function ports.
(16) AVREF0 (Analog reference voltage) … input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(17) EVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(18) EVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(19) VDD (Power supply)
This pin supplies positive power. Connect all the VDD pins to a positive power supply.
(20) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(21) FLMD0 (Flash programming mode) Input
This is a signal input pin for flash memory programming mode. Connect this pin to VSS in the normal operation
mode.
(22) BVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(23) BVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(24) REGC (Regulator control) … input
This pin connects a capacitor for the regulator.
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2.3.4 V850ES/FJ2
(1) P00 to P06 (port 0) … 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) … input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (Interrupt request from peripherals) … input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) … input
These pins input to timers P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) … output
These pins output from timers P3 (TMP3).
(v) ADTRG (A/D trigger input) … input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) … input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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(2) P10, P11 (port 1) … 3-state I/O
P10 and P11 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request input in the control mode.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
INTR1 and INTF1 registers.
An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).
(a) Port mode
P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).
(b) Control mode
(i) INTP9, INTP10 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(3) P30 to P39 (port 3) … 3-state output
P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, timer/counter I/O, and CAN data I/O. This port can be set in the port mode or control mode in 1-bit units.
The valid edge of each pin is specified by using INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).
(a) Port mode
P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).
(b) Control mode
(i) RXDA0, RXDA2 (Receive data) … input
These pins input the serial receive data of UARTA0 and UARTA2.
(ii) TXDA0, TXDA2 (Transmit data) … output
These pins output the serial transmit data of UARTA0 and UARTA2.
(iii) ASCKA0 (Asynchronous serial clock) … input
This pin inputs of UARTA0.
(iv) INTP7, INTP8 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) … input
These pins input to timers P0 and P1 (TMP0, TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) … output
These pins output from timers P0 and P1 (TMP0, TMP1).
(vii) CRXD0, CRXD1 (CAN receive data) … input
These pins input the receive data of CAN0 and CAN1.
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(viii) CTXD0, CTXD1 (CAN transmit data) … output
These pins output the transmit data of CAN0 and CAN1.
(4) P40 to P42 (port 4) … 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) … input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) … output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) … 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
(5) P50 to P55 (Port 5) … 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as an I/O port, but also as timer/counter I/O, debug
function I/O, and key interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) … input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) … input
These pins input to timers Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) … output
These pins output from timers Q0 (TMQ0).
(iv) DDI (Debug data input) … input
This pin inputs debug data to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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(v) DDO (Debug data output) … output
This pin outputs debug data from the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(iv) DCK (Debug clock input) … input
This pin inputs a debug clock to the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(vii) DMS (Debug mode select) … input
This pin selects the debug mode of the on-chip debug circuit.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
(6) P60 to P615 … 3-state I/O
P60 to P615 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, timer/counter
I/O, and CAN data I/O. P60 to P62 can be set in the port mode or control mode in 1-bit units. The valid edge
of each pin is specified by INTR6L and INTF6L registers.
(a) Port mode
P60 to P65 can be set in the input or output mode in 1-bit units, by using port mode register 6 (PM6).
(b) Control mode
(i) INTP11 to INTP13 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(ii) TIQ20, TIQ21, TIQ22, TIQ23 (Timer input) … input
These pins input to timers Q2 (TMQ2).
(iii) TOQ20, TOQ21, TOQ22, TOQ23 (Timer output) … input
These pins output from timers Q2 (TMQ2).
(iv) CRXD2, CRXD3 (CAN receive data)Note … input
These pins input the receive data of CAN2 and CAN3.
(v) CTXD2, CTXD3 (CAN transmit data)Note … output
These pins output the transmit data of CAN2 and CAN3.
Note In the µPD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and
CRXD3) are not available.
(7) P70 to P715 (Port 7) … 3-state I/O
P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode register 7L, H (PM7L,
PM7H).
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(b) Control mode
P70 to P715 function alternately as the ANI0 to ANI15 pins.
(i) ANI0 to ANI15 (Analog input 0 to 15) … input
These pins input an analog signal to the A/D converter.
(8) P80 and P81 (port 8) … 3-state I/O
P80 and P81 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, and serial
interface I/O. P80 and P81 can be set in the port mode or control mode in 1-bit units. The valid edge of each
pin is specified by INTR8 and INTF8 registers.
An on-chip pull-up resistor can be connected to P80 and P81 by using pull-up resistor option register 8 (PU8).
(a) Port mode
P80 and P81 can be set in the input or output mode in 1-bit units, by using port mode register 8 (PM8).
(b) Control mode
(i) INTP14 (Interrupt request from peripherals) … input
This pin inputs an external interrupt request signal.
(ii) RXDA3 (Receive data)Note … input
This pin inputs the serial receive data of UARTA3.
(iii) TXDA3 (Transmit data)Note … output
This pin outputs the serial transmit data of UARTA3.
Note In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are
not available. The alternate function of the P80 pin in the µPD70F3237 is INTP14 only.
(9) P90 to P915 (Port 9) … 3-state I/O
P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by using INTF9H register.
An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).
(a) Port mode
P90 to P915 can be set in the input or output mode in 1-bit units, by using port 9 mode register (PM9).
(b) Control mode
(i) SIB1, SIB2 (Serial input) … input
These pins input the serial receive data of CSIB1 and CSIB2.
(ii) SOB1, SOB2 (Serial output) … output
These pins output the serial receive data of CSIB1 and CSIB2.
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(iii) SCKB1, SCKB2 (Serial clock) … 3-state I/O
These pins input/output the serial clock of CSIB1 and CSIB2.
(iv) RXDA1 (Receive data) … input
This pin inputs the serial receive data of UARTA1.
(v) TXDA1 (Transmit data) … output
This pin outputs the serial transmit data of UARTA1.
(vi) TIP20, TIP21 (Timer input) … input
These pins input timers P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) … output
These pins output from timers P2 (TMP2).
(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) … input
These pins input an external count clock to timers Q1.
(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) … output
These pins output a pulse signal from timers Q1.
(x) PCL (Clock output) … output
This pin outputs a clock.
(xi) INTP4 to INTP6 (Interrupt request from peripherals) … input
These pins input an external interrupt request signal.
(xii) KR6, KR7 (Key return) … input
These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in
the input port mode.
(10) P120 to P127 (Port 12) … 3-state I/O
P120 to P127 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P120 to P127 can be set in the input or output mode in 1-bit units, by using port mode register 12 (PM12).
(b) Control mode
P120 to P127 function alternately as the ANI16 to ANI23 pins.
(i) ANI16 to ANI23 (Analog input 16 to 23) … input
These pins input an analog signal to the A/D converter.
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(11) PCD0 to PCD3 (port CD) … 3-state I/O
PCD0 to PCD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCD0 to PCD3 can be set in the input or output mode in 1-bit units, by using port mode register CD
(PMCD).
(12) PCM0 to PCM5 (port CM) … 3-state I/O
PCM0 to PCM5 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as bus hold control signal I/O, bus clock output, and a
control signal that inserts a wait cycle in the bus cycle (WAIT), in the control mode.
(a) Port mode
PCM0 to PCM5 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) HLDAK (Hold acknowledge) … output
This pin outputs an acknowledge signal that indicates that the V850ES/FJ2 has placed the address
bus, data bus, and control bus in a high-impedance state in response to a bus hold request.
While this signal is active, the address bus, data bus, and control bus go into a high-impedance state.
(ii) HLDRQ (Hold request) … input
An external device uses this input pin to request the V850ES/FJ2 to release the address bus, data
bus, and control bus. A signal can be input to this pin asynchronously to CLKOUT. When this pin is
asserted, the V850ES/FJ2 places the address bus, data bus, and control bus in a high-impedance
state after completion of a bus cycle under execution, if any, or immediately if no such bus cycle is
under execution. The V850ES/FJ2 then asserts the HLDAK signal and releases the buses.
(iii) CLKOUT (Clock output) … output
This pin outputs an internally generated bus clock.
(iv) WAIT (Wait) … input
This is a control signal input pin that inserts a data wait state in the bus cycle. A signal can be input to
this pin asynchronously to the CLKOUT signal. The signal input to this pin is sampled at the falling
edge of the CLKOUT signal in the T2 and TW states of the bus cycle in the multiplexed mode. No wait
state may be inserted if the setup/hold time of the sampling timing is not satisfied.
The wait function is set to on or off by port mode control register CM (PMCCM).
(13) PCS0 to PCS7 (port CS) … 3-state I/O
PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as chip select signal output in the control mode.
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(a) Port mode
PCS0 to PCS7 can be set in the input or output mode in 1-bit units, by using port mode register CS
(PMCS).
(b) Control mode
(i) CS0 to CS3 (Chip select input) … output
These pins output a chip select signal to external memory and external peripheral I/O.
The CSn signal is assigned to memory block n (n = 0 to 3).
This signal is asserted while a bus cycle for accessing the corresponding memory block is being
executed.
This signal is deasserted in the idle state (TI).
(14) PCT0 to PCT7 (port CT) … 3-state I/O
PCT0 to PCT7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as control signal output in the control mode when
memory is externally expanded.
(a) Port mode
PCT0 to PCT7 can be set in the input or output mode in 1-bit units, by using port mode register CT
(PMCT).
(b) Control mode
(i) WR0 (Lower byte write strobe) … output
This pin outputs the write strobe signal of the lower data of the external 16-bit data bus.
(ii) WR1 (Upper byte write strobe) … output
This pin outputs the write strobe signal of the higher data of the external 16-bit data bus.
(iii) RD (Read strobe) … output
This pin outputs the read strobe signal of the external 16-bit data bus.
(iv) ASTB (Address strobe) … output
This pin outputs the latch strobe signal of the external address bus. The signal output from this pin
goes low at the falling edge of the T1 state of the bus cycle, and goes high at the falling edge of the
T3 state. It goes high while the bus cycle is not active.
(15) PDL0 to PDL15 (port DL) … 3-state I/O
PDL0 to PDL15 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as a time-division address/data bus (AD0 to AD15)
when the memory is externally expanded.
PDL5/AD5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input
to FLD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL15 can be set in the input or output mode in 1-bit units, by using port mode register DL
(PMDL).
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(b) Control mode
(i) AD0 to AD15 (Address/Data Bus 0 to 15) … 3-state I/O
This is a multiplexed address/data bus for external access.
(16) RESET (Reset) … input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
(17) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
(18) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(19) AVSS (Ground for analog)
This is a ground pin for the A/D converter, and alternate-function ports.
(20) AVREF0 (Analog reference voltage) … input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(21) EVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(22) EVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(23) VDD (Power supply)
This pin supplies positive power. Connect all the VDD pins to a positive power supply.
(24) VSS (Ground)
This is a ground pin. Connect all the VSS pins to ground.
(25) FLMD0 (Flash programming mode) Input
This is a signal input pin for flash memory programming mode. Connect this pin to VSS in the normal operation
mode.
(26) BVDD (Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
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(27) BVSS (Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(28) REGC (Regulator control) … input
This pin connects a capacitor for the regulator.
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2.4 Pin I/O Circuit Types and Recommended Connection of Unused Pins
2.4.1
V850ES/FE2
(1/2)
Pin
I/O Circuit
Type
Recommended Connection
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
5-AF
5-W
Input: Independently connect to EVSS
Output: Leave open
P06/INTP3
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P30/TXDA0
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/ TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
5-W
P40/SIB0
5-W
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P41/SOB0
P42/SCKB0
5-W
5-W
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P55/KR5/DMS
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(2/2)
Pin
I/O Circuit
Type
Recommended Connection
P70/ANI0 to P79/ANI9
11-G
Input: Independently connect to AVREF0 or AVSS via a resistor
Output: Leave open
P90/KR6/TXDA1
P91/KR7/RXDA1
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
P98/SOB1
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
5-A
5-W
5-W
P99/SCKB1
P913/INTP4/PCL
P914/INTP5
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P915/INTP6
PCM0
5
5
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
PCM1/CLKOUT
PDL0 to PDL4
PDL5/FLMD1
PDL6, PDL7
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
AVREF0
−
−
Directly connect to VDD
AVSS
FLMD0Note
REGC
RESET
X1
−
−
Directly connect to VSS
−
−
2
−
−
−
X2
−
−
XT1
16
16
−
Connect to VSS via a resistor
XT2
Leave open
VDD
−
−
−
−
VSS
−
EVDD
EVSS
−
−
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
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2.4.2 V850ES/FF2
(1/2)
Pin
I/O Circuit
Type
Recommended Connection
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
5-AF
5-W
Input: Independently connect to EVSS
Output: Leave open
P06/INTP3
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P30/TXDA0
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/ TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
P38
5-W
5-A
5-W
5-W
5-A
P39
P40/SIB0
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P41/SOB0
P42/SCKB0
5-W
5-W
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P55/KR5/DMS
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(2/2)
Pin
I/O Circuit
Type
Recommended Connection
P70/ANI0 to P711/ANI11
11-G
Input: Independently connect to AVREF0 or AVSS via a resistor
Output: Leave open
P90/KR6/TXDA1
P91/KR7/RXDA1
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
P98/SOB1
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
5-A
5-W
5-W
P99/SCKB1
P913/INTP4/PCL
P914/INTP5
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P915/INTP6
PCM0
5
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
PCM1/CLKOUT
PCM2, PCM3
PCS0, PCS1
5
5
5
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
PCT0. PCT1, PCT4, PCT6
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
PDL0 to PDL4
PDL5/FLMD1
PDL6 to PDL11
AVREF0
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
−
−
Directly connect to VDD
AVSS
FLMD0Note
REGC
RESET
X1
−
−
Directly connect to VSS
−
−
2
−
−
−
X2
−
−
XT1
16
16
−
Connect to VSS via a resistor
XT2
Leave open
VDD
−
−
−
−
VSS
−
EVDD
EVSS
−
−
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
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2.4.3 V850ES/FG2
(1/2)
Pin
I/O Circuit
Type
Recommended Connection
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
5-AF
5-W
5-W
Input: Independently connect to EVSS via a resistor
Output: Leave open
P06/INTP3
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P10/INTP9
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P11/INTP10
P30/TXDA0
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
P36/CTXD1
5-W
5-A
5-W
5-A
P37/CRXD1
P38/TXDA2
P39/RXDA2/INTP8
P40/SIB0
5-W
5-W
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P41/SOB0
P42/SCKB0
5-W
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P55/KR5/DMS
P70/ANI0 to P711/ANI11
P712/ANI12 to P715/ANI15
P90/KR6/TXDA1
11-G
5-W
Input: Independently connect to AVREF0 or AVSS via a resistor
Output: Leave open
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P91/KR7/RXDA1
P92/TIQ11/TOQ11
P93/TIQ12/TOQ12
P94/TIQ13/TOQ13
P95/TIQ10/TOQ10
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(2/2)
Pin
I/O Circuit
Type
Recommended Connection
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
P98/SOB1
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
5-A
5-W
5-A
P99/SCKB1
P910
P911
P912
P913/INTP4/PCL
P914/INTP5
P915/INTP6
PCM0
5-W
5
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PCM1/CLKOUT
PCM2, PCM3
PCS0, PCS1
5
5
5
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PCT0, PCT1, PCT4,
PCT6
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PDL0 to PDL4
PDL5/ FLMD1
PDL6 to AD13
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
AVREF0
AVSS
FLMD0Note
REGC
RESET
X1
−
−
Directly connect to VDD
−
−
Directly connect to VSS
−
−
2
−
−
−
X2
−
−
XT1
16
16
−
Connect to VSS via a resistor
XT2
Leave open
VDD
−
−
−
−
−
−
VSS
−
BVDD
BVSS
EVDD
EVSS
−
−
−
−
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
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2.4.4 V850ES/FJ2
(1/4)
Pin
I/O Circuit
Type
Recommended Connection
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
5-AF
5-W
5-W
Input: Independently connect to EVSS
Output: Leave open
P06/INTP3
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P10/INTP9
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P11/INTP10
P30/TXDA0
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/ TOP01
P33/TIP01/TOP01/CTXD0
P34/TIP10/TOP10/CRXD0
P35/TIP11/TOP11
P36/CTXD1
5-W
5-A
5-W
5-A
P37/CRXD1
P38/TXDA2Note
P39/RXDA2/INTP8Note
5-W
5-W
5-A
P40/SIB0
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P41/SOB0
P42/SCKB0
5-W
5-W
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P55/KR5/DMS
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(2/4)
Pin
I/O Circuit
Type
Recommended Connection
P60/INTP11
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P61/INTP12
P62/INTP13
P63
5-A
P64
P65/CTXD2Note1
P66/CRXD2Note1
P67/CTXD3Note1
P68/CRXD3Note1
P69
5-W
5-A
5-W
5-A
P610/TIQ20/TOQ20
P611/TIQ21/TOQ21
P612/TIQ22/TOQ22
P613/TIQ23/TOQ23
P614
5-W
5-A
P615
P70/ANI0 to P79/ANI9
P710/ANI10, P11/ANI11
P712/ANI12 to P715/ANI15
P80/RXDA3/INTP14Note2
P81/TXDA3Note2
P90/KR6/TXDA1
P91/KR7/RXDA1
P92/TIQ11/TOQ11
P93/TIQ12/TOQ12
P94/TIQ13/TOQ13
P95/TIQ10/TOQ10
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
P98/SOB1
11-G
Input: Independently connect to AVREF0 or AVSS via a resistor
Output: Leave open
5-W
5-A
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
5-A
P99/SCKB1
5-W
P910/SIB2
P911/SOB2
5-A
P912/SCKB2
5-W
Notes 1. In the µPD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, and
CRXD3) are not available.
2. In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not
available.
The alternate function of the P80 pin in the µPD70F3237 is only INTP14.
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(3/4)
Pin
I/O Circuit
Type
Recommended Connection
P913/INTP4/PCL
P914/INTP5
5-W
Input: Independently connect to EVDD or EVSS via a resistor
Output: Leave open
P915/INTP6
P120/ANI16 to P127/ANI23
11-G
Input: Independently connect to AVREF0 or AVSS via a resistor
Output: Leave open
PCD0 to PCD3
5
5
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PCM0/WAIT
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PCM1/CLKOUT
PCM2/HLDAK
PCM3/HLDRQ
PCM4
PCM5
PCS0/CS0, PCS3/CS1
PCS0/CS2, PCS3/CS3,
PCS4 to PCS7
PCT0/WR0
5
5
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
PCT1/WR1
PCT2
PCT3
PCT4/RD
PCT5
PCT6/ASTB
PCT7
PDL0/AD0 to PDL4/AD4
PDL5/AD5/FLMD1
PDL6/AD6, PDL7/AD7
PDL8/AD8 to PDL11/AD11
PDL12/AD12, PDL13/AD13
PDL14/AD14, PDL15/AD15
5
Input: Independently connect to BVDD or BVSS via a resistor
Output: Leave open
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(4/4)
Pin
I/O Circuit
Type
Recommended Connection
AVREF0
AVSS
FLMD0Note
REGC
RESET
X1
−
−
Directly connect to VDD
Directly connect to VSS
−
−
−
−
−
−
−
2
−
X2
−
XT1
16
16
−
Connect to VSS via a resistor
Leave open
XT2
VDD
−
−
−
−
−
−
VSS
−
BVDD
BVSS
EVDD
EVSS
−
−
−
−
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
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2.5 Pin I/O Circuits
Figure 2-1. Pin I/O Circuit Types (1/2)
Type 2
Type 5-AF
V
DD
Pullup
enable
P-ch
V
DD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Input enable
N-ch
Schmitt-triggered input with hysteresis characteristics
Pulldown
enable
Type 5
Data
Type 11-G
Data
AVREF0
P-ch
V
DD
IN/OUT
P-ch
Output
disable
N-ch
IN/OUT
AVSS
Output
disable
P-ch
N-ch
Comparator
N-ch
+
_
V
REF
Input
enable
(Threshold voltage)
AVSS
Input enable
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Figure 2-1. Pin I/O Circuit Types (2/2)
Type 5-A
Type 16
VDD
Feedback cut-off
P-ch
Pullup
enable
P-ch
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
XT1
XT2
Input
enable
Type 5-W
V
DD
Pullup
enable
P-ch
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
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CHAPTER 3 CPU FUNCTIONS
Based on the RISC architecture, the CPU of the V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 executes
most of the instructions in one clock under control of a five-stage pipeline.
3.1 Features
{ Minimum instruction execution time: 50 ns (at 20 MHz operation)
{ Memory space Program space: 64 MB, linear
Data space:
4 GB, linear
{ General-purpose registers: 32 bits × 32
{ Internal 32-bit architecture
{ Five-stage pipeline control
{ Multiplication/division instructions
{ Saturation operation instructions
{ 32-bit shift instructions: 1 clock
{ Load/store instructions with long/short format
{ Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
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3.2 CPU Register Set
The registers of the V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 can be classified into two types:
general-purpose program registers and dedicated system registers. All the registers are 32 bits wide.
For details, refer to V850ES Architecture User’s Manual.
(2) System register set
(1) Program register set
31
r0
0
31
EIPC
0
(Zero register)
(Status saving register on interrupt)
(Status saving register on interrupt)
(Assembler-reserved register)
r1
EIPSW
r2
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
r3
(Status saving register on NMI)
FEPC
r4
FEPSW (Status saving register on NMI)
r5
r6
(Interrupt source register)
(Program status word)
ECR
PSW
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
(Status saving register on CALLT execution)
(Status saving register on CALLT execution)
CTPC
CTPSW
(Status saving register on exception/debug trap)
(Status saving register on exception/debug trap)
DBPC
DBPSW
(CALLT base pointer)
CTBP
(Element pointer (EP))
(Link pointer (LP))
31
PC
0
(Program counter)
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3.2.1 Program register set
The program registers include general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used for a data
variable or address variable.
However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers.
Register r0 always holds 0, and is used for an operation using 0 or addressing with offset 0. Register r30 is
used as a base pointer when the SLD or SST instruction is used to access the memory. Registers r1, r3 to r5,
and r31 are implicitly used by the assembler and C compiler. When using these registers, therefore, their
contents must be saved so that they are not lost, and later restored to the registers. Register r2 may be used
by a real-time OS. If the real-time OS used does not use r2, r2 can be used as a register for variables.
Table 3-1. Program Register List
Name
Usage
Zero register
Assembler-reserved register
Register for address/data variable (if the real-time OS used does not use r2)
Operation
r0
r1
r2
r3
r4
r5
Always holds 0.
Used as a working register for creating 32-bit immediate
Stack pointer
Global pointer
Text pointer
Used to generate a stack frame when a function is called
Used to access a global variable in the data area
Used as a register that points to the beginning of a text area
(area where program codes are located)
r6 to r29
r30
Registers for address/data variable
Element pointer
Used as a base pointer when memory is accessed
Used when the compiler calls a function
r31
Link pointer
PC
Program counter
Holds an instruction address during program execution
Remark For further details on the r1, r3 to r5, and r31that are used in the assembler and C compiler, refer to the
CA850 (C Compiler Package) Assembly Language of the user’s Manual.
(2) Program counter (PC)
The program counter holds an instruction address during program execution. The lower 26 bits of this counter
are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to bit 26 is ignored.
Bit 0 is always fixed to 0, and execution cannot branch to an odd address.
31
2625
1 0
0
Default value
00000000H
PC
Fixed to 0
Instruction address during program execution
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3.2.2 System register set
The system registers are used to control the status of the CPU or to hold interrupt information.
Data can be read from or written to system registers by setting one of the system register numbers listed below
using a system register load or store (LDSR or STSR) instruction.
Table 3-2. System Register Numbers
Register No.
System Register Name
Operand Specification
LDSR
STSR
Instruction
Instruction
0
Interrupt status saving register (EIPC)Note 1
√
√
√
√
×
√
×
√
√
√
√
√
√
×
1
Interrupt status saving register (EIPSW)Note 1
NMI status saving register (FEPC)
NMI status saving register (FEPSW)
Interrupt source register (ECR)
2
3
4
5
Program status word (PSW)
6 to 15
Reserved for future function expansion. (Operation is not guaranteed if these
registers are accessed.)
16
17
CALLT execution status saving register (CTPC)
CALLT execution status saving register (CTPSW)
Exception/debug trap status saving register (DBPC)
Exception/debug trap status saving register (DBPSW)
CALLT base pointer (CTBP)
√
√
√
√
√
√
√
×
Note 2
18
√
Note 2
19
√
20
√
×
21 to 31
Reserved for future function expansion. (Operation is not guaranteed if these
registers are accessed.)
Notes 1. Because only one pair of these registers is provided, the contents of these registers must be saved by
program when multiple interrupt servicing is enabled.
2. These registers can be accessed only between DBTRAP or the illegal instruction execution and DBRET
instruction execution.
Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution returns from interrupt servicing to the main routine by the RETI instruction (this is
because bit 0 of the PC is fixed to 0). When setting a value to EIPC, FEPC, or CTPC, set an even
value (bit = 0).
Remark √: Accessible
×: Access prohibited
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(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are interrupt status saving registers.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to
EIPC, and the contents of the program status word (PSW) are saved to EIPSW. (The contents of the PC and
PSW are saved to FEPC and FEPSW (NMI status saving registers) if a non-maskable interrupt (NMI) occurs.)
The address of the instruction next to the one under execution, except some instructions (see 17.7 Periods in
Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception or a maskable
interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one pair of interrupt status saving registers is available, the contents of these registers must be
saved by program if multiple interrupt servicing is enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are fixed
to 0). The values of EIPC restore the PC, and the values of EIPSW do to the PSW by the RETI instruction.
31
2625
0
0
0
Default value
0xxxxxxxH
(x: undefined)
EIPC
0 0
0
0
0
0
0
(Contents of PC)
31
8 7
0
Default value
000000xxH
(x: undefined)
EIPSW
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Contents of PSW)
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(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are NMI status saving registers.
If a non-maskable interrupt (NMI) occurs, the contents of the program counter (PC) are saved to FEPC, and
the contents of the program status word (PSW) are saved to FEPSW.
The address of the instruction next to the one under execution, except some instructions, is saved to FEPC.
The current contents of the PSW are saved to FEPSW.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are
fixed to 0).
31
2625
0
Default value
0xxxxxxxH
(x: undefined)
FEPC
0 0 0 0 0 0
(Contents of PC)
31
8 7
0
Default value
000000xxH
(x: undefined)
FEPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Contents of PSW)
(3) Interrupt source register (ECR)
The interrupt source register ECR holds the source of an exception or an interrupt that has occurred. The
value ECR is to hold is an exception code for each interrupt source. This register is a read-only register. No
data can be written to this register by using the LDSR instruction.
31
1615
0
Default value
00000000H
ECR
FECC
EICC
Bit Position
31 to 16
15 to 0
Bit Name
FECC
Meaning
Exception code of non-maskable interrupt (NMI)
Exception code of exception or maskable interrupt
EICC
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(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the status of the program (result of
instruction execution) or the CPU.
If the contents of any bit of this register are changed by using the LDSR instruction, the new contents become
valid immediately after execution of the LDSR instruction. When the ID flag is set to 1, however,
acknowledgment of an interrupt request is disabled from when the LDSR instruction is still under execution.
Bits 31 to 8 are reserved for future function expansion (these bits are fixed to 0).
31
8 7 6 5 4 3 2 1 0
Default value
00000020H
PSW
RFU
NP EP ID SAT CY OV S Z
Bit Position Flag Name
Meaning
31 to 8
7
RFU
NP
Reserved field. Always fixed to 0
Indicates that a non-maskable interrupt (NMI) is being serviced. This flag is set to 1, disabling
multiple interrupt servicing, when an NMI request is acknowledged.
0: NMI is not being serviced.
1: NMI is being serviced.
6
EP
Indicates that exception processing is in progress. This flag is set to 1 when an exception is
generated. Interrupt requests are acknowledged even if this bit is set.
0: Exception is not being processed.
1: Exception is being processed.
5
4
ID
Indicates whether a maskable interrupt request can be acknowledged.
0: Interrupts enabled
1: Interrupts disabled
SATNote
Indicates that the result of an operation of a saturation operation instruction overflows and that
the operation result is saturated. Because this is a cumulative flag, it is set to 1 if the operation
result of a saturation operation instruction is saturated, and is not cleared to 0 even if the
operation result of the subsequent instructions is not saturated. This flag is cleared to 0 by the
LDSR instruction. When an arithmetic operation instruction is executed, this flag is neither set
to 1 nor cleared to 0.
0: Not saturated
1: Saturated
3
2
1
0
CY
Indicates whether a carry or a borrow occurred as a result of an operation.
0: Carry or borrow did not occur.
1: Carry or borrow occurred.
OVNote
SNote
Z
Indicates whether an overflow occurred during an operation.
0: Overflow did not occur.
1: Overflow occurred.
Indicates whether the result of an operation is negative or not.
0: Operation result is positive or 0.
1: Operation result is negative.
Indicates whether the result of an operation is 0 or not.
0: Result of operation is not 0.
1: Result of operation is 0.
Remark Refer to the next page for the explanation of Note.
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(2/2)
Note The result of an operation of saturation processing is determined by the contents of the OV and S flags when a
saturation operation is performed. The SAT flag is set to 1 only when the OV flag is set to 1 as a result of a
saturation operation.
Status of Operation
Result
Flag Status
OV
Result of Operation of Saturation
Processing
SAT
S
Maximum positive
value is exceeded.
1
1
1
1
0
0
1
0
1
7FFFFFFFH
Maximum negative
value is exceeded.
80000000H
Positive (maximum
value not exceeded)
Holds value
before
Operation result itself
operation.
Negative (maximum
value not exceeded)
(5) CALLT execution status saving registers (CTPC and CTPSW)
CTPC and CTPSW are CALLT execution status saving registers.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and
the contents of the program status word (PSW) are saved to CTPSW.
The contents saved to CTPC are the address of the instruction next to the CALLT instruction.
The current contents of the PSW are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (these bits are
fixed to 0).
31
2625
0
Default value
0xxxxxxxH
CTPC
0 0 0 0 0 0
(Contents of PC)
(x: undefined)
31
8 7
0
Default value
000000xxH
(x: undefined)
CTPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Contents of PSW)
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(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status saving registers.
If an exception trap or a debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and
the contents of the program status word (PSW) are saved to DBPSW.
The contents saved to DBPC are the address of the instruction next to the one under execution when an
exception trap or a debug trap has occurred.
The current contents of the PSW are saved to DBPSW.
These registers can be accessed only between DBTRAP or the illegal instruction execution and DBRET
instruction execution.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (these bits are
fixed to 0).
The values of DBPC restore PC, and the values of DBPSW do to PSW by DBRET instruction.
31
2625
0
0
Default value
0xxxxxxxH
(x: undefined)
DBPC
0 0 0 0 0 0
(Contents of PC)
31
8 7
Default value
000000xxH
DBPSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Contents of PSW)
(x: undefined)
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or to generate a target address (bit 0 is
fixed to 0).
Bits 31 to 26 of this register are reserved for future function expansion (these bits are fixed to 0).
31
2625
0
0
0
Default value
0xxxxxxxH
(x: undefined)
CTBP
0 0
0 0 0
(Base address)
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3.3 Operation Modes
The V850ES/Fx2 have the following operation modes.
FLMD0
FLMD1
Operation Mode
Normal operation mode
0
1
1
X
0
1
Flash memory programming mode
Setting prohibited
Remark x: don't care
(1) Normal operation mode
After system reset is released, each pin related to the bus interface is set in the port mode, execution branches
to the reset entry address of the internal ROM, and instruction processing is started. When the PMCDL,
PMCCM, PMCCS, and PMCCT registers are set in the control mode by software, an external device can be
connected to the external memory area.
(2) Flash memory programming mode
When this mode is specified, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/FJ2 is provided with an on-chip debug function that employ the JTAG (Joint Test Action Group)
communication specifications and that is executed via an N-Wire emulator. For details, see CHAPTER 27 ON-
CHIP DEBUG FUNCTION."
3.3.1 Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins. In the normal mode, make sure that the
FLMD0/IC pin goes low when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
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3.4 Address Space
3.4.1 CPU address space
The CPU of the V850ES/Fx2 has 32-bit architecture, and supports a linear address space (data space) of up to 4
GB for operand addressing (data access). It also supports a linear address space (program space) of up to 64 MB for
addressing instruction addresses. However, both the program and data spaces have areas prohibited from being
used. For details, refer to Figure 3-2.
Figure 3-1 illustrates the CPU address space.
Figure 3-1. CPU Address Space
CPU address space
F F F F F F F F H
Data area
(4 GB, linear)
0 4 0 0 0 0 0 0 H
0 3 F F F F F F H
Program area
(64 MB, linear)
0 0 0 0 0 0 0 0 H
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3.4.2 Image
Up to 16 MB of external memory area, internal ROM area, and internal RAM area of up to 16 MB of linear address
space (program space) are supported for addressing of instruction addresses. Up to 4 GB of linear address space
(data space) are supported for operand addressing (data access). Note, however, that there seems to be sixty-four
64 MB physical address spaces on the 4 GB address space. This means that the same 64 MB physical address
space is accessed regardless of the value of bits 31 to 26.
Figure 3-2. Image on Address Space
Image 63
.
4 GB
.
.
Data space
Peripheral I/O area
Program space
Image 1
Internal RAM area
Use-prohibited area
Use-prohibited area
Internal RAM area
64 MB
Use-prohibited area
64 MB
External memory area
Image 0
External memory area
Internal ROM area
(external memory area)
16 MB
Internal ROM area
(external memory area)
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3.4.3 Wraparound of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid.
The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are
contiguous addresses. That the highest address and the lowest address of the program space are contiguous
in this way is called wraparound.
Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O
area, instructions cannot be fetched from this area. Therefore, do not execute an operation
in which the result of a branch address calculation affects this area.
Program space
0 0 0 0 0 0 0 1 H
0 0 0 0 0 0 0 0 H
(+) direction
(−) direction
0 3 F F F F F F H
0 3 F F F F F E H
Program space
(2) Data space
The result of an operand address calculation operation that exceeds 32 bits is ignored.
Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are
contiguous, and wraparound occurs at the boundary of these addresses.
Data space
0 0 0 0 0 0 0 1 H
0 0 0 0 0 0 0 0 H
(+) direction
(−) direction
F F F F F F F F H
F F F F F F F E H
Data space
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3.4.4 Memory map
The V850ES/Fx2 reserves the areas shown in Figure 3-3.
Figure 3-3. Data Memory Map (Physical Addresses)
3 F F F F F F H
3 F F F F F F H
On-chip peripheral I/O area
(4 KB)
3 F F F 0 0 0 H
3 F F E F F F H
(80 KB)
3 F E C 0 0 0 H
3 F E B F F F H
Internal RAM area
(60 KB)Note 1
3 F F 0 0 0 0 H
3 F E F F F F H
Use prohibited
Use prohibitedNote 2
3 F E F 0 0 0 H
3 F E E F F F H
Programmable peripheral
I/O area
1 0 0 0 0 0 0 H
0 F F F F F F H
3 F E C 0 0 0 H
External memory area
(8 MB)
0 8 0 0 0 0 0 H
0 7 F F F F F H
External memory area
(4 MB)
0 4 0 0 0 0 0 H
0 3 F F F F F H
0 1 F F F F F H
External memory area
(2 MB)
External memory area
(1 MB)
0 1 0 0 0 0 0 H
0 0 F F F F F H
0 2 0 0 0 0 0 H
0 1 F F F F F H
Internal ROM areaNote 3
(1 MB)
(2 MB)
0 0 0 0 0 0 0 H
0 0 0 0 0 0 0 H
Notes 1. V850ES/FE2: µPD703230: 4K, µPD70F3231: 6K are provided.
V850ES/FF2: µPD703232: 6K , µPD70F3232: 12K , µPD703232: 12K are provided
V850ES/FG2: µPD70F3234: 6K , µPD70F3235: 12K , µPD70F3236: 16K are provided
V850ES/FJ2: µPD70F3237: 12KB, µPD70F3238: 20KB, µPD703239: 20KB are provided.
2. Use of addresses 3FEF000H to 3FEFFFFH is prohibited because these addresses are in the same
area as the on-chip peripheral I/O area.
3. A fetch access and a read access to addresses 0000000H to 00FFFFFH is made to the internal
ROM area, but these addresses are used as an external memory area when a data write access is
made.
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Figure 3-4. Program Memory Map
0 3 F F F F F F H
Use prohibited
(program fetch prohibited area)
0 3 F F F 0 0 0 H
0 3 F F E F F F H
Internal RAM area (60 KB)
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
Use prohibited
(program fetch prohibited area)
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
External memory area
(14 MB)
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
External memory area
(1 MB)
Internal ROM area
(1 MB)
0 0 0 0 0 0 0 0 H
Remark Instructions can be executed in the external memory area without a branch from the internal ROM
area to the external memory area. For details, refer to 3.4.5 (2) Internal RAM area
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3.4.5 Areas
(1) Internal flash memory area
Up to 1 MB is reserved as an internal flash memory area.
(a) Internal Mask ROM memory area (64 KB)
64 KB, addresses 0000000H to 000FFFFH, are provided in the following products as an internal flash
memory area.
Accessing addresses 0001000H to 00FFFFFH is prohibited.
• V850ES/FE2: µPD703230
Figure 3-5. Internal Flash Memory Area (64 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 1 0 0 0 0 H
0 0 0 0 F F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(b) Internal flash memory area (128 KB)
128 KB, addresses 0000000H to 001FFFFH, are provided in the following products as an internal flash
memory area.
Accessing addresses 0020000H to 00FFFFFH is prohibited.
• V850ES/FE2: µPD70F3231
• V850ES/FF2: µPD70F3232
• V850ES/FG2: µPD70F3234
Figure 3-6. Internal Flash Memory Area (128 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 2 0 0 0 0 H
0 0 1 F F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(c) Internal flash memory area (256 KB)
256 KB, addresses 0000000H to 003FFFFH, are provided in the following products as an internal flash
memory area.
Accessing addresses 0040000H to 00FFFFFH is prohibited.
• V850ES/FF2: µPD70F3233
• V850ES/FG2: µPD70F3235
• V850ES/FJ2: µPD70F3237
Figure 3-7. Internal Flash Memory Area (256 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 4 0 0 0 0 H
0 0 3 F F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(d) Internal flash memory area (376 KB)
The following products have a 376 KB area of 00000000H to 0005DFFFH.
Use of addresses 005E000H to 00FFFFFH is prohibited.
• V850ES/FJ2: µPD70F3238
Figure 3-8. Internal Flash Memory Area (376 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 5 E 0 0 0 H
0 0 5 D F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(e) Internal flash memory area (384 KB)
The following products have a 384 KB area of 00000000H to 0005FFFFH.
Use of addresses 0060000H to 00FFFFFH is prohibited.
• V850ES/FG2: µPD70F3236
Figure 3-9. Internal Flash Memory Area (384 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 6 0 0 0 0 H
0 0 0 5 F F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(f) Internal flash memory area (512 KB)
512 KB, addresses 0000000H to 007FFFFH, are provided in the following product as an internal flash
memory area.
Accessing addresses 0080000H to 00FFFFFH is prohibited.
• V850ES/FJ2: µPD70F3239
Figure 3-10. Internal Flash Memory Area (512 KB)
0 0 F F F F F H
Access-prohibited
area
0 0 8 0 0 0 0 H
0 0 7 F F F F H
Internal flash memory
0 0 0 0 0 0 0 H
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(2)
Internal RAM area
Up to 60 KB are reserved as an internal RAM area.
(a) Internal RAM (4 KB)
The following product has a 4 KB area from addresses 3FFE000H to 3FFEFFFH. Use of addresses
3FF0000H to 3FFDFFFH is prohibited.
• V850ES/FE2: µPD703230
Figure 3-11. Internal RAM Area (4 KB)
3
F F E F F F
F F E 0 0 0
H
Internal RAM
3
3
H
H
F F
D F F F
A
cc
e
ss
-
p
r
ohibited
a
r
ea
3
F F 0 0 0 0
H
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(b) Internal RAM (6 KB)
The following products have a 6 KB area from addresses 3FFD800H to 3FFEFFFH. Use of addresses
3FF0000H to 3FFD7FFH is prohibited.
• V850ES/FE2: µPD70F3231
• V850ES/FF2: µPD703232
• V850ES/FG2: µPD70F3234
Figure 3-12. Internal RAM Area (6 KB)
3 F F E F F F H
Internal RAM
3 F F D 8 0 0 H
3 F F D 7 F F H
Access-prohibited
area
3 F F 0 0 0 0 H
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(c) Internal RAM (12 KB)
The following products have a 12 KB area from addresses 3FFC000H to 3FFEFFFH. Use of addresses
3FF0000H to 3FFBFFFH is prohibited.
• V850ES/FF2: µPD70F3232, µPD70F3233
• V850ES/FG2: µPD70F3235
• V850ES/FJ2: µPD70F3237
Figure 3-13. Internal RAM Area (12 KB)
3 F F E F F F H
Internal RAM
3 F F C 0 0 0 H
3 F F B F F F H
Access-prohibited
area
3 F F 0 0 0 0 H
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(d) Internal RAM (16 KB)
The following product has a 16 KB area from addresses 3FFb000H to 3FFEFFFH. Use of addresses
3FF0000H to 3FFAFFFH is prohibited.
• V850ES/FG2: µPD70F3236
Figure 3-14. Internal RAM Area (16 KB)
3 F F E F F F H
Internal RAM
3 F F B 0 0 0 H
3 F F A F F F H
Access-prohibited
area
3 F F 0 0 0 0 H
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(e) Internal RAM (20 KB)
The following products have a 20 KB area from addresses 3FFA000H to 3FFEFFFH. Use of addresses
3FF0000H to 3FF9FFFH is prohibited.
• V850ES/FJ2: µPD70F3238, µPD70F3239
Figure 3-15. Internal RAM Area (20 KB)
3 F F E F F F H
Internal RAM
3 F F A 0 0 0 H
3 F F 9 F F F H
Access-prohibited
area
3 F F 0 0 0 0 H
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(3) On-chip peripheral I/O area
4 KB, addresses 3FFF000H to 3FFFFFFH, are reserved as an on-chip peripheral I/O area.
Figure 3-16. On-Chip Peripheral I/O Area
3 F F F F F F H
On-chip peripheral I/O area
(4 KB)
3 F F F 0 0 0 H
Peripheral I/O registers that are used to specify the operation mode of and to monitor the status of the on-chip
peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. If a register is accessed in word units, a word area with the lower 2 bits of an address
ignored is accessed in halfword units in the order of the lower halfword and the higher
halfword.
2. If a register that can be accessed in bytes is accessed in halfwords, the higher 8 bits are
undefined when the register is read. Data is written to the lower 8 bits when a write
access is made to the register.
3. Addresses not defined as those of registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
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(4) Programmable peripheral I/O area
12 KB of addresses 03FEC000H to 03FEEFFFH are reserved as the programmable peripheral I/O area.
Figure 3-17. Programmable Peripheral I/O Area
03FEEFFFH
Programmable peripheral
I/O area
(12 KB)
0 3 F E C 0 0 0 H
Caution
The programmable peripheral I/O area is seen as images of 256 MB each in the 4 GB
address space.
(5) External memory area
An external memory area of 15 MB (0100000H to 0FFFFFFH) is available. For details, refer to CHAPTER 5
BUS CONTROL FUNCTION.
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3.4.6 Recommended use of address space
With the architecture of the V850ES/Fx2, a register that serves as a pointer must be secured for address
generation when operand data in the data space is to be accessed. The ±32 KB of this pointer register can be directly
accessed from an instruction for operand data. However, the number of general-purpose registers that can be used
as a pointer is limited. The number of general-purpose registers that can be allocated for variables can be maximized
and the program size can be reduced by suppressing a drop in performance due to address calculation when a
pointer value is to be changed.
(1) Program space
Of the 32 bits of the PC (program counter), only the lower 26 bits are valid and the higher 6 bits are fixed to 0.
Therefore, a contiguous 64 MB space, starting from address 00000000H, is mapped as a program space.
When using the internal RAM area as a program space, access the following addresses.
Caution The prefetch operation (invalid fetch) across internal peripheral I/O area is not generated if
there is a branch instruction in the upper-limit addresses of the internal RAM area.
RAM Size
20 KB
Addresses to Be Accessed
3FFA000H to 3FFEFFFH
16 KB
12 KB
6 KB
3FFB000H to 3FFEFFFH
3FFC000H to3FFEFFFH
3FFD800H to3FFEFFFH
3FFE000H to3FFEFFFH
4 KB
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(2) Data space
On the 4 GB CPU address space of the V850ES/Fx2, there seems to be sixty-four 64 MB physical address
spaces. Therefore, 26-bit addresses with the most significant bit (bit 25) sign-extended up to 32 bits in length
are allocated.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, the range of address 00000000H
±32 KB can be addressed by sign-extended disp16. All the resources of the internal hardware can be
addressed by using one pointer.
The zero register (r0) is fixed to 0 by hardware and a register used for a pointer is basically unnecessary.
Example: µPD70F3239
0 0 0 8 0 0 0 0 H
0 0 0 0 7 F F F H
32 KB
4 KB
Internal ROM area
0 0 0 0 0 0 0 0 H
(R = )
On-chip peripheral
I/O area
F F F F F 0 0 0 H
F F F F E F F F H
Internal RAM area
Use prohibited
20 KB
8 KB
F F F F A 0 0 0 H
F F F F 9 F F F H
F F F F 8 0 0 0 H
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Figure 3-18. Recommended Memory Map
Program space
Data space
F F F F F F F F H
On-chip
peripheral I/O
F F F F F 0 0 0 H
F F F F E F F F H
Internal RAM
x F F F F F F F H
F F F F C 0 0 0 H
F F F F B F F F H
On-chip
peripheral I/O
x F F F F 0 0 0 H
x F F F E F F F H
Internal RAM
x F F F 7 0 0 0 H
x F F F 6 F F F H
x F F E C 0 0 0 H
x F F E B F F F H
0 4 0 0 0 0 0 0 H
0 3 F F F F F F H
On-chip
peripheral I/ONote
0 3 F F F 0 0 0 H
0 3 F F E F F F H
Internal RAM
Use prohibited
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 3 F E C 0 0 0 H
0 3 F E B F F F H
Use prohibited
Program space,
64 MB
External memory
Internal ROM
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
x 0 1 0 0 0 0 0 H
x 0 0 F F F F F H
x 0 0 0 0 0 0 0 H
External
memory
0 0 0 2 0 0 0 0 H
0 0 0 1 F F F F H
Internal ROM
Internal ROM
0 0 0 0 0 0 0 0 H
Note Accessing this area is prohibited. To access on-chip peripheral I/O in this area, specify addresses
FFFF000H to FFFFFFFH.
Remarks 1. The upper and lower arrows indicate the area recommended to be used.
2. This figure is the recommended memory map of the uPD70F3238 and uPD79F0239.
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3.4.7 Peripheral I/O registers
3.4.7.1 V850ES/FE2
(1/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PDL
R/W
R/W
Default Value
1
8
16
FFFFF004H
FFFFF004H
FFFFF005H
FFFFF00CH
FFFFF024H
FFFFF024H
FFFFF025H
FFFFF02CH
FFFFF04CH
FFFFF064H
FFFFF06EH
FFFFF100H
FFFFF100H
FFFFF101H
FFFFF102H
FFFFF102H
FFFFF103H
FFFFF104H
FFFFF104H
FFFFF105H
FFFFF106H
FFFFF106H
FFFFF107H
FFFFF108H
FFFFF108H
FFFFF109H
Port DL
Undefined
Undefined
Undefined
Undefined
FFFFH
FFH
√
Port DLL
PDLL
√
√
√
√
√
√
Port DLH
PDLH
PCM
Port CM
Port mode register DL
Port mode register DLL
Port mode register DLH
Port mode register CM
Port mode control register CM
Peripheral I/O area select control register
System wait control register
Interrupt mask register 0
Interrupt mask register 0L
Interrupt mask register 0H
Interrupt mask register 1
Interrupt mask register 1L
Interrupt mask register 1H
Interrupt mask register 2
Interrupt mask register 2L
Interrupt mask register 2H
Interrupt mask register 3
Interrupt mask register 3L
Interrupt mask register 3H
Interrupt mask register 4
Interrupt mask register 4L
Interrupt mask register 4H
PMDL
PMDLL
PMDLH
PMCM
PMCCM
BPC
√
√
√
√
√
√
√
√
√
FFH
FFH
00H
0000H
77H
√
√
VSWC
IMR0
√
FFFFH
FFH
IMR0L
IMR0H
IMR1
√
√
√
√
FFH
FFFFH
FFH
√
√
√
√
IMR1L
IMR1H
IMR2
√
√
√
√
FFH
FFFFH
FFH
IMR2L
IMR2H
IMR3
√
√
√
√
FFH
FFFFH
FFH
IMR3L
IMR3H
IMR4
√
√
√
√
FFH
FFFFH
FFH
IMR4L
IMR4H
√
√
√
√
FFH
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Manipulatable Bits
Address
Function Register Name
Symbol
IMR5L
R/W
R/W
Default Value
1
8
16
FFFFF10AH
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
Interrupt mask register 5L
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LVIIC
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PIC7
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
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Manipulatable Bits
Address
Function Register Name
Symbol
TP3OVIC
R/W
R/W
Default Value
1
8
16
FFFFF13EH
FFFFF140H
FFFFF142H
FFFFF144H
FFFFF146H
FFFFF148H
FFFFF14AH
FFFFF14CH
FFFFF14EH
FFFFF150H
FFFFF152H
FFFFF154H
FFFFF156H
FFFFF158H
FFFFF15AH
FFFFF15CH
FFFFF15EH
FFFFF160H
FFFFF162H
FFFFF164H
FFFFF1FAH
FFFFF1FCH
FFFFF1FEH
FFFFF200H
FFFFF201H
FFFFF202H
FFFFF203H
FFFFF204H
FFFFF205H
Interrupt control register
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Interrupt control register
TP3CCIC0
TP3CCIC1
TM0EQIC0
CB0RIC
CB0TIC
CB1RIC
CB1TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
ADIC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
C0ERRIC
C0WUPIC
C0RECIC
C0TRXIC
KRIC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
WTIIC
Interrupt control register
WTIC
In-service priority register
Command register
ISPR
R
PRCMD
PSC
W
Power save control register
A/D converter mode register 0
A/D converter mode register 1
A/D converter channel specification register 0
A/D converter mode register 2
Power-fail comparison mode register
Power-fail comparison threshold value register
R/W
√
√
√
√
√
√
√
ADA0M0
ADA0M1
ADA0S
ADA0M2
ADA0PFM
ADA0PFT
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Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R
Default Value
1
8
16
FFFFF210H
FFFFF211H
FFFFF212H
FFFFF213H
FFFFF214H
FFFFF215H
FFFFF216H
FFFFF217H
FFFFF218H
FFFFF219H
FFFFF21AH
A/D conversion result register 0
A/D conversion result register 0H
A/D conversion result register 1
A/D conversion result register 1H
A/D conversion result register 2
A/D conversion result register 2H
A/D conversion result register 3
A/D conversion result register 3H
A/D conversion result register 4
A/D conversion result register 4H
A/D conversion result register 5
ADA0CR0
ADA0CR0H
ADA0CR1
ADA0CR1H
ADA0CR2
ADA0CR2H
ADA0CR3
ADA0CR3H
ADA0CR4
ADA0CR4H
ADA0CR5
ADA0CR5H
ADA0CR6
ADA0CR6H
ADA0CR7
ADA0CR7H
ADA0CR8
ADA0CR8H
ADA0CR9
ADA0CR9H
KRM
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFF21BH A/D conversion result register 5H
FFFFF21CH A/D conversion result register 6
FFFFF21DH A/D conversion result register 6H
FFFFF21EH
FFFFF21FH
FFFFF220H
FFFFF221H
FFFFF222H
FFFFF223H
FFFFF300H
FFFFF308H
FFFFF318H
FFFFF400H
FFFFF406H
FFFFF406H
FFFFF408H
FFFFF40AH
FFFFF40EH
FFFFF40FH
FFFFF412H
FFFFF412H
FFFFF413H
A/D conversion result register 7
A/D conversion result register 7H
A/D conversion result register 8
A/D conversion result register 8H
A/D conversion result register 9
A/D conversion result register 9H
√
√
√
√
√
Key return mode register
R/W
√
√
√
√
Selector operation control register 0
SELCNT0
NFC
00H
Noise elimination control register
00H
Port 0
P0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Port 3
P3
√
Port 3L
Port 4
P3L
√
√
√
√
√
√
√
√
√
√
P4
Port 5
P5
Port 7L
Port 7H
Port 9
P7L
P7H
P9
√
Port 9L
Port 9H
P9L
√
√
√
√
P9H
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Manipulatable Bits
Address
Function Register Name
Symbol
PM0
R/W
R/W
Default Value
1
8
16
FFFFF420H
FFFFF426H
FFFFF426H
FFFFF428H
FFFFF42AH
FFFFF42EH
FFFFF42EH
FFFFF42FH
FFFFF432H
FFFFF432H
FFFFF433H
FFFFF440H
FFFFF446H
FFFFF446H
FFFFF447H
FFFFF448H
FFFFF44AH
FFFFF452H
FFFFF452H
FFFFF453H
FFFFF460H
FFFFF466H
FFFFF46AH
FFFFF472H
FFFFF472H
FFFFF473H
FFFFF540H
FFFFF541H
FFFFF542H
FFFFF543H
Port mode register 0
FFH
FFFFH
FFH
FFH
FFH
FFFFH
FFH
FFH
FFFFH
FFH
FFH
00H
√
√
Port mode register 3
PM3
√
Port mode register 3L
PM3L
√
√
√
√
√
√
Port mode register 4
PM4
Port mode register 5
PM5
Port mode register 7
PM7
√
√
Port mode register 7L
PM7L
√
√
√
√
Port mode register 7H
PM7H
PM9
Port mode register 9
Port mode register 9L
PM9L
√
√
√
√
√
√
Port mode register 9H
PM9H
PMC0
PMC3
PMC3L
PMC3H
PMC4
PMC5
PMC9
PMC9L
PMC9H
PFC0
Port mode control register 0
Port mode control register 3
Port mode control register 3L
Port mode control register 3H
Port mode control register 4
Port mode control register 5
Port mode control register 9
Port mode control register 9L
Port mode control register 9H
Port function control register 0
Port function control register 3L
Port function control register 5
Port function control register 9
Port function control register 9L
Port function control register 9H
TMQ0 control register 0
TMQ0 control register 1
TMQ0 I/O control register 0
TMQ0 I/O control register 1
√
√
0000H
00H
√
√
√
√
√
√
√
√
00H
00H
00H
0000H
00H
√
√
√
√
√
√
√
√
√
√
00H
00H
PFC3L
PFC5
00H
00H
PFC9
√
0000H
00H
PFC9L
PFC9H
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
√
√
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
00H
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Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
8
√
√
16
FFFFF544H
FFFFF545H
FFFFF546H
FFFFF548H
FFFFF54AH
FFFFF54CH
FFFFF54EH
FFFFF590H
FFFFF591H
FFFFF592H
FFFFF593H
FFFFF594H
FFFFF595H
FFFFF596H
FFFFF598H
FFFFF59AH
FFFFF5A0H
FFFFF5A1H
FFFFF5A2H
FFFFF5A3H
FFFFF5A4H
FFFFF5A5H
FFFFF5A6H
FFFFF5A8H
FFFFF5AAH
FFFFF5B0H
FFFFF5B1H
FFFFF5B2H
FFFFF5B3H
FFFFF5B4H
FFFFF5B5H
FFFFF5B6H
FFFFF5B8H
FFFFF5BAH
FFFFF5C0H
FFFFF5C1H
FFFFF5C2H
FFFFF5C3H
FFFFF5C4H
FFFFF5C5H
FFFFF5C6H
FFFFF5C8H
TMQ0 I/O control register 2
TMQ0 option register 0
TQ0IOC2
TQ0OPT0
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0CCR0
TP0CCR1
TP0CNT
00H
00H
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ0 counter read buffer register
TMP0 control register 0
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP0 control register 1
00H
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register 0
00H
00H
00H
00H
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP1 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1CCR0
TP1CCR1
TP1CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP1 control register 1
00H
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register 0
00H
00H
00H
00H
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP2 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2CCR0
TP2CCR1
TP2CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP2 control register 1
00H
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register 0
00H
00H
00H
00H
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP3 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP3CTL0
TP3CTL1
TP3IOC0
TP3IOC1
TP3IOC2
TP3OPT0
TP3CCR0
TP3CCR1
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP3 control register 1
00H
TMP3 I/O control register 0
TMP3 I/O control register 1
TMP3 I/O control register 2
TMP3 option register 0
00H
00H
00H
00H
TMP3 capture/compare register 0
TMP3 capture/compare register 1
√
√
0000H
0000H
142
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(7/9)
Manipulatable Bits
Address
Function Register Name
Symbol
TP3CNT
R/W
Default Value
1
8
16
FFFFF5CAH
FFFFF610H
FFFFF680H
FFFFF690H
FFFFF694H
FFFFF6C0H
FFFFF6C1H
FFFFF6D0H
FFFFF6D1H
FFFFF706H
FFFFF70AH
FFFFF712H
FFFFF712H
FFFFF713H
FFFFF802H
FFFFF80CH
FFFFF820H
FFFFF824H
FFFFF828H
FFFFF82CH
FFFFF82EH
FFFFF82FH
FFFFF870H
FFFFF888H
FFFFF890H
FFFFF891H
FFFFF892H
FFFFF8B0H
FFFFF8B1H
FFFFF9FCH
FFFFF9FEH
FFFFFA00H
FFFFFA01H
FFFFFA02H
FFFFFA03H
FFFFFA04H
FFFFFA06H
FFFFFA07H
FFFFFA10H
FFFFFA11H
FFFFFA12H
TMP3 counter read buffer register
TMQ1 timer control register 0
Watch timer operation mode register
TMM0 control register 0
R
√
0000H
00H
00H
00H
0000H
06H
03H
67H
9AH
00H
00H
0000H
00H
00H
00H
00H
00H
00H
03H
01H
00H
00H
00H
00H
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
TQ1CTL0
WTM
R/W
R/W
√
√
√
√
√
√
TM0CTL0
TM0CMP0
OSTS
TMM0 compare register 0
√
Oscillation stabilization time select register
PLL lockup time specification register
Watchdog timer mode register 2
Watchdog timer enable register
Port function control expansion register 3L
Port function control expansion register 5
Port function control expansion register 9
Port function control expansion register 9L
Port function control expansion register 9H
System status register
√
√
√
√
√
√
PLLS
WDTM2
WDTE
PFCE3L
PFCE5
PFCE9
PFCE9L
PFCE9H
SYS
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Ring OSC mode register
RCM
Power save mode register
PSMR
Lock register
LOCKR
PCC
R
Processor clock control register
PLL control register
R/W
PLLCTL
CCLS
CPU operating clock status register
Programmable clock mode register
Clock monitor mode register
Reset source flag register
R
PCLM
R/W
CLM
RESF
Low-voltage detection register
Low-voltage detection level select register
Internal RAM data status register
Prescaler mode register 0
LVIM
LVIS
RAMS
√
PRSM0
PRSCM0
OCDM
Prescaler compare register 0
On-chip debug mode register
Peripheral emulation register 1
UARTA0 control register 0
√
√
√
PEMU1
UA0CTL0
UA0CTL1
UA0CTL2
UA0OPT0
UA0STR
UA0RX
UA0TX
UA1CTL0
UA1CTL1
UA1CTL2
UARTA0 control register 1
UARTA0 control register 2
UARTA0 option control register 0
UARTA0 status register
√
√
UARTA0 receive data register
UARTA0 transmit data register
UARTA1 control register 0
R
R/W
√
UARTA1 control register 1
UARTA1 control register 2
Caution For OCDM details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
143
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(8/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
Default Value
1
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
FFFFFA13H
FFFFFA14H
FFFFFA16H
FFFFFA17H
FFFFFB00H
FFFFFB04H
FFFFFB08H
FFFFFB0CH
FFFFFB10H
FFFFFB14H
FFFFFB18H
FFFFFB1CH
FFFFFB50H
FFFFFB54H
FFFFFB58H
FFFFFB5CH
FFFFFC00H
FFFFFC06H
UARTA1 option control register 0
UA1OPT0
UA1STR
UA1RX
14H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
0000H
UARTA1 status register
UARTA1 receive data register
R
UARTA1 receive data register
UA1TX
R/W
R/W
TIP00 noise eliminator control register
TIP01 noise eliminator control register
TIP10 noise eliminator control register
TIP11 noise eliminator control register
TIP20 noise eliminator control register
TIP21 noise eliminator control register
TIP30 noise eliminator control register
TIP31 noise eliminator control register
TIQ00 noise eliminator control register
TIQ01 noise eliminator control register
TIQ02 noise eliminator control register
TIQ03 noise eliminator control register
External interrupt falling edge specification register 0
External interrupt falling edge specification register 3
P00NFC
P01NFC
P10NFC
P11NFC
P20NFC
P21NFC
P30NFC
P31NFC
Q00NFC
Q01NFC
Q02NFC
Q03NFC
INTF0
√
√
√
√
√
√
√
√
√
√
√
√
√
INTF3
√
√
√
FFFFFC06H External interrupt falling edge specification register 3L
INTF3L
√
√
√
√
√
√
√
√
FFFFFC07H External interrupt falling edge specification register 3H INTF3H
FFFFFC13H
FFFFFC20H
FFFFFC26H
External interrupt falling edge specification register 9H INTF9H
External interrupt rising edge specification register 0
External interrupt rising edge specification register 3
INTR0
INTR3
INTR3L
INTR3H
INTR9H
PU0
FFFFFC26H External interrupt rising edge specification register 3L
FFFFFC27H External interrupt rising edge specification register 3H
√
√
√
√
√
√
√
√
FFFFFC33H
FFFFFC40H
FFFFFC46H
External interrupt rising edge specification register 9H
Pull-up resistor option register 0
Pull-up resistor option register 3
PU3
144
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(9/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PU3L
R/W
R/W
Default Value
1
√
√
√
√
8
√
√
√
√
16
FFFFFC46H
FFFFFC47H
FFFFFC48H
FFFFFC4AH
FFFFFC52H
FFFFFC52H
FFFFFC53H
FFFFFD00H
FFFFFD01H
FFFFFD02H
FFFFFD03H
FFFFFD04H
FFFFFD04H
FFFFFD06H
FFFFFD06H
FFFFFD10H
FFFFFD11H
FFFFFD12H
FFFFFD13H
FFFFFD14H
FFFFFD14H
FFFFFD16H
FFFFFD16H
Pull-up resistor option register 3L
Pull-up resistor option register 3H
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 9
Pull-up resistor option register 9L
Pull-up resistor option register 9H
CSIB0 control register 0
00H
PU3H
00H
PU4
00H
PU5
00H
PU9
√
0000H
00H
PU9L
√
√
√
√
√
√
√
√
√
√
PU9H
00H
CB0CTL0
CB0CTL1
CB0CTL2
CB0STR
CB0RX
CB0RXL
CB0TX
CB0TXL
CB1CTL0
CB1CTL1
CB1CTL2
CB1STR
CB1RX
CB1RXL
CB1TX
CB1TXL
01H
CSIB0 control register 1
00H
CSIB0 control register 2
00H
CSIB0 status register
√
00H
CSIB0 receive data register
CSIB0 receive data register L
CSIB0 transmit data register
CSIB0 transmit data register L
CSIB1 control register 0
R
√
√
0000H
00H
√
R/W
0000H
00H
√
√
√
√
√
√
√
01H
CSIB1 control register 1
00H
CSIB1control register 2
00H
CSIB1 status register
√
00H
CSIB1 receive data register
CSIB1 receive data register L
CSIB1 transmit data register
CSIB1 transmit data register L
R
√
√
0000H
00H
√
√
R/W
0000H
00H
145
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
3.4.1.2 V850ES/FF2
(1/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PDL
R/W
R/W
Default Value
1
8
16
FFFFF004H
FFFFF004H
FFFFF005H
FFFFF008H
FFFFF00AH
FFFFF00CH
FFFFF024H
FFFFF024H
FFFFF025H
FFFFF02CH
FFFFF04CH
FFFFF064H
FFFFF06EH
FFFFF100H
FFFFF100H
FFFFF101H
FFFFF102H
FFFFF102H
FFFFF103H
FFFFF104H
FFFFF104H
FFFFF105H
FFFFF106H
FFFFF106H
FFFFF107H
FFFFF108H
FFFFF108H
FFFFF109H
Port DL
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFFFH
FFH
√
Port DLL
PDLL
√
√
√
√
√
√
√
√
√
√
Port DLH
PDLH
PCS
Port CS
Port CT
PCT
Port CM
PCM
Port mode register DL
Port mode register DLL
Port mode register DLH
Port mode register CM
Port mode control register CM
Peripheral I/O area select control register
System wait control register
Interrupt mask register 0
Interrupt mask register 0L
Interrupt mask register 0H
Interrupt mask register 1
Interrupt mask register 1L
Interrupt mask register 1H
Interrupt mask register 2
Interrupt mask register 2L
Interrupt mask register 2H
Interrupt mask register 3
Interrupt mask register 3L
Interrupt mask register 3H
Interrupt mask register 4
Interrupt mask register 4L
Interrupt mask register 4H
PMDL
PMDLL
PMDLH
PMCM
PMCCM
BPC
√
√
√
√
√
√
√
√
√
FFH
FFH
00H
0000H
77H
√
√
VSWC
IMR0
√
FFFFH
FFH
IMR0L
IMR0H
IMR1
√
√
√
√
FFH
FFFFH
FFH
√
√
√
√
IMR1L
IMR1H
IMR2
√
√
√
√
FFH
FFFFH
FFH
IMR2L
IMR2H
IMR3
√
√
√
√
FFH
FFFFH
FFH
IMR3L
IMR3H
IMR4
√
√
√
√
FFH
FFFFH
FFH
IMR4L
IMR4H
√
√
√
√
FFH
146
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(2/9)
Manipulatable Bits
Address
Function Register Name
Symbol
IMR5L
R/W
R/W
Default Value
1
8
16
FFFFF10AH
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
Interrupt mask register 5L
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LVIIC
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PIC7
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
147
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(3/9)
Manipulatable Bits
Address
Function Register Name
Symbol
TP3OVIC
R/W
R/W
Default Value
1
8
16
FFFFF13EH
FFFFF140H
FFFFF142H
FFFFF144H
FFFFF146H
FFFFF148H
FFFFF14AH
FFFFF14CH
FFFFF14EH
FFFFF150H
FFFFF152H
FFFFF154H
FFFFF156H
FFFFF158H
FFFFF15AH
FFFFF15CH
FFFFF15EH
FFFFF160H
FFFFF162H
FFFFF164H
FFFFF1FAH
FFFFF1FCH
FFFFF1FEH
FFFFF200H
FFFFF201H
FFFFF202H
FFFFF203H
FFFFF204H
FFFFF205H
Interrupt control register
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Interrupt control register
TP3CCIC0
TP3CCIC1
TM0EQIC0
CB0RIC
CB0TIC
CB1RIC
CB1TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
ADIC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
C0ERRIC
C0WUPIC
C0RECIC
C0TRXIC
KRIC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
WTIIC
Interrupt control register
WTIC
In-service priority register
Command register
ISPR
R
PRCMD
PSC
W
Power save control register
A/D converter mode register 0
A/D converter mode register 1
A/D converter channel specification register 0
A/D converter mode register 2
Power-fail comparison mode register
Power-fail comparison threshold value register
R/W
√
√
√
√
√
√
√
ADA0M0
ADA0M1
ADA0S
ADA0M2
ADA0PFM
ADA0PFT
148
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(4/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R
Default Value
1
8
16
FFFFF210H
FFFFF211H
FFFFF212H
FFFFF213H
FFFFF214H
FFFFF215H
FFFFF216H
FFFFF217H
FFFFF218H
FFFFF219H
FFFFF21AH
A/D conversion result register 0
A/D conversion result register 0H
A/D conversion result register 1
A/D conversion result register 1H
A/D conversion result register 2
A/D conversion result register 2H
A/D conversion result register 3
A/D conversion result register 3H
A/D conversion result register 4
A/D conversion result register 4H
A/D conversion result register 5
ADA0CR0
ADA0CR0H
ADA0CR1
ADA0CR1H
ADA0CR2
ADA0CR2H
ADA0CR3
ADA0CR3H
ADA0CR4
ADA0CR4H
ADA0CR5
ADA0CR5H
ADA0CR6
ADA0CR6H
ADA0CR7
ADA0CR7H
ADA0CR8
ADA0CR8H
ADA0CR9
ADA0CR9H
ADA0CR10
ADA0CR10H
ADA0CR11
ADA0CR11H
KRM
00H
√
00H
√
√
√
√
√
√
√
√
√
√
√
00H
√
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
00H
00H
00H
00H
FFFFF21BH A/D conversion result register 5H
FFFFF21CH A/D conversion result register 6
FFFFF21DH A/D conversion result register 6H
00H
00H
00H
FFFFF21EH
FFFFF21FH
FFFFF220H
FFFFF221H
FFFFF222H
FFFFF223H
FFFFF224H
FFFFF225H
FFFFF226H
FFFFF227H
FFFFF300H
FFFFF308H
FFFFF318H
FFFFF400H
FFFFF406H
FFFFF406H
FFFFF407H
FFFFF408H
FFFFF40AH
FFFFF40EH
FFFFF40FH
FFFFF412H
FFFFF412H
FFFFF413H
A/D conversion result register 7
A/D conversion result register 7H
A/D conversion result register 8
A/D conversion result register 8H
A/D conversion result register 9
A/D conversion result register 9H
A/D conversion result register 10
A/D conversion result register 10H
A/D conversion result register 11
A/D conversion result register 11H
Key return mode register
Selector operation control register 0
Noise elimination control register
Port 0
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
R/W
00H
√
√
√
√
SELCNT0
NFC
00H
00H
P0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Port 3
P3
√
Port 3L
P3L
√
√
√
√
√
√
√
√
√
√
√
√
Port 3H
P3H
Port 4
P4
Port 5
P5
Port 7L
P7L
Port 7H
P7H
Port 9
P9
√
Port 9L
P9L
√
√
√
√
Port 9H
P9H
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User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(5/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PM0
R/W
R/W
Default Value
1
8
16
FFFFF420H
FFFFF426H
FFFFF426H
FFFFF427H
FFFFF428H
FFFFF42AH
FFFFF42EH
FFFFF42EH
FFFFF42FH
FFFFF432H
FFFFF432H
FFFFF433H
FFFFF440H
FFFFF446H
FFFFF446H
FFFFF447H
FFFFF448H
FFFFF44AH
FFFFF452H
FFFFF452H
FFFFF453H
FFFFF460H
FFFFF466H
FFFFF46AH
FFFFF472H
FFFFF472H
FFFFF473H
FFFFF540H
FFFFF541H
FFFFF542H
FFFFF543H
Port mode register 0
FFH
FFFFH
FFH
FFH
FFH
FFH
FFFFH
FFH
FFH
FFFFH
FFH
FFH
00H
√
√
Port mode register 3
PM3
√
Port mode register 3L
PM3L
√
√
√
√
√
√
√
√
Port mode register 3H
PM3H
PM4
Port mode register 4
Port mode register 5
PM5
Port mode register 7
PM7
√
√
Port mode register 7L
PM7L
√
√
√
√
Port mode register 7H
PM7H
PM9
Port mode register 9
Port mode register 9L
PM9L
√
√
√
√
√
√
Port mode register 9H
PM9H
PMC0
PMC3
PMC3L
PMC3H
PMC4
PMC5
PMC9
PMC9L
PMC9H
PFC0
Port mode control register 0
Port mode control register 3
Port mode control register 3L
Port mode control register 3H
Port mode control register 4
Port mode control register 5
Port mode control register 9
Port mode control register 9L
Port mode control register 9H
Port function control register 0
Port function control register 3L
Port function control register 5
Port function control register 9
Port function control register 9L
Port function control register 9H
TMQ0 control register 0
TMQ0 control register 1
TMQ0 I/O control register 0
TMQ0 I/O control register 1
√
√
0000H
00H
√
√
√
√
√
√
√
√
00H
00H
00H
0000H
00H
√
√
√
√
√
√
√
√
√
√
00H
00H
PFC3L
PFC5
00H
00H
PFC9
√
0000H
00H
PFC9L
PFC9H
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
√
√
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
00H
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CHAPTER 3 CPU FUNCTIONS
(6/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
8
√
√
16
FFFFF544H
FFFFF545H
FFFFF546H
FFFFF548H
FFFFF54AH
FFFFF54CH
FFFFF54EH
FFFFF590H
FFFFF591H
FFFFF592H
FFFFF593H
FFFFF594H
FFFFF595H
FFFFF596H
FFFFF598H
FFFFF59AH
FFFFF5A0H
FFFFF5A1H
FFFFF5A2H
FFFFF5A3H
FFFFF5A4H
FFFFF5A5H
FFFFF5A6H
FFFFF5A8H
FFFFF5AAH
FFFFF5B0H
FFFFF5B1H
FFFFF5B2H
FFFFF5B3H
FFFFF5B4H
FFFFF5B5H
FFFFF5B6H
FFFFF5B8H
FFFFF5BAH
FFFFF5C0H
FFFFF5C1H
FFFFF5C2H
FFFFF5C3H
FFFFF5C4H
FFFFF5C5H
FFFFF5C6H
FFFFF5C8H
TMQ0 I/O control register 2
TMQ0 option register 0
TQ0IOC2
TQ0OPT0
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0CCR0
TP0CCR1
TP0CNT
00H
00H
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ0 counter read buffer register
TMP0 control register 0
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP0 control register 1
00H
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register 0
00H
00H
00H
00H
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP1 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1CCR0
TP1CCR1
TP1CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP1 control register 1
00H
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register 0
00H
00H
00H
00H
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP2 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2CCR0
TP2CCR1
TP2CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP2 control register 1
00H
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register 0
00H
00H
00H
00H
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP3 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP3CTL0
TP3CTL1
TP3IOC0
TP3IOC1
TP3IOC2
TP3OPT0
TP3CCR0
TP3CCR1
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP3 control register 1
00H
TMP3 I/O control register 0
TMP3 I/O control register 1
TMP3 I/O control register 2
TMP3 option register 0
00H
00H
00H
00H
TMP3 capture/compare register 0
TMP3 capture/compare register 1
√
√
0000H
0000H
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CHAPTER 3 CPU FUNCTIONS
(7/9)
Manipulatable Bits
Address
Function Register Name
Symbol
TP3CNT
R/W
Default Value
1
8
16
FFFFF5CAH
FFFFF680H
FFFFF690H
FFFFF694H
FFFFF6C0H
FFFFF6C1H
FFFFF6D0H
FFFFF6D1H
FFFFF706H
FFFFF70AH
FFFFF712H
FFFFF712H
FFFFF713H
FFFFF802H
FFFFF80CH
FFFFF820H
FFFFF824H
FFFFF828H
FFFFF82CH
FFFFF82EH
FFFFF82FH
FFFFF870H
FFFFF888H
FFFFF890H
FFFFF891H
FFFFF892H
FFFFF8B0H
FFFFF8B1H
FFFFF9FCH
FFFFF9FEH
FFFFFA00H
FFFFFA01H
FFFFFA02H
FFFFFA03H
FFFFFA04H
FFFFFA06H
FFFFFA07H
FFFFFA10H
FFFFFA11H
FFFFFA12H
TMP3 counter read buffer register
Watch timer operation mode register
TMM0 control register 0
R
√
0000H
00H
00H
0000H
06H
03H
67H
9AH
00H
00H
0000H
00H
00H
00H
00H
00H
00H
03H
01H
00H
00H
00H
00H
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
WTM
R/W
√
√
√
√
TM0CTL0
TM0CMP0
OSTS
TMM0 compare register 0
√
Oscillation stabilization time select register
PLL lockup time specification register
Watchdog timer mode register 2
Watchdog timer enable register
Port function control expansion register 3L
Port function control expansion register 5
Port function control expansion register 9
Port function control expansion register 9L
Port function control expansion register 9H
System status register
√
√
√
√
√
√
PLLS
WDTM2
WDTE
PFCE3L
PFCE5
PFCE9
PFCE9L
PFCE9H
SYS
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Ring OSC mode register
RCM
Power save mode register
PSMR
Lock register
LOCKR
PCC
R
Processor clock control register
PLL control register
R/W
PLLCTL
CCLS
CPU operating clock status register
Programmable clock mode register
Clock monitor mode register
Reset source flag register
R
PCLM
R/W
CLM
RESF
Low-voltage detection register
Low-voltage detection level select register
Internal RAM data status register
Prescaler mode register 0
LVIM
LVIS
RAMS
√
PRSM0
PRSCM0
OCDM
PEMU1
UA0CTL0
UA0CTL1
UA0CTL2
UA0OPT0
UA0STR
UA0RX
UA0TX
UA1CTL0
UA1CTL1
UA1CTL2
Prescaler compare register 0
On-chip debug mode register
Peripheral emulation register 1
UARTA0 control register 0
√
√
√
UARTA0 control register 1
UARTA0 control register 2
UARTA0 option control register 0
UARTA0 status register
√
√
UARTA0 receive data register
UARTA0 transmit data register
UARTA1 control register 0
R
R/W
√
UARTA1 control register 1
UARTA1 control register 2
Caution For OCDM details, refer to CHAPTER 25 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
152
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(8/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
Default Value
1
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
FFFFFA13H
FFFFFA14H
FFFFFA16H
FFFFFA17H
FFFFFB00H
FFFFFB04H
FFFFFB08H
FFFFFB0CH
FFFFFB10H
FFFFFB14H
FFFFFB18H
FFFFFB1CH
FFFFFB50H
FFFFFB54H
FFFFFB58H
FFFFFB5CH
FFFFFC00H
FFFFFC06H
UARTA1 option control register 0
UA1OPT0
UA1STR
UA1RX
14H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
0000H
UARTA1 status register
UARTA1 receive data register
R
UARTA1 receive data register
UA1TX
R/W
R/W
TIP00 noise eliminator control register
TIP01 noise eliminator control register
TIP10 noise eliminator control register
TIP11 noise eliminator control register
TIP20 noise eliminator control register
TIP21 noise eliminator control register
TIP30 noise eliminator control register
TIP31 noise eliminator control register
TIQ00 noise eliminator control register
TIQ01 noise eliminator control register
TIQ02 noise eliminator control register
TIQ03 noise eliminator control register
External interrupt falling edge specification register 0
External interrupt falling edge specification register 3
P00NFC
P01NFC
P10NFC
P11NFC
P20NFC
P21NFC
P30NFC
P31NFC
Q00NFC
Q01NFC
Q02NFC
Q03NFC
INTF0
√
√
√
√
√
√
√
√
√
√
√
√
√
INTF3
√
√
√
FFFFFC06H External interrupt falling edge specification register 3L
INTF3L
√
√
√
√
√
√
√
√
FFFFFC07H External interrupt falling edge specification register 3H INTF3H
FFFFFC13H
FFFFFC20H
FFFFFC26H
External interrupt falling edge specification register 9H INTF9H
External interrupt rising edge specification register 0
External interrupt rising edge specification register 3
INTR0
INTR3
INTR3L
INTR3H
INTR9H
PU0
FFFFFC26H External interrupt rising edge specification register 3L
FFFFFC27H External interrupt rising edge specification register 3H
√
√
√
√
√
√
√
√
FFFFFC33H
FFFFFC40H
FFFFFC46H
External interrupt rising edge specification register 9H
Pull-up resistor option register 0
Pull-up resistor option register 3
PU3
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CHAPTER 3 CPU FUNCTIONS
(9/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PU3L
R/W
R/W
Default Value
1
√
√
√
√
8
√
√
√
√
16
FFFFFC46H
FFFFFC47H
FFFFFC48H
FFFFFC4AH
FFFFFC52H
FFFFFC52H
FFFFFC53H
FFFFFD00H
FFFFFD01H
FFFFFD02H
FFFFFD03H
FFFFFD04H
FFFFFD04H
FFFFFD06H
FFFFFD06H
FFFFFD10H
FFFFFD11H
FFFFFD12H
FFFFFD13H
FFFFFD14H
FFFFFD14H
FFFFFD16H
FFFFFD16H
Pull-up resistor option register 3L
Pull-up resistor option register 3H
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 9
Pull-up resistor option register 9L
Pull-up resistor option register 9H
CSIB0 control register 0
00H
PU3H
00H
PU4
00H
PU5
00H
PU9
√
0000H
00H
PU9L
√
√
√
√
√
√
√
√
√
√
PU9H
00H
CB0CTL0
CB0CTL1
CB0CTL2
CB0STR
CB0RX
CB0RXL
CB0TX
CB0TXL
CB1CTL0
CB1CTL1
CB1CTL2
CB1STR
CB1RX
CB1RXL
CB1TX
CB1TXL
01H
CSIB0 control register 1
00H
CSIB0 control register 2
00H
CSIB0 status register
√
00H
CSIB0 receive data register
CSIB0 receive data register L
CSIB0 transmit data register
CSIB0 transmit data register L
CSIB1 control register 0
R
√
√
0000H
00H
√
R/W
0000H
00H
√
√
√
√
√
√
√
01H
CSIB1 control register 1
00H
CSIB1control register 2
00H
CSIB1 status register
√
00H
CSIB1 receive data register
CSIB1 receive data register L
CSIB1 transmit data register
CSIB1 transmit data register L
R
√
√
0000H
00H
√
√
R/W
0000H
00H
154
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
3.4.1.3 V850ES/FG2
(1/9)
Manipulatable Bits
Address
Function Register Name
Symbol
PDL
R/W
R/W
Default Value
1
8
16
FFFFF004H
FFFFF004H
FFFFF005H
FFFFF008H
FFFFF00AH
FFFFF00CH
FFFFF024H
FFFFF024H
FFFFF025H
FFFFF028H
FFFFF02AH
FFFFF02CH
FFFFF04CH
FFFFF064H
FFFFF06EH
FFFFF080H
FFFFF082H
FFFFF084H
FFFFF086H
FFFFF088H
FFFFF08AH
FFFFF08CH
FFFFF08EH
FFFFF090H
FFFFF092H
FFFFF094H
FFFFF096H
FFFFF098H
FFFFF09AH
FFFFF09CH
FFFFF09EH
FFFFF0C0H
FFFFF0C2H
FFFFF0C4H
FFFFF0C6H
FFFFF0D0H
FFFFF0D2H
FFFFF0D4H
FFFFF0D6H
Port DL
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFFFH
√
Port DLL
PDLL
√
√
√
√
√
√
√
√
√
√
Port DLH
PDLH
Port CS
PCS
Port CT
PCT
Port CM
PCM
Port mode register DL
PMDL
PMDLL
PMDLH
PMCS
PMCT
PMCM
PMCCM
BPC
√
Port mode register DLL
FFH
√
√
√
√
√
√
√
√
√
√
√
√
Port mode register DLH
FFH
Port mode register CS
FFH
Port mode register CT
FFH
Port mode register CM
FFH
Port mode control register CM
Peripheral I/O area select control register
System wait control register
DMA source address register 0L
DMA source address register 0H
DMA destination address register 0L
DMA destination address register 0H
DMA source address register 1L
DMA source address register 1H
DMA destination address register 1L
DMA destination address register 1H
DMA source address register 2L
DMA source address register 2H
DMA destination address register 2L
DMA destination address register 2H
DMA source address register 3L
DMA source address register 3H
DMA destination address register 3L
DMA destination address register 3H
DMA transfer count register 0
DMA transfer count register 1
DMA transfer count register 2
DMA transfer count register 3
DMA addressing control register 0
DMA addressing control register 1
DMA addressing control register 2
DMA addressing control register 3
00H
0000H
√
VSWC
DSA0L
DSA0H
DDA0L
DDA0H
DSA1L
DSA1H
DDA1L
DDA1H
DSA2L
DSA2H
DDA2L
DDA2H
DSA3L
DSA3H
DDA3L
DDA3H
DBC0
77H
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
DBC1
DBC2
DBC3
DADC0
DADC1
DADC2
DADC3
0000H
0000H
0000H
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CHAPTER 3 CPU FUNCTIONS
(2/12)
Manipulatable Bits
Address
Function Register Name
Symbol
DCHC0
R/W
R/W
Default Value
1
8
16
FFFFF0E0H
FFFFF0E2H
FFFFF0E4H
FFFFF0E6H
FFFFF100H
FFFFF100H
FFFFF101H
FFFFF102H
FFFFF102H
FFFFF103H
FFFFF104H
FFFFF104H
FFFFF105H
FFFFF106H
FFFFF106H
FFFFF107H
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
FFFFF13EH
FFFFF140H
FFFFF142H
DMA channel control register 0
DMA channel control register 1
DMA channel control register 2
DMA channel control register 3
Interrupt mask register 0
Interrupt mask register 0L
Interrupt mask register 0H
Interrupt mask register 1
Interrupt mask register 1L
Interrupt mask register 1H
Interrupt mask register 2
Interrupt mask register 2L
Interrupt mask register 2H
Interrupt mask register 3
Interrupt mask register 3L
Interrupt mask register 3H
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
00H
00H
00H
00H
FFFFH
FFH
FFH
FFFFH
FFH
FFH
FFFFH
FFH
FFH
FFFFH
FFH
FFH
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
√
√
√
√
√
√
√
√
DCHC1
DCHC2
DCHC3
IMR0
√
√
√
√
IMR0L
√
√
√
√
IMR0H
IMR1
IMR1L
√
√
√
√
IMR1H
IMR2
IMR2L
√
√
√
√
IMR2H
IMR3
IMR3L
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
IMR3H
LVIIC
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PIC7
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
TP3OVIC
TP3CCIC0
TP3CCIC1
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CHAPTER 3 CPU FUNCTIONS
(3/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
8
16
FFFFF144H
FFFFF146H
FFFFF148H
FFFFF14AH
FFFFF14CH
FFFFF14EH
FFFFF150H
FFFFF152H
FFFFF154H
FFFFF156H
FFFFF158H
FFFFF15AH
FFFFF15CH
FFFFF15EH
FFFFF160H
FFFFF162H
FFFFF164H
FFFFF166H
FFFFF168H
FFFFF16AH
FFFFF16CH
FFFFF16EH
FFFFF170H
FFFFF172H
FFFFF174H
FFFFF176H
FFFFF178H
FFFFF17AH
FFFFF17CH
FFFFF17EH
FFFFF180H
FFFFF182H
FFFFF184H
FFFFF186H
FFFFF188H
FFFFF1FAH
FFFFF1FCH
FFFFF1FEH
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
In-service priority register
Command register
TM0EQIC0
CB0RIC
CB0TIC
CB1RIC
CB1TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
ADIC
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
C0ERRIC
C0WUPIC
C0RECIC
C0TRXIC
KRIC
WTIIC
WTIC
PIC8
PIC9
PIC10
TQ1OVIC
TQ1CCIC0
TQ1CCIC1
TQ1CCIC2
TQ1CCIC3
UA2RIC
UA2TIC
C1ERRIC
C1WUPIC
C1RECIC
C1TRXIC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
ISPR
R
PRCMD
PSC
W
Power save control register
R/W
√
157
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CHAPTER 3 CPU FUNCTIONS
(4/9)
Manipulatable Bits
Address
Function Register Name
Symbol
ADA0M0
R/W
R/W
Default Value
1
8
16
FFFFF200H
FFFFF201H
FFFFF202H
FFFFF203H
FFFFF204H
FFFFF205H
FFFFF210H
FFFFF211H
FFFFF212H
FFFFF213H
FFFFF214H
FFFFF215H
FFFFF216H
FFFFF217H
FFFFF218H
FFFFF219H
FFFFF21AH
A/D converter mode register 0
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
A/D converter mode register 1
ADA0M1
A/D converter channel specification register 0
A/D converter mode register 2
ADA0S
ADA0M2
Power-fail comparison mode register
Power-fail comparison threshold value register
A/D conversion result register 0
A/D conversion result register 0H
A/D conversion result register 1
A/D conversion result register 1H
A/D conversion result register 2
A/D conversion result register 2H
A/D conversion result register 3
A/D conversion result register 3H
A/D conversion result register 4
A/D conversion result register 4H
A/D conversion result register 5
ADA0PFM
ADA0PFT
ADA0CR0
ADA0CR0H
ADA0CR1
ADA0CR1H
ADA0CR2
ADA0CR2H
ADA0CR3
ADA0CR3H
ADA0CR4
ADA0CR4H
ADA0CR5
ADA0CR5H
ADA0CR6
ADA0CR6H
ADA0CR7
ADA0CR7H
ADA0CR8
ADA0CR8H
ADA0CR9
ADA0CR9H
ADA0CR10
ADA0CR10H
ADA0CR11
ADA0CR11H
ADA0CR12
ADA0CR12H
ADA0CR13
ADA0CR13H
ADA0CR14
ADA0CR14H
ADA0CR15
ADA0CR15H
KRM
R
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFF21BH A/D conversion result register 5H
FFFFF21CH A/D conversion result register 6
FFFFF21DH A/D conversion result register 6H
FFFFF21EH
FFFFF21FH
FFFFF220H
FFFFF221H
FFFFF222H
FFFFF223H
FFFFF224H
FFFFF225H
FFFFF226H
FFFFF227H
FFFFF228H
FFFFF229H
FFFFF22AH
A/D conversion result register 7
A/D conversion result register 7H
A/D conversion result register 8
A/D conversion result register 8H
A/D conversion result register 9
A/D conversion result register 9H
A/D conversion result register 10
A/D conversion result register 10H
A/D conversion result register 11
A/D conversion result register 11H
A/D conversion result register 12
A/D conversion result register 12H
A/D conversion result register 13
FFFFF22BH A/D conversion result register 13H
FFFFF22CH A/D conversion result register 14
FFFFF22DH A/D conversion result register 14H
FFFFF22EH
FFFFF22FH
FFFFF300H
FFFFF308H
FFFFF318H
A/D conversion result register 15
A/D conversion result register 15H
Key return mode register
√
√
√
√
R/W
√
√
√
Selector operation control register 0
Noise elimination control register
SELCNT0
NFC
158
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(5/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
8
16
FFFFF400H
FFFFF402H
FFFFF406H
FFFFF406H
FFFFF407H
FFFFF408H
FFFFF40AH
FFFFF40EH
FFFFF40FH
FFFFF412H
FFFFF412H
FFFFF413H
FFFFF420H
FFFFF422H
FFFFF426H
FFFFF426H
FFFFF427H
FFFFF428H
FFFFF42AH
FFFFF42EH
FFFFF42FH
FFFFF432H
FFFFF432H
FFFFF433H
FFFFF440H
FFFFF442H
FFFFF446H
FFFFF446H
FFFFF447H
FFFFF448H
FFFFF44AH
FFFFF452H
FFFFF452H
FFFFF453H
FFFFF460H
FFFFF466H
FFFFF46AH
FFFFF472H
FFFFF472H
FFFFF473H
Port 0
P0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFH
√
√
√
√
Port 1
P1
Port 3
P3
√
Port 3L
P3L
√
√
√
√
√
√
√
√
√
√
√
√
Port 3H
P3H
Port 4
P4
Port 5
P5
Port 7L
P7L
Port 7H
P7H
Port 9
P9
√
√
Port 9L
P9L
√
√
√
√
√
√
√
√
Port 9H
P9H
Port mode register 0
Port mode register 1
Port mode register 3
Port mode register 3L
Port mode register 3H
Port mode register 4
Port mode register 5
Port mode register 7L
Port mode register 7H
Port mode register 9
Port mode register 9L
Port mode register 9H
Port mode control register 0
Port mode control register 1
Port mode control register 3
Port mode control register 3L
Port mode control register 3H
Port mode control register 4
Port mode control register 5
Port mode control register 9
Port mode control register 9L
Port mode control register 9H
Port function control register 0
Port function control register 3L
Port function control register 5
Port function control register 9
Port function control register 9L
Port function control register 9H
PM0
PM1
FFH
PM3
FFFFH
FFH
PM3L
PM3H
PM4
√
√
√
√
√
√
√
√
√
√
√
√
FFH
FFH
PM5
FFH
PM7L
PM7H
PM9
FFH
FFH
√
√
√
FFFFH
FFH
PM9L
PM9H
PMC0
PMC1
PMC3
PMC3L
PMC3H
PMC4
PMC5
PMC9
PMC9L
PMC9H
PFC0
PFC3L
PFC5
PFC9
PFC9L
PFC9H
√
√
√
√
√
√
√
√
FFH
00H
00H
0000H
00H
√
√
√
√
√
√
√
√
00H
00H
00H
0000H
00H
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
√
0000H
00H
√
√
√
√
00H
159
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(6/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
√
√
√
√
8
√
√
√
√
√
√
16
FFFFF540H
FFFFF541H
FFFFF542H
FFFFF543H
FFFFF544H
FFFFF545H
FFFFF546H
FFFFF548H
FFFFF54AH
FFFFF54CH
FFFFF54EH
FFFFF590H
FFFFF591H
FFFFF592H
FFFFF593H
FFFFF594H
FFFFF595H
FFFFF596H
FFFFF598H
FFFFF59AH
FFFFF5A0H
FFFFF5A1H
FFFFF5A2H
FFFFF5A3H
FFFFF5A4H
FFFFF5A5H
FFFFF5A6H
FFFFF5A8H
FFFFF5AAH
FFFFF5B0H
FFFFF5B1H
FFFFF5B2H
FFFFF5B3H
FFFFF5B4H
FFFFF5B5H
FFFFF5B6H
FFFFF5B8H
FFFFF5BAH
FFFFF5C0H
FFFFF5C1H
FFFFF5C2H
FFFFF5C3H
TMQ0 control register 0
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
TQ0IOC2
TQ0OPT0
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0CCR0
TP0CCR1
TP0CNT
00H
TMQ0 control register 1
00H
TMQ0 I/O control register 0
TMQ0 I/O control register 1
TMQ0 I/O control register 2
TMQ0 option register 0
00H
00H
00H
00H
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ0 counter read buffer register
TMP0 control register 0
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP0 control register 1
00H
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register 0
00H
00H
00H
00H
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP1 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1CCR0
TP1CCR1
TP1CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP1 control register 1
00H
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register 0
00H
00H
00H
00H
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP2 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2CCR0
TP2CCR1
TP2CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP2 control register 1
00H
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register 0
00H
00H
00H
00H
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP3 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP3CTL0
TP3CTL1
TP3IOC0
TP3IOC1
R/W
√
√
√
√
√
√
√
√
TMP3 control register 1
00H
TMP3 I/O control register 0
TMP3 I/O control register 1
00H
00H
160
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CHAPTER 3 CPU FUNCTIONS
(7/9)
Manipulatable Bits
Address
Function Register Name
Symbol
TP3IOC2
R/W
R/W
Default Value
1
√
√
8
√
√
16
FFFFF5C4H
FFFFF5C5H
FFFFF5C6H
FFFFF5C8H
FFFFF5CAH
FFFFF610H
FFFFF611H
FFFFF612H
FFFFF613H
FFFFF614H
FFFFF615H
FFFFF616H
FFFFF618H
FFFFF61AH
FFFFF61CH
FFFFF61EH
FFFFF680H
FFFFF690H
FFFFF694H
FFFFF6C0H
FFFFF6C1H
FFFFF6D0H
FFFFF6D1H
FFFFF706H
FFFFF70AH
FFFFF712H
FFFFF712H
FFFFF713H
FFFFF802H
FFFFF80CH
FFFFF810H
FFFFF812H
FFFFF814H
FFFFF816H
FFFFF820H
FFFFF824H
FFFFF828H
FFFFF82CH
FFFFF82EH
FFFFF82FH
FFFFF870H
FFFFF888H
TMP3 I/O control register 2
00H
TMP3 option register 0
TP3OPT0
TP3CCR0
TP3CCR1
TP3CNT
TQ1CTL0
TQ1CTL1
TQ1IOC0
TQ1IOC1
TQ1IOC2
TQ1OPT0
TQ1CCR0
TQ1CCR1
TQ1CCR2
TQ1CCR3
TQ1CNT
WTM
00H
TMP3 capture/compare register 0
TMP3 capture/compare register 0
TMP3 counter read buffer register
TMQ1 control register 0
√
√
√
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMQ1 control register 1
00H
TMQ1 I/O control register 0
00H
TMQ1 I/O control register 1
00H
TMQ1 I/O control register 2
00H
TMQ1 timer option register 0
TMQ1 capture/compare register 0
TMQ1 capture/compare register 1
TMQ1 capture/compare register 2
TMQ1 capture/compare register 3
TMQ1 counter read buffer register
Watch timer operation mode register
TMM0 control register 0
00H
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
TM0CTL0
TM0CMP0
OSTS
00H
TMM0 compare register 0
√
0000H
06H
Oscillation stabilization time select register
PLL lockup time specification register
Watchdog timer mode register 2
Watchdog timer enable register
Port function control expansion register 3L
Port function control expansion register 5
Port function control expansion register 9
Port function control expansion register 9L
Port function control expansion register 9H
System status register
√
√
√
√
√
√
PLLS
03H
WDTM2
WDTE
67H
9AH
00H
PFCE3L
PFCE5
√
√
00H
PFCE9
√
0000H
00H
PFCE9L
PFCE9H
SYS
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
00H
00H
Ring OSC mode register
RCM
00H
DMA trigger source register 0
DMA trigger source register 1
DMA trigger source register 2
DMA trigger source register 3
Power save mode register
DTFR0
00H
DTFR1
00H
DTFR2
00H
DTFR3
00H
PSMR
00H
Lock register
LOCKR
PCC
R
00H
Processor clock control register
PLL control register
R/W
03H
PLLCTL
CCLS
01H
CPU operating clock status register
Programmable clock mode register
Clock monitor mode register
Reset source flag register
R
00H
PCLM
R/W
00H
CLM
00H
RESF
00H
161
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(8/9)
Manipulatable Bits
Address
Function Register Name
Symbol
LVIM
R/W
R/W
Default Value
1
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
FFFFF890H
FFFFF891H
FFFFF892H
FFFFF8B0H
FFFFF8B1H
FFFFF9FCH
FFFFF9FEH
FFFFFA00H
FFFFFA01H
FFFFFA02H
FFFFFA03H
FFFFFA04H
FFFFFA06H
FFFFFA07H
FFFFFA10H
FFFFFA11H
FFFFFA12H
FFFFFA13H
FFFFFA14H
FFFFFA16H
FFFFFA17H
FFFFFA20H
FFFFFA21H
FFFFFA22H
FFFFFA23H
FFFFFA24H
FFFFFA26H
FFFFFA27H
FFFFFB00H
FFFFFB04H
FFFFFB08H
FFFFFB0CH
FFFFFB10H
FFFFFB14H
FFFFFB18H
FFFFFB1CH
FFFFFB50H
FFFFFB54H
FFFFFB58H
FFFFFB5CH
Low-voltage detection register
Low-voltage detection level select register
Internal RAM data status register
Prescaler mode register 0
√
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
LVIS
RAMS
√
PRSM0
Prescaler compare register 0
On-chip debug mode register
Peripheral emulation register 1
UARTA0 control register 0
PRSCM0
OCDM
√
√
√
PEMU1
UA0CTL0
UA0CTL1
UA0CTL2
UA0OPT0
UA0STR
UA0RX
UARTA0 control register 1
UARTA0 control register 2
UARTA0 option control register 0
UARTA0 status register
√
√
UARTA0 receive data register
UARTA0 transmit data register
UARTA1 control register 0
R
UA0TX
R/W
UA1CTL0
UA1CTL1
UA1CTL2
UA1OPT0
UA1STR
UA1RX
√
UARTA1 control register 1
UARTA1 control register 2
UARTA1 option control register 0
UARTA1 status register
√
√
UARTA1 receive data register
UARTA1 receive data register
UARTA2 control register 0
R
UA1TX
R/W
UA2CTL0
UA2CTL1
UA2CTL2
UA2OPT0
UA2STR
UA2RX
√
UARTA2 control register 1
UARTA2 control register 2
UARTA2 option control register 0
UARTA2 status register
√
√
UARTA2 receive data register
UARTA2 transmit data register
TIP00 noise eliminator control register
TIP01 noise eliminator control register
TIP10 noise eliminator control register
TIP11 noise eliminator control register
TIP20 noise eliminator control register
TIP21 noise eliminator control register
TIP30 noise eliminator control register
TIP31 noise eliminator control register
TIQ00 noise eliminator control register
TIQ01 noise eliminator control register
TIQ02 noise eliminator control register
TIQ03 noise eliminator control register
R
UA2TX
R/W
P00NFC
P01NFC
P10NFC
P11NFC
P20NFC
P21NFC
P30NFC
P31NFC
Q00NFC
Q01NFC
Q02NFC
Q03NFC
√
√
√
√
√
√
√
√
√
√
√
√
Caution For OCDM details, refer to CHAPTER 26 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
162
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(9/9)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
√
√
√
√
8
√
√
√
√
√
√
16
FFFFFB60H
FFFFFB64H
FFFFFB68H
FFFFFB6CH
FFFFFC00H
FFFFFC02H
FFFFFC06H
TIQ10 noise eliminator control register
Q10NFC
Q11NFC
Q12NFC
Q13NFC
INTF0
00H
TIQ11 noise eliminator control register
00H
TIQ12 noise eliminator control register
00H
TIQ13 noise eliminator control register
00H
External interrupt falling edge specification register 0
External interrupt falling edge specification register 1
External interrupt falling edge specification register 3
00H
INTF1
00H
INTF3
√
0000H
00H
FFFFFC06H External interrupt falling edge specification register 3L INTF3L
FFFFFC07H External interrupt falling edge specification register 3H INTF3H
√
√
√
√
√
√
√
√
√
√
00H
FFFFFC13H
FFFFFC20H
FFFFFC22H
FFFFFC26H
External interrupt falling edge specification register 9H INTF9H
00H
External interrupt rising edge specification register 0
External interrupt rising edge specification register 1
External interrupt rising edge specification register 3
INTR0
INTR1
INTR3
INTR3L
00H
00H
√
0000H
00H
FFFFFC26H External interrupt rising edge specification register 3L
√
√
√
√
√
√
√
√
√
√
FFFFFC27H External interrupt rising edge specification register 3H INTR3H
00H
FFFFFC33H
FFFFFC40H
FFFFFC42H
FFFFFC46H
External interrupt rising edge specification register 9H INTR9H
00H
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
PU0
00H
PU1
00H
PU3
√
√
0000H
00H
FFFFFC46H Pull-up resistor option register 3L
FFFFFC47H Pull-up resistor option register 3H
PU3L
√
√
√
√
√
√
√
√
PU3H
00H
FFFFFC48H
FFFFFC4AH
FFFFFC52H
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 9
PU4
00H
PU5
00H
PU9
0000H
00H
FFFFFC52H Pull-up resistor option register 9L
FFFFFC53H Pull-up resistor option register 9H
PU9L
√
√
√
√
√
√
√
√
√
√
PU9H
00H
FFFFFD00H
FFFFFD01H
FFFFFD02H
FFFFFD03H
FFFFFD04H
CSIB0 control register 0
CSIB0 control register 1
CSIB0 control register 2
CSIB0 status register
CB0CTL0
CB0CTL1
CB0CTL2
CB0STR
CB0RX
CB0RXL
CB0TX
CB0TXL
CB1CTL0
CB1CTL1
CB1CTL2
CB1STR
CB1RX
CB1RXL
CB1TX
CB1TXL
01H
00H
00H
√
00H
CSIB0 receive data register
R
√
√
0000H
00H
FFFFFD04H CSIB0 receive data register L
FFFFFD06H CSIB0 transmit data register
FFFFFD06H CSIB0 transmit data register L
√
R/W
0000H
00H
√
√
√
√
√
FFFFFD10H
FFFFFD11H
FFFFFD12H
FFFFFD13H
FFFFFD14H
CSIB1 control register 0
CSIB1 control register 1
CSIB1control register 2
CSIB1 status register
√
√
01H
00H
00H
√
00H
CSIB1 receive data register
R
√
√
0000H
00H
FFFFFD14H CSIB1 receive data register L
FFFFFD16H CSIB1 transmit data register
FFFFFD16H CSIB1 transmit data register L
√
√
R/W
0000H
00H
163
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CHAPTER 3 CPU FUNCTIONS
3.4.1.4 V850ES/FJ2)
Note The on-chip peripheral I/O differs for µPD70F3237 and µPD70F3238/µPD70F3239.
(1/12)
Manipulatable Bits
Address
Function Register Name
Symbol
PDL
R/W
R/W
Default Value
1
8
16
FFFFF004H
FFFFF004H
FFFFF005H
FFFFF008H
FFFFF00AH
FFFFF00CH
FFFFF00EH
FFFFF024H
FFFFF024H
FFFFF025H
FFFFF028H
FFFFF02AH
FFFFF02CH
FFFFF02EH
FFFFF044H
FFFFF044H
FFFFF045H
FFFFF048H
FFFFF04AH
FFFFF04CH
FFFFF064H
FFFFF066H
FFFFF06EH
FFFFF080H
FFFFF082H
FFFFF084H
FFFFF086H
FFFFF088H
FFFFF08AH
FFFFF08CH
FFFFF08EH
FFFFF090H
FFFFF092H
FFFFF094H
FFFFF096H
FFFFF098H
FFFFF09AH
FFFFF09CH
FFFFF09EH
Port DL
Port DLL
Port DLH
Port CS
Port CT
Port CM
Port CD
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFFFH
√
PDLL
√
√
√
√
√
√
√
√
√
√
√
√
PDLH
PCS
PCT
PCM
PCD
Port mode register DL
PMDL
√
Port mode register DLL
PMDLL
PMDLH
PMCS
PMCT
PMCM
PMCD
PMCDL
PMCDLL
PMCDLH
PMCCS
PMCCT
PMCCM
BPC
FFH
√
√
√
√
√
√
√
√
√
√
√
√
Port mode register DLH
FFH
Port mode register CS
FFH
Port mode register CT
FFH
Port mode register CM
FFH
Port mode register CD
FFH
Port mode control register DL
Port mode control register DLL
Port mode control register DLH
Port mode control register CS
Port mode control register CT
Port mode control register CM
Peripheral I/O area select control register
Bus size configuration register bus
System wait control register
0000H
√
00H
√
√
√
√
√
√
√
√
√
√
00H
00H
00H
00H
0000H
√
√
BSC
5555H
VSWC
DSA0L
DSA0H
DDA0L
DDA0H
DSA1L
DSA1H
DDA1L
DDA1H
DSA2L
DSA2H
DDA2L
DDA2H
DSA3L
DSA3H
DDA3L
DDA3H
77H
√
DMA source address register 0L
DMA source address register 0H
DMA destination address register 0L
DMA destination address register 0H
DMA source address register 1L
DMA source address register 1H
DMA destination address register 1L
DMA destination address register 1H
DMA source address register 2L
DMA source address register 2H
DMA destination address register 2L
DMA destination address register 2H
DMA source address register 3L
DMA source address register 3H
DMA destination address register 3L
DMA destination address register 3H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
164
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CHAPTER 3 CPU FUNCTIONS
(2/12)
Manipulatable Bits
Address
Function Register Name
Symbol
DBC0
R/W
R/W
Default Value
1
8
16
FFFFF0C0H
FFFFF0C2H
FFFFF0C4H
FFFFF0C6H
FFFFF0D0H
FFFFF0D2H
FFFFF0D4H
FFFFF0D6H
FFFFF0E0H
FFFFF0E2H
FFFFF0E4H
FFFFF0E6H
FFFFF100H
FFFFF100H
FFFFF101H
FFFFF102H
FFFFF102H
FFFFF103H
FFFFF104H
FFFFF104H
FFFFF105H
FFFFF106H
FFFFF106H
FFFFF107H
FFFFF108H
FFFFF108H
FFFFF109H
FFFFF10AH
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
DMA transfer count register 0
DMA transfer count register 1
DMA transfer count register 2
DMA transfer count register 3
DMA addressing control register 0
DMA addressing control register 1
DMA addressing control register 2
DMA addressing control register 3
DMA channel control register 0
DMA channel control register 1
DMA channel control register 2
DMA channel control register 3
Interrupt mask register 0
Interrupt mask register 0L
Interrupt mask register 0H
Interrupt mask register 1
Interrupt mask register 1L
Interrupt mask register 1H
Interrupt mask register 2
Interrupt mask register 2L
Interrupt mask register 2H
Interrupt mask register 3
Interrupt mask register 3L
Interrupt mask register 3H
Interrupt mask register 4
Interrupt mask register 4L
Interrupt mask register 4H
Interrupt mask register 5L
Interrupt control register
Undefined
Undefined
Undefined
Undefined
0000H
0000H
0000H
0000H
00H
√
√
√
√
√
√
√
√
DBC1
DBC2
DBC3
DADC0
DADC1
DADC2
DADC3
DCHC0
DCHC1
DCHC2
DCHC3
IMR0
√
√
√
√
√
√
√
√
00H
00H
00H
FFFFH
FFH
√
√
√
√
√
IMR0L
IMR0H
IMR1
√
√
√
√
FFH
FFFFH
FFH
IMR1L
IMR1H
IMR2
√
√
√
√
FFH
FFFFH
FFH
IMR2L
IMR2H
IMR3
√
√
√
√
FFH
FFFFH
FFH
IMR3L
IMR3H
IMR4
√
√
√
√
FFH
FFFFH
FFH
IMR4L
IMR4H
IMR5L
LVIIC
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFH
FFH
47H
Interrupt control register
PIC0
47H
Interrupt control register
PIC1
47H
Interrupt control register
PIC2
47H
Interrupt control register
PIC3
47H
Interrupt control register
PIC4
47H
Interrupt control register
PIC5
47H
Interrupt control register
PIC6
47H
Interrupt control register
PIC7
47H
Interrupt control register
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
47H
Interrupt control register
47H
Interrupt control register
47H
165
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CHAPTER 3 CPU FUNCTIONS
(3/12)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
8
16
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
FFFFF13EH
FFFFF140H
FFFFF142H
FFFFF144H
FFFFF146H
FFFFF148H
FFFFF14AH
FFFFF14CH
FFFFF14EH
FFFFF150H
FFFFF152H
FFFFF154H
FFFFF156H
FFFFF158H
FFFFF15AH
FFFFF15CH
FFFFF15EH
FFFFF160H
FFFFF162H
FFFFF164H
FFFFF166H
FFFFF168H
FFFFF16AH
FFFFF16CH
FFFFF16EH
FFFFF170H
FFFFF172H
FFFFF174H
FFFFF176H
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
TP3OVIC
TP3CCIC0
TP3CCIC1
TM0EQIC0
CB0RIC
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
CB0TIC
CB1RIC
CB1TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
ADIC
C0ERRIC
C0WUPIC
C0RECIC
C0TRXIC
KRIC
WTIIC
WTIC
PIC8
PIC9
PIC10
TQ1OVIC
TQ1CCIC0
TQ1CCIC1
TQ1CCIC2
TQ1CCIC3
UA2RIC
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CHAPTER 3 CPU FUNCTIONS
(4/12)
Manipulatable Bits
Address
Function Register Name
Symbol
UA2TIC
R/W
R/W
Default Value
1
8
16
FFFFF178H
FFFFF17AH
FFFFF17CH
FFFFF17EH
FFFFF180H
FFFFF182H
FFFFF184H
FFFFF186H
FFFFF188H
FFFFF18AH
FFFFF18CH
FFFFF18EH
FFFFF190H
FFFFF192H
FFFFF194H
FFFFF196H
FFFFF198H
FFFFF19AH
FFFFF19CH
FFFFF19EH
FFFFF1A0H
FFFFF1A2H
FFFFF1A4H
FFFFF1A6H
FFFFF1A8H
FFFFF1AAH
FFFFF1ACH
FFFFF1AEH
FFFFF1B0H
FFFFF1B2H
FFFFF1FAH
FFFFF1FCH
FFFFF1FEH
FFFFF200H
FFFFF201H
FFFFF202H
FFFFF203H
FFFFF204H
FFFFF205H
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
In-service priority register
Command register
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
47H
00H
Undefined
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
C1ERRIC
C1WUPIC
C1RECIC
C1TRXIC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
PIC11
PIC12
PIC13
PIC14
TQ2OVIC
TQ2CCIC0
TQ2CCIC1
TQ2CCIC2
TQ2CCIC3
CB2RIC
CB2TIC
UA3RIC
UA3TIC
C2ERRIC
C2WUPIC
C2RECIC
C2TRXIC
C3ERRIC
C3WUPIC
C3RECIC
C3TRXIC
ISPR
R
PRCMD
PSC
W
Power save control register
A/D converter mode register 0
A/D converter mode register 1
A/D converter channel specification register 0
A/D converter mode register 2
Power-fail comparison mode register
Power-fail comparison threshold value register
R/W
√
√
√
√
√
√
√
ADA0M0
ADA0M1
ADA0S
ADA0M2
ADA0PFM
ADA0PFT
167
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CHAPTER 3 CPU FUNCTIONS
(5/12)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R
Default Value
1
8
16
FFFFF210H
FFFFF211H
FFFFF212H
FFFFF213H
FFFFF214H
FFFFF215H
FFFFF216H
FFFFF217H
FFFFF218H
FFFFF219H
FFFFF21AH
A/D conversion result register 0
A/D conversion result register 0H
A/D conversion result register 1
A/D conversion result register 1H
A/D conversion result register 2
A/D conversion result register 2H
A/D conversion result register 3
A/D conversion result register 3H
A/D conversion result register 4
A/D conversion result register 4H
A/D conversion result register 5
ADA0CR0
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
ADA0CR0H
ADA0CR1
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
ADA0CR1H
ADA0CR2
ADA0CR2H
ADA0CR3
ADA0CR3H
ADA0CR4
ADA0CR4H
ADA0CR5
FFFFF21BH A/D conversion result register 5H
FFFFF21CH A/D conversion result register 6
FFFFF21DH A/D conversion result register 6H
ADA0CR5H
ADA0CR6
ADA0CR6H
ADA0CR7
FFFFF21EH
FFFFF21FH
FFFFF220H
FFFFF221H
FFFFF222H
FFFFF223H
FFFFF224H
FFFFF225H
FFFFF226H
FFFFF227H
FFFFF228H
FFFFF229H
FFFFF22AH
A/D conversion result register 7
A/D conversion result register 7H
A/D conversion result register 8
A/D conversion result register 8H
A/D conversion result register 9
A/D conversion result register 9H
A/D conversion result register 10
A/D conversion result register 10H
A/D conversion result register 11
A/D conversion result register 11H
A/D conversion result register 12
A/D conversion result register 12H
A/D conversion result register 13
ADA0CR7H
ADA0CR8
ADA0CR8H
ADA0CR9
ADA0CR9H
ADA0CR10
ADA0CR10H
ADA0CR11
ADA0CR11H
ADA0CR12
ADA0CR12H
ADA0CR13
ADA0CR13H
ADA0CR14
ADA0CR14H
ADA0CR15
ADA0CR15H
ADA0CR16
ADA0CR16H
ADA0CR17
ADA0CR17H
ADA0CR18
ADA0CR18H
ADA0CR19
ADA0CR19H
FFFFF22BH A/D conversion result register 13H
FFFFF22CH A/D conversion result register 14
FFFFF22DH A/D conversion result register 14H
FFFFF22EH
FFFFF22FH
FFFFF230H
FFFFF231H
FFFFF232H
FFFFF233H
FFFFF234H
FFFFF235H
FFFFF236H
FFFFF237H
A/D conversion result register 15
A/D conversion result register 15H
A/D conversion result register 16
A/D conversion result register 16H
A/D conversion result register 17
A/D conversion result register 17H
A/D conversion result register 18
A/D conversion result register 18H
A/D conversion result register 19
A/D conversion result register 19H
168
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CHAPTER 3 CPU FUNCTIONS
(6/12)
Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R
Default Value
1
8
16
FFFFF238H
FFFFF239H
FFFFF23AH
A/D conversion result register 20
A/D conversion result register 20H
A/D conversion result register 21
ADA0CR20
ADA0CR20H
ADA0CR21
ADA0CR21H
ADA0CR22
ADA0CR22H
ADA0CR23
ADA0CR23H
KRM
00H
√
00H
√
√
√
00H
√
√
√
FFFFF23BH A/D conversion result register 21H
FFFFF23CH A/D conversion result register 22
FFFFF23DH A/D conversion result register 22H
00H
00H
00H
FFFFF23EH
FFFFF23FH
FFFFF300H
FFFFF308H
FFFFF30AH
FFFFF318H
FFFFF400H
FFFFF402H
FFFFF406H
FFFFF406H
FFFFF407H
FFFFF408H
FFFFF40AH
FFFFF40CH
A/D conversion result register 23
00H
A/D conversion result register 23H
00H
√
√
√
√
√
√
√
Key return mode register
R/W
00H
√
√
√
√
√
√
Selector operation control register 0
SELCNT0
SELCNT1
NFC
00H
Selector operation control register 1
00H
Noise elimination control register
00H
Port 0
Port 1
Port 3
Port 3L
Port 3H
Port 4
Port 5
Port 6
P0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
FFH
P1
P3
√
√
P3L
√
√
√
√
√
√
√
√
P3H
P4
P5
P6
FFFFF40CH Port 6L
FFFFF40DH Port 6H
P6L
√
√
√
√
√
√
√
√
√
√
P6H
FFFFF40EH
FFFFF40FH
FFFFF410H
FFFFF412H
FFFFF412H
FFFFF413H
FFFFF418H
FFFFF420H
FFFFF422H
FFFFF426H
FFFFF426H
FFFFF427H
FFFFF428H
FFFFF42AH
FFFFF42CH
Port 7L
P7L
Port 7H
P7H
Port 8
P8
Port 9
P9
√
Port 9L
P9L
√
√
√
√
√
√
√
√
√
√
Port 9H
P9H
Port 12
P12
Port mode register 0
Port mode register 1
Port mode register 3
Port mode register 3L
Port mode register 3H
Port mode register 4
Port mode register 5
Port mode register 6
PM0
PM1
FFH
PM3
FFFFH
FFH
√
√
PM3L
PM3H
PM4
√
√
√
√
√
√
√
√
FFH
FFH
PM5
FFH
PM6
FFFFH
169
User’s Manual U17830EE1V0UM00
CHAPTER 3 CPU FUNCTIONS
(7/11)
Manipulatable Bits
Address
Function Register Name
Symbol
PM6L
R/W
R/W
Default Value
1
√
√
√
√
√
8
√
√
√
√
√
16
FFFFF42CH Port mode register 6L
FFFFF42DH Port mode register 6H
FFH
PM6H
PM7L
FFH
FFFFF42EH
FFFFF42FH
FFFFF430H
FFFFF432H
FFFFF432H
FFFFF433H
FFFFF438H
FFFFF440H
FFFFF442H
FFFFF446H
FFFFF446H
FFFFF447H
FFFFF448H
FFFFF44AH
FFFFF44CH
Port mode register 7L
FFH
Port mode register 7H
PM7H
PM8
FFH
Port mode register 8
FFH
Port mode register 9
PM9
√
FFFFH
FFH
Port mode register 9L
PM9L
√
√
√
√
√
√
√
√
√
√
Port mode register 9H
PM9H
PM12
FFH
Port mode register 12
FFH
Port mode control register 0
Port mode control register 1
Port mode control register 3
Port mode control register 3L
Port mode control register 3H
Port mode control register 4
Port mode control register 5
Port mode control register 6
PMC0
PMC1
PMC3
PMC3L
PMC3H
PMC4
PMC5
PMC6
PMC6L
PMC6H
PMC8
PMC9
PMC9L
PMC9H
PFC0
00H
00H
√
0000H
00H
√
√
√
√
√
√
√
√
00H
00H
00H
√
√
0000H
00H
FFFFF44CH Port mode control register 6L
FFFFF44DH Port mode control register 6H
√
√
√
√
√
√
00H
FFFFF450H
FFFFF452H
FFFFF452H
FFFFF453H
FFFFF460H
FFFFF466H
FFFFF46AH
FFFFF46CH
Port mode control register 8
Port mode control register 9
Port mode control register 9L
Port mode control register 9H
Port function control register 0
Port function control register 3L
Port function control register 5
Port function control register 6
00H
0000H
00H
√
√
√
√
√
√
√
√
√
√
00H
00H
PFC3L
PFC5
00H
00H
PFC6
√
√
0000H
00H
FFFFF46CH Port function control register 6L
FFFFF46DH Port function control register 6H
PFC6L
PFC6H
PFC9
√
√
√
√
00H
FFFFF472H
FFFFF472H
FFFFF473H
FFFFF484H
FFFFF488H
FFFFF48AH
FFFFF540H
FFFFF541H
FFFFF542H
FFFFF543H
Port function control register 9
Port function control register 9L
Port function control register 9H
Data wait control register 0
Address wait control register
Bus cycle control register
TMQ0 control register 0
0000H
00H
PFC9L
PFC9H
DWC0
AWC
√
√
√
√
00H
√
√
√
7777H
FFFFH
AAAAH
00H
BCC
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
√
√
√
√
√
√
√
√
TMQ0 control register 1
00H
TMQ0 I/O control register 0
TMQ0 I/O control register 1
00H
00H
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Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
8
√
√
16
FFFFF544H
FFFFF545H
FFFFF546H
FFFFF548H
FFFFF54AH
FFFFF54CH
FFFFF54EH
FFFFF590H
FFFFF591H
FFFFF592H
FFFFF593H
FFFFF594H
FFFFF595H
FFFFF596H
FFFFF598H
FFFFF59AH
FFFFF5A0H
FFFFF5A1H
FFFFF5A2H
FFFFF5A3H
FFFFF5A4H
FFFFF5A5H
FFFFF5A6H
FFFFF5A8H
FFFFF5AAH
FFFFF5B0H
FFFFF5B1H
FFFFF5B2H
FFFFF5B3H
FFFFF5B4H
FFFFF5B5H
FFFFF5B6H
FFFFF5B8H
FFFFF5BAH
FFFFF5C0H
FFFFF5C1H
FFFFF5C2H
FFFFF5C3H
FFFFF5C4H
FFFFF5C5H
FFFFF5C6H
FFFFF5C8H
TMQ0 I/O control register 2
TMQ0 option register 0
TQ0IOC2
TQ0OPT0
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0CCR0
TP0CCR1
TP0CNT
00H
00H
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ0 counter read buffer register
TMP0 control register 0
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP0 control register 1
00H
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register 0
00H
00H
00H
00H
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP1 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1CCR0
TP1CCR1
TP1CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP1 control register 1
00H
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register 0
00H
00H
00H
00H
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP2 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2CCR0
TP2CCR1
TP2CNT
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP2 control register 1
00H
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register 0
00H
00H
00H
00H
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP3 control register 0
√
√
√
0000H
0000H
0000H
00H
R
TP3CTL0
TP3CTL1
TP3IOC0
TP3IOC1
TP3IOC2
TP3OPT0
TP3CCR0
TP3CCR1
R/W
√
√
√
√
√
√
√
√
√
√
√
√
TMP3 control register 1
00H
TMP3 I/O control register 0
TMP3 I/O control register 1
TMP3 I/O control register 2
TMP3 option register 0
00H
00H
00H
00H
TMP3 capture/compare register 0
TMP3 capture/compare register 1
√
√
0000H
0000H
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Manipulatable Bits
Address
Function Register Name
Symbol
TP3CNT
R/W
Default Value
1
8
16
FFFFF5CAH
FFFFF610H
FFFFF611H
FFFFF612H
FFFFF613H
FFFFF614H
FFFFF615H
FFFFF616H
FFFFF618H
FFFFF61AH
FFFFF61CH
FFFFF61EH
FFFFF620H
FFFFF621H
FFFFF622H
FFFFF623H
FFFFF624H
FFFFF625H
FFFFF626H
FFFFF628H
FFFFF62AH
FFFFF62CH
FFFFF62EH
FFFFF680H
FFFFF690H
FFFFF694H
FFFFF6C0H
FFFFF6C1H
FFFFF6D0H
FFFFF6D1H
FFFFF706H
FFFFF70AH
FFFFF712H
FFFFF712H
FFFFF713H
FFFFF802H
FFFFF80CH
FFFFF810H
FFFFF812H
FFFFF814H
FFFFF816H
FFFFF820H
FFFFF824H
TMP3 counter read buffer register
TMQ1 timer control register 0
TMQ1 control register 1
R
√
0000H
00H
TQ1CTL0
TQ1CTL1
TQ1IOC0
TQ1IOC1
TQ1IOC2
TQ1OPT0
TQ1CCR0
TQ1CCR1
TQ1CCR2
TQ1CCR3
TQ1CNT
TQ2CTL0
TQ2CTL1
TQ2IOC0
TQ2IOC1
TQ2IOC2
TQ2OPT0
TQ2CCR0
TQ2CCR1
TQ2CCR2
TQ2CCR3
TQ2CNT
WTM
R/W
√
√
√
√
√
√
√
√
√
√
√
√
00H
TMQ1 I/O control register 0
00H
TMQ1 I/O control register 1
00H
TMQ1 I/O control register 2
00H
TMQ1 timer option register
00H
TMQ1 capture/compare register 0
TMQ1 capture/compare register 1
TMQ1 capture/compare register 2
TMQ1 capture/compare register 3
TMQ1 counter read buffer register
TMQ2 control register 0
√
√
√
√
√
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
√
√
√
√
√
√
TMQ2 control register 1
00H
TMQ2 I/O control register 0
00H
TMQ2 I/O control register 1
00H
TMQ2 I/O control register 2
00H
TMQ2 option register
√
√
√
√
√
√
00H
TMQ2 capture/compare register 0
TMQ2 capture/compare register 1
TMQ2 capture/compare register 2
TMQ2 capture/compare register 3
TMQ2 counter read buffer register
Watch timer operation mode register
TMM0 control register 0
0000H
0000H
0000H
0000H
0000H
00H
R
R/W
√
√
√
√
TM0CTL0
TM0CMP0
OSTS
00H
TMM0 compare register 0
√
0000H
06H
Oscillation stabilization time select register
PLL lockup time specification register
Watchdog timer mode register 2
Watchdog timer enable register
Port function control expansion register 3L
Port function control expansion register 5
Port function control expansion register 9
Port function control expansion register 9L
Port function control expansion register 9H
System status register
√
√
√
√
√
√
PLLS
03H
WDTM2
WDTE
67H
9AH
PFCE3L
PFCE5
√
√
00H
00H
PFCE9
√
0000H
00H
PFCE9L
PFCE9H
SYS
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
00H
00H
Ring OSC mode register
RCM
00H
DMA trigger source register 0
DMA trigger source register 1
DMA trigger source register 2
DMA trigger source register 3
Power save mode register
DTFR0
00H
DTFR1
00H
DTFR2
00H
DTFR3
00H
PSMR
00H
Lock register
LOCKR
R
00H
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Manipulatable Bits
Address
Function Register Name
Symbol
PCC
R/W
R/W
Default Value
1
√
√
√
√
√
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
FFFFF828H
FFFFF82CH
FFFFF82EH
FFFFF82FH
FFFFF870H
FFFFF888H
FFFFF890H
FFFFF891H
FFFFF892H
FFFFF8B0H
FFFFF8B1H
FFFFF9FCH
FFFFF9FEH
FFFFFA00H
FFFFFA01H
FFFFFA02H
FFFFFA03H
FFFFFA04H
FFFFFA06H
FFFFFA07H
FFFFFA10H
FFFFFA11H
FFFFFA12H
FFFFFA13H
FFFFFA14H
FFFFFA16H
FFFFFA17H
FFFFFA20H
FFFFFA21H
FFFFFA22H
FFFFFA23H
FFFFFA24H
FFFFFA26H
FFFFFA27H
FFFFFA30H
FFFFFA31H
FFFFFA32H
FFFFFA33H
FFFFFA34H
FFFFFA36H
FFFFFA37H
Processor clock control register
PLL control register
03H
01H
00H
00H
00H
00H
00H
00H
01H
00H
00H
01H
00H
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
10H
00H
FFH
14H
00H
FFH
FFH
PLLCTL
CCLS
CPU operating clock status register
Programmable clock mode register
Clock monitor mode register
Reset source flag register
R
PCLM
R/W
CLM
RESF
Low-voltage detection register
Low-voltage detection level select register
Internal RAM data status register
Prescaler mode register 0
LVIM
LVIS
RAMS
√
PRSM0
PRSCM0
OCDM
Prescaler compare register 0
On-chip debug mode register
Peripheral emulation register 1
UARTA0 control register 0
UARTA0 control register 1
UARTA0 control register 2
UARTA0 option control register 0
UARTA0 status register
√
√
√
PEMU1
UA0CTL0
UA0CTL1
UA0CTL2
UA0OPT0
UA0STR
UA0RX
√
√
UARTA0 receive data register
UARTA0 transmit data register
UARTA1 control register 0
UARTA1 control register 1
UARTA1 control register 2
UARTA1 option control register 0
UARTA1 status register
R
UA0TX
R/W
UA1CTL0
UA1CTL1
UA1CTL2
UA1OPT0
UA1STR
UA1RX
√
√
√
UARTA1 receive data register
UARTA1 receive data register
UARTA2 control register 0
UARTA2 control register 1
UARTA2 control register 2
UARTA2 option control register 0
UARTA2 status register
R
UA1TX
R/W
UA2CTL0
UA2CTL1
UA2CTL2
UA2OPT0
UA2STR
UA2RX
√
√
√
UARTA2 receive data register
UARTA2 transmit data register
UARTA3 control register 0
UARTA3 control register 1
UARTA3 control register 2
UARTA3 option control register 0
UARTA3 status register
R
UA2TX
R/W
UA3CTL0
UA3CTL1
UA3CTL2
UA3OPT0
UA3STR
UA3RX
√
√
√
UARTA3 receive data register
UARTA3 transmit data register
R
UA3TX
R/W
Caution For OCDM details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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Manipulatable Bits
Address
Function Register Name
Symbol
R/W
R/W
Default Value
1
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
FFFFFB00H
FFFFFB04H
FFFFFB08H
FFFFFB0CH
FFFFFB10H
FFFFFB14H
FFFFFB18H
FFFFFB1CH
FFFFFB50H
FFFFFB54H
FFFFFB58H
FFFFFB5CH
FFFFFB60H
FFFFFB64H
FFFFFB68H
FFFFFB6CH
FFFFFB70H
FFFFFB74H
FFFFFB78H
FFFFFB7CH
FFFFFC00H
FFFFFC02H
FFFFFC06H
TIP00 noise eliminator control register
TIP01 noise eliminator control register
TIP10 noise eliminator control register
TIP11 noise eliminator control register
TIP20 noise eliminator control register
TIP21 noise eliminator control register
TIP30 noise eliminator control register
TIP31 noise eliminator control register
TIQ00 noise eliminator control register
TIQ01 noise eliminator control register
TIQ02 noise eliminator control register
TIQ03 noise eliminator control register
TIQ10 noise eliminator control register
TIQ11 noise eliminator control register
TIQ12 noise eliminator control register
TIQ13 noise eliminator control register
TIQ20 noise eliminator control register
TIQ21 noise eliminator control register
TIQ22 noise eliminator control register
TIQ23 noise eliminator control register
External interrupt falling edge specification register 0
External interrupt falling edge specification register 1
External interrupt falling edge specification register 3
P00NFC
P01NFC
P10NFC
P11NFC
P20NFC
P21NFC
P30NFC
P31NFC
Q00NFC
Q01NFC
Q02NFC
Q03NFC
Q10NFC
Q11NFC
Q12NFC
Q13NFC
Q20NFC
Q21NFC
Q22NFC
Q23NFC
INTF0
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
00H
00H
00H
0000H
00H
00H
00H
00H
00H
00H
00H
0000H
INTF1
INTF3
√
√
√
FFFFFC06H External interrupt falling edge specification register 3L INTF3L
FFFFFC07H External interrupt falling edge specification register 3H INTF3H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFFC0CH
FFFFFC10H
FFFFFC13H
FFFFFC20H
FFFFFC22H
FFFFFC26H
External interrupt falling edge specification register 6L INTF6L
External interrupt falling edge specification register 8 INTF8
External interrupt falling edge specification register 9H INTF9H
External interrupt rising edge specification register 0
External interrupt rising edge specification register 1
External interrupt rising edge specification register 3
INTR0
INTR1
INTR3
INTR3L
FFFFFC26H External interrupt rising edge specification register 3L
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFFC27H External interrupt rising edge specification register 3H INTR3H
FFFFFC2CH
FFFFFC30H
FFFFFC33H
FFFFFC40H
FFFFFC42H
FFFFFC46H
External interrupt rising edge specification register 6L
External interrupt rising edge specification register 8
INTR6L
INTR8
External interrupt rising edge specification register 9H INTR9H
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
PU0
PU1
PU3
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Manipulatable Bits
Address
Function Register Name
Symbol
PU3L
R/W
R/W
Default Value
1
√
√
√
√
8
√
√
√
√
16
FFFFFC46H
FFFFFC47H
FFFFFC48H
FFFFFC4AH
FFFFFC4CH
FFFFFC4CH
FFFFFC4DH
FFFFFC50H
FFFFFC52H
FFFFFC52H
FFFFFC53H
FFFFFD00H
FFFFFD01H
FFFFFD02H
FFFFFD03H
FFFFFD04H
FFFFFD04H
FFFFFD06H
FFFFFD06H
FFFFFD10H
FFFFFD11H
FFFFFD12H
FFFFFD13H
FFFFFD14H
FFFFFD14H
FFFFFD16H
FFFFFD16H
FFFFFD20H
FFFFFD21H
FFFFFD22H
FFFFFD23H
FFFFFD24H
FFFFFD24H
FFFFFD26H
FFFFFD26H
Pull-up resistor option register 3L
Pull-up resistor option register 3H
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 6
Pull-up resistor option register 6L
Pull-up resistor option register 6H
Pull-up resistor option register 8
Pull-up resistor option register 9
Pull-up resistor option register 9L
Pull-up resistor option register 9H
CSIB0 control register 0
00H
PU3H
00H
PU4
00H
PU5
00H
PU6
√
√
0000H
00H
PU6L
√
√
√
√
√
√
PU6H
00H
PU8
00H
PU9
0000H
00H
PU9L
√
√
√
√
√
√
√
√
√
√
PU9H
00H
CB0CTL0
CB0CTL1
CB0CTL2
CB0STR
CB0RX
CB0RXL
CB0TX
CB0TXL
CB1CTL0
CB1CTL1
CB1CTL2
CB1STR
CB1RX
CB1RXL
CB1TX
CB1TXL
CB2CTL0
CB2CTL1
CB2CTL2
CB2STR
CB2RX
CB2RXL
CB2TX
CB2TXL
01H
CSIB0 control register 1
00H
CSIB0 control register 2
00H
CSIB0 status register
√
00H
CSIB0 receive data register
CSIB0 receive data register L
CSIB0 transmit data register
CSIB0 transmit data register L
CSIB1 control register 0
R
√
√
0000H
00H
√
R/W
0000H
00H
√
√
√
√
√
√
√
01H
CSIB1 control register 1
00H
CSIB1control register 2
00H
CSIB1 status register
√
00H
CSIB1 receive data register
CSIB1 receive data register L
CSIB1 transmit data register
CSIB1 transmit data register L
CSIB2 control register 0
R
√
√
0000H
00H
√
R/W
0000H
00H
√
√
√
√
√
√
√
01H
CSIB2 control register 1
00H
CSIB2 control register 2
00H
CSIB2 status register
√
00H
CSIB2 receive data register
CSIB2 receive data register L
CSIB2 transmit data register
CSIB2 transmit data register L
R
√
√
0000H
00H
√
√
R/W
0000H
00H
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CHAPTER 3 CPU FUNCTIONS
3.4.8 Programmable peripheral I/O register
The peripheral I/O area select control register (BPC) is used to select a programmable peripheral I/O register area.
Peripheral I/O registers for the CAN controller are allocated to addresses 03FEC000H to 03FEE6EFH of the
programmable peripheral I/O register area. For details, see CHAPTER 15 CAN CONTROLLER.
(1) Peripheral I/O select control register (BPC)
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
After reset: 0000H
R/W
13 12
Address: FFFFF064H
11 10
15
14
0
9
8
7
6
5
4
3
2
1
0
BPC
PA15
PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PA15
Enable or disable of use of programmable peripheral I/O area
Disable use of programmable peripheral I/O area.
0
1
Enable use of programmable peripheral I/O area.
PA13 to PA0 Setting of resumption address of programmable peripheral I/O area (correspond
to A27 to A14).
Caution Be sure to set the BPC register to 8FFBH when the PA15 bit is set to 1.
Be sure to set the BPC register to 0000H when the PA15 bit is cleared to 0.
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CHAPTER 3 CPU FUNCTIONS
3.4.9 Special registers
Special registers are protected so that no illegal data is written to them in case of a program loop. The V850ES/Fx2
have the following seven special registers.
• Power save control register (PSC)
• Processor clock control register (PCC)
• Clock monitor mode register (CLM)
• Reset source flag register (RESF)
• Low-voltage detection register (LVIM)
• Internal RAM data status register (RAMS)
• On-chip debug mode register (OCDM)
A command register (PRCMD) is provided as a register that protects the special registers from a write operation so
that the application system does not stop inadvertently in case of a program loop. A write access to a special register
is performed in a specific sequence, and an illegal store operation is reported to the system status register (SYS) (if
an operation to read option data (address: 007AH) is illegal due to noise or instantaneous voltage drop, it is also
reported to the system status register (SYS)).
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(1) Setting data to special register
Data is set to the special registers in the following sequence.
<1>
<2>
<3>
<4>
Disable the DMA operation.
Prepare data to be set to a special register, in a general-purpose register.
Write the data prepared in <2> to the command register (PRCMD).
Write the data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction).
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction).
<5> to <9> Insert NOP instructions (five instructions).
<10> Enable DMA operation if necessary.
[Example] To set data to the PSC register (to set standby mode)
ST.B r11, PSMR [r0]
<1> CLR1 0, DCHCn [r0]
<2> MOV 0x02, r10
; Setting PSMR register (setting IDLE1, IDLE2, or software STOP mode).
; Disabling DMA operation. n = 0 to 3
<3> ST.B r10, PRCMD [r0] ; Writing PRCMD register.
<4> ST.B r10, PSC [r0]
<5> NOP
; Setting PSC register.
; Dummy instruction
<6> NOP
; Dummy instruction
<7> NOP
; Dummy instruction
<8> NOP
; Dummy instruction
<9> NOP
; Dummy instruction
<10> SET1 0, DCHCn [r0]
(next instruction)
; Enabling DMA operation. n = 0 to 3
No specific sequence is necessary for reading a special register.
Cautions 1. The instruction that stores data in the command register does not acknowledge an
interrupt. This is because it is assumed that steps <3> and <4> above are executed by
successive store instructions. If an other instruction is written between <3> and <4>, and
if that instruction acknowledges an interrupt, the above sequence may not be established,
causing malfunction.
2. Dummy data is written to the PRCMD register. Use the same general-purpose register as
the one used to set the special register (<4> in the above example) for writing the PRCMD
register (<3>). The same applies when using a general-purpose register for addressing.
3. When shifting to IDLE1, IDLE2, software STOP mode and sub-IDLE mode (STP bit of PSC
register = 1), five NOP instructions or more must be inserted immediately after entering
that mode.
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(2) Command register (PRCMD)
The command register (PRCMD) is an 8-bit register that is used to protect a register that may seriously affect
the system from a write operation, so that the application system does not stop inadvertently in case of a
program loop. Only the first writing of a special register is valid after a write operation is performed on the
PRCMD register in advance. The value written to the PRCMD register can be rewritten only in a specific
sequence, so that an illegal write operation cannot be executed.
The PRCMD register is write-only; in 8-bit units (if this register is read, illegal data is read).
This register becomes undefined at reset.
After reset: Undefined
7
W
Address: FFFFF1FCH
6
5
4
3
2
1
0
PRCMD
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
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(3) System status register (SYS)
A status flag that indicates the overall operating status of the system is allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
This register becomes 00H at reset.
After reset: 00H R/W Address: FFFFF802H
1
0
<0>
2
0
3
0
6
0
7
0
5
0
4
0
SYS
PRERR
Detection of protection error
PRERR
0
1
Protection error did not occur.
Protection error occurred.
The PRERR flag operates under the following conditions.
(a) Setting condition (PRERR flag = 1)
(i) When a write operation is not performed on the PRCMD register and an operation to write a special
register is performed (when <4> in the example in 3.4.9 (1) Setting data to special register is
executed without <3>)
(ii) If a write operation (including a bit manipulation instruction) is performed on an on-chip peripheral I/O
register other than a special register after a write operation to the PRCMD register (when <4> in the
example in 3.4.9 (1) Setting data to special register is not for a special register)
Remark Even if an on-chip peripheral I/O register is read (including a bit manipulation instruction)
between writing the PRCMD register and writing a special register such as an access to the
internal RAM, the PRERR flag is not set, and data can be written to the special register.
(b) Clearing condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag of the SYS register
(ii) When system reset is executed
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write operation to the PRCMD register, the PRERR bit is cleared
to 0 (write priority).
2. If a write operation is performed on the PRCMD register, which is not a special
register immediately after a write operation to the PRCMD register, the PRERR bit is
set to 1.
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3.4.10 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/Fx2.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register (WDTM2）
After setting the OCDM register, set the VSWC register, and set other registers as necessary.
When using the external bus, place each pin in the control mode by setting the port-related registers immediately
after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register is used to control the wait cycle of a bus access to an on-chip peripheral I/O register.
Three clocks are required to access an on-chip peripheral I/O register (when no wait cycle is used). The
V850ES/Fx2 requires a wait cycle depending on the operating frequency used. Set the following value to the
VSWC register.
This register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (fCLK)
32 kHz ≤ fCLK < 16.6 MHz
16.6 MHz ≤ fCLK ≤ 20 MHz
Set Value of VSWC
Number of Wait Cycles
00H
01H
0
1
Remark If an attempt to change the contents of one of the following registers by hardware conflicts with a
CPU access to the register, the register access is kept waiting. Consequently, an access to an on-
chip peripheral I/O register may take a longer time than usual.
Peripheral Function
Timer P (n = 0 to 3)
Register Name
TPnCCR0, TPnCCR1, TPnCNT
Timer P (n = 1, 2)
Watchdog timer 2
A/D converter (n = 0 to 23)
CAN controller
TQnCCR0, TQnCCR1, TQnCCR2, TQnCCR3, TQnCNT
WDTM2
ADA0M0, ADA0CRn, ADA0CRnH
Each control register, each message buffer register
(b) On-chip debug mode register (OCDM)
For details, see CHAPTER 27 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of the watchdog timer 2.
The watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2
register to activate this operation.
For details, refer to CHAPTER 10 FUNCTIONS OF WATCHDOG TIMER 2.
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(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait state. If this wait state occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at
this time are shown below.
(1/2)
Peripheral Function
Register Name
TPnCNT
Access
k
16-bit timer/event counter P (TMP)
(n = 0 to 4)
Read
Write
1 or 2
TPnCCR0, TPnCCR1
• 1st access: No wait
• Continuous write: 3 or 4
Read
Read
Write
1 or 2
1 or 2
16-bit timer/event counter Q (TMQ)
(n= 0 (V850ES/FE2, V850ES/FF2))
(n= 0, 1 (V850ES/FG2))
TQnCNT
TQnCCR0 to TQnCCR3
• 1st access: No wait
• Continuous write: 3 or 4
(n= 0 to 3 (V850ES/FJ2))
Read
Write
1 or 2
3
Watchdog timer 2 (WDT2)
WDTM2
(when WDT2 operating)
A/D converter
ADA0M0
Read
1 or 2
1 or 2
1 or 2
(n= 9 (V850ES/FE2))
(n= 11 (V850ES/FF2))
(n= 15 (V850ES/FG2))
(n= 23 (V850ES/FJ2))
ADA0CR0 to ADA0CRn
ADA0CR0H to ADA0CRnH
Read
Read
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(2/2)
Peripheral Function
CAN controller
Register Name
Access
k
CnGMCTRL,
CnGMCS,
CnGMABT,
CnGMABTD,
CnMASKaL, CnMASKaH,
CnCTRL,
CnLEC,
Read/write
(fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(2 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
(n= 0 (µPD703230))
(n= 0 (µPD70F3231))
(n= 0 (µPD703232))
(n= 0 (µPD703233))
(n = 0, 1 (µPD70F3234))
(n = 0, 1 (µPD70F3235))
(n = 0, 1 (µPD70F3236))
(n = 0, 1 (µPD70F3237))
(n = 0 to 3 (µPD70F3238))
(n = 0 to 3 (µPD70F3239))
(m = 0 to 31, a = 1 to 4)
CnINFO,
CnERC,
CnIE,
CnINTS,
CnBRP,
CnBTR,
CnTS
CnRGPT,
CnTGPT
Write
Read
Read
(fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(2 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
(3 × fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(4 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
CnLIPT,
CnLOPT
(3 × fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(4 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
CnMDATA01m, CnMDATA0m, Write (8 bits)
CnMDATA1m, CnMDATA23m,
(4 × fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(5 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
CnMDATA2m, CnMDATA3m,
Write (16 bits)
(2 × fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(3 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
CnMDATA45m, CnMDATA4m,
CnMDATA5m, CnMDATA67m,
Read (8/16 bits) (3 × fXX/fCANMOD + 1)/(2 + j) (MIN.)Note
(4 × fXX/fCANMOD + 1)/(2 + j) (MAX.)Note
CnMDATA6m, CnMDATA7m,
CnMDLCm,
CnMCONFm,
CnMIDLm,
CnMIDHm,
CnMCTRLm
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Note Digits below the decimal point are rounded up.
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is
generated, it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
Remark fXX:
Main clock frequency = fXX
fCANMOD: CAN module system clock
i:
j:
Values (0) of higher 4 bits of VSWC register
Values (0 or 1) of lower 4 bits of VSWC register
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4.1 Features
O I/O ports: 51 (V850ES/FE2), 67 (V850ES/FF2), 84 (V850ES/FG2), or 128 (V850ES/FJ2)
O Port pins function alternately as other peripheral-function I/O pins
O Can be set in input or output mode in 1-bit units.
4.2 Basic Port Configuration
4.2.1 Basic Port Configuration on V850ES/FE2
The V850ES/FE2 has a total of 51 I/O ports, ports 0, 3 to 5, 7, 9, CM and DL. The port configuration is shown
below.
Figure 4-1. Port Configuration (V850ES/FE2)
P00
P06
P30
P35
P40
P42
P50
P55
P70
P79
P90
P91
P96
Port 0
Port 3
Port 4
Port 5
Port 7
Port 9
P99
P913
P915
PCM0
PCM1
Port CM
Port DL
PDL0
PDL7
Table 4-1 Pin I/O Buffer Power Supplies (V850ES/FE2)
Power Supply
Corresponding Pin
AVREF0
EVDD
Port 7
Port 0, port 3, port 4, port 5, port 9, port CM, port DL, RESET
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4.2.2 Port Configuration on V850ES/FF2
The V850ES/FF2 has a total of 67 I/O ports, ports 0, 3 to 5, 7, 9, CM, CS, CT and DL. The port configuration is
shown below.
Figure 4-2. Port Configuration (V850ES/FF2)
P00
P06
P30
P90
P91
P96
Port 0
Port 3
Port 9
P99
P35
P38
P39
P913
P915
PCM0
PCM3
P40
P42
P50
P55
P70
P711
Port CM
Port CS
Port 4
Port 5
Port 7
PCS0
PCS1
PCT0
PCT1
PCT4
PCT6
Port CT
Port DL
PDL0
PDL11
Table 4-2 Pin I/O Buffer Power Supplies (V850ES/FF2)
Power Supply
Corresponding Pin
AVREF0
EVDD
Port 7
Port 0, Port 3, Port 4, Port 5, Port 9, Port CM, Port CS, Port CT, Port DL, RESET
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4.2.3 Port Configuration on V850ES/FG2
The V850ES/FG2 has a total of 84 I/O ports, ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DL. The port configuration is
shown below.
Figure 4-3. Port Configuration (V850ES/FG2)
P00
P06
P90
P915
Port 0
Port 1
Port 3
Port 9
P10
P11
PCM0
PCM3
Port CM
Port CS
P30
P39
P40
P42
P50
P55
P70
P715
PCS0
PCS1
PCT0
PCT1
PCT4
PCT6
Port 4
Port 5
Port 7
Port CT
Port DL
PDL0
PDL13
Table 4-3 Pin I/O Buffer Power Supplies (V850ES/FG2)
Power Supply
Corresponding Pin
AVREF0
EVDD
BVDD
Port 7
Port 0, port 1, port 3, port 4, port 5, port 9, RESET
Port CM, port CS, port CT, port DL
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4.2.4 Port Configuration on V850ES/FJ2
The V850ES/FJ2 features a total of 128 I/O ports consisting of ports 0, 1, 3 to 9, 12, CD, CM, CS, CT, and DL. The
port configuration is shown below.
Figure 4-4. Port Configuration (V850ES/FJ2)
P00
P06
P90
P915
Port 0
Port 1
Port 3
Port 9
P10
P11
P120
Port 12
Port CD
Port CM
Port CS
Port CT
Port DL
P127
P30
P39
P40
P42
P50
P55
P60
P615
P70
P715
PCD0
PCD3
PCM0
PCM5
PCS0
PCS7
PCT0
PCT7
PDL0
PDL15
Port 4
Port 5
Port 6
Port 7
Port 8
P80
P81
Table 4-4 Pin I/O Buffer Power Supplies (V850ES/FJ2)
Power Supply
Corresponding Pin
AVREF0
BVDD
EVDD
Port 7, port 12
Port CD, port CM, port CS, port CT, port DL
Port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, RESET
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4.3 Port Configuration
The following tables give the relevant registers to configure ports on V850ES/FE2, V850ES/FF2, V850ES/FG2,
V850ES/FJ2.
Table 4-5 Port Configuration (V850ES/FE2)
Item
Configuration
Port mode register (PMn: n = 0, 3, 4, 5, 7L, 7H, 9, CM, or DL)
Port mode control register (PMCn: n = 0, 3, 4, 5, 9, CM, or DL)
Port function control register (PFCn: n = 0, 3L, 5, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Pull-up resistor option register (PUn: n = 0, 3, 4, 5, or 9)
51
Control registers
Ports
Table 4-6 Port Configuration (V850ES/FF2)
Item
Configuration
Port mode register (PMn: n = 0, 3, 4, 5, 7L, 7H, 9, CM, CS, CT, or DL)
Port mode control register (PMCn: n = 0, 3, 4, 5, 9, CM, CS, CT, or DL)
Port function control register (PFCn: n = 0, 3L, 5, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Pull-up resistor option register (PUn: n = 0, 3, 4, 5, or 9)
67
Control registers
Ports
Table 4-7 Port Configuration (V850ES/FG2)
Item
Configuration
Port mode register (PMn: n = 0, 1, 3, 4, 5, 7L, 7H, 9, CM, CS, CT, or DL)
Port mode control register (PMCn: n = 0, 1, 3, 4, 5, 9, CM, or DL)
Port function control register (PFCn: n = 0, 3L, 5, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Pull-up resistor option register (PUn: n = 0, 1, 3, 4, 5, or 9)
84
Control registers
Ports
Table 4-8 Port Configuration (V850ES/FJ2)
Item
Configuration
Control registers
Port mode register (PMn: n = 0, 1, 3, 4, 5, 6, 7L, 7H, 8, 9, 12, CD, CM, CS, CT, or DL)
Port mode control register (PMCn: n = 0, 1, 3, 4, 5, 6, 8, 9, CD, CM, CS, CT, or DL)
Port function control register (PFCn: n = 0, 3L, 5, 6, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Pull-up resistor option register (PUn: n = 0, 1, 3, 4, 5, 6, 8, or 9)
128
Ports
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(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
After reset: 00H (output latch)
R/W
7
7
6
5
3
2
1
0
Pn
Pn7
Pn6
Pn5
Pn4
Pn3
Pn2
Pn1
Pn0
Pnm
Control of output data (in output mode)
0
1
Outputs 0
Outputs 1
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Table 4-9 Writing/Reading Pn Register
Setting of PMn Register
Writing to Pn Register
Data is written to the output latchNote
Reading from Pn Register
Output mode
(PMnm = 0)
.
The value of the output latch is read.
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
Input mode
(PMnm = 1)
Data is written to the output latch.
The pin status is read.
The pin status is not affectedNote
.
Note The value written to the output latch is retained until a new value is written to the output latch.
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(2) Port n mode register (PMn)
The PMn register specifies the input or output mode of the corresponding port pin.
Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit
units.
After reset: FFH
R/W
PMn
PMn7
PMn6
PMn5
PMn4
PMn3
PMn2
PMn1
PMn0
PMnm
Control of input/output mode
0
1
Output mode
Input mode
(3) Port n mode control register (PMCn)
The PMCn register specifies the port mode or alternate function.
Each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit
units.
After reset: 00H
R/W
PMCn
PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0
PMCnm
Specification of operation mode
0
1
Port mode
Alternate function mode
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(4) Port n function control register (PFCn)
The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be
specified in 1-bit units.
After reset: 00H
R/W
PFCn
PFCn7
PFCn6
PFCn5
PFCn4
PFCn3
PFCn2
PFCn1
PFCn0
PFCnm
Specification of alternate function
0
1
Alternate function 1
Alternate function 2
(5) Port n function control expansion register (PFCEn)
The PFCEn register specifies the alternate function of a port pin to be used if the pin has three or more
alternate functions.
Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be
specified in 1-bit units.
After reset: 00H
R/W
PFCEn PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0
PFCn
PFCn7
PFCn6
PFCn5
PFCn4
PFCn3
PFCn2
PFCn1
PFCn0
PFCEnm PFCnm
Specification of alternate function
0
0
1
1
0
1
0
1
Alternate function 1
Alternate function 2
Alternate function 3
Alternate function 4
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(6) Port n function register (PFn)
The PFn register specifies normal output or N-ch open-drain output.
Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified
in 1-bit units.
After reset: 00H
R/W
PFn
PFn7
PFn6
PFn5
PFn4
PFn3
PFn2
PFn1
PFn0
PFnmNote
Control of normal output/N-ch open-drain output
Normal output (CMOS output)
N-ch open-drain output
0
1
Note The PFnm bit of the PFn register is valid only when the PMnm bit of the PMn register is 0 (when the
output mode is specified) in port mode (PMCnm bit = 0). When the PMnm bit is 1 (when the input mode
is specified), the set value of the PFn register is invalid.
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(7) Port setting
Set a port as illustrated below.
Figure 4-5. Setting of Each Register and Pin Function
Port mode
Output mode
Input mode
“0”
PMn register
“1”
Alternate function
(when two alternate
functions are available)
“0”
Alternate function 1
Alternate function 2
“0”
PFCn register
PMCn register
“1”
Alternate function
(when three or more alternate
functions are available)
“1”
Alternate function 1
Alternate function 2
Alternate function 3
Alternate function 4
(a)
(b)
PFCn register
PFCEnm PFCnm
(c)
PFCEn register
(d)
(a)
(b)
(c)
(d)
0
0
1
1
0
1
0
1
Remark Set the alternate functions in the following sequence.
<1> Set the PFCn and PFCEn registers.
<2> Set the PFCn register.
<3> Set the INTRn or INTFn register (to specify an external interrupt pin).
If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn
registers are being set.
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4.3.1 Port 0
Port 0 is a 7-bit (P00 to P06) port for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins is the same for all products.
Product
Number of I/O Port Pins
7-bit I/O port (P00 to P06)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
(1) Functions of port 0
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 0 (P0)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 0 (PM0)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 0 (PMC0)
• Control mode 1 or control mode 2 can be specified in 1-bit units.
Specified by port function control register 0 (PFC0)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 0 (PU0)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 0 (INTF0) and external interrupt rising edge
specification register 0 (INTR0)
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Port 0 includes the following alternate-function pins.
Table 4-10 Alternate-Function Pins of Port 0
Pin Name
P00
Alternate-Function Pin Name
I/O
I/O
Remark
Block Type
G-1
Port 0
TP31/TOP31
TP30/TOP30
NMI Note 1
P01
G-1
P02
L-1
P03
INTP0/ADTRG
N-1
P04
INTP1
L-1
P05
INTP2/DRSTNote 2
INTP3
AA-1
L-2
P06
Notes 1. The NMI pin is used in combination with the P02 pin.
(1) After reset the P02 pin function is active. Set the PMC0.PMC02 bit when you make NMI effective.
(2) Moreover, the NMI pin initialization is "No edge detection". Select an effective edge of the NMI pin by
the INTF0 and the INTR0 register.
2. The DRST pin is for on-chip debugging (flash memory version only).
If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset
signal of the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). Although the mask
ROM versions do not support the on-chip debug mode, handle the P05/INTP2 pin the same as in flash
memory versions.
For details, see 4.4.3 Cautions on on-chip debug pins.
Caution: The P00 to P06 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 0 (P0)
Port register 0 (P0) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
7
R/W
6
Address: FFFFF400H
5
4
3
2
1
0
P0
0
P06
P05
P04
P03
P02
P01
P00
P0n
0
Control of output data (in output mode) (n = 0 to 6)
Output 0.
Output 1.
1
(b) Port mode register 0 (PM0)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
7
R/W
6
Address: FFFFF420H
5
4
3
2
1
0
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
PM0n
Control of input/output mode (n = 0 to 6)
0
1
Output mode
Input mode
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(c) Port mode control register 0 (PMC0)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
7
R/W
6
Address: FFFFF440H
5
4
3
2
1
0
PMC0
0
PMC06
PMC05
PMC04
PMC03
PMC02
PMC01
PMC00
PMC06
Specification of operation mode of P06 pin
Specification of operation mode of P05 pin
Specification of operation mode of P04 pin
Specification of operation mode of P03 pin
Specification of operation mode of P02 pin
Specification of operation mode of P01 pin
Specification of operation mode of P00 pin
0
1
I/O port
INTP3 input
PMC05
0
1
I/O port
INTP2/DRST input
PMC04
0
1
I/O port
INTP1 input
PMC03
0
1
I/O port
INTP0/ADTRG input
PMC02
0
1
I/O port
NMI input
PMC01
0
1
I/O port
TIP30/TOP30 I/O
PMC00
0
1
I/O port
TIP31/TOP31 I/O
Caution The P05/INTP2/DRST pin functions as the DRST pin when the OCDM0 bit of the OCDM
register is 1, regardless of the value of the PMC05 bit.
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(d) Port function control register 0 (PFC0)
This is an 8-bit register that specifies control mode 1 or control mode 2. It can be read or written in 8-bit or
1-bit units.
After reset: 00H
7
R/W
6
Address: FFFFF460H
5
0
4
0
3
2
0
1
0
PFC0
0
0
PFC03
PFC01
PFC00
PFC03
Specification of operation mode when P03 pin is in control mode
0
1
INTP0 input
ADTRG input
PFC01
Specification of operation mode when P01 pin is in control mode
0
1
TIP30 input
TOP30 output
PFC00
Specification of operation mode when P00 pin is in control mode
0
1
TIP31 input
TOP31 output
(e) Pull-up resistor option register 0 (PU0)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H
7
R/W
6
Address: FFFFFC40H
5
4
3
2
1
0
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
PU0n
Control of on-chip pull-up resistor connection (n = 0 to 6)
0
1
Not connected
Connected
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(f) External interrupt falling edge specification register 0 (INTF0)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, refer to
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After reset: 00H
7
R/W
6
Address: FFFFFC00H
5
4
3
2
1
0
0
0
INTF0
0
INTF06
INTF05
INTF04
INTF03
INTF02
Remark Refer to Table 4-11 for how to specify a valid edge.
(g) External interrupt rising edge specification register 0 (INTR0)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, refer to
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After reset: 00H
7
R/W
6
Address: FFFFFC20H
5
4
3
2
1
0
0
0
INTR0
0
INTR06
INTR05
INTR04
INTR03
INTR02
Remark Refer to Table 4-11 for how to specify a valid edge.
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Table 4-11 Valid Edge Specification
INTF0n Bit
INTR0n Bit
Valid Edge Specification (n = 2 to 6)
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both edges
Remark n = 2: Control of NMI pin
n = 3: Control of INTP0 pin
n = 4: Control of INTP1 pin
n = 5: Control of INTP2 pin
n = 6: Control of INTP3 pin
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4.3.2 Port 1
Port 1 is a 2-bit port (P10 and P11) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
-
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
2-bit I/O port (P10 and P11)
(1) Functions of port 1
O The input/output data of the port can be specified in 1-bit units.
Specified by port register 1 (P1)
O The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 1 (PM1)
O Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 1 (PMC1)
O An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 1 (PU1)
O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 1 (INTF1) and external interrupt rising edge
specification register 1 (INTR1)
Port 1 functions alternately as the following pins.
Table 4-12 Alternate-Function Pins of Port 1
Pin Name
P10
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
L-1
Port 1
INTP9
P11
INTP10
L-1
Caution: The P10 to P11 pins have hysteresis characteristics in the input mode of the alternate function,
but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 1 (P1)
Port register 1 (P1) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF402H
(i) V850ES/FG2, V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
P1
0
P11
P10
P1n
0
Control of output data (in output mode) (n = 0, 1)
Output 0.
Output 1.
1
(b) Port mode register 1 (PM1)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF422H
(i) V850ES/FG2, V850ES/FJ2
7
6
1
5
1
4
1
3
1
2
1
1
0
PM1
1
PM11
PM10
PM1n
Control of input/output mode (n = 0, 1)
0
1
Output mode
Input mode
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(c) Port mode control register 1 (PMC1)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF442H
(i) V850ES/FG2, V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
PMC1
0
PMC11
PMC10
PMC11
Specification of operation mode of P11 pin
0
1
I/O port
INTP10 input
PMC10
Specification of operation mode of P10 pin
0
1
I/O port
INTP9 input
(d) Pull-up resistor option register 1 (PU1)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFFC42H
(i) V850ES/FG2, V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
PU1
0
PU11
PU10
PU1n
Control of on-chip pull-up resistor connection (n = 0, 1)
0
1
Not connected
Connected
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(e) External interrupt falling edge specification register 1 (INTF1)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC02H
(i) V850ES/FG2, V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
INTF1
0
INTF11
INTF10
Remark Refer to Table 4-13 for how to specify a valid edge.
(f) External interrupt rising edge specification register 1 (INTR1)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC22H
(i) V850ES/FG2, V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
INTR1
0
INTR11
INTR10
Remark Refer to Table 4-13 for how to specify a valid edge.
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Table 4-13 Valid Edge Specification
INTF1n Bit
INTR1n Bit
Valid Edge Specification (n = 0, 1)
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both edges
Remark
n = 0: Control of INTP9 pin
n = 1: Control of INTP10 pin
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4.3.3 Port 3
Port 3 is a 10-bit port (P30 to P39) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
6-bit I/O port (P30 to P35)
8-bit I/O port (P30 to P35, P38, P39)Note
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
10-bit I/O port (P30 to P39)
Note In the V850ES/FF2, the alternate functions of the P38 and P39 pins (TXDA2, RXDA2/INTP8) are not
available.
(1) Function of port 3
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 3 (P3)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 3 (PM3)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 3 (PMC3)
• Control mode can be specified in 1-bit units.
Specified by port function control register 3 (PFC3) and port function control expansion register 3L
(PFCE3L)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 3 (PU3)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 3 (INTF3) and external interrupt rising edge
specification register 3 (INTR3)
Port 3 functions alternately as the following pins.
Table 4-14 Alternate-Function Pins of Port 3
Pin Name
P30
Alternate-Function Pin Name
TXDA0
I/O
I/O
Remark
Block Type
E-2
Port 3
P31
RXDA0/INTP7
ASCKA0/TIP00/TOP00/TOP01
TIP01/TOP01/CTXD0
TIP10/TOP10/CRXD0
TIP11/TOP11
L-2
P32
U-13
U-3
P33
P34
U-2
P35
G-1
P36
CTXD1
E-2
P37
CRXD1
E-1
P38
TXDA2
E-2
P39
RXDA2/INTP8
L-2
Caution:
206
The P31 to P35, P37, P39 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
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CHAPTER 4 PORT FUNCTIONS
(2) Registers
(a) Port register 3 (P3)
Port register 3 (P3) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P3 register are used as the P3H register, and the lower 8 bits as the P3L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF406H, FFFFF407H
(i) V850ES/FE2
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
P3 (P3HNote
)
7
6
5
4
3
2
1
0
(P3L)
0
0
P35
P34
P33
P32
P31
P30
(ii) V850ES/FF2
15
0
14
0
13
0
12
0
11
0
10
0
9
8
P3 (P3HNote
)
P39
1
P38
0
7
6
5
4
3
2
(P3L)
0
0
P35
P34
P33
P32
P31
P30
(iii) V850ES/FG2, V850ES/FJ2
15
14
0
13
0
12
0
11
0
10
0
9
8
P3 (P3HNote
)
0
7
P39
1
P38
0
6
5
4
3
2
(P3L)
P37
P36
P35
P34
P33
P32
P31
P30
P3n
0
Control of output data (in output mode) (n = 0 to 9)
Output 0.
Output 1.
1
Note To read or write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P3H register. Note that the V850ES/FE2 is not provided with a P3H register. Therefore,
the P3 register can be used only as the P3L register in the V850ES/FE2.
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(b) Port mode register 3 (PM3)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM3 register are used as the PM3H register, and the lower 8 bits as the PM3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF426H, FFFFF427H
(i) V850ES/FE2
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
PM3 (PM3HNote
)
7
6
5
4
3
2
1
0
(PM3L)
1
1
PM35
PM34
PM33
PM32
PM31
PM30
(ii) V850ES/FF2
15
1
14
1
13
1
12
1
11
1
10
1
9
8
PM3 (PM3HNote
)
PM39
1
PM38
7
6
5
4
3
2
0
(PM3L)
1
1
PM35
PM34
PM33
PM32
PM31
PM30
(iii) V850ES/FG2, V850ES/FJ2
15
14
1
13
1
12
1
11
1
10
1
9
8
PM3 (PM3HNote
)
1
7
PM39
1
PM38
6
5
4
3
2
0
(PM3L)
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
PM3n
Control of I/O mode (n = 0 to 9)
0
1
Output mode
Input mode
Note To read or write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM3H register. Note that the V850ES/FE2 is not provided with a PM3H register.
Therefore, the PM3 register can be used only as the PM3L register in the V850ES/FE2.
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(c) Port mode control register 3 (PMC3)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC3 register are used as the PMC3H register, and the lower 8 bits as the
PMC3L register, however, these registers can be read or written in 8-bit or 1-bit units.
(1/2)
After reset: 0000H
R/W
Address: FFFFF446H, FFFFF447H
(i) V850ES/FE2, V850ES/FF2
15
14
0
13
12
11
10
9
8
PMC3 (PMC3HNote 1
)
0
7
0
0
5
0
4
0
3
0
2
0
1
0
0
6
(PMC3L)
0
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
(ii) V850ES/FG2, V850ES/FJ2
15
14
13
12
11
10
9
8
PMC3 (PMC3HNote 1
)
0
7
0
6
0
5
0
4
0
3
0
2
PMC39
1
PMC38
0
(PMC3L)
PMC37
PMC36
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
PMC39
Specification of operation mode of P39 pin
0
1
I/O port
RXDA2/INTP8 inputNote 2
PMC38
Specification of operation mode of P38 pin
0
1
I/O port
TXDA2 output
Notes 1. To read or write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as
bits 0 to 7 of the PMC3H register. Note that the V850ES/FE2, V850ES/FF2 are not provided
with a PMC3H register. Therefore, the PMC3 register can be used only as the PMC3L
register in the V850ES/FE2, V850ES/FF2.
2. The INTP8 pin functions alternately as the RXDA2 pin. To use as the RXDA2 pin, invalidate
the edge detection function of the alternate-function INTP8 pin (by fixing the INTF39 bit of
the INTF3 register to 0 and the INTR39 bit of the INTR3 register to 0). To use as the INTP8
pin, stop the reception operation of UARTA2 (by clearing the UA2RXE bit of the UA2CTL0
register to 0).
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(2/2)
PMC37
Specification of operation mode of P37 pin
0
1
I/O port
CRXD1 input
PMC36
Specification of operation mode of P36 pin
Specification of operation mode of P35 pin
Specification of operation mode of P34 pin
0
1
I/O port
CTXD1 output
PMC35
0
1
I/O port
TIP11/TOP11 I/O
PMC34
0
1
I/O port
TIP10/TOP10/CRXD0 I/O
PMC33
Specification of operation mode of P33 pin
0
1
I/O port
TIP01/TOP01/CTXD0 I/O
PMC32
Specification of operation mode of P32 pin
0
1
I/O port
ASCKA0/TIP00/TOP00/TOP01 I/O
PMC31
Specification of operation mode of P31 pin
0
1
I/O port
RXDA0/INTP7 inputNote
PMC30
Specification of operation mode of P30 pin
0
1
I/O port
TXDA0 output
Note The INTP7 pin functions alternately as the RXDA0 pin. To use as the RXDA0 pin, invalidate the
edge detection function of the alternate-function INTP7 pin (by fixing the INTF31 bit of the
INTF3 register to 0 and the INTR31 bit of the INTR3 register to 0). To use as the INTP7 pin,
stop the reception operation of UARTA0 (by clearing the UA0RXE bit of the UA0CTL0 register to
0).
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(d) Port function control register 3L (PFC3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H
7
R/W
6
Address: FFFFF466H
5
4
3
2
1
0
0
0
PFC3L
0
0
PFC35
PFC34
PFC33
PFC32
Remark For how to specify a control mode, refer to 4.3.4 (2) (f) Setting of control mode of P3 pin.
(e) Port function control expansion register 3L (PFCE3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H
7
R/W
6
Address: FFFFF706H
5
0
4
3
2
1
0
0
0
PFCE3L
0
0
PFCE34
PFCE33
PFCE32
Remark For how to specify a control mode, refer to 4.3.4 (2) (f) Setting of control mode of P3 pin.
(f) Setting of control mode of P3 pin
PFC35
Specification of control mode of P35 pin
0
1
TIP11 input
TOP11 output
PFCE34
PFC34
Specification of control mode of P34 pin
0
0
1
1
0
1
0
1
TIP10 input
TOP10 output
CRXD0 input
Setting prohibited
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PFCE33
PFC33
Specification of control mode of P33 pin
0
0
1
1
0
1
0
1
TIP01 input
TOP01 output
CTXD0 output
Setting prohibited
PFCE32
PFC32
Specification of control mode of P32 pin
0
0
1
1
0
1
0
1
ASCKA0 input
TOP01 output
TIP00 input
TOP00 output
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(g) Pull-up resistor option register 3 (PU3)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16- or 1-bit units.
If the higher 8 bits of the PU3 register are used as the PU3H register, and the lower 8 bits as the PU3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFFC46H, FFFFFC47H
(i) V850ES/FE2
15
14
0
13
0
12
0
11
0
10
0
9
0
8
0
PU3 (PU3HNote
)
0
7
0
6
5
4
3
2
1
0
(PU3L)
0
PU35
PU34
PU33
PU32
PU31
PU30
(ii) V850ES/FF2
15
0
14
0
13
0
12
0
11
0
10
0
9
8
PU3 (PU3HNote
)
PU39
1
PU38
0
7
6
5
4
3
2
(PU3L)
0
0
PU35
PU34
PU33
PU32
PU31
PU30
(iii) V850ES/FG2, V850ES/FJ2
15
14
0
13
0
12
0
11
0
10
0
9
8
PU3 (PU3HNote
)
0
7
PU39
1
PU38
0
6
5
4
3
2
(PU3L)
PU37
PU36
PU35
PU34
PU33
PU32
PU31
PU30
PU3n
Control of on-chip pull-up resistor connection (n = 0 to 9)
0
1
Not connected
Connected
Note To read/write bits 8 to 15 of the PU3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU3H register. Note that the V850ES/FE2 is not provided with a PU3H register.
Therefore, the PU3 register can be used only as the PU3L register in the V850ES/FE2.
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(h) External interrupt falling edge specification register 3 (INTF3)
This is a 16-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTF3 register are used as the INTF3H register, and the lower 8 bits as the
INTF3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC06H, FFFFFC07H
(i) V850ES/FE2, V850ES/FF2
15
14
0
13
0
12
0
11
0
10
0
9
8
0
0
0
INTF3 (INTF3HNote
)
0
7
0
0
1
6
5
4
3
2
(INTF3L)
0
0
0
0
0
INTF31
(ii) V850ES/FG2, V850ES/FJ2
15
14
0
13
0
12
0
11
0
10
0
9
8
0
0
0
INTF3 (INTF3HNote
)
0
7
0
INTF39
1
6
5
4
3
2
(INTF3L)
0
0
0
0
0
INTF31
Note To read/write bits 8 to 15 of the INTF3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTF3H register. Note that the V850ES/FE2, V850ES/FF2 is not provided with an
INTF3H register. Therefore, the INTF3 register can be used only as the INTF3L register in the
V850ES/FE2, V850ES/FE2.
Remark Refer to Table 4-15 for how to specify a valid edge.
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(i) External interrupt rising edge specification register 3 (INTR3)
This is a 16-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTR3 register are used as the INTR3H register, and the lower 8 bits as the
INTR3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC26H, FFFFFC27H
(i) V850ES/FE2, V850ES/FF2
15
14
0
13
0
12
0
11
0
10
0
9
8
0
0
0
INTR3 (INTR3HNote
)
0
7
0
0
1
6
5
4
3
2
(INTR3L)
0
0
0
0
0
INTR31
(ii) V850ES/FG2, V850ES/FJ2
15
14
0
13
0
12
0
11
0
10
0
9
8
0
0
0
INTR3 (INTR3HNote
)
0
7
0
INTR39
1
6
5
4
3
2
(INTR3L)
0
0
0
0
0
INTR31
Note To read/write bits 8 to 15 of the INTR3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTR3H register. Note that the V850ES/FE2, V850ES/FF2 is not provided with an
INTR3H register. Therefore, the INTR3 register can be used only as the INTR3L register in the
V850ES/FE2, V850ES/FF2.
Remark Refer to 4-15 for how to specify a valid edge.
Table 4-15 Valid Edge Specification
INTF3n Bit
INTR3n Bit
Valid Edge Specification (n = 1, 9)
No edge detected
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
Remark n = 1: Control of INTP7 pin
n = 9: Control of INTP8 pin
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4.3.4 Port 4
Port 4 is a 3-bit port (P40 to P42) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins is the same for all products.
Product
Number of I/O Port Pins
3-bit I/O port (P40 to P42)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
(1) Functions of port 4
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 4 (P4)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 4 (PM4)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 4 (PMC4)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 4 (PU4)
Port 4 functions alternately as the following pins.
Table 4-16 Alternate-Function Pins of Port 4
Pin Name
P40
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
E-1
Port 4
SIB0
P41
SOB0
SCKB0
E-2
P42
E-3
Caution:
The P40 to P42 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 4 (P4)
Port register 4 (P4) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
7
R/W
6
Address: FFFFF408H
5
0
4
0
3
0
2
1
0
P4
0
0
P42
P41
P40
P4n
0
Control of output data (in output mode) (n = 0 to 2)
Output 0.
Output 1.
1
(b) Port mode register 4 (PM4)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
7
R/W
6
Address: FFFFF428H
5
1
4
1
3
1
2
1
0
PM4
1
1
PM42
PM41
PM40
PM4n
Control of input/output mode (n = 0 to 2)
0
1
Output mode
Input mode
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(c) Port mode control register 4 (PMC4)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
7
R/W
6
Address: FFFFF448H
5
0
4
0
3
0
2
1
0
PMC4
0
0
PMC42
PMC41
PMC40
PMC42
Specification of operation mode of P42 pin
Specification of operation mode of P41 pin
Specification of operation mode of P40 pin
0
1
I/O port
SCKB0 input/output
PMC41
0
1
I/O port
SOB0 output
PMC40
0
1
I/O port
SIB0 input
(d) Pull-up resistor option register 4 (PU4)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H
7
R/W
6
Address: FFFFFC48H
5
0
4
0
3
0
2
1
0
PU4
0
0
PU42
PU41
PU40
PU4n
Control of on-chip pull-up resistor connection (n = 0 to 2)
0
1
Not connected
Connected
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4.3.5 Port 5
Port 5 is a 6-bit port (P50 to P55) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins is the same for all products.
Product
Number of I/O Port Pins
6-bit I/O port (P50 to P55)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
(1) Functions of port 5
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 5 (P5)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 5 (PM5)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 5 (PMC5)
• Control mode can be specified in 1-bit units.
Specified by port function control register 5 (PFC5) or port function control expansion register 5 (PFCE5)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 5 (PU5)
Port 5 functions alternately as the following pins.
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Table 4-17 Alternate-Function Pins of Port 5
Pin Name
P50
Alternate-Function Pin Name
I/O
I/O
Remark
Block Type
U-4
Port 5
KR0/TIQ01/TOQ01
KR1/TIQ02/TOQ02
KR2/TIQ03/TOQ03/DDINote
KR3/TIQ00/TOQ00/DDONote
KR4/DCKNote
–
P51
U-4
P52
U-5
P53
U-6
P54
G-2
P55
KR5/DMSNote
G-2
Caution:
The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate function,
but do not have hysteresis characteristics in the port mode.
Note The DDI, DDO, DCK, and DMS pins are for the on-chip debug function. To use the DDI, DDO, DCK,
and DMS pins as port pins, not as on-chip debug pins, the following actions must be taken.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the above
actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05
pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not
necessary to manipulate the OCDM0 bit of the OCDM register.
Because a pull-down resistor (30 kΩ TYP) is connected to the buffer of the P05/INTP2/DRST pin, the
pin does not have to be fixed to the low level by an external source. The pull-down resistor is
disconnected by clearing the OCDM0 bit to 0.
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(2) Registers
(a) Port register 5 (P5)
Port register 5 (P5) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
7
R/W
6
Address: FFFFF40AH
5
4
3
2
1
0
P5
0
0
P55
P54
P53
P52
P51
P50
P5n
0
Control of output data (in output mode) (n = 0 to 5)
Output 0.
Output 1.
1
(b) Port mode register 5 (PM5)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
7
R/W
6
Address: FFFFF42AH
5
4
3
2
1
0
PM5
1
1
PM55
PM54
PM53
PM52
PM51
PM50
PM5n
Control of I/O mode (n = 0 to 5)
0
1
Output mode
Input mode
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(c) Port mode control register 5 (PMC5)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
Caution If the control mode is specified by using the PMC5 register when the PFC5n bit of the
PFC5 register and the PFCE5n bit of the PFCE5 register are the default values (0), the
output becomes undefined.
For this reason, first set the PFC5n bit of the PFC5 register and the PFCE5n bit of the
PFCE5 register, and then set the PMC5n bit to 1 to set the control mode.
After reset: 00H
7
R/W
6
Address: FFFFF44AH
5
4
3
2
1
0
PMC5
0
0
PMC55
PMC54
PMC53
PMC52
PMC51
PMC50
PMC55
Specification of operation mode of P55 pin
Specification of operation mode of P54 pin
Specification of operation mode of P53 pin
0
1
I/O port
KR5 input
PMC54
0
1
I/O port
KR4 input
PMC53
0
1
I/O port
KR3/TIQ00/TOQ00 I/O
PMC52
Specification of operation mode of P52 pin
0
1
I/O port
KR2/TIQ03/TOQ03 I/O
PMC51
Specification of operation mode of P51 pin
0
1
I/O port
KR1/TIQ02/TOQ02 I/O
PMC50
Specification of operation mode of P50 pin
0
1
I/O port
KR0/TIQ01/TOQ01 I/O
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(d) Port function control register 5 (PFC5)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H
7
R/W
6
Address: FFFFF46AH
5
4
3
2
1
0
PFC5
0
0
PFC55
PFC54
PFC53
PFC52
PFC51
PFC50
Remark For how to specify a control mode, refer to 4.3.6 (2) (f) Setting of control mode of P5 pin.
(e) Port function control expansion register 5 (PFCE5)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After reset: 00H
7
R/W
6
Address: FFFFF70AH
5
0
4
0
3
2
1
0
PFCE5
0
0
PFCE53
PFCE52
PFCE51
PFCE50
Remark For how to specify a control mode, refer to 4.3.6 (2) (f) Setting of control mode of P5 pin.
(f) Setting of control mode of P5 pin
Caution If the control mode is specified by using the PMC5 register when the PFC5n bit of the
PFC5 register and PFCE5n bit of the PFCE5 register are the default values (0), the output
becomes undefined.
For this reason, first set the PFC5n bit of the PFC5 register and the PFCE5n bit of the
PFCE5 register, and then set the PMC5n bit to 1 to set the control mode.
PFC55
Specification of control mode of P55 pin
Specification of control mode of P54 pin
0
1
Setting prohibited
KR5 input
PFC54
0
1
Setting prohibited
KR4 input
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PFCE53
PFC53
Specification of control mode of P53 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ00/KR3Note input
TOQ00 output
Setting prohibited
PFCE52
PFC52
Specification of control mode of P52 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ03/KR2Note input
TOQ03 output
Setting prohibited
PFCE51
PFC51
Specification of control mode of P51 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ02/KR1Note input
TOQ02 output
Setting prohibited
PFCE50
PFC50
Specification of control mode of P50 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ01/KR0Note input
TOQ01 output
Setting prohibited
Note The KRn pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key
return detection function of the alternate-function KRn pin (by clearing the KRMn bit of the KRM register
to 0). To use this pin as the KRn pin, invalidate the edge detection function of the alternate-function
TIQ0m pin (n = 0 to 3, m = 0 to 3).
Pin Name
KR0/TIQ01
Use as TIQ0m Pin
Use as KRn Pin
KRM0 bit of KRM register = 0
KRM1 bit of KRM register = 0
KRM2 bit of KRM register = 0
KRM3 bit of KRM register = 0
TQ0TIG2, TQ0TIG3 bit of TQ0IOC1 register = 0
TQ0TIG4, TQ0TIG5 bit of TQ0IOC1 register = 0
TQ0TIG6, TQ0TIG7 bit of TQ0IOC1 register = 0
TQ0TIG0, TQ0TIG1 bit of TQ0IOC1 register = 0
TQ0EES0, TQ0EES1 bit of TQ0IOC2 register = 0
TQ0ETS0, TQ0ETS1 bit of TQ0IOC2 register = 0
KR1/TIQ02
KR2/TIQ03
KR3/TIQ00
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(g) Pull-up resistor option register 5 (PU5)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H
7
R/W
6
Address: FFFFFC4AH
5
4
3
2
1
0
PU5
0
0
PU55
PU54
PU53
PU52
PU51
PU50
PU5n
Control of on-chip pull-up resistor connection (n = 0 to 5)
0
1
Not connected
Connected
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4.3.6 Port 6
Port 6 is a 16-bit port (P60 to P615) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
-
16-bit I/O port (P60 to P615)Note
Note In the µPD70F3237, the alternate functions of the P65 to P68 pins (CTXD2, CRXD2, CTXD3, CRXD3) are
not available.
(1) Functions of port 6
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 6 (P6)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 6 (PM6)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 6 (PMC6)
• Control mode 1 or control mode 2 can be specified in 1-bit units.
Specified by port function control register 6 (PFC6)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 6 (PU6)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 6L (INTF6L) and external interrupt rising
edge specification register 6L (INTR6L)
Port 6 functions alternately as the following pins.
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Table 4-18 Alternate-Function Pins of Port 6
Pin Name
P60
Alternate-Function Pin Name
I/O
I/O
Remark
Block Type
N-2
Port 6
INTP11
INTP12
INTP13
–
P61
N-2
P62
N-2
P63
–
–
C-1
P64
C-1
P65
CTXD2
CRXD2
CTXD3
CRXD3
G-3
G-4
G-3
G-4
C-1
P66
P67
P68
P69
–
P610
P611
P612
P613
P614
P615
TIQ20/TOQ20
TIQ21/TOQ21
TIQ22/TOQ22
TIQ23/TOQ23
G-1
G-1
G-1
G-1
C-1
–
–
C-1
Caution:
The P60 to P62, P66, P68, P610 to P613 pins have hysteresis characteristics in the input
mode of the alternate function, but do not have hysteresis characteristics in the port mode.
(P66 and P68 only μPD70F3238, μPD70F3239）
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(2) Registers
(a) Port register 6 (P6)
Port register 6 (P6) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P6 register are used as the P6H register, and the lower 8 bits as the P6L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF40CH, FFFFF40DH
(i) V850ES/FJ2
15
P615
7
14
P614
6
13
P613
5
12
P612
4
11
P611
3
10
P610
2
9
8
P6 (P6HNote
)
P69
1
P68
0
(P6L)
P67
P66
P65
P64
P63
P62
P61
P60
P6n
0
Control of output data (in output mode) (n = 0 to 15)
Output 0.
Output 1.
1
Note To read or write bits 8 to 15 of the P6 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P6H register.
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CHAPTER 4 PORT FUNCTIONS
(b) Port mode register 6 (PM6)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM6 register are used as the PM6H register, and the lower 8 bits as the PM6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFH
R/W
Address: FFFFF42CH, FFFFF42DH
(i) V850ES/FJ2
15
14
PM614
6
13
PM613
5
12
PM612
4
11
PM611
3
10
PM610
2
9
8
PM6 (PM6HNote
)
PM615
7
PM69
1
PM68
0
(PM6L)
PM67
PM66
PM65
PM64
PM63
PM62
PM61
PM60
PM6n
Control of I/O mode (n = 0 to 15)
0
1
Output mode
Input mode
Note To read or write bits 8 to 15 of the PM6 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM6H register.
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(c) Port mode control register 6 (PMC6)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC6 register are used as the PMC6H register, and the lower 8 bits as the
PMC6L register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC6 register when the PFC6n bit of the
PFC6 register is the default value (0), the output becomes undefined (n = 0 to 8).
For this reason, first set the PFC6n bit of the PFC6 register to 1, and then set the PMC6n
bit to 1 to set the control mode.
(1/2)
After reset: 0000H
R/W
Address: FFFFF44CH, FFFFF44DH
(i) V850ES/FJ2 (µ PD70F3237)
15
14
0
13
12
11
10
9
8
PMC6 (PMC6HNote
)
0
7
0
PMC613 PMC612 PMC611 PMC610
0
1
0
0
6
5
0
4
0
3
0
2
(PMC6L)
0
PMC62
PMC61
PMC60
(ii) V850ES/FJ2 (µ PD70F3238,µ PD70F3239)
15
14
13
12
11
10
9
8
PMC6 (PMC6HNote
)
0
7
0
6
PMC613 PMC612 PMC611 PMC610
0
1
PMC68
0
5
4
0
3
0
2
(PMC6L)
PMC67
PMC66
PMC65
PMC62
PMC61
PMC60
PMC613
Specification of operation mode of P613 pin
Specification of operation mode of P612 pin
Specification of operation mode of P611 pin
0
1
I/O port
TIQ23/TOQ23 I/O
PMC612
0
1
I/O port
TIQ22/TOQ22 I/O
PMC611
0
1
I/O port
TIQ21/TOQ21 I/O
Note To read or write bits 8 to 15 of the PMC6 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMC6H register.
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(2/2)
PMC610
Specification of operation mode of P610 pin
0
1
I/O port
TIQ20/TOQ20 I/O
PMC68
Specification of operation mode of P68 pin
Specification of operation mode of P67 pin
Specification of operation mode of P66 pin
Specification of operation mode of P65 pin
Specification of operation mode of P62 pin
Specification of operation mode of P61 pin
Specification of operation mode of P60 pin
0
1
I/O port
CRXD3 input
PMC67
0
1
I/O port
CTXD3 output
PMC66
0
1
I/O port
CRXD2 input
PMC65
0
1
I/O port
CTXD2 output
PMC62
0
1
I/O port
INTP13 input
PMC61
0
1
I/O port
INTP12 input
PMC60
0
1
I/O port
INTP11 input
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(d) Port function control register 6 (PFC6)
This is a 16-bit register that specifies control mode 1 or 2. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC6 register are used as the PFC6H register, and the lower 8 bits as the PFC6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC6 register when the PFC6n bit of the
PFC6 register is the default value (0), the output becomes undefined (n = 0 to 8).
For this reason, first set the PFC6n bit of the PFC6 register to 1, and then set the PMC6n
bit to 1 to set the control mode.
(1/2)
After reset: 0000H
R/W
Address: FFFFF46CH, FFFFF46DH
(i) V850ES/FJ2 (µ PD70F3237)
15
14
0
13
12
11
10
PFC610
2
9
8
PFC6 (PFC6HNote
)
0
7
0
PFC613
PFC612
PFC611
0
1
0
0
6
5
0
4
0
3
0
(PFC6L)
0
PFC62
PFC61
PFC60
(ii) V850ES/FJ2 (µ PD70F3238,µ PD70F3239)
15
14
13
PFC613
5
12
11
10
PFC610
2
9
8
PFC6 (PFC6HNote
)
0
7
0
6
PFC612
PFC611
0
1
PFC68
0
4
0
3
0
(PFC6L)
PFC67
PFC66
PFC65
PFC62
PFC61
PFC60
PFC613
Specification of control mode of P613 pin
Specification of control mode of P612 pin
Specification of control mode of P611 pin
0
1
TIQ23 input
TOQ23 output
PFC612
0
1
TIQ22 input
TOQ22 output
PFC611
0
1
TIQ21 input
TOQ21 output
Note To read or write bits 8 to 15 of the PFC6 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFC6H register.
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(2/2)
PFC610
Specification of control mode of P610 pin
0
1
TIQ20 input
TOQ20 output
PFC68
Specification of control mode of P68 pin
Specification of control mode of P67 pin
Specification of control mode of P66 pin
Specification of control mode of P65 pin
Specification of control mode of P62 pin
Specification of control mode of P61 pin
Specification of control mode of P60 pin
0
1
Setting prohibited
CRXD3 input
PFC67
0
1
Setting prohibited
CTXD3 output
PFC66
0
1
Setting prohibited
CRXD2 input
PFC65
0
1
Setting prohibited
CTXD2 output
PFC62
0
1
Setting prohibited
INTP13 input
PFC61
0
1
Setting prohibited
INTP12 input
PFC60
0
1
Setting prohibited
INTP11 input
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(e) Pull-up resistor option register 6 (PU6)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16-bit units.
If the higher 8 bits of the PU6 register are used as the PU6H register, and the lower 8 bits as the PU6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFFC4CH, FFFFFC4DH
(i) V850ES/FJ2
15
PU615
7
14
PU614
6
13
PU613
5
12
PU612
4
11
PU611
3
10
PU610
2
9
8
PU6 (PU6HNote
)
PU69
1
PU68
0
(PU6L)
PU67
PU66
PU65
PU64
PU63
PU62
PU61
PU60
PU6n
Control of on-chip pull-up resistor connection (n = 0 to 15)
0
1
Not connected
Connected
Note To read/write bits 8 to 15 of the PU6 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU6H register.
(f) External interrupt falling edge specification register 6L (INTF6L)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF6n and
INTR6n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC0CH
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
1
0
INTF6L
0
INTF62
INTF61
INTF60
Remark Refer to Table 4-19 for how to specify a valid edge.
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(g) External interrupt rising edge specification register 6L (INTR6L)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF6n and
INTR6n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC2CH
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
1
0
INTR6L
0
INTR62
INTR61
INTR60
Remark Refer to Table 4-19 for how to specify a valid edge.
Table 4-19 Valid Edge Specification
INTF6n Bit
INTR6n Bit
Valid Edge Specification (n = 0 to 2)
No edge detected
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
Remark n = 0: Control of INTP11 pin
n = 1: Control of INTP12 pin
n = 2: Control of INTP13 pin
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4.3.7 Port 7
Port 7 is a 10-bit, 12-bit or16-bit port (P70 to P715) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
10-bit I/O port (P70 to P79)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
12-bit I/O port (P70 to P711)
16-bit I/O port (P70 to P715)
(1) Functions of port 7
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 7 (P7)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 7L, ７H（P7L, P７H）
Port 7 functions alternately as the following pins.
Table 4-20 Alternate-Function Pins of Port 7
Pin Name
P70
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
A-1
Port 7
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
P71
A-1
P72
A-1
P73
A-1
P74
A-1
P75
A-1
P76
A-1
P77
A-1
P78
A-1
P79
A-1
P710
P711
P712
P713
P714
P715
A-1
A-1
A-1
A-1
A-1
A-1
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(2) Registers
(a) Port register 7H, port register 7L (P7H, P7L)
Port registers 7H and 7L (P7H and P7L) are 8-bit registers that control reading the pin level and writing the
output level. These registers can be read or written in 8-bit or 1-bit units.
They cannot be accessed in 16-bit units.
After reset: Undefined
R/W
Address: FFFFF40FH, FFFFF40EH
(i) V850ES/FE2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
P7H
P7L
P79
1
P78
0
7
6
5
4
3
2
P77
P76
P75
P74
P73
P72
P71
P70
(ii) V850ES/FF2
7
0
6
0
5
0
4
0
3
P711
3
2
P710
2
1
0
P7H
P7L
P79
1
P78
0
7
6
5
4
P77
P76
P75
P74
P73
P72
P71
P70
(iii) V850ES/FG2, V850ES/FJ2
7
6
P714
6
5
P713
5
4
P712
4
3
P711
3
2
P710
2
1
0
P7H
P715
7
P79
1
P78
0
P7L
P77
P76
P75
P74
P73
P72
P71
P70
P7n
0
Control of output data (in output mode) (n = 0 to 15)
Output 0.
Output 1.
1
Caution Do not read the P7H and P7L registers during A/D conversion.
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(b) Port mode registers 7H, 7L (PM7H, PM7L)
These are 8-bit registers that specify an input or output mode. They can be read or written in 8-bit or 1-bit
units.
These registers cannot be accessed in 16-bit units.
After reset: FFH
R/W
Address: FFFFF42FH, FFFFF42EH
(i) V850ES/FE2
7
6
0
5
0
4
0
3
0
2
0
1
0
PM7H
0
7
PM79
1
PM78
0
6
5
4
3
2
PM7L
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
(ii) V850ES/FF2
7
0
6
0
5
0
4
0
3
2
1
0
PM7H
PM7L
PM711
3
PM710
2
PM79
1
PM78
0
7
6
5
4
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
(iii) V850ES/FG2, V850ES/FJ2
7
6
5
4
3
2
PM710
2
1
0
PM7H
PM715
PM714
6
PM713
5
PM712
4
PM711
3
PM79
1
PM78
0
7
PM7L
PM77
PM76
PM75
PM74
PM73
PM72
PM71
PM70
PM7n
Control of I/O mode (n = 0 to 15)
0
1
Output mode
Input mode
Caution To use the alternate function of P7n (ANIn), set PM7n to 1.
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4.3.8 Port 8
Port 8 is a 2-bit port (P80, P81) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
-
2-bit I/O port (P80, P81)Note
Note In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not available.
The alternate function of the P80 pin in the µPD70F3237 is INTP14 only.
(1) Functions of port 8
O The input/output data of the port can be specified in 1-bit units.
Specified by port register 8 (P8)
O The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 8 (PM8)
O Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 8 (PMC8)
O An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 8 (PU8)
O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 8 (INTF8) and external interrupt rising edge
specification register 8 (INTR8)
Port 8 functions alternately as the following pins.
Table 4-21 Alternate-Function Pins of Port 8
Pin Name
P80
Alternate-Function Pin Name
RXDA3/INTP14
I/O
I/O
Remark
–
Block Type
L-1Note
Port 8
P81
TXDA3
C-1Note
Note In the µPD70F3237, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are not available.
Moreover, the port type becomes P80: L-1 and P81: C-1.
Caution: The P80 pins have hysteresis characteristics in the input mode of the alternate function, but do not
have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 8 (P8)
Port register 8 (P8) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF410H
(i) V850ES/FJ2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
P8
P81
P80
P8n
0
Control of output data (in output mode) (n = 0, 1)
Output 0.
Output 1.
1
(b) Port mode register 8 (PM8)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF430H
(i) V850ES/FJ2
7
6
1
5
1
4
1
3
1
2
1
1
0
PM8
1
PM81
PM80
PM8n
Control of I/O mode (n = 0, 1)
0
1
Output mode
Input mode
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(c) Port mode control register 8 (PMC8)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF450H
(i) V850ES/FJ2 (µ PD70F3237)
7
6
0
5
0
4
0
3
0
2
0
1
0
0
PMC8
0
PMC80
(ii) V850ES/FJ2 (µ PD70F3238,µ PD70F3239)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PMC8
PMC81
PMC80
PMC81
Specification of operation mode of P81 pin
0
1
I/O port
TXDA3 output
PMC80
Specification of operation mode of P80 pin
0
1
I/O port
RXDA3/INTP14 inputNote
Note The µPD70F3237 does not have RXDA3.
The INTP14 pin of the µPD70F3238, µPD70F3239 functions alternately as the RXDA3 pin. To
use this pin as the RXDA3 pin, invalidate the edge detection function of the alternate-function
INTP14 pin (by clearing the INTF80 bit of the INTF8 register to 0 and the INTR80 bit of the
INTR8 register to 0). To use this pin as the INTP14 pin, stop the reception operation of UARTA3
(by clearing the UA3RXE bit of the UA3CTL0 register to 0).
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(d) Pull-up resistor option register 8 (PU8)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFFC50H
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
PU8
0
PU81
PU80
PU8n
Control of on-chip pull-up resistor connection (n = 0, 1)
0
1
Not connected
Connected
(e) External interrupt falling edge specification register 8 (INTF8)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF80 and
INTR80 bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address FFFFFC10H
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
0
INTF8
0
INTF80
Remark Refer to Table 4-22 or how to specify a valid edge.
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(f) External interrupt rising edge specification register 8 (INTR8)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF80 and
INTR80 bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address FFFFFC30H
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
0
2
0
1
0
0
INTR8
0
INTR80
Remark Refer to Table 4-22 for how to specify a valid edge.
Table 4-22 Valid Edge Specification
INTF80 Bit
INTR80 Bit
Valid Edge Specification
No edge detected
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
Remark Control of INTP14 pin
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4.3.9 Port 9
Port 9 is a 9-bit or 16-bit port (P90 to P915) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
9-bit I/O port (P90, P91, P96 to P99,
P913 to P915)
16-bit I/O port (P90 to P915)Note
Note In the V850ES/FG2, the alternate functions of the P910 to P912 pins (SIB2, SOB2, SCKB2) are not available.
(1) Functions of port 9
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 9 (P9)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 9 (PM9)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 9 (PMC9)
• Control mode can be specified in 1-bit units.
Specified by port function control register 9 (PFC9) and port function control expansion register 9 (PFCE9)
• An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 9 (PU9)
• The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 9H (INTF9H) and external interrupt rising
edge specification register 9H (INTR9H)
Port 9 functions alternately as the following pins.
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Table 4-23 Alternate-Function Pins of Port 9
Pin Name
P90
Alternate-Function Pin Name
I/O
I/O
Remark
Block Type
U-12
U-7
Port 9
KR6/TXDA1
KR7/RXDA1
TIQ11/TOQ11
TIQ12/TOQ12
TIQ13/TOQ13
TIQ10/TOQ10
TIP21/TOP21
SIB1/TIP20/TOP20
SOB1
–
P91
P92
U-11
U-11
U-11
U-11
U-9
P93
P94
P95
P96
P97
U-8
P98
G-3
P99
SCKB1
G-5
P910
P911
P912
P913
P914
P915
SIB2
G-4
SOB2
G-3
SCKB2
G-5
INTP4/PCL
INTP5
W-1
N-2
INTP6
N-2
Caution The P90 to P97, P910, P912 to P915 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
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CHAPTER 4 PORT FUNCTIONS
(2) Registers
(a) Port register 9 (P9)
Port register 9 (P9) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P9 register are used as the P9H register, and the lower 8 bits as the P9L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF412H, FFFFF413H
(i) V850ES/FE2, V850ES/FF2
15
14
P914
6
13
P913
5
12
0
11
0
10
0
9
8
P9 (P9HNote
)
P915
7
P99
1
P98
0
4
3
2
(P9L)
P97
P96
0
0
0
0
P91
P90
(ii) V850ES/FG2, V850ES/FJ2
15
14
P914
6
13
P913
5
12
P912
4
11
P911
3
10
P910
2
9
8
P9 (P9HNote
)
P915
7
P99
1
P98
0
(P9L)
P97
P96
P95
P94
P93
P92
P91
P90
P9n
0
Control of output data (in output mode) (n = 0 to 15)
Output 0.
Output 1.
1
Note To read or write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P9H register.
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CHAPTER 4 PORT FUNCTIONS
(b) Port mode register 9 (PM9)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM9 register are used as the PM9H register, and the lower 8 bits as the PM9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF432H, FFFFF433H
(i) V850ES/FE2, V850ES/FF2
15
14
PM914
6
13
12
1
11
1
10
1
9
8
PM9 (PM9HNote
)
PM915
7
PM913
PM99
1
PM98
0
5
1
4
3
2
(PM9L)
PM97
PM96
1
1
1
PM91
PM90
(ii) V850ES/FG2, V850ES/FJ2
15
14
PM914
6
13
PM913
5
12
PM912
4
11
PM911
3
10
PM910
2
9
8
PM9 (PM9HNote
)
PM915
7
PM99
1
PM98
0
(PM9L)
PM97
PM96
PM95
PM94
PM93
PM92
PM91
PM90
PM9n
Control of I/O mode (n = 0 to 15)
0
1
Output mode
Input mode
Note To read or write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM9H register.
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CHAPTER 4 PORT FUNCTIONS
(c) Port mode control register 9 (PMC9)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC9 register are used as the PMC9H register, and the lower 8 bits as the
PMC9L register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC9 register when the PFC9n bit of the
PFC9 register and the PFCE9n bit of the PFCE9 register are the default values (0), the
output becomes undefined.
For this reason, first set the PFC9n bit of the PFC9 register and the PFCE9n bit of the
PFCE9 register to 1, and then set the PMC9n bit to 1 to set the control mode.
(1/3)
After reset: 0000H
R/W
Address: FFFFF452H, FFFFF453H
(i) V850ES/FE2, V850ES/FF2
15
14
13
12
0
11
0
10
0
9
8
PMC9 (PMC9HNote
)
PMC915 PMC914 PMC913
PMC99
1
PMC98
0
7
6
5
0
4
3
2
(PMC9L) PMC97
PMC96
0
0
0
PMC91
PMC90
(ii) V850ES/FG2
15
14
13
12
11
10
9
8
PMC9 (PMC9HNote
)
PMC915 PMC914 PMC913
0
4
0
3
0
2
PMC99
1
PMC98
0
7
6
5
(PMC9L) PMC97
PMC96
PMC95
PMC94
PMC93
PMC92
PMC91
PMC90
(iii) V850ES/FJ2
15
14
13
12
11
10
9
8
PMC9 (PMC9HNote
)
PMC915 PMC914 PMC913 PMC912 PMC911 PMC910
PMC99
1
PMC98
0
7
6
5
4
3
2
(PMC9L)
PMC97
PMC96
PMC95
PMC94
PMC93
PMC92
PMC91
PMC90
PMC915
Specification of operation mode of P915 pin
Specification of operation mode of P914 pin
0
1
I/O port
INTP6 input
PMC914
0
1
I/O port
INTP5 input
Note To read or write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMC9H register.
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CHAPTER 4 PORT FUNCTIONS
(2/3)
PMC913
Specification of operation mode of P913 pin
0
1
I/O port
INTP4/PCL I/O
PMC912
Specification of operation mode of P912 pin
Specification of operation mode of P911 pin
Specification of operation mode of P910 pin
Specification of operation mode of P99 pin
Specification of operation mode of P98 pin
Specification of operation mode of P97 pin
0
1
I/O port
SCKB2 I/O
PMC911
0
1
I/O port
SOB2 output
PMC910
0
1
I/O port
SIB2 input
PMC99
0
1
I/O port
SCKB1 I/O
PMC98
0
1
I/O port
SOB1 output
PMC97
0
1
I/O port
SIB1/TIP20/TOP20 I/O
PMC96
Specification of operation mode of P96 pin
0
1
I/O port
TIP21/TOP21 I/O
PMC95
Specification of operation mode of P95 pin
Specification of operation mode of P94 pin
0
1
I/O port
TIQ10/TOQ10 I/O
PMC94
0
1
I/O port
TIQ13/TOQ13 I/O
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CHAPTER 4 PORT FUNCTIONS
(3/3)
PMC93
Specification of operation mode of P93 pin
0
1
I/O port
TIQ12/TOQ12 I/O
PMC92
Specification of operation mode of P92 pin
Specification of operation mode of P91 pin
Specification of operation mode of P90 pin
0
1
I/O port
TIQ11/TOQ11 I/O
PMC91
0
1
I/O port
KR7/RXDA1 input
PMC90
0
1
I/O port
KR6/TXDA1 I/O
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(d) Port function control register 9 (PFC9)
This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF472H, FFFFF473H
(i) V850ES/FE2, V850ES/FF2
15
14
PFC914
6
13
12
0
11
0
10
0
9
8
PFC9 (PFC9HNote
)
PFC915
7
PFC913
PFC99
1
PFC98
0
5
0
4
3
2
(PFC9L)
PFC97
PFC96
0
0
0
PFC91
PFC90
(ii) V850ES/FG2
15
PFC915
7
14
PFC914
6
13
PFC913
5
12
11
10
9
8
PFC9 (PFC9HNote
)
0
4
0
3
0
2
PFC99
1
PFC98
0
(PFC9L)
PFC97
PFC96
PFC95
PFC94
PFC93
PFC92
PFC91
PFC90
(iii) V850ES/FJ2
15
PFC915
7
14
PFC914
6
13
PFC913
5
12
PFC912
4
11
PFC911
3
10
PFC910
2
9
8
PFC9 (PFC9HNote
)
PFC99
1
PFC98
0
(PFC9L)
PFC97
PFC96
PFC95
PFC94
PFC93
PFC92
PFC91
PFC90
Note To read or write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFC9H register.
Remark For how to specify a control mode, refer to 4.3.10 (2) (f) Setting of control mode of P9 pin.
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(e) Port function control expansion register 9 (PFCE9)
This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF712H, FFFFF713H
(i) V850ES/FE2, V850ES/FF2
15
14
13
12
0
11
0
10
0
9
8
PFCE9 (PFCE9HNote
)
0
7
0
6
PFCE913
0
1
0
0
5
0
4
3
2
(PFCE9L) PFCE97
PFCE96
0
0
0
PFCE91
PFCE90
(ii) V850ES/FG2, V850ES/FJ2
15
14
13
PFCE913
5
12
11
10
9
8
PFCE9 (PFCE9HNote
)
0
7
0
6
0
4
0
3
0
2
0
1
0
0
(PFCE9L) PFCE97
PFCE96
PFCE95
PFCE94
PFCE93
PFCE92
PFCE91
PFCE90
Note To read or write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFCE9H register.
Remark For how to specify a control mode, refer to 4.3.10 (2) (f) Setting of control mode of P9 pin.
(f) Setting of control mode of P9 pin
Caution If the control mode is specified by using the PFC9 register when the PFC9n bit of the
PFC9 register and PFCE9n bit of the PFCE9 register are the default values (0), the output
becomes undefined.
For this reason, first set the PFC9n bit of the PFC9 register and the PFCE9n bit of the
PFCE9 register, and then set the PMC9n bit to 1 to set the control mode.
PFC915
Specification of control mode of P915 pin
Specification of control mode of P914 pin
0
1
Setting prohibited
INTP6 input
PFC914
0
1
Setting prohibited
INTP5 input
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CHAPTER 4 PORT FUNCTIONS
PFCE913
PFC913
Specification of control mode of P913 pin
0
0
1
1
0
1
0
1
Setting prohibited
INTP4 input
PCL output
Setting prohibited
PFC912
Specification of control mode of P912 pin
0
1
Setting prohibited
SCKB2 I/O
PFC911
Specification of control mode of P911 pin
Specification of control mode of P910 pin
Specification of control mode of P99 pin
Specification of control mode of P98 pin
Specification of control mode of P97 pin
0
1
Setting prohibited
SOB2 output
PFC910
0
1
Setting prohibited
SIB2 input
PFC99
0
1
Setting prohibited
SCKB1 I/O
PFC98
0
1
Setting prohibited
SOB1 input
PFCE97
PFC97
0
0
0
1
1
Setting prohibited
SIB1 input
1
0
1
TIP20 input
TOP20 output
PFCE96
PFC96
Specification of control mode of P96 pin
0
0
1
1
0
1
0
1
Setting prohibited
Setting prohibited
TIP21 input
TOP21 output
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CHAPTER 4 PORT FUNCTIONS
PFCE95
PFC95
Specification of control mode of P95 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ10 input
TOQ10 output
Setting prohibited
PFCE94
PFC94
Specification of control mode of P94 pin
Specification of control mode of P93 pin
Specification of control mode of P92 pin
Specification of control mode of P91 pin
Specification of control mode of P90 pin
0
0
1
1
0
1
0
1
Setting prohibited
TIQ13 input
TOQ13 output
Setting prohibited
PFCE93
PFC93
0
0
1
1
0
1
0
1
Setting prohibited
TIQ12 input
TOQ12 output
Setting prohibited
PFCE92
PFC92
0
0
1
1
0
1
0
1
Setting prohibited
TIQ11 input
TOQ11 output
Setting prohibited
PFCE91
PFC91
0
0
1
1
0
1
0
1
Setting prohibited
KR7 input
RXDA1 input
Setting prohibited
PFCE90
PFC90
0
0
1
1
0
1
0
1
Setting prohibited
KR6 input
TXDA1 output
Setting prohibited
Note KR7 and RXDA1 pins are using combined.
Invalidate the key return detection of KR7 pins when you use the pins as an RXDA1pin ("0" is set to the
KRM7 bit of the KRM register). Moreover, it is recommended to set it to PFC91 bit = 1, PFCE91 bit =0 when
using it as KR7 pin.
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(g) Pull-up resistor option register 9 (PU9)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16-bit units.
If the higher 8 bits of the PU9 register are used as the PU9H register, and the lower 8 bits as the PU9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFFC52H, FFFFFC53H
(i) V850ES/FE2, V850ES/FF2
15
14
PU914
6
13
12
0
11
0
10
0
9
8
PU9 (PU9HNote
)
PU915
7
PU913
PU99
1
PU98
0
5
0
4
3
2
(PU9L)
PU97
PU96
0
0
0
PU91
PU90
(ii) V850ES/FG2, V850ES/FJ2
15
14
PU914
6
13
PU913
5
12
PU912
4
11
PU911
3
10
PU910
2
9
8
PU9 (PU9HNote
)
PU915
7
PU99
1
PU98
0
(PU9L)
PU97
PU96
PU95
PU94
PU93
PU92
PU91
PU90
PU9n
Control of on-chip pull-up resistor connection (n = 0 to 15)
0
1
Not connected
Connected
Note To read/write bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU9H register.
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(h) External interrupt falling edge specification register 9H (INTF9H)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF9n and
INTR9n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
7
R/W
6
Address: FFFFFC13H
5
4
0
3
0
2
0
1
0
0
0
INTF9H
INTF915 INTF914 INTF913
Remark Refer to Table 4-24 or how to specify a valid edge.
(i) External interrupt rising edge specification register 9H (INTR9H)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF9n and
INTR9n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
7
R/W
6
Address: FFFFFC33H
5
4
0
3
0
2
0
1
0
0
0
INTR9H INTR915 INTR914 INTR913
Remark Refer to Table 4-24 or how to specify a valid edge.
Table 4-24 Valid Edge Specification
INTF9n Bit
INTR9n Bit
Valid Edge Specification (n = 13 to 15)
No edge detected
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both edges
Remark n = 13: Control of INTP4 pin
n = 14: Control of INTP5 pin
n = 15: Control of INTP6 pin
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CHAPTER 4 PORT FUNCTIONS
4.3.10 Port 12
Port 12 is an 8-bit port (P120 to P127) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
-
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
8-bit I/O port (P120 to P127)
(1) Functions of port 12
• The input/output data of the port can be specified in 1-bit units.
Specified by port register 12 (P12)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 12 (PM12)
Port 12 functions alternately as the following pins.
Table 4-25 Alternate-Function Pins of Port 12
Pin Name
Port 12 P120
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
A-1
ANI16
ANI17
ANI18
ANI19
ANI20
ANI21
ANI22
ANI23
P121
P122
P123
P124
P125
P126
P127
A-1
A-1
A-1
A-1
A-1
A-1
A-1
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(2) Registers
(a) Port register 12 (P12)
Port register 12 (P12) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF418H
(i) V850ES/FJ2
7
6
5
4
3
2
1
0
P12
P127
P126
P125
P124
P123
P122
P121
P120
P12n
Control of output data (in output mode) (n = 0 to 7)
0
1
Output 0.
Output 1.
(b) Port mode register 12 (PM12)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF438H
(i) V850ES/FJ2
7
6
5
4
3
2
1
0
PM12
PM127
PM126
PM125
PM124
PM123
PM122
PM121
PM120
PM12n
Control of I/O mode (n = 0 to 7)
0
1
Output mode
Input mode
Caution To use the alternate function of P12n (ANIn), set PM12n to 1.
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4.3.11 Port CD
Port CD is a 4-bit port (PCD0 to PCD3) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
-
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
4-bit I/O port (PCD0 to PCD3)
(1) Functions of port CD
• The input/output data of the port can be specified in 1-bit units.
Specified by port register CD (PCD)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CD (PMCD)
Port CD functions alternately as the following pins.
Table 4-26. Alternate-Function Pins of Port CD
Pin Name
Port CD PCD0
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
B-1
–
–
–
–
PCD1
PCD2
PCD3
B-1
B-1
B-1
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(2) Registers
(a) Port register CD (PCD)
Port register CD (PCD) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF00EH
(i) V850ES/FJ2
7
0
6
0
5
0
4
0
3
2
1
0
PCD
PCD3
PCD2
PCD1
PCD0
PCDn
Control of output data (in output mode) (n = 0 to 3)
0
1
Output 0.
Output 1.
(b) Port mode register CD (PMCD)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF02EH
(i) V850ES/FJ2
7
6
1
5
1
4
1
3
2
1
0
PMCD
1
PMCD3
PMCD2
PMCD1
PMCD0
PMCDn
Control of I/O mode (n = 0 to 3)
0
1
Output mode
Input mode
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CHAPTER 4 PORT FUNCTIONS
4.3.12 Port CM
Port CM is a 2-bit, 4-bit, or 6-bit port (PCM0 to PCM5) for which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
2-bit I/O port (PCM0, PCM1)Note 1
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
4-bit I/O port (PCM0 to PCM3)Note 2
4-bit I/O port (PCD0 to PCD3)
Notes 1. In the V850ES/FE2, the alternate function of the PCM0 pin (WAIT) is not available.
2. In the V850ES/FF2 and V850ES/FG2, the alternate functions of the PCM0, PCM2, and PCM3 pins.
(WAIT, HLDAK, HLDRQ) are not available.
(1) Functions of port CM
• The input/output data of the port can be specified in 1-bit units.
Specified by port register CM (PCM)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CM (PMCM)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CM (PMCCM)
Port CM functions alternately as the following pins.
Table 4-27 Alternate-Function Pins of Port CM
Pin Name
Port CM PCM0
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
D-1
WAIT
CLKOUT
HLDAK
CLDRQ
–
PCM1
PCM2
PCM3
PCM4
PCM5
D-2
D-2
D-1
B-1
–
B-1
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(2) Registers
(a) Port register CM (PCM)
Port register CM (PCM) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF00CH
(i) V850ES/FE2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PCM
PCM1
PCM0
(ii) V850ES/FF2, V850ES/FG2
7
6
0
5
0
4
0
3
2
1
0
PCM
0
PCM3
PCM2
PCM1
PCM0
(iii) V850ES/FJ2
7
0
6
0
5
4
3
2
1
0
PCM
PCM5
PCM4
PCM3
PCM2
PCM1
PCM0
PCMn
Control of output data (in output mode) (n = 0 to 5)
0
1
Output 0.
Output 1.
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(b) Port mode register CM (PMCM)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF02CH
(i) V850ES/FE2
7
6
1
5
1
4
1
3
1
2
1
1
0
PMCM
1
PMCM1
PMCM0
(ii) V850ES/FF2, V850ES/FG2
7
6
1
5
1
4
1
3
2
1
0
PMCM
1
PMCM3
PMCM2
PMCM1
PMCM0
(iii) V850ES/FJ2
7
1
6
1
5
4
3
2
1
0
PMCM
PMCM5
PMCM4
PMCM3
PMCM2
PMCM1
PMCM0
PMCMn
Control of I/O mode (n = 0 to 5)
0
1
Output mode
Input mode
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(c) Port mode control register CM (PMCCM)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF04CH
(i) V850ES/FE2, V850ES/FF2, V850ES/FG2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PMCCM
PMCCM1
(ii) V850ES/FJ2
7
0
6
0
5
0
4
0
3
2
1
0
PMCCM
PMCCM3 PMCCM2 PMCCM1 PMCCM0
PMCCM3
Specification of operation mode of PCM3 pin
Specification of operation mode of PCM2 pin
Specification of operation mode of PCM1 pin
Specification of operation mode of PCM0 pin
0
1
I/O port
HLDRQ input
PMCCM2
0
1
I/O port
HLDAK output
PMCCM1
0
1
I/O port
CLKOUT output
PMCCM0
0
1
I/O port
WAIT input
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4.3.13 Port CS
Port CS is a 2-bit or 8-bit port (PCS0 to PCS7) or which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
-
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
2-bit I/O port (PCS0, PCS1)Note
8-bit I/O port (PCS0 to PCS7)
Note In the V850ES/FF2 and V850ES/FG2, the alternate functions of the PCS0 and PCS1 pins (CS0, CS1) are not
available.
(1) Functions of port CS
• The input/output data of the port can be specified in 1-bit units.
Specified by port register CS (PCS)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CS (PMCS)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CS (PMCCS)
Port CS functions alternately as the following pins.
Table 4-28 Alternate-Function Pins of Port CS
Pin Name
Port CS PCS0
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
D-2
CS0
CS1
CS2
CS3
–
PCS1
PCS2
PCS3
PCS4
PCS5
PCS6
PCS7
D-2
D-2
D-2
B-1
–
B-1
–
B-1
–
B-1
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(2) Registers
(a) Port register CS (PCS)
Port register CS (PCS) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF008H
(i) V850ES/FF2, V850ES/FG2
7
6
0
5
0
4
0
3
0
2
0
1
0
PCS
0
PCS1
PCS0
(ii) V850ES/FJ2
7
6
5
4
3
2
1
0
PCS
PCS7
PCS6
PCS5
PCS4
PCS3
PCS2
PCS1
PCS0
PCSn
Control of output data (in output mode) (n = 0 to 7)
0
1
Output 0.
Output 1.
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(b) Port mode register CS (PMCS)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF028H
(i) V850ES/FF2, V850ES/FG2
7
6
1
5
1
4
1
3
1
2
1
1
0
PMCS
1
PMCS1
PMCS0
(ii) V850ES/FJ2
7
6
5
4
3
2
1
0
PMCS
PMCS7
PMCS6
PMCS5
PMCS4
PMCS3
PMCS2
PMCS1
PMCS0
PMCSn
Control of I/O mode (n = 0 to 7)
0
1
Output mode
Input mode
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(c) Port mode control register CS (PMCCS)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF048H
(i) V850ES/FJ2
7
6
0
5
0
4
0
3
2
1
0
PMCCS
0
PMCCS3 PMCCS2 PMCCS1 PMCCS0
PMCCS3
Specification of operation mode of PCS3 pin
Specification of operation mode of PCS2 pin
Specification of operation mode of PCS1 pin
Specification of operation mode of PCS0 pin
0
1
I/O port
CS3 output
PMCCS2
0
1
I/O port
CS2 output
PMCCS1
0
1
I/O port
CS1 output
PMCCS0
0
1
I/O port
CS0 output
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4.3.14 Port CT
Port CT is a 4-bit or 8-bit port (PCT0 to PCT7) or which I/O settings can be controlled in 1-bit units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
-
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
4-bit I/O port (PCT0, PCT1, PCT4,
PCT6)Note
8-bit I/O port (PCT0 to PCT7)
Note In the V850ES/FF2 and V850ES/FG2, the alternate functions of the PCT0, PCT1, PCT4, and PCT6 pins
(WR0, WR1, RD, ASTB) are not available.
(1) Functions of port CT
• The input/output data of the port can be specified in 1-bit units.
Specified by port register CT (PCT)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CT (PMCT)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CT (PMCCT)
Port CT functions alternately as the following pins.
Table 4-29 Alternate-Function Pins of Port CT
Pin Name
Port CT PCT0
Alternate-Function Pin Name
I/O
I/O
Remark
–
Block Type
D-2
WR0
WR1
–
PCT1
PCT2
PCT3
PCT4
PCT5
PCT6
PCT7
D-2
B-1
–
B-1
RD
D-2
–
B-1
ASTB
D-2
–
B-1
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(2) Registers
(a) Port register CT (PCT)
Port register CT (PCT) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF00AH
(i) V850ES/FF2, V850ES/FG2
7
6
5
0
4
3
0
2
0
1
0
PCT
0
PCT6
PCT4
PCT1
PCT0
(ii) V850ES/FJ2
7
6
5
4
3
2
1
0
PCT
PCT7
PCT6
PCT5
PCT4
PCT3
PCT2
PCT1
PCT0
PCTn
Control of output data (in output mode) (n = 0 to 7)
0
1
Output 0.
Output 1.
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(b) Port mode register CT (PMCT)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After reset: FFH
R/W
Address: FFFFF02AH
(i) V850ES/FF2, V850ES/FG2
7
6
5
1
4
3
1
2
1
1
0
PMCT
1
PMCT6
PMCT4
PMCT1
PMCT0
(ii) V850ES/FJ2
7
6
5
4
3
2
1
0
PMCT
PMCT7
PMCT6
PMCT5
PMCT4
PMCT3
PMCT2
PMCT1
PMCT0
PMCTn
Control of I/O mode (n = 0 to 7)
0
1
Output mode
Input mode
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(c) Port mode control register CT (PMCCT)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF04AH
(i) V850ES/FJ2
7
6
5
0
4
3
0
2
0
1
0
PMCCT
0
PMCCT6
PMCCT4
PMCCT1 PMCCT0
PMCCT6
Specification of operation mode of PCT3 pin
Specification of operation mode of PCT2 pin
Specification of operation mode of PCT1 pin
Specification of operation mode of PCT0 pin
0
1
I/O port
ASTB output
PMCCT4
0
1
I/O port
RD output
PMCCT1
0
1
I/O port
WR1 output
PMCCT0
0
1
I/O port
WR0 output
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4.3.15 Port DL
Port DL is an 8-bit, 12-bit, 14-bit, or 16-bit port (PDL0 to PDL15) or which I/O settings can be controlled in 1-bit
units.
The number of I/O port pins differs depending on the product.
Product
Number of I/O Port Pins
8-bit I/O port (PDL0 to PDL7)Note
12-bit I/O port (PDL0 to PDL11)Note
14-bit I/O port (PDL0 to PDL13)Note
16-bit I/O port (PDL0 to PDL15)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
Note In the V850ES/FE2, V850ES/FF2, and V850ES/FG2, the alternate function of the PDLn pin (ADn) is not
available. The alternate function of the PDL5 pin in the V850ES/FE2, V850ES/FF2, and V850ES/FG2 is
FLMD1 only.
(1) Function of port DL
• The input/output data of the port can be specified in 1-bit units.
Specified by port register DL (PDL)
• The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register DL (PMDL)
• Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register DL (PMCDL)
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Port DL functions alternately as the following pins.
Table 4-30 Alternate-Function Pins of Port DL
Pin Name
PDL0
Alternate-Function Pin Name
I/O
I/O
Remark
Block Type
D-3
AD0
Port DL
–
PDL1
PDL2
PDL3
PDL4
PDL5
PDL6
PDL7
PDL8
PDL9
PDL10
PDL11
PDL12
PDL13
PDL14
PDL15
AD1
D-3
AD2
D-3
AD3
D-3
AD4
D-3
AD5/FLMD1Note
D-3
AD6
D-3
AD7
D-3
AD8
D-3
AD9
D-3
AD10
AD11
AD12
AD13
AD14
AD15
D-3
D-3
D-3
D-3
D-3
D-3
Note Because the FLMD1 pin is used in the flash programming mode, it does not have to be manipulated
by using a port control register. For details, refer to CHAPTER 25 FLASH MEMORY.
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(2) Registers
(a) Port register DL (PDL)
Port register DL (PDL) is a 16-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 16-bit units.
If the higher 8 bits of the PDL register are used as the PDLH register, and the lower 8 bits as the PDLL
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF004H, FFFFF005H
(i) V850ES/FE2
7
6
5
4
3
2
1
0
PDL
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
(ii) V850ES/FF2
15
0
14
0
13
0
12
0
11
PDL11
3
10
PDL10
2
9
8
PDL (PDLHNote
)
PDL9
1
PDL8
0
7
6
5
4
(PDLL)
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
(iii) V850ES/FG2
15
0
14
0
13
PDL13
5
12
PDL12
4
11
PDL11
3
10
PDL10
2
9
8
PDL (PDLHNote
)
PDL9
1
PDL8
0
7
6
(PDLL)
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
(iv) V850ES/FJ2
15
PDL15
7
14
PDL14
6
13
PDL13
5
12
PDL12
4
11
PDL11
3
10
PDL10
2
9
8
PDL (PDLHNote
)
PDL9
1
PDL8
0
(PDLL)
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
PDLn
Control of output data (in output mode) (n = 0 to 15)
0
1
Output 0.
Output 1.
Note To read or write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PDLH register.
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(b) Port mode register DL (PMDL)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PMDL register are used as the PMDLH register, and the lower 8 bits as the
PMDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF024H, FFFFF025H
(i) V850ES/FE2
7
6
5
4
3
2
1
0
PMDL PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
(ii) V850ES/FF2
15
14
13
12
11
10
9
8
PMDL (PMDLHNote
)
1
7
1
6
1
5
1
4
PMDL11 PMDL10
PMDL9
1
PMDL8
0
3
2
(PMDLL) PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
(iii) V850ES/FG2
15
1
14
13
12
11
10
9
8
PMDL (PMDLHNote
)
1
6
PMDL13 PMDL12 PMDL11 PMDL10
PMDL9
1
PMDL8
0
7
5
4
3
2
(PMDLL) PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
(iv) V850ES/FJ2
15
14
13
12
11
10
9
8
PMDL (PMDLHNote
)
PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10
PMDL9
1
PMDL8
0
7
6
5
4
3
2
(PMDLL)
PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
PMDLn
Control of I/O mode (n = 0 to 15)
0
1
Output mode
Input mode
Note To read or write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMDLH register.
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(c) Port mode control register DL (PMCDL)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMCDL register are used as the PMCDLH register, and the lower 8 bits as the
PMCDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF044H, FFFFF045H
(i) V850ES/FJ2
15
14
13
12
11
10
9
8
PMCDL (PMCDLHNote
) PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8
7
6
5
4
3
2
1
0
(PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0
PMCDLn
Specification of operation mode of PDL15 pin (n = 0 to 15)
0
1
I/O port
ADn I/O (address/data bus I/O)
Note To read or write bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify these bits as
bits 0 to 7 of the PMCDLH register.
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4.3.16 Port pins that function alternately as on-chip debug function
The pins shown in Table 4-31 function alternately as on-chip debug pins. After an external reset, these pins are
initialized as on-chip debug pins (DRST, DDI, DDO, DCK, and DMS).
Table 4-31 On-Chip Debug Pins
Pin Name
P05
Alternate Function Pin
INTP2/DRST
P52
KR2/TIQ03/TOQ03/DDI
KR3/TIQ00/TOQ00/DDO
KR4/DCK
P53
P54
P55
KR5/DMS
To use these pins as port pins, not as on-chip debug pins, the following actions must be taken after an external
reset.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the above actions are
taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05 pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not necessary to
manipulate the OCDM0 bit of the OCDM register.
Because a pull-down resistor (30 kΩ TYP) is connected to the buffer of the P05/INTP2/DRST pin, the pin does not
have to be fixed to the low level by an external source. The pull-down resistor is disconnected by clearing the OCDM0
bit to 0.
For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
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4.3.17 Register settings to use port pins as alternate-function pins
Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (1/7)
Pin
Alternate-Function Pin
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
Name
TIP31
I/O
P00
Input
Setting not required PMC00 = 1
PFC00 = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
TOP31
TIP30
TOP30
NMI
Output Setting not required PMC00 = 1
Setting not required PMC01 = 1
Output Setting not required PMC01 = 1
PFC00 = 1
P01
Input
PFC01 = 0
PFC01 = 1
P02
P03
Input
Input
Setting not required PMC02 = 1
Setting not required PMC03 = 1
–
INTP0
ADTRG
INTP1
INTP2
DRST
INTP3
INTP9
INTP10
PFC03 = 0
INTx03 (INTx0)
Output Setting not required PMC03 = 1
PFC03 = 1
P04
Input
Input
Input
Input
Input
Input
Setting not required PMC04 = 1
Setting not required PMC05 = 1
–
–
–
–
–
–
INTx04 (INTx0)
INTx05 (INTx0)
OCDM0 (OCDM) = 1
INTx06 (INTx0)
INTx10 (INTx1)
INTx11 (INTx1)
P05Note
Setting not required
Setting not required
P06
P10
P11
Setting not required PMC06 = 1
Setting not required PMC10 = 1
Setting not required PMC11 = 1
Note After an external reset, the P05/INTP2/DRST pin is initialized as an on-chip debug pin (DRST). To not use the
P05/INTP2/DRST pin as an on-chip debug pin, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-
CHIP DEBUG UNIT).
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (2/7)
Pin
Alternate-Function Pin
Name I/O
TXDA0
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
P30
Output Setting not required PMC30 = 1
–
–
P31
RXDA0
INTP7
ASCKA0
TOP01
TIP00
Input
Input
Input
Setting not required PMC31 = 1
Setting not required PMC31 = 1
Setting not required PMC32 = 1
–
–
Note 1
–
PFC32 = 0
PFC32 = 1
PFC32 = 0
PFC32 = 1
PFC33 = 0
PFC33 = 1
PFC33 = 0
PFC34 = 0
PFC34 = 1
PFC34 = 0
PFC35 = 0
PFC35 = 1
–
–
Note 1, INTx31 (INTx3)
P32
PFCE32 = 0
Output Setting not required PMC32 = 1
Setting not required PMC32 = 1
Output Setting not required PMC32 = 1
Setting not required PMC33 = 1
PFCE32 = 0
Input
PFCE32 = 1
TOP00
TIP01
PFCE32 = 1
P33
P34
P35
Input
PFCE33 = 0
TOP01
CTXD0
TIP10
Output Setting not required PMC33 = 1
Output Setting not required PMC33 = 1
PFCE33 = 0
PFCE33 = 1
Input
Setting not required PMC34 = 1
PFCE34 = 0
TOP10
CRXD0
TIP11
Output Setting not required PMC34 = 1
PFCE34 = 0
Input
Input
Setting not required PMC34 = 1
Setting not required PMC35 = 1
PFCE34 = 1
–
–
–
–
–
–
–
–
–
–
TOP11
CTXD1
CRXD1
TXDA2
RXDA2
INTP8
SIB0
Output Setting not required PMC35 = 1
Output Setting not required PMC36 = 1
P36
P37
P38
P39
Input
Setting not required PMC37 = 1
–
Output Setting not required PMC38 = 1
–
Input
Input
Input
Setting not required PMC39 = 1
Setting not required PMC39 = 1
Setting not required PMC40 = 1
–
Note 2
–
Note 2, INTx39 (INTx3)
P40
P41
P42
–
SOB0
Output Setting not required PMC41 = 1
Setting not required PMC42 = 1
–
SCKB0
I/O
–
Notes 1. The INTP7 pin functions alternately as the RXDA0 pin. To use this pin as the RXDA0 pin, invalidate the
edge detection function of the alternate-function INTP7 pin (by clearing the INTF31 bit of the INTF3 register
to 0 and the INTR31 bit of the INTR3 register to 0). To use this pin as the INTP7 pin, stop the reception
operation of UARTA0 (by clearing the UA0RXE bit of the UA0CTL0 register to 0).
2. The INTP8 pin functions alternately as the RXDA2 pin. To use this pin as the RXDA2 pin, invalidate the
edge detection function of the alternate-function INTP8 pin (by clearing the INTF39 bit of the INTF3 register
to 0 and the INTR39 bit of the INTR3 register to 0). To use this pin as the INTP8 pin, stop the reception
operation of UARTA2 (by clearing the UA2RXE bit of the UA2CTL0 register to 0).
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (3/7)
Pin
Alternate-Function Pin
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
Name
KR0
I/O
Input
Input
P50
Setting not required PMC50 = 1
Setting not required PMC50 = 1
PFC50 = 1
PFC50 = 1
PFC50 = 0
PFC51 = 1
PFC51 = 1
PFC51 = 0
PFC52 = 1
PFC52 = 1
PFC52 = 0
Setting not required
PFC53 = 1
PFC53 = 1
PFC53 = 0
Setting not required
PFC54 = 1
Setting not required
PFC55 = 1
Setting not required
PFCE50 = 0
PFCE50 = 0
PFCE50 = 1
PFCE54 = 0
PFCE51 = 0
PFCE51 = 1
PFCE52 = 0
PFCE52 = 0
PFCE52 = 1
Note 1
Note 1
TIQ01
TOQ01
KR1
Output Setting not required PMC50 = 1
P51
P52
Input
Input
Setting not required PMC51 = 1
Setting not required PMC51 = 1
Note 1
Note 1
TIQ02
TOQ02
KR2
Output Setting not required PMC51 = 1
Input
Input
Setting not required PMC52 = 1
Setting not required PMC52 = 1
Note 1
Note 1
TIQ03
TOQ03
DDINote 2
KR3
Output Setting not required PMC52 = 1
Input
Input
Input
Setting not required
Setting not required
Setting not required OCDM0 (OCDM) = 1
P53
Setting not required PMC53 = 1
Setting not required PMC53 = 1
PFCE53 = 0
PFCE53 = 0
PFCE53 = 1
Note 1
Note 1
TIQ00
TOQ00
DDONote 2
KR4
Output Setting not required PMC53 = 1
Output Setting not required Setting not required
Setting not required PMC54 = 1
Output Setting not required Setting not required
Setting not required PMC55 = 1
Output Setting not required Setting not required
Setting not required OCDM0 (OCDM) = 1
–
P54
P55
Input
2
DCKNote
–
–
–
OCDM0 (OCDM) = 1
KR5
Input
DMSNote 2
OCDM0 (OCDM) = 1
Notes 1. The KRn pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key
return detection function of the alternate-function KRn pin (by clearing the KRMn bit of the KRM register to
0). To use this pin as the KRn pin, invalidate the edge detection function of the alternate-function TIQ0m
pin (n = 0 to 3, m = 0 to 3).
Pin Name
KR0/TIQ01
KR1/TIQ02
KR2/TIQ03
KR3/TIQ00
When Used as TIQ0m Pin
KRM0 bit of KRM register = 0
KRM1 bit of KRM register = 0
KRM2 bit of KRM register = 0
KRM3 bit of KRM register = 0
When Used as KRn Pin
TQ0TIG2, TQ0TIG3 bits of TQ0IOC1 register = 0
TQ0TIG4, TQ0TIG5 bits of TQ0IOC1 register = 0
TQ0TIG6, TQ0TIG7 bits of TQ0IOC1 register = 0
TQ0TIG0, TQ0TIG1 bits of TQ0IOC1 register = 0
TQ0EES0, TQ0EES1 bits of TQ0IOC2 register = 0
TQ0ETS0, TQ0ETS1 bits of TQ0IOC2 register = 0
2. The DDI, DDO, DCK, and DMS pins are on-chip debug pins. To not use these pins as on-chip debug pins
after an external reset, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION (ON-CHIP DEBUG UNIT).
Caution If the control mode is specified by using the PMC5 register when the PFC5n bit of the PFC5 register
and the PFCE5n bit of the PFCE5 register are the default values (0), the output becomes undefined.
For this reason, first set the PFC5n bit of the PFC5 register and the PFCE5n bit of the PFCE5
register, and then set the PMC5n bit to 1 to set the control mode.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (4/7)
Pin
Alternate-Function Pin
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
Name
INTP11
INTP12
INTP13
CTXD2
CRXD2
CTXD3
CRXD3
TIQ20
TOQ20
TIQ21
TOQ21
TIQ22
TOQ22
TIQ23
TOQ23
ANI0
I/O
Input
Input
Input
P60
Setting not required PMC60 = 1
Setting not required PMC61 = 1
Setting not required PMC62 = 1
PFC60 = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––
–
–
–
–
–
–
–
INTx60 (INTx6L)
INTx61 (INTx6L)
INTx62 (INTx6L)
P61
P62
P65
P66
P67
P68
P610
PFC61 = 1
PFC62 = 1
Output Setting not required PMC65 = 1
Setting not required PMC66 = 1
Output Setting not required PMC67 = 1
PFC65 = 1
Input
PFC66 = 1
PFC67 = 1
Input
Input
Setting not required PMC68 = 1
Setting not required PMC610 = 1
PFC68 = 1
PFC610 = 0
Output Setting not required PMC610 = 1
Setting not required PMC611 = 1
Output Setting not required PMC611 = 1
Setting not required PMC612 = 1
Output Setting not required PMC612 = 1
Setting not required PMC613 = 1
Output Setting not required PMC613 = 1
PFC610 = 1
P611
P612
P613
Input
PFC611 = 0
PFC611 = 1
Input
PFC612 = 0
PFC612 = 1
Input
PFC613 = 0
PFC613 = 1
P70
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PM70 = 1Note
PM71 = 1Note
PM72 = 1Note
PM73 = 1Note
PM74 = 1Note
PM75 = 1Note
PM76 = 1Note
PM77 = 1Note
PM78 = 1Note
PM79 = 1Note
PM710 = 1Note
PM711 = 1Note
PM712 = 1Note
PM713 = 1Note
PM714 = 1Note
PM715 = 1Note
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P71
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
ANI7
P78
ANI8
P79
ANI9
P710
P711
P712
P713
P714
P715
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
Note Set PM7n to 1 to use the alternate function of P7n (ANIn).
Caution If the control mode is specified by using the PMC6 register when the PFC6n bit (n = 0 to 8) of the
PFC6 register is the default value (0), the output becomes undefined.
For this reason, first set the PFC6n bit of the PFC6 register and then set the PMC6n bit to 1 to set
the control mode.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-32 Register Settings to Use Port Pin as Alternate-Function Pins (5/7)
Pin
Alternate-Function Pin
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
Name
I/O
P80
RXDA3
INTP14
TXDA3
KR6
Input
Input
Setting not required PMC80 = 1
Setting not required PMC80 = 1
–
–
–
Note 2
–
Note, INTx80 (INTx8)
P81
P90
Output Setting not required PMC81 = 1
Setting not required PMC90 = 1
Output Setting not required PMC90 = 1
–
–
Input
PFC90 = 1
PFC90 = 0
PFC91 = 1
PFC91 = 0
PFC91 = 0
PFC92 = 1
PFC92 = 0
PFC93 = 1
PFC93 = 0
PFC94 = 1
PFC94 = 0
PFC95 = 1
PFC95 = 0
PFC96 = 0
PFC96 = 1
PFC97 = 1
PFC97 = 0
PFC97 = 1
PFC98 = 1
PFC99 = 1
PFC910 = 1
PFC911 = 1
PFC912 = 1
PFC913 = 1
PFC913 = 0
PFC914 = 1
PFC915 = 1
PFCE90 = 0
PFCE90 = 1
PFCE91 = 0
PFCE91 = 1
PFCE91 = 1
PFCE92 = 0
PFCE92 = 1
PFCE93 = 0
PFCE93 = 1
PFCE94 = 0
PFCE94 = 1
PFCE95 = 0
PFCE95 = 1
PFCE96 = 1
PFCE96 = 1
PFCE97 = 0
PFCE97 = 1
PFCE97 = 1
–
TXDA1
KR7 Note 1
P91
Input
Setting not required PMC91 = 1
RXDA1
TIQ11
TOQ11
TIQ12
TOQ12
TIQ13
TOQ13
TIQ10
TOQ10
TIP21
TOP21
SIB1
Input
Input
Setting not required PMC91 = 1
Setting not required PMC92 = 1
P92
P93
P94
P95
P96
P97
Output Setting not required PMC92 = 1
Setting not required PMC93 = 1
Output Setting not required PMC93 = 1
Setting not required PMC94 = 1
Output Setting not required PMC94 = 1
Setting not required PMC95 = 1
Output Setting not required PMC95 = 1
Setting not required PMC96 = 1
Output Setting not required PMC96 = 1
Input
Input
Input
Input
Input
Input
Setting not required PMC97 = 1
Setting not required PMC97 = 1
TIP20
TOP20
SOB1
SCKB1
SIB2
Output Setting not required PMC97 = 1
Output Setting not required PMC98 = 1
P98
P99
I/O
Setting not required PMC99 = 1
Setting not required PMC910 = 1
–
P910
P911
P912
P913
Input
–
SOB2
SCKB2
INTP4
PCL
Output Setting not required PMC911 = 1
–
I/O
Setting not required PMC912 = 1
Setting not required PMC913 = 1
–
Input
PFCE913 = 0
PFCE913 = 1
–
INTx913 (INTx9H)
Output Setting not required PMC913 = 1
P914
P915
INTP5
INTP6
Input
Input
Setting not required PMC914 = 1
Setting not required PMC915 = 1
INTx914 (INTx9H)
INTx915 (INTx9H)
–
Note 1. The KR7 pin and the RXDA1 pin are using combined. Invalidate the key return detection of the KR7 pin
when you use the terminal as the RXDA1 pin ("0" is set to the KRM7 bit of the KRM register.). Moreover, it is
recommended to set it to PFC91 bit = 1, PFCE91 bit =0 when using it as the KR7 pin.
2 The INTP14 pin functions alternately as the RXDA3 pin. To use this pin as the RXDA3 pin, invalidate the
edge detection function of the alternate-function INTP14 pin (by clearing the INTF80 bit of the INTF8 register to
0 and the INTR80 bit of the INTR8 register to 0). To use this pin as the INTP14 pin, stop the reception
operation of UARTA3 (by clearing the UA3RXE bit of the UA3CTL0 register to 0).
Caution If the control mode is specified by using the PMC9 register when the PFC9n bit of the PFC9 register
and the PFCE9n bit of the PFCE9 register are the default values (0), the output becomes undefined.
For this reason, first set the PFC9n bit of the PFC9 register and the PFCE9n bit of the PFCE9
register, and then set the PMC9n bit to 1 to set the control mode.
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Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (6/7)
Pin
Alternate-Function Pin
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
Name
ANI16
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
P120
PM120 = 1Note
PM121 = 1Note
PM122 = 1Note
PM123 = 1Note
PM124 = 1Note
PM125 = 1Note
PM126 = 1Note
PM127 = 1Note
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P121
P122
P123
P124
P125
P126
P127
PCM0
PCM1
PCM2
PCM3
PCS0
PCS1
PCS2
PCS3
PCT0
PCT1
PCT4
PCT6
ANI17
ANI18
ANI19
ANI20
ANI21
ANI22
ANI23
WAIT
CLKOUT
HLDAK
HLDRQ
CS0
Setting not required PMCCM0 = 1
Output Setting not required PMCCM1 = 1
Output Setting not required PMCCM2 = 1
Input
Setting not required PMCCM3 = 1
Output Setting not required PMCCS0 = 1
Output Setting not required PMCCS1 = 1
Output Setting not required PMCCS2 = 1
Output Setting not required PMCCS3 = 1
Output Setting not required PMCCT0 = 1
Output Setting not required PMCCT1 = 1
Output Setting not required PMCCT4 = 1
Output Setting not required PMCCT6 = 1
CS1
CS2
CS3
WR0
WR1
RD
ASTB
Note Set PM12n to 1 to use the alternate function of P12n (ANIn).
Remark The port register (Pn) does not have to be set when the alternate function is used.
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Table 4-32 Register Settings to Use Port Pins as Alternate-Function Pins (7/7)
Pin
Alternate-Function Pin
Name I/O
AD0 I/O
PMn Register PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
Name
PDL0
Setting not required PMCDL0 = 1
Setting not required PMCDL1 = 1
Setting not required PMCDL2 = 1
Setting not required PMCDL3 = 1
Setting not required PMCDL4 = 1
Setting not required PMCDL5 = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PDL1
PDL2
PDL3
PDL4
PDL5
AD1
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD2
AD3
AD4
AD5
FLMD1
AD6
Setting not required
Setting not required
Note
PDL6
Setting not required PMCDL6 = 1
Setting not required PMCDL7 = 1
Setting not required PMCDL8 = 1
Setting not required PMCDL9 = 1
Setting not required PMCDL10 = 1
Setting not required PMCDL11 = 1
Setting not required PMCDL12 = 1
Setting not required PMCDL13 = 1
Setting not required PMCDL14 = 1
Setting not required PMCDL15 = 1
PDL7
AD7
PDL8
AD8
PDL9
AD9
PDL10
PDL11
PDL12
PDL13
PDL14
PDL15
AD10
AD11
AD12
AD13
AD14
AD15
Note The FLMD1 pin does not have to be manipulated by using a port control register because it is used in the flash
programming mode. For details, refer to CHAPTER 25 FLASH MEMORY.
Remark The port register (Pn) does not have to be set when the alternate function is used.
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4.3.18 Operation of Port Function
The operation of a port differs depending on setting of the input or output mode, as follows.
(1)
Writing to I/O port
(a) In output mode
A value can be written to the output latch by using a transfer instruction. The contents of the output latch are
output from the pin. Once data has been written to the output latch, it is retained until new data is written to the
output latch.
(b) In input mode
A value can be written to the output latch by using a transfer instruction. Because the output buffer is off,
however, the status of the pin remains unchanged.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-
bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not subject to
manipulation.
(2)
Reading from I/O port
(a) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output latch
are not changed.
(b) In input mode
The status of the pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
(3)
Operation of I/O port
(a) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch. The
contents of the output latch are output from the pin.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
(b) In input mode
The contents of the output latch become undefined. Because the output buffer is off, however, the status of the
pin remains unchanged.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-
bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not subject to
manipulation.
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4.4 Cautions
4.4.1 Cautions on setting port pins
(1) The general-purpose port function and several peripheral function I/O pin share a pin. To switch between the
general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the
PMCn register. In regards to this register setting sequence, note with caution the following.
(a) Cautions on switching from port mode to alternate-function mode
To switch from the port mode to alternate-function mode in the following order.
<1> Set the PFn registerNote: N-ch open-drain setting
<2> Set the PFCn and PFCEn registers: Alternate-function selection
<3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode
If the PMCn register is set first, note with caution that, at that moment or depending on the change of the pin
states in accordance with the setting of the PFn, PFCn, and PFCEn registers, unexpected operations may
occur.
Note No-ch open-drain output pin only
Caution Regardless of the port mode/alternate-function mode, the Pn register is read and written as
follows.
•
Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read
the pin states (PMn.PMnm bit = 1).
•
. Pn register write:Write to the port output latch
(b) Cautions on alternate-function mode (input)
The input signal to the alternate-function block is low level when the PMCn.PMCnm bit is 0 due to the AND
output of the PMCn register set value and the pin level. Thus, depending on the port setting and alternate
function operation enable timing, unexpected operations may occur. Therefore, switch between the port
mode and alternate-function mode in the following sequence.
•
•
To switch from port mode to alternate-function mode (input)
Set the pins to the alternate-function mode using the PMCn register and then enable the alternate
function operation.
To switch from alternate-function mode (input) to port mode
Stop the alternate-function operation and then switch the pins to the port mode.
(2) In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit = 0). In the input mode (PMnm
bit = 1), the value of the PFnm bit is not reflected in the buffer.
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4.4.2 Cautions on bit manipulation instruction for port n register (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value
of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
4.4.3 Cautions on on-chip debug pins
The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins (these pins are available only in the flash
memory versions).
After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If
a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO
pins can be used.
The following action must be taken if on-chip debugging is not used.
•
Clear the OCDM0 bit of the OCDM register (special register) (0)
At this time, fix the P05/INTP2/DRST pin to low level from when reset by the RESET pin is released until the above
action is taken.
If a high level is input to the DRST pin before the above action is taken, it may cause a malfunction (CPU deadlock).
Handle the P05 pin with the utmost care.
Caution After reset by the WDT2RES signal, clock monitor (CLM), or low-voltage detector (LVI), the
P05/INTP2/DRST pin is not initialized to function as an on-chip debug pin (DRST). The OCDM
register holds the current value.
4.4.4 Cautions on P05/INTP2/DRST pin
The P05/INTP2/DRST pin has an internal pull-down resistor (30 K TYP.). After a reset by the RESET pin, a pull-down
resistor is connected. The pull-down resistor is disconnected when the OCDM0 bit is cleared (0).
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The V850ES/FJ2 is provided with an external bus interface function by which memories such as ROM and RAM, or
I/O, can be externally connected. V850ES/FE2, V850ES/FF2, V850ES/FG2 do not embed this interface.
5.1 Features
Output from a multiplexed bus with a minimum of 3 bus cycles
8-bit/16-bit data bus selectable
Wait function
• Programmable wait function of up to 7 states per memory block
• External wait function using WAIT pin
Idle state insertion function
Bus hold function
External devices can be connected using alternate-function port pins
Fixed to little-endian format
Misaligned access possible
Chip select function (4 spaces)
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5.2 Bus Control Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. Bus Control Pins (Multiplexed Bus)
Bus Control Pin
AD0 to AD15
Alternate-Function Pin
PDL0 to PDL15
PCM0
I/O
Function
I/O
Address/data bus
External wait control
Internal system clock
Chip select signal
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
WAIT
Input
CLKOUT
CS0 to CS3
WR0, WR1
RD
PCM1
Output
Output
Output
Output
Output
Input
PCS0 to PCS3
PCT0, PCT1
PCT4
ASTB
PCT6
HLDRQ
HLDAK
PCM3
PCM2
Output
5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
The following list shows pin statuses when internal ROM, internal RAM, or on-chip peripheral I/O is accessed.
Access Destination
Internal ROM
Address Bus
Undefined
Data Bus
Control Signal
Hi-Z
Hi-Z
Hi-Z
Inactive
Inactive
Inactive
Internal RAM
Undefined
On-chip peripheral I/O
Note
Note When an on-chip peripheral I/O is accessed, the address of the on-chip peripheral I/O being accessed is
output via the address bus.
5.2.2 Pin status in each operation mode
For the pin status of the V850ES/FJ2 in each operation mode, see 2.2 Pin Status.
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5.3 Memory Block Function
5.3.1 Memory space
The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The
programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in
one-block units.
Figure 5-1. Data Memory Map
3FFFFFFH
3FFFFFFH
On-chip peripheral I/O area
(4 KB)
(80 KB)
3FFF000H
3FFEFFFH
3FEC000H
3FEBFFFH
Internal RAM area
(60 KB)
Use prohibited
3FF0000H
3FEFFFFH
Use prohibited
3FEF000H
3FEEFFFH
Programmable
peripheral I/O area
1000000H
0FFFFFFH
3FEC000H
External memory area
(8 MB)
CS3
0800000H
07FFFFFH
External memory area
(4 MB)
CS2
0400000H
03FFFFFH
01FFFFFH
Internal ROM/
external memory areaNote
(1 KB)
External memory area
(2 MB)
CS1
CS0
0200000H
01FFFFFH
0100000H
00FFFFFH
Internal ROM/
external memory areaNote
(1 KB)
(2 MB)
0000000H
0000000H
Note Addresses 0000000H to 00FFFFFH are internal ROM area when a fetch access or read access is
performed and external memory area when a write access is performed.
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5.3.2 Chip select function
Of the 64 MB address space, the lower 16 MB (0000000H to 0FFFFFFH) include four chip select functions, CS0 to
CS3. The areas that can be selected by CS0 to CS3 are fixed as shown in Table 5-2.
However, since the V850ES/FJ2 has sixteen address pins (PDL0/AD0 to PDL15/AD15); 64 KB addresses can be
selected linearly.
Table 5-2. Area Selected by Chip Select Function
Pin Name
CS0
Area
0000000H to 01FFFFFH (2 MB)
0200000H to 03FFFFFH (2 MB)
0400000H to 07FFFFFH (4 MB)
0800000H to 0FFFFFFH (8 MB)
CS1
CS2
CS3
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5.4 Bus Access
5.4.1 Number of clocks for access
The following table shows the number of base clocks required for accessing each resource.
Table 5-3. Number of Clocks for Access
Area (Bus Width)
Internal ROM (32 Bits)
Internal RAM (32 Bits)
External Memory (16 Bits)
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
1
2
3
1Note
1
3 + n
3 + n
3 + n
1
Note 2 if a conflict with a data access occurs.
Remark Unit: Clocks/access
5.4.2 Bus size setting function
The bus size of each external memory area selected by CS0 to CS3 can be set (to 8 bits or 16 bits) by using the
bus size configuration (BSC) register.
The external memory area (01000000H to 0FFFFFFH) of the V850ES/FJ2 is selected by CS0 to CS3.
(1) Bus size configuration (BSC) register
The BSC register can be read or written in 16-bit units.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
access an external memory area other than the one for this initialization routine until the
initial settings of the BSC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
After reset: 5555H
15
R/W
14
Address: FFFFF066H
13
0
12
1
11
0
10
1
9
0
1
0
8
1
BSC
0
7
0
1
6
5
4
3
2
0
BS30
0
BS20
0
BS10
BS00
CSn signal
CS3
CS2
CS1
CS0
BSn0
Data bus size of CSn space (n = 0 to 3)
0
1
8 bits
16 bits
Caution Be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0.
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5.4.3 Access according to bus size
The V850ES/FJ2 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus
size is as follows.
• The bus size of the on-chip peripheral I/O is fixed to 16 bits.
• The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register).
The operation when each of the above is accessed is described below. All data is accessed starting from the lower
side.
The V850ES/FJ2 supports only the little-endian format.
Figure 5-2. Little-Endian Address in Word
31
24 23
16 15
8 7
0
000BH
0007H
0003H
000AH
0006H
0002H
0009H
0005H
0001H
0008H
0004H
0000H
(1) Byte access (8 bits)
(a) 16-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
Address
15
15
2n + 1
8
8
7
7
0
7
7
0
2n
0
0
Byte data External data
bus
Byte data External data
bus
(b) 8-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
Address
2n
7
0
7
0
7
0
7
0
2n + 1
Byte data External data
bus
Byte data External data
bus
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(2) Halfword access (16 bits)
(a) With 16-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
First access Second access
Address
2n + 1
15
15
Address
Address
15
15
15
15
8
7
8
7
2n + 1
2n
8
7
8
7
8
7
8
7
2n
2n + 2
0
0
0
0
0
0
Halfword data External data
bus
Halfword data
External data
bus
Halfword data
External data
bus
(b) 8-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
First access Second access
First access
Second access
15
15
15
15
Address
2n + 1
Address
2n
Address
2n + 2
Address
2n + 1
8
7
8
7
8
7
8
7
7
0
7
0
7
0
7
0
0
0
0
0
Halfword data External data Halfword data External data
bus bus
Halfword data External data Halfword data External data
bus bus
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(3) Word access (32 bits)
(a) 16-bit data bus width (1/2)
<1> Access to address (4n)
First access
31
Second access
31
24
23
24
23
Address
4n + 1
Address
4n + 3
16
15
16
15
15
15
8
7
8
7
8
7
8
7
4n
4n + 2
0
0
0
0
Word data External data
bus
Word data External data
bus
<2> Access to address (4n + 1)
First access
31
Second access
Third access
31
31
24
23
24
23
24
23
Address
16
Address
4n + 3
Address
4n + 4
16
15
16
15
15
15
15
15
4n + 1
8
7
8
7
8
7
8
7
8
7
8
7
4n + 2
0
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
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(a) 16-bit data bus width (2/2)
<3> Access to address (4n + 2)
First access
31
Second access
31
24
23
24
23
Address
16
Address
16
15
15
15
15
4n + 3
4n + 2
4n + 5
4n + 4
8
7
8
7
8
7
8
7
0
0
0
0
Word data External data
bus
Word data External data
bus
<4> Access to address (4n + 3)
First access
31
Second access
31
Third access
31
24
23
24
23
24
23
Address
16
Address
Address
4n + 6
16
15
16
15
15
15
15
15
4n + 3
4n + 5
4n + 4
8
7
8
7
8
7
8
7
8
7
8
7
0
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
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(b) 8-bit data bus width (1/2)
<1> Access to address (4n)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
4n
Address
4n + 1
Address
4n + 2
Address
4n + 3
8
7
8
7
8
7
8
7
7
0
7
0
7
0
7
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
Word data External data
bus
<2> Access to address (4n + 1)
First access
Second access
Third access
31
Fourth access
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
8
7
8
7
8
7
8
7
Address
4n + 1
Address
4n + 2
Address
4n + 3
Address
4n + 4
7
0
7
0
7
0
7
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
Word data External data
bus
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(b) 8-bit data bus width (2/2)
<3> Access to address (4n + 2)
First access
Second access
Third access
Fourth access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
4n + 2
Address
4n + 3
Address
4n + 4
Address
4n + 5
8
7
8
7
8
7
8
7
7
0
7
0
7
0
7
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
Word data External data
bus
<4> Access to address (4n + 3)
First access
Second access
Third access
31
Fourth access
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
4n + 3
Address
4n + 4
Address
4n + 5
Address
4n + 6
8
7
8
7
8
7
8
7
7
0
7
0
7
0
7
0
0
0
0
0
Word data External data
bus
Word data External data
bus
Word data External data
bus
Word data External data
bus
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5.5 Wait Function
5.5.1 Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each memory block space.
The number of wait states can be programmed for each chip select area (CS0 to CS3) by using data wait
control register 0 (DWC0). Immediately after system reset, 7 data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The on-chip peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
not access an external memory area other than the one for this initialization routine until
the initial settings of the DWC0 register are complete. However, external memory areas
whose initial settings are complete may be accessed.
After reset: 7777H
15
R/W
14
Address: FFFFF484H
13
12
11
0
10
9
8
DWC0
0
DW32
DW31
DW30
DW22
DW21
DW20
CSn signal
CS3
5
CS2
1
7
6
4
3
2
0
0
DW12
DW11
CS1
DW10
0
DW02
DW01
CS0
DW00
CSn signal
Number of wait states inserted in
CSn space (n = 0 to 3)
DWn2
DWn1
DWn0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
1
2
3
4
5
6
7
Caution Be sure to clear bits 15, 11, 7, and 3 to 0.
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5.5.2 External wait function
To synchronize an extremely slow external memory, I/O device, or asynchronous system, any number of wait states
can be inserted in the bus cycle by using the external wait pin (WAIT).
Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the
external wait function, in the same manner as the programmable wait function.
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2
and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in
the next state, or not inserted at all.
5.5.3 Relationship between programmable wait and external wait
Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the
programmable wait and the wait cycles controlled by the WAIT pin.
Figure 5-3. Wait Control
Programmable wait
Wait control
Wait via WAIT pin
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait
states will be inserted in the bus cycle.
Figure 5-4. Inserting Wait Example
TW
T1
TW
TW
T2
CLKOUT
WAIT pin
Wait via WAIT pin
Programmable wait
Wait control
Remark The circles indicate the sampling timing.
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5.5.4 Programmable address wait function
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control
register (AWC). Address wait insertion is set for each chip select area (CS0 to CS3).
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
After reset: FFFFH
15
R/W
14
Address: FFFFF488H
13
1
12
1
11
1
10
1
9
1
1
8
1
0
AWC
1
7
1
6
5
4
3
2
AHW3
ASW3
AHW2
ASW2
AHW1
ASW1
AHW0
ASW0
CSn signal
CS3
CS2
CS1
CS0
AHWn
Specification of insertion of address hold wait in CSn space (n = 0 to 3)
0
1
Not inserted
Inserted
ASWn
Specification of insertion of address setup wait in CSn space (n = 0 to 3)
0
1
Not inserted
Inserted
Caution Be sure to set bits 15 to 8 to 1.
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5.6 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
cycle that is executed for each space selected by the chip select function. By inserting an idle state, the data output
float delay time of the memory can be secured during read access (an idle state cannot be inserted during write
access).
Whether the idle state is to be inserted can be programmed by using the bus cycle control (BCC) register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control (BCC) register
The BCC register can be read or written in 16-bit units.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
state insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area other than the one for this initialization routine until the
initial settings of the BCC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
After reset: AAAAH
15
R/W
Address: FFFFF48AH
14
0
13
12
0
11
10
0
9
1
1
8
0
0
BCC
1
7
1
5
1
3
4
2
6
BC31
CS3
0
BC21
CS2
0
BC11
CS1
0
BC01
CS0
0
CSn signal
Specification of insertion of idle state (n = 0 to 3)
BCn1
0
1
Not inserted
Inserted
Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
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5.7 Bus Hold Function
5.7.1 Functional outline
The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for bus
mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until a
peripheral I/O register or the external memory is accessed.
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
configuration of multi-processor type systems in which two or more bus masters exist.
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing
function or a bit manipulation instruction.
Status
Data Bus
Width
Access Type
Timing at Which Bus Hold Request
Is Not Acknowledged
CPU bus lock
16 bits
8 bits
−
Word access to even address
Word access to odd address
Between first and second access
Between first and second access
Between second and third access
Between first and second access
Between first and second access
Between second and third access
Between third and fourth access
Between first and second access
Halfword access to odd address
Word access
Halfword access
Read-modify-write access of bit
manipulation instruction
−
Between read access and write
access
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5.7.2 Bus hold procedure
The bus hold status transition procedure is shown in Figure 5-5.
Figure 5-5. Bus Hold Status Transition
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
<5> HLDAK = 0
Normal status
Bus hold status
Normal status
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Bus cycle start request inhibition released
<9> Bus cycle starts
HLDRQ (input)
HLDAK (output)
<1> <2>
<3><4> <5>
<6> <7><8><9>
5.7.3 Operation in power save mode
Because the internal system clock is stopped in the software STOP, IDLE1, IDLE2 and Sub IDLE modes, the bus
hold status is not entered even if the HLDRQ pin is asserted.
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold
status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold
status is cleared.
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5.8 Bus Priority
Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the
external bus cycle.
Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch
(successive).
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
accesses due to bus size limitations.
Table 5-4. Bus Priority
Priority
High
External Bus Cycle
Bus Master
External device
DMAC
Bus hold
DMA transfer
Operand data access
Instruction fetch (branch)
Instruction fetch (successive)
CPU
CPU
Low
CPU
5.9 Boundary Operation Conditions
5.9.1 Program space
(1) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation straddling over
the on-chip peripheral I/O area (invalid fetch) does not occur.
(2) Instruction execution to the external memory area cannot be continued without a branch from the internal ROM
area to the external memory area.
5.9.2 Data space
The V850ES/FJ2 has an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword
data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least
twice, causing the bus efficiency to drop.
(1) Halfword-length data access
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(2) Word-length data access
(a) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if
the least significant bit of the address is 1.
(b) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
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5.10 BusTiming
5.10.1 Multiplexed bus
Figure 5-6. Basic Bus Cycle
T1
A1
T2
D1
T3
T1
A2
T2
TW
D2
TW
T3
TI
T1
A3
CLKOUT
AD15 to AD0
ASTB
CSn
WAIT
RD
Programmable
Weight
External
Weight
Idle
State
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
Remark ↑↓: Sampling clock
At the time of 8bit access
AD15-AD8
Odd number address
Even number address
Data
−
AD7-AD0
−
Data
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Figure 5-7. When Wait State (1 Wait) Is Inserted
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT
AD15 to AD8
AD7 to AD0
A1
D1
A2
D2
A1
A2
A3
ASTB
CSn
WAIT
RD
Programmable
Weight
External
Weight
Idle
State
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
Remark
.↑↓: Sampling clock
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Figure 5-8. When Idle State Is Inserted
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT
AD15 to AD0
A1
D1
A2
D2
A3
ASTB
CSn
WAIT
WR1, WR0
00
00
Programmable
Weight
External
Weight
Idle
State
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
Remark. ↑↓: Sampling clock
At the time of 8bit access
AD15-AD8
Odd number address
Data
Even number address
Uncertain
Data
AD7-AD0
Uncertain
01
WRn (n = 1 or 0)
10
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Figure 5-9. When Wait State (1 Wait) and Idle State Are Inserted
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
CLKOUT
AD15 to AD8
A1
A2
D2
A1
D1
A2
A3
AD7 to AD0
ASTB
CSn
WAIT
WR1, WR0
10
10
Programmable
Weight
External
Weight
Idle
State
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
Remark. ↑↓: Sampling clock
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Figure 5-10. When Address Wait State Is Inserted
T1
T2
TASW
T1
TAHW
T2
T3
CLKOUT
AD15 to AD0
ASTB
A1
D1
Address
Data
CSn
WAIT
WR1, WR0
00
00
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
Remark. ↑: Sampling clock
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Figure 5-11. Basic Bus Cycle
T1
T2
T3
TI
TH
TH
TH
TH
TI
T1
T2
T3
CLKOUT
HLDRQ
HLDAK
AD15 to AD0
Undefined
Undefined
A1
D1
A2
D2
ASTB
CSn
RD
All
All
Bus Idle
Notes 1. AD0 to AD7 hold the address output when odd address byte data is accessed.
AD8 to AD15 hold the address output when even address byte data is accessed.
2. WR0 and WR1 output a low level as shown in the above timing chart when target data access is
performed. At all other times, these pins output a high level.
3. CSn (n = 3 to 0) becomes low level, as shown above, when the corresponding CSn area is accessed.
Otherwise, CSn is always high level.
4. Idle state (TI) that does not depend on the setting value of BCC register.
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CHAPTER 6 CLOCK GENERATION FUNCTION
6.1 Overview
The following clock generation functions are available.
{ Main clock oscillator
• In clock-through mode
fX = 4 to 5 MHz (fXX = 4 to 5 MHz)
• In PLL (Phase Locked Loop) mode
fX = 4 to 5 MHz (fXX = 16 to 20 MHz)
{ Subclock oscillator (sub-resonator)
• 32.768 kHz
• 20 kHz (RCR = 390 kΩ, C = 47 pF)
{ Multiply (×4) function via PLL (Phase Locked Loop)
• Clock-through mode/PLL mode selectable
{ Ring OSC
• fR = 200 kHz (TYP.)
{ Internal system clock generation
• 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT
{ Peripheral clock generation
)
{ Clock output function
{ Programmable clock output (PCL) function
Remarks: 1. fX：main clock oscillation frequency
2. fXX：Main clock frequency
3. fR：Internal oscillator clock frequency
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6.2 Configuration
Figure 6-1. Clock Generator
FRC bit
Xtal
XT1
f
XT
f
XT
Subclock
oscillator
Watch timer clock
XT2
IDLE
control
1/2 divider
RC
Select
oscillator
IDLE mode 1, 2
Prescaler 3
fX/2 to fX
/212
Watch timer (WT) clock,
CSIB0 clock
IDLE mode 1, 2
PLLON
bit
MFRC bit
Main clock oscillator
stop detection
CK3 bit
CK2 to CK0 bits
f
XX
X1
X2
IDLE
control
Main clock
oscillator
PLL
Prescaler 2
f
X
HALT mode
f
f
XX/32
XX/16
f
XT
Main clock
oscillator
f
CPU
f
f
f
XX/8
XX/4
XX/2
HALT
control
stop control
CPU clock
PCK1,
PCK0 bit
Internal
system clock
Software STOP mode
fCLK
SELPLL bit
f
XX
f
XX to fXX/1024
PCL
Prescaler 1
Prescaler 4
Peripheral clock
fX to fX/128
Watchdog timer 2 (WDT2)
Port CM
CLKOUT
8
R
f
1/8 divider
Ring-OSC
RSTP bit
Watchdog timer 2 (WDT2) clock
(1) Main clock oscillator
The main clock oscillator oscillates the following frequencies (fX).
• In clock-through mode
fX = 4 to 5 MHz (internal fXX = 4 to 5 MHz)
• In PLL mode
fX = 4 to 5 MHz (internal fXX = 16 to 20 MHz)
(2) Subclock oscillator
The subclock oscillator oscillates a frequency (fXT) of 32.768 kHz or 20 kHz.
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(3) Main clock oscillator stop control
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the software STOP mode or when the MCK bit of the PCC
register = 1 (valid only when the CLS bit of the PCC register = 1).
(4) Ring-OSC
Outputs a frequency (fR) = 200 kHz (TYP.)
(5) Prescaler 1
This prescaler generates the clock (fxx to fxx/1,024) to be supplied to on-chip peripheral functions. Peripheral
functions are as follows.
TMP0-TMP3, TMQ0-TMQ2, TMM0, CSIB0-CSIB2, UARTA0-UARTA3, ADC, WDT2.
(6) Prescaler 2
This circuit divides the CPU clock (fCPU) and main clock (fXX).
The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the internal system
clock (fCLK).
fCLK is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
(7) Prescaler 3
This circuit divides the clock generated by the main clock oscillator (fX) to a specific frequency (32.768 kHz)
and supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
(8) Prescaler 4
This prescaler generates the clock (fX to fX/1048) to be supplied to on-chip peripheral functions such as the
only WDT2.
(9) PLL
This circuit multiplies the clock generated by the main clock oscillator (fX) by 4.
It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied
clock is output. These modes can be selected by using the SELPLL bit of the PLL control register (PLLCTL).
PLL is started or stopped by the PLLON bit of the PLLCTL register.
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6.3 Control Registers
(1) Processor clock control register (PCC)
The PCC register is a special register. Data can be written to this register in combination of specific sequences
(see 3.4.9 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 03H.
(1/2)
After reset: 03H
R/W
Address: FFFFF828H
PCC
FRC
MCK
MFRC
CLSNote
CK3
CK2
CK1
CK0
FRC
Use of subclock on-chip feedback resistor
0
1
Used
Not used
MCK
Operation of main clock
0
1
Enable oscillation
Oscillation stopped
• Even if the MCK bit is set to 1 while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
• When the main clock is stopped and the device is operating on the subclock, clear
the MCK bit to 0 and wait until the oscillation stabilization time has been secured
by the program before switching back to the main clock.
MFRC
Use of main clock on-chip feedback resistor
0
1
Used
Not used
CLS
0
Status of CPU clock (fCPU)
Main clock operation
Subclock operation
1
Note The CLS bit is a read-only bit.
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(2/2)
CK3
0
CK2
0
CK1
0
CK0
0
Clock selection (fCLK/fCPU)
f
f
f
f
f
f
XX
0
0
0
1
XX/2
XX/4
XX/8
XX/16
XX/32
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
×
Setting prohibited
1
×
×
×
f
XT
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
output.
2. Use a bit manipulation instruction to manipulate the CK3 (0→1 or 1→0) bit. When using
an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Remark ×: don’t care
(a) Example of setting main clock operation → subclock operation
<1> CK3 bit ← 1:
Use a bit manipulation instruction. Do not change the CK2 to CK0 bits.
<2> Subclock operation: It takes up to the following number of instructions after the CK3 bit is set until
the subclock operation is started.
1/subclock frequency (fXT)
Therefore, read the CLS bit to check if the subclock operation has started.
<3> MCK bit ← 1:
Set the MCK bit to 1 only when stopping the main clock.
Cautions 1. When stopping the main clock, stop the PLL.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied, then change to the subclock operation mode. Setting clock by
CK2-CK0 (fxx-fxx/32) > Subclock (fXT) x4
(b) Example of setting subclock operation → main clock operation
<1> MCK bit ← 0:
<2> Insert wait cycles by program and wait until the oscillation of the main clock has stabilized.
<3> CK3 bit ← 0: Use a bit manipulation instruction. Do not change the CK2 to CK0 bits.
Main clock oscillation starts.
<4> Main clock operation: it takes up to the following time after the CK3 bit is set until the main clock
operation specified by the CK2 to CK0 bits is started.
Max.: (1/subclock frequency)
Therefore, read the CLS bit to check if the main clock operation has started.
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(2) CPU operation clock status register (CCLS)
The CCLS register indicates the CPU operating clock status.
This register is read-only, in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R
Address: FFFFF82EH
CCLS
0
0
0
0
0
0
0
CCLSF
CCLSF
CPU operating clock status
Operates on main clock (f ) or subclock (fXT
Operates on Internal oscillator (f
0
1
X
)
R)
Caution If WDT2 overflows before counting the oscillation stabilization time ends after a reset or STOP
mode release, it is judged as abnormal oscillation of fX (main clock) and the CPU operates on
the Ring-OSC clock.
(3) Ring-OSC mode register (RCM)
The RCM register is an 8-bit register that sets the operation mode of Ring-OSC.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
0
Address: FFFFF80CH
RCM
0
0
0
0
0
0
RSTOP
RSTOP
Operation/stop of Ring-OSC
0
1
Ring-OSC operating
Ring-OSC stopped
Caution 1. Ring-OSC can be stopped by setting the RSTOP bit of the RCM register to 1 only when “Ring-
OSC stopped” is selected by the option function.
Caution 2. If RSTOP bit is set (1), the internal oscillator is oscillated by .CCLSF bit is set (1) (WDT overflow
is generated in the oscillation stabilization time).Then, the RSTOP bit remains being set (1).
(4) Oscillation stabilization time select register (OSTS)
The OSTS register selects the oscillation stabilization time following reset or release of the STOP mode.
See 11.3 (1) Oscillation stabilization time select register (OSTS).
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6.4 Operation
6.4.1 Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
PCC Register
CLS Bit = 0, MCK Bit = 0
CLS Bit = 1,
MCK Bit = 0
CLS Bit = 1,
MCK Bit = 1
<1>
×
<2>
<3>
{
{
×
<4>
<5>
×
<6>
{
{
{
{
{
{
{
{
{
{
{
<7>
<6>
×
<7>
Main clock oscillator (fX)
Subclock oscillator (fXT)
CPU clock (fCPU)
{
{
{
{
×
×
{
×
{
×
{
{
{
×
{
{
{
×
×
×
Internal system clock (fCLK)
Peripheral clock (fXX to fXX/1,024)
WT clock (main)
×
×
{
{
{
{
{
{
{
{
×
×
×
×
×
×
×
×
×
×
×
×
{
{
×
{
{
{
{
×
×
×
WT clock (sub)
{
×
{
{
{
×
{
{
×
{
{
×
WDT2 clock (ring)
{
{
WDT2 clock (main)
×
×
{
Main clock oscillator (fxx)
×
×
×
×
×
×
PLL clock (fPLL
)
×
Note1
Note 2
×
{
×
×
Notes:1. The stable clock is supplied from beginning operation after the time of 172 passes and through the lock-
up time.
2. The operation enable at IDLE1 mode. Stopped at IDLE2 mode
Remark CLS bit: Bit 4 of the processor clock control register (PCC)
MCK bit: Bit 6 of the PCC register
O:
Operable
Stopped
×:
<1>: RESET pin input
<2>: During oscillation stabilization time count
<3>: HALT mode
<4>: IDLE1, IDLE2 mode
<5>: Software STOP mode
<6>: Subclock operation mode
<7>: Sub-IDLE mode
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6.4.2 Clock output function
The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin.
The internal system clock (fCLK) is selected by using the CK3 to CK0 bits of the processor clock control register
(PCC).
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the
control register of port CM.
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the
clock when it is in the operable status. It outputs a low level in the stopped status. However, the alternate-function
pin (PCM1: input mode) is selected in <1> and <2> after the RESET signal has been input. Consequently, the
CLKOUT pin goes into a high-impedance state.
6.5 PLL Function
6.5.1 Overview
The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 4 times
higher than the oscillation frequency, and select the clock-through mode.
When PLL function is used: Input clock = 4 to 5 MHz (output: 16 to 20 MHz)
Clock-through mode:
Input clock = 4 to 5 MHz (output: 4 to 5 MHz)
6.5.2 Control registers
(1) PLL control register (PLLCTL)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 01H.
After reset: 01H
R/W
0
Address: FFFFF82CH
PLLCTL
0
0
0
0
0
SELPLL PLLON
SELPLL
CPU operation clock selection
0
1
Clock-through mode
PLL mode
PLLON
Control of PLL operation/stop
0
1
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
Cautions 1. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
(unlocked), “0” is written to the SELOLL bit if data is written to it.
2. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
through mode).
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(2) Lock register (LOCKR)
Phase lock occurs at a given frequency following power application or immediately after the software STOP
mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This
time until stabilization is called the lockup status, and the stabilized state is called the locked status.
The lock register (LOCKR) includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Remark: At the lockup time (frequency stabilization time) LOCKR is set (1)
After reset: 00H
R
Address: FFFFF824H
LOCKR
0
0
0
0
0
0
0
LOCK
LOCK
PLL lock status check
0
1
Locked status
Unlocked status
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/reset
conditions are as follows.
[Set conditions]
• In IDLE2 or upon system resetNote
• In software STOP mode
• Upon setting of PLL stop (clearing of PLLON bit of PLLCTL register to 0)
• Upon stopping main clock and using CPU with subclock (setting of CK3 bit of PCC register to 1 and setting
of MCK bit of same register to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
oscillation stabilization time has elapsed.
[Reset conditions]
• Upon overflow of oscillation stabilization time following reset release (OSTS register default time)
• Upon oscillation stabilization timer overflow (time set by OSTS register) following software STOP mode
release, when the software STOP mode was set in the PLL operating status
• Upon PLL lockup timer overflow (time set by PLLS register) when the PLLON bit of the PLLCTL register is
changed from 0 to 1
• Upon oscillation stabilization timer overflow (time set by OSTS register) following software IDLE2 mode
release, when the software IDLE2 mode was set in the PLL operating status
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(3) PLL lockup time specification register (PLLS)
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLON bit of the PLLCTL
register is changed from 0 to 1.
This register can be read or written in 8-bit units.
Reset input sets this register to 03H.
After reset: 03H
R/W
0
Address: FFFFF6C1H
PLLS
0
0
0
0
0
PLLS1
PLLS0
PLLS1
PLLS0
Selection of PLL lockup time
0
0
1
1
0
1
0
1
Setting prohibited
Setting prohibited
212/f
213/f
X
X
(default value)
Caution Set so that the lockup time is 800 µs or longer.
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(4) Programmable clock mode register (PCLM)
The PCLM register is an 8-bit register used to control the PCL output.
This register can be read or written in 8-bit or 1-bit units.
After reset: 00H
R/W
0
Address: FFFFF82FH
PCLM
0
0
PCLE
0
0
PCK1
PCK0
PCLE
Selection of PCL output operation
PCL output disabled (fixed to low level)
PCL output enabled
0
1
Caution Set the port-related control registers (PM, PMC, PFC, PFCE, etc.) first, and then set PCLE to 1.
PCK1
PCK0
Selection of PLL output clock
0
0
1
1
0
1
0
1
f
f
f
f
XX/2
XX/4
XX/8
XX/16
Caution Set PCLE to 1 only during PLL operation. To stop the PLL, clear PCLE to 0.
6.5.3 Usage
(1) To use PLL
• After the RESET signal has been released, the PLL operates (PLLON bit = 1), but because the default mode
is the clock-through mode (SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
• To operate the PLL from the stopped status, set the PLLON bit to 1, and then set the SELPLL bit to 1 after
the LOCKR.LOCK bit = 0 (the lockup time can be counted by setting the lockup time to the PLLS register
and monitoring the LOCK flag of the LOCKR register).
• To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then
stop the PLL (PLLON bit = 0)
When shifting to the IDLE2 or STOP mode while remaining in the PLL operation mode, set the OSTS register
as follows.
• Software STOP mode: Oscillation stabilization time > PLL lockup time (800 µs (min.))
• IDLE2 mode: Setup time > PLL lockup time (800 µs (min.))
When shifting to the IDLE1 mode, the PLL does not stop.Stop the PLL if necessary.
(2) When PLL is not used
• The clock-through mode (SELPLL bit = 0) is selected after the RESET signal has been released, but the PLL
is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P
The V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2 include 16-bit timer/event counter P (TMP0 to TMP3).
7.1 Features
Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways.
TMP can perform the following operations.
• PWM output
• Interval timer
• External event counter (operation disabled when clock is stopped)
• One-shot pulse output
• Pulse width measurement function
• Timer synchronized operation function
• Free-running function
• External trigger pulse output function
7.2 Functional Outline
• Capture trigger input signal × 2
• External trigger input signal × 1
• Clock selection × 8
• External event count input × 1
• Readable counter × 1
• Capture/compare reload register × 2
• Capture/compare match interrupt × 2
• Timer output (TOPn0, TOPn1) × 2
Remark n = 0 to 3
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7.3 Configuration
TMP consists of the following hardware.
Table 7-1. Configuration ofTMP0 to TMP3
Item
Timer register
Registers
Configuration
16-bit counter
TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1)
TMPn counter read buffer register (TPnCNT)
CCR0, CCR1 buffer registers
Timer inputs
2 (TIPn0Note 1, TIPn1)
Timer outputs
Control registers
2 (TOPn0, TOPn1)
TMPn control registers 0, 1 (TPnCTL0, TPnCTL1)
TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)
TMPn option register 0 (TPnOPT0)
Selector operation control registers 0, 1 (SELCNT0, SELCNT1Note 2
)
TIPnm pin noise elimination control register (PnmNFC)
Notes 1. TIPn0 functions alternately as a capture trigger input signal, external trigger input signal, and external
event count input signal.
2. SELCNT1 is incorporated only in the µPD70F3239.
Remark n = 0 to 3, m = 0, 1
The pins of TMP function alternately as port pins. For how to set the alternate function, refer to the description of
the registers in CHAPTER 4 PORT FUNCTIONS.
Table 7-2. TMP Pin List
Pin Name
TIP00
TIP01
TIP10
TIP11
Alternate-Function Pin
P32/ASCKA0/TOP00/TOP01
P33/TOP01/CTXD0
P34/TOP10/CRXD0
P35/TOP11
I/O
Function
Input
External event/clock input (TMP0)
External event/clock input (TMP1)
External event/clock input (TMP2)
External event/clock input (TMP3)
Timer output (TMP0)
TIP20
TIP21
TIP30
TIP31
TOP00
TOP01
P97/SIB1/TOP20
P96/TOP21
P01/TOP30
P00/TOP31
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
P33/TIP01/CTXD0
P34/TIP10/CRXD0
P35/TIP11
Output
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
Timer output (TMP1)
Timer output (TMP2)
Timer output (TMP3)
P97/SIB1/TIP20
P96/TIP21
P01/TIP30
P00/TIP31
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Figure 7-1. Block Diagram of Timer P
Internal bus
TPnCTL0
TPnIOC2
TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnEES1 TPnEES0 TPnETS1 TPnETS0
TPnCE
f
XX
f
f
f
XX/2
XX/4
XX/8
TPnCCR0
f
f
f
XX/16
XX/32
XX/64
CCR0 buffer
register
TPnCNT0
Load
Clear
INTTPnCC0
f
XX/128Note 1
Note 2
XT
f
TPnCE
Edge
detector
Counter control
16-bit counter
INTTPnOV
CCR1 buffer
register
Trigger
control
INTTPnCC1
Load
Edge
detector
Edge
TPnCCR1
TIPn0
TIPn1
detector
Note 3
Note 4
Capture/compare
selection function
Edge
detector
SELCNT0/1
TOPn0
TOPn1
Output
controller
ISEL11 to ISEL10,
ISEL06 to ISEL00
TPnIS3 to TPnIS0 TPnSYE TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0
TPnCCS1 TPnCCS0 TPnOVF
TPnOPT0
TPnOL1 TPnOE1 TPnOL0 TPnOE0
TPnIOC0
TPnIOC1
TPnCTL1
Internal bus
Notes 1. TMP0, TMP2
2. TMP1, TMP3
3. TSOUT signal of CAN0 block (TMP0)
RXDA0 pin (TMP1)
TSOUT signal of CAN2 block (TMP2)
RXDA2 pin (TMP3)
Refer to 7.4 (7) Selector operation control register 0 (SELCNT0) and 7.4 (8) Selector operation
control register 1 (SELCNT1).
4. INTTM0EQ0 interrupt of TMM block or TSOUT signal of CAN1 block (TMP0)
RXDA1 pin (TMP1)
TSOUT signal of CAN3 block (TMP2)
RXDA3 pin (TMP3)
Refer to 7.7 (1) Selector operation control register 0 (SELCNT0) and 7.7 (2) Selector operation
control register 1 (SELCNT1).
Remark n = 0 to 3
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(1) TMPn capture/compare register 0 (TPnCCR0)
The TPnCCR0 register is a 16-bit register that has a capture function and a compare function.
Only in the free-running mode, this register is used as a capture register or a compare register, this behavior
can be specified by using the TPnCCS0 bit of the TPnOPT0 register.
In the pulse width measurement mode, this register works only as a capture register.
In all the modes other than the free-running mode and pulse width measurement mode, this register functions
as a compare register.
In the default status, the TPnCCR0 register functions as a compare register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
Caution At the time of subclock operated and main clock stopped, the access to TPnCCR0 is
prohibited. For details, refer to 3. 4. 10（2）
After reset: 0000H R/W
Address: TP0CCR0: FFFFF596H, TP1CCR0: FFFFF5A6H,
TP2CCR0: FFFFF5B6H, TP3CCR0: FFFFF5C6H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPnCCR0
(n = 0 to 3)
• When used as compare register
TPnCCR0 can be rewritten when TPnCE = 1.
TMP Operation Mode
Method of Writing TPnCCR0 Register
PWM output mode or external trigger pulse
output mode
Reload
Free-running mode, external event count mode,
one-shot pulse output mode, or interval timer
mode
Anytime write
Pulse width measurement mode
Cannot be used because used only as capture
register
• When used as capture register
The count value is stored in TPnCCR0 on detection of the edge of the capture trigger (TIPn0) input.
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(2) TMPn capture/compare register 1 (TPnCCR1)
The TPnCCR1 register is a 16-bit register that has a capture function and a compare function.
Only in the free-running mode, this register is used as a capture register or a compare register, this behavior
can be specified by using the TPnCCS0 bit of the TPnOPT0 register.
In the pulse width measurement mode, this register works only as a capture register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
Caution At the time of subclock operation and main clock stopped, the access to TPnCCR1 is
prohibited. For details, refer to 3. 4. 10（2）
After reset: 0000H R/W
Address: TP0CCR1: FFFFF598H, TP1CCR1: FFFFF5A8H,
TP2CCR1: FFFFF5B8H, TP3CCR1: FFFFF5C8H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPnCCR1
(n = 0 to 3)
• When used as compare register
TPnCCR1 can be rewritten when TPnCE = 1.
TMP Operation Mode
Method of Writing TPnCCR1 Register
PWM output mode or external trigger pulse
output mode
Reload
Free-running mode, external event count mode,
one-shot pulse output mode, or interval timer
mode
Anytime write
Pulse width measurement mode
Cannot be used because used only as capture
register
• When used as capture register
The count value is stored in TPnCCR1 on detection of the edge of the capture trigger (TIPn1) input.
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(3) TMPn counter read buffer register (TPnCNT)
The TPnCNT register is a read buffer register that can read the value of the 16-bit counter.
This register is read-only, in 16-bit units.
Reset input sets this register to FFFFH.
Although the hardware status is FFFFH when TPnCE = 0, 0000H is read from this register.
The counter value of the 16-bit counter is read when TPnCE = 1.
Caution At subclock operated and at main clock stopped, the acsess to TPnCNT register is not enable.
For details, refer to 3. 4. 10（2）
After reset: FFFFH
R
Address: TP0CNT: FFFFF59AH, TP1CNT: FFFFF5AAH,
TP2CNT: FFFFF5BAH, TP3CNT: FFFFF5CAH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPnCNT
(n = 0 to 3)
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7.4 Control Registers
(1) TMPn control register 0 (TPnCTL0)
The TPnCTL0 register is an 8-bit register that controls the operation of timer P.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
TPnCTL0 register cannot be rewritten in operating. But only TPnCE bit can always be rewritten.
(1/2)
After reset: 00H
R/W
Address: TP0CTL0: FFFFF590H, TP1CTL0: FFFFF5A0H,
TP2CTL0: FFFFF5B0H, TP3CTL0: FFFFF5C0H
7
6
0
5
0
4
0
3
0
2
1
0
TPnCTL0
TPnCE
TPnCKS2 TPnCKS1 TPnCKS0
(n = 0 to 3)
TPnCE
Control of operation of timer Pn
0
1
Disable internal operating clock operation (asynchronously reset TMPn).
Enable internal operating clock operation.
The TPnCE bit controls the internal operating clock and asynchronously resets TMPn. When this bit
is cleared to 0, the internal operating clock of TMPn is stopped (fixed to the low level), and TMPn is
asynchronously reset.
When the TPnCE bit is set to 1, the internal operating clock is enabled within 2 input clocks, and
TMPn counts up.
TPnCKS2 TPnCKS1 TPnCKS0
Selection of internal count clock
n = 0, 2 n = 1, 3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
fXT
Caution Set the TPnCKS2 to TPnCKS0 bits when TPnCE = 0.
When the TPnCE bit setting is changed from 0 to 1, the TPnCKS2 to
TPnCKS0 bits can be set at the same time.
Remark
f
f
XX: Main system clock frequency
XT: XT1 input clock frequency
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(2/2)
Resolution and maximum number of counts
Internal count clock Resolution [µs]
Maximum count time [ms]
fXX = 16 MHz
fXX = 20 MHz
0.050
fXX = 16 MHz
4.10
fXX = 20 MHz
3.28
fXX
0.0625
0.125
0.250
0.500
1.000
2.000
4.000
8.000
fXX/2
0.100
8.19
6.55
fXX/4
0.200
16.38
13.11
fXX/8
0.400
32.77
26.21
fXX/16
fXX/32
fXX/64
fXX/128
0.800
65.54
52.43
1.600
131.11
262.14
524.29
104.86
209.72
419.43
3.200
6.400
Internal count clock
Resolution [µs]
Maximum count time [ms]
fXT = 32.768 kHz
2000.00
fXT = 32.768 kHz
30.52
fXT
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(2) TMPn control register 1 (TPnCTL1)
The TPnCTL1 register is an 8-bit register that controls the operation of timer P.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
(1/2)
After reset: 00H
R/W
Address: TP0CTL1: FFFFF591H, TP1CTL1: FFFFF5A1H,
TP2CTL1: FFFFF5B1H, TP3CTL1: FFFFF5C1H
7
6
5
4
0
3
0
2
1
0
TPnCTL1 TPnSYE
TPnEST
TPnEEE
TPnMD2
TPnMD1
TPnMD0
(n = 0 to 3)
TPnSYE
Tuned operation mode enable control
0
1
Independent operation mode (asynchronous operation mode)
Tuned operation mode (specification of slave operation)
In this mode, timer P can operate in synchronization with a master timer.
Master timer
TMP0
Slave timer
TMP1
TMP3
TMQ2
–
TMQ0
–
TMP2
TMQ1
For the tuned operation mode, refer to 7.6 Timer Synchronized Operation Function.
Caution Be sure to clear the TP0SYE and TP2SYE bits to 0.
TPnEST
Software trigger control
No operation
0
1
In one-shot pulse mode: One-shot pulse software trigger
In external trigger pulse output mode: Pulse output software trigger
The TPnEST bit functions as a software trigger in the one-shot pulse mode or external trigger pulse
output mode (this bit is invalid in any other mode). By setting TPnEST to 1 when TPnCE = 1, a
software trigger is issued. Therefore, be sure to set TPnEST to 1 when TPnCE = 1.
The TIPn0 pin is used for an external trigger. The read value of the TPnEST bit is always 0.
TPnEEE
Selection of count clock
Internal clock (clock selected by TPnCKS2 to TPnCKS0 bits)
External event count input (edge of input to TIPn0)
0
1
The valid edge is specified by the TPnEES1 and TPnEES0 bits when TPnEEE = 1 (External event
count input: TIPn0).
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(2/2)
TPnMD2
TPnMD1
TPnMD0
Selection of timer mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse mode
PWM mode
Free-running mode
Pulse width measurement mode
Setting prohibited
Cautions
1. Set the TPnEEE and TPnMD2 to TPnMD0 bits when TPnCE = 0 (the
same value can be written when TPnCE = 1). If these bits are
rewritten when TPnCE = 1, the operation cannot be guaranteed. If
these bits are rewritten by mistake, clear TPnCE to 0 and then set
them again.
2. The external event count input is selected regardless of the value
of the TPnEEE bit at an external event count mode.
3. Set "0" to bit 3 and 4.
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(3) TMPn I/O control register 0 (TPnIOC0)
The TPnIOC0 register is an 8-bit register that controls the timer outputs (TOPn0 and TOPn1).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TP0IOC0: FFFFF592H, TP1IOC0: FFFFF5A2H,
TP2IOC0: FFFFF5B2H, TP3IOC0: FFFFF5C2H
7
0
6
0
5
0
4
0
3
2
1
0
TPnIOC0
TPnOL1
TPnOE1
TPnOL0
TPnOE0
(n = 0 to 3)
TPnOLm
Setting of TOPnm output level (m = 0, 1)
0
1
Normal output
Inverted output
TPnOEm
0
Setting of TOPnm output (m = 0, 1)
Disable timer output (TOPnm pin outputs low level when TPnOLm = 0, and high level
when TPnOLm = 1).
1
Enable timer output (TOPnm pin outputs pulses).
Cautions 1. Rewrite the TPnOL1, TPnOE1, TPnOL0 and TPnOE0 bits when TPnCE
= 0 (the same value can be written when TPnCE = 1). If these bits are
rewritten by mistake, clear TPnCE to 0 and then set them again.
2. To enable the timer output, be sure to set the corresponding
alternate-function pins TPnIS3 to TPnIS0 of the TPnIOC1 register to
“Detect no edge” and invalidate the capture operation. Then set the
corresponding alternate-function port to output mode.
3. In the state of TPnCE bit = 0 and TPnOEm bit = 0, the output level of
TOPnm pin changes even when the TPnOLm bit is operated.
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(4) TMPn I/O control register 1 (TPnIOC1)
The TPnIOC1 register is an 8-bit register that controls the valid edge of the external input signals (TIPn0 and
TIPn1).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TP0IOC1: FFFFF593H, TP1IOC1: FFFFF5A3H,
TP2IOC1: FFFFF5B3H, TP3IOC1: FFFFF5C3H
7
0
6
0
5
0
4
0
3
2
1
0
TPnIOC1
TPnIS3
TPnIS2
TPnIS1
TPnIS0
(n = 0 to 3)
TPnIS3
TPnIS2
Setting of valid edge of capture input (TIPn1)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TPnIS1
TPnIS0
Setting of valid edge of capture input (TIPn0)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
Cautions 1. Rewrite the TPnIS3 to TPnIS0 bits when TPnCE0 = 0 (the same value
can be written when TPnCE = 1). If these bits are rewritten by
mistake, clear TPnCE to 0 and then set them again.
2. The TPnIS3 to TPnIS0 bits are valid only in the free-running mode
and pulse width measurement mode. A capture operation is not
performed in any other mode.
3. If used as the capture input, be sure to set the corresponding
alternate-function pins TPnOE1 and TPnOE0 of the TPnIOC0 register
to “Disable timer output” and set the capture input valid edge. Then
set the corresponding alternate-function port to input mode
4. Set it without the edge detection of the TIPn0 capture input (TPnIS1
and 0 bit = 00b) when using it in the external event count mode
(TPnEEE bit = 1 of TPnCTL1).
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(5) TMPn I/O control register 2 (TPnIOC2)
The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIPn0) and external trigger input signal (TIPn0).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TP0IOC2: FFFFF594H, TP1IOC2: FFFFF5A4H,
TP2IOC2: FFFFF5B4H, TP3IOC2: FFFFF5C4H
7
0
6
0
5
0
4
0
3
2
1
0
TPnIOC2
TPnEES1 TPnEES0 TPnETS1 TPnETS0
(n = 0 to 3)
TPnEES1 TPnEES0
Setting of valid edge of external event count input (TIP00)
0
0
1
1
0
1
0
1
Detect no edge (external event count is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TPnETS1 TPnETS0
Setting of valid edge of external trigger input (TIP00)
Detect no edge (external trigger is invalid).
Detect rising edge.
0
0
1
1
0
1
0
1
Detect falling edge.
Detect both the edges.
Cautions 1. Rewrite the TPnEES1, TPnEES0, TPnETS1and TPnETS0 bits when
TPnCE = 0 (the same value can be written when TPnCE = 1). If these
bits are rewritten by mistake, clear TPnCE to 0 and then set them
again.
2. The TPnEES1 and TPnEES0 bits are valid when TPnEEE = 1 or when
the external event count mode is set (TPnMD2 to TPnMD of
TIPnCTL1 register = 001).
3. TPnETS1and TPnETS0 bits are valid when the external trigger pulse
output mode (TPnMD2-0=010b of TPnCTL register) and the one-shot
pulse output mode (TPnMD2-0=011b of TPnCTL1 register) is set.
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(6) TMPn option register 0 (TPnOPT0)
The TPnOPT0 register is an 8-bit register that selects a capture or compare operation, and detects an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TP0OPT0: FFFFF595H, TP1OPT0: FFFFF5A5H,
TP2OPT0: FFFFF5B5H, TP3OPT0: FFFFF5C5H
7
0
6
0
5
4
3
0
2
0
1
0
0
TPnOPT0
(n = 0 to 3)
TPnCCS1 TPnCCS0
TPnOVF
TPnCCSm
Selection of capture or compare operation of TPnCCRm register (m = 0, 1)
0
1
Compare register
Capture register
The set value of the TPnCCSm bit is valid only in the free-running mode.
TPnOVF
Set (1)
Reset (0)
Detection of overflow of timer P
Overflow occurred
0 written to TPnOVF bit or TPnCE = 0
• The TPnOVF bit is set when the 16-bit counter overflows from FFFFH to 0000H in the free-running
mode and pulse width measurement mode.
• As soon as the TPnOVF bit has been set to 1, an interrupt request signal (INTTPnOV) is
generated. The INTTPnOV signal is not generated in any mode other than the free-running mode
and pulse width measurement mode.
• The TPnOVF bit is not cleared even if the TPnOVF bit and TPnOPT0 register are read when
TPnOVF = 1.
• The TPnOVF bit can be read and written, but 1 cannot be written to the TPnOVF bit. Writing 1 to
this bit does not affect the operation of timer P.
Caution Rewrite the TPnCCS1 and TPnCCS0 bits when TPnCE0 = 0 (the same
value can be written when TPnCE = 1). If these bits are rewritten by
mistake, clear TPnCE to 0 and then set them again.
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(7) TIPnm pin noise elimination control register n (PnmNFC)
The PnmNFC register is an 8-bit register that sets the digital noise filter of the timer P input pin for noise
elimination.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: P00NFC : FFFFFB00H (TIP00 pin)
P01NFC : FFFFFB04H (TIP01 pin)
P10NFC : FFFFFB08H (TIP10 pin)
P11NFC : FFFFFB0CH (TIP11 pin)
P20NFC : FFFFFB10H (TIP20 pin)
P21NFC : FFFFFB14H (TIP21 pin)
P30NFC : FFFFFB18H (TIP30 pin)
P31NFC : FFFFFB1CH (TIP31 pin)
7
6
5
0
4
0
3
0
2
1
0
PnmNFC
0
NFSTS
NFC2
NFC1
NFC0
NFSTS
Setting of number of times of sampling by digital noise filter
0
1
3 times
2 times
NFC2
NFC1
NFC0
Sampling clock
n = 0, 2
n = 1, 3
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fXX
fXX/2
fXX/4
fXX/16
fXX/32
fXX/64
fXX/8
fXX/16
fXT
Other than above
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 5 and 7 to 0.
2. A signal input to the timer input pin (TIPnm) before the PnmNFC
register is set is output with digital noise eliminated.
Therefore, set the sampling clock (NFC2 to NFC0) and the number of
times of sampling (NFSTS) by using the PnmNFC register, wait for
initialization time = (Sampling clock) × (Number of times of
sampling), and enable the timer operation.
Remarks 1. The width of the noise that can be accurately eliminated is (Sampling
clock) × (Number of times of sampling – 1). Even noise with a width
narrower than this may cause a miscount if it is synchronized with the
sampling clock.
2. n: Number of timer channels (0 to 3)
m: Number of input pins (0, 1)
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7.5 Operation
Timer P performs the following operations.
Operation
TPnEST (Software
Trigger Bit)
Invalid
TIPn0 (External
Trigger Input)
Capture/Compare
Selection
Compare Write
Interval timer mode
Invalid
Compare only
Compare only
Compare only
Anytime write
Anytime write
Reload
External event count mode Note 1
Invalid
Valid
Invalid
Valid
External trigger pulse output
modeNote 2
One-shot pulse output modeNote 2
Valid
Valid
Compare only
Compare only
Anytime write
Reload
PWM mode
Invalid
Invalid
Invalid
Invalid
Free-running mode
Capture/compare
selectable
Anytime write
Pulse width measurement modeNote 2 Invalid
Invalid
Capture only
Not applicable
Notes 1. To use the external event counter function, specify that the input edge of the TIPn0 pin is not detected (by
clearing the TPnIS1 and TPnIS0 bits of the TPnIOC1 register to “00”).
2. To use the external trigger pulse output mode, one-shot pulse mode, or pulse width measurement mode,
select a count clock (by clearing the TPnEEE bit of the TPnCTL1 register to 0).
Remark n = 0 to 3
7.5.1 Anytime write and reload
Timer P allows rewriting of the TPnCCR0 and TPnCCR1 registers while the timer is operating (TPnCE = 1). These
registers are written differently (anytime write or reload) depending on the mode.
(1) Anytime write
When data is written to the TPnCCRm register during timer operation, it is transferred at any time to the CCRm
buffer register and is compared with the value of the 16-bit counter.
Remark n = 0 to 3
m = 0, 1
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Figure 7-2. Flowchart of Basic Operation of Anytime Write
START
Initial setting
Enable timer operation (TpnCE = 1)
→ Transfer values of TPnCCR0
and TPnCCR1 to CCR0 buffer
register and CCR1 buffer register
Rewrite TPnCCR0
→ Transfer to CCR0 buffer register
Rewrite TPnCCR1
→ Transfer to CCR1 buffer register
INTTPnCC0 occurs
• CCR0 buffer register matches
16-bit counter.
• Clear and start 16-bit counter.
Remarks 1. This is an example in the interval timer mode.
2. n = 0 to 3
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Figure 7-3. Timing Chart of Anytime Write
TPnCE = 1
D01
D01
D02
16-bit
D12
D12
D11
D11
counter
D
01
TPnCCR0
D
02
02
CCR0 buffer
register
0000H
0000H
D
01
D
D11
D
12
12
TPnCCR1
CCR1 buffer
register
D11
D
INTTPnCC0
INTTPnCC1
Remarks 1. D01, D02: Set value of TPnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TPnCCR1 register (0000H to FFFFH)
2. This is an example in the interval timer mode.
3. n = 0 to 3
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(2) Reload
When data is written to the TPnCCR0 and TPnCCR1 registers during timer operation, it is compared with the
value of the 16-bit counter transferred to the CCRm buffer register after reserved until the written value
becoming a specific state. The values of the TPnCCR0 and TPnCCR1 registers can be rewritten when TPnCE
= 1.
So that the set values of the TPnCCR0 and TPnCCR1 registers are compared with the value of the 16-bit
counter (the set values are reloaded to the CCRm buffer register), the value of the TPnCCR0 register must be
rewritten and then a value must be written to the TPnCCR1 register before the value of the 16-bit counter
matches the value of TPnCCR0. When the value of the TPnCCR0 register matches the value of the 16-bit
counter, the values of the TPnCCR0 and TPnCCR1 registers are reloaded.
Whether the next reload timing is made valid or not is controlled by writing to the TPnCCR1 register. Therefore,
write the same value to the TPnCCR1 register when it is necessary to rewrite the value of only the TPnCCR0
register.
Figure 7-4. Flowchart of Basic Operation of Reload
START
Initial setting
Enable timer operation (TPnCE = 1)
→ Transfer value of TPnCCRm
to CCRm buffer register
Rewrite TPnCCR0.
Reload is enabled
INTTPnCC0 occurs
Rewrite TPnCCR1.
• TPnCCR0 matches 16-bit
counter.
• Clear and start 16-bit counter.
• Value of TPnCCRm is reloaded
to CCRm buffer register.
Caution Writing the TPnCCR1 register includes an operation to enable reload.Therefore, rewrite the
TPnCCR1 register after rewriting the TPnCCR0 register.
Remarks 1. This is an example in the PWM mode.
2. n = 0 to 3, m = 0, 1
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Figure 7-5. Timing Chart of Reload
TPnCE = 1
D01
D03
D02
D02
D11
D12
D12
D12
D12
16-bit
counter
D01
D02
D03
TPnCCR0
CCR0 buffer
register
0000H
0000H
D
D
01
11
D
D
03
Note 02
Same value write
TPnCCR1
D11
D
12
D12
CCR1 buffer
register
D
12
D12
Note
INTTPnCC0
INTTPnCC1
Note The value is not reloaded because the TPnCCR1 register is not written.
Remarks 1. D01, D02, D03: Set value of TPnCCR0 register (0000H to FFFFH)
D11, D12:
Set value of TPnCCR1 register (0000H to FFFFH)
2. This is an example in the PWM mode.
3. n = 0 to 3
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7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000)
In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated when the set value of the
TPnCCR0 register matches the value of the 16-bit counter, and the 16-bit counter is cleared. Rewriting the TPnCCR0
register is enabled when TPnCE = 1. When a value is set to the TPnCCRm register, it is transferred to the CCRm
buffer register by means of anytime write, and is compared with the value of the 16 bit counter.
The 16-bit counter is not cleared by using the TPnCCR1 register.
However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register and compared with the
value of the 16-bit counter. As a result, an interrupt request (INTTPnCC1) is generated.
The value can also be output from the TOPnm pin by setting the TPnOEm bit to 1.
When the TPnCCR1 register is not used, it is recommended to set the TPnCCR1 register to FFFFH.
Remarks 1. Refer to 7.5.1 Anytime write and reload about write operation of TPnCCR0, TPnCCR1 during timer
operation (TPnCE = 1).
2. n = 0 to 3, m = 0, 1
Figure 7-6. Flowchart of Basic Operation in Interval Timer Mode
START
Initial setting
• Select clock (TPnCTL0: TPnCKS2 to
TPnCKS0).
• Set interval timer mode (TPnCTL1:
TPnMD2 to TPnMD0 = 000).
• Set compare register (TPnCCR0,
TPnCCR1).
Enable timer operation (TPnCE = 1)
→ Transfer values of TPnCCR0 and
TPnCCR1 to CCR0 buffer register
and CCR1 buffer register
INTTPnCC1 occurs
INTTPnCC0 occurs
16-bit counter matches
CCR1 buffer registerNote
.
16-bit counter and CCR0
buffer register match.
Clear and start 16-bit counter.
Note The 16-bit counter is not cleared when its value matches the value of TPnCCR1.
Remark n = 0 to 3
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Figure 7-7. Timing of Basic Operation in Interval Timer Mode (1/2)
(a) When D1 > D2 > D3, only TPnCCR0 register value is written, and TOPn0 and TOPn1 are not output
(TPnOE0 = 0,TPnOE1 = 0,TPnOL0 = 0,TPnOL1 = 1)
TPnCE = 1
FFFFH
D1
D1
D2
D3
D3
D3
16-bit
counterNote
TPnCCR0
D1
D2
CCR0 buffer
register
0000H
D1
D2
TPnCCR1
D3
CCR1 buffer
register
D3
0000H
INTTPnCC0
INTTPnCC1
TOPn0
TOPn1
L
H
t
D1
t
D1
t
D2
Note The 16-bit counter is not cleared when its value matches the value of TPnCCR1.
Remarks 1. D1, D2: Set value of TPnCCR0 register (0000H to FFFFH)
D3:
Set value of TPnCCR1 register (0000H to FFFFH)
2. Interval time (tDn) = (Dn + 1) × (Count clock cycle)
3. n = 0 to 3
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Figure 7-7. Timing of Basic Operation in Interval Timer Mode (2/2)
(b) When D1 = D2, TPnCCR0 and TPnCCR1 are not rewritten, and TOPn0 and TOPn1 are output
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1)
TPnCE = 1
FFFFH
D1
= D
2
D1
= D
2
D1
= D
2
16-bit
counter
TPnCCR0
D1
CCR0 buffer
register
D1
0000H
TPnCCR1
D2
CCR1 buffer
register
D2
0000H
INTTPnCC0
INTTPnCC1
TOPn0
TOPn1
t
D1 = tD2
t
D1 = tD2
tD1 = tD2
Remarks 1. D1: Set value of TPnCCR0 register (0000H to FFFFH)
D2: Set value of TPnCCR1 register (0000H to FFFFH)
2. Interval time (tDn) = (Dn + 1) × (Count clock cycle)
3. n = 0 to 3
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7.5.3
External event count mode (TPnMD2 to TPnMD0 = 001)
In the external event count mode, the external event count input (TIPn0 pin input) is used as a count-up signal.
Regardless of the setting of the TPnEEE bit of the TPnCTL0 register, 16-bit timer/event counter P counts up the
external event count input (TIPn0 pin input) when it is set in the external event count mode.
In the external event count mode, an interrupt request (INTTPnCC0) is generated when the set value of the
TPnCCR0 register matches the value of the 16-bit counter, and the value of the 16-bit counter is cleared.
When a value is set to the TPnCCRm register, it is transferred to the CCR0 buffer register, and is compared with
the value of the 16-bit counter.
The 16-bit counter cannot be cleared by using the TPnCCR1 register.
However, the set value of the TPnCCR1 register is transferred to the CCR1 buffer register and is compared with the
value of the 16-bit counter. As a result, an interrupt request (INTTPnCC1) is generated.
By setting the TPnOE1 bit to 1, a signal can be output from the TOPn1 pin.
Rewriting the TPnCCR0 register is enabled when TPnCE = 1. When the TPnCCR1 register is not used, it is
recommended to set TPnCCR1 to FFFFH.
Remarks 1. Refer to 7.5.1 Anytime write and reload about write operation of TPnCCR0, TPnCCR1 during timer
operation (TPnCE = 1).
2. n = 0 to 3
Caution 1. TOPn0 pin output in an external event count mode cannot be used. Set to TPnEEE = 1by interval
timer mode (TPnMD2 to 0 = 000b) when TOPn0 pin output in an external event count mode is
used.
2. In external event count mode, when TPnCCRm register value is set to 0000H the interrupt
occurs after the overflow of the timer (FFFFH to 0000H)
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Figure 7-8. Flowchart of Basic Operation in External Event Count Mode
START
Initial setting
• Set external event count mode (TPnCTL1:
TPnMD2 to TPnMD0 = 001)Note 1
.
• Set valid edge (TPnIOC2: TPnEES1,
TPnEES0).
• Set compare register (TPnCCR0,
TPnCCR1).
Enable timer operation (TPnCE = 1)
→ Transfer values of TPnCCR0 and
TPnCCR1 to CCR0 buffer register
and CCR1 buffer register
INTTPnCC1 occurs
INTTPnCC0 occurs
16-bit counter matches
CCR1 buffer registerNote 2
.
16-bit counter matches
CCR0 buffer register.
Clear and start 16-bit counter.
Notes 1. Selecting the TPnEEE bit has no effect.
2. The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Remark n = 0 to 3
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Figure 7-9. Timing of Basic Operation in External Event Count Mode (1/2)
(a) When D1 > D2 > D3, only TPnCCR0 register value is rewritten, and TOPn1 is not output
(TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 1)
TPnCE = 1
FFFFH
D1
D1
D2
D3
D3
D3
16-bit
counter
TPnCCR0
D1
D2
CCR0 buffer
register
0000H
D1
D2
TPnCCR1
D3
CCR1 buffer
register
D3
0000H
INTTPnCC0
INTTPnCC1
Remarks 1. D1, D2: Set value of TPnCCR0 register (0000H to FFFFH)
D3: Set value of TPnCCR1 register (0000H to FFFFH)
2. Whenever times of (Set value of TPnCCRm register +1) are detected, the compare match interrupt is
generated (m = 0, 1)
3. n = 0 to 3
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Figure 7-9. Timing of Basic Operation in External Event Count Mode (2/2)
(b) When D
1
= D2, TPnCCR0 and TPnCCR1 are not rewritten, and TOPn1 is output
(TPnOE0 = 0, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1)
TPnCE = 1
FFFFH
D1
= D
2
D1
= D
2
D1
= D
2
16-bit
counter
TPnCCR0
D1
CCR0 buffer
register
D1
0000H
TPnCCR1
D2
CCR1 buffer
register
D2
0000H
INTTPnCC0
INTTPnCC1
TOPn1
Remarks 1. D1:
Set value of TPnCCR0 register (0000H to FFFFH)
Set value of TPnCCR1 register (0000H to FFFFH)
D2:
2. Whenever times of (Set value of TPnCCRm register +1) are detected, the compare match interrupt is
generated (m = 0, 1)
3. n = 0 to 3
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7.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010)
When TPnCE = 1 in the external trigger pulse output mode, the 16-bit counter keeps at FFFFH and waits for input
of an external trigger (input of TIPn0 pin or set of TPnEST bit). When the counter detects the trigger pulse input, it
starts counting up.
The duty factor of the signal output from the TOPn1 pin is set by a reload register (TPnCCR1) and the period is set
by a compare register (TPnCCR0).
In case of the software trigger mode, pulse of half cycle setting by TPnCCR0 register is outputted from TOPn0
terminal pin.
Rewriting the TPnCCR0 and TPnCCR1 registers is possible when TPnCE = 1.
To stop timer P, clear TPnCE to o. If the edge of the external trigger (input of TIPn0 pin or set TPnEST bit) is
detected more than once in the external trigger pulse output mode, the 16-bit counter is cleared at the point of edge
detection, and resumes counting up. Then, TOPn0, TOPn1 terminal pin is initialized at the same time.
Caution 1. In the external trigger pulse output mode, select the internal clock (TPnEEE of TPnCTL1 register
= 0) as the count clock.
2. In the external trigger pulse output mode, TPnCCR0 and TPnCCR1 registers are fixed as
compare register.Therefore, capture function can not to use.
Remarks 1. For the reload operation when TPnCCR0 and TPnCCR1 are rewritten during timer operation, refer to
7.5.1 (2) Reload.
2. n = 0 to 3
m = 0, 1
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Figure 7-10. Flowchart of Basic Operation in External Trigger Pulse Output Mode
START
Initial setting
• Select clock. (TPnCTL1: TPnEEE = 0)
(TPnCTL0: TPnCKS2 to TPnCKS0)
• Set external trigger pulse output
External trigger
(TIPn0 pin) input
mode. (TPnCTL1: TPnMD2 to
TPnMD0 = 010)
• Set compare register. (TPnCCR0,
TPnCCR1)
Clear and start
16-bit counter.
Enable timer operation (TPnCE = 1)
→ Transfer values of TPnCCR0 and
TPnCCR1 to CCR0 buffer register
and CCR1 buffer register
External trigger (TIPn0 pin) input
or TPnEST = 1 Note 1
→ 16-bit counter starts counting
16-bit counter matches
INTTPnCC1 occurs
TPnCCR1Note 2
.
16-bit counter matches TPnCCR0.
Clear and start 16-bit counter.
INTTPnCC0 occurs
Notes: 1. TPnEST bit of TPnCTL1 register can be written during timer operation (TPnCE = 1)
2. The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Remark n = 0 to 3
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Figure 7-11. Timing of Basic Operation in External Trigger Pulse Output Mode
(TPnOE0 = 0, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 1)
TPnCE = 1
FFFFH
D01
D02
16-bit
D12
counterNote
D11
D11
External trigger
(TIPn0 pin)
TPnCCR0
D
01
11
D
02
CCR0 buffer
register
0000H
0000H
D
01
D
02
12
TPnCCR1
D
D12
CCR1 buffer
register
D11
D
TOPn1
Note The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Remarks 1. D01, D02: Set value of TPnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TPnCCR1 register (0000H to FFFFH)
2. Duty of TOPn1 output = (Set value of TPnCCR1 register) / (Set value of TP0CCR0 register +1)
Cycle TOPn1 output = (Set value of TPnCCR0 +1) × (Count clock cycle)
3. n = 0 to 3
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7.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011)
When TPnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TPnEST bit (to 1)
or a trigger that is input when the edge of the TIPn0 pin is detected, while holding FFFFH. When the trigger is input,
the 16-bit counter starts counting up. When the value of the 16-bit counter matches the value of the CCR1 buffer
register that has been transferred from the TPnCCR1 register, TOPn1 goes high. When the value of the 16-bit counter
matches the value of the CCR0 buffer register that has been transferred from the TPnCCR0 register, TOPn1 goes low,
and the 16-bit counter is cleared to 0000H and stops. Input of a second or subsequent trigger is ignored while the 16-
bit counter is operating. Be sure to input a second trigger while the 16-bit counter is stopped at 0000H. The waveform
of the one-shot pulse is output from the TOPn1 pin. The TOPn0 pin produces an active level output during counting by
timer counter. Active level is set by TPnCL0 register.
Cautions:
1. Select the internal clock (TPnEEE of the TPnCTL1 register = 0) as the count clock in the one-
shot pulse mode.
2. In the one-shot pulse mode,TPnCCR0 and TPnCCR1 registers are fixed as compare register.
Therefore, capture function can not to use.
3. In the one-shot pulse mode, when setting value of TPnCCR1 register is bigger than setting
value of TPnCCR0 register, on-shot pulse is not outputted.
Remarks
1. In the one-shot pulse mode, TPnCCR0 and TPnCCR1 are rewritten during timer operation
(TPnCE=1). During timer operation (TPnCE=1), for anytime write operation when rewriting of
TPnCCR0 and TPnCCR1, refer to 7.5.1 (1) Anytime write.
2. n = 0 to 3
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Figure 7-12. Flowchart of Basic Operation in One-Shot Pulse Mode
START
Initial setting
• Select clock. (TPnCTL1: TPnEEE = 0)
(TPnCTL0: TPnCKS2 to TPnCKS0)
• Set one-shot pulse mode. (TPnCTL1:
TPnMD2 to TPnMD0 = 011)
• Set compare register. (TPnCCR0,
TPnCCR1)
Enable timer operation (TPnCE = 1)
→ Transfer values of TPnCCR0 and
TPnCCR1 to CCR0 buffer
register and CCR1 buffer register
Wait for trigger.
16-bit counter stands by at FFFFH.
Input external trigger (TIPn0 pin)
or TPnEST = 1 Note 1
→ 16-bit counter starts counting
Wait for trigger.
16-bit counter stands by at 0000H.
16-bit counter matches
INTTPnCC1 occurs
INTTPnCC0 occurs
CCR1 buffer register Note 2
.
16-bit counter matches
CCR0 buffer register.
Clear 16-bit counter.
Notes: 1. Only TPnEST bit of TPnCTL1 register can be written during timer operation (TPnCE = 1).
2. The 16-bit counter is not cleared when it matches the CCR1 buffer register.
Caution The 16-bit counter is not cleared even if the trigger is input while the counter is counting up, and
the trigger input is ignored.
Remark n = 0 to 3
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Figure 7-13. Timing of Basic Operation in One-Shot Pulse Mode
(TPnOE0 = 0, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1 TPnEST = 1
FFFFH
D0
D0
D0
Note
16-bit
counter
D1
D1
D1
External trigger
(TIPn0 pin)
TPnCCR0
D0
CCR0 buffer
register
0000H
0000H
D
0
TPnCCR1
D
1
CC1 buffer
register
D1
INTTPnCC0
INTTPnCC1
TOPn0
TOPn1
Note The 16-bit counter starts counting up either when TPnEST = 1 or when TIPn0 is input.
Remarks 1. D0: Set value of TPnCCR0 register (0000H to FFFFH)
D1: Set value of TPnCCR1 register (0000H to FFFFH)
2. n = 0 to 3
3. 3. The active level term of TOPn1 pin output is: (Set value of TPnCCR0 - Set value of TPnCCR1 +1) ×
Count clock cycle
Time of output delay = (Set value of TPnCCR1register) × Count clock cycle
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7.5.6 PWM mode (TPnMD2 to TPnMD0 = 100)
In the PWM mode, TMPn capture/compare register 1 (TPnCCR1) is used to set the duty factor and TMPn
capture/compare register 0 (TPnCCR0) is used to set the cycle.
By using these two registers and operating the timer, variable-duty PWM is output.
To stop timer P, clear TPnCE to 0. The waveform of PWM is output from the TOPn1 pin. The TOPn0 pin produces a
pulse of half the PWM cycle.
The TPnCCR0 and TPnCCR1 registers cannot be used as capture registers.
Remark n = 0 to 3
For the reload operation when TPnCCR0 and TPnCCR1 are rewritten during timer operation (TPnCE1=1), refer to
7.5.1 (2) Reload.
Caution In the PWM mode, TPnCCR0 and TPnCCR1 registers are fixed as compare register. Therefore, capture
function can not to use.
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(1) Operation flowchart of PWM mode
Figure 7-14. Flowchart of Basic Operation in PWM Mode (1/2)
(a) When values of TPnCCR0 and TPnCCR1 registers are not rewritten during timer operation
START
Initial setting
• Select clock.
(TPnCTL0: TPnCKS2 to TPnCKS0)
• Set PWM mode.
(TPnCTL1: TPnMD2 to TPnMD0 = 100)
• Set compare register.
(TPnCCR0, TPnCCR1)
Enable timer operation (TPnCE = 1)
→ Transfer value of TPnCCRm
register to CCRm buffer register
INTTPnCC1 occurs
16-bit counter matches
CCR1 buffer register.
TOPn1 outputs low level.
16-bit counter matches
CCR0 buffer register.
INTTPnCC0 occurs
Clear and start 16-bit counter.
TOPn1 outputs high level.
Remark n = 0 to 3
m = 0, 1
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(2) Operation flowchart of PWM mode
(a) Change of pulse width during operation
When change of PWM waveform during operation, please write to TPnCCR1 register at last. After write to
TPnCCR1 register, when write to TPnCCR0 register again, please rewrite after detection of INTTPnCC1
signal.
Figure 7-14. Flowchart of Basic Operation in PWM Mode (2/2)
(b) When values of TPnCCR0 and TPnCCR1 registers are rewritten during timer operation
START
Initial setting
• Select clock.
(TPnCTL0: TPnCKS2 to TPnCKS0)
• Set PWM mode.
(TPnCTL1: TPnMD2 to TPnMD0 = 100)
• Set compare register.
(TPnCCR0, TPnCCR1)
Enable timer operation (TPnCE = 1)
→ Transfer value of TPnCCRm
register to CCRm buffer register
16-bit counter matches TPnCCR1.
INTTPnCC1 occurs
TOPn1 outputs low level.
16-bit counter matches TPnCCR0.
INTTPnCC0 occurs
Clear and start 16-bit counter.
TOPn1 outputs high level.
<1>
<2>
Rewrite TPnCCR0.
16-bit counter matches
CCR1 buffer register.
INTTPnCC1 occurs
Note
TOPn1 outputs low level.
Reload is enabled
INTTPnCC0 occurs
Rewrite TPnCCR1.
<3>
• CCR0 buffer register matches 16-bit
counter.
• Clear and start 16-bit counter.
• Value of TPnCCRm is reloaded to
CCRm buffer register.
Note The timing of <2> may differ depending on the rewrite timing of <1> and <3> and the value of TPnCCR1, but
make sure that <3> comes after <1>.
Remark n = 0 to 3
m = 0, 1
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Figure 7-15. Timing of Basic Operation in PWM Mode (1/2)
(a) When rewriting value of TPnCCR1
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D00
D00
D00
D00
D11
16-bit
counter
D10
D10
D12
D00
TPnCCR0
CCR0 buffer
register
0000H
0000H
D00
TPnCCR1
D10
D11
D12
D13
CCR1 buffer
register
D10
D11
D12
D13
TOPn1
TOPn0
Remarks 1. D00:
Set value of TPnCCR0 register (0000H to FFFFH)
D10, D11, D12, D13: Set value of TPnCCR1 register (0000H to FFFFH)
2. Duty of TOPn1 output = (set value of TPnCCR1 register +1)/(Set value of TP0CCR0 register)
Cycle of TOPn1 output = (Set value of TPnCCR0 register +1)×(Count clock cycle)
Toggle width of TOPn0 output = (Set value of TPnCCR0 register + 1) × (Count clock period)
3. n = 0 to 3
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Figure 7-15. Timing of Basic Operation in PWM Mode (2/2)
(b) When rewriting values of TPnCCR0 and TPnCCR1
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D00
D01
D01
D02
16-bit
counter
D11
D11
D12
D10
D00
D01
D02
D03
TPnCCR0
Note
CCR0 buffer
register
0000H
0000H
D
00
D
01
D02
D03
Same value write
TPnCCR1
D
10
D11
D12
D12
Note
CCR1 buffer
register
D
10
D
11
D12
D12
TOPn1
TOPn0
Note No value is reloaded because the TPnCCR1 register is not rewritten.
Remarks 1. D00, D01, D02, D03: Set value of TPnCCR0 register (0000H to FFFFH)
D10, D11, D12, D13: Set value of TPnCCR1 register (0000H to FFFFH)
2. Duty of TOPn1 output = (set value of TPnCCR1 register +1)/(Set value of TP0CCR0 register)
Cycle of TOPn1 output = (Set value of TPnCCR0 register +1)×(Count clock cycle)
Toggle width of TOPn0 output = (Set value of TPnCCR0 register + 1) × (Count clock cycle)
3. n = 0 to 3
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is
FFFFH, the INTTPnCC1 signal is generated periodically.
Count clock
FFFF
0000
D00 − 1
D00
0000
0001
D
00 − 1
D00
0000
16-bit counter
TPnCE bit
D
00
D
00
D
00
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
0000H
0000H
0000H
Remark n = 0 to 8
To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register.
If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
FFFF
0000
D00 − 1
D00
0000
0001
D00 − 1
D00
0000
16-bit counter
TPnCE bit
D
00
D
00
D
00
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D00 + 1
D00 + 1
D00 + 1
Remark n = 0 to 8
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7.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101)
In the free-running mode, the 16-bit counter free-runs, and the bit that selects the capture or compare register
function can be select by the setting of the TPnCCS1 and TPnCCS0 bits.
Setting of the TPnCCS1 and TPnCCS0 bits of the TPnOPT0 register is valid only in the free-running mode.
TPnCCS1
Operation
0
1
TPnCCR1 register is used as compare register.
TPnCCR1 register is used as capture register.
TPnCCS0
Operation
0
1
TPnCCR0 register is used as compare register.
TPnCCR0 register is used as capture register.
• When TPnCCR1 register is used as compare register
When the value of the 16-bit counter matches the value of the CCR0 buffer register in the free-running mode,
an interrupt is generated.
TPnCCR1 register is enabled for write operation when TPnCE=1. Any data is set to TPnCCR1 register by
anytime write, data is translated to CCR1 buffer register, and data become comparison value with value of the
16 bit counter.
If timer output (TOPn0) is enabled, TOPn0 produces a toggle output when the value of the 16-bit counter
matches the value of the CCR0 buffer register.
• When TPnCCR1 register is used as capture register
The value of the 16-bit counter is stored in the TPnCCR1 register when the edge of the TIPn1 pin is detected.
• When TPnCCR0 register is used as compare register
When the value of the 16-bit counter matches the value of the CCR1 buffer register in the free-running mode,
an interrupt is generated.
TPnCCR0 register is enabled for write operation when TPnCE=1. Any data is set to TPnCCR0 register by
anytime write, data is translated to CCR1 buffer register, and data become comparison value with value of the
16 bit counter.
If timer output (TOPn0) is enabled, TOPn0 produces a toggle output when the value of the 16-bit counter
matches the value of the CCR0 buffer register.
• When TPnCCR0 register is used as capture register
The value of the 16-bit counter is stored in the TPnCCR0 register when the edge of the TIPn0 pin is detected.
Caution: External event count input as count clock (TPnCTRL.TPnEEE=1), TPnCCR0 register can not
to use as capture register.
Remark: Using TPnCCR0 and TPnCCR1 register as a compare register, the written operation at timer
operation (TPnCE = 1) refer to 7. 5. 1 (1) Anytime write.
Caution: At free running mode, count clear operation is not used by compare register matches.
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Figure 7-16. Flowchart of Basic Operation in Free-Running Mode
START
Initial setting
• Select clock.
(TPnCTL0: TPnCKS2 to TPnCKS0)
• Set free-running mode.
(TPnCTL1: TPnMD2 to TPnMD0 = 101)
Set TPnCCS1 and TPnCCS0.
TPnCCS1 = 0
TPnCCS0 = 0
TPnCCS1 = 0
TPnCCS0 = 1
TPnCCS1 = 1
TPnCCS0 = 0
TPnCCS1 = 1
TPnCCS0 = 1
Enable timer operation
Set detection of edge of
Set detection of edge of
Set detection of edge of
(TPnCE = 1)
TIPn0 (TPnIS1, TPnIS0).
TIPn1 (TPnIS3, TPnIS2).
TIPn1 and TIPn0
→ Transfer values of
TPnCCR0 and TPnCCR1
to CCR0 buffer register
and CCR1 buffer register
(TPnIS3 to TPnIS0).
Enable timer operation
(TPnCE = 1)
Enable timer operation
(TPnCE = 1)
Enable timer operation
(TPnCE = 1)
→ Transfer values of
TPnCCR1 to CCR1
buffer register
→ Transfer values of
TPnCCR0 to CCR0
buffer register
Edge of TIPn1 is detected.
Value of 16-bit counter is
captured to TPnCCR1.
CCR1 buffer
register matches
16-bit counter.
CCR1 buffer
register matches
16-bit counter.
Edge of TIPn1 is detected.
Value of 16-bit counter is
captured to TPnCCR1.
Edge of TIPn0 is detected.
Value of 16-bit counter is
captured to TPnCCR0.
CCR0 buffer
register matches
16-bit counter.
Edge of TIPn0 is detected.
Value of 16-bit counter is
captured to TPnCCR0.
CCR0 buffer
register matches
16-bit counter.
16-bit counter
overflows.
16-bit counter
overflows.
16-bit counter
overflows.
16-bit counter
overflows.
Remark n = 0 to 3
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(1) When TPnCCS1 = 0 and TPnCCS0 = 0 (compare function)
When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the
free-running mode until TPnCE is cleared to 0. If a value is written to the TPnCCR0 and TPnCCR1 registers in
this mode, it is transferred to the CCR0 and CCR1 buffer registers (anytime write). Even if a one-shot pulse
trigger is input in this mode, a one-shot pulse is not generated. If TPnOEm is set to 1, TOPnm produces a
toggle output when the value of the 16-bit counter matches the value of the CCRm buffer register.
Remark n = 0 to 3
m = 0, 1
Figure 7-17. Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 0,TPnCCS0 = 0)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D01
D11
D11
16-bit
counter
D00
D00
D10
TPnCCR0
D00
D01
CCR0 buffer
register
0000H
0000H
D
00
D
01
INTTPnCC0
match interrupt
TPnCCR1
D10
D11
CCR1 buffer
register
D10
D11
INTTPnCC1
match interrupt
TOPn0
TOPn1
INTTPnOV
TPnOVF
Clear by writing 0 to TPnOVF
Clear by writing 0 to TPnOVF
Remarks 1. D00, D01: Set value of TPnCCR0 register (0000H to FFFFH)
D10, D11: Set value of TPnCCR1 register (0000H to FFFFH)
2. Toggle width of TOPn0 output = (Set value of TPnCCR0 register) × (Count clock cycle)
Toggle width of TOPn1 output = (Set value of TPnCCR1 register)
3. TOPnm output goes high when counting is started.
4. n = 0 to 3
m = 0, 1
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(2) When TPnCCS1 = 1 and TPnCCS0 = 1 (capture function)
When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the
free-running mode until TPnCE is cleared to 0. The value captured by the capture trigger is written to the
TPnCCR0 and TPnCCR1 registers.
Capturing close to an overflow (FFFFH) is judged using the overflow flag (TPnOVF).
However, if the interval of the capture trigger is such that the overflow occurs twice (two or more cycles of free-
running); the TPnOVF flag cannot be used for judgment.
Figure 7-18. Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 1,TPnCCS0 = 1)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D10
D02
16-bit
D12
counter
D00
D01
D11
D03
TIPn0
TPnCCR0
TIPn1
0000H
D00
D01
D02
D03
TPnCCR1
0000H
D10
D11
D12
INTTPnCC0
match interrupt
INTTPnCC1
match interrupt
INTTPnOV
TOPn0
L
L
TOPn1
Remarks 1. D00, D01, D02, D03: Value captured to TPnCCR0 register (0000H to FFFFH)
D10, D11, D12: Value captured to TPnCCR1 register (0000H to FFFFH)
2. TIPn0: Rising edge is detected (TPnIS1, TPnIS0 = 01).
TIPn1: Falling edge is detected (TPnIS3, TPnIS2 = 10).
3. n = 0 to 3
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(3) When TPnCCS1 = 0 and TPnCCS0 = 1
When TPnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the
free-running mode until TPnCE is cleared to 0. The TPnCCR1 register is used as a compare register. As an
interval function, an interrupt signal is output when the value of the 16-bit counter matches the set value of the
TPnCCR1 register. If TPnOE1 is set to 1, TOPn1 produces a toggle output when the value of the 16-bit
counter matches the set value of the TPnCCR1 register.
Figure 7-19. Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 0,TPnCCS0 = 1)
(TPnOE0 = 1, TPnOE1 = 1, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
D02
D00
D03
D10
16-bit
counter
D12
D01
D11
D11
TIPn0
TPnCCR0
0000H
D00
D01
D02
D03
INTTPnCC0
match interrupt
TPnCCR1
D10
D
11
11
D
12
12
CCR1 buffer
register
0000H
D10
D
D
INTTPnCC1
match interrupt
INTTPnOV
TOPn0
L
TOPn1
Remarks 1. D00, D01, D02, D03: Value captured to TPnCCR0 register (0000H to FFFFH)
D10, D11, D12: Value captured to TPnCCR1 register (0000H to FFFFH)
2. TIPn0: Falling edge is detected (TPnIS1, TPnIS0 = 10).
3. n = 0 to 3
(4) Overflow flag
When the counter overflows from FFFFH to 0000H in the free-running mode, the overflow flag (TPnOVF) is set
to 1, and an overflow interrupt (INTTPnOV) is generated.
After generation of the overflow interrupt (INTTPnOV), be sure to check if the overflow flag (TPnOVF) is set to
1.
The overflow flag is cleared by the CPU by writing 0 to it.
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7.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110)
In the pulse width measurement mode, free-running counting is performed. The value of the 16-bit counter is
captured to capture register 0 (TPnCCR0) when both the rising and falling edges of the TIPn0 pin are detected, and
the 16-bit counter is cleared to 0000H. In this way, the external input pulse width can be measured.
To measure a long pulse width that exceeds the overflow of the 16-bit counter, use the overflow flag for detection.
For measurement a pulse width that causes overflow to occur twice or more, please count number with overflow
interrupt, etc. When the edge of the TIPn1 pin is detected, the value of the 16-bit counter is stored in capture register
1 (TPnCCR1), and the 16-bit counter is cleared.
Caution In the pulse width measurement mode, select the internal clock (TPnEEE of the TPnCTL1 register =
0) as the count clock.
Figure 7-20. Flowchart of Basic Operation in Pulse Width Measurement Mode
START
Initial setting
· Select clock.
(TPnCTL0: TPnCKS2 to TPnCKS0)
· Set pulse width measurement mode.
(TPnCTL1: TPnMD2 to TPnMD0 = 110)
· Set compare register.
(TPnCCR0, TPnCCR1)
Set edge detection of TIPn1/TIPn0Note
(TPnIS3 to TPnIS0)
.
Enable timer operation (TPnCE = 1).
Input rising edge of pulse to TIPnm.
Capture value to TPnCCRm.
Clear and start 16-bit counter.
Input falling edge of pulse to TIPnm.
Capture value to TPnCCRm.
Clear and start 16-bit counter.
Note An external pulse can be input from either TIPn0 or TIPn1. Only one of them can be used. Specify that both
the rising and falling edges are detected. Specify that the input edge of an external pulse input that is not
used is not detected.
Remark n = 0 to 3
m = 0, 1
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Figure 7-21. Timing of Basic Operation in Pulse Width Measurement Mode
(TPnOE0 = 0, TPnOE1 = 0, TPnOL0 = 0, TPnOL1 = 0)
TPnCE = 1
FFFFH
FFFFH
D01
D03
D02
D00
16-bit
counter
TIPn0
TPnCCR0
INTTPnCC0
TPnOVF
0000H
D00
D01
D02
D
03
Cleared
by writing 0
from CPU
INTTPnOV
Remarks 1. D00, D01, D02, D03: Value captured to TPnCCR0 register (0000H to FFFFH)
2. TIPn0: Both the rising and falling edges are detected (TPnIS1, TPnIS0 = 11).
3. n = 0 to 34.
4. Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an
overflow interrupt request signal (INTTPnOV) is generated at the next count clock, and the counter is
cleared to 0000H and continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is
also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TPnOVF bit set (1) count + Captured value) × Count clock cycle
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7.6 Timer Synchronized Operation Function
Timer P and timer Q have a timer synchronized operation function (tuned operation mode).
The timers that can be synchronized are listed in Table 7-3.
Table 7-3. Tuned Operation Mode of Timers
Master Timer
TMP0
Slave Timer
TMP1
TMP3
TMQ2
–
TMQ0
–
TMP2
TMQ1
Cautions 1. The tuned operation mode is enabled or disabled by the TPmSYE bit of the TPmCTL1 register
and TQnSYE bit of the TQnCTL1 register. For TMP2, either or both TMP3 and TMQ0 can be
specified as slaves.
2. Set the tuned operation mode using the following procedure.
<1> Set the TPmSYE bit of the TPmCTL1 register and the TQnSYE bit of the TQnCTL1
register of the slave timer to enable the tuned operation.
Set the TPmMD2 to TPmMD0 bits of the TPmCTL1 register and TQnMD2 to TQnMD0 bits
of the TQnCTL1 register of the slave timer to the free-running mode.
<2> Set the timer mode by using the TPnMD2 to TPnMD0 bits of the TPnCTL1 register and
the TPnMD2 to TPnMD0 bits of the TQnCTL1 register.
At this time, do not set the TPnSYE bit of the TPnCTL1 register and the TQnSYE bit of
the TQnCTL1 register of the master timer.
<3> Set the compare register value of the master and slave timers.
<4> Set the TPmCE bit of the TPmCTL0 register and the TQnCE bit of the TQnCTL0 register of
the slave timer to enable operation on the internal operating clock.
<5> Set the TPnCE bit of the TPnCTL0 register and the TQnCE bit of the TQnCTL0 register of
the master timer to enable operation on the internal operating clock.
Remark n = 1, 3, m = 0, 2
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Tables 7-4 and 7-5 show the timer modes that can be used in the tuned operation mode (√: Settable, ×: Not
settable).
Table 7-4. Timer Modes Usable in Tuned Operation Mode
Master Timer
TMP0
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
√
√
√
√
√
√
×
×
√
TMP2
TMQ1
Table 7-5. Timer Output Functions
Tuned
Timer
Pin
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
Channel
Tuning OFF Tuning ON Tuning OFF Tuning ON Tuning OFF Tuning ON
Ch0
TMP0
TOP00
TOP01
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
TOQ00
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
←
←
←
←
←
←
←
←
←
←
Toggle
PWM
←
←
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
←
←
(master)
TMP1
Toggle
PWM
PWM
←
←
(slave)
←
Ch1
TMP2
Toggle
PWM
PWM
←
←
(master)
←
TMP3
Toggle
PWM
PWM
←
←
(slave)
←
Ch1
Ch2
TMQ0
(slave)
Toggle
PWM
PWM
←
Toggle
Triangular
wave PWM
Toggle
N/A
N/A
TOQ01 to TOQ03
TMQ1
TOQ10
PPG
PPG
←
←
Toggle
PWM
←
←
←
←
(master)
TOQ11 to TOQ13
Triangular
wave PWM
Toggle
TMQ2
(slave)
TOQ20
PPG
PPG
←
←
Toggle
PWM
←
←
Triangular
wave PWM
←
TOQ21 to TOQ23
Triangular
wave PWM
Remark The timing of transmitting data from the compare register of the master timer to the compare register of
the slave timer is as follows.
PPG: CPU write timing
Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0
and TOQm0 (n = 0 to 3, m = 0 to 2)
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Figure 7-22. Tuned Operation Image (TMP2,TMP3,TMQ0)
Unit operation
Tuned operation
TMP2
TMP3
TMQ0
TMP2 (master) + TMP3 (slave) + TMQ0 (slave)
16-bit timer/counter
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOP21 (PWM output)
16-bit capture/compare
TOP21 (PWM output)
16-bit capture/compare
16-bit capture/compare
TOP30 (PWM output)
TOP31 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOQ00 (PWM output)
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
TOP31 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
Five PWM outputs are available
when PWM is operated as a single unit.
Seven PWM outputs are available when
PWM is operated in tuned operation mode.
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Figure 7-23. Basic Operation Timing of Tuned PWM Function (TMP2,TMP3,TMQ0)
FFFFH
D00
D00
D70
D70
D60
D60
TMP2
16-bit
counter
D50
D50
D40
D40
D30
D30
D20
D20
D10
D10
0000H
TP2CE
TP3CE
TQ0CE
TP2CCR0
TP2CCR1
TP3CCR0
TP3CCR1
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
D00
D10
D20
D30
D40
D50
D60
D70
INTTP2CC0
match interrupt
INTTP2CC1
match interrupt
INTTP3CC0
match interrupt
INTTP3CC1
match interrupt
INTTQ0CC0
match interrupt
INTTQ0CC1
match interrupt
INTTQ0CC2
match interrupt
INTTQ0CC3
match interrupt
TOP20
TOP21
TOP30
TOP31
TOQ00
TOQ01
TOQ02
TOQ03
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7.7 Selector Function
In the V850ES/Fx2, the TIP input/RXDA input and the TIP input/TSOUT signal can be used to select the capture
trigger input of TMP.
By using this function, the following is possible.
• The TIP00 and TIP01 input signals can be selected from the port/timer alternate-function pins (TIP00 and TIP01
pins) and the TSOUT signal of the CAN controller.
→ If the TSOUT signal of CAN0 or CAN1 is selected, the time stamp function of the CAN controller can be used.
• The TIP10 and TIP11 input signals of TMP1 can be selected from the port/timer alternate-function pins (TIP10
and TIP11 pins) and the UARTA reception alternate-function pins (RXDA0 and RXDA1). The TIP30 and TIP31
input signals of TMP3 can be selected from a port/timer alternate-function pin (TIP30 and TIP31 pins) and the
UARTA reception alternate function pin (RXDA2 and RXDA3).
→ When the RXDA0, RXDA1, RXDA2 or RXDA3 signal of UART0, UART1, UART2 or UART3 is selected, the
LIN reception transfer rate and baud rate error of UARTA can be calculated.
Cautions 1. When using the selector function, set the capture trigger input of TMP before connecting
the timer.
2. When setting the selector function, first disable the peripheral I/O to be connected
(TMP/UARTA or TMP/CAN controller).
The capture input for the selector function is specified by the following register.
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(1) Selector operation control register 0 (SELCNT0)
The SELCNT0 register is an 8-bit register that selects the capture trigger for TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: FFFFF308H
(i) V850ES/FE2, V850ES/FF2, V850ES/FG2
7
0
6
0
5
0
4
3
2
1
0
0
SELCNT0
ISEL04
ISEL03
ISEL02
ISEL00
(ii) V850ES/FJ2: µPD70F3237
7
6
0
5
4
3
2
1
0
SELCNT0
0
ISEL05
ISEL04
ISEL03
ISEL02
ISEL01
ISEL00
(iii) V850ES/FJ2: µPD70F3238, µPD70F3239
7
6
5
4
3
2
1
0
SELCNT0
0
ISEL06
ISEL05
ISEL04
ISEL03
ISEL02
ISEL01
ISEL00
ISEL06
Selection of TIP31 input signal (TMP3)
Selection of TIP30 input signal (TMP3)
Selection of TIP11 input signal (TMP1)
Selection of TIP10 input signal (TMP1)
Selection of TIP01 input signal (TMP0)
0
1
TIP31 pin input
RXDA3 pin input
ISEL05
0
1
TIP30 pin input
RXDA2 pin input
ISEL04
0
1
TIP11 pin input
RXDA1 pin input
ISEL03
0
1
TIP10 pin input
RXDA0 pin input
ISEL02Note
0
1
Signal selected by ISEL01 bit
INTTM0EQ0 interrupt of TMM0
ISEL01
Selection of TIP01 input signal (TMP0)
0
1
TIP01 pin input
TSOUT signal of CAN1
ISEL00
Selection of TIP00 input signal (TMP0)
0
1
TIP00 pin input
TSOUT signal of CAN0
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Note Use the INTTM0EQ0 interrupt signal as the TIP01 input signal in the following range.
TMM operation clock cycle ≥ TMP operation clock cycle × 4
Cautions 1. To set the ISEL06 to ISEL00 bits to 1, set the corresponding pin in the capture input mode.
2. Set TMP0 and CAN0 after prohibiting operating when you set the ISEL00 bit.
Set TMP0 and CAN1 after prohibiting operating when you set the ISEL01 bit.
Set TMP0 and TMM0 after prohibiting operating when you set the ISEL02 bit.
Set TMP1 and UARTA0 after prohibiting operating when you set the ISEL03 bit.
Set TMP1 and UARTA1 after prohibiting operating when you set the ISEL04 bit.
Set TMP3 and UARTA2 after prohibiting operating when you set the ISEL05 bit.
Set TMP3 and UARTA3 after prohibiting operating when you set the ISEL06 bit.
(2) Selector operation control register 1 (SELCNT1)
The SELCNT1 register is an 8-bit register that selects the capture trigger for TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
This register is incorporated only in the µPD70F3238 and µPD70F3239.
After reset: 00H
R/W
Address: FFFFF30AH
(i) V850ES/FJ2: µPD70F3238, µPD70F3239
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SELCNT1
ISEL11
ISEL10
ISEL11Note
Selection of TIP21 input signal (TMP2)
0
1
TIP21 pin input
TSOUT signal of CAN3
ISEL10Note
Selection of TIP20 input signal (TMP2)
0
1
TIP20 pin input
TSOUT signal of CAN2
Note The µPD70F3237 does not have the CAN3 and CAN2 functions. Fix the ISEL11
and ISEL10 bits of these products to 0.
Cautions 1. To set the ISEL11 and ISEL10 bits to 1, set the corresponding pin in
the capture input mode.
2. Set TMP2 and CAN2 after prohibiting operating when you set the
ISEL10 bit. Set TMP2 and CAN3 after prohibiting operating when you set
the ISEL11 bit.
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7. 8 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may
be captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input until operation start of count
clock after the TPnCE bit is set to 1.
(a)Free running timer mode
FFFFH
16 bit counter
0000H
Count clock
Sampling clock
TPnCCR0 register 0000H
TPnCE bit
FFFFH
0002H
TIPn0 pin input
Capture trigger
Capture trigger input
(b)Pulse mode
FFFFH
16 bit counter
0000H
Count clock
Sumpling clock
TPnCCR0 register 0000H
TPnCE bit
FFFFH
0001H
TIPn0 pin input
Capture trigger
Caputure torigger input
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(2) Notes on rewriting the TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
D1
16-bit counter
0000H
D2
D2
D2
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
D1
D2
External event
count signal
interval (1)
External event count signal External event
interval (NG)
(10000H + D
count signal
interval (2)
2
+ 1)
(D1
+ 1)
(D2 + 1)
Remark n = 0 to 3
If the value of the TPnCCR0 register is changed from D1 to D2 while the count value is greater than D2 but
less than D1, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has
been rewritten. Consequently, the value that is compared with the 16-bit counter is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH,
overflows, and then counts up again from 0000H. When the count value matches D2, the INTTPnCC0 signal is
generated.
Therefore, the INTTPnCC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2 + 1)
times” originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.
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(3) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit
when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
L
L
set signal
set signal
0 write signal
Register
0 write signal
Overflow flag
(TPnOVF bit)
Read
Write
access signal
Overflow flag
(TPnOVF bit)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
Overflow
set signal
0 write signal
0 write signal
Register
Overflow flag
(TPnOVF bit)
Read
Write
access signal
Overflow flag
(TPnOVF bit)
H
Remark n = 0 to 3
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.
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The V850ES/FE2, V850ES/FF2, V850ES/FG2, and V850ES/FJ2 include 16-bit timer/event counter Q. The number
of channels of timer Q (TMQ) differs depending on the product.
Table 8-1. Number of Channels of Timer Q
Product
V850ES/FE2
Number of Channels
1 (TMQ0)
V850ES/FF2
V850ES/FG2
V850ES/FJ2
2 (TMQ0, TMQ1)
3 (TMQ0, TMQ1, TIMQ2)
8.1 Features
Timer Q (TMQ) is a 16-bit timer/event counter that can be used in various ways.
TMQ can perform the following operations.
• PWM output
• Interval timer
• External event counter (operation disabled when clock is stopped)
• One-shot pulse output
• Pulse width measurement function
• Triangular wave PWM output
• Timer synchronized operation function
• External trigger pulse output function
• Free-running function
8.2 Functional Outline
• Capture trigger input signal × 4
• External trigger input signal × 1
• Clock selection × 8
• External event count input × 1
• Readable counter × 1
• Capture/compare reload register × 4
• Capture/compare match interrupt × 4
• Timer output (TOQn0 to TOQn3) × 4
Remark n = 0 (V850ES/FE2, V850ES/FF2)
n = 0,1 (V850ES/FG2)
n = 0 to 2 (V850ES/FJ2)
This chapter explains the case where n = 0 to 2.
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8.3 Configuration
TMQ consists of the following hardware.
Table 8-2. Configuration ofTMQ0 to TMQ2
Item
Timer register
Registers
Configuration
16-bit counter
TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
TMQn counter read buffer register (TQnCNT)
CCR0 buffer register to CCR3 buffer register
Timer inputs
4 (TIQn0Note to TIQn3)
Timer outputs
Control registers
2 (TOQn0 to TOQn3)
TMQn timer control registers 0, 1 (TQnCTL0, TQnCTL1)
TMQn timer dedicated I/O control registers 0 to 2 (TQnIOC0 to TQnIOC2)
TMQn timer option register 0 (TQnOPT0)
TIQnm pin noise elimination control register (QnmNFC)
Note TIQn0 functions alternately as a capture trigger input signal, external trigger input signal, and external event
count input signal.
Remark n = 0 to 2, m = 0 to 3
The pins of TMQ function alternately as port pins. For how to set the alternate function, refer to the description of
the registers in CHAPTER 4 PORT FUNCTIONS.
Table 8-3. TMQ Pin List
Pin Name
TIQ00
Alternate-Function Pin
P53/KR3/TOQ00/DDO
P50/KR0/TOQ01
P51/KR1/TOQ02
P52/KR2/TOQ03/DDI
P95/TOQ10
I/O
Input
Function
External event/clock input (TMQ0)
TIQ01
TIQ02
TIQ03
TIQ10
External event/clock input (TMQ1)
External event/clock input (TMQ2)
Timer output (TMQ0)
TIQ11
P92/TOQ11
TIQ12
P93/TOQ12
TIQ13
P94/TOQ13
TIQ20
P610/TOQ20
TIQ21
P611/TOQ21
TIQ22
P612/TOQ22
TIQ23
P613/TOQ23
TOQ00
TOQ01
TOQ02
TOQ03
TOQ10
TOQ11
TOQ12
TOQ13
TOQ20
TOQ21
TOQ22
TOQ23
P53/KR3/TIQ00/DDO
P50/KR0/TIQ01
P51/KR1/TIQ02
P52/KR2/TIQ03/DDI
P95/TIQ10
Output
Timer output (TMQ1)
P92/TIQ11
P93/TIQ12
P94/TIQ13
P610/TIQ20
Timer output (TMQ2)
P611/TIQ21
P612/TIQ22
P613/TIQ23
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Figure 8-1. Block Diagram of Timer Q
Internal bus
TQnCTL0
TQnIOC2
TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnESS1 TQnESS0 TQnETS1 TQnETS0
TQnCE
f
XX
f
f
f
XX/2
XX/4
XX/8
TQnCCR0
f
f
f
XX/16
XX/32
XX/64
CCR0 buffer
register
TQnCNT
Load
Clear
INTTQnCC0
f
XX/128
TQnCE
Edge
detector
Counter control
16-bit counter
INTTQnOV
CCR1 buffer
register
Trigger
control
INTTQnCC1
Load
Edge
detector
Edge
TQnCCR1
16-bit counter
TIQn0
TIQn1
TIQn2
TIQn3
detector
Edge
detector
CCR2 buffer
register
INTTQnCC2
Load
Edge
detector
TQnCCR2
16-bit counter
Edge
detector
CCR3 buffer
register
INTTQnCC3
Load
TQnCCR3
TOQn0
TOQn1
TOQn2
TOQn3
Output
controller
Capture/compare
selection function
INTTQnOV
TQnIS7 to TQnIS0
TQnIOC1
TQnSYE TQnEST TQnEEE TQnMD2 TQnMD1 TQnMD0
TQnCTL1
TQnCCS4 to TQnCCS0 TQnOVF TQnOL3 to TQnOL0 TQnOE3 to TQnOE0
TQnOPT0
TQnIOC0
Internal bus
Remark n = 0 to 2
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(1) TMQn capture/compare register 0 (TQnCCR0)
The TQnCCR0 register is a 16-bit register that has a capture function and a compare function.
A capture register or a compare register behavior can be set by the setting of TQnCCS0 bit only in the free-
running mode.
In the pulse width measurement mode, this register functions only as a capture register.
In all the modes other than the free-running mode and pulse width measurement mode, this register functions
as a compare register.
In the default status, the TQnCCR0 register functions as a compare register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
After reset: 0000H R/W
Address: TQ0CCR0: FFFFF546H, TQ1CCR0: FFFFF616H,
TQ2CCR0: FFFFF626H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TQnCCR0
(n = 0 to 2)
• When used as compare register
TQnCCR0 can be rewritten when TQnCE = 1.
Each operation mode and capture/compare register functions and the method of writing the compare
register are as follows.
TMQ Operation Mode
Method of Writing TQnCCR0 Register
PWM output mode, external trigger pulse output Reload
mode, or triangular wave PWM mode
Free-running mode, external event count mode,
one-shot pulse mode, or interval timer mode
Anytime write
Pulse width measurement mode
Cannot be written because used only as
capture register
• When used as capture register
The count value is stored in TQnCCR0 on detection of the edge of the capture trigger (TIQn0) input.
Caution: At subclock operated and at main clock stopped, the access to TQnCCR0 register is
prohibited. For details, refer to 3. 4. 10（2）
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(2) TMQn capture/compare register 1 (TQnCCR1)
The TQnCCR1 register is a 16-bit register that has a capture function and a compare function.
A capture register or a compare register behavior can be specified by setting the TQnCCS1 bit of the
TQnOPT0 register only in the free-running mode.
In the pulse width measurement mode, this register functions only as a capture register.
In all the modes other than the free-running mode and pulse width measurement mode, this register functions
as a compare register.
Reset input clears this register to 0000H.
After reset: 0000H R/W
Address: TQ0CCR1: FFFFF548H, TQ1CCR1: FFFFF618H,
TQ2CCR1: FFFFF628H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TQnCCR1
(n = 0 to 2)
• When used as compare register
TQnCCR1 can be rewritten when TQnCE = 1.
Each operation mode and capture/compare register functions and the method of writing the compare
register are as follows.
TMQ Operation Mode
Method of Writing TQnCCR1 Register
PWM output mode, external trigger pulse output Reload
mode, or triangular wave PWM mode
Free-running mode, external event count mode,
one-shot pulse mode, or interval timer mode
Anytime write
Pulse width measurement mode
Cannot be written because used only as
capture register
• When used as capture register
The count value is stored in TQnCCR1 on detection of the edge of the capture trigger (TIQn1) input.
Caution: At subclock operated and at main clock stopped, the access to TQnCCR1 register is
prohibited. For details, refer to 3. 4. 10（2）
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(3) TMQn capture/compare register 2 (TQnCCR2)
The TQnCCR2 register is a 16-bit register that has a capture function and a compare function.
A capture register or a compare register behavior can be specified by setting the TQnCCS2 bit of the
TQnOPT0 register only in the free-running mode.
In the pulse width measurement mode, this register functions only as a capture register.
In all the modes other than the free-running mode and pulse width measurement mode, this register functions
as a compare register.
In the default status, the TQnCCR2 register functions as a compare register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
After reset: 0000H R/W
Address: TQ0CCR2: FFFFF54AH, TQ1CCR2: FFFFF61AH,
TQ2CCR2: FFFFF62AH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TQnCCR2
(n = 0 to 2)
• When used as compare register
TQnCCR2 can be rewritten when TQnCE = 1.
Each operation mode and capture/compare register functions and the method of writing the compare
register are as follows.
TMQ Operation Mode
Method of Writing TQnCCR2 Register
PWM output mode, external trigger pulse output Reload
mode, or triangular wave PWM mode
Free-running mode, external event count mode,
one-shot pulse mode, or interval timer mode
Anytime write
Pulse width measurement mode
Cannot be written because used only as
capture register
• When used as capture register
The count value is stored in TQnCCR2 on detection of the edge of the capture trigger (TIQn2) input.
Caution: At subclock operated and at main clock stopped, the access to TQnCCR1 register is
prohibited. For details, refer to 3. 4. 10（2）
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(4) TMQn capture/compare register 3 (TQnCCR3)
The TQnCCR3 register is a 16-bit register that has a capture function and a compare function.
A capture register or a compare register can be specified by setting the TQnCCS3 bit of the TQnOPT0 register
only in the free-running mode.
In the pulse width measurement mode, this register functions only as a capture register.
In all the modes other than the free-running mode and pulse width measurement mode, this register functions
as a compare register.
In the default status, the TQnCCR3 register functions as a compare register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
After reset: 0000H R/W
Address: TQ0CCR3: FFFFF54CH, TQ1CCR3: FFFFF61CH,
TQ2CCR3: FFFFF62CH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TQnCCR3
(n = 0 to 2)
• When used as compare register
TQnCCR3 can be rewritten when TQnCE = 1.
Each operation mode and capture/compare register functions and the method of writing the compare
register are as follows.
TMQ Operation Mode
Method of Writing TQnCCR3 Register
PWM output mode, external trigger pulse output Reload
mode, or triangular wave PWM mode
Free-running mode, external event count mode,
one-shot pulse mode, or interval timer mode
Anytime write
Pulse width measurement mode
Cannot be written because used only as
capture register
• When used as capture register
The count value is stored in TQnCCR3 on detection of the edge of the capture trigger (TIQn3) input.
Caution: At subclock operated and at main clock stopped, the access to TQnCCR1 register is
prohibited. For details, refer to 3. 4. 10（2）
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(5) TMQn counter read buffer register (TQnCNT)
The TQnCNT register is a read buffer register that can read the value of the 16-bit counter.
This register is read-only, in 16-bit units.
Reset input clears this register to FFFFH.
When TQnCE bit = 0, the TQnCNT register is 000H. At this time if TQnCNT register is read, the value of 16-bit
counter is not read and 0000H is read as it is.
If this register is read, the count value of 16-bit counter can be read when TQnCE = 1.
After reset: FFFFH
R
Address: TQ0CNT: FFFFF54EH, TQ1CNT: FFFFF61EH,
TQ2CNT: FFFFF62EH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TQnCNT
(n = 0 to 2)
Caution: At subclock operated and at main clock stopped, the access to TQnCCR1 register is
prohibited. For details, refer to 3. 4. 10（2）
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8.4 Control Registers
(1) TMQn control register 0 (TQnCTL0)
The TQnCTL0 register is an 8-bit register that controls the operation of timer Q.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register of default value to 00H.
Rewriting the TQnCTL0 register is prohibited while operating (TQnCE = 1). However, only the TQnCE bit can
be rewritten at any time.
(1/2)
After reset: 00H
R/W
Address: TQ0CTL0: FFFFF540H, TQ1CTL0: FFFFF610H,
TQ2CTL0: FFFFF620H
7
6
0
5
0
4
0
3
0
2
1
0
TQnCTL0
TQnCE
TQnCKS2 TQnCKS1 TQnCKS0
(n = 0 to 2)
TQnCE
Control of operation of timer Qn
0
1
Disable internal operating clock operation (asynchronously reset TMQn).
Enable internal operating clock operation.
The TQnCE bit controls the internal operating clock and asynchronously resets TMQn. When this bit
is cleared to 0, the internal operating clock of TMQn is stopped (fixed to the low level), and TMQn is
asynchronously reset.
When the TQnCE bit is set to 1, the internal operating clock is enabled within 2 input clocks, and
TMQn counts up.
TQnCKS2 TQnCKS1 TQnCKS0
Selection of internal count clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
Cautions: 1. Set the TQnCKS2 to TQnCKS0 bits when TQnCE = 0. When the
TQnCE bit setting is changed from 0 to 1, the TQnCKS2 to
TQnCKS0 bits can be set at the same time.
2. Be sure to clear bit 3 to bit 6 to 0.
Remark
fXX: Main system clock frequency
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(2/2)
Resolution and Maximum Count time
Internal count clock Resolution [µs]
Maximum Count Time [ms]
fXX = 16 MHz
fXX = 20 MHz
0.050
fXX = 16 MHz
4.10
fXX = 20 MHz
3.28
fXX
0.0625
0.125
0.250
0.500
1.000
2.000
4.000
8.000
fXX/2
0.100
8.19
6.55
fXX/4
0.200
16.38
13.11
fXX/8
0.400
32.77
26.21
fXX/16
fXX/32
fXX/64
fXX/128
0.800
65.54
52.43
1.600
131.11
262.14
524.29
104.86
209.72
419.43
3.200
6.400
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(2) TMQn timer control register 1 (TQnCTL1)
The TQnCTL1 register is an 8-bit register that controls the operation of timer Q.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
(1/2)
After reset: 00H
R/W
Address: TQ0CTL1: FFFFF541H, TQ1CTL1: FFFFF611H,
TQ2CTL1: FFFFF621H
7
6
5
4
0
3
0
2
1
0
TQnCTL1 TQnSYE
TQnEST
TQnEEE
TQnMD2
TQnMD1
TQnMD0
(n = 0 to 2)
TQnSYE
Tuned operation mode enable
0
1
Independent operation mode (asynchronous operation mode)
Tuned operation mode (specification of slave operation)
In this mode, timer Q can operate in synchronization with a master timer.
Master timer
TMP2
Slave timer
TMP3
TMQ2
TMQ0
–
TMQ1
For the tuned operation mode, refer to 8.6 Timer Synchronized Operation Function.
TQnEST
Software trigger control
No operation
0
1
In one-shot pulse mode: One-shot pulse software trigger
In external trigger pulse output mode: Pulse output software trigger
The TQnEST bit functions as a software trigger in the one-shot pulse mode or external trigger pulse
output mode (this bit is invalid in any other mode). By setting TQnEST to 1 when TQnCE = 1, a
software trigger is issued. Therefore, be sure to set TQnEST to 1 when TQnCE = 1.
The TIQn0 pin is used for an external trigger. The read value of the TQnEST bit is always 0.
TQnEEE
Selection of count clock
Internal clock (clock selected by TQnCKS2 to TQnCKS0 bits)
External event count input (edge of input to TIQn0)
0
1
The valid edge is specified by the TQnEES1 and TQnEES0 bits when TQnEEE = 1 (External event
count input: TIQn0).
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(2/2)
TQnMD2
TQnMD1
TQnMD0
Selection of timer mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse mode
PWM mode
Free-running mode
Pulse width measurement mode
Triangular wave PWM mode
Cautions 1. Set the TQnEEE and TQnMD2 to TQnMD0 bits when TQnCE = 0 (the
same value can be written when TQnCE = 1). If these bits are
rewritten when TQnCE = 1, the operation cannot be guaranteed. If
these bits are rewritten by mistake, clear TQnCE to 0 and then set
them again.
2. The external event count input is selected regardless of the value of
the TQnEEE bit at an external event count mode.
3. Be sure to clear bits 3 and 4 to 0.
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(3) TMQn timer dedicated I/O control register 0 (TQnIOC0)
The TQnIOC0 register is an 8-bit register that controls the timer outputs.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TQ0IOC0: FFFFF542H, TQ1IOC0: FFFFF612H,
TQ2IOC0: FFFFF622H
7
6
5
4
3
2
1
0
TQnIOC0 TQnOL3
TQnOE3
TQnOL2
TQnOE2
TQnOL1
TQnOE1
TQnOL0
TQnOE0
(n = 0 to 2)
TQnOLm
Setting of TOQnm output level (m = 0 to 3)
0
1
Normal output
Inverted output
TQnOEm
0
Setting of TOQnm output (m = 0 to 3)
Disable timer output (TOQnm pin outputs low level when TQnOLm = 0, and high level
when TQnOLm = 1).
1
Enable timer output (TOQnm pin outputs pulses).
Cautions 1. Rewrite the TQnOL1, TQnOE1, TQnOL0, and TQnOE0 bits when
TQnCE = 0 (the same value can be written when TQnCE = 1). If these
bits are rewritten by mistake, clear TQnCE to 0 and then set them
again.
2. To enable the timer output, be sure to set the corresponding
alternate-function pins TQnIS7 to TQnIS0 of the TQnIOC1 register to
“Detect no edge” and invalidate the capture operation. Then set the
corresponding alternate-function port to output mode.
3. The output level of the TOQnm pin changes into the state of
TQnCE=0 and TQnOEm=0 if the TQnOLm bit is operated when the
pin is assumed to be a control output mode.
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(4) TMQn timer dedicated I/O control register 1 (TQnIOC1)
The TQnIOC1 register is an 8-bit register that controls the valid edge of the external input signals (TIQn0 to
TIQn3).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
(1/2)
After reset: 00H
R/W
Address: TQ0IOC1: FFFFF543H, TQ1IOC1: FFFFF613H,
TQ2IOC1: FFFFF623H
7
6
5
4
3
2
1
0
TQnIOC1
TQnIS7
TQnIS6
TQnIS5
TQnIS4
TQnIS3
TQnIS2
TQnIS1
TQnIS0
(n = 0 to 2)
TQnIS7
TQnIS6
Setting of valid edge of capture input (TIQn3)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TQnIS5
TQnIS4
Setting of valid edge of capture input (TIQn2)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TQnIS3
TQnIS2
Setting of valid edge of capture input (TIQn1)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TQnIS1
TQnIS0
Setting of valid edge of capture input (TIQn0)
0
0
1
1
0
1
0
1
Detect no edge (capture operation is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
Remark: Refer to the next page for the cautions.
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(2/2)
Cautions 1. Rewrite the TQnIS7 to TQnIS0 bits when TQnCE0 = 0 (the same value
can be written when TQnCE = 1). If these bits are rewritten by
mistake, clear TQnCE to 0 and then set them again.
2. The TQnIS7 to TQnIS0 bits are valid only in the free-running mode
and pulse width measurement mode. A capture operation is not
performed in any other mode.
3. To use the capture input, be sure to set the corresponding
alternate-function pins TQnOE3 to TQnOE0 of the TQnIOC register
to "Timer output prohibit" and be sure to set variable edge of
capture input. Then, set the corresponding alternate-function port
to input mode.
4. To use the external event count mode (TQnCTL1.TQ0EEE bit=1), be
sure to set TIQn0 capture input to "No edge detection" (TQnIS1, 0
bit=00b).
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(5) TMQn timer dedicated I/O control register 2 (TQnIOC2)
The TQnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIQn0) and external trigger input signal (TIQn0).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TQ0IOC2: FFFFF544H, TQ1IOC2: FFFFF614H,
TQ2IOC2: FFFFF624H
7
0
6
0
5
0
4
0
3
2
1
0
TQnIOC2
TQnEES1 TQnEES0 TQnETS1 TQnETS0
(n = 0 to 2)
TQnEES1 TQnEES0
Setting of valid edge of external event count input (TIQn0)
0
0
1
1
0
1
0
1
Detect no edge (external event count is invalid).
Detect rising edge.
Detect falling edge.
Detect both the edges.
TQnETS1 TQnETS0
Setting of valid edge of external trigger input (TIQn0)
Detect no edge (external trigger is invalid).
Detect rising edge.
0
0
1
1
0
1
0
1
Detect falling edge.
Detect both the edges.
Cautions 1. Rewrite the TQnEES1, TQnEES0, TQnETS1 and TQnETS0 bits when
TQnCE = 0 (the same value can be written when TQnCE = 1). If these
bits are rewritten by mistake, clear TQnCE to 0 and then set them
again.
2. The TQnEES1 and TQnEES0 bits are valid when TQnEEE = 1 or
when the external event count mode is set (TQnMD2 to TQnMD0 of
TIQnCTL1 register = 001).
3. When setting of the external trigger pulse output mode
(TQnCTL1.TQnMD2-0=010b) or the one-shot pulse output mode
(TQnCTL1.TQnMD2=011b) only, TQnETS1, TQnETS0 bits are
variable.
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(6) TMQn timer option register 0 (TQnOPT0)
The TQnOPT0 register is an 8-bit register that selects a capture or compare operation, and detects an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: TQ0OPT0: FFFFF545H, TQ1OPT0: FFFFF615H,
TQ2OPT0: FFFFF625H
7
6
5
4
3
0
2
0
1
0
TQnOPT0 TQnCCS3 TQnCCS2 TQnCCS1 TQnCCS0
(n = 0 to 2)
TQnCUF
TQnOVF
TQnCCSm
Selection of capture or compare operation of TQnCCRm register (m = 0 to 3)
Compare register
Capture register
0
1
The set value of the TQnCCSm bit is valid only in the free-running mode.
TQnCUF
Timer Q down count flag
0
1
TMQn counting up
TMQn counting down
TQnUCF bit is valid in the triangular wave PWM mode.
This is read-only; a value written to this flag is invalid.
TQnOVF
Set (1)
Detection of overflow of timer Q
Overflow occurred
Reset (0)
0 written to TQnOVF bit or TQnCE = 0
• The TQnOVF bit is set when the 16-bit counter overflows from FFFFH to 0000H in the free-
running mode and pulse width measurement mode.
• As soon as the TQnOVF bit has been set to 1, an interrupt request signal (INTTQnOV) is
generated. The INTTQnOV signal is not generated in any mode other than the free-running mode
and pulse width measurement mode.
• The TQnOVF bit is not cleared even if the TQnOVF bit and TQnOPT0 register are read when
TQnOVF = 1.
• The TQnOVF bit can be read and written, but 1 cannot be written to the TQnOVF bit. Writing 1 to
this bit does not affect the operation of timer Q.
Cautions 1. Rewrite the TQnCCS1 and TQnCCS0 bits when TQnCE0 = 0 (the
same value can be written when TQnCE = 1). If these bits are
rewritten by mistake, clear TQnCE to 0 and then set them again.
2. Be sure to clear bits 2 and 3 to 0.
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(7) TIQnm pin noise elimination control register n (QnmNFC)
The QnmNFC register is an 8-bit register that sets the digital noise filter of the timer Q input pin for noise
elimination.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: Q00NFC: FFFFFB50H (TIQ00 pin)
Q01NFC: FFFFFB54H (TIQ01 pin)
Q02NFC: FFFFFB58H (TIQ02 pin)
Q03NFC: FFFFFB5CH (TIQ03 pin)
Q10NFC: FFFFFB60H (TIQ10 pin)
Q11NFC: FFFFFB64H (TIQ11 pin)
Q12NFC: FFFFFB68H (TIQ12 pin)
Q13NFC: FFFFFB6CH (TIQ13 pin)
Q20NFC: FFFFFB70H (TIQ20 pin)
Q21NFC: FFFFFB74H (TIQ21 pin)
Q22NFC: FFFFFB78H (TIQ22 pin)
Q23NFC: FFFFFB7CH (TIQ23 pin)
7
6
5
0
4
0
3
0
2
1
0
QnmNFC
0
NFSTS
NFC2
NFC1
NFC0
NFSTS
Setting of number of times of sampling by digital noise filter
0
1
3 times
2 times
NFC2
NFC1
NFC0
Sampling clock
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fXX
fXX/2
fXX/4
fXX/16
fXX/32
fXX/64
Other than above
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 5 and 7 to 0.
2. A signal input to the timer input pin (TIQnm) before the QnmNFC
register is set is output with digital noise eliminated.
Therefore, set the sampling clock (NFC2 to NFC0) and the number of
times of sampling (NFSTS) by using the QnmNFC register, wait for
initialization time = (Sampling clock) × (Number of times of
sampling), and enable the timer operation.
Remarks 1. The width of the noise that can be accurately eliminated is (Sampling
clock) × (Number of times of sampling – 1). Even noise with a width
narrower than this may cause a miscount if it is synchronized with the
sampling clock.
2. n: Number of timer channels (0 to 2)
m: Number of input pins (0 to 3)
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8.5 Operation
Timer Q performs the following operations.
Operation
TQnEST (Software
TIQn0 (External
Trigger Input)
Capture/Compare
Selection
Compare Write
Trigger Bit)
Interval timer mode
Invalid
Invalid
Valid
Compare only
Compare only
Compare only
Anytime write
Anytime write
Reload
External event count modeNote 1
Invalid
External trigger pulse output
modeNote 2
Valid
Valid
One-shot pulse output modeNote 2
Valid
Invalid
Invalid
Valid
Invalid
Invalid
Compare only
Compare only
Anytime write
Reload
PWM mode
Free-running mode
Capture/compare
selectable
Anytime write
Pulse width measurement modeNote 2
Triangular wave PWM mode
Invalid
Invalid
Invalid
Invalid
Capture only
Compare only
Not applicable
Reload
Notes 1. To use the external event counter input function, specify that the input edge of the TIQn0 pin is not detected
(by clearing the TQnIS1 and TQnIS0 bits of the TQnIOC1 register to 00).
2. To use the external trigger pulse output mode, one-shot pulse mode, or pulse width measurement mode,
select a count clock (by clearing the TQnEEE bit of the TQnCTL1 register to 0).
8.5.1 Anytime write and reload
Timer Q allows rewriting of the TQnCCR0 to TQnCCR3 registers while the timer is operating (TQnCE = 1). These
registers are written differently (anytime write or reload) depending on the mode.
(1) Anytime write
When data is written to the TQnCCR0 to TQnCCR3 registers during timer operation, it is transferred at any
time to the CCR0 to CCR3 buffer register and is compared with the value of the 16-bit counter.
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Figure 8-2. Flowchart of Basic Operation of Anytime Write
START
Initial setting
Enable timer operation (TQnCE = 1)
→ Transfer values of TQnCCR0
to CCR0 buffer register
Rewrite TQnCCR0
→ Transfer to CCR0 buffer register
Rewrite TQnCCR1
→ Transfer to CCR1 buffer register
Rewrite TQnCCR2
→ Transfer to CCR2 buffer register
Rewrite TQnCCR3
→ Transfer to CCR3 buffer register
INTTQnCC occurs
• CCR0 buffer register matches 16-
bit counter.
• Clear and start 16-bit counter.
Remarks 1. This is an example in the interval timer mode.
2. n = 0 to 2
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Figure 8-3. Timing Chart of Anytime Write
TQnCE = 1
D01
D01
D02
D21
D21
D21
D11
16-bit
counter
D12
D11
D12
D
31
02
D31
D
31
D31
TQnCCR0
D
01
D
CCR0 buffer
register
0000H
D01
D02
INTTQnCC0
TQnCCR1
D11
D12
CCR1 buffer
register
0000H
0000H
0000H
D11
D12
INTTQnCC1
TQnCCR2
D
21
CCR2 buffer
register
D
21
INTTQnCC2
TQnCCR3
D
31
CCR3 buffer
register
D31
INTTQnCC3
Remarks 1. D01, D02: Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TQnCCR1 register (0000H to FFFFH)
D21:
D31:
Set value of TQnCCR2 register (0000H to FFFFH)
Set value of TQnCCR3 register (0000H to FFFFH)
2. This is an example in the interval timer mode.
3. n = 0 to 2
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(2) Reload
When data is written to the TQnCCRm register during timer operation, it is compared with the value of the 16-
bit counter via the CCRm buffer register. The value of the TQnCCRm register can be rewritten when TQnCE =
1. So that the set values of the TQnCCRm register is compared with the value of the 16-bit counter (the set
values are reloaded to the CCRm buffer register), the value of the TQnCCR0, TQnCCR2 and TQnCCR3
register must be rewritten and then a value must be written to the TQnCCR1 register before the value of the
16-bit counter matches the value of the CCR0 buffer register.
When the value of the CCR0 buffer register matches the value of the 16-bit counter, the value of the
TQnCCRm register is reloaded to the CCRm buffer register.
Whether the next reload timing is made valid or not is controlled by writing to the TQnCCR1 register.
Therefore, when rewriting value of TQnCCR0, TQnCCR2 or TQnCCR3 registers, be sure to write TQnCCR1
register to same value (Set same value of TQnCCR1 register).
Figure 8-4. Flowchart of Basic Operation of Reload
START
Initial setting
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCR0
to CCR0 buffer register
Rewrite TQnCCR0.
Rewrite TQnCCR2.
Rewrite TQnCCR3.
Rewrite TQnCCR1.
Reload is enabled
INTTQnCC0 occurs
• TQnCCR0 matches 16-bit counter.
• Clear and start 16-bit counter.
• Value of TQnCCRm is reloaded to
CCRm buffer register.
Caution Writing the TQnCCR1 register includes an operation to enable reload.Therefore, when rewriting
one of TQnCCR0,TQnCCR2 or TQnCCR3 registers,TQnCCR1 register needs to write same value
enable the next reload.Then rewrite the TQnCCR1 register after rewriting other TQnCCR registers.
Remarks 1. This is an example in the PWM mode.
2. n = 0 to 2, m = 0 to 3
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Figure 8-5. Timing Chart of Reload
TQnCE = 1
D01
D03
D02
D02
D11
D
32
D
32
D
32
D12
D
12
D
12
D
12
16-bit
counter
D31
D21
D21
D21
D21
D21
TQnCCR0
D01
D02
D03
CCR0 buffer
register
0000H
0000H
0000H
0000H
D
01
D
02
D
03
Note
Note
Same value write
TQnCCR1
D
11
D
12
D
12
CCR1 buffer
register
D11
D12
D
12
D
21
TQnCCR2
CCR2 buffer
register
D
21
TQnCCR3
D31
D32
D33
CCR3 buffer
register
D31
D32
D
33
Note
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
Note The value is not reloaded because the TQnCCR1 register is not written.
Remarks 1. D01, D02, D03: Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12:
D21:
Set value of TQnCCR1 register (0000H to FFFFH)
Set value of TQnCCR2 register (0000H to FFFFH)
D31, D32, D33: Set value of TQnCCR3 register (0000H to FFFFH)
2. This is an example in the PWM mode.
3. n = 0 to 2
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8.5.2 Interval timer mode (TQnMD2 to TQnMD0 = 000)
In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated when the set value of the
TQnCCR0 register matches the value of the 16-bit counter, and the 16-bit counter is cleared. Rewriting the
TQnCCRm register is enabled when TQnCE = 1. When a value is set to the TQnCCRm register, it is transferred to the
CCRm buffer register by means of anytime write, and is compared with the value of the 16-bit counter.
The 16-bit counter is not cleared by using the TQnCCRk register.
However, the set value of the TQnCCRk register is transferred to the CCRk buffer register and compared with the
value of the 16-bit counter. As a result, an interrupt request (INTTQnCCk) is generated.
The value can also be output from the TOQnm pin by setting the TQnOEm bit to 1.
When the TQnCCRk register is not used, it is recommended to set the TQnCCRk register to FFFFH.
Remarks 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE=1), refer to 8. 5. 1 Anytime
write.
2. n = 0 to 2, m = 0 to 3, k = to 3
Figure 8-6. Flowchart of Basic Operation in Interval Timer Mode
START
Initial setting
• Select clock (TQnCTL0: TQnCKS2 to
TQnCKS0).
• Set interval timer mode (TQnCTL0:
TQnMD2 to TQnMD0 = 000).
• Set compare register (TQnCCRm).
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
to CCRm buffer register
16-bit counter matches
CCRk buffer registerNote
INTTQnCCk occurs
INTTQnCC0 occurs
.
16-bit counter and CCR0
buffer register match.
Clear and start 16-bit counter.
Note The 16-bit counter is not cleared when its value matches the value of TQnCCRk.
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
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Figure 8-7. Timing of Basic Operation in Interval Timer Mode (1/2)
(a) When only TQnCCR0 register value is rewritten and TOQnm is not output
(TQnOEm = 0, TQnOLm = 0)
TQnCE = 1
FFFFH
D02
D21
D01
D01
D11
D11
D11
16-bit
counter
D31
D31
D31
D01
D02
TQnCCR0
CCR0 buffer
register
0000H
0000H
0000H
0000H
D01
D02
D
D
D
11
TQnCCR1
CCR1 buffer
register
D
11
21
31
21
TQnCCR2
CCR2 buffer
register
D
D
TQnCCR3
31
CCR3 buffer
register
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
Remarks 1. D01, D02: Set value of TQnCCR0 register (0000H to FFFFH)
D11:
D21:
D31:
Set value of TQnCCR1 register (0000H to FFFFH)
Set value of TQnCCR2 register (0000H to FFFFH)
Set value of TQnCCR3 register (0000H to FFFFH)
2. Interval time = (D0n + 1) × (Count clock cycle)
3. n = 0 to 2, m = 0 to 3
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Figure 8-7. Timing of Basic Operation in Interval Timer Mode (2/2)
(b) When D01 = D31, only TQnCCR1 register value is rewritten, and TOQnm is output
(TQnOEm = 1, TQnOLm = 0)
TQnCE = 1
FFFFH
D01 = D31
D01 = D31
D11
D11
D12
16-bit
counter
D21
D21
D21
TQnCCR0
D01
CCR0 buffer
register
0000H
0000H
0000H
0000H
D
01
TQnCCR1
D11
D12
CCR1 buffer
register
D11
D12
D
21
31
TQnCCR2
CCR2 buffer
register
D
21
31
D
TQnCCR3
CCR3 buffer
register
D
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
TOQn0
TOQn1
TOQn2
TOQn3
Remarks 1. D01:
Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TQnCCR1 register (0000H to FFFFH)
D21:
D31:
Set value of TQnCCR2 register (0000H to FFFFH)
Set value of TQnCCR3 register (0000H to FFFFH)
2. Interval time = (D0n + 1) × (Count clock cycle)
3. n = 0 to 2, m = 0 to 3
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8.5.3 External event count mode (TQnMD2 to TQnMD0 = 001)
In the external event count mode, the external event count input (TIQn0 pin input) is used as a count-up signal.
Regardless of the setting of the TQnEEE bit of the TQnCTL0 register, 16-bit timer/event counter Q counts up the
external event count input (TIQn0 pin input) when it is set in the external event count mode.
In the external event count mode, an interrupt request (INTTQnCC0) is generated when the set value of the
TQnCCR0 register matches the value of the 16-bit counter, and the value of the 16-bit counter is cleared.
When a value is set to the TQnCCRm register, it is transferred to the CCRm buffer register by means of anytime
write, and is compared with the value of the 16-bit counter.
The 16-bit counter cannot be cleared by using the TQnCCRk register.
However, the set value of the TQnCCRk register is transferred to the CCRk buffer register and is compared with the
value of the 16-bit counter. As a result, an interrupt request (INTTQnCCk) is generated.
By setting the TQnOEk bit to 1, a signal can be output from the TOQnk pin.
TOQn pin can not to use. When the TQnCCRk register is not used, it is recommended to set TQnCCRk to FFFFH.
Remarks 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE=1), refer to 8. 5. 1 Anytime
write.
2. n = 0 to 2, m = 0 to 3, k = to 3
Caution 1. TOQn0 pin output in an external event count mode cannot be used. Set to TQnEEE = 1by
interval timer mode (TQnMD2 to 0 = 000b) when TOQn0 pin output in an external event count
mode is used.
2. In external event count mode, when TQnCCRm register value is set to 0000H the interrupt
occurs after the overflow of the timer (FFFFH to 0000H)
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Figure 8-8. Flowchart of Basic Operation in External Event Count Mode
START
Initial setting
• Set external event count mode
(TQnCTL0: TQnMD2 to TQnMD0 =
001)Note 1
• Set valid edge (TQnIOC2: TQnEES1,
TQnEES0).
• Set compare register (TQnCCRm).
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
to CCRm buffer register
INTTQnCCk occurs
INTTQnCC0 occurs
16-bit counter matches
CCRk buffer registerNote 2
.
16-bit counter matches
CCR0 buffer register.
Clear and start 16-bit counter.
Notes 1. Selecting the TQnEEE bit has no effect.
2. The 16-bit counter is not cleared when it matches the CCRk buffer register.
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
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Figure 8-9. Timing of Basic Operation in External Event Count Mode (1/2)
(a) When only TQnCCR0 register value is rewritten and TOQnm is not output
(TQnOEm = 0, TQnOLm = 0)
TQnCE = 1
FFFFH
D02
D21
D01
D01
D11
D11
D11
16-bit
counter
D31
D31
D31
D01
D02
D02
TQnCCR0
CCR0 buffer
register
0000H
0000H
0000H
0000H
D01
D11
D21
D31
TQnCCR1
CCR1 buffer
register
D11
TQnCCR2
CCR2 buffer
register
D21
D31
TQnCCR3
CCR3 buffer
register
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
Remarks 1. D01, D02: Set value of TQnCCR0 register (0000H to FFFFH)
D11:
D21:
D31:
Set value of TQnCCR1 register (0000H to FFFFH)
Set value of TQnCCR2 register (0000H to FFFFH)
Set value of TQnCCR3 register (0000H to FFFFH)
2. A compare match interrupt is generated each time (the value set to TQnCCRm register +1) is
detected.
3. n = 0 to 2, m = 0 to 3
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Figure 8-9. Timing of Basic Operation in External Event Count Mode (2/2)
(b) When D01 = D31, only TQnCCR1 register is rewritten, and TOQnm is output
(TQnOE0 = 0, TQnOEk = 1, TQnOL0 = 0, TQnOLk = 0)
TQnCE = 1
FFFFH
D01 = D31
D01 = D31
D11
D11
D12
16-bit
counter
D21
D21
D21
TQnCCR0
D01
CCR0 buffer
register
0000H
0000H
0000H
0000H
D
01
TQnCCR1
D11
D12
CCR1 buffer
register
D11
D12
D
21
31
TQnCCR2
CCR2 buffer
register
D
21
31
D
TQnCCR3
CCR3 buffer
register
D
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
TOQn1
TOQn2
TOQn3
Remarks 1. D01:
Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TQnCCR1 register (0000H to FFFFH)
D21:
D31:
Set value of TQnCCR2 register (0000H to FFFFH)
Set value of TQnCCR3 register (0000H to FFFFH)
2. A compare match interrupt is generated each time (the value set to TQnCCRm register +1) is
detected.
3. n = 0 to 2, k = 1 to 3
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8.5.4 External trigger pulse output mode (TQnMD2 to TQnMD0 = 010)
When TQnCE = 1 in the external trigger pulse output mode, the 16-bit counter stops at FFFFH and waits for input
of an external trigger (TIQn0 pin input). When the counter detects the edge of the external trigger (TIQn0 pin input), it
starts counting up.
The duty factor of the signal output from the TOQnk pin is set by a reload register (TQnCCRk) and the period is set
by a compare register (TQnCCR0).
Rewriting the TQnCCRm register is enabled when TQnCE = 1.
To stop timer Q, clear TQnCE to 0. If the edge of the external trigger (TIQn0 pin input) is detected more than once
in the external trigger pulse output mode, the 16-bit counter is cleared at the point of edge detection, and resumes
counting up. At the same time, TOQn0 pin is initialized. To realize the same function as the external trigger pulse
output mode by using a software trigger instead of the external trigger input (TIQn0 pin input) (software trigger pulse
output mode), a software trigger is generated by setting the TQnEST bit of the TQnCTL1 register to 1. The waveform
of the external trigger pulse is output from TOQnk.
In the external trigger pulse output mode, the capture function of the TQnCCRm register cannot be used because
this register can be used only as a compare register.
Caution In the external trigger pulse output mode, select the internal clock (TQnEEE of TQnCTL1 register =
0) as the count clock.
Remarks 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE=1),
refer to 8.5.1 (2) Reload.
2. n = 0 to 2, m = 0 to 3, k = to 3
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Figure 8-10. Flowchart of Basic Operation in External Trigger Pulse Output Mode
START
Initial setting
• Select clock.
(TQnCTL1: TQnEEE = 0)
(TQnCTL0: TQnCKS2 to TQnCKS0)
External trigger
• Set external trigger pulse output mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 010)
• Set compare register.
(TIQn0 pin) input
(TQnCCRm)
Clear and start
16-bit counter.
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
to CCRm buffer register
External trigger (TIQn0 pin) input
or TQnEST = 1Note 1
→ 16-bit counter starts counting
16-bit counter matches
INTTQnCCk occurs
INTTQnCC0 occurs
TQnCCRkNote 2
.
16-bit counter matches TQnCCR0.
Clear and start 16-bit counter.
Notes 1. Only TQnEST bit of TQnCT register can be rewritten during timer operation (TQnCE = 1).
2. The 16-bit counter is not cleared when it matches the CCRk buffer register.
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
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Figure 8-11. Timing of Basic Operation in External Trigger Pulse Output Mode
(TQnOE0 = 0, TQnOEk = 1, TQnOL0 = 0, TQnOLk = 0)
TQnCE = 1
FFFFH
D01
D02
D21
D21
D32
16-bit
counter
D11
D12
D12
D31
D31
External trigger
(TOQn0 pin)
TQnCCR0
D01
D02
CCR0 buffer
register
0000H
0000H
0000H
0000H
D
01
D
02
TQnCCR1
D11
D12
CCR1 buffer
register
D11
D
12
TQnCCR2
D21
CCR2 buffer
register
D
21
TQnCCR3
D31
D32
CCR3 buffer
register
D
31
D
32
TOQn1
TOQn2
TOQn3
Remarks 1. D01, D02: Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12: Set value of TQnCCR1 register (0000H to FFFFH)
D21:
Set value of TQnCCR2 register (0000H to FFFFH)
D31, D32: Set value of TQnCCR3 register (0000H to FFFFH)
2. Duty of TOQnk output = (Set value of TQnCCRk register) / (Set value of TQnCCR0 register)
Cycle of TOQnk output = (Set value of TQnCCR0 register +1) × (Count clock cycle)
3. n = 0 to 2, k = 1 to 3
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8.5.5 One-shot pulse mode (TQnMD2 to TQnMD0 = 011)
When TQnCE is set to 1 in the one-shot pulse mode, the 16-bit counter waits for the setting of the TQnEST bit (to
1) or a trigger that is input when the edge of the TIQn0 pin is detected, while holding FFFFH. When the trigger is
inputted, the 16-bit counter starts counting up. When the value of the 16-bit counter matches the value of the CCRk
buffer register that has been transferred from the TQnCCR0 register, TOQnk goes high. When the value of the 16-bit
counter matches the value of the CCR0 buffer register that has been transferred from the TQnCCR0 register, TOQnk
goes low, and the 16-bit counter is cleared to 0000H and stops. Input of a second or subsequent trigger is ignored
while the 16-bit counter is operating. Be sure to input a second trigger while the 16-bit counter is stopped at 0000H.
In the one-shot pulse mode, rewriting the TQnCCRm register is enabled when TQnCE = 1. If the value is set to the
TQnCCRm register, it is transferred to the CCRm buffer register by anytime write and it becomes an object of
comparison value with 16 bit counter value. The waveform of the one-shot pulse is output from the TOQnk pin. The
TOQnm pin produces an active level until counting by timer counter. Active level is set by TQnOL0 bit.
Cautions 1. Select the internal clock (TQnEEE of the TQnCTL1 register = 0) as the count clock in the one-
shot pulse mode.
2. In the one-shot pulse mode, the TQnCCRm register is used only as a compare register. It cannot
be used as a capture register.
3. When the set value of TQnCCRk is larger than the set value of TQnCCR0 in the one-shot pulse
mode, in the one-shot pulse is not output.
Remarks 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE=1), refer to 8. 5. 1 Anytime
write.
2. n = 0 to 2, m = 0 to 3, k = 1 to 3.
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Figure 8-12. Flowchart of Basic Operation in One-Shot Pulse Mode
START
Initial setting
• Select clock.
(TQnCTL1: TQnEEE = 0)
(TQnCTL0: TQnCKS2 to TQnCKS0)
• Set one-shot pulse mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 011)
• Set compare register.
(TQnCCRm)
Enable timer operation (TQnCE = 1)
→ Transfer values of TQnCCR0
to CCR0 buffer register
Wait for trigger.
16-bit counter stands by at FFFFH.
Input external trigger (TIQn0 pin)
or TQnEST = 1Note 1
→ 16-bit counter starts counting
Wait for trigger.
16-bit counter stands by at 0000H.
16-bit counter matches
INTTQnCCk occurs
INTTQnCC0 occurs
CCRk buffer registerNote 2
.
16-bit counter matches
CCR0 buffer register.
Clear 16-bit counter.
Notes 1. Only TQnEST bit of TQnCT register can be rewritten during timer operation (TQnCE = 1).
2. The 16-bit counter is not cleared when it matches the CCRk buffer register.
Caution The 16-bit counter is not cleared even if the trigger is input while the counter is counting up, and
the trigger input is ignored.
Remark n= 0 to 2, m = 0 to 3, k = 1 to 3
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Figure 8-13. Timing of Basic Operation in One-Shot Pulse Mode
(TQnOE0 = 0, TQnOEk = 1, TQnOL0 = 0, TQnOLk = 0)
TQnCE = 1 TQnEST = 1
FFFFH
D01
D01
D01
Note
D32
D21
D21
D21
16-bit
counter
D11
D11
D11
D31
D31
External trigger
(TOQn0 pin)
TQnCCR0
D01
CCR0 buffer
register
0000H
0000H
0000H
D
01
TQnCCR1
D
11
CCR1 buffer
register
D11
TQnCCR2
D
21
CCR2 buffer
register
D21
TQnCCR3
D31
D32
CCR3 buffer
register
0000H
D31
D32
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
TOQn1
TOQn2
TOQn3
Note The 16-bit counter starts counting up either when TQnEST = 1 or when an external trigger (TOQn0 pin) is
input.
Remarks 1. D01:
Set value of TQnCCR0 register (0000H to FFFFH)
Set value of TQnCCR1 register (0000H to FFFFH)
Set value of TQnCCR2 register (0000H to FFFFH)
D11:
D21:
D31, D32: Set value of TQnCCR3 register (0000H to FFFFH)
2. n = 0 to 2, k = 1 to 3
3. Output delay time = (Set value of TQnCCRk register) × (Count clock cycle)
Active level width = (Set value of TQnCCR0 register - Set value of TQnCCRk register +1) × (Count
clock cycle)
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
8.5.6 PWM mode (TQnMD2 to TQnMD0 = 100)
In the PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor and TMQn
capture/compare register 0 (TQnCCR0) is used to set the cycle.
By using these two registers and operating the timer, variable-duty PWM is output.
Rewriting the TQnCCRm register is enabled when TQnCE = 1.
To stop timer Q, clear TQnCE to 0. The waveform of PWM is output from the TOQnk pin. The TOQn0 pin produces
a half pulse output of PWM cycle when the 16-bit counter matches the TQnCCR0 register.
Remarks 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE = 1), refer to 8.5.1 (2) Reload.
2. n = 0 to 2, m = 0 to 3, k = 1 to 3
Caution: In the PWM mode, the TQnCCRm register is used only as a compare register. It cannot be used as a
capture register.
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(1) Operation flow of PWM mode
Figure 8-14. Flowchart of Basic Operation in PWM Mode (1/2)
(a) When values of TQnCCRm register is not rewritten during timer operation
START
Initial setting
• Select clock.
(TQnCTL0: TQnCKS2 to TQnCKS0)
• Set PWM mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 100)
• Set compare register.
(TQnCCRm)
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
register to CCRm buffer register
INTTQnCCk occurs
16-bit counter matches
CCRk buffer register.
TOQnk outputs low level.
16-bit counter matches
INTTQnCC0 occurs
CCR0 buffer register.
Clear and start 16-bit counter.
TOQnk outputs high level.
TOQn0 reverses
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
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Figure 8-14. Flowchart of Basic Operation in PWM Mode (2/2)
(b) When value of TQnCCRm register is rewritten during timer operation
START
Initial setting
• Select clock.
(TQnCTL0: TQnCKS2 to TQnCKS0)
• Set PWM mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 100)
• Set compare register.
(TQnCCRm)
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
register to CCRn buffer register
16-bit counter matches TQnCCRk.
INTTQnCCk occurs
TOQnk outputs low level.
16-bit counter matches TQnCCR0.
INTTQnCC0 occurs
Clear and start 16-bit counter.
TOQnk outputs high level.
TOQn0 reverses
Rewrite other than TQnCCR1
(TQnCCR0, TQnCCR2,
TQnCCR3).
<1>
16-bit counter matches
CCRk buffer register.
INTTQnCCk occurs
Note
<2>
<3>
TOQnk outputs low level.
Reload is enabled
INTTQnCC0 occurs
Rewrite TQnCCR1.
• CCR0 buffer register matches 16-bit
counter.
• Clear and start 16-bit counter.
• Value of TQnCCRm is reloaded to
CCRm buffer register.
• TOQnk outputs high level.
• TOQn0 reverses
Note The timing of <2> may differ depending on the rewrite timing of <1> and <3> and the value of TQnCCRk, but
make sure that <3> comes after <1>.
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
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(2) PWM output mode operation timing
(a) Change of pulse width during operation
When change of PWM waveform during operation, please write to TQ0CCR1 register at last. After write to
TQ0CCR1 register, when write to TPnCCR0 register again, please rewrite after detection of INTTQ0CC1
signal.
Figure 8-15. Timing of Basic Operation in PWM Mode (1/2)
(a) When rewriting values of TQnCCR1 to TQnCCR3 registers
(TQnOE0 = 1, TQnOEk = 1, TQnOL0 = 0, TQnOLk = 0)
TQnCE = 1
FFFFH
D01
D01
D01
D21
D21
D32
D32
D12
D12
D31
16-bit
counter
D22
D11
TQnCCR0
D
01
12
32
CCR0 buffer
register
0000H
D01
Same value write
D
11
D
12
D12
D13
TQnCCR1
CCR1 buffer
register
0000H
0000H
D
11
D
D12
D13
D21
D22
TQnCCR2
CCR2 buffer
register
D21
D22
D31
D
D33
TQnCCR3
CCR3 buffer
register
0000H
D31
D32
D33
TOQn0
TOQn1
TOQn2
TOQn3
Remarks 1. D01:
Set value of TQnCCR0 register (0000H to FFFFH)
D11, D12, D13: Set value of TQnCCR1 register (0000H to FFFFH)
D21, D22: Set value of TQnCCR2 register (0000H to FFFFH)
D31, D32, D33: Set value of TQnCCR3 register (0000H to FFFFH)
2. Duty of TOQnk output = (Set value of TQnCCRk register) / (Set value of TQnCCR0 register + 1)
Cycle of TOQnk output = (Set value of TQnCCR0 register) × (Count clock cycle)
Toggle width of TOQn0 output = (Set value of TQnCCR0 register + 1) × (Count clock cycle)
3. n = 0 to 2, k = 1 to 3
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Figure 8-15. Timing of Basic Operation in PWM Mode (2/2)
(b) When rewriting values of TQnCCR0 to TQnCCR3 registers
(TQnOE0 = 1, TQnOEk = 1, TQnOL0 = 0, TQnOLk = 0)
TQnCE = 1
FFFFH
D01
D01
D21
D21
D02
D32
D12
D31
D31
16-bit
counter
D22
D22
D11
D11
D33
TQnCCR0
D01
D02
CCR0 buffer
register
0000H
D01
D02
Same value write
D11
D12
D12
TQnCCR1
CCR1 buffer
register
0000H
0000H
D
11
D12
D12
D21
D22
TQnCCR2
Note
CC2 buffer
register
D21
D22
D31
D32
D33
TQnCCR3
CCR3 buffer
register
0000H
D31
D32
D33
TOQn0
TOQn1
TOQn2
TOQn3
Note No value is reloaded because the TQnCCR1 register is not rewritten.
Remarks 1. D01, D02:
D11, D12:
Set value of TQnCCR0 register (0000H to FFFFH)
Set value of TQnCCR1 register (0000H to FFFFH)
Set value of TQnCCR2 register (0000H to FFFFH)
D21, D22:
D31, D32, D33: Set value of TQnCCR3 register (0000H to FFFFH)
2. Duty of TOQnk output = (Set value of TQnCCRk register) / (Set value of TQnCCR0 register + 1)
Cycle of TOQnk output = (Set value of TQnCCR0 register) × (Count clock cycle)
Toggle width of TOQn0 output = (Set value of TQnCCR0 register + 1) × (Count clock cycle)
3. n = 0 to 2, k = 1 to 3
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is
FFFFH, the INTTQ0CCk signal is generated periodically.
Count clock
FFFF
0000
D0
− 1
D0
0000
0001
D
0
− 1
D0
0000
16-bit counter
TQ0CE bit
D
0
D
0
D
0
TQ0CCR0 register
TQ0CCRk register
INTTQ0CC0 signal
INTTQ0CCk signal
TOQ0k pin output
0000H
0000H
0000H
Remark k = 1 to 3
To output a 100% waveform, set a value of (set value of TQ0CCR0 register + 1) to the TQ0CCRk register.
If the set value of the TQ0CCR0 register is FFFFH, 100% output cannot be produced.
Count clock
FFFF
0000
D0
− 1
D0
0000
0001
D
0
− 1
D0
0000
16-bit counter
TQ0CE bit
D
0
D
0
D
0
0
TQ0CCR0 register
TQ0CCRk register
INTTQ0CC0 signal
INTTQ0CCk signal
TOQ0k pin output
D0
+ 1
D0
+ 1
D
+ 1
Remark k = 1 to 3
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8.5.7 Free-running mode (TQnMD2 to TQnMD0 = 101)
In the free-running mode, the 16-bit counter free-runs, and the bit that selects the capture or compare register
function can be by the setting of the TQnCCS3 to TQnCCS0 bits, so that an interval function and a capture function
can be realized.
Setting of the TQnCCS3 to TQnCCS0 bits of the TQnOPT0 register is valid only in the free-running mode.
Caution: In the free-running mode, counter clear can be operated by matched compare register.
TQnCCSm
Operation
0
1
TQnCCRm register is used as compare register.
TQnCCRm register is used as capture register.
• When TQnCCRm register is used as compare register
When the value of the 16-bit counter matches the value of the CCRm buffer register in the free-running mode,
an interrupt is generated.
TQnCCRm register is enabled for write operation when TPnCE=1. Any data is set to TPnCCR1 register by
anytime write, data is translated to CCRm buffer register, and data become comparison value with value of the
16 bit counter.
Caution: External event count input as count clock (TQnCTL.TQnEEE=1), TQnCCR0 register can not to
use as capture register.
If timer output (TOQnm) is enabled, TOQnm produces a toggle output when the value of the 16-bit counter
matches the value of the CCRm buffer register.
• When TQnCCRm register is used as capture register
The value of the 16-bit counter is stored in the TQnCCRm register when the edge of the TIQnm pin is detected.
Remarks 1. For the rewritten TQnCCR0 to TQnCCR3 during timer operation, refer to 8.5.1 (1) Anytime write.
2. n = 0 to 2, m = 0 to 3
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Figure 8-16. Flowchart of Basic Operation in Free-Running Mode
START
Initial setting
• Select clock.
(TQnCTL0: TQnCKS2 to TQnCKS0)
• Set free-running mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 101)
Set TQnCCSm.
TQnCCSm = 0
(Compare)
TQnCCSm = 1
(Capture)
Enable timer operation (TQnCE = 1)
→ Transfer value of TQnCCRm
to CCRm buffer register
Set detection of edge of TIQnm
(TQnIOC1 registerNote).
Enable timer operation (TQnCE = 1)
CCRm buffer register
matches 16-bit counter.
Edge of TIQnm is detected.
Value of 16-bit counter is
captured to TQnCCRm.
16-bit counter
overflows.
16-bit counter
overflows.
Note TQnCCR0 edge detection: TQnIS1, TQnIS0 bits
TQnCCR1 edge detection: TQnIS3, TQnIS2 bits
TQnCCR2 edge detection: TQnIS5, TQnIS4 bits
TQnCCR3 edge detection: TQnIS7, TQnIS6 bits
Remark n = 0 to 2, m = 0 to 3
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(1) When TQnCCSm = 0 (compare function)
When TQnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the
free-running mode until TQnCE is cleared to 0. If a value is written to the TQnCCRm register in this mode, it is
transferred to the CCRm buffer registers (anytime write). Even if a one-shot pulse trigger is input in this mode,
a one-shot pulse is not generated. If TQnOEm is set to 1, TOQnm produces a toggle output when the value of
the 16-bit counter matches the value of the CCRm buffer register.
(2) When TQnCCSm = 1 (capture function)
When TQnCE is set to 1, the 16-bit counter counts from 0000H to FFFFH, and continues counting up in the
free-running mode until TQnCE is cleared to 0. The value captured by a capture trigger is written to the
TQnCCRm registers.
Capturing before and after overflow (FFFFH) is judged using the overflow flag (TQnOVF).
However, if the interval of the capture trigger is such that the overflow occurs two times (two periods of more of
free-running), the TQnOVF flag cannot be used for judgment.
Remark n = 0 to 2, m = 0 to 3
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Figure 8-17. Timing of Basic Operation in Free-Running Mode (1/4)
(a) TQnCCS3 = 0, TQnCCS2 = 0, TQnCCS1 = 0, TQnCCS0 = 0
(TQnOEm = 1, TQnOLm = 0)
TQnCE = 1
FFFFH
16-bit
D30
D30
D01
D20
D
20
D
20
D
11
D
11
D00
D00
D10
D31
counter
TQnCCR0
D00
D
01
01
CCR0 buffer
register
0000H
0000H
0000H
0000H
D00
D
INTTQnCC0
match interrupt
TOQn0
D10
D
11
TQnCCR1
CCR1 buffer
register
D10
D
11
INTTQnCC1
match interrupt
TOQn1
TQnCCR2
D20
CCR2 buffer
register
D20
INTTQnCC2
match interrupt
TOQn2
D30
D
31
TQnCCR3
CCR3 buffer
register
D30
D
31
INTTQnCC3
match interrupt
TOQn3
Remarks 1. D00, D01: Set value of TQnCCR0 register (0000H to FFFFH)
D10, D11: Set value of TQnCCR1 register (0000H to FFFFH)
D20:
Set value of TQnCCR2 register (0000H to FFFFH)
D30, D31: Set value of TQnCCR3 register (0000H to FFFFH)
2. TOQnm output goes high when counting is started.
3. n = 0 to 2,m = 0 to 3
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Figure 8-17. Timing of Basic Operation in Free-Running Mode (2/4)
(b) TQnCCS3 = 1, TQnCCS2 = 1, TQnCCS1 = 1, TQnCCS0 = 1
(TQnOEm = 0, TQnOLm = 0)
TQnCE = 1
FFFFH
16-bit
D32
D10
D
12
D00
D
02
D31
D11
D30
counter
D21
D22
D01
D20
TIQn0
TQnCCR0
0000H
D00
D01
D02
INTTQnCC0
capture interrupt
TIQn1
TQnCCR1
0000H
D10
D11
D12
INTTQnCC1
capture interrupt
TIQn2
0000H
D20
D21
D22
TQnCCR2
INTTQnCC2
capture interrupt
TIQn3
TQnCCR3
0000H
D30
D31
D32
INTTQnCC3
capture interrupt
Remarks 1. D00, D01, D02: Value captured to TQnCCR0 register (0000H to FFFFH)
D10, D11, D12: Value captured to TQnCCR1 register (0000H to FFFFH)
D20, D21, D22: Value captured to TQnCCR2 register (0000H to FFFFH)
D30, D31, D32: Value captured to TQnCCR3 register (0000H to FFFFH)
2. TIQn0: Detection of rising edge (TQnIS1, TQnIS0 = 01) is set.
TIQn1: Detection of falling edge (TQnIS3, TQnIS2 = 10) is set.
TIQn2: Detection of falling edge (TQnIS5, TQnIS4 = 10) is set.
TIQn3: Detection of both rising and falling edges (TQnIS7, TQnIS6 = 11) is set.
3. n = 0 to 2, m = 0 to 3
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Figure 8-17. Timing of Basic Operation in Free-Running Mode (3/4)
(c) TQnCCS3 = 0, TQnCCS2 = 0, TQnCCS1 = 1, TQnCCS0 = 1
(TQnOEm = 0, TQnOLm = 0)
TQnCE = 1
FFFFH
16-bit
D12
D10
D02
D13
D
20
D20
D
00
D03
D
11
D21
D
01
counter
D30
D30
D30
TIQn0
INTTQnCC0
0000H
D00
D01
D02
D03
INTTQnCC0
capture interrupt
TIQn1
TQnCCR1
0000H
D10
D11
D12
D13
INTTQnCC1
capture interrupt
D20
D
21
21
TQnCCR2
CCR2 buffer
register
0000H
0000H
D20
D
INTTQnCC2
match interrupt
TQnCCR3
D30
CCR3 buffer
register
D30
INTTQnCC3
match interrupt
Remarks 1. D00, D01, D02, D03: Value captured to TQnCCR0 register (0000H to FFFFH)
D10, D11, D12, D13: Value captured to TQnCCR1 register (0000H to FFFFH)
D20, D21:
D30:
Value captured to TQnCCR2 register (0000H to FFFFH)
Value captured to TQnCCR3 register (0000H to FFFFH)
2. TIQn0: Detection of rising edge (TQnIS1, TQnIS0 = 01) is set.
TIQn1: Detection of falling edge (TQnIS3, TQnIS2 = 10) is set.
3. n = 0 to 2, m = 0 to 3
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Figure 8-17. Timing of Basic Operation in Free-Running Mode (4/4)
(d) TQnCCS3 = 0, TQnCCS2 = 1, TQnCCS1 = 0, TQnCCS0 = 1
(TQnOEm = 0, TQnOLm = 0)
TQnCE = 1
D02
FFFFH
16-bit
D00
D31
D31
D03
D21
D10
D12
D01
D20
counter
D11
D11
D30
TIQn0
TQnCCR0
0000H
D
00
D01
D02
D03
INTTQnCC0
capture interrupt
D10
D11
D12
TQnCCR1
CCR1 buffer
register
D10
D11
D12
0000H
INTTQnCC1
match interrupt
TIQn2
0000H
D20
D21
TQnCCR2
INTTQnCC2
capture interrupt
TQnCCR3
D30
D31
CCR3 buffer
register
0000H
D30
D31
INTTQnCC3
match interrupt
Remarks 1. D00, D01, D02, D03: Value captured to TQnCCR0 register (0000H to FFFFH)
D10, D11, D12:
D20, D21:
Value captured to TQnCCR1 register (0000H to FFFFH)
Value captured to TQnCCR2 register (0000H to FFFFH)
Value captured to TQnCCR3 register (0000H to FFFFH)
D30, D31:
2. TIQn0: Detection of rising edge (TQnIS1, TQnIS0 = 10) is set.
TIQn2: Detection of falling edge (TQnIS5, TQnIS4 = 10) is set.
3. n = 0 to 2, m = 0 to 3
(3) Overflow flag
When the counter overflows from FFFFH to 0000H in the free-running mode, the overflow flag (TQnOVF) is set
to 1, and an overflow interrupt (INTTQnOV) is generated.
The overflow flag is cleared by the CPU by writing 0 to it.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
8.5.8 Pulse width measurement mode (TQnMD2 to TQnMD0 = 110)
In the pulse width measurement mode, free-running counting is performed. The value of the 16-bit counter is
captured to capture register m (TQnCCRm) when both the rising and falling edges of the TIQnm pin are detected, and
the 16-bit counter is cleared to 0000H. In this way, the external input pulse width can be measured.
To measure a long pulse width that exceeds the overflow of the 16-bit counter, use the overflow flag for detection.
For measurement a pulse width that causes overflow to occur twice or more, please count the overflow number with
the overflow interrupt.
Caution In the pulse width measurement mode, select the internal clock (TQnEEE of the TQnCTL1 register =
0) as the count clock.
Figure 8-18 Flowchart of Basic Operation in Pulse Width Measurement Mode
START
Initial setting
• Select clock.
(TQnCTL0: TQnCKS2 to TQnCKS0)
• Set pulse width measurement mode.
(TQnCTL1: TQnMD2 to TQnMD0 = 110)
• Set compare register.
(TQnOPT0: TQnCCS3 to TQnCCS0)
Set edge detection of TIQnmNote
(TQnIS3 to TQnIS0)
.
Enable timer operation (TQnCE = 1).
Input rising edge of pulse to TIQnm.
Capture value to TQnCCRm.
Clear and start 16-bit counter.
Input falling edge of pulse to TIQnm.
Capture value to TQnCCRm.
Clear and start 16-bit counter.
Note An external pulse can be input from any of TIQn0 to TIQn3. Only one of them can be used. Specify that both
the rising and falling edges are detected. Specify that the input edge of an external pulse input that is not
used is not detected.
Remark n = 0 to 2, m = 0 to 3
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
Figure 8-19. Timing of Basic Operation in Pulse Width Measurement Mode
TQnCE = 1
FFFFH
FFFFH
D01
D03
D02
D00
16-bit
counter
TIQn0
TQnCCR0
INTTQnCC0
TQnOVF
0000H
D00
D01
D02
D
03
Cleared by
writing 0
from CPU
INTTQnOV
Remarks 1. D00, D01, D02, D03: Value captured to TQnCCR0 register (0000H to FFFFH)
2. TIQn0: Both the rising and falling edges are detected.
3. n = 0 to 2
4. Pulse width = Captured value × Count clock cycle
If the valid edge is not input even when the 16-bit counter counted up to FFFFH, an overflow interrupt
request signal (INTTQnOV) is generated at the next count clock, and the counter is cleared to 0000H
and continues counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Clear
the overflow flag to 0 by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TQnOVF bit set (1) count + Captured value) × Count clock cycle
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
8.5.9 Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111)
In the triangular wave PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor,
and TMQn capture/compare register 0 (TQnCCR0) is used to set the cycle.
By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output.
The value of the TQnCCRm register can be rewritten when TQnCE = 1.
Whether the next reload timing is made valid or not is controlled by writing to the TQnCCR1 register. Therefore,
write the same value to the TQnCCR1 register when it is necessary to rewrite the value of only the TQnCCR0 register.
Reload is invalid when only the TQnCCR0 register is rewritten.
To stop timer Q, clear TQnCE to 0. The waveform of PWM is output from the TOQnk pin. The TOQn0 pin produces
a toggle output when the value of the 16-bit counter matches the value of the TQnCCR0 register and when the
counter underflows.
Remarks: 1. For the rewriting TQnCCR0 to TQnCCR3 during timer operation (TQnCE=1), refer to 8. 5. 1 (2) Reload.
2. n = 0 to 2, m = 0 to 3, k = 1 to 3
Caution: In the PWM mode, the TQnCCRm register is used only as a compare register. It cannot be used as a
capture register.
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Figure 8-20. Timing of Basic Operation in Triangular Wave PWM Mode
(TQnOE0 = 1, TQnOE1 = 1, TQnOE2 = 1, TQnOE3 = 1,
TQnOL0 = 0, TQnOL1 = 0, TQnOL2 = 0, TQnOL3 = 0)
TQnCE = 1
FFFFH
D00
D00
D00
16-bit
counter
D30
D30
D30
D30
D30
D30
D20
D
20
D20
10
D
20
D20
10
D20
D10
D
D
TQnCCR0 0000H
TQnCCR1 0000H
TQnCCR2 0000H
TQnCCR3 0000H
D
00
10
20
30
D
D
D
INTTQnCC0
match interrupt
INTTQnCC1
match interrupt
INTTQnCC2
match interrupt
INTTQnCC3
match interrupt
INTTQnOV
TOQn0
TOQn1
TOQn2
TOQn3
Remark n = 0 to 2
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
8.6 Timer Synchronized Operation Function
Timer P and timer Q have a timer synchronized operation function (tuned operation mode).
The timers that can be synchronized are listed in Table 8-4.
Table 8-4. Tuned Operation Mode of Timers
Master Timer
TMP0
Slave Timer
TMP1
TMP3
TMQ2
–
TMQ0
–
TMP2
TMQ1
Cautions 1. The tuned operation mode is enabled or disabled by the TPmSYE bit of the TPmCTL1 register
and TQnSYE bit of the TQnCTL1 register. For TMQ2, either or both TMQ3 and TMQ0 can be
specified as slaves.
2. Set the tuned operation mode using the following procedure.
<1> Set the TPmSYE bit of the TPmCTL1 register and the TQnSYE bit of the TQnCTL1
register of the slave timer to enable the tuned operation.
Set the TPmMD2 to TPmMD0 bits of the TPmCTL1 register and TQnMD2 to TQnMD0 bits
of the TQnCTL1 register of the slave timer to the free-running mode
<2> Set the timer mode by using the TPnMD2 to TPnMD0 bits of the TPnCTL1 register and
the TPnMD2 to TPnMD0 bits of the TQnCTL1 register.
At this time, do not set the TPnSYE bit of the TPnCTL1 register and the TQnSYE bit of
the TQnCTL1 register of the master timer.
<3> Set the compare register value of the master and slave timers.
<4> Set the TPmCE bit of the TPmCTL0 register and the TQnCE bit of the TQnCTL0 register
of the slave timer to enable operation on the internal operating clock.
<5> Set the TPnCE bit of the TPnCTL0 register and the TQnCE bit of the TQnCTL0 register of
the master timer to enable operation on the internal operating clock.
Remark n = 0, 2, m = 1, 3
Tables 8-5 and 8-6 show the timer modes that can be used in the tuned operation mode (√: Settable, ×: Not
settable).
Table 8-5. Timer Modes Usable in Tuned Operation Mode
Master Timer
TMP0
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
√
√
√
√
√
√
×
×
√
TMP2
TMQ1
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Table 8-6. Timer Output Functions (1/2)
Tuned
Channel
Timer
TMP0
Pin
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
Tuning OFF Tuning ON Tuning OFF Tuning ON Tuning OFF Tuning ON
Ch0
TOP00
TOP01
TOP10
TOP11
TOP20
TOP21
TOP30
TOP31
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
←
←
←
←
←
←
←
←
Toggle
PWM
←
←
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
←
←
←
←
←
←
←
←
(master)
TMP1
Toggle
PWM
PWM
←
(slave)
TMP2
Ch1
Toggle
PWM
←
(master)
TMP3
←
Toggle
PWM
PWM
←
(slave)
Table 8-7. Timer Output Functions (2/2)
Tuned
Timer
Pin
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
Channel
Tuning OFF Tuning ON Tuning OFF Tuning ON Tuning OFF Tuning ON
Ch1
TMQ0
(slave)
TOQ00
PPG
PPG
←
←
Toggle
PWM
PWM
Toggle
N/A
N/A
TOQ01 to TOQ03
←
Triangular
wave PWM
Ch2
TMQ1
(master)
TOQ10
PPG
PPG
←
←
Toggle
PWM
←
←
Toggle
←
←
TOQ11 to TOQ13
Triangular
wave PWM
TMQ2
(slave)
TOQ20
PPG
PPG
←
←
Toggle
PWM
PWM
Toggle
Triangular
wave PWM
TOQ21 to TOQ23
←
Triangular
←
wave PWM
Remark The timing of transmitting data from the compare register of the master timer to the compare register of
the slave timer is as follows.
PPG: CPU write timing
Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0
and TOQm0 (n = 0 to 3, m = 0 to 2)
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Figure 8-21. Tuned Operation Image (TMP2,TMP3,TMQ0)
Unit operation
Tuned operation
TMP2
TMP3
TMQ0
TMP2 (master ) + TMP3 (slave) + TMQ0 (slave)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
TOP21 (PWM output)
16-bit capture/compare
TOP21 (PWM output)
16-bit capture/compare
16-bit capture/compare
TOP30 (PWM output)
TOP31 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOQ00 (PWM output)
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
TOP31 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
Five PWM outputs are available when
PWM is operated as a single unit.
Seven PWM outputs are available when
PWM is operated in tuned operation mode.
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Figure 8-22. Basic Operation Timing of Tuned PWM Function (TMP2,TMP3,TMQ0)
FFFFH
D00
D00
D70
D70
D60
D60
TMP2
16-bit
counter
D50
D50
D40
D40
D30
D30
D20
D20
D10
D10
0000H
TP2CE
TP3CE
TQ0CE
TP2CCR0
TP2CCR1
TP3CCR0
TP3CCR1
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
D00
D10
D20
D30
D40
D50
D60
D70
INTTP2CC0
match interrupt
INTTP2CC1
match interrupt
INTTP3CC0
match interrupt
INTTP3CC1
match interrupt
INTTQ0CC0
match interrupt
INTTQ0CC1
match interrupt
INTTQ0CC2
match interrupt
INTTQ0CC3
match interrupt
TOP20
TOP21
TOP30
TOP31
TOQ00
TOQ01
TOQ02
TOQ03
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
8.7 Cautions
(1) Capture operation
When the capture signal occurs before the count clock is available and the selected count clock is slower than
the internal sampling signal, the value in the capture register is FFFFH (instead of 0000H).
(a)Free running timer mode
FFFFH
16 bit counter
0000H
Count clock
Sampling clock
TQnCCR0 register 0000H
TQnCE bit
FFFFH
0002H
TIQn0 pin input
Capture trigger
Capture trigger input
(b)Pulse mode
FFFFH
16 bit counter
0000H
Count clock
Sumpling clock
TQnCCR0 register 0000H
TQnCE bit
FFFFH
0001H
TIQn0 pin input
Capture trigger
Caputure torigger input
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q
(2) Notes on rewriting the TQ0CCR0 register
To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
D1
D1
16-bit counter
0000H
D2
D2
D2
TQ0CE bit
TQ0CCR0 register
INTTQ0CC0 signal
D1
D2
External event
count signal
interval (1)
External event count signal External event
interval (NG)
(10000H + D
count signal
interval (2)
2
+ 1)
(D1
+ 1)
(D2 + 1)
If the value of the TQ0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less
than D1, the count value is transferred to the CCR0 buffer register as soon as the TQ0CCR0 register has been
rewritten. Consequently, the value that is compared with the 16-bit counter is D2.
Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows,
and then counts up again from 0000H. When the count value matches D2, the INTTQ0CC0 signal is generated.
Therefore, the INTTQ0CC0 signal may not be generated at the valid edge count of “(D1 + 1) times” or “(D2+ 1)
times” originally expected, but may be generated at the valid edge count of “(10000H + D2 + 1) times”.
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(3) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8-
bit data (bit 0 is 0) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1,
and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
Overflow
(iii) Operation to clear to 0 (without conflict with setting)
Overflow
L
L
set signal
set signal
0 write signal
Register
0 write signal
Overflow flag
(TQ0OVF bit)
Read
Write
access signal
Overflow flag
(TQ0OVF bit)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
Overflow
set signal
Overflow
set signal
0 write signal
0 write signal
Register
Overflow flag
(TQ0OVF bit)
Read
Write
access signal
Overflow flag
(TQ0OVF bit)
H
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow
may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has
occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to
0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction.
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CHAPTER 9 16-BIT INTERVAL TIMER M
The V850ES/Fx2 include a 16-bit interval timer M (TMM0).
Table 9-1. Number of Channels of Timer M
Product
Number of Channels
1 channel (TMM)
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
9.1 Features
Timer M (TMM) supports only a clear & start mode. It does not support a free-running mode. To use timer M in a
manner equivalent to in the free-running mode, set the compare register to FFFFH and start the 16-bit counter. A
match interrupt will occur when the timer overflows.
• Interval function
• Clock selection × 8
• Simple counter × 1
(The simple counter is a counter that does not use a counter read buffer. This counter cannot be read during
timer count operation.)
• Simple compare × 1
(The simple compare register is a register that does not use a compare write buffer. No data can be written to
this compare register during timer count operation.)
• Compare match interrupt × 1
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CHAPTER 9 16-BIT INTERVAL TIMER M
9.2 Configuration
TMM consists of the following hardware.
Table 9-2. Configuration ofTMM
Item
Configuration
Timer register
Register
16-bit counter
TMM compare register 0 (TM0CMP0)
TMM0 control register (TM0CTL0)
Control register
Figure 9-1. Block Diagram of Timer M
Internal bus
TM0CTL0
TM0CE TM0CKS2 TM0CKS1TM0CKS0
TM0CMP0
Match
INTTM0EQ0
f
XX
f
f
XX/2
XX/4
f
XX/64
XX/512
INTWT
/8
Controller
16-bit counter
f
Clear
f
R
f
XT
Remark
f
f
f
XX
:
Main clock frequency
R:
Internal oscillation clock frequency
Subclock frequency
XT:
INTWT: Watch timer interrupt request signal
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CHAPTER 9 16-BIT INTERVAL TIMER M
(1) 16-bit counter
This is a 16-bit counter that counts the internal clock.
The 16-bit counter cannot be read or written.
(2) TMM0 compare register 0 (TM0CMP0)
The TM0CMP0 register is a 16-bit compare register.
This register can be read or written in 16-bit units.
Reset input clears this register to 0000H.
The same value can always be written to the TM0CMP0 register by software.
After reset: 0000H R/W
Address: TM0CMP0: FFFFF694H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TM0CMP0
Caution: Rewriting the TM0CMP0 register is prohibited while the timer is working (TM0CE = 1). But The same
value can be rewritten.
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CHAPTER 9 16-BIT INTERVAL TIMER M
9.3 Control Register
(1) TMM0 control register 0 (TM0CTL0)
The TM0CTL0 register is an 8-bit register that controls the operation of TMM.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Rewriting the TM0CTL0 register is prohibited while the timer is working. Only the TM0CE bit can always be
rewritten.
(1/2)
After reset: 00H
R/W
Address: TM0CTL0: FFFFF690H
7
6
0
5
0
4
0
3
0
2
1
0
TM0CTL0
TM0CE
TM0CKS2 TM0CKS1 TM0CKS0
TM0CE
Control of operation of timer M0
0
1
Disable internal operating clock operation (asynchronously reset TMM0).
Enable internal operating clock operation.
The TM0CE bit controls the internal operating clock and asynchronously resets TMM0. When this
bit is cleared to 0, the internal operating clock of TMM is stopped (fixed to the low level), and TMM0
is asynchronously reset.
When the TM0CE bit is set to 1, the internal operating clock is enabled within two input clocks, and
the timer counts up.
TM0CKS2 TM0CKS1 TM0CKS0
Selection of internal count clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fXX
fXX/2
fXX/4
fXX/64
fXX/512
INTWT
fR/8
fXT
Cautions: 1. Set TM0CKS2 to TM0CKS0 bits at TM0CE = 0. When the TM0CE bit is
set from 0 to 1, the TM0CKS2 to TM0CKS0 bits can be set at the same
time.
2. Set bit 6-3 to 0.
Remark
f
f
f
XX: Main system clock frequency
Ring-OSC clock frequency
XT: Subclock frequency
R
:
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CHAPTER 9 16-BIT INTERVAL TIMER M
(2/2)
Resolution and maximum number of counts
Internal count
clock
Resolution [µs]
Maximum count time [ms]
fXX = 16 MHz fXX = 20 MHz
4.10 3.28
fXX = 16 MHz
fXX = 20 MHz
0.050
fXX
0.0625
0.125
0.250
4.000
32.000
fXX/2
0.100
8.19
16.38
6.55
13.11
fXX/4
0.200
fXX/64
fXX/512
3.200
262.14
2097.15
209.72
1677.72
25.600
Internal count
clock
Resolution [µs]
Maximum count time [ms]
fR =100kHz fR =200kHz fR =400kHz fR =100kHz fR =200kHz fR =400kHz
(Min.)
80.0
(Typ.)
40.0
(Max.)
20.0
(Min.)
(Typ.)
(Max.)
fR/8
5242.88
2621.44
1310.72
Internal count
clock
Resolution [µs]
fXT = 32.768 kHz
30.52
Maximum count time [ms]
fXT = 32.768 kHz
2000.00
fXT
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CHAPTER 9 16-BIT INTERVAL TIMER M
9.4 Operation
9.4.1 Interval timer mode
In the interval timer mode, a match interrupt signal (INTTM0EQ0) is output when the value of the 16-bit counter
matches the value of TMM0 compare register 0 (TM0CMP0). At the same time, the counter is cleared to 0000H and
starts counting up.
Figure 9-2. Basic Timing of Operation in Interval Timer Mode
FFFFH
D
D
D
D
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
D
Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1)
Figure 9-3. Timing of Operation in Interval Timer Mode
Count clock
M – 2
M – 1
M
M
0000H
0001H
16-bit counter
TM0CMP0
INTTM0EQ0
Caution To set M clocks as the interval period, set the TM0CMP0 register to M – 1.
When FFFFH is set to the TM0CMP0 register, timer M performs an operation similar to that in the free-running
mode.
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CHAPTER 9 16-BIT INTERVAL TIMER M
9. 5 Cautions
(1) Clock generator and clock enable timing
It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1,
depending on the count clock selected.
Selected Count Clock
Maximum Time Before Counting Start
fXX
2/fXX
fXX/2
fXX/4
fXX/64
fXX/512
INTWT
fR/8
6/fXX
24/fXX
128/fXX
1024/fXX
Second rising edge of INTWT signal
16/fR
2/fXT
fXT
Figure 9-4. Count Operation Start Timing
Clock for counting
TM0CE bit
Clock enable signal
(internal signal)
Count clock
(2) Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is operating.
If these registers are rewritten while the TM0CE bit is 1, the operation cannot be guaranteed.
If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set the registers.
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.1 Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and interval timer functions can be used at the same time.
Figure 10-1. Block Diagram of Watch Timer
Reset
Clear
5-bit counter
INTWT
INTWTI
Prescaler
3Note
f
X
f
BRG
11-bit prescaler
/25 f /26 f /27 f /28
f
W
Clear
f
W
/24 f
W
W
W
W
f
W
/210
f
W
/211
f
/29
W
f
XT
3
WTM7 WTM6 WTM5 WTM4
WTM3
WTM2 WTM1 WTM0
Watch timer operation mode register
(WTM)
Internal bus
Note For details of prescaler 3, see Figure 10-2 Block Diagram of Prescaler 3.
Remark fBRG:
Prescaler 3 output frequency
Main clock oscillation frequency
Subclock frequency
fX:
fXT:
fW:
Watch timer clock frequency
INTWT: Watch timer interrupt
INTWTI: Interval timer interrupt
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CHAPTER 10 WATCH TIMER FUNCTIONS
Figure 10-2. Block Diagram of Prescaler 3
f
X
3-bit prescaler
f
f
f
f
X
X
X
X
/8
/4
/2
f
BGCS
8-bit counter
Match
f
BRG
Output
control
2
Prescaler compare register0
(PRSCM0)
Prescaler mode register 0 (PRSM0)
BGCE0 BGCS01 BGCS00
Remark fBGCS: Prescaler 3 count clock frequency
fBRG: Prescaler 3 output frequency
fX:
Oscillation frequency
(1) Watch timer
The watch timer generates an interrupt request (INTWT) at time intervals of 0.5 or 0.25 seconds by using the
subclock (fXT = 32.768 kHz).
Caution When using a clock obtained by dividing the main clock as the watch timer count clock, set
the PRSM0 and PRSCM0 registers according to the main clock frequency that is used so as
to obtain a divided clock frequency of 32.768 kHz.
If 32.768 kHz cannot be generated, correction using software is necessary to realize the
watch function.
(2) Interval timer
The watch timer generates an interrupt request (INTWTI) at time intervals specified in advance.
Table 10-1. Interval Time of Interval Timer
Interval Time
Operation at fW = 32.768 kHz
24 × 1/fW
25 × 1/fW
26 × 1/fW
27 × 1/fW
28 × 1/fW
29 × 1/fW
488 µs
977 µs
1.95 ms
3.91 ms
7.81 ms
15.6 ms
31.2 ms
62.5 ms
2
2
10 × 1/fW
11 × 1/fW
Remark fW: Watch timer clock frequency
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.2 Configuration
The watch timer consists of the following hardware.
Table 10-2. Configuration of Watch Timer
Item
Configuration
Counter
5 bits × 1
Prescaler
11 bits × 1
Control register
Watch timer operation mode register (WTM)
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.3 Control Registers
The watch timer operation mode register (WTM) controls the watch timer. Before operating the watch timer, set
the count clock and the interval time.
(1) Watch timer operation mode register (WTM)
The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time
of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
(1/2)
After reset: 00H
R/W
Address: FFFFF680H
WTM
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
WTM7 WTM6
WTM5 WTM4
Selection of watch timer interrupt time
24/f
25/f
26/f
27/f
28/f
29/f
W
W
W
W
W
W
(488
µ
s: f
W
W
= fXT
= fXT
)
)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
µ
(977 s: f
(1.95 ms: f
(3.91 ms: f
(7.81 ms: f
(15.6 ms: f
W
W
W
W
= fXT
= fXT
= fXT
= fXT
)
)
)
)
210/f
211/f
W
W
(31.3 ms: f
(62.5 ms: f
W
W
= fXT
= fXT
)
)
24/f
25/f
26/f
27/f
28/f
29/f
W
(488
µ
s: f
W
= fBRG
= fBRG
)
)
W
W
W
W
W
(977 s: f
W
µ
(1.95 ms: f
(3.90 ms: f
(7.81 ms: f
(15.6 ms: f
W
W
W
W
= fBRG
= fBRG
= fBRG
= fBRG
)
)
)
)
210/f
211/f
W
W
(31.2 ms: f
(62.5 ms: f
W
W
= fBRG
= fBRG
)
)
Remarks 1. fW: Watch timer clock frequency
fXT: Subclock frequency
fBRG: Prescaler 3 output frequency
2. Values in parentheses apply to operation with fW = 32.768 kHz
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CHAPTER 10 WATCH TIMER FUNCTIONS
(2/2)
WTM7 WTM3 WTM2
Selection of set time of watch flag
214/fW (0.5 s: fW = fXT)
213/fW (0.25 s: fW = fXT)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25/fW (977 s: fW = fXT)
µ
24/fW (488 s: fW = fXT)
µ
214/fW (0.5 s: fW = fBRG)
213/fW (0.25 s: fW = fBRG)
25/fW (977 s: fW = fBRG)
µ
24/fW (488
µ
s: fW = fBRG)
WTM1
Control of 5-bit counter operation
0
1
Clears after operation stops
Starts
WTM0
Watch timer operation enable
0
1
Stops operation (clears both prescaler and 5-bit counter)
Enables operation
Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0.
Remarks 1. fW: Watch timer clock frequency
fXT: Subclock frequency
fBRG: Prescaler 3 output frequency
2. Values in parentheses apply to operation with fW = 32.768 kHz
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.4 Operation
10.4.1 Operation as watch timer
The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time
intervals of 0.5 or 0.25 seconds with the subclock (32.768 kHz).
The count operation starts when the WTM1 and WTM0 bits of the WTM register are set to 11. When the WTM0 bit
is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops.
The time of the watch timer can be adjusted by clearing the WTM1 bit to 0 and then the 5-bit counter. At this time,
an error of up to 15.6 ms may occur.
The interval timer may be cleared by clearing the WTM0 bit to 0. However, because the 5-bit counter is cleared at
the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (INTWT).
10.4.2 Operation as interval timer
The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified
by a preset count value.
The interval time can be selected by the WTM4 to WTM7 bits of the WTM register.
Table 10-3. Interval Time of Interval Timer
WTM7
WTM6
WTM5
WTM4
Interval Time
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
24 × 1/fw
25 × 1/fw
26 × 1/fw
27 × 1/fw
28 × 1/fw
29 × 1/fw
488 µs (operating at fW = fXT = 32.768 kHz)
977 µs (operating at fW = fXT = 32.768 kHz)
1.95 ms (operating at fW = fXT = 32.768 kHz)
3.91 ms (operating at fW = fXT = 32.768 kHz)
7.81 ms (operating at fW = fXT = 32.768 kHz)
15.6 ms (operating at fW = fXT = 32.768 kHz)
31.3 ms (operating at fW = fXT = 32.768 kHz)
62.5 ms (operating at fW = fXT = 32.768 kHz)
488 µs (operating at fW = fBRG = 32.768 kHz)
977 µs (operating at fW = fBRG = 32.768 kHz)
1.95 ms (operating at fW = fBRG = 32.768 kHz)
3.91 ms (operating at fW = fBRG = 32.768 kHz)
7.81 ms (operating at fW = fBRG = 32.768 kHz)
15.6 ms (operating at fW = fBRG = 32.768 kHz)
31.3 ms (operating at fW = fBRG = 32.768 kHz)
62.5 ms (operating at fW = fBRG = 32.768 kHz)
2
10 × 1/fw
11 × 1/fw
2
24 × 1/fw
25 × 1/fw
26 × 1/fw
27 × 1/fw
28 × 1/fw
29 × 1/fw
2
2
10 × 1/fw
11 × 1/fw
Remark fW: Watch timer clock frequency
fXT: Subclock frequency
fBRG: Prescaler 3 output frequency
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CHAPTER 10 WATCH TIMER FUNCTIONS
Figure 10-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H
Overflow
Overflow
Start
Count clock
or f
/29
f
W
W
Watch timer interrupt
INTWT
Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Interval timer interrupt
INTWTI
Interval time (T)
nT
Interval time (T)
nT
Remark fW: Watch timer clock frequency
Values in parentheses apply to operation with count clock fW = 32.768 kHz.
n: Number of interval timer operations
10.4.3 Cautions
The following time is required before the first watch timer interrupt request signal (INTWT) is generated after
operation is enabled (WTM1 and WTM0 bits of WTM register = 1).
Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT)
(When Interrupt Period = 0.5 s)
It takes 0.515625 seconds for the first INTWT signal to be generated (29 × 1/32768 = 0.015625 s longer). The
INTWT signal is then generated every 0.5 seconds.
WTM0, WTM1
0.515625 s
0.5 s
0.5 s
INTWT
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.5 Prescaler 3
Prescaler 3 has the following function.
• Generation of watch timer count clock (source clock: main oscillation clock)
10.5.1 Control registers
(1) Prescaler mode register 0 (PRSM0)
The PRSM0 register controls the generation of the watch timer count clock.
This register can be read or written in 8-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
0
Address: FFFFF8B0H
PRSM0
0
0
BGCE0
0
0
BGCS01 BGCS00
BGCE0
Prescaler output
0
1
Disabled (fixed to 0)
Enabled
BGCS01 BGCS00
Selection of prescaler 3 clock (fBGCS)
f
X
= 5 MHz
200 ns
400 ns
800 ns
f
X
= 4 MHz
250 ns
500 ns
0
0
1
1
0
1
0
1
f
f
f
f
X
X
X
X
/2
/4
/8
1
2
s
s
µ
µ
1.6 s
µ
Cautions 1. Do not change the values of the BGCS00 and BGCS01 bits during watch timer operation.
2. Set the PRSM0 register before setting the BGCE0 bit to 1.
3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an fBRG frequency of 32.768 kHz.
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CHAPTER 10 WATCH TIMER FUNCTIONS
(2) Prescaler compare register 0 (PRSCM0)
The PRSCM0 register is an 8-bit compare register.
This register can be read or written in 8-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: FFFFF8B1H
PRSCM0
PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00
Cautions 1. Do not rewrite the PRSCM0 register during watch timer operation.
2. Set the PRSCM0 register before setting the BGCE0 bit of the PRSM0 register to 1.
3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an fBRG frequency of 32.768 kHz.
10.5.2 Generation of watch timer count clock
The clock input to the watch timer (fBRG) can be corrected to approximate 32.768 kHz.
The relationship between the main clock (fX), prescaler 3 clock selection bit BGCSn setting value (m), PRSCM0
register setting value (N) and output clock (fBRG) is as follows.
fX
fBRG =
2m × N × 2
Example: When fX = 4.00 MHz, m = 0 (BGCS01 bit = BGCS00 bit = 0), and N = 3DH
fBRG = 32.787 kHz
Remark fBRG: Watch timer count clock
N: PRSCM0 register setting value (1 to FFH)
In the case of a PRSCM0 register setting value of 00H, N = 256
m: BGCSn bit setting value (0 to 3)
n = 00, 01
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
11.1 Functions
Watchdog timer 2 has the following functions.
• Default-start watchdog timer
→ Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal)
→ Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of
INTWDT2 signal)Note
• Input selectable from main clock and Ring-OSC as the source clock
Note
Restoring using the RETI instruction following non-maskable interrupt servicing due to a non-
maskable interrupt request signal (INTWDT2) is not possible. Therefore, following completion of
interrupt servicing, perform a system reset.
Figure 11-1. Block Diagram of Watchdog Timer 2
f
f
X
/216 to fXX/223,
/212 to f /219
/27
/23
INTWDT2
f
X
R
R
Clock
input
controller
16-bit
counter
Output
controller
Selector
WDT2RES
(internal reset signal)
f
R
2
3
3
Clear
0
WDM21 WDM20
WDCS24 WDCS23 WDCS22 WDCS21WDCS20
RUN2
Watchdog timer mode
register 2 (WDTM2)
Watchdog timer enable
register (WDTE)
Internal bus
Remark fX:
Oscillation frequency
fR:
Ring-OSC clock frequency
INTWDT2: Non-maskable interrupt request signal from watchdog timer 2
WDT2RES: Watchdog timer 2 reset signal
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
11.2 Configuration
Watchdog timer 2 consists of the following hardware.
Table 11-1. Configuration of Watchdog Timer 2
Item
Configuration
Control registers
Oscillation stabilization time select register (OSTS)
Watchdog timer mode register 2 (WDTM2)
Watchdog timer enable register (WDTE)
11.3 Control Registers
(1) Oscillation stabilization time select register (OSTS)
The OSTS register selects the oscillation stabilization time following reset or release of the stop mode.
This register can be read or written in 8-bit units.
Reset input sets this register to 06H.
After reset: 06H
R/W
0
Address: FFFFF6C0H
OSTS
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0 Selection of oscillation stabilization time/setup timeNote
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
210/f
211/f
212/f
213/f
214/f
215/f
216/f
X
X
X
X
X
X
X
Setting prohibited
Note The oscillation stabilization time and setup time are required when the software
STOP mode and idle mode are released, respectively.
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
(2) Watchdog timer mode register 2 (WDTM2)
This register is a special register. This register can be written only by a specific sequence.
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset input sets this register to 67H.
After reset: 67H
R/W
Address: FFFFF6D0H
WDTM2
0
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
WDM21 WDM20
Selection of operation mode of watchdog timer 2
Stops operation
0
0
0
1
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
1
–
Reset mode (generation of WDT2RES signal)
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2 Clock
Selection.
2. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated. But, The overflow signal does not occur, even if the WDTM2 register is written
twice after the watch dog timer is suspended.
3. To stop the operation of watchdog timer 2 set the RSTP bit of the RCM register to 1 (to
stop Ring-OSC) and the WDTM2 register to 1FH.
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
Table 11-2. Watchdog Timer 2 Clock Selection
WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock 100 kHz (MIN.) 200 kHz (TYP.) 400 kHz (MAX.)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
212/fR
213/fR
214/fR
215/fR
216/fR
217/fR
218/fR
41.0 ms
20.5 ms
10.2 ms
20.5 ms
81.9 ms
41.0 ms
163.8 ms
327.7 ms
655.4 ms
1,310.7 ms
2,621.4 ms
81.9 ms
41.0 ms
163.8 ms
327.7 ms
655.4 ms
1,310.7 ms
2,621.47 ms
81.9 ms
163.8 ms
327.7 ms
655.4 ms
1,310.7 ms
fX = 5 MHz
219/fR (default) 5,242.9 ms
fX = 4 MHz
16.4 ms
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
216/fX
217fX
13.1 ms
32.8 ms
26.2 ms
52.4 ms
218/fX
219/fX
220/fX
221/fX
222/fX
223/fX
Stop
65.5 ms
131.1 ms
262.1 ms
524.3 ms
1,048.6 ms
2,097.2 ms
104.9 ms
209.7 ms
419.4 ms
838.9 ms
1,677.7 ms
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
(3) Watchdog timer enable register (WDTE)
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset input sets this register to 9AH.
After reset: 9AH
R/W
Address: FFFFF6D1H
WDTE
RUN2
RUN2 Selection of watchdog timer operation modeNote
RUN2
0
1
Counting stopped
Counter cleared and counting started
Note Once RUN2 is set to 1 it cannot be cleared to 0 by software. Therefore, counting can be stopped only by
RESET input after counting is started.
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
forcibly output.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
overflow signal is forcibly output (an error results in the assembler).
3. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
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Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2. The description focus on the V850ES/FJ2
12.1 Overview
This product features an A/D converter. The number of channels varies depending on the product as shown below.
Product Name
Number of
Channels
V850ES/FE2
10
12
16
24
V850ES/FF2
V850ES/FG2
V850ES/FJ2
12.2 Functions
The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle up
to 24 analog input signal channels (ANI0 to ANIn).
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
The A/D converter has the following features.
{ 10-bit resolution
{ 10, 12, 16 or 24 channels
{ Successive approximation method
{ Operating voltage: AVREF0 = 4.0 to 5.5 V
{ Analog input voltage: 0 V to AVREF0
{ The following functions are provided as operation modes.
• Continuous select mode
• Continuous scan mode
• One-shot scan mode
{ The following functions are provided as trigger modes.
• Software trigger mode
• External trigger mode (external, 1)
• Timer trigger mode
{ Power-fail monitor function (conversion result compare function)
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The block diagram of the A/D converter is shown below.
Figure 12-1. Block Diagram of A/D Converter
AVREF0
ADA0CE bit
ANI0
ANI1
ANI2
Sample & hold circuit
:
:
AVSS
ANI13
ANI14
ANI15
ADA0CE bit
Voltage
comparator
SAR
ADA0TMD1 bit
ADA0TMD0 bit
INTAD
INTTP2CC0
INTTP2CC1
ADA0PFE bit
ADA0PFC bit
Controller
Controller
ADA0CR0
ADA0CR1
ADA0CR2
Edge
ADTRG
detection
Voltage
comparator
ADA0ETS0 bit
ADA0ETS1 bit
:
:
ADA0CR22
ADA0CR23
ADA0M0
ADA0M1 ADA0M2 ADA0S
ADA0PFT ADA0PFM
Internal bus
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12.3 Configuration
The A/D converter includes the following hardware.
Table 12-1. Configuration of A/D Converter
Item
Configuration
Analog inputs
10 channels for V850ES/FE2 (ANI0 to ANI9 pins)
12 channels for V850ES/FF2 (ANI0 to ANI11 pins)
16 channels for V850ES/FG2 (ANI0 to ANI15 pins)
24 channels for V850ES/FJ2 (ANI0 to ANI23 pins)
Registers
Successive approximation register (SAR)
A/D conversion result registers
0 to 9 for V850ES/FE2 (ADA0CR0 to ADA0CR9)
0 to 11 for V850ES/FF2 (ADA0CR0 to ADA0CR11)
0 to 15 for V850ES/FG2 (ADA0CR0 to ADA0CR15)
0 to 23 for V850ES/FJ2 (ADA0CR0 to ADA0CR23)
A/D conversion result registers high where only higher 8 bits can be read
0H to 9H for V850ES/FE2 (ADA0CR0H to ADA0CR9H)
0H to 11H for V850ES/FF2 (ADA0CR0H to ADA0CR11H)
0H to 15H for V850ES/FG2 (ADA0CR0H to ADA0CR15H)
0H to 23H for V850ES/FJ2 (ADA0CR0H to ADA0CR23H)
Control registers
A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power-fail compare mode register (ADA0PFM)
Power-fail compare threshold value register (ADA0PFT)
(1) Successive approximation register (SAR)
The SAR register compares the voltage value of the analog input signal with the voltage tap (compare voltage)
value from the D/A converter, and holds the comparison result starting from the most significant bit (MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is
complete), the contents of the SAR register are transferred to the ADA0CRn register.
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
(2) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage during
A/D conversion.
(3) Voltage comparator
The voltage comparator compares a voltage value that has been sampled and held with the voltage value of
the D/A converter.
(4) D/A converter
This D/A converter is connected between AVREF0 and AVSS and generates a voltage for comparison with the
analog input signal.
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(5) ANIn pins
These are analog input pins for the A/D converter channels and are used to input analog signals to be
converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register can
be used as input port pins.
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
Cautions 1. Make sure that the voltages input to the ANI0 to ANI23 pins do not exceed the rated
values. In particular if a voltage of AVREF0 or higher is input to a channel, the
conversion value of that channel becomes undefined, and the conversion values of the
other channels may also be affected.
2. The analog input pins (ANI0 to ANI23) function alternately as input port pins (P70 to
P79, P710 to P715, P120 to P127). If any of ANI0 to ANI23 is selected and A/D converted,
do not execute an input instruction to ports 7 and 12 during conversion. If executed,
the conversion resolution may be degraded.
(6) AVREF0 pin
This is the pin used to input the reference voltage of the A/D converter. The signals input to the ANI0 to ANI23
pins are converted to digital signals based on the voltage applied between the AVREF0 and AVSS pins.
(7) AVSS pin
This is the ground pin of the A/D converter. Always make the potential at this pin the same as that at the VSS
pin even when the A/D converter is not used.
12.4 Control Registers
The A/D converter is controlled by the following registers.
•
•
•
A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power-fail compare mode register (ADA0PFM)
The following registers are also used.
•
•
•
A/D conversion result register n (ADA0CRn)
A/D conversion result register nH (ADA0CRnH)
Power-fail compare threshold value register (ADA0PFT)
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
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(1) A/D converter mode register 0 (ADA0M0)
The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations.
This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only.
Reset input clears this register to 00H.
After reset: 00H
R/W
0
Address: FFFFF200H
ADA0M0
ADA0CE
ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD ADA0EF
A/D conversion control
ADA0CE
0
1
Stops conversion
Enables conversion
Specification of A/D converter operation mode
Continuous select mode
ADA0MD1ADA0MD0
0
0
1
0
1
1
Continuous scan mode
One-shot scan mode
Setting prohibited
Other than above
Specification of external trigger (ADTRG pin) input valid edge
No edge detection
ADA0ETS1ADA0ETS0
0
0
1
1
0
1
0
1
Falling edge detection
Rising edge detection
Detection of both rising and falling edges
Trigger mode specification
ADA0TMD
0
1
Software trigger mode
External trigger mode/timer trigger mode
A/D converter status display
ADA0EF
0
1
A/D conversion stopped
A/D conversion in progress
Cautions 1. If bit 0 is written, this is ignored.
2. Changing the ADA0FR2 to ADA0FR0 bits of the ADA0M1 register
during conversion (ADA0CE0 bit = 1) is prohibited.
3. When not using the A/D converter, stop the operation by setting the
ADA0CE bit to 0 to reduce the current consumption.
4. The resolution of the first input terminal immediately after A/D
conversion can be decreased. For details, refer to 12. 6. (7) AVREF0
pin.
5. When the subclock is operating and the main clock is stopped,
accessing the ADA0M0 register is disabled. For details, see 3.4.10 (2).
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(2) A/D converter mode register 1 (ADA0M1)
The ADA0M1 register is an 8-bit register that controls the conversion time specification.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this bit to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF201H
5
0
4
0
3
2
1
0
ADA0M1 ADA0HS1 ADA0HS0
ADA0FR3 ADA0FR2 ADA0FR1 ADA0FR0
Caution Be sure to clear bits 5 and 4 to 0.
Remark For A/D conversion time setting examples, see Table 12-2.
Table 12-2. Conversion Mode Setting Example
A/D
A/D
A/D
ADA0HS ADA0FR3 to ADA0FR0
A/D Conversion time including sample time
fXX = 16 MHz fXX = 4 MHz
XX = 20 MHz
Conversion Sampling
Stabilization
TimeNote
1
1
0
x
3
2
1
0
f
Time
Time
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
31/fXX
8/fXX
Setting prohibited Setting prohibited 7.75 µs
16/fXX
31/fXX
62/fXX
16/fXX
24/fXX
32/fXX
40/fXX
48/fXX
56/fXX
64/fXX
72/fXX
80/fXX
88/fXX
96/fXX
104/fXX
112/fXX
120/fXX
128/fXX
3.10 µs
4.65 µs
6.20 µs
7.75 µs
9.30 µs
10.85 µs
12.40 µs
13.95 µs
15.50 µs
3.88 µs
5.81 µs
7.75 µs
9.69 µs
11.63 µs
13.56 µs
15.50 µs
15.50 µs
93/fXX
Setting prohibited 47/fXX
Setting prohibited 50/fXX
Setting prohibited 50/fXX
Setting prohibited 50/fXX
Setting prohibited 50/fXX
Setting prohibited 50/fXX
124/fXX
155/fXX
186/fXX
217/fXX
248/fXX
279/fXX
310/fXX
341/fXX
372/fXX
403/fXX
434/fXX
465/fXX
496/fXX
Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Setting prohibited Setting prohibited Setting prohibited 50/fXX
Note When the ADA0CE bit of the ADA0M0 register is changed from 0 to 1 to secure the A/D converter
stabilization time, the first A/D conversion starts after one of the above clock values is input.
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(3) A/D converter mode register (ADA0M2)
The ADA0M2 register specifies the hardware trigger mode.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
Address: FFFFF203H
6
0
5
0
4
0
3
0
2
0
1
0
ADA0M2
0
ADA0TMD1 ADA0TMD0
ADA0TMD1 ADA0TMD0
Specification of hardware trigger mode
External trigger mode (when ADTRG pin valid edge detected)
0
0
0
1
Timer trigger mode 0
(when INTTP2CC0 interrupt request generated)
1
1
Timer trigger mode 1
(when INTTP2CC1 interrupt request generated)
0
1
Setting prohibited
Caution Be sure to clear bits 7 to 2 to 0.
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(4) A/D converter channel specification register 0 (ADA0S)
The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF202H
5
0
4
3
2
1
0
ADA0S
0
0
ADA0S4 ADA0S3 ADA0S2 ADA0S1 ADA0S0
ADA0S4 ADA0S3 ADA0S2 ADA0S1 ADA0S0
Select mode
ANI0
Scan mode
ANI0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ANI1
ANI0, ANI1
ANI2
ANI0 to ANI2
ANI0 to ANI3
ANI0 to ANI4
ANI0 to ANI5
ANI0 to ANI6
ANI0 to ANI7
ANI0 to ANI8
ANI0 to ANI9
ANI0 to ANI10
ANI0 to ANI11
ANI0 to ANI12
ANI0 to ANI13
ANI0 to ANI14
ANI0 to ANI15
ANI0 to ANI16
ANI0 to ANI17
ANI0 to ANI18
ANI0 to ANI19
ANI0 to ANI20
ANI0 to ANI21
ANI0 to ANI22
ANI0 to ANI23
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ANI16
ANI17
ANI18
ANI19
ANI20
ANI21
ANI22
ANI23
Setting prohibited
Other than above
Remark ANI0 to ANI9 (V850ES/FE2)
ANI0 to ANI12 (V850ES/FF2)
ANI0 to ANI15 (V850ES/FG2)
ANI0 to ANI23 (V850ES/FJ2)
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(5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH)
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0CRn consist of n
registers. The ADA0CRn and ADA0CRnH registers are read-only, in 16-bit or 8-bit units. However, specify the
ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access. The 10 bits of the
conversion result are read from the higher 10 bits of the ADA0CRn register, and 0 is read from the lower 6 bits.
The higher 8 bits of the conversion result are read from the ADA0CRnH register.
After reset: 00H
R
Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H，
ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H
ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH
ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH
ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H
ADA0CR10 FFFFF224H, ADA0CR11 FFFFF226H
ADA0CR12 FFFFF228H, ADA0CR13 FFFFF22AH
ADA0CR14 FFFFF22CH, ADA0CR15 FFFFF22EH
ADA0CR16 FFFFF230H, ADA0CR17 FFFFF232H
ADA0CR18 FFFFF234H, ADA0CR19 FFFFF236H
ADA0CR20 FFFFF238H, ADA0CR21 FFFFF23AH
ADA0CR22 FFFFF23CH, ADA0CR23 FFFFF23EH
15
14
13
12
11
10
9
8
ADA0CRn
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
7
6
5
0
4
0
3
0
2
0
1
0
0
0
AD1
AD0
After reset: 00H
R
Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H
ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H
ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH
ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH
ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H
ADA0CR10H FFFFF225H, ADA0CR11H FFFFF227H
ADA0CR12H FFFFF229H, ADA0CR13H FFFFF22BH
ADA0CR14H FFFFF22DH, ADA0CR15H FFFFF22FH
ADA0CR16H FFFFF231H, ADA0CR17H FFFFF233H
ADA0CR18H FFFFF235H, ADA0CR19H FFFFF237H
ADA0CR20H FFFFF239H, ADA0CR21H FFFFF23BH
ADA0CR22H FFFFF23DH, ADA0CR23H FFFFF23FH
7
6
5
4
3
2
1
0
ADA0CRnH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
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Cautions 1. A write operation to the ADA0M0 and ADA0S registers may cause the contents of the
ADA0CRn register to become undefined. After the conversion, read the conversion result
before writing to the ADA0M0 and ADA0S registers. Correct conversion results may not be
read if a sequence other than the above is used.
2. When the subclock is operating and the main clock is stopped, accessing the ADA0CRn and
ADA0CRnH registers is disabled. For details, see 3.4.10 (2).
The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion
result (of A/D conversion result register n (ADA0CRn)) is as follows.
VIN
ADA0CR= INT (
× 1,024 + 0.5)
AVREF0
Or,
AVREF0
AVREF0
1,024
(ADA0CR− 0.5)×
≤ VIN < (ADA0CR+ 0.5)×
1,024
INT( ):
VIN:
Function that returns the integer of the value in ( )
Analog input voltage
AVREF0:
AVREF0 pin voltage
ADA0CR: Value of A/D conversion result register n (ADA0CRn)
Figure 12-2 shows the relationship between the analog input voltage and the A/D conversion results.
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Figure 12-2. Relationship Between Analog Input Voltage and A/D Conversion Results
1,023
1,022
A/D conversion
results (ADA0CRn)
1,021
3
2
1
0
1
1
3
2
5
3
2,043 1,022 2,0451,023 2,047
2,048 1,024 2,0481,024 2,048
1
2,048 1,024 2,048 1,024 2,048 1,024
Input voltage/AVREF0
Remark n = 0 to 11
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(6) Power-fail compare mode register (ADA0PFM)
The ADA0PFM register is an 8-bit register that sets the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
Address: FFFFF204H
6
5
0
4
0
3
0
2
0
1
0
0
0
ADA0PFM
ADA0PFE ADA0PFC
ADA0PFE
Selection of power-fail compare enable/disable
0
1
Power-fail compare disabled
Power-fail compare enabled
ADA0PFC
Selection of power-fail compare mode
0
1
Generates an interrupt request signal (INTAD) when ADA0CRn ≥ ADA0PFT
Generates an interrupt request signal (INTAD) when ADA0CRn < ADA0PFT
Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the
value of the ADA0CRnH register specified by the ADA0S register. If the result matches
the condition specified by the ADA0PFC bit, the conversion result is stored in the
ADA0CRn register and the INTAD signal is generated. If it does not match, however,
the interrupt signal is not generated.
2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the
contents of the ADA0CR0H register. If the result matches the condition specified by
the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the
INTAD signal is generated. If it does not match, however, the INTAD signal is not
generated. Regardless of the comparison result, the scan operation is continued and
the conversion result is stored in the ADA0CRn register until the scan operation is
completed. However, the INTAD signal is not generated after the scan operation has
been completed.
(7) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register
nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D
conversion result register (ADA0CRnH).
The ADA0PFT register sets the compare value in the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
Address: FFFFF205H
6
5
4
3
2
1
0
ADA0PFT
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12.5 Operation
12.5.1 Basic operation
<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the
ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set,
conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or
timer trigger mode.
<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
sample & hold circuit.
<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and
holds the input analog voltage until A/D conversion is complete.
<4> Set bit 9 of the successive approximation register (SAR). The voltage of the D/A converter is (1/2) AVREF0.
<5> The voltage difference between the voltage of the D/A converter and the analog input voltage is compared by
the voltage comparator. If the analog input voltage is higher than (1/2) AVREF0, the MSB of the SAR register
remains set. If it is lower than (1/2) AVREF0, the MSB is reset.
<6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the
value of bit 9, to which a result has been already set, <6>, the voltage of the D/A converter is selected as
follows.
• Bit 9 = 1: (3/4) AVREF0
• Bit 9 = 0: (1/4) AVREF0
This voltage of the D/A converter and the analog input voltage are compared and, depending on the result, bit
8 is manipulated as follows.
• Analog input voltage ≧ Voltage of the D/A converter
• Analog input voltage ≦ Voltage of the D/A converter
<7> This comparison is continued to bit 0 of the SAR register.
<8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then
transferred to and stored in the ADA0CRn register. At the same time, an A/D conversion end interrupt request
signal (INTAD) is generated.
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Figure 12-3. A/D Converter Basic Operation
Conversion time
A/D conversion
Sampling time
Sampling
A/D converter
operation
Conversion
result
SAR
Undefined
Conversion
result
ADA0CRn
INTAD
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12.5.2 Trigger mode
The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a
software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1,
and external trigger mode. The ADA0TMD bit of the ADA0M0 register is used to set the trigger mode. The hardware
trigger modes are set by the ADA0TMD1 and ADA0TMD0 bits of the ADA0M2 register.
(1) Software trigger mode
When the ADA0CE bit of the ADA0M0 register is set to 1, the signal of the analog input pin (ANI0 to ANI23 pin)
specified by the ADA0S register is converted. When conversion is complete, the result is stored in the
ADA0CRn register. At the same time, the A/D conversion end interrupt request signal (INTAD) is generated.
If the operation mode specified by the ADA0MD1 and ADA0MD0 bits of the ADA0M0 register is the continuous
select/scan mode, the next conversion is started, unless the ADA0CE bit is cleared to 0 after completion of the
first conversion.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress).
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion
is aborted and started again from the beginning.
(2) External trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI23) specified by the ADA0S register is
started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be
detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the
ADA0ETS1 and ATA0ETS0 bits of the ADA0M0 register. When the ADA0CE bit of the ADA0M0 register set to
1, the A/D converter waits for the trigger, and starts conversion after the external trigger has been input.
When conversion is completed, the result of conversion is stored in the ADA0CRn register. At the same time,
the A/D conversion end interrupt request signal (INTAD) is generated, and the A/D converter waits for the
trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation,
the conversion is not aborted, and the A/D converter waits for the trigger again.
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(3) Timer trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI23) specified by the ADA0S register is
started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare
register connected to the timer. The timer compare match interrupt request signal (INTTP2CC0 or
INTTP2CC1) is selected by the ADA0TMD1 and ADA0TMD0 bits of the ADA0M2 register, and conversion is
started at the rising edge of the specified compare match interrupt request signal. When the ADA0CE bit of the
ADA0M0 register is set to 1, the A/D converter waits for a trigger, and starts conversion when the compare
match interrupt signal of the timer is input.
When conversion is completed, the result of the conversion is stored in the ADA0CRn register. At the same
time, the A/D conversion end interrupt request signal (INTAD) is generated, and the A/D converter waits for the
trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion
is stopped and the A/D converter waits for the trigger again.
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12.5.3 Operation mode
Three operation modes are available as the modes in which to set the ANI0 to ANI23 pins: continuous select mode
continuous scan mode and one-shot scan mode.
The operation mode is selected by the ADA0MD1 and ADA0MD0 bits of the ADA0M0 register.
(1) Continuous select mode
In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into
a digital value.
The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode,
an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is
completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of
conversion, the next conversion is started, unless the ADA0CE bit of the ADA0M0 register is cleared to 0 (n = 0
to 23).
Figure 12-4. Timing Example of Continuous Select Mode Operation (ADA0S = 01H)
ANI1
Data 4
Data 5
Data 1
Data 2
Data 3
Data 6
Data 7
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 5
Data 6
(ANI1)
Data 7
(ANI1)
A/D conversion
(ANI1)
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 6
(ANI1)
ADA0CR1
INTAD
Conversion start
Conversion start
Set ADA0CE bit = 1
Set ADA0CE bit = 1
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(2) Continuous scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are converted into digital values.
The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When
conversion of the analog input pin specified by the ADA0S register is complete, the A/D conversion end
interrupt request signal (INTAD) is generated, and A/D conversion is started again from the ANI0 pin, unless
the ADA0CE bit of the ADA0M0 register is cleared to 0 (n = 0 to 23).
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Figure 12-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
Data 7
(ANI2)
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
ADA0CRn
INTAD
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ANI0
ANI1
ANI2
ANI3
ANI4
A/D converter
ANI5
.
.
.
.
.
.
.
ADA0CR21
ADA0CR22
ADA0CR23
ANI21
ANI22
ANI23
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(3) One-shot scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are converted into digital values. The result of each conversion is stored in the
ADA0CRn register corresponding to the analog input pin. When conversion of the analog input pin specified by
the ADA0S register is complete, the A/D conversion end interrupt request signal (INTAD) is generated, and A/D
conversion is stopped.
Figure 12-6. Timing Example of One-shot Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
ADA0CRn
INTAD
Transformation
completion
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ANI0
ANI1
ANI2
ANI3
ANI4
A/D converter
ANI5
.
.
.
.
.
.
.
ADA0CR21
ADA0CR22
ADA0CR23
ANI21
ANI22
ANI23
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12.5.4 Power-fail compare mode
The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and
ADA0PFT registers.
• When the ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of
the A/D converter).
• When the ADA0PFE bit = 1 and when the ADA0PFC bit = 0, the value of the ADA0CRnH register is compared
with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if
ADA0CR0H ≥ ADA0PFT.
• When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared
with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if
ADA0CR0H < ADA0PFT.
Remark n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
In the power-fail compare mode, two modes are available as modes in which to set the ANI0 to ANI23 pins:
continuous select mode and continuous scan mode.
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(1) Continuous select mode
In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is
compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the
condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD
signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the
INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless
the ADA0CE bit of the ADA0M0 register is cleared to 0 (n = 0 to 23).
Figure 12-7. Timing Example of Continuous Select Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 01H)
ANI1
Data 4
Data 5
Data 1
Data 2
Data 3
Data 6
Data 7
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 5
Data 6
(ANI1)
Data 7
(ANI1)
A/D conversion
(
ANI1)
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 6
(ANI1)
ADA0CR1
INTAD
ADA0PFT ADA0PFT ADA0PFT ADA0PFT
unmatch unmatch match match
ADA0PFT
match
Conversion start
Set ADA0CE bit = 1
Conversion start
Set ADA0CE bit = 1
(2) Continuous scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0
pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of
channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches
the condition set by the ADA0PFC bit of the ADA0PFM register, the conversion result is stored in the ADA0CR0
register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the
ADA0CR0 register, and the INTAD signal is not generated.
After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially
converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously
stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the
ADA0CE bit of the ADA0M0 register is cleared to 0.
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Figure 12-8. Timing Example of Continuous Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
Data 7
(ANI2)
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
ADA0CRn
INTAD
ADA0PFT
match
ADA0PFT
unmatch
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ANI0
ANI1
ANI2
ANI3
ANI4
A/D converter
ANI5
.
.
.
.
.
.
.
ADA0CR21
ADA0CR22
ADA0CR23
ANI21
ANI22
ANI23
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(3) One-shot scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0
pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of
channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches
the condition set by the ADA0PFC bit of the ADA0PFM register, the conversion result is stored in the ADA0CR0
register, and the INTAD signal is generated. If it does not match, the conversion result is stored in the
ADA0CR0 register, and the INTAD signal is not generated.
After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially
converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously
stored.
After completion of conversion, A/D conversion is stopped. The 1st conversion result after A/D conversion has
to be ignored, because it is not good.
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Figure 12-9. Timing Example of One-shot Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
ANI0
Data 1
Data 5
ANI1
Data 6
Data 2
Data 7
Data 3
ANI2
ANI3
Data 4
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
ADA0CRn
INTAD
ADA0PFT
match
Conversion
completion
Conversion start
Set ADA0CE bit = 1
(b) Block diagram
Analog input pin
ADA0CRn register
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ANI0
ANI1
ANI2
ANI3
ANI4
A/D converter
ANI5
.
.
.
.
.
.
.
ADA0CR21
ADA0CR22
ADA0CR23
ANI21
ANI22
ANI23
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12.6 Cautions
(1) When A/D converter is not used
When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0CE bit of the
ADA0M0 register to 0.
(2) Input range of ANI0 to ANI23 pins
Input the voltage within the specified range to the ANI0 to ANI23 pins. If a voltage equal to or higher than
AVREF0 or equal to or lower than AVSS (even within the range of the absolute maximum ratings) is input to any of
these pins, the conversion value of that channel is undefined, and the conversion value of the other channels
may also be affected.
(3) Countermeasures against noise
To maintain the 10-bit resolution, the ANI0 to ANI23 pins must be effectively protected from noise. The
influence of noise increases as the output impedance of the analog input source becomes higher. To lower the
noise, connecting an external capacitor as shown in Figure 12-10 is recommended.
Figure 12-10. Processing of Analog Input Pin
VDD
AVREF0
C = 100 to 1,000 pF
AVSS
GND0
(4) Alternate I/O
The analog input pins (ANI0 to ANI23) function alternately as port pins. When selecting one of the ANI0 to
ANI23 pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output
port during conversion as the conversion resolution may drop.
Also the conversion resolution may drop at the pins set as output port pins during A/D conversion if the output
current fluctuates due to the effect of the external circuit connected to the port pins.
If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D
conversion value may not be as expected due to the influence of coupling noise. Therefore, do not apply a
pulse to a pin adjacent to the pin undergoing A/D conversion.
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(5) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the
analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected
analog input signal may be stored and the conversion end interrupt request flag may be set immediately before
the ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the
ADIF flag may be set even though the A/D conversion of the newly selected analog input pin has not been
completed. When A/D conversion is stopped, clear the ADIF flag before resuming conversion.
Figure 12-11. Generation Timing of A/D Conversion End Interrupt Request
ADA0S rewriting
ADA0S rewriting
ADIF is set, but ANIm
(ANIn conversion start)
(ANIm conversion start)
conversion does not end
ANIn
ANIn
ANIm
ANIm
A/D conversion
ADA0CRn
INTAD
ANIn
ANIn
ANIm
ANIm
Remark n = 0 to 23
m = 0 to 23
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(6) Internal equivalent circuit
The following shows the equivalent circuit of the analog input block.
Figure 13-14. Internal Equivalent Circuit of ANIn Pin
RIN
ANIn
CIN
Product Name
RIN
CIN
V850ES/FE2, FF2, FG2
V850ES/FJ2
5.9 kΩ
6.0 kΩ
7.0 pF
8.3 pF
Remarks
1. The above values are reference values.
2. n = 0 to 9 (V850ES/FE2)
n = 0 to 11 (V850ES/FF2)
n = 0 to 15 (V850ES/FG2)
n = 0 to 23 (V850ES/FJ2)
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(7) AVREF0 pin
(a) The AVREF0 pin is used as the power supply pin of the A/D converter and also supplies power to the
alternate-function ports. In an application where a backup power supply is used, be sure to supply the
same voltage as VDD to the AVREF0 pin as shown in Figure 12-10.
(b) The AVREF0 pin is also used as the reference voltage pin of the A/D converter. If the source supplying
power to the AVREF0 pin has a high impedance or if the power supply has a low current supply capability,
the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately
after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy
may drop. To avoid this, it is recommended to connect a capacitor across the AVREF0 and AVSS pins to
suppress the reference voltage fluctuation as shown in Figure 12-12.
(c) If the source supplying power to the AVREF0 pin has a high DC resistance (for example, because of
insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when
conversion is stopped, because of a voltage drop caused by the A/D conversion current.
Figure 12-12. AVREF0 Pin Processing Example
Note
AVREF0
Main power supply
AVSS
Note Parasitic inductance
(8) Reading ADA0CRn register
When the ADA0M0 to ADA0M2 or ADA0S register is written, the contents of the ADA0CRn register may be
undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to
ADA0M2 and ADA0S registers. The correct conversion result may not be read at a timing different from the
above.
(9) Standby mode
Because the A/D converter stops operating in the STOP mode, conversion results are invalid, so power
consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D
conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP
mode is released, before setting the STOP mode or releasing the STOP mode, clear the ADA0M0.ADA0CE bit
to 0 then set the ADA0CE bit to 1 after releasing the STOP mode.
In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower the power consumption,
therefore, clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage
value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid.
The results of conversions before the IDLE1 and IDLE2 modes were set are valid.
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(10) About A/D conversion result
The illegal conversion result sometimes occur by noise, in the case that the analogue input pin and also
reference voltage input pin receive the influence of noise. The software processing is necessary; to avoid that
exerts bad influence to the system by this illegal conversion result. Next the example of software processing is
shown.
• Please use the mean value of A/D conversion result of the plural time as the result of A/D conversion.
• In the case that does A/D conversion of the plural time continuously and the specific conversion result was
obtained, please use the conversion result that is excluded this value.
• Please do abnormal processing after abnormal occurrence is confirmed once again, without doing abnormal
processing right away, in the case that A/D conversion result that is judged that abnormality occurred to the
system was obtained.
(11) A/D conversion result hysteresis characteristics
The successive comparison type A/D converter holds the analog input voltage in the internal sample & holds
capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage
remains in the internal sample & hold capacitor. As a result, the following phenomena may occur.
• When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D
conversion, then hysteresis characteristics may appear where the conversion result is affected by the
previous value. Thus, even if the conversion is performed at the same potential, the result may vary.
• When switching the analog input channel, hysteresis characteristics may appear where the conversion
result is affected by the previous channel value. This is because one A/D converter is used for the A/D
conversions. Thus, even if the conversion is performed at the same potential, the result may vary.
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12.7 How to Read A/D Converter Characteristics Table
This section describes the terms related to the A/D converter.
(1) Resolution
The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of
digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR
(full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage,
and can be expressed as follows, independently of the resolution.
1%FSR = (Maximum value of convertible analog input voltage – Minimum value of convertible analog
input voltage)/100
= (AVREF0 − 0)/100
= AVREF0/100
When the resolution is 10 bits, 1 LSB is as follows:
1 LSB = 1/210 = 1/1,024
= 0.098%FSR
The accuracy is determined by the overall error, independently of the resolution.
(2) Overall error
This is the maximum value of the difference between an actually measured value and a theoretical value.
It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors.
The overall error in the characteristics table does not include the quantization error.
Figure 12-13. Overall Error
......
1
1
Ideal line
Overall error
......
0
0
0
AVREF0
Analog input
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(3) Quantization error
This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value.
Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes,
a quantization error is unavoidable.
This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or
differential linearity error in the characteristics table.
Figure 12-14. Quantization Error
......
1
1
1/2 LSB
Quantization error
1/2 LSB
......
0
0
0
AVREF0
Analog input
(4) Zero-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the
digital output changes from 0…000 to 0…001 (1/2 LSB).
Figure 12-15. Zero-Scale Error
111
Ideal line
100
Zero-scale error
011
010
001
000
−1
0
1
2
3
AVREF0
Analog input (LSB)
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(5) Full-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the
digital output changes from 1…110 to 0…111 (full scale − 3/2 LSB).
Figure 12-16. Full-Scale Error
Full-scale error
111
100
011
010
000
0
AVREF0
−
3
AVREF0
−
2
AVREF0
−
1
AVREF0
Analog input (LSB)
(6) Differential linearity error
Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually
measured value and its theoretical value when a specific code is output.
Figure 12-17. Differential Linearity Error
......
1
1
Ideal width of 1 LSB
Differential
linearity error
......
0
0
AVREF0
Analog input
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(7) Integral linearity error
This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It
indicates the maximum value of the difference between the actually measured value and its theoretical value
where the zero-scale error and full-scale error are 0.
Figure 12-18. Integral Linearity Error
......
1
1
Ideal line
Integral
linearity error
......
0
0
0
AVREF0
Analog input
(8) Conversion time
This is the time required to obtain a digital output after an analog input voltage has been assigned.
The conversion time in the characteristics table includes the sampling time.
(9) Sampling time
This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit.
Figure 12-19. Sampling Time
A/D conversion start
A/D conversion end
Sampling time
Conversion time
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Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
The V850ES/Fx2 includes asynchronous serial interface A (UARTA).
The number of channels differs depending on the product. Table 13-1 shows the number of channels of each
product.
Table 13-1. Number of Channels of Asynchronous Serial Interface A
Product Name (Part Number)
V850ES/FE2
Number of Channels
2 (UARTA0 to UARTA1)
V850ES/FF2
V850ES/FG2
3 (UARTA0 to UARTA2)
3 (UARTA0 to UARTA2)
4 (UARTA0 to UARTA3)
V850ES/FJ2
µPD70F3237
µPD70F3238
µPD70F3239
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
13.1 Features
• Transfer rate
300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated baud
rate generator)
• Full-duplex communication UARTA receive data register n (UAnRX)
UARTA transmit data register n (UAnTX)
• 2-pin configuration
TXDAn: Output pin of transmit data
RXDAn: Input pin of receive data
• Reception error detection function
• Parity error
• Framing error
• Overrun error
• Interrupt sources: 2 types
• Reception complete interrupt (INTUAnR): An interrupt is generated in the reception enabled status by ORing
three types of reception errors. It is also generated when receive data is transferred from the shift register to
receive buffer register n after completion of serial transfer.
• Transmission enable interrupt (INTUAnT): Generated when transmit data is transferred from the transmit buffer
register to the shift register in the transmission enabled status.
• Character length: 7 or 8 bits
• Parity function: Odd, even, 0, none
• Transmission stop bit: 1 or 2 bits
• Dedicated baud rate generator
• MSB/LSB first transfer selectable
• Transmit/receive data reversible
• 13 to 20 bits selectable for SBF (Sync Break Field) transmission in LIN (Local Interconnect Network)
communication format
• 11 or more bits recognizable for SBF reception in LIN communication format
• SBF reception flag
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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13.2 Configuration
UARTA consists of the following hard ware
Table 13-2. configuration of UARTA0 to UARTA2
Item
Configuration
UARTAn reception shift register
Register
UARTAn reception data register (UAnRX)
UARTAn transmit shift register
UARTAn transmit data register (UAnTX)
µ PD70F3237: 3 (RXDAn)
Reception data input
Transmit data output
µPD70F3239: 4
µ PD70F3237: 3 (TXDAn)
µ PD70F3239: 4
Baud rateNote clock input
Control register
1 (ASCKA0)
UARTAn control register (UAnCTL0 to UAnCTL3)
UARTAn option control register (UAnOPT0)
UARTAn status register (UAnSTR)
Note IN the baud rate clock input which is supported only for UARTA0
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
The pins of asynchronous serial interface A (UARTA) function alternately as port pins. For how to select the
alternate functions, refer to the description of registers in CHAPTER 4 PORT FUNCTIONS.
Table 13-3. List of Pins of Asynchronous Serial Interface A
Pin Name Alternate-Function Pin
I/O
Function
RXDA0
RXDA1
RXDA2
RXDA3
TXDA0
TXDA1
TXDA2
TXDA3
ASCKA0
P31/INTP7
P91/KR7
P39/INTP8
P80/INTP14
P30
Input
Serial receive data input (UARTA0)
Serial receive data input (UARTA1)
Serial receive data input (UARTA2)
Serial receive data input (UARTA3)
Serial transmit data output (UARTA0)
Serial transmit data output (UARTA1)
Serial transmit data output (UARTA2)
Serial transmit data output (UARTA3)
Baud rate clock input of UARTA0
Output
P90/KR6
P38
P81
P32/TIP00/TOP00
Input
Remark The number of channels differs depending on the product.
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Figure 13-1. Block Diagram of Asynchronous Serial Interface A
Internal bus
INTUAnT
INTUAnR
Reception unit
Transmission unit
UAnRX
UAnTX
Transmit
shift register
Receive shift
register
Reception
controller
Transmission
controller
Filter
Baud rate
generator
Baud rate
generator
Selector
TXDAn
RXDAn
Selector
f
XX to fXX/210
ASCKA0
UAnCTL1
UAnCTL2
UAnCTL0
UAnSTR
UAnOTP0
Internal bus
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
Note: UARTA0 only.
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13.2.1 Control registers
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that specifies the operation of the asynchronous serial interface A.
(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is an 8-bit register that selects the input clock of the asynchronous serial interface A.
(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is an 8-bit register that controls the baud rate of the asynchronous serial interface A.
(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register that controls serial transfer by the asynchronous serial interface A.
(5) UARTAn status register (UAnSTR)
The UAnSTR register is a collection of flags that indicate the contents of the error when a reception error
occurs. The corresponding reception error flag is set to 1 when a reception error occurs, and is reset to 0
when the UAnSTR register is read.
(6) UARTAn receive shift register
This shift register converts the serial data input to the RXDAn pin into parallel data. When data of 1 byte is
received and then a stop bit is detected, the receive data is transferred to the UAnRX register.
This register cannot be directly manipulated.
(7) UARTAn receive data register (UAnRX)
The UAnRX register is an 8-bit buffer register that holds receive data. When seven characters are received, 0
is stored in the higher bit (in LSB-first reception).
While reception is enabled, receive data is transferred from the UARTAn receive shift register to the UAnRX
register in synchronization with completion of shift-in processing of one frame.
When the data has been transferred to the UAnRX register, a reception complete interrupt request signal
(INTUAnR) is generated.
(8) UARTAn transmit shift register
The transmit shift register converts the parallel data transferred from the UAnTX register into serial data.
When data of 1 byte is transferred from the UAnTX register, the data of the shift register is output from the
TXDAn pin.
This register cannot be directly manipulated.
(9) UARTAn transmit data register (UAnTX)
The UAnTX register is an 8-bit buffer for transmit data. By writing transmit data to the UAnTX register, a
transmission operation is started. When data can be written to the UAnTX register (when data of one frame is
transferred from the UAnTX register to the UARTAn transmit shift register), a transmission enable interrupt
request signal (INTUAnT) is generated.
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13.3 Control Registers
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the serial transfer operation of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 10H.
(1/2)
After reset: 10H
R/W
Address: UA0CTL0: FFFFFA00H, UA1CTL0: FFFFFA10H,
UA2CTL0: FFFFFA20H, UA3CTL0: FFFFFA30H
7
6
5
4
3
2
1
0
UAnCTL0 UAnPWR
UAnTXE
UAnRXE
UAnDIR
UAnPS1
UAnPS0
UAnCL
UAnSL
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
UAnPWR
Control of operation of UARTAn
0
1
Disable clock operation (asynchronously reset UARTAn).
Enable clock operation.
The UAnPWR bit controls the operating clock and asynchronously resets UARTAn. When this bit is
cleared to 0, the output of the TXDAn pin is fixed to the high level.
UAnTXE
Transmission operation enable
Stop transmission operation.
Enable transmission operation.
0
1
When the UAnTDL bit is cleared to 0, then the UAnTXE bit is cleared to 0, the output of the TXDAn
pin is fixed to the high level.
When the UAnTDL bit is set to 1, then the UAnTXE bit is set to 0, the output of the TXDAn pin is
fixed to the low level.
This bit is synchronized with the operating clock. When the transmission unit is initialized, therefore,
set the UAnTXE bit from 0 to 1. The transmission operation will be enabled two clocks later.
A value written to the UAnTXE bit is ignored when the UAnPWR bit = 0.
UAnRXE
Reception operation enable
0
1
Stop reception operation.
Enable reception operation.
When the UAnRXE bit is cleared to 0, the reception operation is stopped. Consequently, even if
specified data is transferred, the reception complete interrupt is not output, and the UAnRX register
is not updated.
The UAnRXE bit is synchronized with the operating clock. When the reception unit is initialized,
therefore, set the UAnRXE bit from 0 to 1. The reception operation will be enabled two clocks later.
A value written to the UAnRXE bit is ignored when the UAnPWR bit = 0.
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UAnDIR
Selection of transfer direction mode (MSB/LSB)
0
1
MSB first
LSB first
This bit can be rewritten only when the UAnPWR bit = 0 or when UAnTXE bit = UAnRXE bit = 0.
・ Set the UA0DIR bits to "1" to execute transmission/reception in LIN format.
UAnPS1
UAnPS0
Selection of parity for transmission
No parity output
Selection of parity for reception
Reception without parity
Reception with 0 parity
0
0
1
1
0
1
0
1
Output 0 parity
Output odd parity
Identified as odd parity
Output even parity
Identified as even parity
• This bit can be rewritten only when the UAnPWR bit = 0 or when the UAnTXE bit = UAnRXE bit
= 0.
• If “Reception with 0 parity” is selected for reception, the parity is not identified.
Consequently, the UAnPE bit of the UAnSTR register is not set, and an error interrupt is not
generated even if a parity error occurs.
• Clear the UAnPS1 and UAnPS0 bits to “00” to execute transmission/reception in LIN format.
UAnCL
Specification of data character length of one frame of transmit/receive data.
0
1
7 bits
8 bits
This bit can be rewritten only when the UAnPWR bit = 0 or when the UAnTXE bit = UAnRXE bit = 0.
・ Set the UA0CL bits to "1" to execute transmission/reception in LIN format.
UAnSL
Specification of stop bit length of transmit data.
0
1
1 bit
2 bits
This bit can be rewritten only when the UAnPWR bit = 0 or when the UAnTXE bit = UAnRXE bit = 0.
Remark For details of the parity, refer to 13.5.9 Types and operation of parity.
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(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is an 8-bit register that selects the clock of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: UA0CTL1: FFFFFA01H, UA1CTL1: FFFFFA11H,
UA2CTL1: FFFFFA21H, UA3CTL1: FFFFFA31H
7
0
6
0
5
0
4
0
3
2
1
0
UAnCTL1
UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0
Selection of base clock (fXCLK)
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
fXX
0
fXX/2
0
fXX/4
0
fXX/8
0
fXX/16
0
fXX/32
0
fXX/64
0
fXX/128
1
fXX/256
1
fXX/512
1
fXX/1024
1
External clockNote (ASCKA0 pin)
Other than above
Setting prohibited
Note The ASCKA0 pin can be used only when UARTA0 is used. Setting this bit is prohibited when UARTA1 to
UARTA3 are used.
Caution This register can be rewritten only when the UAnPWR bit of the UAnCTL0 register = 0.
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(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is used to select the baud rate (serial transfer rate) clock of UARTAn.
This register can be read or written in 8-bit units.
Reset input sets this register to FFH.
After reset: FFH R/W
Address: UA0CTL2: FFFFFA02H, UA1CTL2: FFFFFA12H,
UA2CTL2: FFFFFA22H, UA3CTL2: FFFFFA32H
7
6
5
4
3
2
1
0
UAnCTL2
UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
Rated
Serial clock
UAnBRS7 UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0
value (k)
0
0
0
0
0
0
×
×
×
Setting
prohibited
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
1
1
1
:
0
0
1
:
0
1
0
:
4
5
fXCLK/4
fXCLK/5
6
fXCLK/6
:
:
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
fXCLK/252
fXCLK/253
fXCLK/254
fXCLK/255
Remarks: 1.
fXCLK is the frequency of the base clock selected by the UAnCTL1 register.
2. Refer to Table 13.6 about setting samples of fxclk.
3. ×: Don't care
Cautions 1. This register can be rewritten only when the UAnPWR bit of the UAnCTL0 register = 0 or
when the UAnTXE bit = UAnRXE bit = 0.
2. The baud rate is the serial clock divided by two.
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(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 14H.
After reset: 14H
R/W
Address: UA0OPT0: FFFFFA03H, UA1OPT0: FFFFFA13H,
UA2OPT0: FFFFFA23H, UA3OPT0: FFFFFA33H
7
6
5
4
3
2
1
0
UAnOPT0 UAnSFR
UAnSRT
UAnSTT
UAnSLS2 UAnSLS1 UAnSLS0
UAnTDL
UAnRDL
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
UAnSFR
0
SBF reception flag
When UAnCTL0 register’s UAnPWR bit = UAnRXE bit = 0. Or, on normal completion of
SBF reception
1
SBF reception in progress
• This bit indicates that SBF (Sync Brake Field) is received in LIN communication.
• In case of an SBF reception error, the UAnSRF bit is hold to 1, and then SBF reception is started
again.
• The UAnSFR bit can only be read.
UAnSRT
SBF reception trigger
―
0
1
SBF reception trigger
• This is the reception trigger bit of SBF in LIN communication. It is always 0 when read. To receive
SBF, set the UAnSRT bit to 1 to enable SBF reception.
• Set the UAnPWR bit and UAnRXE bit of the UAnCTL0 register to 1 and then set the UAnSRT bit.
UAnSTT
SBF transmission trigger
―
0
1
SBF transmission trigger
• This is the transmission trigger bit of SBF in LIN communication. It is always 0 when read.
• Set the UAnPWR bit and UAnTXE bit of the UAnCTL0 register to 1 and then set the UAnSTT bit.
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UAnSLS2 UAnSLS1 UAnSLS0
SBF length selection
Outputs 13 bits (reset value).
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Outputs 14 bits.
Outputs 15 bits.
Outputs 16 bits.
Outputs 17 bits.
Outputs 18 bits.
Outputs 19 bits.
Outputs 20 bits.
This bit can be set when the UAnPWR bit of the UAnCTL0 register = 0 or when the UAnTXE bit of
the UAnCTL0 register = 0.
UAnTDL
Transmit data level bit
0
1
Normal output of transfer data
Inverted output of transfer data
• The value of the TXDAn bit can be inverted by the UAnTDL bit.
• This bit can be set when the UAnPWR bit of the UAnCTL0 register = 0 or when the UAnTXE bit of
the UAnCTL0 register = 0.
UAnRDL
Receive data level bit
0
1
Normal input of transfer data
Inverted input of transfer data
• The value of the RXDAn pin can be inverted by the UAnRDL bit.
• This bit can be set when the UAnPWR bit of the UAnCTL0 register = 0 or when the UAnRXE bit of
the UAnCTL0 register = 0.
Remark For details of the parity, refer to 13.5.9 Types and operation of parity.
(5) UARTAn status register (UAnSTR)
The UAnSTR register is an 8-bit register that indicates the transfer status of UARTAn and the contents of a
reception error.
This bit can be read or written in 8-bit or 1-bit units, but the UAnTSF bit can only be read. The UAnPE, UAnFE,
and UAnOVE bits can be read or written, but they can only be cleared by writing 0 to them, and cannot be set
by writing 1 (if 1 is written to these bits, they hold the current status).
The following table shows the initialization conditions of these bits.
Register/Bit
UAnSTR register
Initialization Conditions
• Reset input
• UAnPWR bit of UAnCTL0 register = 0
UAnTSF bit
• UAnTXE bit of UAnCTL0 register = 0
UAnPE, UAnFE, UAnOVE bits
• Writing of 0
• UAnRXE bit of UAnCTL0 register = 0
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After reset: 00H
R/W
Address: UA0STR: FFFFFA04H, UA1STR: FFFFFA14H,
UA2STR: FFFFFA24H, UA3STR: FFFFFA34H
7
UAnSTR UAnTSF
6
0
5
0
4
0
3
0
2
1
0
UAnPE
UAnFE
UAnOVE
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
UAnTSF
0
Transfer status flag
• When UAnPWR bit of UAnCTL0 register = 0 or when UAnTXE bit of UAnCTL0
register = 0
• If next transfer data is not in UAnTX after completion of transfer
1
Writing to UAnTX register
The UAnTSF bit is always 1 when transmission is executed continuously. Before initializing the
transmission unit, check that the UAnTSF bit = 0. If the transmission unit is initialized while the
UAnTSF bit = 1, the transmit data cannot be guaranteed.
UAnPE
0
Parity error flag
• When UAnPWR bit of UAnCTL0 register = 0 or when UAnRXE bit of UAnCTL0
register = 0
• When 0 is written to this bit
1
When the parity of the received data does not match the parity bit
• The operation of the UAnPE bit differs depending on how the UAnPS1 and UAnPS0 bits of the
UAnCTL0 register are set.
• Although the UAnPE bit can be read or written, it can only be cleared by writing 0, and cannot be
set by writing 1. It holds the current status when 1 is written.
UAnFE
0
Framing error flag
• When UAnPWR bit of UAnCTL0 register = 0 or when UAnRXE bit of UAnCTL0
register = 0
• When 0 is written
1
When a stop bit is not detected on reception
• Only the first bit of the receive data is checked as a stop bit, regardless of the value of the UAnSL
bit of the UAnCTL0 register.
• Although the UAnFE bit can be read or written, it can only be cleared by writing 0, and cannot be
set by writing 1. It holds the current status when 1 is written.
UAnOVE
0
Overrun error flag
• When UAnPWR bit of UAnCTL0 register = 0 or when UAnRXE bit of UAnCTL0
register = 0
• When 0 is written
1
When receive data is set to the UAnRX register and the next reception operation is
completed before that data is read
• If an overrun error occurs, the next receive data is not written to the receive buffer but discarded.
• Although the UAnOVE bit can be read or written, it can only be cleared by writing 0, and cannot
be set by writing 1. It holds the current status when 1 is written.
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(6) UARTAn receive data register (UAnRX)
The UAnRX register is an 8-bit buffer register that stores the parallel data converted by the receive shift register.
On completion of reception of 1 byte of data, the data stored in the receive shift register is transferred to the
UAnRX register.
If the data length is specified to be 7 bits and when data is received with the LSB first, the receive data is
transferred to bits 6 to 0 of the UAnRX register, and the MSB is always 0. If data is received with the MSB first,
the receive data is transferred to bits 7 to 1 of the UAnRX register, and the LSB is always 0.
If an overrun error (UAnOVE) occurs, the receive data at that time is not transferred to the UAnRX register.
The UAnRX register is read-only, in 8-bit units.
Reset input and setting the UAnPWR bit of the UAnCTL0 register to 0 set this register to FFH.
After reset: FFH
R
Address: UA0RX: FFFFFA06H, UA1RX: FFFFFA16H,
UA2RX: FFFFFA26H, UA3RX: FFFFFA36H
7
6
5
4
3
0
1
2
UAnRX
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
(7) UARTAn transmit data register (UAnTX)
The UAnTX register is an 8-bit register that sets transmit data.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to FFH.
After reset: FFH
R/W
Address: UA0TX: FFFFFA07H, UA1TX: FFFFFA17H,
UA2TX: FFFFFA27H, UA3TX: FFFFFA37H
7
6
5
4
3
2
1
0
UAnTX
n = 0 to 1 (V850ES/FE2,V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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13.4 Interrupt Request Signals
UARTAn generates the following two types of interrupt request signals.
• Reception complete interrupt request signal (INTUAnR)
• Transmission enable interrupt request signal (INTUAnT)
Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by
default, and the priority of the transmission enable interrupt request signal is lower.
Table 13-4. Interrupts and Their Default Priority
Interrupt
Priority
High
Reception complete
Transmission enable
Low
(1) Reception complete interrupt request signal (INTUAnR)
When data is shifted in to the receive shift register with reception enabled, and transferred to the UAnRX
register, the reception complete interrupt request signal is generated.
A reception error interrupt can also be generated in this interrupt request signal if a reception error occurs.
Moreover, read the UAnSTR register to check that the result of reception is not an error.
Reception complete interrupt request signals are not generated while reception is disabled.
(2) Transmission enable interrupt request signal (INTUAnT)
The transmission enable interrupt request signal is generated when transmit data is transferred from the
UAnTX register to the UARTAn transmit shift register with transmission enabled.
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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13.5 Operation
13.5.1 Data format
Full-duplex serial data is transmitted or received.
The transmit/receive data is in the format shown in Figure 13-2, consisting of a start bit, character bits, a parity bit,
and 1 or 2 stop bits.
The character bit length in one data frame, parity, stop bit length, and whether data is transferred with the MSB or
LSB first, are specified by the UAnCTL0 register.
The UAnTDL bit of the UAnOPT0 register is used to specify whether the signal output from the TXDAn pin is
inverted or not.
• Start bit
… 1 bit
• Character bit … 7 or 8 bits
• Parity bit
• Stop bit
… Even parity, odd parity, 0 parity, or no parity
… 1 or 2 bits
Figure 13-2. Format of Transmit/Receive Data of UARTA
(a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
Stop
bit
Parity
bit
D0
D1
D2
D3
D4
D5
D6
D7
(b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
Parity Stop
D7
D6
D5
D4
D3
D2
D1
D0
bit
bit
(c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inverted
1 data frame
Start
bit
Parity Stop
D7
D6
D5
D4
D3
D2
D1
D0
bit
bit
(d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H
1 data frame
Start
bit
Parity Stop Stop
D0
D1
D2
D3
D4
D5
D6
bit
bit
bit
(e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H
1 data frame
Start
bit
Stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
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13.5.2 SBF transmission/reception format
The V850ES/Fx2 has an SBF (Sync Break Field) transmission/reception control function as a LIN (Local
Interconnect Network) function.
Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
intended to aid the cost reduction of an automotive network. LIN communication is single-master
communication, and up to 15 slaves can be connected to the LIN master via the LIN network. Normally, the
LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is
±15% or less.
Figure 13-3. Outline of Transmission Operation of LIN
Wakeup
signal
frame
Sync
break
field
Check
sum
field
Sync
field
Ident
field
DATA
field
DATA
field
Sleep
bus
Note 3
8 bits
Note 2
13 bits
55H
transmission
Data
Data
Data
Data
Note 1
transmission transmission transmission transmission
TXDAn (output)
Note 4
SBF transmission
INTUAnT
interrupt
Notes 1. The interval between each field is controlled by software.
2. SBF is output by hardware. The output width is the bit length specified by the UAnSBL2 to UAnSBL0 bits
of the UAnOPT0 register. If the output width must be adjusted more finely, the UAnBRST7 to UAnBRS0
bits of the UAnCTLn register can be used.
3. The wakeup signal frame is substituted by 80H transfer in the 8-bit mode.
4. A transmission enable interrupt request signal (INTUAnT) is output each time transmission is started. The
INTUAnT signal is also output when SBF transmission is started.
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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Figure 13-4. Outline of Reception Operation of LIN
Wakeup
signal
frame
Sync
break
field
Check
sum
field
Sync
field
DATA
field
DATA
field
Ident
field
Sleep
bus
Note 5
DATA
reception
Note 2
13 bits
DATA
reception
DATA
reception
SF reception
ID reception
SBF
reception
Disable
Enable
RXDAn (intput)
Note 3
Reception interrupt (INTUAnR)
Note 1
Edge detection
Note 4
Capture timer
Disable
Enable
Notes 1. The wakeup signal is detected by the edge detector of the pin, and enables UARTAn and places it in the
SBF reception mode.
2. Reception is performed until the STOP bit is detected. When SBF reception of 11 bits or more is
detected, it is assumed that normal SBF reception has been completed, and the interrupt signal is output.
If SBF reception of less than 11 bits is detected, it is assumed that an SBF reception error has occurred.
No interrupt signal is output and UARTAn returns to the SBF reception mode.
3. When SBF reception is completed normally, the interrupt signal is output. The SBF reception complete
interrupt enables a timer. Error detection by the UAnOVE, UAnPE, and UAnFE bits of the UAnSTR
register is suppressed. Consequently, neither error detection processing of UART communication nor
data transfer from the UARTAn receive shift register to UAnRX register is executed. The UARTAn receive
shift register holds the default value FFH.
4. The RXDAn pin is connected to TI (capture input) of the timer and the transfer rate and baud rate error
are calculated. After SF reception, UARTAn is no longer enabled. The value with the baud rate error
corrected is set to the UAnCTL2 register to enable reception.
5. The checksum field is distinguished by software. After CSF reception, UARTAn is initialized and the SBF
mode is set again by software.
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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13.5.3 SBF transmission
Transmission is enabled when the UAnPWR bit and UAnTXE bit of the UAnCTL0 register are set to 1, and SBF
transmission is started by setting the SBF transmission trigger (UAnSTT bit of the UAnOPT0 register) to 1.
After that, a 13-bit to 20-bit low level, as specified by the UAnSLS2 to UAnSLS0 bits of the UAnOPT0 register, is
output. A transmission enable interrupt request signal (INTUAnT) is generated when SBF transmission is started.
After SBF transmission is completed, the UAnSTT bit is automatically cleared, and the UART transmission mode is
restored.
The transmission operation is stopped until the data to be transmitted next is written to the UAnTX register or the
SBF transmission trigger (UAnSTT bit) is set.
Cautions 1. This macro becomes error when SBF is transmitted with data reception because it doesn't
assume the thing that SBF is transmitted while receiving data.
2. Set (1) neither SBF reception trigger bit （UAnSRT） nor SBF transmission trigger bit
(UAnSTT) while receiving SBF (UAnSRF = 1).
Figure 13-5. SBF Transmission
Stop
bit
1
2
3
4
5
6
7
8
9
10 11 12 13
INTUAnT
interrupt
UAnSTT bit is set.
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13.5.4 SBF reception
When the UAnPWR bit of the UAnCTL0 register is set to 1 and then the UAnRX bit of the UAnCTL0 register is set
to 1, UARTA waits for reception.
When the SBF reception trigger (UAnSRT bit of the UAnOPT0 register) is set to 1, UARTA waits for SBF reception.
In the SBF reception waiting status, the RXDAn pin is monitored and the start bit is detected, in the same manner
as in the reception wait status of UART.
When the start bit is detected, reception is started, and the internal counter counts up at the selected baud rate.
When the stop bit is received, a reception complete interrupt request signal (INTUAnR) is generated as normal
processing, if the width of SBF is 11 bits or longer. The UAnSRF bit of the UAnOPT0 register is automatically cleared,
and SBF reception is completed. Error detection by the UAnOVE, UAnPE, and UAnFE bits of the UAnSTR register is
suppressed, and error detection processing of UART communication is not performed. Moreover, data is not
transferred from the UARTAn receive shift register to the UAnRX register, and the UAnRX register holds the default
value FFH. If the width of SBF is 10 bits or less, the interrupt does not occur, reception is completed, and the SBF
reception mode is restored again, as error processing. At this time, the UAnSRF bit is not cleared.
Figure 13-6. SBF Reception
(a) Normal SBF reception (STOP bit is detected when SBF width exceeds 10.5 bits)
1
2
3
4
5
6
7
8
9
10 11
11.5
UAnSRF
INTUAnR
interrupt
(b) SBF reception error (STOP bit is detected when SBF width is 10.5 bits or less)
1
2
3
4
5
6
7
8
9
10
10.5
UA0SRF
INTUAnR
interrupt
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13.5.5 UART transmission
When the UAnPWR bit of the UAnCTL0 register is set to 1, the TXDAn pin outputs a high level.
If the UAnTXE bit of the UAnCTL0 register is subsequently set to 1, transmission is enabled. Transmission is
started by writing transmit data to the UAnTX register. A start bit, parity bit, and stop bit are automatically appended to
the transmit data.
When transmission is started, the data in the UAnTX register is transferred to the UARTAn transmit shift register.
As soon as the data of the UAnTX register has been transferred to the UARTAn transmit shift register, a
transmission enable interrupt request signal (INTUAnT) is generated. Then the UARTAn transmit shift register
sequentially outputs the data to the TXDAn pin, starting from the LSB. When the INTUAnT signal is generated, writing
the next transfer data to the UAnTX register is enabled.
By writing the data to be transmitted next to the UAnTX register during transfer, transmission can be continuously
executed.
Figure 13-7. UART Transmission
Start
bit
Parity
bit
Stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
INTUAnT
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13.5.6 Procedure of continuous transmission
With UARTAn, the next transmit data can be written to the UAnTX register as soon as the UARTAn transmit shift
register has started its shift operation. The timing at which data is transferred to the UARTAn transmit shift register
can be identified by the transmission enable interrupt request signal (INTUAnT). The INTUAnT signal enables
continuous transmission even while an interrupt is being serviced after transmission of 1 data frame, so that an
efficient communication rate can be realized.
During continuous transmission, do not write the next transmit data to the UAnTX register before a transmit request
interrupt signal (INTUAnT) is generated after transmit data is written to the UAnTX register and transferred to the
UARTAn transmit shift register. If a value is written to the UAnTX register before a transmit request interrupt signal is
generated, the previously set transmit data is overwritten by the latest transmit data.
Caution Continuous transmission operating (UAnTSF bit is 1), can not change register. While continuous
transmission is being executed, execute initialization after checking that the UAnTSF bit is 0. If
initialization is executed while the UAnTSF bit is 1, the transmit data cannot be guaranteed.
The communication rate from the stop bit to the following start bit expands more than usually for
two clocks of the operation clock at a continuous transmission.
Figure 13-8. Processing Flow of Continuous Transfer
Start
Set registers.
Write UAnTX.
No
Transmission interrupt occurred?
Yes
No
Necessary number
of data written?
Yes
End
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Figure 13-9. Timing of Continuous Transmission Operation
(a) Start of transfer
Start
Data (1)
Parity Stop
Data (2)
Start
Data (2)
Parity Stop
Data (3)
Start
TXDAn
UAnTX
Data (1)
Transmit
shift
Data (2)
Data (1)
register
INTUAnT
UAnTSF
(b) End of transfer
Stop
Parity
UATTXD
Parity
Stop
Start
Data (n-1) Parity Stop
Start
Data (n)
UAnTX
Data (n-1)
Data (n)
Transmit
shift
Data (n-1)
Data (n)
FF
register
INTUAnT
UAnTSF
UAnPWR or UAnTXE
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13.5.7 UART reception
When the UAnPWR bit of the UAnCTL0 register is set to 1 and then the UAnRX bit of the UAnCTL0 register is set
to 1, UARTA waits for reception. In the reception wait status, the RXDAn pin is monitored and the start bit is detected.
To recognize the start bit, a two-stage detection routine is used.
First the falling edge of the RXDAn pin is detected and sampling is started. The start bit is recognized if the RXDAn
pin is low level at the start bit sampling point. When the start bit is recognized, reception is started, and serial data is
sequentially stored in the UARTAn receive shift register at the selected baud rate.
When the stop bit is received, a reception complete interrupt request signal (INTUAnR) is generated and, at the
same time, the data of the UARTAn receive shift register is written to the UAnRX register. If an overrun error occurs
(indicated by the UAnOVE bit of the UAnSTR register), the receive data is not written to the UAnRX register.
Even if a parity error (indicated by the UAnPE bit of the UAnSTR register) or framing error (indicated by the UAnFE
bit of the UAnSTR register) occurs in the middle of reception, reception continues to the reception position of the stop
bit. The INTUAnR signal is generated when reception is completed.
Figure 13-10. UART Reception
Start
bit
Stop
bit
Parity
bit
D0
D1
D2
D3
D4
D5
D6
D7
INTUAnR
UAnRX
Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. Unless the UAnRX
register is read, an overrun error occurs when the next data is received, and the reception
error status persists.
2. It is always assumed that the number of stop bits is 1 during reception. A second stop bit is
ignored.
3. When reception is completed, read the UAnRX register after the reception complete interrupt
request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If
the UAnPWR or UAnRXE bit is cleared to 0 before the NTUAnR signal is generated, the read
value of the UAnRX register cannot be guaranteed.
4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit
= 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being
no data stored in the UAnRX register. To complete reception without waiting INTUAnR signal
generation, be sure to clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register,
after setting (1) the interrupt mask flag (UAnRMK) of the interrupt control register (UAnRIC)
and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0.
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13.5.8 Reception errors
Reception errors are classified into three types: parity errors, framing errors, and overrun errors. As a result of
receiving data, an error flag is set in the UAnSTR register, and a reception complete interrupt request signal
(INTUAnR) is generated.
By reading the contents of the UAnSTR register in the reception error interrupt servicing, which error has occurred
during reception can be checked.
The reception error flag is cleared by writing 0 to it.
• Receive data read flow
Figure 13-11. Receive data read flow
START
No
INTUAnR signal
generated?
Yes
Read UAnRX register
Read UAnSTR register
No
Error occurs?
Yes
Error processing
END
Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors.
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•
Reception error causes
Table 13-5. Reception Error Causes
Error Flag
UAnPE
Reception Error
Parity error
Cause
Received parity bit does not match setting.
Stop bit is not detected.
UAnFE
Framing error
Overrun error
UAnOVE
Next data reception is completed before data is read from receive
buffer.
When reception errors occur, perform the following procedures depending upon the kind of error.
•
Parity error
If false data is received due to problems such as noise in the reception line, discard the received data and
retransmit.
•
Framing error
A baud rate error may have occurred between the reception side and transmission side or the start bit may have
been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in
the transmission side, perform initialization processing each other, and then start the communication again.
•
Overrun error
Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was
needed, do a retransmission.
Caution If a receive error interrupt occurs during continuous reception, read the contents of the UAnSTR
register must be read before the next reception is completed, and then perform error processing.
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13.5.9 Types and operation of parity
Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to “00”.
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on
both the transmission side and reception side.
Even parity and odd parity can be used to detect a “1” bit error (odd number). With zero parity and no parity, no
errors are detected.
(1) Even parity
(a) During transmission
The number of bits that are “1” in the transmit data, including the parity bit, is controlled to be even. The
value of the parity bit is as follows.
• Number of bits that are “1” in transmit data is odd: 1
• Number of bits that are “1” in transmit data is even: 0
(b) During reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a parity
error occurs.
(2) Odd parity
(a) During transmission
Opposite to even parity, the number of bits that are “1” in the transmit data, including the parity bit, is
controlled to be odd. The value of the parity bit is as follows.
• Number of bits that are “1” in transmit data is odd: 0
• Number of bits that are “1” in transmit data is even: 1
(b) During reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a parity
error occurs.
(3) 0 parity
The parity bit is cleared to 0 during transmission, regardless of the transmit data.
The parity bit is not checked during reception. Therefore, a parity error does not occur regardless of whether
the parity bit is 0 or 1.
(4) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit. Because no parity bit is used, a parity error does
not occur.
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13.5.10 Noise filter of receive data
The RXDAn pin is sampled using the UART internal clock (fXCLK).
When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled
as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal
circuit (see Figure 13-13). See 13.6 (1) (a) Base clock regarding the base clock.
Moreover, since the circuit is as shown in Figure 13-12, the processing that goes on within the receive operation is
delayed by 3 clocks in relation to the external signal status.
Figure 13-12. Noise Filter Circuit
Base clock (fXCLK
)
Internal signal A
Internal signal B
In
Q
RXDAn
In
Q
I
n
Q
Internal signal C
Match
detector
LD_EN
Figure 13-13. Timing of RXDAn Signal Judged as Noise
Base clock
RXDAn (input)
Internal signal A
Internal signal B
Match
Match
Mismatch
Mismatch
(judged as noise)
(judged as noise)
Internal signal C
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13.6 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector and 8-bit programmable counters, and
generates a serial clock for transmission/reception by UARTAn. The output of the dedicated baud rate generator can
be selected as the serial clock on a channel by channel basis.
8-bit counters are provided separately for transmission and reception.
(1) Configuration of baud rate generator
Figure 13-14. Configuration of Baud Rate Generator
UAnPWR
f
XX
f
f
f
XX/2
XX/4
XX/8
UAnPWR, UAnTXEn (UAnRXE)
8-bit counter
f
f
f
XX/16
XX/32
XX/64
Clock
(fXCLK)
Selector
f
f
f
XX/128
XX/256
XX/512
f
XX/1024
Match detector
Baud rate
1/2
ASCKA0Note
UAnCTL1:
UAnCTL2:
UAnCKS3 to UAnCKS0
UAnBRS7 to UAnBRS0
Note The ASCKA0 pin can be used only for UARTA0. It cannot be used for UARTA1 to UARTA3.
Remarks 1. n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
2. fXX: Internal system clock
3. fXCLK = Base clock frequency
(a) Base clock
The clock selected by the UAnCKS3 to UAnCKS0 bits of the UAnCTL1 register is supplied to the 8-bit
counter when the UAnPWR bit of the UAnCTL0 register is 1. This clock is called the base clock, and its
frequency is called fXCLK.
(b) Generation of serial clock
A serial clock can be generated in accordance with the setting of the UAnCTL1 and UAnCTL2 registers
The base clock is selected by using the UAnCKS3 to UAnCKS0 bits of the UAnCTL1 register.
The division ratio of the 8-bit counter can be selected by using the UAnBRS7 to UAnBRS0 bits of the
UAnCTL2 register.
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(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is used to select the clock for UARTAn.
For details, refer to 13.3 (2) UARTAn control register 1 (UAnCTL1).
(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is used to select the baud rate (serial transfer rate) clock for UARTAn.
For details, refer to 13.3 (3) UARTAn control register 2 (UAnCTL2).
(4) Baud rate
The baud rate can be calculated by the following expression.
fXCLK
Baud rate =
[bps]
2 × k
fXCLK = Frequency of base clock selected by UAnCKS3 to UAnCKS0 bits of UAnCTL1 register
k = Value set by UAnBRS7 to UAnBRS0 bits of UAnCTL2 register (k = 4, 5, 6, …, 255)
(5) Error of baud rate
The baud rate error is calculated by the following expression.
Actual baud rate (baud rate with error)
Error (%) =
− 1 × 100 [%]
Target baud rate (correct baud rate)
fXCLK
=
− 1 × 100 [%]
2 × k × Target baud rate
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
receiving side.
2. The baud rate error during reception must satisfy the range indicated in (7)
Permissible baud rate range for reception.
Example: Frequency of base clock = 20 MHz = 20,000,000 Hz
Set value of UAnBRS7 to UAnBRS0 bits of UAnCTL2 register = 01000001B (k = 65)
Target baud rate = 153,600 bps
Baud rate = 20,000,000/ (2 × 65)
= 153,846 [bps]
Error = (153,846/153,600 – 1) × 100
= 0.160 [%]
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(6) Example of baud rate setting
Table 13-6. Baud Rate Generator Set Data
Baud Rate
(bps)
fXX = 20 MHz
UAnCTL1 UAnCTL2
fXX = 16 MHz
fXX = 10 MHz
ERR (%)
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
0.00
UAnCTL1 UAnCTL2
ERR (%)
0.16
UAnCTL1 UAnCTL2
ERR (%)
0.16
300
600
09H
08H
07H
06H
05H
04H
03H
01H
01H
00H
00H
00H
41H
41H
41H
41H
41H
41H
41H
A0H
82H
82H
41H
20H
0AH
0AH
09H
08H
07H
06H
05H
01H
00H
00H
00H
00H
1AH
0DH
0DH
0DH
0DH
0DH
0DH
80H
D0H
68H
34H
1AH
08H
07H
06H
05H
04H
03H
02H
00H
00H
00H
00H
00H
41H
41H
41H
41H
41H
41H
41H
A0H
82H
41H
21H
10H
0.16
0.16
1200
0.16
0.16
2,400
0.16
0.16
4,800
0.16
0.16
9,600
0.16
0.16
19,200
31,250
38,400
76,800
153,600
312,500
0.16
0.16
0.00
0.00
0.16
0.16
0.16
0.16
0.16
–1.36
0.00
–1.54
Remarks: 1. fXX: Internal system clock
ERR: Baud rate error [%]
2. n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
(7) Permissible baud rate range for reception
The permissible baud rate error during reception is shown below.
Caution Be sure to set the baud rate error for reception to within the permissible error range, by
using the expressions shown below.
Figure 13-15. Permissible Baud Rate Range for Reception
Latch
timing
Transfer rate
of UARTAn
Start bit
Start bit
Start bit
Bit 0
FL
Bit 1
Bit 7
Parity bit
Stop bit
1 data frame (11 × FL)
Permissible
minimum
transfer rate
Bit 0
Bit 1
Bit 7
Parity bit Stop bit
FLmin
Permissible
maximum
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
transfer rate
FLmax
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2)
n = 0 to 2 (V850ES/FG2, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
As shown in Figure 13-15, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
1
FL = (Brate)−
Brate: UARTAn baud rate (n = 0 to 3)
k:
Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
1-bit data length
FL:
Latch timing margin: 2 clocks
k − 2
21k + 2
2k
Minimum allowable transfer rate: FLmin = 11 × FL −
× FL =
FL
2k
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Therefore, the maximum baud rate that can be received by the destination is as follows.
22k
1
BRmax = (FLmin/11)−
=
Brate
21k + 2
Similarly, obtaining the following maximum allowable transfer rate yields the following.
10
11
21k − 2
2 × k
k + 2
× FLmax = 11 × FL −
× FL =
FL
2 × k
21k − 2
FLmax =
FL × 11
20 k
Therefore, the minimum baud rate that can be received by the destination is as follows.
20k
1
BRmin = (FLmax/11)−
=
Brate
21k − 2
Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for
obtaining the minimum and maximum baud rate values yields the following.
Table 13-7. Maximum/Minimum Allowable Baud Rate Error
Division Ratio (k)
Maximum Allowable Baud Rate Error
Minimum Allowable Baud Rate Error
4
+2.32%
+3.52%
+4.26%
+4.56%
+4.66%
+4.72%
−2.43%
−3.61%
−4.30%
−4.58%
−4.67%
−4.72%
8
20
50
100
255
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock
frequency, and the division ratio (k). The higher the input clock frequency
and the larger the division ratio (k), the higher the accuracy.
2. k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
(8) Transfer rate for continuous transmission
The transfer rate from the stop bit to the start bit of the next data is extended two clocks when continuous
transmission is executed. However, the timing on the reception side is initialized when the start bit is detected,
and therefore, the transfer result is not affected.
Figure 13-16. Transfer Rate for Continuous Transmission
Start bit in
1 data frame
second byte
Start bit
FL
Bit 0
FL
Bit 1
FL
Bit 7
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Bit 0
FL
Where 1 bit data length is FL, stop bit length is FLstp, and base clock frequency is fXCLK, the stop bit length can
be calculated by the following expression.
FLstp = FL + 2/fXCLK
Therefore, the transfer rate for continuous transmission is as follows.
Transfer rate = 11 x FL + 2/fXCLK
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
13.7 Cautions
(1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation
stops with each register retaining the value it had immediately before the clock supply was stopped. The
TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply
is resumed, the circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and
UAnCTL0.UAnTXEn bits to 000.
(2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear
PFCE91 bit to 0).
(3) In UARTAn, the interrupt caused by a communication error does not occur. When performing the transfer of
transmit data and receive data using DMA transfer, error processing cannot be performed even if errors
(parity, overrun, framing) occur during transfer. Either read the UAnSTR register after DMA transfer has been
completed to make sure that there are no errors, or read the UAnSTR register during communication to check
for errors.
(4) Start up the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1.
(5) Stop the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if port setting is not changed).
(6) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value
to the UAnTX register by software because transmission starts by writing to this register. To transmit the same
value continuously, overwrite the same value.
(7) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base
clocks more than usual. However, the reception side initializes the timing by detecting the start bit, so the
reception result is not affected.
(8) When break command is based and UARTA receives data for on-chip debug mode, over run error is occurred.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
The V850ES/Fx2 includes a 3-wire serial interface (CSIB).
The number of channels differs depending on the product. Following table shows the number of channels of each
product.
Table 14-1. Number of Channels of 3-wire serial interface B
Product Name (Part Number)
V850ES/FE2
Number of Channels
2 (CSIB0 to CSIB1)
V850ES/FF2
V850ES/FG2
V850ES/FJ2
3 (CSIB0 to CSIB2)
14.1 Features
• Master mode and slave mode selectable
• 3-wire serial interface for 8-bit to 16-bit transfer
• Interrupt request signals (INTCBnT and INTCBnR)
• Serial clock and data phase selectable
• Transfer data length selectable from 8 to 16 bits in 1-bit units
• Data transfer with MSB- or LSB-first selectable
• 3-wire SOBn: Serial data output
SIBn:
Serial data input
SCKBn: Serial clock I/O
• Transmission mode, reception mode, and transmission/reception mode selectable
• Transfer rate : 8 Mbps - 4.9 kbps (fxx=20 MHz, using internal clock)
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2, V850ES/FG2)
n = 0 to 2 (V850ES/FJ2)
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14.2 Configuration
CSIBn consists of the following hardware
Table 14-2. configuration of CSIBn
Item
Configuration
CSIBn reception data register (CBnRX)
CSIBn transmit data register (CBnTX)
SIBn
Register
Reception data input
Transmit data output
Serial clock I/O
SOBn
SCKBn
Control register
CSIBn control register (CBnCTL0 to CBnCTL2)
CSIBn status register (CBnSTR)
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2, V850ES/FG2)
n = 0 to 2 (V850ES/FJ2)
The pins of the 3-wire serial interface (CSIBn) function alternately as port pins. For how to select the alternate
function, refer to the descriptions of the registers in CHAPTER 4 PORT FUNCTIONS.
Table 14-3. List of 3-Wire Serial Interface Pins
Pin Name Alternate-Function Pin
I/O
Function
Serial receive data input (CSIB0)
Serial receive data input (CSIB1)
Serial receive data input (CSIB2)
Serial transmit data input (CSIB0)
Serial transmit data input (CSIB1)
Serial transmit data input (CSIB2)
Serial clock I/O (CSIB0)
SIB0
P40
Input
SIB1
P97/TIP20/TOP20
SIB2
P910
P41
SOB0
SOB1
SOB2
SCKB0
SCKB1
SCKB2
Output
I/O
P98
P911
P42
P99
Serial clock I/O (CSIB1)
P912
Serial clock I/O (CSIB2)
Remark The number of channels differs depending on the product.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
Figure 14-1. Block Diagram of 3-Wire Serial Interface
Internal bus
CBnCTL1
CBnCTL0
CBnSTR
Controller
CBnCTL2
INTCBnT
INTCBnR
f
f
f
XX/2
XX/4
XX/8
f
f
f
XX/16
XX/32
XX/64
Phase control
CBnTX
f
BRG (n = 0)
TOP01 (n = 1)
XX/128 (n = 2)
f
SCKBn
SIBn
Phase
control
SO latch
SOBn
Shift register
CBnRX
Remark n = 0 to 1 (V850ES/FE2, V850ES/FF2, V850ES/FG2)
n = 0 to 2 (V850ES/FJ2)
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(1) CSIBn receive data register (CBnRX)
The CBnRX register is a 16-bit buffer register that holds receive data.
This register is read-only, in 16-bit units.
If reception is enabled, a reception operation is started when the CBnRX register is read.
If the transfer data length is 8 bits, the lower 8 bits of the CBnRX register are read-only in 8-bit units as the
CBnRXL register.
Reset input clears this register to 0000H.
In addition to reset input, the CBnRX register can be initialized by clearing (to 0) the CBnPWR bit of the
CBnCTL0 register.
After reset: 0000H
R
Address: CB0RX: FFFFFD04H, CB1RX: FFFFFD14H,
CB2RX: FFFFFD24H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CBnRX
(n = 0 to 2)
(2) CSIBn transmit data register (CBnTX)
The CBnTX register is a 16-bit buffer register to which transfer data of CSIB is written.
This register can be read or written in 16-bit units.
If transmission is enabled, a transmission operation is started when the CBnTX register is written.
If the transfer data length is 8 bits, the lower 8 bits of the CBnTX register can be read or written in 8-bit units as
the CBnTXL register.
Reset input clears this register to 0000H.
After reset: 0000H
R/W Address: CB0TX: FFFFFD06H, CB1TX: FFFFFD16H,
CB2TX: FFFFFD26H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CBnTX
(n = 0 to 2)
Remark The communication start conditions are shown below.
Transmission mode (CBnTXE bit = 1, CBnRXE bit = 0):
Write to CBnTX register
Transmission/reception mode (CBnTXE bit = 1, CBnRXE bit = 1): Write to CBnTX register
Reception mode (CBnTXE bit = 0, CBnRXE bit = 1):
Read from CBnRX register
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.3 Control Registers
(1) CSIBn control register 0 (CBnCTL0)
This register controls the serial transfer operation of CSIB.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 01H.
(1/2)
After reset: 01H
R/W
Address: CB0CTL0: FFFFFD00H, CB1CTL0: FFFFFD10H,
CB2CTL0: FFFFFD20H
7
6
5
4
3
0
2
0
1
0
CBnTXENote1 CBnRXENote1 CBnDIRNote1
CBnTMSNote1
CBnCTL0 CBnPWR
CBnSCE
(n = 0 to 2)
CBnPWR
Specification of CSIB operation stop or enable
Stop clock operation (asynchronously reset CSIBn).
Enable clock operation.
0
1
The CBnPWR bit controls the operating clock of CSIB and resets the internal circuit.
CBnTXENote1
Specification of transmission operation stop or enable
0
1
Stop transmission.
Enable transmission.
When the CBxTXE bit is cleared to 0, the serial output pin SOBn is fixed to the low level and
communication is stopped.
CBnRXENote1
Reception operation enable
0
1
Stop reception.
Enable reception.
When the CBnRXE bit is cleared to 0, because reception is stopped, the reception complete
interrupt is not output and the receive data in the CBnRX register is not updated even if the specified
data is transferred.
CBnDIRNote1
Specification of transfer direction mode (MSB/LSB)
0
1
MSB first
LSB first
CBnTMSNote1
Specification of transfer mode
0
1
Single transfer mode
Continuous transfer mode
When the CBnTMS bit = 0, the single transfer mode is set in which continuous
transmission/reception is not supported. Even when only transmission is executed, an interrupt is
output on completion of reception transfer.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(2/2)
CBnSCE
Specification of start transfer disable or enable
Disable transfer operation.
0
1
Enable transfer operation.
• In master mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous transmission or
continuous transmission/reception mode
A communication operation can be started only by writing data to the CBnTX register when
the CBnSCE bit is 1.
Set the CBnSCE bit to 1.
(b) In single reception mode
Clear the CBnSCE bit to 0 before reading the last receive data because reception is started
by reading the receive data (CBnRX register)Note 2 to disable the reception startup.
(c) In continuous reception mode
Clear the CBnSCE bit to 0 one communication clock before reception of the last data is
completed to disable the reception startup after the last data is receivedNote 3
.
• In slave mode
This bit enables or disables the communication start trigger.
Set the CBnSCE bit to 1.
[Usage of CBnSCE bit]
• In single reception mode
<1> When reception of the last data is completed by INTCBnR interrupt servicing, clear the
CBnSCE bit to 0 before reading the CBnRX register.
<2> After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to disable reception.
To continue reception, set the CBnSCE bit to 1 to start up the next reception by dummy-
reading the CBnRX register.
• In continuous reception mode
<1> Clear the CBnSCE bit to 0 during the reception of the last data by INTCBnR interrupt
servicing.
<2> Read the CBnRX register.
<3> Read the last reception data by reading the CBnRX register after acknowledging the CBnTIR
interrupt.
<4> After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to disable reception.
To continue reception, set the CBnSCE bit to 1 to wait for the next reception by dummy-
reading the CBnRX register.
Notes 1. These bits can only be rewritten when the CBnPWR bit = 0. However, the CBnPWR can be set to
1 at the same time as these bits are rewritten.
2. If the CBnSCE bit is read while it is 1, the next communication operation is started.
3. The CBnSCE bit is not cleared to 0 one communication clock before the completion of the last
data reception, the next communication operation is automatically started.
Caution 1: To forcibly suspend transmission/reception, clear the CBnPWR bit instead of the CBnRXE bit
and the CBnTXE bit to 0. At this time, the clock output is stopped.
2: Be sure to clear bits 3 and 2 to 0.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(2) CSIBn control register 1 (CBnCTL1)
This is an 8-bit register that selects the transmission/reception timing and input clock of CSIBn.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when the
CBnTXE and CBnRXE bits are 0.
After reset: 00H
R/W
Address: CB0CTL1: FFFFFD01H, CB1CTL1: FFFFFD11H,
CB2CTL1: FFFFFD21H
7
0
6
0
5
0
4
3
2
1
0
CBnCTL1
CBnCKP
CBnDAP CBnCKS2 CBnCKS1 CBnCKS0
(n = 0 to 2)
CBnCKP
0
CBnDAP
0
Specification of transmission/reception timing of data of SCKBn
SCKBn (I/O)
D7
D6
D5
D4
D3
D2
D1
D0
SOBn (output)
SIBn capture
0
1
1
1
0
1
SCKBn (I/O)
SOBn (output)
SIBn capture
D7
D6
D5
D4
D3
D2
D1
D0
SCKBn (I/O)
D7
D6
D5
D4
D3
D2
D1
D0
SOBn (output)
SIBn capture
SCKBn (I/O)
SOBn (output)
SIBn capture
D7
D6
D5
D4
D3
D2
D1
D0
CBnCKS2 CBnCKS1 CBnCKS0
Input clock
n = 1
Mode
n = 0
n = 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
XX/2
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
XX/4
XX/8
XX/16
XX/32
XX/64
Note
BRG
TMP0(TOP01) fXX/128
External clock (SCKBn)
Note fBRG: Output clock frequency of prescaler 3
For details of the prescaler, refer to 14.8 Prescaler 3.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(3) CSIBn control register 2 (CBnCTL2)
This is an 8-bit register that controls the number of serial transfer bits of CSIB.
It can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution The CBnCTL2 register can be rewritten when the CBnPWR bit of the CBnCTL0 register = 0 or
when the CB0TXE and CB0RXE bits = 0.
After reset: 00H
R/W
Address: CB0CTL2: FFFFFD02H, CB1CTL2: FFFFFD12H,
CB2CTL2: FFFFFD22H
7
0
6
0
5
0
4
0
3
2
1
0
CBnCTL2
CBnCL3
CBnCL2
CBnCL1
CBnCL0
(n = 0 to 2)
CBnCL3
CBnCL2
CBnCL1
CBnCL0
Bit length of serial register
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
8 bits
9 bits
10 bits
11 bits
12 bits
13 bits
14 bits
15 bits
16 bits
Caution If the number of transfer bits is not 8 or 16, prepare data, justifying it to the least significant bit of
the CBnTX or CBnRX register.
Remark. ×: don’t care
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(4) CSIBn status register (CBnSTR)
This is an 8-bit register that indicates the status of CSIB.
Although this register can be read or written in 8-bit or 1-bit units, the CBnTSF flag is read-only.
Reset input clears this register to 00H.
Clearing the CBnPWR bit of the CBnCTL0 register to 0 also initializes this register.
After reset: 00H
R/W
Address: CB0STR: FFFFFD03H, CB1STR: FFFFFD13H,
CB2STR: FFFFFD23H
7
CBnSTR CBnTSF
(n = 0 to 2)
6
0
5
0
4
0
3
0
2
0
1
0
0
CBnOVE
CBnTSF
Communication status flag
0
1
Communication stopped
Communicating
This bit is set when data is prepared in the CBnTX register for transmission. It is set when dummy
data is read from the CBnRX register for reception.
It is cleared when the edge of the last clock is completed.
CBnOVE
Overrun error flag
0
1
No overrun
Overrun
• An overrun error occurs when the next reception completes without reading the value of the
receive buffer by CPU, upon completion of the receive operation.
The CBnOVE flag indicates occurrence of this overrun error.
• The CBnOVE bit is valid also in the single transfer mode. Therefore, when only using
transmission, note the following.
• Do not check the CBnOVE flag.
• Read this bit even if reading the reception data is not required.
• The OBnOVE flag is cleared when 0 is written to it. It is not set when 1 is written to it.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.4 Transfer Data Length Change Function
The transfer data length of CSIB can be changed from 8 to 16 bits in 1-bit units by using the CBnCL3 to CBnCL0
bits of the CBnCTL2 register.
If a transfer data length of other than 16 bits is specified, set data in the CBnTX or CBnRX register, justifying to the
least significant bit, regardless of whether the first transfer bit is the MSB or LSB. Any data can be set to the higher
bits that are not used, but the receive data is 0 after serial transfer.
Figure 14-2. Changing Transfer Data Length
(a) When transfer bit length = 10 bits, MSB first
SOBn
SIBn
15
10
9
0
Insert 0
(b) When transfer bit length = 12 bits, LSB first
SIBn
12
SOBn
15
11
0
Insert 0
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14.5 Interrupt Request Signals
CSIBn can generate the following two types of interrupt request signals.
• Reception complete interrupt request signal (INTCBnR)
• Transmission enable interrupt request signal (INTCBnT)
Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by
default, and the priority of the transmission enable interrupt request signal is lower.
Table 14-4. Interrupts and Their Default Priority
Interrupt
Priority
High
Reception complete
Transmission enable
Low
(1) Reception complete interrupt request signal (INTCBnR)
When receive data is transferred to the CBnRX register while reception is enabled, the reception complete
interrupt request signal is generated.
This interrupt request signal can also be generated if a reception error occurs, instead of a reception error
interrupt.
When the reception complete interrupt request signal is acknowledged and the data is read, read the CBnSTR
register to check that the result of reception is not an error.
The reception complete interrupt request signal is not generated while reception is disabled.
(2) Transmission enable interrupt request signal (INTCBnT)
The transmission enable interrupt request signal is generated when transmit data is transferred from the
CBnTX register while transmission enabled.
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14.6 Operation
14.6.1 Single transfer mode (master mode, transmission/reception mode)
This section shows a case of MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 14.3 (2) CSIBn
control register 1 (CBnCTL1), and transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0,
0, 0).
CBnTX write (55H)
CBnRX read (AAH)
SCKBn pin
CBnTX register
55H (transmit data)
Shift
register
ABH
ADH
5AH
B5H
6AH
D5H
AAH
AAH
56H
CBnRX register
00H
INTCBnR signalNote
CBnTSF bit
CBnSCE bit
SIBn pin
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
(AAH)
SOBn pin
1
(55H)
(1) (5)
(2)
(6)
(7) (8)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Write transfer data to the CBnTX register (transmission start).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Read the CBnRX register before clearing the CBnPWR bit to 0.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop operation of CSIBn (end
of transmission/reception).
Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated.
When communication is complete, the INTCBnR signal is generated.
Remark The processing of steps (3) and (4) can be set simultaneously.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.2 Single transfer mode (master mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
CBnRX read (dummy read)
CBnRX read (AAH)
SCKBn pin
CBnRX register
AAH
AAH
00H
00H
Shift
register
01H
05H
0AH
15H
2AH
55H
02H
INTCBnR signal
(AAH)
0
SIBn pin
1
0
1
0
1
0
1
SOBn pin
L
CBnTSF bit
CBnSCE bit
(1) (5)
(2)
(3)
(6)
(7)
(8)
(9)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the
transfer mode using the CBnDIR bit, to set the reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Set the CBnSCE bit to 0 to set the final receive data status.
(8) Read the CBnRX register.
(9) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the CSIBn operation
(end of reception).
Remark The processing of steps (3) and (4) can be set simultaneously.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.3 Continuous mode (master mode, transmission/reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 3 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
CBnTX register
SCKBn pin
55H
AAH
SOBn pin
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
SIBn pin
1
0
INTCBnT signal
INTCBnR signal
CBnTSF bit
CBnSCE bit
CCH
Shift register
SO latch
96H
CBnRX register
CCH
96H 00H
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(7)
(8)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Write transfer data to the CBnTX register (transmission start).
(6) The transmission enable interrupt request signal (INTCBnT) is received and transfer data is written to
the CBnTX register.
(7) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
In transmission mode or transmission/reception mode, the communication is not started by reading the
CBnRX register.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.4 Continuous mode (master mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
SCKBn pin
CBnSCE bit
SIBn pin
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
INTCnR signal
CBnTSF bit
Shift register
55H
AAH
AAH
CBnRX register
55H
00H
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(6)
(8)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR
bit, to set the reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to
0.
(7) Set the CBnCTL0.CBnSCE bit = 0 while the last data being received to set the final receive data status.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of reception).
To continue transfer, repeat steps (5) and (6) before (7).
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.5 Continuous reception mode (error)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
SCKBn pin
SIBn pin
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
INTCBnR signal
CBnTSF bit
55H
AAH
Shift register
CBnRX register
CBnOVE bit
55H
AAH 00H
(1)
(2)
(3)
(4)
(5)
(6)
(8) (9) (10)
(7)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR
bit, to set the reception enabled status.
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) If the data could not be read before the end of the next transfer, the CBnSTR.CBnOVE flag is set to 1
upon the end of reception and the INTCBnR signal is output.
(8) Overrun error processing is performed after checking that the CBnOVE bit = 1 in the INTCBnR interrupt
servicing.
(9) Clear CBnOVE bit to 0.
(10) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation CSIBn
(end of reception).
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.6 Continuous mode (slave mode, transmission/reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
CBnTX register
SCKBn pin
55H
AAH
SOBn pin
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
SIBn pin
1
INTCBnT signal
INTCBnR signal
CBnTSF bit
CBnSCE bit
Shift register
SO latch
96H
96H
CCH
CBnRX register
CCH
00H
(5)
(1)
(2)
(3)
(4)
(6)
(7)
(7)
(8)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable supply of the CSIBn operation.
(5) Write the transfer data to the CBnTX register.
(6) The transmission enable interrupt request signal (INTCBnT) is received and the transfer data is written
to the CBnTX register.
(7) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.7 Continuous mode (slave mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
SCKBn pin
SIBn pin
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
INTCBnR signal
CBnTSF bit
CBnSCE bit
Shift register
AAH
55H
CBnRX register
55H
AAH
(7)
00H
(1) (5)
(2)
(6)
(6)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the
transfer mode using the CBnDIR bit, to set the reception enabled status.
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register. When reading the last data, clear the CBnCTL0.CBnSCE bit to 0 before
reading the CBnRX register.
(7) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of reception).
To continue transfer, repeat steps (5) and (6) before (7).
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.6.8 Clock timing
(1/2)
(1) Communication type 1 (CBnCKP = 0, CBnDAP = 0)
SCKBn pin
SIBn
capture
SOBn pin
Reg-R/W
D7
D6
D5
D4
D3
D2
D1
D0
INTCBnT
interruptNote 1
INTCBnR
interruptNote 2
CBnTSF bit
(2) Communication type 2 (CBnCKP = 0, CBnDAP = 1)
SCKBn pin
SIBn
capture
D7
D6
D5
D4
D3
D2
D1
D0
SOBn pin
Reg-R/W
INTCBnT
interruptNote 1
INTCBnR
interruptNote 2
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated upon completion of
communication.
2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the
CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the
INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of
communication.
Caution In communication type 2, the CBnTSF bit is cleared half a SCKBn clock after generation of the
INTCBnR interrupt request signal.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(2/2)
(3) Communication type 3 (CBnCKP = 1, CBnDAP = 0)
SCKBn pin
SIBn
capture
D7
D6
D5
D4
D3
D2
D1
D0
SOBn pin
Reg-R/W
INTCBnT
interruptNote 1
INTCBnR
interruptNote 2
CBnTSF bit
(4) Communication type 4 (CBnCKP = 1, CBnDAP = 1)
SCKBn pin
SIBn
capture
D7
D6
D5
D4
D3
D2
D1
D0
SOBn pin
Reg-R/W
INTCBnT
interruptNote 1
INTCBnR
interruptNote 2
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data
shift register in the continuous transmission or continuous transmission/reception modes. In the
single transmission or single transmission/reception modes, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated upon completion of
communication.
2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the
CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the
INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of
communication.
Caution In communication type 4, the CBnTSF bit is cleared half a SCKBn clock after generation of the
INTCBnR interrupt request signal.
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.7 Output Pins
(1) SCKBn pin
When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows.
CBnCKS2
1
CBnCKS1
1
CBnCKS0
1
CBnCKP
SCKBn Pin Output
High impedance
×
0
1
Other than above
Fixed to high level
Fixed to low level
Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and
CBnCKS2 to CBnCKS0 bits is rewritten.
2. n = 0 to 2
3. ×: don’t care
(2) SOBn pin
When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows.
CBnTXE
CBnDAP
CBnDIR
SOBn Pin Output
Fixed to low level
0
1
×
0
1
×
×
0
1
SOBn latch value (low level)
CBnTX register value (MSB)
CBnTX register value (LSB)
Remarks 1. The SOBn pin output changes when any one of the
CBnCTL0.CBnTXE, CBnCTL0.CBnDIR bits, and
CBnCTL1.CBnDAP bit is rewritten.
2. n = 0 to 2
3. ×: don’t care
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.8 Operation Flow
(1) Single transmission
START
Initial setting (CBnCTL0Note
CBnCTL1 registers, etc.)
,
Write CBnTX register
(start transfer).
No
INTCBnR signal is
generated?
Yes
Transfer data exists?
No
Yes
CBnPWR bit = 0
(CBnCTL0)
END
Note Set the CBnSCE bit to 1 in the initial setting.
Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input
earlier than the CBnTX register is written.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(2) Single reception
START
Initial setting (CBnCTL0Note
CBnCTL1 registers, etc.)
,
CBnRX register dummy read
(start reception)
No
No
INTCBnR signal is
generated?
Yes
Last data?
Yes
CBnRX register read
CBnSCE bit = 0
(CBnCTL0)
CBnRX register read
CBnPWR bit = 0
(CBnCTL0)
END
Note Set the CBnSCE bit to 1 in the initial setting.
Caution In the single mode, data cannot be correctly received if the next transfer clock is input
earlier than the CBnRX register is read.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(3) Single transmission/reception
START
Initial setting (CBnCTL0Note 1
CBnCTL1 registers, etc.)
,
Write CBnTX register
(start transfer).
No
INTCBnR signal is
generated?
Yes
Transmission/reception
Reception
Transmission
Read CBnRX register.
Read CBnRX register.
No
No
No
Transfer end?
Yes
Transfer end?
Yes
Transfer end?
Yes
Write CBnTX registerNote 2
.
Write CBnTX registerNote 2
.
Write CBnTX registerNote 2
.
B
A
B
A
CBnPWR bit = 0,
CBnTXE bit = CBnRXE bit = 0
(CBnCTL0)
END
Notes 1. Set the CBnSCE bit to 1 in the initial setting.
2. If the next transfer is reception only, dummy data is written to the CBnTX register.
Caution Even in the single mode, the CBnSTR.CBnOVE flag is set to 1. If only transmission is
used in the transmission/reception mode, therefore, checking the CBnOVE flag is not
required.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(4) Continuous transmission
START
Initial setting (CBnCTL0Note
CBnCTL1 registers, etc.)
,
Write CBnTX register
(start transfer).
No
INTCBnT signal is
generated?
Yes
Data to be
Yes
transferred next exists?
No
No
CBnTSF bit = 1?
(CBnSTR)
Yes
CBnPWR bit = 0
(CBnCTL0)
END
Note Set the CBnSCE bit to 1 in the initial setting.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(5) Continuous reception
START
Initial setting (CBnCTL0Note
CBnCTL1 registers, etc.)
,
CBnRX register dummy read
(start reception)
No
INTCBnR signal is
generated?
Yes
CBnRX register read
Yes
CBnOVE bit = 1?
(CBnSTR)
No
CBnRX register read
No
Is data being
received last data?
CBnOVE bit clear
(CBnSTR)
Yes
CBnSCE bit = 0
(CBnCTL0)
CBnRX register read
No
INTCBnR signal is
generated?
Yes
CBnRX register read
CBnSCE bit = 1
(CBnCTL0)
END
Note Set the CBnSCE bit to 1 in the initial setting
Caution In the master mode, the clock is output without limit when dummy data is read from the
CBnRX register. To stop the clock, execute the flow marked ◆ in the above flowchart.
In the slave mode, malfunction due to noise during communication can be prevented by
executing the flow marked ◆ in the above flowchart.
Before resuming communication, set the CBnCTL0.CBnSCE bit to 1, and read dummy
data from the CBnRX register.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(6) Continuous transmission/reception
START
Initial setting (CBnCTL0Note
CBnCTL1 registers, etc.)
,
Write CBnTX register.
No
INTCBnT signal is
generated?
Yes
No
Is data being
transferred last data?
Yes
Write CBnTX register.
No
INTCBnT signal is
generated?
Yes
CBnRX register read
No
CBnOVE bit = 0?
(CBnSTR)
Yes
CBnOVE bit clear
(CBnSTR)
No
Is data completely
received last data?
Yes
END
Note Set the CBnSCE bit to 1 in the initial setting.
Remark n = 0 to 2
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.9 Prescaler 3
Prescaler 3 has the following function.
• Generation of count clock for watch timer and CSIB0 (source clock: main oscillation clock)
14.9.1 Control registers of prescaler 3
(1) Prescaler mode register 0 (PRSM0)
The PRSM0 register is used to control generation of the count clock for the watch timer and CSIB0.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Cautions 1. Do not change the values of the BGCS01 and BGCS00 bits while the watch timer is
operating.
2. Set the PRSM0 register before setting the BGCE0 bit to 1.
After reset: 00H
R/W
Address: FFFFF8B0H
7
0
6
0
5
0
4
3
0
2
0
1
0
PRSM0
BGCE0
BGCS01
BGCS00
BGCE0
Prescaler output
0
1
Disabled
Enabled
BGCS01
BGCS00
Selection of count clock (fBRG)
fX = 4 MHz
250 ns
500 ns
1 µ s
fX = 5 MHz
0
0
1
1
0
1
0
1
fX
200 ns
400 ns
800 ns
1.6 µ s
fX/2
fX/4
fX/8
2 µ s
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
(2) Prescaler compare register 0 (PRSCM0)
This is an 8-bit compare register.
It can be read or written in 8-bit units.
Reset input clears this register to 00H.
Cautions 1. Do not rewrite the PRSCM0 register while the watch timer is operating.
2. Set the PRSCM0 register before setting the BGCE0 bit of the PRSM0 register to 1.
After reset: 00H
7
R/W
Address: FFFFF8B1H
6
5
4
3
2
1
0
PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00
14.9.2 Generation of count clock
The clock input to the watch timer or CSIB0 (fBRG) can be corrected to 32.768 kHz.
The relationship between the main clock (fX), set value of count clock selection bits BGCSn (m), set value of the
PRSCM0 register (N), and output clock (fBGR) is as follows.
fX
fBRG =
2m × N × 2
Example: Where fX = 4.00 MHz, m = 0 (BGCS01 bit = BGCS00 bit = 0), and N = 3DH
fBGR = 32.787 kHz
Remark fBRG: Count clock
N: Set value of PRSCM0 register (01H to FFH)
N = 256 if the set value of the PRSCM0 register is 00H.
M: Set value of BGCSn bits (00B to 11B)
n = 00, 01
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CHAPTER 14 3-WIRE SERIAL INTERFACE (CSIB)
14.10 Cautions
(1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed
even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading
the CBnSTR.CBnOVE bit after DMA transfer has been completed.
(2) In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.CBnPWR bit is 1),
if rewriting has been carried out by mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then
initialize CSIBn.
Registers to which rewriting during operation are prohibited are shown below.
• CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
• CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
• CBnCTL2 register: CBnCL3 to CBnCL0 bits
(3) In communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half a SCKBn
clock after occurrence of a reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1),
and the next communication is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0,
CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during
communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay
particular attention to the following.
• To start the next transmission, confirm that CBnTSF bit = 0 and then write the transmit data to the CBnTX
register.
• To perform the next reception continuously when reception-only communication (CBnTXE bit = 0, CBnRXE
bit = 1) is set, confirm that CBnTSF bit = 0 and then read the CBnRX register.
Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode
is recommended especially for using DMA.
Remark n = 0 to 2
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Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
15.1 Overview
This product features an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN
protocol as standardized in ISO 11898. The number of channels varies depending on the product as shown below.
Product Name (Part Number)
V850ES/FE2
Number of Channels
1
1
2
2
4
V850ES/FF2
V850ES/FG2
V850ES/FJ2
µPD70F3237
µPD70F3238
µPD70F3239
15.1.1 Features
• Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test)
• Standard frame and extended frame transmission/reception enabled
• Transfer rate: 1 Mbps max. (CAN clock input ≥ 8 MHz)
• 32 message buffers per each channel
• Receive/transmit history list function
• Automatic block transmission function
• Multi-buffer receive block function
• Mask setting of four patterns is possible for each channel
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15.1.2 Overview of Functions
Table 15-1 presents an overview of the CAN controller functions.
Table 15-1. Overview of Functions
Function
Details
CAN protocol ISO 11898 (standard and extended frame transmission/reception)
Maximum 1 Mbps (CAN clock input ≥ 8 MHz)
Protocol
Baud rate
Data storage
Storing messages in the CAN RAM
Number of messages
• 32 message buffers per each channelNote
• Each message buffer can be set to be either a transmit message buffer or a receive
message buffer.
Message reception
• Unique ID can be set to each message buffer.
• Mask setting of four patterns is possible for each channel.
• A receive completion interrupt is generated each time a message is received and stored in
a message buffer.
• Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer
receive block function).
• Receive history list function
Message transmission
• Unique ID can be set to each message buffer.
• Transmit completion interrupt for each message buffer
• Message buffer numbers 0 to 7 specified as transmit message buffers can be used for
automatic block transfer. Message transmission interval is programmable (automatic
block transmission function (hereafter referred to as “ABT”)).
• Transmission history list function
Remote frame processing
Time stamp function
Remote frame processing by transmit message buffer
• The time stamp function can be set for a receive message when a 16-bit timer is used in
combination.
SOF or EOF in a CAN message frame can be detected by using a trigger that selects a
time stamp capture.
Diagnostic function
• Readable error counters
• “Valid protocol operation flag” for verification of bus connections
• Receive-only mode
• Single-shot mode
• CAN protocol error type decoding
• Self-test mode
Forced release from bus-off state
Power save mode
• Default mode can be set while bus is off, so that bus can be forcibly released from bus-off
state.
• CAN sleep mode (can be woken up by CAN bus)
• CAN stop mode (cannot be woken up by CAN bus)
Note 4 channels max.
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15.1.3 Configuration
The CAN controller is composed of the following four blocks.
(1) NPB interface
This functional block provides an NPB (NEC Peripheral I/O Bus) interface and means of transmitting and
receiving signals between the CAN module and the host CPU.
(2) MAC (Memory Access Controller)
This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module.
(3) CAN protocol layer
This functional block is involved in the operation of the CAN protocol and its related settings.
(4) CAN RAM
This is the CAN memory functional block, which is used to store message IDs, message data, etc.
Figure 15-1. Block Diagram of CAN Module
CPU
Interrupt request
NPB
INTCnTRX
(NEC peripheral I/O bus)
INTCnREC
INTCnERR
INTCnWUP
CAN bus
CAN module
CANTXn
CANRXn
CAN_Hn
CAN_Ln
CAN
protocol
layer
CAN
transceiver
MAC
NPB
interface
(Memory Access Controller)
CAN RAM
Message
buffer 0
Message
buffer 1
Message
buffer 2
Message
buffer 3
CnMASK1
CnMASK2
CnMASK3
CnMASK4
Message
buffer 31
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15.2 CAN Protocol
CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in
automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898
specifications.
The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data
link layer includes logical link and medium access control. The composition of these layers is illustrated below.
Figure 15-2. Composition of Layers
Higher
·
·
Logical link control (LLC)
·
·
·
·
·
·
·
·
·
·
Acceptance filtering
Overload report
Data link
layerNote
Recovery management
Medium access control (MAC)
Data capsuled/not capsuled
Frame coding (stuffing/no stuffing)
Medium access management
Error detection
Error report
Acknowledgement
Seriated/not seriated
Physical layer
Prescription of signal level and bit description
Lower
Note CAN controller specification
15.2.1 Frame format
(1) Standard format frame
• The standard format frame uses 11-bit identifiers, which means that it can handle up to 2,048 messages.
(2) Extended format frame
• The extended format frame uses 29-bit (11 bits + 18 bits) identifiers, which increases the number of
messages that can be handled to 2,048 × 218 messages.
• An extended format frame is set when “recessive level” (CMOS level of “1”) is set for both the SRR and IDE
bits in the arbitration field.
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15.2.2 Frame types
The following four types of frames are used in the CAN protocol.
Table 15-2. Frame Types
Frame Type
Data frame
Description
Frame used to transmit data
Remote frame
Error frame
Frame used to request a data frame
Frame used to report error detection
Frame used to delay the next data frame or remote frame
Overload frame
(1) Bus value
The bus values are divided into dominant and recessive.
• Dominant level is indicated by logical 0.
• Recessive level is indicated by logical 1.
• When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes
dominant level.
15.2.3 Data frame and remote frame
(1) Data frame
A data frame is composed of seven fields.
Figure 15-3. Data Frame
Data frame
R
D
<1>
<2>
<3>
<4>
<5>
<6> <7>
<8>
Interframe space
End of frame (EOF)
ACK field
CRC field
Data field
Control field
Arbitration field
Start of frame (SOF)
Remark D: Dominant = 0
R: Recessive = 1
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(2) Remote frame
A remote frame is composed of six fields.
Figure 15-4. Remote Frame
Remote frame
R
D
<1>
<2>
<3>
<5>
<6> <7>
<8>
Interframe space
End of frame (EOF)
ACK field
CRC field
Control field
Arbitration field
Start of frame (SOF)
Remarks 1. The data field is not transferred even if the control field’s data length code is not “0000B”.
2. D: Dominant = 0
R: Recessive = 1
(3) Description of fields
<1> Start of frame (SOF)
The start of frame field is located at the start of a data frame or remote frame.
Figure 15-5. Start of Frame (SOF)
(Interframe space or bus idle)
Start of frame
1 bit
(Arbitration field)
R
D
Remark D: Dominant = 0
R: Recessive = 1
• If dominant level is detected in the bus idle state, a hard-synchronization is performed (the current TQ
is assigned to be the SYNC segment).
• If dominant level is sampled at the sample point following such a hard-synchronization, the bit is
assigned to be a SOF. If recessive level is detected, the protocol layer returns to the bus idle state and
regards the preceding dominant pulse as a disturbance only. No error frame is generated in such case.
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<2> Arbitration field
The arbitration field is used to set the priority, data frame/remote frame, and frame format.
Figure 15-6. Arbitration Field (in Standard Format Mode)
Arbitration field
(Control field)
R
D
Identifier
RTR
IDE
(r1)
r0
ID28 · · · · · · · · · · · · · · · · · · · · ID18
(11 bits)
(1 bit)
(1 bit)
Cautions 1. ID28 to ID18 are identifiers.
2. An identifier is transmitted MSB first.
Remark D: Dominant = 0
R: Recessive = 1
Figure 15-7. Arbitration Field (in Extended Format Mode)
Arbitration field
(Control field)
R
D
Identifier
SRR
IDE
Identifier
RTR
r1
r0
ID28 · · · · · · · · · · · · · · ID18
(11 bits)
ID17 · · · · · · · · · · · · · · · · · ID0
(18 bits)
(1 bit) (1 bit)
(1 bit)
Cautions 1. ID28 to ID18 are identifiers.
2. An identifier is transmitted MSB first.
Remark D: Dominant = 0
R: Recessive = 1
Table 15-3. RTR Frame Settings
Frame Type
Data frame
Remote frame
RTR Bit
0 (D)
1 (R)
Table 15-4. Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits
Frame Format
Standard format mode
Extended format mode
SRR Bit
None
1 (R)
IDE Bit
Number of Bits
11 bits
29 bits
0 (D)
1 (R)
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<3> Control field
The control field sets “N” as the number of data bytes in the data field (N = 0 to 8).
Figure 15-8. Control Field
(Arbitration field)
Control field
(Data field)
R
D
RTR
r1
r0
DLC3 DLC2 DLC1 DLC0
(IDE)
Remark D: Dominant = 0
R: Recessive = 1
In a standard format frame, the control field’s IDE bit is the same as the r1 bit.
Table 15-5. Data Length Setting
Data Length Code
Data Byte Count
DLC3
DLC2
DLC1
DLC0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0 bytes
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
Other than above
8 bytes regardless of the
value of DLC3 to DLC0
Caution In the remote frame, there is no data field even if the data length code
is not 0000B.
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<4> Data field
The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can
be set.
Figure 15-9. Data Field
(Control field)
Data field
(CRC field)
R
D
Data 0
(8 bits)
→
Data 7
(8 bits)
→
MSB
LSB
MSB
LSB
Remark D: Dominant = 0
R: Recessive = 1
<5> CRC field
The CRC field is a 16-bit field that is used to check for errors in transmit data.
Figure 15-10. CRC Field
(Data field or control field)
CRC field
(ACK field)
R
D
CRC sequence
(15 bits)
CRC delimiter
(1 bit)
Remark D: Dominant = 0
R: Recessive = 1
• The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows.
P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1
• Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the
start of frame, arbitration field, control field, and data field.
• Receiving node:
Compares the CRC sequence calculated using data bits that exclude the
stuffing bits in the receive data with the CRC sequence in the CRC field. If the
two CRC sequences do not match, the node issues an error frame.
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<6> ACK field
The ACK field is used to acknowledge normal reception.
Figure 15-11. ACK Field
(CRC field)
ACK field
(End of frame)
R
D
ACK slot
(1 bit)
ACK delimiter
(1 bit)
Remark D: Dominant = 0
R: Recessive = 1
• If no CRC error is detected, the receiving node sets the ACK slot to the dominant level.
• The transmitting node outputs two recessive-level bits.
<7> End of frame (EOF)
The end of frame field indicates the end of data frame/remote frame.
Figure 15-12. End of Frame (EOF)
(ACK field)
End of frame
(7 bits)
(Interframe space or overload frame)
R
D
Remark D: Dominant = 0
R: Recessive = 1
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<8> Interframe space
The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to
separate one frame from the next.
• The bus state differs depending on the error status.
(a) Error active node
The interframe space consists of a 3-bit intermission field and a bus idle field.
Figure 15-13. Interframe Space (Error Active Node)
(Frame)
Interframe space
(Frame)
R
D
Intermission
(3 bits)
Bus idle
(0 to ∞ bits)
Remarks 1. Bus idle: State in which the bus is not used by any node.
2. D: Dominant = 0
R: Recessive = 1
(b) Error passive node
The interframe space consists of an intermission field, a suspend transmission field, and a bus idle
field.
Figure 15-14. Interframe Space (Error Passive Node)
(Frame)
Interframe space
(Frame)
R
D
Intermission
(3 bits)
Suspend transmission
(8 bits)
Bus idle
(0 to ∞ bits)
Remarks 1. Bus idle:
State in which the bus is not used by any node.
Suspend transmission: Sequence of 8 recessive-level bits transmitted from the
node in the error passive status.
2. D: Dominant = 0
R: Recessive = 1
Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third
bit of the intermission field, however, it executes transmission.
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• Operation in error status
Table 15-6. Operation in Error Status
Error Status
Error active
Operation
A node in this status can transmit immediately after a 3-bit intermission.
A node in this status can transmit 8 bits after the intermission.
Error passive
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15.2.4 Error frame
An error frame is output by a node that has detected an error.
Figure 15-15. Error Frame
Error frame
R
D
(<4>)
<1>
<2>
<3>
(<5>)
6 bits
0 to 6 bits
8 bits
Interframe space or overload frame
Error delimiter
Error flag 2
Error flag 1
Error bit
Remark D: Dominant = 0
R: Recessive = 1
Table 15-7. Definition of Error Frame Fields
No.
Name
Bit Count
Definition
<1>
Error flag 1
6
Error active node: Outputs 6 dominant-level bits consecutively.
Error passive node: Outputs 6 recessive-level bits consecutively.
If another node outputs a dominant level while one node is outputting a
passive error flag, the passive error flag is not cleared until the same level
is detected 6 bits in a row.
<2>
<3>
Error flag 2
0 to 6
8
Nodes receiving error flag 1 detect bit stuff errors and issue this error flag.
Error delimiter
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame is
transmitted from the next bit.
<4>
<5>
Error bit
–
–
The bit at which the error was detected.
The error flag is output from the bit next to the error bit.
In the case of a CRC error, this bit is output following the ACK delimiter.
Interframe space/overload
frame
An interframe space or overload frame starts from here.
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15.2.5 Overload frame
An overload frame is transmitted under the following conditions.
• When the receiving node has not completed the reception operation Note
• If a dominant level is detected at the first two bits during intermission
• If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error
delimiter/overload delimiter
Note The CAN is internally fast enough to process all received frames not generating overload frames.
Figure 15-16. Overload Frame
Overload frame
R
D
(<4>)
<1>
<2>
<3>
(<5>)
6 bits
0 to 6 bits
8 bits
Interframe space or overload frame
Overload delimiter
Overload flag (node n)
Overload flag (node m)
Frame
Remark D: Dominant = 0
R: Recessive = 1
Node n ≠ node m
Table 15-8. Definition of Overload Frame Fields
No
<1>
<2>
Name
Overload flag
Bit Count
Definition
6
Outputs 6 dominant-level bits consecutively.
Overload flag from other node
0 to 6
The node that received an overload flag in the interframe space
outputs an overload flag.
<3>
Overload delimiter
8
Outputs 8 recessive-level bits consecutively.
If a dominant level is detected at the 8th bit, an overload frame
is transmitted from the next bit.
<4>
<5>
Frame
–
–
Output following an end of frame, error delimiter, or overload
delimiter.
Interframe space/overload
frame
An interframe space or overload frame starts from here.
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15.3 Functions
15.3.1 Determining bus priority
(1) When a node starts transmission:
• During bus idle, the node that output data first transmits the data.
(2) When more than one node starts transmission:
• The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field
has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant
level is taken as the bus value).
• The transmitting node compares its output arbitration field and the data level on the bus.
Table 15-9. Determining Bus Priority
Level match
Continuous transmission
Continuous transmission
Level mismatch
(3) Priority of data frame and remote frame
• When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the
last bit in the arbitration field, carries a dominant level.
Caution If the extended-format data frame and the standard-format remote frame conflict on the bus (if
ID28 to ID18 of both of them are the same), the standard-format remote frame takes priority.
15.3.2 Bit stuffing
Bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues
for 5 bits, in order to prevent a burst error.
Table 15-10. Bit Stuffing
Transmission
Reception
During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data
between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit.
During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data
between the start of frame and the ACK field, reception is continued after deleting the next bit.
15.3.3 Multi masters
As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus
master.
15.3.4 Multi cast
Although there is one transmitting node, two or more nodes can receive the same data at the same time because
the same identifier can be set to two or more nodes.
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15.3.5 CAN sleep mode/CAN stop mode function
The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power
consumption.
The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop
mode by bus operation (the CAN stop mode is controlled by CPU access).
15.3.6 Error control function
(1) Error types
Table 15-11. Error Types
Type
Description of Error
Detection Method
Detection State
Field/Frame
Detection
Condition
Transmission/
Reception
Bit error
Comparison of the output level Mismatch of levels
and level on the bus (except
stuff bit)
Transmitting/
Bit that is outputting data on the bus
at the start of frame to end of frame,
error frame and overload frame.
receiving node
Stuff error Check of the receive data at
the stuff bit
6 consecutive bits of
the same output level
Receiving node
Receiving node
Start of frame to CRC sequence
CRC error Comparison of the CRC
sequence generated from the
receive data and the received
CRC sequence
Mismatch of CRC
CRC field
Form error Field/frame check of the fixed
format
Detection of fixed
format violation
Receiving node
CRC delimiter
ACK field
End of frame
Error frame
Overload frame
ACK error Check of the ACK slot by the
transmitting node
Detection of recessive Transmitting node ACK slot
level in ACK slot
(2) Output timing of error frame
Table 15-12. Output Timing of Error Frame
Type
Output Timing
Bit error, stuff error, form Error frame output is started at the timing of the bit following the detected error.
error, ACK error
CEC error
Error frame output is started at the timing of the bit following the ACK delimiter.
(3) Processing in case of error
The transmission node re-transmits the data frame or remote frame after the error frame. (However, it does
not re-transmit the frame in the single-shot mode.)
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(4) Error state
(a) Types of error states
The following three types of error states are defined by the CAN specification.
• Error active
• Error passive
• Bus-off
These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error
counter bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register
as shown in Table 15-13.
The present error state is indicated by the CAN module information register (CnINFO).
When each error counter value becomes equal to or greater than the error warning level (96), the TECS0
or RECS0 bit of the CnINFO register is set to 1. In this case, the bus state must be tested because it is
considered that the bus has a serious fault. An error counter value of 128 or more indicates an error
passive state and the TECS1 or RECS1 bit of the CnINFO register is set to 1.
• If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission
error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and
the BOFF bit of the CnINFO register is set to 1.
• If only one node is active on the bus at startup (i.e., when the bus is connected only to the local station),
ACK is not returned even if data is transmitted. Consequently, re-transmission of the error frame and
data is repeated. In the error passive state, however, the transmission error counter is not incremented
and the bus-off state is not reached.
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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Table 15-13. Types of Error States
Type
Operation
Value of Error
Counter
Transmission 0 to 95
Reception 0 to 95
Transmission 96 to 127
Reception 96 to 127
Error passive Transmission 128 to 255
Reception 128 or more
Indication of CnINFO
Register
Operation Specific to Error State
Error active
TECS1, TECS0 = 00 • Outputs an active error flag (6 consecutive dominant-
level bits) on detection of the error.
RECS1, RECS0 = 00
TECS1, TECS0 = 01
RECS1, RECS0 = 01
TECS1, TECS0 = 11 • Outputs a passive error flag (6 consecutive
recessive-level bits) on detection of the error.
RECS1, RECS0 = 11
• Transmits 8 recessive-level bits, in between
transmissions, following an intermission (suspend
transmission).
Bus-off
Transmission 256 or more
BOFF = 1,
• Communication is not possible.
(not indicated)Note TECS1, TECS0 = 11
<1> TSOUT toggles.
<2> REC is incremented / decremented.
<3> VALID bit is set.
• If the initialization mode is set and then 11 recessive-
level bits are generated 128 times in a row in an
operation mode other than the initialization mode, the
error counter is reset to 0 and the error active state
can be restored.
Note Value of the transmission error counter (TEC) is not meaning when BOFF bit is set. If an error that increments
the value of the transmission error counter by 8 while the counter value is in a range of 248 to 255, the counter
is not incremented and the bus-off state is assumed.
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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(b) Error counter
The error counter counts up when an error has occurred, and counts down upon successful transmission
and reception. The error counter is updated during the first bit of the error delimiter.
Table 15-14. Error Counter
State
Transmission Error Counter
(TEC7 to TEC0)
Reception Error Counter
(REC6 to REC0)
Receiving node detects an error (except bit error in the active error
flag or overload flag).
No change
No change
+8
+1 (REPS bit = 0)
+8 (REPS bit = 0)
No change
Receiving node detects dominant level following error flag of error
frame.
Transmitting node transmits an error flag.
[As exceptions, the error counter does not change in the following
cases.]
<1> ACK error is detected in error passive state and dominant level
is not detected while the passive error flag is being output.
<2> A stuff error is detected in an arbitration field that transmitted a
recessive level as stuff bit, but a dominant level is detected.
Bit error detection while active error flag or overload flag is being
output (error-active transmitting node)
+8
No change
Bit error detection while active error flag or overload flag is being
output (error-active receiving node)
No change
+8 (transmitting)
+8 (REPS bit = 0)
+8 (receiving, REPS bit = 0)
When the node detects 14 consecutive dominant-level bits from the
beginning of the active error flag or overload flag, and then
subsequently detects 8 consecutive dominant-level bits.
When the node detects 8 consecutive dominant levels after a
passive error flag
When the transmitting node has completed transmission without
–1
No change
error (±0 if error counter = 0)
When the receiving node has completed reception without error
No change
• –1 (1 ≤ REC6 to REC0 ≤
127, REPS bit = 0)
• ±0 (REC6 to REC0 = 0,
REPS bit = 0)
• Any value of 119 to 127
is set (REPS bit = 1)
(c) Occurrence of bit error in intermission
An overload frame is generated.
Caution If an error occurs, it is controlled according to the contents of the transmission error
counter and reception error counter before the error occurred. The value of the error
counter is incremented after the error flag has been output.
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CHAPTER 15 CAN CONTROLLER
(5) Recovery from bus-off state
When the CAN module is in the bus-off state, the transmission pins (CTXDn) cut off from the CAN bus always
output the recessive level.
The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
<1> Request to enter the CAN initialization mode
<2> Request to enter a CAN operation mode
(a) Recovery operation through normal recovery sequence
(b) Forced recovery operation that skips recovery sequence
(a) Recovery from bus-off state through normal recovery sequence
The CAN module first issues a request to enter the initialization mode (refer to timing <1> in Figure 15-17).
This request will be immediately acknowledged, and the OPMODE bits of the CnCTRL register are
cleared to 000B. Processing such as analyzing the fault that has caused the bus-off state, re-defining the
CAN module and message buffer using application software, or stopping the operation of the CAN module
can be performed by clearing the GOM bit to 0.
Next, the module requests to change the mode from the initialization mode to an operation mode (refer to
timing <2> in Figure 15-17). This starts an operation to recover the CAN module from the bus-off state.
The conditions under which the module can recover from the bus-off state are defined by the CAN
protocol ISO 11898, and it is necessary to detect 11 consecutive recessive-level bits 128 times or more.
At this time, the request to change the mode to an operation mode is held pending until the recovery
conditions are satisfied. When the recovery conditions are satisfied (refer to timing <3> in Figure 15-17),
the CAN module can enter the operation mode it has requested. Until the CAN module enters this
operation mode, it stays in the initialization mode. Whether the CAN module has entered the operation
mode can be confirmed by reading the OPMODE bits of the CnCTRL register.
During the bus-off period and bus-off recovery sequence, the BOFF bit of the CnINFO register stays set
(to 1). In the bus-off recovery sequence, the reception error counter (REC[6:0]) counts the number of
times 11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state
can be checked by reading REC[6:0].
Caution In the bus-off recovery sequence, REC[6:0] counts up (+1) each time 11 consecutive
recessive-level bits have been detected. Even during the bus-off period, the CAN
module can enter the CAN sleep mode or CAN stop mode. To be released from the bus-
off state, the module must enter the initialization mode once. If the module is in the CAN
sleep mode or CAN stop mode, however, it cannot enter the initialization mode. In this
case, release the module from the CAN sleep or stop mode, and then make a request to
place the module in the initialization mode.
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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Figure 15-17. Recovery from Bus-off State Through Normal Recovery Sequence
TEC > FFH
»bus-off«
»bus-off-recovery-sequence«
»error-active«
»error-passive«
BOFF bit
in CnINFO
register
<1>
<2>
OPMODE[2:0]
in CnCTRL
register
≠ 00H
≠ 00H
00H
≠ 00H
(written by user)
<3>
OPMODE[2:0]
in CnCTRL
register
00H
≠ 00H
(read by user)
TEC[7:0]
in CnERC
register
80H ≤ TEC[7:0] ≤ FFH
00H
00H ≤ TEC[7:0] < 80H
00H ≤ REC[7:0] < 80H
FFH < TEC [7:0]
REC[7:0]
in CnERC
register
00H ≤ REC[7:0] ≤ 80H
Undefined
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
(b) Forced recovery operation that skips bus-off recovery sequence
The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping
the bus-off recovery sequence. Here is the procedure.
First, the CAN module requests to enter the initialization mode. For the operation and points to be noted
at this time, refer to 15.3.6 (5) (a) Recovery from bus-off state through normal recovery sequence.
Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the CnCTRL
register must be set to 1.
As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the
module immediately enters the operation mode. In this case, the module is connected to the CAN bus
after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure
15-53.
Caution This function is not defined by the CAN protocol ISO 11898. When using this function,
thoroughly evaluate its effect on the network system.
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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(6) Initializing CAN module error counter register (CnERC) in initialization mode
If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information
register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting
the CCERC bit of the CnCTRL register in the initialization mode. When initialization has been completed, the
CCERC bit is automatically cleared to 0.
Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1
in a CAN operation mode, the CnERC and CnINFO registers are not initialized.
2. The CCERC bit can be set at the same time as the request to enter a CAN operation
mode.
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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15.3.7 Baud rate control function
(1) Prescaler
The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a
CAN protocol layer base clock (fTQ) that is the CAN module system clock (fCANMOD) divided by 1 to 256 (refer
to 15.6 (12) CAN module bit rate prescaler register (CnBRP)).
(2) Data bit time (8 to 25 time quanta)
One data bit time is defined as figure 14-8. The CAN controller sets time segment 1, time segment 2, and
resynchronization Jump Width (SJW) as the data bit time, as shown in Figure 15-18. Time segment 1 is
equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the CAN
protocol specification. Time segment 2 is equivalent to phase segment 2.
Figure 15-18. Segment Setting
Data bit time(DBT)
Sync segment
Prop segment
Phase segment 1
Phase segment 2
Time segment 2
(TSEG2)
Time segment 1(TSEG1)
Sample point (SPT)
Segment name
Settable range
2TQ to 16TQ
Notes on setting to conform to CAN specification
—
Time segment 1 (TSEG1)
Time segment 2 (TSEG2)
1TQ to 8TQ
IPTNote of the CAN controller is 0TQ. To conform to the
CAN protocol specification, therefore, a length equal to
phase segment 1 must be set here. This means that the
length of time segment 1 minus 1TQ is the settable upper
limit of time segment 2.
resynchronization Jump Width
(SJW)
1TQ to 4TQ
The length of time segment 1 minus 1TQ or 4 TQ,
whichever is smaller.
Note IPT: Information Processing Time
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Reference: The CAN protocol specification defines the segments constituting the data bit time as shown in Figure
15-19.
Figure 15-19. Reference: Configuration of Data Bit Time Defined by CAN Specification
Data bit time(DBT)
Sync segment
Prop segment
Phase segment 1
Phase segment 2
SJW
Sample point (SPT)
Segment name
Segment length
Description
Sync segment
1
This segment starts at the edge where the level changes
from recessive to dominant when hardware synchronization
is established.
(Synchronization segment)
Prop segment
Programmable to 1 to 8
or more great
This segment absorbs the delay of the output buffer, CAN
bus, and input buffer.
(Propagation segment)
The length of this segment is set so that ACK is returned
before the start of phase segment 1.
Phase segment 1
Programmable to 1 to 8
Time of prop segment ≥ (Delay of output buffer) + 2 ×
(Delay of CAN bus) + (Delay of input buffer)
(Phase buffer segment 1)
Phase segment 2
Phase segment 1 or
This segment compensates for an error in the data bit time.
(Phase buffer segment 2)
IPTNote, whichever greater The longer this segment, the wider the permissible range
but the slower the communication speed.
SJW
Programmable from 1TQ This width sets the upper limit of expansion or contraction
(resynchronization Jump Width) to length of segment 1 or of the phase segment during resynchronization.
4TQ, whichever is
smaller
Note IPT: Information Processing Time
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CHAPTER 15 CAN CONTROLLER
(3) Synchronizing data bit
• The receiving node establishes synchronization by a level change on the bus because it does not have a
sync signal.
• The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
(a) Hardware synchronization
This synchronization is established when the receiving node detects the start of frame in the interframe
space.
• When a falling edge is detected on the bus that TQ means the sync segment and the next segment is
the prop segment. In this case, synchronization is established regardless of SJW.
Figure 15-20. Adjusting Synchronization of Data Bit
Interframe space
Start of frame
CAN bus
Bit timing
Phase
segment 1
Sync
segment
Prop
segment
Phase
segment 2
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(b) Resynchronization
Synchronization is established again if a level change is detected on the bus during reception (only if a
recessive level was sampled previously).
• The phase error of the edge is given by the relative position of the detected edge and sync segment.
<Sign of phase error>
0: If the edge is within the sync segment
Positive: If the edge is before the sample point (phase error)
Negative: If the edge is after the sample point (phase error)
If phase error is positive: Phase segment 1 is longer by specified SJW.
If phase error is negative: Phase segment 2 is shorter by specified SJW.
• The sample point of the data of the receiving node moves relatively due to the “discrepancy” in the baud
rate between the transmitting node and receiving node.
Figure 15-21. Resynchronization
If phase error is positive
CAN bus
Prop
segment
Sync
segment
Phase
segment 2
Bit timing
Phase segment 1
Sample point
If phase error is negative
CAN bus
Bit timing
Prop
segment
Phase
segment 2
Sync
segment
Phase segment 1
Sample point
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15.4 Connection with Target System
The CAN module has to be connected to the CAN bus using an external transceiver.
Figure 15-22. Connection to CAN Bus
CTxDn
CRxDn
CANL
CANH
CAN module
Transceiver
Remark n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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15.5 Internal Registers of CAN controller
15.5.1 CAN controller configuration
Table 15-15. List of CAN Controller Registers
(1/2)
Item
Register Name
CAN global control register (CnGMCTRL)
CAN global registers
CAN global clock selection register (CnGMCS)
CAN global automatic block transmission control register (CnGMABT)
CAN global automatic block transmission delay setting register (CnGMABTD)
CAN module mask 1 register (CnMASK1L, CnMASK1H)
CAN module mask 2 register (CnMASK2L, CnMASK2H)
CAN module mask3 register (CnMASK3L, CnMASK3H)
CAN module mask 4 registers (CnMASK4L, CnMASK4H)
CAN module control register (CnCTRL)
CAN module registers
CAN module last error information register (CnLEC)
CAN module information register (CnINFO)
CAN module error counter register (CnERC)
CAN module interrupt enable register (CnIE)
CAN module interrupt status register (CnINTS)
CAN module bit rate prescaler register (CnBRP)
CAN module bit rate register (CnBTR)
CAN module last in-pointer register (CnLIPT)
CAN module receive history list register (CnRGPT)
CAN module last out-pointer register (CnLOPT)
CAN module transmit history list register (CnTGPT)
CAN module time stamp register (CnTS)
Remark 1. n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
2. CAN global registers are identified by CnGM<register function>.
CAN module registers are identified by Cn<register function>.
Message buffer registers are identified by CnM<register function>.
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(2/2)
Item
Register Name
Message buffer registers
CAN message data byte 01 register m (CnMDATA01m)
CAN message data byte 0 register m (CnMDATA0m)
CAN message data byte 1 register m (CnMDATA1m)
CAN message data byte 23 register m (CnMDATA23m)
CAN message data byte 2 register m (CnMDATA2m)
CAN message data byte 3 register m (CnMDATA3m)
CAN message data byte 45 register m (CnMDATA45m)
CAN message data byte 4 register m (CnMDATA4m)
CAN message data byte 5 register m (CnMDATA5m)
CAN message data byte 67 register m (CnMDATA67m)
CAN message data byte 6 register m (CnMDATA6m)
CAN message data byte 7 register m (CnMDATA7m)
CAN message data length register m (CnMDLCm)
CAN message configuration register m (CnMCONFm)
CAN message ID register m (CnMIDLm, CnMIDHm)
CAN message control register m (CnMCTRLm)
Remark 1. n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
2. CAN global registers are identified by CnGM<register function>.
CAN module registers are identified by Cn<register function>.
Message buffer registers are identified by CnM<register function>.
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CHAPTER 15 CAN CONTROLLER
15.5.2 Register access type
The peripheral I/O register for the CAN controller is assigned to 03FEC000H - 03FED800H. For details, refer to
3.4.8 Programmable peripheral I/O register.
Table 15-16. Register Access Type
(1/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
−
−
−
−
8
−
√
−
√
16
√
03FEC000H
03FEC002H
03FEC006H
03FEC008H
CAN0 global control register
C0GMCTRL
C0GMCS
R/W
R/W
R/W
R/W
0000H
0FH
CAN0 global clock select register
CAN0 global block transmission control register
−
C0GMABT
C0GMABTD
√
0000H
00H
CAN0 global block transmission delay setting
register
−
03FEC040H
03FEC042H
03FEC044H
03FEC046H
03FEC048H
03FEC04AH
03FEC04CH
03FEC04EH
03FEC050H
03FEC052H
03FEC053H
03FEC054H
03FEC056H
03FEC058H
03FEC05AH
03FEC05CH
03FEC05EH
03FEC060H
03FEC062H
03FEC064H
03FEC066H
CAN0 module mask 1 register
CAN0 module mask 2 register
CAN0 module mask 3 register
CAN0 module mask 4 register
C0MASK1L
C0MASK1H
C0MASK2L
C0MASK2H
C0MASK3L
C0MASK3H
C0MASK4L
C0MASK4H
C0CTRL
C0LEC
R/W
R/W
R/W
R/W
−
−
−
−
−
−
−
−
√
√
√
√
Undefined
Undefined
Undefined
Undefined
CAN0 module control register
R/W
R/W
R
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
√
−
√
−
√
−
−
√
−
−
√
√
√
−
√
−
√
−
√
√
0000H
00H
CAN0 module last error information register
CAN0 module information register
CAN0 module error counter register
CAN0 module interrupt enable register
CAN0 module interrupt status register
CAN0 module bit rate prescaler register
CAN0 module bit rate register
C0INFO
00H
C0ERC
R
0000H
0000H
0000H
FFH
C0IE
R/W
R/W
R/W
R/W
R
C0INTS
C0BRP
C0BTR
370FH
Undefined
xx02H
Undefined
xx02H
0000H
CAN0 module last in-pointer register
CAN0 module receive history list register
CAN0 module last out-pointer register
CAN0 module transmit history list register
CAN0 module time stamp register
C0LIPT
C0RGPT
C0LOPT
C0TGPT
C0TS
R/W
R
R/W
R/W
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Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC100H
CAN0 message data byte 01 register 00
C0MDATA0100 R/W
C0MDATA000
C0MDATA100
C0MDATA2300
C0MDATA200
C0MDATA300
C0MDATA4500
C0MDATA400
C0MDATA500
C0MDATA6700
C0MDATA600
C0MDATA700
C0MDLC00
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC100H CAN0 message data byte 0 register 00
03FEC101H CAN0 message data byte 1 register 00
√
√
03FEC102H
CAN0 message data byte 23 register 00
√
√
√
03FEC102H CAN0 message data byte 2 register 00
03FEC103H CAN0 message data byte 3 register 00
√
√
03FEC104H
CAN0 message data byte 45 register 00
03FEC104H CAN0 message data byte 4 register 00
03FEC105H CAN0 message data byte 5 register 00
√
√
03FEC106H
CAN0 message data byte 67 register 00
03FEC106H CAN0 message data byte 6 register 00
03FEC107H CAN0 message data byte 7 register 00
√
√
√
√
03FEC108H
03FEC109H
03FEC10AH
03FEC10CH
03FEC10EH
CAN0 message data length code register 00
CAN0 message configuration register 00
CAN0 message ID register 00
C0MCONF00
C0MIDL00
√
√
√
C0MIDH00
CAN0 message control register 00
C0MCTRL00
00x00000
000xx000B
03FEC120H
CAN0 message data byte 01 register 01
C0MDATA0101
C0MDATA001
C0MDATA101
C0MDATA2301
C0MDATA201
C0MDATA301
C0MDATA4501
C0MDATA401
C0MDATA501
C0MDATA6701
C0MDATA601
C0MDATA701
C0MDLC01
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC120H CAN0 message data byte 0 register 01
03FEC121H CAN0 message data byte 1 register 01
√
√
03FEC122H
CAN0 message data byte 23 register 01
03FEC122H CAN0 message data byte 2 register 01
03FEC123H CAN0 message data byte 3 register 01
√
√
03FEC124H
CAN0 message data byte 45 register 01
03FEC124H CAN0 message data byte 4 register 01
03FEC125H CAN0 message data byte 5 register 01
√
√
03FEC126H
CAN0 message data byte 67 register 01
03FEC126H CAN0 message data byte 6 register 01
03FEC127H CAN0 message data byte 7 register 01
√
√
√
√
03FEC128H
03FEC129H
03FEC12AH
03FEC12CH
03FEC12EH
CAN0 message data length code register 01
CAN0 message configuration register 01
CAN0 message ID register 01
C0MCONF01
C0MIDL01
√
√
√
C0MIDH01
CAN0 message control register 01
C0MCTRL01
00x00000
000xx000B
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Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC140H
CAN0 message data byte 01 register 02
C0MDATA0102 R/W
C0MDATA002
C0MDATA102
C0MDATA2302
C0MDATA202
C0MDATA302
C0MDATA4502
C0MDATA402
C0MDATA502
C0MDATA6702
C0MDATA602
C0MDATA702
C0MDLC02
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC140H CAN0 message data byte 0 register 02
03FEC141H CAN0 message data byte 1 register 02
√
√
03FEC142H
CAN0 message data byte 23 register 02
√
√
√
03FEC142H CAN0 message data byte 2 register 02
03FEC143H CAN0 message data byte 3 register 02
√
√
03FEC144H
CAN0 message data byte 45 register 02
03FEC144H CAN0 message data byte 4 register 02
03FEC145H CAN0 message data byte 5 register 02
√
√
03FEC146H
CAN0 message data byte 67 register 02
03FEC146H CAN0 message data byte 6 register 02
03FEC147H CAN0 message data byte 7 register 02
√
√
√
√
03FEC148H
03FEC149H
03FEC14AH
03FEC14CH
03FEC14EH
CAN0 message data length code register 02
CAN0 message configuration register 02
CAN0 message ID register 02
C0MCONF02
C0MIDL02
√
√
√
C0MIDH02
CAN0 message control register 02
C0MCTRL02
00x00000
000xx000B
03FEC160H
CAN0 message data byte 01 register 03
C0MDATA0103
C0MDATA003
C0MDATA103
C0MDATA2303
C0MDATA203
C0MDATA303
C0MDATA4503
C0MDATA403
C0MDATA503
C0MDATA6703
C0MDATA603
C0MDATA703
C0MDLC03
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC160H CAN0 message data byte 0 register 03
03FEC161H CAN0 message data byte 1 register 03
√
√
03FEC162H
CAN0 message data byte 23 register 03
03FEC162H CAN0 message data byte 2 register 03
03FEC163H CAN0 message data byte 3 register 03
√
√
03FEC164H
CAN0 message data byte 45 register 03
03FEC164H CAN0 message data byte 4 register 03
03FEC165H CAN0 message data byte 5 register 03
√
√
03FEC166H
CAN0 message data byte 67 register 03
03FEC166H CAN0 message data byte 6 register 03
03FEC167H CAN0 message data byte 7 register 03
√
√
√
√
03FEC168H
03FEC169H
03FEC16AH
03FEC16CH
03FEC16EH
CAN0 message data length code register 03
CAN0 message configuration register 03
CAN0 message ID register 03
C0MCONF03
C0MIDL03
√
√
√
C0MIDH03
CAN0 message control register 03
C0MCTRL03
00x00000
000xx000B
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Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC180H
03FEC180H
03FEC181H
03FEC182H
03FEC182H
03FEC183H
03FEC184H
03FEC184H
03FEC185H
03FEC186H
03FEC186H
03FEC187H
03FEC188H
03FEC189H
03FEC18AH
03FEC18CH
03FEC18EH
CAN0 message data byte 01 register 04
CAN0 message data byte 0 register 04
CAN0 message data byte 1 register 04
CAN0 message data byte 23 register 04
CAN0 message data byte 2 register 04
CAN0 message data byte 3 register 04
CAN0 message data byte 45 register 04
CAN0 message data byte 4 register 04
CAN0 message data byte 5 register 04
CAN0 message data byte 67 register 04
CAN0 message data byte 6 register 04
CAN0 message data byte 7 register 04
CAN0 message data length code register 04
CAN0 message configuration register 04
CAN0 message ID register 04
C0MDATA0104 R/W
C0MDATA004
C0MDATA104
C0MDATA2304
C0MDATA204
C0MDATA304
C0MDATA4504
C0MDATA404
C0MDATA504
C0MDATA6704
C0MDATA604
C0MDATA704
C0MDLC04
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF04
C0MIDL04
√
√
√
C0MIDH04
CAN0 message control register 04
C0MCTRL04
00x00000
000xx000B
03FEC1A0H
03FEC1A0H
03FEC1A1H
03FEC1A2H
03FEC1A2H
03FEC1A3H
03FEC1A4H
03FEC1A4H
03FEC1A5H
03FEC1A6H
03FEC1A6H
03FEC1A7H
03FEC1A8H
03FEC1A9H
03FEC1AAH
03FEC1ACH
03FEC1AEH
CAN0 message data byte 01 register 05
CAN0 message data byte 0 register 05
CAN0 message data byte 1 register 05
CAN0 message data byte 23 register 05
CAN0 message data byte 2 register 05
CAN0 message data byte 3 register 05
CAN0 message data byte 45 register 05
CAN0 message data byte 4 register 05
CAN0 message data byte 5 register 05
CAN0 message data byte 67 register 05
CAN0 message data byte 6 register 05
CAN0 message data byte 7 register 05
CAN0 message data length code register 05
CAN0 message configuration register 05
CAN0 message ID register 05
C0MDATA0105
C0MDATA005
C0MDATA105
C0MDATA2305
C0MDATA205
C0MDATA305
C0MDATA4505
C0MDATA405
C0MDATA505
C0MDATA6705
C0MDATA605
C0MDATA705
C0MDLC05
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF05
C0MIDL05
√
√
√
C0MIDH05
CAN0 message control register 05
C0MCTRL05
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
591
CHAPTER 15 CAN CONTROLLER
(5/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC1C0H
03FEC1C0H
03FEC1C1H
03FEC1C2H
03FEC1C2H
03FEC1C3H
03FEC1C4H
03FEC1C4H
03FEC1C5H
03FEC1C6H
03FEC1C6H
03FEC1C7H
03FEC1C8H
03FEC1C9H
03FEC1CAH
03FEC1CCH
03FEC1CEH
CAN0 message data byte 01 register 06
CAN0 message data byte 0 register 06
CAN0 message data byte 1 register 06
CAN0 message data byte 23 register 06
CAN0 message data byte 2 register 06
CAN0 message data byte 3 register 06
CAN0 message data byte 45 register 06
CAN0 message data byte 4 register 06
CAN0 message data byte 5 register 06
CAN0 message data byte 67 register 06
CAN0 message data byte 6 register 06
CAN0 message data byte 7 register 06
CAN0 message data length code register 06
CAN0 message configuration register 06
CAN0 message ID register 06
C0MDATA0106 R/W
C0MDATA006
C0MDATA106
C0MDATA2306
C0MDATA206
C0MDATA306
C0MDATA4506
C0MDATA406
C0MDATA506
C0MDATA6706
C0MDATA606
C0MDATA706
C0MDLC06
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF06
C0MIDL06
√
√
√
C0MIDH06
CAN0 message control register 06
C0MCTRL06
00x00000
000xx000B
03FEC1E0H
03FEC1E0H
03FEC1E1H
03FEC1E2H
03FEC1E2H
03FEC1E3H
03FEC1E4H
03FEC1E4H
03FEC1E5H
03FEC1E6H
03FEC1E6H
03FEC1E7H
03FEC1E8H
03FEC1E9H
03FEC1EAH
03FEC1ECH
03FEC1EEH
CAN0 message data byte 01 register 07
CAN0 message data byte 0 register 07
CAN0 message data byte 1 register 07
CAN0 message data byte 23 register 07
CAN0 message data byte 2 register 07
CAN0 message data byte 3 register 07
CAN0 message data byte 45 register 07
CAN0 message data byte 4 register 07
CAN0 message data byte 5 register 07
CAN0 message data byte 67 register 07
CAN0 message data byte 6 register 07
CAN0 message data byte 7 register 07
CAN0 message data length code register 07
CAN0 message configuration register 07
CAN0 message ID register 07
C0MDATA0107
C0MDATA007
C0MDATA107
C0MDATA2307
C0MDATA207
C0MDATA307
C0MDATA4507
C0MDATA407
C0MDATA507
C0MDATA6707
C0MDATA607
C0MDATA707
C0MDLC07
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF07
C0MIDL07
√
√
√
C0MIDH07
CAN0 message control register 07
C0MCTRL07
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
592
CHAPTER 15 CAN CONTROLLER
(6/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC200H
03FEC200H
03FEC201H
03FEC202H
03FEC202H
03FEC203H
03FEC204H
03FEC204H
03FEC205H
03FEC206H
03FEC206H
03FEC207H
03FEC208H
03FEC209H
03FEC20AH
03FEC20CH
03FEC20EH
CAN0 message data byte 01 register 08
CAN0 message data byte 0 register 08
CAN0 message data byte 1 register 08
CAN0 message data byte 23 register 08
CAN0 message data byte 2 register 08
CAN0 message data byte 3 register 08
CAN0 message data byte 45 register 08
CAN0 message data byte 4 register 08
CAN0 message data byte 5 register 08
CAN0 message data byte 67 register 08
CAN0 message data byte 6 register 08
CAN0 message data byte 7 register 08
CAN0 message data length code register 08
CAN0 message configuration register 08
CAN0 message ID register 08
C0MDATA0108 R/W
C0MDATA008
C0MDATA108
C0MDATA2308
C0MDATA208
C0MDATA308
C0MDATA4508
C0MDATA408
C0MDATA508
C0MDATA6708
C0MDATA608
C0MDATA708
C0MDLC08
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF08
C0MIDL08
√
√
√
C0MIDH08
CAN0 message control register 08
C0MCTRL08
00x00000
000xx000B
03FEC220H
03FEC220H
03FEC221H
03FEC222H
03FEC222H
03FEC223H
03FEC224H
03FEC224H
03FEC225H
03FEC226H
03FEC226H
03FEC227H
03FEC228H
03FEC229H
03FEC22AH
03FEC22CH
03FEC22EH
CAN0 message data byte 01 register 09
CAN0 message data byte 0 register 09
CAN0 message data byte 1 register 09
CAN0 message data byte 23 register 09
CAN0 message data byte 2 register 09
CAN0 message data byte 3 register 09
CAN0 message data byte 45 register 09
CAN0 message data byte 4 register 09
CAN0 message data byte 5 register 09
CAN0 message data byte 67 register 09
CAN0 message data byte 6 register 09
CAN0 message data byte 7 register 09
CAN0 message data length code register 09
CAN0 message configuration register 09
CAN0 message ID register 09
C0MDATA0109
C0MDATA009
C0MDATA109
C0MDATA2309
C0MDATA209
C0MDATA309
C0MDATA4509
C0MDATA409
C0MDATA509
C0MDATA6709
C0MDATA609
C0MDATA709
C0MDLC09
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF09
C0MIDL09
√
√
√
C0MIDH09
CAN0 message control register 09
C0MCTRL09
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
593
CHAPTER 15 CAN CONTROLLER
(7/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC240H
03FEC240H
03FEC241H
03FEC242H
03FEC242H
03FEC243H
03FEC244H
03FEC244H
03FEC245H
03FEC246H
03FEC246H
03FEC247H
03FEC248H
03FEC249H
03FEC24AH
03FEC24CH
03FEC24EH
CAN0 message data byte 01 register 10
CAN0 message data byte 0 register 10
CAN0 message data byte 1 register 10
CAN0 message data byte 23 register 10
CAN0 message data byte 2 register 10
CAN0 message data byte 3 register 10
CAN0 message data byte 45 register 10
CAN0 message data byte 4 register 10
CAN0 message data byte 5 register 10
CAN0 message data byte 67 register 10
CAN0 message data byte 6 register 10
CAN0 message data byte 7 register 10
CAN0 message data length code register 10
CAN0 message configuration register 10
CAN0 message ID register 10
C0MDATA0110 R/W
C0MDATA010
C0MDATA110
C0MDATA2310
C0MDATA210
C0MDATA310
C0MDATA4510
C0MDATA410
C0MDATA510
C0MDATA6710
C0MDATA610
C0MDATA710
C0MDLC10
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF10
C0MIDL10
√
√
√
C0MIDH10
CAN0 message control register 10
C0MCTRL10
00x00000
000xx000B
03FEC260H
03FEC260H
03FEC261H
03FEC262H
03FEC262H
03FEC263H
03FEC264H
03FEC264H
03FEC265H
03FEC266H
03FEC266H
03FEC267H
03FEC268H
03FEC269H
03FEC26AH
03FEC26CH
03FEC26EH
CAN0 message data byte 01 register 11
CAN0 message data byte 0 register 11
CAN0 message data byte 1 register 11
CAN0 message data byte 23 register 11
CAN0 message data byte 2 register 11
CAN0 message data byte 3 register 11
CAN0 message data byte 45 register 11
CAN0 message data byte 4 register 11
CAN0 message data byte 5 register 11
CAN0 message data byte 67 register 11
CAN0 message data byte 6 register 11
CAN0 message data byte 7 register 11
CAN0 message data length code register 11
CAN0 message configuration register 11
CAN0 message ID register 11
C0MDATA0111
C0MDATA011
C0MDATA111
C0MDATA2311
C0MDATA211
C0MDATA311
C0MDATA4511
C0MDATA411
C0MDATA511
C0MDATA6711
C0MDATA611
C0MDATA711
C0MDLC11
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF11
C0MIDL11
√
√
√
C0MIDH11
CAN0 message control register 11
C0MCTRL11
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
594
CHAPTER 15 CAN CONTROLLER
(8/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC280H
03FEC280H
03FEC281H
03FEC282H
03FEC282H
03FEC283H
03FEC284H
03FEC284H
03FEC285H
03FEC286H
03FEC286H
03FEC287H
03FEC288H
03FEC289H
03FEC28AH
03FEC28CH
03FEC28EH
CAN0 message data byte 01 register 12
CAN0 message data byte 0 register 12
CAN0 message data byte 1 register 12
CAN0 message data byte 23 register 12
CAN0 message data byte 2 register 12
CAN0 message data byte 3 register 12
CAN0 message data byte 45 register 12
CAN0 message data byte 4 register 12
CAN0 message data byte 5 register 12
CAN0 message data byte 67 register 12
CAN0 message data byte 6 register 12
CAN0 message data byte 7 register 12
CAN0 message data length code register 12
CAN0 message configuration register 12
CAN0 message ID register 12
C0MDATA0112 R/W
C0MDATA012
C0MDATA112
C0MDATA2312
C0MDATA212
C0MDATA312
C0MDATA4512
C0MDATA412
C0MDATA512
C0MDATA6712
C0MDATA612
C0MDATA712
C0MDLC12
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF12
C0MIDL12
√
√
√
C0MIDH12
CAN0 message control register 12
C0MCTRL12
00x00000
000xx000B
03FEC2A0H
03FEC2A0H
03FEC2A1H
03FEC2A2H
03FEC2A2H
03FEC2A3H
03FEC2A4H
03FEC2A4H
03FEC2A5H
03FEC2A6H
03FEC2A6H
03FEC2A7H
03FEC2A8H
03FEC2A9H
03FEC2AAH
03FEC2ACH
03FEC2AEH
CAN0 message data byte 01 register 13
CAN0 message data byte 0 register 13
CAN0 message data byte 1 register 13
CAN0 message data byte 23 register 13
CAN0 message data byte 2 register 13
CAN0 message data byte 3 register 13
CAN0 message data byte 45 register 13
CAN0 message data byte 4 register 13
CAN0 message data byte 5 register 13
CAN0 message data byte 67 register 13
CAN0 message data byte 6 register 13
CAN0 message data byte 7 register 13
CAN0 message data length code register 13
CAN0 message configuration register 13
CAN0 message ID register 13
C0MDATA0113
C0MDATA013
C0MDATA113
C0MDATA2313
C0MDATA213
C0MDATA313
C0MDATA4513
C0MDATA413
C0MDATA513
C0MDATA6713
C0MDATA613
C0MDATA713
C0MDLC13
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF13
C0MIDL13
√
√
√
C0MIDH13
CAN0 message control register 13
C0MCTRL13
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
(9/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC2C0H
03FEC2C0H
03FEC2C1H
03FEC2C2H
03FEC2C2H
03FEC2C3H
03FEC2C4H
03FEC2C4H
03FEC2C5H
03FEC2C6H
03FEC2C6H
03FEC2C7H
03FEC2C8H
03FEC2C9H
03FEC2CAH
03FEC2CCH
03FEC2CEH
CAN0 message data byte 01 register 14
CAN0 message data byte 0 register 14
CAN0 message data byte 1 register 14
CAN0 message data byte 23 register 14
CAN0 message data byte 2 register 14
CAN0 message data byte 3 register 14
CAN0 message data byte 45 register 14
CAN0 message data byte 4 register 14
CAN0 message data byte 5 register 14
CAN0 message data byte 67 register 14
CAN0 message data byte 6 register 14
CAN0 message data byte 7 register 14
CAN0 message data length code register 14
CAN0 message configuration register 14
CAN0 message ID register 14
C0MDATA0114 R/W
C0MDATA014
C0MDATA114
C0MDATA2314
C0MDATA214
C0MDATA314
C0MDATA4514
C0MDATA414
C0MDATA514
C0MDATA6714
C0MDATA614
C0MDATA714
C0MDLC14
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF14
C0MIDL14
√
√
√
C0MIDH14
CAN0 message control register 14
C0MCTRL14
00x00000
000xx000B
03FEC2E0H
03FEC2E0H
03FEC2E1H
03FEC2E2H
03FEC2E2H
03FEC2E3H
03FEC2E4H
03FEC2E4H
03FEC2E5H
03FEC2E6H
03FEC2E6H
03FEC2E7H
03FEC2E8H
03FEC2E9H
03FEC2EAH
03FEC2ECH
03FEC2EEH
CAN0 message data byte 01 register 15
CAN0 message data byte 0 register 15
CAN0 message data byte 1 register 15
CAN0 message data byte 23 register 15
CAN0 message data byte 2 register 15
CAN0 message data byte 3 register 15
CAN0 message data byte 45 register 15
CAN0 message data byte 4 register 15
CAN0 message data byte 5 register 15
CAN0 message data byte 67 register 15
CAN0 message data byte 6 register 15
CAN0 message data byte 7 register 15
CAN0 message data length code register 15
CAN0 message configuration register 15
CAN0 message ID register 15
C0MDATA0115
C0MDATA015
C0MDATA115
C0MDATA2315
C0MDATA215
C0MDATA315
C0MDATA4515
C0MDATA415
C0MDATA515
C0MDATA6715
C0MDATA615
C0MDATA715
C0MDLC15
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxx
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF15
C0MIDL15
√
√
√
C0MIDH15
CAN0 message control register 15
C0MCTRL15
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
596
CHAPTER 15 CAN CONTROLLER
(10/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC300H
CAN0 message data byte 01 register 16
C0MDATA0116 R/W
C0MDATA016
C0MDATA116
C0MDATA2316
C0MDATA216
C0MDATA316
C0MDATA4516
C0MDATA416
C0MDATA516
C0MDATA6716
C0MDATA616
C0MDATA716
C0MDLC16
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC300H CAN0 message data byte 0 register 16
03FEC301H CAN0 message data byte 1 register 16
√
√
03FEC302H
CAN0 message data byte 23 register 16
√
√
√
03FEC302H CAN0 message data byte 2 register 16
03FEC303H CAN0 message data byte 3 register 16
√
√
03FEC304H
CAN0 message data byte 45 register 16
03FEC304H CAN0 message data byte 4 register 16
03FEC305H CAN0 message data byte 5 register 16
√
√
03FEC306H
CAN0 message data byte 67 register 16
03FEC306H CAN0 message data byte 6 register 16
03FEC307H CAN0 message data byte 7 register 16
√
√
√
√
03FEC308H
03FEC309H
03FEC30AH
03FEC30CH
03FEC30EH
CAN0 message data length code register 16
CAN0 message configuration register 16
CAN0 message ID register 16
C0MCONF16
C0MIDL16
√
√
√
C0MIDH16
CAN0 message control register 16
C0MCTRL16
00x00000
000xx000B
03FEC320H
CAN0 message data byte 01 register 17
C0MDATA0117
C0MDATA017
C0MDATA117
C0MDATA2317
C0MDATA217
C0MDATA317
C0MDATA4517
C0MDATA417
C0MDATA517
C0MDATA6717
C0MDATA617
C0MDATA717
C0MDLC17
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC320H CAN0 message data byte 0 register 17
03FEC321H CAN0 message data byte 1 register 17
√
√
03FEC322H
CAN0 message data byte 23 register 17
03FEC322H CAN0 message data byte 2 register 17
03FEC323H CAN0 message data byte 3 register 17
√
√
03FEC324H
CAN0 message data byte 45 register 17
03FEC324H CAN0 message data byte 4 register 17
03FEC325H CAN0 message data byte 5 register 17
√
√
03FEC326H
CAN0 message data byte 67 register 17
03FEC326H CAN0 message data byte 6 register 17
03FEC327H CAN0 message data byte 7 register 17
√
√
√
√
03FEC328H
03FEC329H
03FEC32AH
03FEC32CH
03FEC32EH
CAN0 message data length code register 17
CAN0 message configuration register 17
CAN0 message ID register 17
C0MCONF17
C0MIDL17
√
√
√
C0MIDH17
CAN0 message control register 17
C0MCTRL17
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
597
CHAPTER 15 CAN CONTROLLER
(11/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC340H
CAN0 message data byte 01 register 18
C0MDATA0118 R/W
C0MDATA018
C0MDATA118
C0MDATA2318
C0MDATA218
C0MDATA318
C0MDATA4518
C0MDATA418
C0MDATA518
C0MDATA6718
C0MDATA618
C0MDATA718
C0MDLC18
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC340H CAN0 message data byte 0 register 18
03FEC341H CAN0 message data byte 1 register 18
√
√
03FEC342H
CAN0 message data byte 23 register 18
√
√
√
03FEC342H CAN0 message data byte 2 register 18
03FEC343H CAN0 message data byte 3 register 18
√
√
03FEC344H
CAN0 message data byte 45 register 18
03FEC344H CAN0 message data byte 4 register 18
03FEC345H CAN0 message data byte 5 register 18
√
√
03FEC346H
CAN0 message data byte 67 register 18
03FEC346H CAN0 message data byte 6 register 18
03FEC347H CAN0 message data byte 7 register 18
√
√
√
√
03FEC348H
03FEC349H
03FEC34AH
03FEC34CH
03FEC34EH
CAN0 message data length code register 18
CAN0 message configuration register 18
CAN0 message ID register 18
C0MCONF18
C0MIDL18
√
√
√
C0MIDH18
CAN0 message control register 18
C0MCTRL18
00x00000
000xx000B
03FEC360H
CAN0 message data byte 01 register 19
C0MDATA0119
C0MDATA019
C0MDATA119
C0MDATA2319
C0MDATA219
C0MDATA319
C0MDATA4519
C0MDATA419
C0MDATA519
C0MDATA6719
C0MDATA619
C0MDATA719
C0MDLC19
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC360H CAN0 message data byte 0 register 19
03FEC361H CAN0 message data byte 1 register 19
√
√
03FEC362H
CAN0 message data byte 23 register 19
03FEC362H CAN0 message data byte 2 register 19
03FEC363H CAN0 message data byte 3 register 19
√
√
03FEC364H
CAN0 message data byte 45 register 19
03FEC364H CAN0 message data byte 4 register 19
03FEC365H CAN0 message data byte 5 register 19
√
√
03FEC366H
CAN0 message data byte 67 register 19
03FEC366H CAN0 message data byte 6 register 19
03FEC367H CAN0 message data byte 7 register 19
√
√
√
√
03FEC368H
03FEC369H
03FEC36AH
03FEC36CH
03FEC36EH
CAN0 message data length code register 19
CAN0 message configuration register 19
CAN0 message ID register 19
C0MCONF19
C0MIDL19
√
√
√
C0MIDH19
CAN0 message control register 19
C0MCTRL19
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
598
CHAPTER 15 CAN CONTROLLER
(12/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC380H
03FEC380H
03FEC381H
03FEC382H
03FEC382H
03FEC383H
03FEC384H
03FEC384H
03FEC385H
03FEC386H
03FEC386H
03FEC387H
03FEC388H
03FEC389H
03FEC38AH
03FEC38CH
03FEC38EH
CAN0 message data byte 01 register 20
CAN0 message data byte 0 register 20
CAN0 message data byte 1 register 20
CAN0 message data byte 23 register 20
CAN0 message data byte 2 register 20
CAN0 message data byte 3 register 20
CAN0 message data byte 45 register 20
CAN0 message data byte 4 register 20
CAN0 message data byte 5 register 20
CAN0 message data byte 67 register 20
CAN0 message data byte 6 register 20
CAN0 message data byte 7 register 20
CAN0 message data length code register 20
CAN0 message configuration register 20
CAN0 message ID register 20
C0MDATA0120 R/W
C0MDATA020
C0MDATA120
C0MDATA2320
C0MDATA220
C0MDATA320
C0MDATA4520
C0MDATA420
C0MDATA520
C0MDATA6720
C0MDATA620
C0MDATA720
C0MDLC20
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF20
C0MIDL20
√
√
√
C0MIDH20
CAN0 message control register 20
C0MCTRL20
00x00000
000xx000B
03FEC3A0H
03FEC3A0H
03FEC3A1H
03FEC3A2H
03FEC3A2H
03FEC3A3H
03FEC3A4H
03FEC3A4H
03FEC3A5H
03FEC3A6H
03FEC3A6H
03FEC3A7H
03FEC3A8H
03FEC3A9H
03FEC3AAH
03FEC3ACH
03FEC3AEH
CAN0 message data byte 01 register 21
CAN0 message data byte 0 register 21
CAN0 message data byte 1 register 21
CAN0 message data byte 23 register 21
CAN0 message data byte 2 register 21
CAN0 message data byte 3 register 21
CAN0 message data byte 45 register 21
CAN0 message data byte 4 register 21
CAN0 message data byte 5 register 21
CAN0 message data byte 67 register 21
CAN0 message data byte 6 register 21
CAN0 message data byte 7 register 21
CAN0 message data length code register 21
CAN0 message configuration register 21
CAN0 message ID register 21
C0MDATA0121
C0MDATA021
C0MDATA121
C0MDATA2321
C0MDATA221
C0MDATA321
C0MDATA4521
C0MDATA421
C0MDATA521
C0MDATA6721
C0MDATA621
C0MDATA721
C0MDLC21
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF21
C0MIDL21
√
√
√
C0MIDH21
CAN0 message control register 21
C0MCTRL21
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
599
CHAPTER 15 CAN CONTROLLER
(13/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC3C0H
03FEC3C0H
03FEC3C1H
03FEC3C2H
03FEC3C2H
03FEC3C3H
03FEC3C4H
03FEC3C4H
03FEC3C5H
03FEC3C6H
03FEC3C6H
03FEC3C7H
03FEC3C8H
03FEC3C9H
03FEC3CAH
03FEC3CCH
03FEC3CEH
CAN0 message data byte 01 register 22
CAN0 message data byte 0 register 22
CAN0 message data byte 1 register 22
CAN0 message data byte 23 register 22
CAN0 message data byte 2 register 22
CAN0 message data byte 3 register 22
CAN0 message data byte 45 register 22
CAN0 message data byte 4 register 22
CAN0 message data byte 5 register 22
CAN0 message data byte 67 register 22
CAN0 message data byte 6 register 22
CAN0 message data byte 7 register 22
CAN0 message data length code register 22
CAN0 message configuration register 22
CAN0 message ID register 22
C0MDATA0122 R/W
C0MDATA022
C0MDATA122
C0MDATA2322
C0MDATA222
C0MDATA322
C0MDATA4522
C0MDATA422
C0MDATA522
C0MDATA6722
C0MDATA622
C0MDATA722
C0MDLC22
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF22
C0MIDL22
√
√
√
C0MIDH22
CAN0 message control register 22
C0MCTRL22
00x00000
000xx000B
03FEC3E0H
03FEC3E0H
03FEC3E1H
03FEC3E2H
03FEC3E2H
03FEC3E3H
03FEC3E4H
03FEC3E4H
03FEC3E5H
03FEC3E6H
03FEC3E6H
03FEC3E7H
03FEC3E8H
03FEC3E9H
03FEC3EAH
03FEC3ECH
03FEC3EEH
CAN0 message data byte 01 register 23
CAN0 message data byte 0 register 23
CAN0 message data byte 1 register 23
CAN0 message data byte 23 register 23
CAN0 message data byte 2 register 23
CAN0 message data byte 3 register 23
CAN0 message data byte 45 register 23
CAN0 message data byte 4 register 23
CAN0 message data byte 5 register 23
CAN0 message data byte 67 register 23
CAN0 message data byte 6 register 23
CAN0 message data byte 7 register 23
CAN0 message data length code register 23
CAN0 message configuration register 23
CAN0 message ID register 23
C0MDATA0123
C0MDATA023
C0MDATA123
C0MDATA2323
C0MDATA223
C0MDATA323
C0MDATA4523
C0MDATA423
C0MDATA523
C0MDATA6723
C0MDATA623
C0MDATA723
C0MDLC23
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF23
C0MIDL23
√
√
√
C0MIDH23
CAN0 message control register 23
C0MCTRL23
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
600
CHAPTER 15 CAN CONTROLLER
(14/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC400H
03FEC400H
03FEC401H
03FEC402H
03FEC402H
03FEC403H
03FEC404H
03FEC404H
03FEC405H
03FEC406H
03FEC406H
03FEC407H
03FEC408H
03FEC409H
03FEC40AH
03FEC40CH
03FEC40EH
CAN0 message data byte 01 register 24
CAN0 message data byte 0 register 24
CAN0 message data byte 1 register 24
CAN0 message data byte 23 register 24
CAN0 message data byte 2 register 24
CAN0 message data byte 3 register 24
CAN0 message data byte 45 register 24
CAN0 message data byte 4 register 24
CAN0 message data byte 5 register 24
CAN0 message data byte 67 register 24
CAN0 message data byte 6 register 24
CAN0 message data byte 7 register 24
CAN0 message data length code register 24
CAN0 message configuration register 24
CAN0 message ID register 24
C0MDATA0124 R/W
C0MDATA024
C0MDATA124
C0MDATA2324
C0MDATA224
C0MDATA324
C0MDATA4524
C0MDATA424
C0MDATA524
C0MDATA6724
C0MDATA624
C0MDATA724
C0MDLC24
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF24
C0MIDL24
√
√
√
C0MIDH24
CAN0 message control register 24
C0MCTRL24
00x00000
000xx000B
03FEC420H
03FEC420H
03FEC421H
03FEC422H
03FEC422H
03FEC423H
03FEC424H
03FEC424H
03FEC425H
03FEC426H
03FEC426H
03FEC427H
03FEC428H
03FEC429H
03FEC42AH
03FEC42CH
03FEC42EH
CAN0 message data byte 01 register 25
CAN0 message data byte 0 register 25
CAN0 message data byte 1 register 25
CAN0 message data byte 23 register 25
CAN0 message data byte 2 register 25
CAN0 message data byte 3 register 25
CAN0 message data byte 45 register 25
CAN0 message data byte 4 register 25
CAN0 message data byte 5 register 25
CAN0 message data byte 67 register 25
CAN0 message data byte 6 register 25
CAN0 message data byte 7 register 25
CAN0 message data length code register 25
CAN0 message configuration register 25
CAN0 message ID register 25
C0MDATA0125
C0MDATA025
C0MDATA125
C0MDATA2325
C0MDATA225
C0MDATA325
C0MDATA4525
C0MDATA425
C0MDATA525
C0MDATA6725
C0MDATA625
C0MDATA725
C0MDLC25
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF25
C0MIDL25
√
√
√
C0MIDH25
CAN0 message control register 25
C0MCTRL25
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
601
CHAPTER 15 CAN CONTROLLER
(15/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC440H
03FEC440H
03FEC441H
03FEC442H
03FEC442H
03FEC443H
03FEC444H
03FEC444H
03FEC445H
03FEC446H
03FEC446H
03FEC447H
03FEC448H
03FEC449H
03FEC44AH
03FEC44CH
03FEC44EH
CAN0 message data byte 01 register 26
CAN0 message data byte 0 register 26
CAN0 message data byte 1 register 26
CAN0 message data byte 23 register 26
CAN0 message data byte 2 register 26
CAN0 message data byte 3 register 26
CAN0 message data byte 45 register 26
CAN0 message data byte 4 register 26
CAN0 message data byte 5 register 26
CAN0 message data byte 67 register 26
CAN0 message data byte 6 register 26
CAN0 message data byte 7 register 26
CAN0 message data length code register 26
CAN0 message configuration register 26
CAN0 message ID register 26
C0MDATA0126 R/W
C0MDATA026
C0MDATA126
C0MDATA2326
C0MDATA226
C0MDATA326
C0MDATA4526
C0MDATA426
C0MDATA526
C0MDATA6726
C0MDATA626
C0MDATA726
C0MDLC26
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF26
C0MIDL26
√
√
√
C0MIDH26
CAN0 message control register 26
C0MCTRL26
00x00000
000xx000B
03FEC460H
03FEC460H
03FEC461H
03FEC462H
03FEC462H
03FEC463H
03FEC464H
03FEC464H
03FEC465H
03FEC466H
03FEC466H
03FEC467H
03FEC468H
03FEC469H
03FEC46AH
03FEC46CH
03FEC46EH
CAN0 message data byte 01 register 27
CAN0 message data byte 0 register 27
CAN0 message data byte 1 register 27
CAN0 message data byte 23 register 27
CAN0 message data byte 2 register 27
CAN0 message data byte 3 register 27
CAN0 message data byte 45 register 27
CAN0 message data byte 4 register 27
CAN0 message data byte 5 register 27
CAN0 message data byte 67 register 27
CAN0 message data byte 6 register 27
CAN0 message data byte 7 register 27
CAN0 message data length code register 27
CAN0 message configuration register 27
CAN0 message ID register 27
C0MDATA0127
C0MDATA027
C0MDATA127
C0MDATA2327
C0MDATA227
C0MDATA327
C0MDATA4527
C0MDATA427
C0MDATA527
C0MDATA6727
C0MDATA627
C0MDATA727
C0MDLC27
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF27
C0MIDL27
√
√
√
C0MIDH27
CAN0 message control register 27
C0MCTRL27
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
602
CHAPTER 15 CAN CONTROLLER
(16/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC480H
03FEC480H
03FEC481H
03FEC482H
03FEC482H
03FEC483H
03FEC484H
03FEC484H
03FEC485H
03FEC486H
03FEC486H
03FEC487H
03FEC488H
03FEC489H
03FEC48AH
03FEC48CH
03FEC48EH
CAN0 message data byte 01 register 28
CAN0 message data byte 0 register 28
CAN0 message data byte 1 register 28
CAN0 message data byte 23 register 28
CAN0 message data byte 2 register 28
CAN0 message data byte 3 register 28
CAN0 message data byte 45 register 28
CAN0 message data byte 4 register 28
CAN0 message data byte 5 register 28
CAN0 message data byte 67 register 28
CAN0 message data byte 6 register 28
CAN0 message data byte 7 register 28
CAN0 message data length code register 28
CAN0 message configuration register 28
CAN0 message ID register 28
C0MDATA0128 R/W
C0MDATA028
C0MDATA128
C0MDATA2328
C0MDATA228
C0MDATA328
C0MDATA4528
C0MDATA428
C0MDATA528
C0MDATA6728
C0MDATA628
C0MDATA728
C0MDLC28
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF28
C0MIDL28
√
√
√
C0MIDH28
CAN0 message control register 28
C0MCTRL28
00x00000
000xx000B
03FEC4A0H
03FEC4A0H
03FEC4A1H
03FEC4A2H
03FEC4A2H
03FEC4A3H
03FEC4A4H
03FEC4A4H
03FEC4A5H
03FEC4A6H
03FEC4A6H
03FEC4A7H
03FEC4A8H
03FEC4A9H
03FEC4AAH
03FEC4ACH
03FEC4AEH
CAN0 message data byte 01 register 29
CAN0 message data byte 0 register 29
CAN0 message data byte 1 register 29
CAN0 message data byte 23 register 29
CAN0 message data byte 2 register 29
CAN0 message data byte 3 register 29
CAN0 message data byte 45 register 29
CAN0 message data byte 4 register 29
CAN0 message data byte 5 register 29
CAN0 message data byte 67 register 29
CAN0 message data byte 6 register 29
CAN0 message data byte 7 register 29
CAN0 message data length code register 29
CAN0 message configuration register 29
CAN0 message ID register 29
C0MDATA0129
C0MDATA029
C0MDATA129
C0MDATA2329
C0MDATA229
C0MDATA329
C0MDATA4529
C0MDATA429
C0MDATA529
C0MDATA6729
C0MDATA629
C0MDATA729
C0MDLC29
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF29
C0MIDL29
√
√
√
C0MIDH29
CAN0 message control register 29
C0MCTRL29
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
603
CHAPTER 15 CAN CONTROLLER
(17/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC4C0H
03FEC4C0H
03FEC4C1H
03FEC4C2H
03FEC4C2H
03FEC4C3H
03FEC4C4H
03FEC4C4H
03FEC4C5H
03FEC4C6H
03FEC4C6H
03FEC4C7H
03FEC4C8H
03FEC4C9H
03FEC4CAH
03FEC4CCH
03FEC4CEH
CAN0 message data byte 01 register 30
CAN0 message data byte 0 register 30
CAN0 message data byte 1 register 30
CAN0 message data byte 23 register 30
CAN0 message data byte 2 register 30
CAN0 message data byte 3 register 30
CAN0 message data byte 45 register 30
CAN0 message data byte 4 register 30
CAN0 message data byte 5 register 30
CAN0 message data byte 67 register 30
CAN0 message data byte 6 register 30
CAN0 message data byte 7 register 30
CAN0 message data length code register 30
CAN0 message configuration register 30
CAN0 message ID register 30
C0MDATA0130 R/W
C0MDATA030
C0MDATA130
C0MDATA2330
C0MDATA230
C0MDATA330
C0MDATA4530
C0MDATA430
C0MDATA530
C0MDATA6730
C0MDATA630
C0MDATA730
C0MDLC30
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C0MCONF30
C0MIDL30
√
√
√
C0MIDH30
CAN0 message control register 30
C0MCTRL30
00x00000
000xx000B
03FEC4E0H
03FEC4E0H
03FEC4E1H
03FEC4E2H
03FEC4E2H
03FEC4E3H
03FEC4E4H
03FEC4E4H
03FEC4E5H
03FEC4E6H
03FEC4E6H
03FEC4E7H
03FEC4E8H
03FEC4E9H
03FEC4EAH
03FEC4ECH
03FEC4EEH
CAN0 message data byte 01 register 31
CAN0 message data byte 0 register 31
CAN0 message data byte 1 register 31
CAN0 message data byte 23 register 31
CAN0 message data byte 2 register 31
CAN0 message data byte 3 register 31
CAN0 message data byte 45 register 31
CAN0 message data byte 4 register 31
CAN0 message data byte 5 register 31
CAN0 message data byte 67 register 31
CAN0 message data byte 6 register 31
CAN0 message data byte 7 register 31
CAN0 message data length code register 31
CAN0 message configuration register 31
CAN0 message ID register 31
C0MDATA0131
C0MDATA031
C0MDATA131
C0MDATA2331
C0MDATA231
C0MDATA331
C0MDATA4531
C0MDATA431
C0MDATA531
C0MDATA6731
C0MDATA631
C0MDATA731
C0MDLC31
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxx
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C0MCONF31
C0MIDL31
√
√
√
C0MIDH31
CAN0 message control register 31
C0MCTRL31
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
604
CHAPTER 15 CAN CONTROLLER
(18/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
−
−
−
8
−
√
−
16
√
03FEC600H
03FEC602H
03FEC606H
CAN1 global control register
C1GMCTRL
C1GMCS
R/W
R/W
R/W
0000H
0FH
CAN1 global clock select register
−
CAN1 global block transmission control
register
C1GMABT
√
0000H
03FEC608H
CAN1 global block transmission delay setting
register
C1GMABTD
R/W
R/W
−
−
√
−
−
√
00H
03FEC640H
03FEC642H
03FEC644H
03FEC646H
03FEC648H
03FEC64AH
03FEC64CH
03FEC64EH
03FEC650H
03FEC652H
03FEC653H
03FEC654H
03FEC656H
03FEC658H
03FEC65AH
03FEC65CH
03FEC65EH
03FEC660H
03FEC662H
03FEC664H
03FEC666H
CAN1 module mask 1 register
CAN1 module mask 2 register
CAN1 module mask 3 register
CAN1 module mask 4 register
C1MASK1L
C1MASK1H
C1MASK2L
C1MASK2H
C1MASK3L
C1MASK3H
C1MASK4L
C1MASK4H
C1CTRL
C1LEC
Undefined
R/W
R/W
R/W
−
−
−
−
−
−
√
√
√
Undefined
Undefined
Undefined
CAN1 module control register
R/W
R/W
R
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
√
−
√
−
√
−
−
√
−
−
√
√
√
−
√
−
√
−
√
√
0000H
00H
CAN1 module last error information register
CAN1 module information register
CAN1 module error counter register
CAN1 module interrupt enable register
CAN1 module interrupt status register
CAN1 module bit rate prescaler register
CAN1 module bit rate register
C1INFO
00H
C1ERC
R
0000H
0000H
0000H
FFH
C1IE
R/W
R/W
R/W
R/W
R
C1INTS
C1BRP
C1BTR
370FH
Undefined
xx02H
Undefined
xx02H
0000H
CAN1 module last in-pointer register
CAN1 module receive history list register
CAN1 module last out-pointer register
CAN1 module transmit history list register
CAN1 module time stamp register
C1LIPT
C1RGPT
C1LOPT
C1TGPT
C1TS
R/W
R
R/W
R/W
User’s Manual U17830EE1V0UM00
605
CHAPTER 15 CAN CONTROLLER
(19/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC700H
03FEC700H
03FEC701H
03FEC702H
03FEC702H
03FEC703H
03FEC704H
03FEC704H
03FEC705H
03FEC706H
03FEC706H
03FEC707H
03FEC708H
03FEC709H
03FEC70AH
03FEC70CH
03FEC70EH
CAN1 message data byte 01 register 00
CAN1 message data byte 0 register 00
CAN1 message data byte 1 register 00
CAN1 message data byte 23 register 00
CAN1 message data byte 2 register 00
CAN1 message data byte 3 register 00
CAN1 message data byte 45 register 00
CAN1 message data byte 4 register 00
CAN1 message data byte 5 register 00
CAN1 message data byte 67 register 00
CAN1 message data byte 6 register 00
CAN1 message data byte 7 register 00
CAN1 message data length code register 00
CAN1 message configuration register 00
CAN1 message ID register 00
C1MDATA0100 R/W
C1MDATA000
C1MDATA100
C1MDATA2300
C1MDATA200
C1MDATA300
C1MDATA4500
C1MDATA400
C1MDATA500
C1MDATA6700
C1MDATA600
C1MDATA700
C1MDLC00
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF00
C1MIDL00
√
√
√
C1MIDH00
CAN1 message control register 00
C1MCTRL00
00x00000
000xx000B
03FEC720H
03FEC720H
03FEC721H
03FEC722H
03FEC722H
03FEC723H
03FEC724H
03FEC724H
03FEC725H
03FEC726H
03FEC726H
03FEC727H
03FEC728H
03FEC729H
03FEC72AH
03FEC72CH
03FEC72EH
CAN1 message data byte 01 register 01
CAN1 message data byte 0 register 01
CAN1 message data byte 1 register 01
CAN1 message data byte 23 register 01
CAN1 message data byte 2 register 01
CAN1 message data byte 3 register 01
CAN1 message data byte 45 register 01
CAN1 message data byte 4 register 01
CAN1 message data byte 5 register 01
CAN1 message data byte 67 register 01
CAN1 message data byte 6 register 01
CAN1 message data byte 7 register 01
CAN1 message data length code register 01
CAN1 message configuration register 01
CAN1 message ID register 01
C1MDATA0101
C1MDATA001
C1MDATA101
C1MDATA2301
C1MDATA201
C1MDATA301
C1MDATA4501
C1MDATA401
C1MDATA501
C1MDATA6701
C1MDATA601
C1MDATA701
C1MDLC01
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF01
C1MIDL01
√
√
√
C1MIDH01
CAN1 message control register 01
C1MCTRL01
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
(20/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC740H
03FEC740H
03FEC741H
03FEC742H
03FEC742H
03FEC743H
03FEC744H
03FEC744H
03FEC745H
03FEC746H
03FEC746H
03FEC747H
03FEC748H
03FEC749H
03FEC74AH
03FEC74CH
03FEC74EH
CAN1 message data byte 01 register 02
CAN1 message data byte 0 register 02
CAN1 message data byte 1 register 02
CAN1 message data byte 23 register 02
CAN1 message data byte 2 register 02
CAN1 message data byte 3 register 02
CAN1 message data byte 45 register 02
CAN1 message data byte 4 register 02
CAN1 message data byte 5 register 02
CAN1 message data byte 67 register 02
CAN1 message data byte 6 register 02
CAN1 message data byte 7 register 02
CAN1 message data length code register 02
CAN1 message configuration register 02
CAN1 message ID register 02
C1MDATA0102 R/W
C1MDATA002
C1MDATA102
C1MDATA2302
C1MDATA202
C1MDATA302
C1MDATA4502
C1MDATA402
C1MDATA502
C1MDATA6702
C1MDATA602
C1MDATA702
C1MDLC02
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF02
C1MIDL02
√
√
√
C1MIDH02
CAN1 message control register 02
C1MCTRL02
00x00000
000xx000B
03FEC760H
03FEC760H
03FEC761H
03FEC762H
03FEC762H
03FEC763H
03FEC764H
03FEC764H
03FEC765H
03FEC766H
03FEC766H
03FEC767H
03FEC768H
03FEC769H
03FEC76AH
03FEC76CH
03FEC76EH
CAN1 message data byte 01 register 03
CAN1 message data byte 0 register 03
CAN1 message data byte 1 register 03
CAN1 message data byte 23 register 03
CAN1 message data byte 2 register 03
CAN1 message data byte 3 register 03
CAN1 message data byte 45 register 03
CAN1 message data byte 4 register 03
CAN1 message data byte 5 register 03
CAN1 message data byte 67 register 03
CAN1 message data byte 6 register 03
CAN1 message data byte 7 register 03
CAN1 message data length code register 03
CAN1 message configuration register 03
CAN1 message ID register 03
C1MDATA0103
C1MDATA003
C1MDATA103
C1MDATA2303
C1MDATA203
C1MDATA303
C1MDATA4503
C1MDATA403
C1MDATA503
C1MDATA6703
C1MDATA603
C1MDATA703
C1MDLC03
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF03
C1MIDL03
√
√
√
C1MIDH03
CAN1 message control register 03
C1MCTRL03
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
607
CHAPTER 15 CAN CONTROLLER
(21/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC780H
03FEC780H
03FEC781H
03FEC782H
03FEC782H
03FEC783H
03FEC784H
03FEC784H
03FEC785H
03FEC786H
03FEC786H
03FEC787H
03FEC788H
03FEC789H
03FEC78AH
03FEC78CH
03FEC78EH
CAN1 message data byte 01 register 04
CAN1 message data byte 0 register 04
CAN1 message data byte 1 register 04
CAN1 message data byte 23 register 04
CAN1 message data byte 2 register 04
CAN1 message data byte 3 register 04
CAN1 message data byte 45 register 04
CAN1 message data byte 4 register 04
CAN1 message data byte 5 register 04
CAN1 message data byte 67 register 04
CAN1 message data byte 6 register 04
CAN1 message data byte 7 register 04
CAN1 message data length code register 04
CAN1 message configuration register 04
CAN1 message ID register 04
C1MDATA0104 R/W
C1MDATA004
C1MDATA104
C1MDATA2304
C1MDATA204
C1MDATA304
C1MDATA4504
C1MDATA404
C1MDATA504
C1MDATA6704
C1MDATA604
C1MDATA704
C1MDLC04
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF04
C1MIDL04
√
√
√
C1MIDH04
CAN1 message control register 04
C1MCTRL04
00x00000
000xx000B
03FEC7A0H
03FEC7A0H
03FEC7A1H
03FEC7A2H
03FEC7A2H
03FEC7A3H
03FEC7A4H
03FEC7A4H
03FEC7A5H
03FEC7A6H
03FEC7A6H
03FEC7A7H
03FEC7A8H
03FEC7A9H
03FEC7AAH
03FEC7ACH
03FEC7AEH
CAN1 message data byte 01 register 05
CAN1 message data byte 0 register 05
CAN1 message data byte 1 register 05
CAN1 message data byte 23 register 05
CAN1 message data byte 2 register 05
CAN1 message data byte 3 register 05
CAN1 message data byte 45 register 05
CAN1 message data byte 4 register 05
CAN1 message data byte 5 register 05
CAN1 message data byte 67 register 05
CAN1 message data byte 6 register 05
CAN1 message data byte 7 register 05
CAN1 message data length code register 05
CAN1 message configuration register 05
CAN1 message ID register 05
C1MDATA0105
C1MDATA005
C1MDATA105
C1MDATA2305
C1MDATA205
C1MDATA305
C1MDATA4505
C1MDATA405
C1MDATA505
C1MDATA6705
C1MDATA605
C1MDATA705
C1MDLC05
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF05
C1MIDL05
√
√
√
C1MIDH05
CAN1 message control register 05
C1MCTRL05
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
608
CHAPTER 15 CAN CONTROLLER
(22/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC7C0H
03FEC7C0H
03FEC7C1H
03FEC7C2H
03FEC7C2H
03FEC7C3H
03FEC7C4H
03FEC7C4H
03FEC7C5H
03FEC7C6H
03FEC7C6H
03FEC7C7H
03FEC7C8H
03FEC7C9H
03FEC7CAH
03FEC7CCH
03FEC7CEH
CAN1 message data byte 01 register 06
CAN1 message data byte 0 register 06
CAN1 message data byte 1 register 06
CAN1 message data byte 23 register 06
CAN1 message data byte 2 register 06
CAN1 message data byte 3 register 06
CAN1 message data byte 45 register 06
CAN1 message data byte 4 register 06
CAN1 message data byte 5 register 06
CAN1 message data byte 67 register 06
CAN1 message data byte 6 register 06
CAN1 message data byte 7 register 06
CAN1 message data length code register 06
CAN1 message configuration register 06
CAN1 message ID register 06
C1MDATA0106 R/W
C1MDATA006
C1MDATA106
C1MDATA2306
C1MDATA206
C1MDATA306
C1MDATA4506
C1MDATA406
C1MDATA506
C1MDATA6706
C1MDATA606
C1MDATA706
C1MDLC06
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF06
C1MIDL06
√
√
√
C1MIDH06
CAN1 message control register 06
C1MCTRL06
00x00000
000xx000B
03FEC7E0H
03FEC7E0H
03FEC7E1H
03FEC7E2H
03FEC7E2H
03FEC7E3H
03FEC7E4H
03FEC7E4H
03FEC7E5H
03FEC7E6H
03FEC7E6H
03FEC7E7H
03FEC7E8H
03FEC7E9H
03FEC7EAH
03FEC7ECH
03FEC7EEH
CAN1 message data byte 01 register 07
CAN1 message data byte 0 register 07
CAN1 message data byte 1 register 07
CAN1 message data byte 23 register 07
CAN1 message data byte 2 register 07
CAN1 message data byte 3 register 07
CAN1 message data byte 45 register 07
CAN1 message data byte 4 register 07
CAN1 message data byte 5 register 07
CAN1 message data byte 67 register 07
CAN1 message data byte 6 register 07
CAN1 message data byte 7 register 07
CAN1 message data length code register 07
CAN1 message configuration register 07
CAN1 message ID register 07
C1MDATA0107
C1MDATA007
C1MDATA107
C1MDATA2307
C1MDATA207
C1MDATA307
C1MDATA4507
C1MDATA407
C1MDATA507
C1MDATA6707
C1MDATA607
C1MDATA707
C1MDLC07
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF07
C1MIDL07
√
√
√
C1MIDH07
CAN1 message control register 07
C1MCTRL07
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
609
CHAPTER 15 CAN CONTROLLER
(23/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC800H
03FEC800H
03FEC801H
03FEC802H
03FEC802H
03FEC803H
03FEC804H
03FEC804H
03FEC805H
03FEC806H
03FEC806H
03FEC807H
03FEC808H
03FEC809H
03FEC80AH
03FEC80CH
03FEC80EH
CAN1 message data byte 01 register 08
CAN1 message data byte 0 register 08
CAN1 message data byte 1 register 08
CAN1 message data byte 23 register 08
CAN1 message data byte 2 register 08
CAN1 message data byte 3 register 08
CAN1 message data byte 45 register 08
CAN1 message data byte 4 register 08
CAN1 message data byte 5 register 08
CAN1 message data byte 67 register 08
CAN1 message data byte 6 register 08
CAN1 message data byte 7 register 08
CAN1 message data length code register 08
CAN1 message configuration register 08
CAN1 message ID register 08
C1MDATA0108 R/W
C1MDATA008
C1MDATA108
C1MDATA2308
C1MDATA208
C1MDATA308
C1MDATA4508
C1MDATA408
C1MDATA508
C1MDATA6708
C1MDATA608
C1MDATA708
C1MDLC08
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF08
C1MIDL08
√
√
√
C1MIDH08
CAN1 message control register 08
C1MCTRL08
00x00000
000xx000B
03FEC820H
03FEC820H
03FEC821H
03FEC822H
03FEC822H
03FEC823H
03FEC824H
03FEC824H
03FEC825H
03FEC826H
03FEC826H
03FEC827H
03FEC828H
03FEC829H
03FEC82AH
03FEC82CH
03FEC82EH
CAN1 message data byte 01 register 09
CAN1 message data byte 0 register 09
CAN1 message data byte 1 register 09
CAN1 message data byte 23 register 09
CAN1 message data byte 2 register 09
CAN1 message data byte 3 register 09
CAN1 message data byte 45 register 09
CAN1 message data byte 4 register 09
CAN1 message data byte 5 register 09
CAN1 message data byte 67 register 09
CAN1 message data byte 6 register 09
CAN1 message data byte 7 register 09
CAN1 message data length code register 09
CAN1 message configuration register 09
CAN1 message ID register 09
C1MDATA0109
C1MDATA009
C1MDATA109
C1MDATA2309
C1MDATA209
C1MDATA309
C1MDATA4509
C1MDATA409
C1MDATA509
C1MDATA6709
C1MDATA609
C1MDATA709
C1MDLC09
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF09
C1MIDL09
√
√
√
C1MIDH09
CAN1 message control register 09
C1MCTRL09
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
(24/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC840H
03FEC840H
03FEC841H
03FEC842H
03FEC842H
03FEC843H
03FEC844H
03FEC844H
03FEC845H
03FEC846H
03FEC846H
03FEC847H
03FEC848H
03FEC849H
03FEC84AH
03FEC84CH
03FEC84EH
CAN1 message data byte 01 register 10
CAN1 message data byte 0 register 10
CAN1 message data byte 1 register 10
CAN1 message data byte 23 register 10
CAN1 message data byte 2 register 10
CAN1 message data byte 3 register 10
CAN1 message data byte 45 register 10
CAN1 message data byte 4 register 10
CAN1 message data byte 5 register 10
CAN1 message data byte 67 register 10
CAN1 message data byte 6 register 10
CAN1 message data byte 7 register 10
CAN1 message data length code register 10
CAN1 message configuration register 10
CAN1 message ID register 10
C1MDATA0110 R/W
C1MDATA010
C1MDATA110
C1MDATA2310
C1MDATA210
C1MDATA310
C1MDATA4510
C1MDATA410
C1MDATA510
C1MDATA6710
C1MDATA610
C1MDATA710
C1MDLC10
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF10
C1MIDL10
√
√
√
C1MIDH10
CAN1 message control register 10
C1MCTRL10
00x00000
000xx000B
03FEC860H
03FEC860H
03FEC861H
03FEC862H
03FEC862H
03FEC863H
03FEC864H
03FEC864H
03FEC865H
03FEC866H
03FEC866H
03FEC867H
03FEC868H
03FEC869H
03FEC86AH
03FEC86CH
03FEC86EH
CAN1 message data byte 01 register 11
CAN1 message data byte 0 register 11
CAN1 message data byte 1 register 11
CAN1 message data byte 23 register 11
CAN1 message data byte 2 register 11
CAN1 message data byte 3 register 11
CAN1 message data byte 45 register 11
CAN1 message data byte 4 register 11
CAN1 message data byte 5 register 11
CAN1 message data byte 67 register 11
CAN1 message data byte 6 register 11
CAN1 message data byte 7 register 11
CAN1 message data length code register 11
CAN1 message configuration register 11
CAN1 message ID register 11
C1MDATA0111
C1MDATA011
C1MDATA111
C1MDATA2311
C1MDATA211
C1MDATA311
C1MDATA4511
C1MDATA411
C1MDATA511
C1MDATA6711
C1MDATA611
C1MDATA711
C1MDLC11
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF11
C1MIDL11
√
√
√
C1MIDH11
CAN1 message control register 11
C1MCTRL11
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
611
CHAPTER 15 CAN CONTROLLER
(25/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC880H
03FEC880H
03FEC881H
03FEC882H
03FEC882H
03FEC883H
03FEC884H
03FEC884H
03FEC885H
03FEC886H
03FEC886H
03FEC887H
03FEC888H
03FEC889H
03FEC88AH
03FEC88CH
03FEC88EH
CAN1 message data byte 01 register 12
CAN1 message data byte 0 register 12
CAN1 message data byte 1 register 12
CAN1 message data byte 23 register 12
CAN1 message data byte 2 register 12
CAN1 message data byte 3 register 12
CAN1 message data byte 45 register 12
CAN1 message data byte 4 register 12
CAN1 message data byte 5 register 12
CAN1 message data byte 67 register 12
CAN1 message data byte 6 register 12
CAN1 message data byte 7 register 12
CAN1 message data length code register 12
CAN1 message configuration register 12
CAN1 message ID register 12
C1MDATA0112 R/W
C1MDATA012
C1MDATA112
C1MDATA2312
C1MDATA212
C1MDATA312
C1MDATA4512
C1MDATA412
C1MDATA512
C1MDATA6712
C1MDATA612
C1MDATA712
C1MDLC12
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF12
C1MIDL12
√
√
√
C1MIDH12
CAN1 message control register 12
C1MCTRL12
00x00000
000xx000B
03FEC8A0H
03FEC8A0H
03FEC8A1H
03FEC8A2H
03FEC8A2H
03FEC8A3H
03FEC8A4H
03FEC8A4H
03FEC8A5H
03FEC8A6H
03FEC8A6H
03FEC8A7H
03FEC8A8H
03FEC8A9H
03FEC8AAH
03FEC8ACH
03FEC8AEH
CAN1 message data byte 01 register 13
CAN1 message data byte 0 register 13
CAN1 message data byte 1 register 13
CAN1 message data byte 23 register 13
CAN1 message data byte 2 register 13
CAN1 message data byte 3 register 13
CAN1 message data byte 45 register 13
CAN1 message data byte 4 register 13
CAN1 message data byte 5 register 13
CAN1 message data byte 67 register 13
CAN1 message data byte 6 register 13
CAN1 message data byte 7 register 13
CAN1 message data length code register 13
CAN1 message configuration register 13
CAN1 message ID register 13
C1MDATA0113
C1MDATA013
C1MDATA113
C1MDATA2313
C1MDATA213
C1MDATA313
C1MDATA4513
C1MDATA413
C1MDATA513
C1MDATA6713
C1MDATA613
C1MDATA713
C1MDLC13
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF13
C1MIDL13
√
√
√
C1MIDH13
CAN1 message control register 13
C1MCTRL13
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(26/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC8C0H
03FEC8C0H
03FEC8C1H
03FEC8C2H
03FEC8C2H
03FEC8C3H
03FEC8C4H
03FEC8C4H
03FEC8C5H
03FEC8C6H
03FEC8C6H
03FEC8C7H
03FEC8C8H
03FEC8C9H
03FEC8CAH
03FEC8CCH
03FEC8CEH
CAN1 message data byte 01 register 14
CAN1 message data byte 0 register 14
CAN1 message data byte 1 register 14
CAN1 message data byte 23 register 14
CAN1 message data byte 2 register 14
CAN1 message data byte 3 register 14
CAN1 message data byte 45 register 14
CAN1 message data byte 4 register 14
CAN1 message data byte 5 register 14
CAN1 message data byte 67 register 14
CAN1 message data byte 6 register 14
CAN1 message data byte 7 register 14
CAN1 message data length code register 14
CAN1 message configuration register 14
CAN1 message ID register 14
C1MDATA0114 R/W
C1MDATA014
C1MDATA114
C1MDATA2314
C1MDATA214
C1MDATA314
C1MDATA4514
C1MDATA414
C1MDATA514
C1MDATA6714
C1MDATA614
C1MDATA714
C1MDLC14
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF14
C1MIDL14
√
√
√
C1MIDH14
CAN1 message control register 14
C1MCTRL14
00x00000
000xx000B
03FEC8E0H
03FEC8E0H
03FEC8E1H
03FEC8E2H
03FEC8E2H
03FEC8E3H
03FEC8E4H
03FEC8E4H
03FEC8E5H
03FEC8E6H
03FEC8E6H
03FEC8E7H
03FEC8E8H
03FEC8E9H
03FEC8EAH
03FEC8ECH
03FEC8EEH
CAN1 message data byte 01 register 15
CAN1 message data byte 0 register 15
CAN1 message data byte 1 register 15
CAN1 message data byte 23 register 15
CAN1 message data byte 2 register 15
CAN1 message data byte 3 register 15
CAN1 message data byte 45 register 15
CAN1 message data byte 4 register 15
CAN1 message data byte 5 register 15
CAN1 message data byte 67 register 15
CAN1 message data byte 6 register 15
CAN1 message data byte 7 register 15
CAN1 message data length code register 15
CAN1 message configuration register 15
CAN1 message ID register 15
C1MDATA0115
C1MDATA015
C1MDATA115
C1MDATA2315
C1MDATA215
C1MDATA315
C1MDATA4515
C1MDATA415
C1MDATA515
C1MDATA6715
C1MDATA615
C1MDATA715
C1MDLC15
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF15
C1MIDL15
√
√
√
C1MIDH15
CAN1 message control register 15
C1MCTRL15
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
(27/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC900H
CAN1 message data byte 01 register 16
C1MDATA0116 R/W
C1MDATA016
C1MDATA116
C1MDATA2316
C1MDATA216
C1MDATA316
C1MDATA4516
C1MDATA416
C1MDATA516
C1MDATA6716
C1MDATA616
C1MDATA716
C1MDLC16
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC900H CAN1 message data byte 0 register 16
03FEC901H CAN1 message data byte 1 register 16
√
√
03FEC902H
CAN1 message data byte 23 register 16
√
√
√
03FEC902H CAN1 message data byte 2 register 16
03FEC903H CAN1 message data byte 3 register 16
√
√
03FEC904H
CAN1 message data byte 45 register 16
03FEC904H CAN1 message data byte 4 register 16
03FEC905H CAN1 message data byte 5 register 16
√
√
03FEC906H
CAN1 message data byte 67 register 16
03FEC906H CAN1 message data byte 6 register 16
03FEC907H CAN1 message data byte 7 register 16
√
√
√
√
03FEC908H
03FEC909H
03FEC90AH
03FEC90CH
03FEC90EH
CAN1 message data length code register 16
CAN1 message configuration register 16
CAN1 message ID register 16
C1MCONF16
C1MIDL16
√
√
√
C1MIDH16
CAN1 message control register 16
C1MCTRL16
00x00000
000xx000B
03FEC920H
CAN1 message data byte 01 register 17
C1MDATA0117
C1MDATA017
C1MDATA117
C1MDATA2317
C1MDATA217
C1MDATA317
C1MDATA4517
C1MDATA417
C1MDATA517
C1MDATA6717
C1MDATA617
C1MDATA717
C1MDLC17
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC920H CAN1 message data byte 0 register 17
03FEC921H CAN1 message data byte 1 register 17
√
√
03FEC922H
CAN1 message data byte 23 register 17
03FEC922H CAN1 message data byte 2 register 17
03FEC923H CAN1 message data byte 3 register 17
√
√
03FEC924H
CAN1 message data byte 45 register 17
03FEC924H CAN1 message data byte 4 register 17
03FEC925H CAN1 message data byte 5 register 17
√
√
03FEC926H
CAN1 message data byte 67 register 17
03FEC926H CAN1 message data byte 6 register 17
03FEC927H CAN1 message data byte 7 register 17
√
√
√
√
03FEC928H
03FEC929H
03FEC92AH
03FEC92CH
03FEC92EH
CAN1 message data length code register 17
CAN1 message configuration register 17
CAN1 message ID register 17
C1MCONF17
C1MIDL17
√
√
√
C1MIDH17
CAN1 message control register 17
C1MCTRL17
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(28/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC940H
CAN1 message data byte 01 register 18
C1MDATA0118 R/W
C1MDATA018
C1MDATA118
C1MDATA2318
C1MDATA218
C1MDATA318
C1MDATA4518
C1MDATA418
C1MDATA518
C1MDATA6718
C1MDATA618
C1MDATA718
C1MDLC18
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC940H CAN1 message data byte 0 register 18
03FEC941H CAN1 message data byte 1 register 18
√
√
03FEC942H
CAN1 message data byte 23 register 18
√
√
√
03FEC942H CAN1 message data byte 2 register 18
03FEC943H CAN1 message data byte 3 register 18
√
√
03FEC944H
CAN1 message data byte 45 register 18
03FEC944H CAN1 message data byte 4 register 18
03FEC945H CAN1 message data byte 5 register 18
√
√
03FEC946H
CAN1 message data byte 67 register 18
03FEC946H CAN1 message data byte 6 register 18
03FEC947H CAN1 message data byte 7 register 18
√
√
√
√
03FEC948H
03FEC949H
03FEC94AH
03FEC94CH
03FEC94EH
CAN1 message data length code register 18
CAN1 message configuration register 18
CAN1 message ID register 18
C1MCONF18
C1MIDL18
√
√
√
C1MIDH18
CAN1 message control register 18
C1MCTRL18
00x00000
000xx000B
03FEC960H
CAN1 message data byte 01 register 19
C1MDATA0119
C1MDATA019
C1MDATA119
C1MDATA2319
C1MDATA219
C1MDATA319
C1MDATA4519
C1MDATA419
C1MDATA519
C1MDATA6719
C1MDATA619
C1MDATA719
C1MDLC19
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FEC960H CAN1 message data byte 0 register 19
03FEC961H CAN1 message data byte 1 register 19
√
√
03FEC962H
CAN1 message data byte 23 register 19
03FEC962H CAN1 message data byte 2 register 19
03FEC963H CAN1 message data byte 3 register 19
√
√
03FEC964H
CAN1 message data byte 45 register 19
03FEC964H CAN1 message data byte 4 register 19
03FEC965H CAN1 message data byte 5 register 19
√
√
03FEC966H
CAN1 message data byte 67 register 19
03FEC966H CAN1 message data byte 6 register 19
03FEC967H CAN1 message data byte 7 register 19
√
√
√
√
03FEC968H
03FEC969H
03FEC96AH
03FEC96CH
03FEC96EH
CAN1 message data length code register 19
CAN1 message configuration register 19
CAN1 message ID register 19
C1MCONF19
C1MIDL19
√
√
√
C1MIDH19
CAN1 message control register 19
C1MCTRL19
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(29/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC980H
03FEC980H
03FEC981H
03FEC982H
03FEC982H
03FEC983H
03FEC984H
03FEC984H
03FEC985H
03FEC986H
03FEC986H
03FEC987H
03FEC988H
03FEC989H
03FEC98AH
03FEC98CH
03FEC98EH
CAN1 message data byte 01 register 20
CAN1 message data byte 0 register 20
CAN1 message data byte 1 register 20
CAN1 message data byte 23 register 20
CAN1 message data byte 2 register 20
CAN1 message data byte 3 register 20
CAN1 message data byte 45 register 20
CAN1 message data byte 4 register 20
CAN1 message data byte 5 register 20
CAN1 message data byte 67 register 20
CAN1 message data byte 6 register 20
CAN1 message data byte 7 register 20
CAN1 message data length code register 20
CAN1 message configuration register 20
CAN1 message ID register 20
C1MDATA0120 R/W
C1MDATA020
C1MDATA120
C1MDATA2320
C1MDATA220
C1MDATA320
C1MDATA4520
C1MDATA420
C1MDATA520
C1MDATA6720
C1MDATA620
C1MDATA720
C1MDLC20
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF20
C1MIDL20
√
√
√
C1MIDH20
CAN1 message control register 20
C1MCTRL20
00x00000
000xx000B
03FEC9A0H
03FEC9A0H
03FEC9A1H
03FEC9A2H
03FEC9A2H
03FEC9A3H
03FEC9A4H
03FEC9A4H
03FEC9A5H
03FEC9A6H
03FEC9A6H
03FEC9A7H
03FEC9A8H
03FEC9A9H
03FEC9AAH
03FEC9ACH
03FEC9AEH
CAN1 message data byte 01 register 21
CAN1 message data byte 0 register 21
CAN1 message data byte 1 register 21
CAN1 message data byte 23 register 21
CAN1 message data byte 2 register 21
CAN1 message data byte 3 register 21
CAN1 message data byte 45 register 21
CAN1 message data byte 4 register 21
CAN1 message data byte 5 register 21
CAN1 message data byte 67 register 21
CAN1 message data byte 6 register 21
CAN1 message data byte 7 register 21
CAN1 message data length code register 21
CAN1 message configuration register 21
CAN1 message ID register 21
C1MDATA0121
C1MDATA021
C1MDATA121
C1MDATA2321
C1MDATA221
C1MDATA321
C1MDATA4521
C1MDATA421
C1MDATA521
C1MDATA6721
C1MDATA621
C1MDATA721
C1MDLC21
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF21
C1MIDL21
√
√
√
C1MIDH21
CAN1 message control register 21
C1MCTRL21
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(30/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FEC9C0H
03FEC9C0H
03FEC9C1H
03FEC9C2H
03FEC9C2H
03FEC9C3H
03FEC9C4H
03FEC9C4H
03FEC9C5H
03FEC9C6H
03FEC9C6H
03FEC9C7H
03FEC9C8H
03FEC9C9H
03FEC9CAH
03FEC9CCH
03FEC9CEH
CAN1 message data byte 01 register 22
CAN1 message data byte 0 register 22
CAN1 message data byte 1 register 22
CAN1 message data byte 23 register 22
CAN1 message data byte 2 register 22
CAN1 message data byte 3 register 22
CAN1 message data byte 45 register 22
CAN1 message data byte 4 register 22
CAN1 message data byte 5 register 22
CAN1 message data byte 67 register 22
CAN1 message data byte 6 register 22
CAN1 message data byte 7 register 22
CAN1 message data length code register 22
CAN1 message configuration register 22
CAN1 message ID register 22
C1MDATA0122 R/W
C1MDATA022
C1MDATA122
C1MDATA2322
C1MDATA222
C1MDATA322
C1MDATA4522
C1MDATA422
C1MDATA522
C1MDATA6722
C1MDATA622
C1MDATA722
C1MDLC22
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF22
C1MIDL22
√
√
√
C1MIDH22
CAN1 message control register 22
C1MCTRL22
00x00000
000xx000B
03FEC9E0H
03FEC9E0H
03FEC9E1H
03FEC9E2H
03FEC9E2H
03FEC9E3H
03FEC9E4H
03FEC9E4H
03FEC9E5H
03FEC9E6H
03FEC9E6H
03FEC9E7H
03FEC9E8H
03FEC9E9H
03FEC9EAH
03FEC9ECH
03FEC9EEH
CAN1 message data byte 01 register 23
CAN1 message data byte 0 register 23
CAN1 message data byte 1 register 23
CAN1 message data byte 23 register 23
CAN1 message data byte 2 register 23
CAN1 message data byte 3 register 23
CAN1 message data byte 45 register 23
CAN1 message data byte 4 register 23
CAN1 message data byte 5 register 23
CAN1 message data byte 67 register 23
CAN1 message data byte 6 register 23
CAN1 message data byte 7 register 23
CAN1 message data length code register 23
CAN1 message configuration register 23
CAN1 message ID register 23
C1MDATA0123
C1MDATA023
C1MDATA123
C1MDATA2323
C1MDATA223
C1MDATA323
C1MDATA4523
C1MDATA423
C1MDATA523
C1MDATA6723
C1MDATA623
C1MDATA723
C1MDLC23
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF23
C1MIDL23
√
√
√
C1MIDH23
CAN1 message control register 23
C1MCTRL23
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(31/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECA00H
03FECA00H
03FECA01H
03FECA02H
03FECA02H
03FECA03H
03FECA04H
03FECA04H
03FECA05H
03FECA06H
03FECA06H
03FECA07H
03FECA08H
03FECA09H
03FECA0AH
03FECA0CH
03FECA0EH
CAN1 message data byte 01 register 24
CAN1 message data byte 0 register 24
CAN1 message data byte 1 register 24
CAN1 message data byte 23 register 24
CAN1 message data byte 2 register 24
CAN1 message data byte 3 register 24
CAN1 message data byte 45 register 24
CAN1 message data byte 4 register 24
CAN1 message data byte 5 register 24
CAN1 message data byte 67 register 24
CAN1 message data byte 6 register 24
CAN1 message data byte 7 register 24
CAN1 message data length code register 24
CAN1 message configuration register 24
CAN1 message ID register 24
C1MDATA0124 R/W
C1MDATA024
C1MDATA124
C1MDATA2324
C1MDATA224
C1MDATA324
C1MDATA4524
C1MDATA424
C1MDATA524
C1MDATA6724
C1MDATA624
C1MDATA724
C1MDLC24
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF24
C1MIDL24
√
√
√
C1MIDH24
CAN1 message control register 24
C1MCTRL24
00x00000
000xx000B
03FECA20H
03FECA20H
03FECA21H
03FECA22H
03FECA22H
03FECA23H
03FECA24H
03FECA24H
03FECA25H
03FECA26H
03FECA26H
03FECA27H
03FECA28H
03FECA29H
03FECA2AH
03FECA2CH
03FECA2EH
CAN1 message data byte 01 register 25
CAN1 message data byte 0 register 25
CAN1 message data byte 1 register 25
CAN1 message data byte 23 register 25
CAN1 message data byte 2 register 25
CAN1 message data byte 3 register 25
CAN1 message data byte 45 register 25
CAN1 message data byte 4 register 25
CAN1 message data byte 5 register 25
CAN1 message data byte 67 register 25
CAN1 message data byte 6 register 25
CAN1 message data byte 7 register 25
CAN1 message data length code register 25
CAN1 message configuration register 25
CAN1 message ID register 25
C1MDATA0125
C1MDATA025
C1MDATA125
C1MDATA2325
C1MDATA225
C1MDATA325
C1MDATA4525
C1MDATA425
C1MDATA525
C1MDATA6725
C1MDATA625
C1MDATA725
C1MDLC25
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF25
C1MIDL25
√
√
√
C1MIDH25
CAN1 message control register 25
C1MCTRL25
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(32/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECA40H
03FECA40H
03FECA41H
03FECA42H
03FECA42H
03FECA43H
03FECA44H
03FECA44H
03FECA45H
03FECA46H
03FECA46H
03FECA47H
03FECA48H
03FECA49H
03FECA4AH
03FECA4CH
03FECA4EH
CAN1 message data byte 01 register 26
CAN1 message data byte 0 register 26
CAN1 message data byte 1 register 26
CAN1 message data byte 23 register 26
CAN1 message data byte 2 register 26
CAN1 message data byte 3 register 26
CAN1 message data byte 45 register 26
CAN1 message data byte 4 register 26
CAN1 message data byte 5 register 26
CAN1 message data byte 67 register 26
CAN1 message data byte 6 register 26
CAN1 message data byte 7 register 26
CAN1 message data length code register 26
CAN1 message configuration register 26
CAN1 message ID register 26
C1MDATA0126 R/W
C1MDATA026
C1MDATA126
C1MDATA2326
C1MDATA226
C1MDATA326
C1MDATA4526
C1MDATA426
C1MDATA526
C1MDATA6726
C1MDATA626
C1MDATA726
C1MDLC26
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF26
C1MIDL26
√
√
√
C1MIDH26
CAN1 message control register 26
C1MCTRL26
00x00000
000xx000B
03FECA60H
03FECA60H
03FECA61H
03FECA62H
03FECA62H
03FECA63H
03FECA64H
03FECA64H
03FECA65H
03FECA66H
03FECA66H
03FECA67H
03FECA68H
03FECA69H
03FECA6AH
03FECA6CH
03FECA6EH
CAN1 message data byte 01 register 27
CAN1 message data byte 0 register 27
CAN1 message data byte 1 register 27
CAN1 message data byte 23 register 27
CAN1 message data byte 2 register 27
CAN1 message data byte 3 register 27
CAN1 message data byte 45 register 27
CAN1 message data byte 4 register 27
CAN1 message data byte 5 register 27
CAN1 message data byte 67 register 27
CAN1 message data byte 6 register 27
CAN1 message data byte 7 register 27
CAN1 message data length code register 27
CAN1 message configuration register 27
CAN1 message ID register 27
C1MDATA0127
C1MDATA027
C1MDATA127
C1MDATA2327
C1MDATA227
C1MDATA327
C1MDATA4527
C1MDATA427
C1MDATA527
C1MDATA6727
C1MDATA627
C1MDATA727
C1MDLC27
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF27
C1MIDL27
√
√
√
C1MIDH27
CAN1 message control register 27
C1MCTRL27
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
619
CHAPTER 15 CAN CONTROLLER
(33/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECA80H
03FECA80H
03FECA81H
03FECA82H
03FECA82H
03FECA83H
03FECA84H
03FECA84H
03FECA85H
03FECA86H
03FECA86H
03FECA87H
03FECA88H
03FECA89H
03FECA8AH
03FECA8CH
03FECA8EH
CAN1 message data byte 01 register 28
CAN1 message data byte 0 register 28
CAN1 message data byte 1 register 28
CAN1 message data byte 23 register 28
CAN1 message data byte 2 register 28
CAN1 message data byte 3 register 28
CAN1 message data byte 45 register 28
CAN1 message data byte 4 register 28
CAN1 message data byte 5 register 28
CAN1 message data byte 67 register 28
CAN1 message data byte 6 register 28
CAN1 message data byte 7 register 28
CAN1 message data length code register 28
CAN1 message configuration register 28
CAN1 message ID register 28
C1MDATA0128 R/W
C1MDATA028
C1MDATA128
C1MDATA2328
C1MDATA228
C1MDATA328
C1MDATA4528
C1MDATA428
C1MDATA528
C1MDATA6728
C1MDATA628
C1MDATA728
C1MDLC28
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF28
C1MIDL28
√
√
√
C1MIDH28
CAN1 message control register 28
C1MCTRL28
00x00000
000xx000B
03FECAA0H
03FECAA0H
03FECAA1H
03FECAA2H
03FECAA2H
03FECAA3H
03FECAA4H
03FECAA4H
03FECAA5H
03FECAA6H
03FECAA6H
03FECAA7H
03FECAA8H
03FECAA9H
03FECAAAH
03FECAACH
03FECAAEH
CAN1 message data byte 01 register 29
CAN1 message data byte 0 register 29
CAN1 message data byte 1 register 29
CAN1 message data byte 23 register 29
CAN1 message data byte 2 register 29
CAN1 message data byte 3 register 29
CAN1 message data byte 45 register 29
CAN1 message data byte 4 register 29
CAN1 message data byte 5 register 29
CAN1 message data byte 67 register 29
CAN1 message data byte 6 register 29
CAN1 message data byte 7 register 29
CAN1 message data length code register 29
CAN1 message configuration register 29
CAN1 message ID register 29
C1MDATA0129
C1MDATA029
C1MDATA129
C1MDATA2329
C1MDATA229
C1MDATA329
C1MDATA4529
C1MDATA429
C1MDATA529
C1MDATA6729
C1MDATA629
C1MDATA729
C1MDLC29
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF29
C1MIDL29
√
√
√
C1MIDH29
CAN1 message control register 29
C1MCTRL29
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
620
CHAPTER 15 CAN CONTROLLER
(34/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECAC0H
03FECAC0H
03FECAC1H
03FECAC2H
03FECAC2H
03FECAC3H
03FECAC4H
03FECAC4H
03FECAC5H
03FECAC6H
03FECAC6H
03FECAC7H
03FECAC8H
03FECAC9H
03FECACAH
03FECACCH
03FECACEH
CAN1 message data byte 01 register 30
CAN1 message data byte 0 register 30
CAN1 message data byte 1 register 30
CAN1 message data byte 23 register 30
CAN1 message data byte 2 register 30
CAN1 message data byte 3 register 30
CAN1 message data byte 45 register 30
CAN1 message data byte 4 register 30
CAN1 message data byte 5 register 30
CAN1 message data byte 67 register 30
CAN1 message data byte 6 register 30
CAN1 message data byte 7 register 30
CAN1 message data length code register 30
CAN1 message configuration register 30
CAN1 message ID register 30
C1MDATA0130 R/W
C1MDATA030
C1MDATA130
C1MDATA2330
C1MDATA230
C1MDATA330
C1MDATA4530
C1MDATA430
C1MDATA530
C1MDATA6730
C1MDATA630
C1MDATA730
C1MDLC30
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C1MCONF30
C1MIDL30
√
√
√
C1MIDH30
CAN1 message control register 30
C1MCTRL30
00x00000
000xx000B
03FECAE0H
03FECAE0H
03FECAE1H
03FECAE2H
03FECAE2H
03FECAE3H
03FECAE4H
03FECAE4H
03FECAE5H
03FECAE6H
03FECAE6H
03FECAE7H
03FECAE8H
03FECAE9H
03FECAEAH
03FECAECH
03FECAEEH
CAN1 message data byte 01 register 31
CAN1 message data byte 0 register 31
CAN1 message data byte 1 register 31
CAN1 message data byte 23 register 31
CAN1 message data byte 2 register 31
CAN1 message data byte 3 register 31
CAN1 message data byte 45 register 31
CAN1 message data byte 4 register 31
CAN1 message data byte 5 register 31
CAN1 message data byte 67 register 31
CAN1 message data byte 6 register 31
CAN1 message data byte 7 register 31
CAN1 message data length code register 31
CAN1 message configuration register 31
CAN1 message ID register 31
C1MDATA0131
C1MDATA031
C1MDATA131
C1MDATA2331
C1MDATA231
C1MDATA331
C1MDATA4531
C1MDATA431
C1MDATA531
C1MDATA6731
C1MDATA631
C1MDATA731
C1MDLC31
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxx
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C1MCONF31
C1MIDL31
√
√
√
C1MIDH31
CAN1 message control register 31
C1MCTRL31
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
621
CHAPTER 15 CAN CONTROLLER
(35/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
−
−
−
8
−
√
−
16
√
03FECC00H
03FECC02H
03FECC06H
CAN2 global control register
C2GMCTRL
C2GMCS
R/W
R/W
R/W
0000H
0FH
CAN2 global clock select register
−
CAN2 global block transmission control
register
C2GMABT
√
0000H
03FECC08H
CAN2 global block transmission delay setting
register
C2GMABTD
R/W
R/W
−
−
√
−
−
√
00H
03FECC40H
03FECC42H
03FECC44H
03FECC46H
03FECC48H
03FECC4AH
03FECC4CH
03FECC4EH
03FECC50H
03FECC52H
03FECC53H
03FECC54H
03FECC56H
03FECC58H
03FECC5AH
03FECC5CH
03FECC5EH
03FECC60H
03FECC62H
03FECC64H
03FECC66H
CAN2 module mask 1 register
CAN2 module mask 2 register
CAN2 module mask 3 register
CAN2 module mask 4 register
C2MASK1L
C2MASK1H
C2MASK2L
C2MASK2H
C2MASK3L
C2MASK3H
C2MASK4L
C2MASK4H
C2CTRL
C2LEC
Undefined
R/W
R/W
R/W
−
−
−
−
−
−
√
√
√
Undefined
Undefined
Undefined
CAN2 module control register
R/W
R/W
R
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
√
−
√
−
√
−
−
√
−
−
√
√
√
−
√
−
√
−
√
√
0000H
00H
CAN2 module last error information register
CAN2 module information register
CAN2 module error counter register
CAN2 module interrupt enable register
CAN2 module interrupt status register
CAN2 module bit rate prescaler register
CAN2 module bit rate register
C2INFO
00H
C2ERC
R
0000H
0000H
0000H
FFH
C2IE
R/W
R/W
R/W
R/W
R
C2INTS
C2BRP
C2BTR
370FH
Undefined
xx02H
Undefined
xx02H
0000H
CAN2 module last in-pointer register
CAN2 module receive history list register
CAN2 module last out-pointer register
CAN2 module transmit history list register
CAN2 module time stamp register
C2LIPT
C2RGPT
C2LOPT
C2TGPT
C2TS
R/W
R
R/W
R/W
User’s Manual U17830EE1V0UM00
622
CHAPTER 15 CAN CONTROLLER
(36/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECD00H
03FECD00H
03FECD01H
03FECD02H
03FECD02H
03FECD03H
03FECD04H
03FECD04H
03FECD05H
03FECD06H
03FECD06H
03FECD07H
03FECD08H
03FECD09H
03FECD0AH
03FECD0CH
03FECD0EH
CAN2 message data byte 01 register 00
CAN2 message data byte 0 register 00
CAN2 message data byte 1 register 00
CAN2 message data byte 23 register 00
CAN2 message data byte 2 register 00
CAN2 message data byte 3 register 00
CAN2 message data byte 45 register 00
CAN2 message data byte 4 register 00
CAN2 message data byte 5 register 00
CAN2 message data byte 67 register 00
CAN2 message data byte 6 register 00
CAN2 message data byte 7 register 00
CAN2 message data length code register 00
CAN2 message configuration register 00
CAN2 message ID register 00
C2MDATA0100 R/W
C2MDATA000
C2MDATA100
C2MDATA2300
C2MDATA200
C2MDATA300
C2MDATA4500
C2MDATA400
C2MDATA500
C2MDATA6700
C2MDATA600
C2MDATA700
C2MDLC00
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF00
C2MIDL00
√
√
√
C2MIDH00
CAN2 message control register 00
C2MCTRL00
00x00000
000xx000B
03FECD20H
03FECD20H
03FECD21H
03FECD22H
03FECD22H
03FECD23H
03FECD24H
03FECD24H
03FECD25H
03FECD26H
03FECD26H
03FECD27H
03FECD28H
03FECD29H
03FECD2AH
03FECD2CH
03FECD2EH
CAN2 message data byte 01 register 01
CAN2 message data byte 0 register 01
CAN2 message data byte 1 register 01
CAN2 message data byte 23 register 01
CAN2 message data byte 2 register 01
CAN2 message data byte 3 register 01
CAN2 message data byte 45 register 01
CAN2 message data byte 4 register 01
CAN2 message data byte 5 register 01
CAN2 message data byte 67 register 01
CAN2 message data byte 6 register 01
CAN2 message data byte 7 register 01
CAN2 message data length code register 01
CAN2 message register 01
C2MDATA0101
C2MDATA001
C2MDATA101
C2MDATA2301
C2MDATA201
C2MDATA301
C2MDATA4501
C2MDATA401
C2MDATA501
C2MDATA6701
C2MDATA601
C2MDATA701
C2MDLC01
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF01
C2MIDL01
CAN2 message ID register 01
√
√
√
C2MIDH01
CAN2 message control register 01
C2MCTRL01
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
623
CHAPTER 15 CAN CONTROLLER
(37/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECD40H
03FECD40H
03FECD41H
03FECD42H
03FECD42H
03FECD43H
03FECD44H
03FECD44H
03FECD45H
03FECD46H
03FECD46H
03FECD47H
03FECD48H
03FECD49H
03FECD4AH
03FECD4CH
03FECD4EH
CAN2 message data byte 01 register 02
CAN2 message data byte 0 register 02
CAN2 message data byte 1 register 02
CAN2 message data byte 23 register 02
CAN2 message data byte 2 register 02
CAN2 message data byte 3 register 02
CAN2 message data byte 45 register 02
CAN2 message data byte 4 register 02
CAN2 message data byte 5 register 02
CAN2 message data byte 67 register 02
CAN2 message data byte 6 register 02
CAN2 message data byte 7 register 02
CAN2 message data length code register 02
CAN2 message configuration register 02
CAN2 message ID register 02
C2MDATA0102 R/W
C2MDATA002
C2MDATA102
C2MDATA2302
C2MDATA202
C2MDATA302
C2MDATA4502
C2MDATA402
C2MDATA502
C2MDATA6702
C2MDATA602
C2MDATA702
C2MDLC02
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF02
C2MIDL02
√
√
√
C2MIDH02
CAN2 message control register 02
C2MCTRL02
00x00000
000xx000B
03FECD60H
03FECD60H
03FECD61H
03FECD62H
03FECD62H
03FECD63H
03FECD64H
03FECD64H
03FECD65H
03FECD66H
03FECD66H
03FECD67H
03FECD68H
03FECD69H
03FECD6AH
03FECD6CH
03FECD6EH
CAN2 message data byte 01 register 03
CAN2 message data byte 0 register 03
CAN2 message data byte 1 register 03
CAN2 message data byte 23 register 03
CAN2 message data byte 2 register 03
CAN2 message data byte 3 register 03
CAN2 message data byte 45 register 03
CAN2 message data byte 4 register 03
CAN2 message data byte 5 register 03
CAN2 message data byte 67 register 03
CAN2 message data byte 6 register 03
CAN2 message data byte 7 register 03
CAN2 message data length code register 03
CAN2 message configuration register 03
CAN2 message ID register 03
C2MDATA0103
C2MDATA003
C2MDATA103
C2MDATA2303
C2MDATA203
C2MDATA303
C2MDATA4503
C2MDATA403
C2MDATA503
C2MDATA6703
C2MDATA603
C2MDATA703
C2MDLC03
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF03
C2MIDL03
√
√
√
C2MIDH03
CAN2 message control register 03
C2MCTRL03
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
624
CHAPTER 15 CAN CONTROLLER
(38/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECD80H
03FECD80H
03FECD81H
03FECD82H
03FECD82H
03FECD83H
03FECD84H
03FECD84H
03FECD85H
03FECD86H
03FECD86H
03FECD87H
03FECD88H
03FECD89H
03FECD8AH
03FECD8CH
03FECD8EH
CAN2 message data byte 01 register 04
CAN2 message data byte 0 register 04
CAN2 message data byte 1 register 04
CAN2 message data byte 23 register 04
CAN2 message data byte 2 register 04
CAN2 message data byte 3 register 04
CAN2 message data byte 45 register 04
CAN2 message data byte 4 register 04
CAN2 message data byte 5 register 04
CAN2 message data byte 67 register 04
CAN2 message data byte 6 register 04
CAN2 message data byte 7 register 04
CAN2 message data length code register 04
CAN2 message configuration register 04
CAN2 message ID register 04
C2MDATA0104 R/W
C2MDATA004
C2MDATA104
C2MDATA2304
C2MDATA204
C2MDATA304
C2MDATA4504
C2MDATA404
C2MDATA504
C2MDATA6704
C2MDATA604
C2MDATA704
C2MDLC04
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF04
C2MIDL04
√
√
√
C2MIDH04
CAN2 message control register 04
C2MCTRL04
00x00000
000xx000B
03FECDA0H
03FECDA0H
03FECDA1H
03FECDA2H
03FECDA2H
03FECDA3H
03FECDA4H
03FECDA4H
03FECDA5H
03FECDA6H
03FECDA6H
03FECDA7H
03FECDA8H
03FECDA9H
03FECDAAH
03FECDACH
03FECDAEH
CAN2 message data byte 01 register 05
CAN2 message data byte 0 register 05
CAN2 message data byte 1 register 05
CAN2 message data byte 23 register 05
CAN2 message data byte 2 register 05
CAN2 message data byte 3 register 05
CAN2 message data byte 45 register 05
CAN2 message data byte 4 register 05
CAN2 message data byte 5 register 05
CAN2 message data byte 67 register 05
CAN2 message data byte 6 register 05
CAN2 message data byte 7 register 05
CAN2 message data length code register 05
CAN2 message configuration register 05
CAN2 message ID register 05
C2MDATA0105
C2MDATA005
C2MDATA105
C2MDATA2305
C2MDATA205
C2MDATA305
C2MDATA4505
C2MDATA405
C2MDATA505
C2MDATA6705
C2MDATA605
C2MDATA705
C2MDLC05
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF05
C2MIDL05
√
√
√
C2MIDH05
CAN2 message control register 05
C2MCTRL05
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
625
CHAPTER 15 CAN CONTROLLER
(39/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECDC0H
CAN2 message data byte 01 register 06
C2MDATA0106 R/W
C2MDATA006
C2MDATA106
C2MDATA2306
C2MDATA206
C2MDATA306
C2MDATA4506
C2MDATA406
C2MDATA506
C2MDATA6706
C2MDATA606
C2MDATA706
C2MDLC06
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FECDC0H CAN2 message data byte 0 register 06
03FECDC1H CAN2 message data byte 1 register 06
√
√
03FECDC2H
CAN2 message data byte 23 register 06
√
√
√
03FECDC2H CAN2 message data byte 2 register 06
03FECDC3H CAN2 message data byte 3 register 06
√
√
03FECDC4H
CAN2 message data byte 45 register 06
03FECDC4H CAN2 message data byte 4 register 06
03FECDC5H CAN2 message data byte 5 register 06
√
√
03FECDC6H
CAN2 message data byte 67 register 06
03FECDC6H CAN2 message data byte 6 register 06
03FECDC7H CAN2 message data byte 7 register 06
√
√
√
√
03FECDC8H
03FECDC9H
03FECDCAH
03FECDCCH
03FECDCEH
CAN2 message data length code register 06
CAN2 message configuration register 06
CAN2 message ID register 06
C2MCONF06
C2MIDL06
√
√
√
C2MIDH06
CAN2 message control register 06
C2MCTRL06
00x00000
000xx000B
03FECDE0H
03FECDE0H
03FECDE1H
03FECDE2H
03FECDE2H
03FECDE3H
03FECDE4H
03FECDE4H
03FECDE5H
03FECDE6H
03FECDE6H
03FECDE7H
03FECDE8H
03FECDE9H
03FECDEAH
03FECDECH
03FECDEEH
CAN2 message data byte 01 register 07
CAN2 message data byte 0 register 07
CAN2 message data byte 1 register 07
CAN2 message data byte 23 register 07
CAN2 message data byte 2 register 07
CAN2 message data byte 3 register 07
CAN2 message data byte 45 register 07
CAN2 message data byte 4 register 07
CAN2 message data byte 5 register 07
CAN2 message data byte 67 register 07
CAN2 message data byte 6 register 07
CAN2 message data byte 7 register 07
CAN2 message data length code register 07
CAN2 message configuration register 07
CAN2 message ID register 07
C2MDATA0107
C2MDATA007
C2MDATA107
C2MDATA2307
C2MDATA207
C2MDATA307
C2MDATA4507
C2MDATA407
C2MDATA507
C2MDATA6707
C2MDATA607
C2MDATA707
C2MDLC07
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF07
C2MIDL07
√
√
√
C2MIDH07
CAN2 message control register 07
C2MCTRL07
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
626
CHAPTER 15 CAN CONTROLLER
(40/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECE00H
03FECE00H
03FECE01H
03FECE02H
03FECE02H
03FECE03H
03FECE04H
03FECE04H
03FECE05H
03FECE06H
03FECE06H
03FECE07H
03FECE08H
03FECE09H
03FECE0AH
03FECE0CH
03FECE0EH
CAN2 message data byte 01 register 08
CAN2 message data byte 0 register 08
CAN2 message data byte 1 register 08
CAN2 message data byte 23 register 08
CAN2 message data byte 2 register 08
CAN2 message data byte 3 register 08
CAN2 message data byte 45 register 08
CAN2 message data byte 4 register 08
CAN2 message data byte 5 register 08
CAN2 message data byte 67 register 08
CAN2 message data byte 6 register 08
CAN2 message data byte 7 register 08
CAN2 message data length code register 08
CAN2 message configuration register 08
CAN2 message ID register 08
C2MDATA0108 R/W
C2MDATA008
C2MDATA108
C2MDATA2308
C2MDATA208
C2MDATA308
C2MDATA4508
C2MDATA408
C2MDATA508
C2MDATA6708
C2MDATA608
C2MDATA708
C2MDLC08
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF08
C2MIDL08
√
√
√
C2MIDH08
CAN2 message control register 08
C2MCTRL08
00x00000
000xx000B
03FECE20H
03FECE20H
03FECE21H
03FECE22H
03FECE22H
03FECE23H
03FECE24H
03FECE24H
03FECE25H
03FECE26H
03FECE26H
03FECE27H
03FECE28H
03FECE29H
03FECE2AH
03FECE2CH
03FECE2EH
CAN2 message data byte 01 register 09
CAN2 message data byte 0 register 09
CAN2 message data byte 1 register 09
CAN2 message data byte 23 register 09
CAN2 message data byte 2 register 09
CAN2 message data byte 3 register 09
CAN2 message data byte 45 register 09
CAN2 message data byte 4 register 09
CAN2 message data byte 5 register 09
CAN2 message data byte 67 register 09
CAN2 message data byte 6 register 09
CAN2 message data byte 7 register 09
CAN2 message data length code register 09
CAN2 message configuration register 09
CAN2 message ID register 09
C2MDATA0109
C2MDATA009
C2MDATA109
C2MDATA2309
C2MDATA209
C2MDATA309
C2MDATA4509
C2MDATA409
C2MDATA509
C2MDATA6709
C2MDATA609
C2MDATA709
C2MDLC09
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF09
C2MIDL09
√
√
√
C2MIDH09
CAN2 message control register 09
C2MCTRL09
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
627
CHAPTER 15 CAN CONTROLLER
(41/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECE40H
03FECE40H
03FECE41H
03FECE42H
03FECE42H
03FECE43H
03FECE44H
03FECE44H
03FECE45H
03FECE46H
03FECE46H
03FECE47H
03FECE48H
03FECE49H
03FECE4AH
03FECE4CH
03FECE4EH
CAN2 message data byte 01 register 10
CAN2 message data byte 0 register 10
CAN2 message data byte 1 register 10
CAN2 message data byte 23 register 10
CAN2 message data byte 2 register 10
CAN2 message data byte 3 register 10
CAN2 message data byte 45 register 10
CAN2 message data byte 4 register 10
CAN2 message data byte 5 register 10
CAN2 message data byte 67 register 10
CAN2 message data byte 6 register 10
CAN2 message data byte 7 register 10
CAN2 message data length code register 10
CAN2 message configuration register 10
CAN2 message ID register 10
C2MDATA0110 R/W
C2MDATA010
C2MDATA110
C2MDATA2310
C2MDATA210
C2MDATA310
C2MDATA4510
C2MDATA410
C2MDATA510
C2MDATA6710
C2MDATA610
C2MDATA710
C2MDLC10
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF10
C2MIDL10
√
√
√
C2MIDH10
CAN2 message control register 10
C2MCTRL10
00x00000
000xx000B
03FECE60H
03FECE60H
03FECE61H
03FECE62H
03FECE62H
03FECE63H
03FECE64H
03FECE64H
03FECE65H
03FECE66H
03FECE66H
03FECE67H
03FECE68H
03FECE69H
03FECE6AH
03FECE6CH
03FECE6EH
CAN2 message data byte 01 register 11
CAN2 message data byte 0 register 11
CAN2 message data byte 1 register 11
CAN2 message data byte 23 register 11
CAN2 message data byte 2 register 11
CAN2 message data byte 3 register 11
CAN2 message data byte 45 register 11
CAN2 message data byte 4 register 11
CAN2 message data byte 5 register 11
CAN2 message data byte 67 register 11
CAN2 message data byte 6 register 11
CAN2 message data byte 7 register 11
CAN2 message data length code register 11
CAN2 message configuration register 11
CAN2 message ID register 11
C2MDATA0111
C2MDATA011
C2MDATA111
C2MDATA2311
C2MDATA211
C2MDATA311
C2MDATA4511
C2MDATA411
C2MDATA511
C2MDATA6711
C2MDATA611
C2MDATA711
C2MDLC11
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF11
C2MIDL11
√
√
√
C2MIDH11
CAN2 message control register 11
C2MCTRL11
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
628
CHAPTER 15 CAN CONTROLLER
(42/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECE80H
03FECE80H
03FECE81H
03FECE82H
03FECE82H
03FECE83H
03FECE84H
03FECE84H
03FECE85H
03FECE86H
03FECE86H
03FECE87H
03FECE88H
03FECE89H
03FECE8AH
03FECE8CH
03FECE8EH
CAN2 message data byte 01 register 12
CAN2 message data byte 0 register 12
CAN2 message data byte 1 register 12
CAN2 message data byte 23 register 12
CAN2 message data byte 2 register 12
CAN2 message data byte 3 register 12
CAN2 message data byte 45 register 12
CAN2 message data byte 4 register 12
CAN2 message data byte 5 register 12
CAN2 message data byte 67 register 12
CAN2 message data byte 6 register 12
CAN2 message data byte 7 register 12
CAN2 message data length code register 12
CAN2 message configuration register 12
CAN2 message ID register 12
C2MDATA0112 R/W
C2MDATA012
C2MDATA112
C2MDATA2312
C2MDATA212
C2MDATA312
C2MDATA4512
C2MDATA412
C2MDATA512
C2MDATA6712
C2MDATA612
C2MDATA712
C2MDLC12
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF12
C2MIDL12
√
√
√
C2MIDH12
CAN2 message control register 12
C2MCTRL12
00x00000
000xx000B
03FECEA0H
03FECEA0H
03FECEA1H
03FECEA2H
03FECEA2H
03FECEA3H
03FECEA4H
03FECEA4H
03FECEA5H
03FECEA6H
03FECEA6H
03FECEA7H
03FECEE8H
03FECEA9H
03FECEAAH
03FECEACH
03FECEAEH
CAN2 message data byte 01 register 13
CAN2 message data byte 0 register 13
CAN2 message data byte 1 register 13
CAN2 message data byte 23 register 13
CAN2 message data byte 2 register 13
CAN2 message data byte 3 register 13
CAN2 message data byte 45 register 13
CAN2 message data byte 4 register 13
CAN2 message data byte 5 register 13
CAN2 message data byte 67 register 13
CAN2 message data byte 6 register 13
CAN2 message data byte 7 register 13
CAN2 message data length code register 13
CAN2 message configuration register 13
CAN2 message ID register 13
C2MDATA0113
C2MDATA013
C2MDATA113
C2MDATA2313
C2MDATA213
C2MDATA313
C2MDATA4513
C2MDATA413
C2MDATA513
C2MDATA6713
C2MDATA613
C2MDATA713
C2MDLC13
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF13
C2MIDL13
√
√
√
C2MIDH13
CAN2 message control register 13
C2MCTRL13
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
629
CHAPTER 15 CAN CONTROLLER
(43/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECEC0H
03FECEC0H
03FECEC1H
03FECEC2H
03FECEC2H
03FECEC3H
03FECEC4H
03FECEC4H
03FECEC5H
03FECEC6H
03FECEC6H
03FECEC7H
03FECEC8H
03FECEC9H
03FECECAH
03FECECCH
03FECECEH
CAN2 message data byte 01 register 14
CAN2 message data byte 0 register 14
CAN2 message data byte 1 register 14
CAN2 message data byte 23 register 14
CAN2 message data byte 2 register 14
CAN2 message data byte 3 register 14
CAN2 message data byte 45 register 14
CAN2 message data byte 4 register 14
CAN2 message data byte 5 register 14
CAN2 message data byte 67 register 14
CAN2 message data byte 6 register 14
CAN2 message data byte 7 register 14
CAN2 message data length code register 14
CAN2 message configuration register 14
CAN2 message ID register 14
C2MDATA0114 R/W
C2MDATA014
C2MDATA114
C2MDATA2314
C2MDATA214
C2MDATA314
C2MDATA4514
C2MDATA414
C2MDATA514
C2MDATA6714
C2MDATA614
C2MDATA714
C2MDLC14
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF14
C2MIDL14
√
√
√
C2MIDH14
CAN2 message control register 14
C2MCTRL14
00x00000
000xx000B
03FECEE0H
03FECEE0H
03FECEE1H
03FECEE2H
03FECEE2H
03FECEE3H
03FECEE4H
03FECEE4H
03FECEE5H
03FECEE6H
03FECEE6H
03FECEE7H
03FECEE8H
03FECEE9H
03FECEEAH
03FECEECH
03FECEEEH
CAN2 message data byte 01 register 15
CAN2 message data byte 0 register 15
CAN2 message data byte 1 register 15
CAN2 message data byte 23 register 15
CAN2 message data byte 2 register 15
CAN2 message data byte 3 register 15
CAN2 message data byte 45 register 15
CAN2 message data byte 4 register 15
CAN2 message data byte 5 register 15
CAN2 message data byte 67 register 15
CAN2 message data byte 6 register 15
CAN2 message data byte 7 register 15
CAN2 message data length code register 15
CAN2 message configuration register 15
CAN2 message ID register 15
C2MDATA0115
C2MDATA015
C2MDATA115
C2MDATA2315
C2MDATA215
C2MDATA315
C2MDATA4515
C2MDATA415
C2MDATA515
C2MDATA6715
C2MDATA615
C2MDATA715
C2MDLC15
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF15
C2MIDL15
√
√
√
C2MIDH15
CAN2 message control register 15
C2MCTRL15
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
630
CHAPTER 15 CAN CONTROLLER
(44/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECF00H
CAN2 message data byte 01 register 16
C2MDATA0116 R/W
C2MDATA016
C2MDATA116
C2MDATA2316
C2MDATA216
C2MDATA316
C2MDATA4516
C2MDATA416
C2MDATA516
C2MDATA6716
C2MDATA616
C2MDATA716
C2MDLC16
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FECF00H CAN2 message data byte 0 register 16
03FECF01H CAN2 message data byte 1 register 16
√
√
03FECF02H
CAN2 message data byte 23 register 16
√
√
√
03FECF02H CAN2 message data byte 2 register 16
03FECF03H CAN2 message data byte 3 register 16
√
√
03FECF04H
CAN2 message data byte 45 register 16
03FECF04H CAN2 message data byte 4 register 16
03FECF05H CAN2 message data byte 5 register 16
√
√
03FECF06H
CAN2 message data byte 67 register 16
03FECF06H CAN2 message data byte 6 register 16
03FECF07H CAN2 message data byte 7 register 16
√
√
√
√
03FECF08H
03FECF09H
03FECF0AH
03FECF0CH
03FECF0EH
CAN2 message data length code register 16
CAN2 message configuration register 16
CAN2 message ID register 16
C2MCONF16
C2MIDL16
√
√
√
C2MIDH16
CAN2 message control register 16
C2MCTRL16
00x00000
000xx000B
03FECF20H
CAN2 message data byte 01 register 17
C2MDATA0117
C2MDATA017
C2MDATA117
C2MDATA2317
C2MDATA217
C2MDATA317
C2MDATA4517
C2MDATA417
C2MDATA517
C2MDATA6717
C2MDATA617
C2MDATA717
C2MDLC17
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FECF20H CAN2 message data byte 0 register 17
03FECF21H CAN2 message data byte 1 register 17
√
√
03FECF22H
CAN2 message data byte 23 register 17
03FECF22H CAN2 message data byte 2 register 17
03FECF23H CAN2 message data byte 3 register 17
√
√
03FECF24H
CAN2 message data byte 45 register 17
03FECF24H CAN2 message data byte 4 register 17
03FECF25H CAN2 message data byte 5 register 17
√
√
03FECF26H
CAN2 message data byte 67 register 17
03FECF26H CAN2 message data byte 6 register 17
03FECF27H CAN2 message data byte 7 register 17
√
√
√
√
03FECF28H
03FECF29H
03FECF2AH
03FECF2CH
03FECF2EH
CAN2 message data length code register 17
CAN2 message configuration register 17
CAN2 message ID register 17
C2MCONF17
C2MIDL17
√
√
√
C2MIDH17
CAN2 message control register 17
C2MCTRL17
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
(45/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECF40H
CAN2 message data byte 01 register 18
C2MDATA0118 R/W
C2MDATA018
C2MDATA118
C2MDATA2318
C2MDATA218
C2MDATA318
C2MDATA4518
C2MDATA418
C2MDATA518
C2MDATA6718
C2MDATA618
C2MDATA718
C2MDLC18
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FECF40H CAN2 message data byte 0 register 18
03FECF41H CAN2 message data byte 1 register 18
√
√
03FECF42H
CAN2 message data byte 23 register 18
√
√
√
03FECF42H CAN2 message data byte 2 register 18
03FECF43H CAN2 message data byte 3 register 18
√
√
03FECF44H
CAN2 message data byte 45 register 18
03FECF44H CAN2 message data byte 4 register 18
03FECF45H CAN2 message data byte 5 register 18
√
√
03FECF46H
CAN2 message data byte 67 register 18
03FECF46H CAN2 message data byte 6 register 18
03FECF47H CAN2 message data byte 7 register 18
√
√
√
√
03FECF48H
03FECF49H
03FECF4AH
03FECF4CH
03FECF4EH
CAN2 message data length code register 18
CAN2 message configuration register 18
CAN2 message ID register 18
C2MCONF18
C2MIDL18
√
√
√
C2MIDH18
CAN2 message control register 18
C2MCTRL18
00x00000
000xx000B
03FECF60H
CAN2 message data byte 01 register 19
C2MDATA0119
C2MDATA019
C2MDATA119
C2MDATA2319
C2MDATA219
C2MDATA319
C2MDATA4519
C2MDATA419
C2MDATA519
C2MDATA6719
C2MDATA619
C2MDATA719
C2MDLC19
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FECF60H CAN2 message data byte 0 register 19
03FECF61H CAN2 message data byte 1 register 19
√
√
03FECF62H
CAN2 message data byte 23 register 19
03FECF62H CAN2 message data byte 2 register 19
03FECF63H CAN2 message data byte 3 register 19
√
√
03FECF64H
CAN2 message data byte 45 register 19
03FECF64H CAN2 message data byte 4 register 19
03FECF65H CAN2 message data byte 5 register 19
√
√
03FECF66H
CAN2 message data byte 67 register 19
03FECF66H CAN2 message data byte 6 register 19
03FECF67H CAN2 message data byte 7 register 19
√
√
√
√
03FECF68H
03FECF69H
03FECF6AH
03FECF6CH
03FECF6EH
CAN2 message data length code register 19
CAN2 message configuration register 19
CAN2 message ID register 19
C2MCONF19
C2MIDL19
√
√
√
C2MIDH19
CAN2 message control register 19
C2MCTRL19
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
632
CHAPTER 15 CAN CONTROLLER
(46/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECF80H
03FECF80H
03FECF81H
03FECF82H
03FECF82H
03FECF83H
03FECF84H
03FECF84H
03FECF85H
03FECF86H
03FECF86H
03FECF87H
03FECF88H
03FECF89H
03FECF8AH
03FECF8CH
03FECF8EH
CAN2 message data byte 01 register 20
CAN2 message data byte 0 register 20
CAN2 message data byte 1 register 20
CAN2 message data byte 23 register 20
CAN2 message data byte 2 register 20
CAN2 message data byte 3 register 20
CAN2 message data byte 45 register 20
CAN2 message data byte 4 register 20
CAN2 message data byte 5 register 20
CAN2 message data byte 67 register 20
CAN2 message data byte 6 register 20
CAN2 message data byte 7 register 20
CAN2 message data length code register 20
CAN2 message configuration register 20
CAN2 message ID register 20
C2MDATA0120 R/W
C2MDATA020
C2MDATA120
C2MDATA2320
C2MDATA220
C2MDATA320
C2MDATA4520
C2MDATA420
C2MDATA520
C2MDATA6720
C2MDATA620
C2MDATA720
C2MDLC20
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF20
C2MIDL20
√
√
√
C2MIDH20
CAN2 message control register 20
C2MCTRL20
00x00000
000xx000B
03FECFA0H
03FECFA0H
03FECFA1H
03FECFA2H
03FECFA2H
03FECFA3H
03FECFA4H
03FECFA4H
03FECFA5H
03FECFA6H
03FECFA6H
03FECFA7H
03FECFA8H
03FECFA9H
03FECFAAH
03FECFACH
03FECFAEH
CAN2 message data byte 01 register 21
CAN2 message data byte 0 register 21
CAN2 message data byte 1 register 21
CAN2 message data byte 23 register 21
CAN2 message data byte 2 register 21
CAN2 message data byte 3 register 21
CAN2 message data byte 45 register 21
CAN2 message data byte 4 register 21
CAN2 message data byte 5 register 21
CAN2 message data byte 67 register 21
CAN2 message data byte 6 register 21
CAN2 message data byte 7 register 21
CAN2 message data length code register 21
CAN2 message configuration register 21
CAN2 message ID register 21
C2MDATA0121
C2MDATA021
C2MDATA121
C2MDATA2321
C2MDATA221
C2MDATA321
C2MDATA4521
C2MDATA421
C2MDATA521
C2MDATA6721
C2MDATA621
C2MDATA721
C2MDLC21
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF21
C2MIDL21
√
√
√
C2MIDH21
CAN2 message control register 21
C2MCTRL21
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
633
CHAPTER 15 CAN CONTROLLER
(47/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FECFC0H
03FECFC0H
03FECFC1H
03FECFC2H
03FECFC2H
03FECFC3H
03FECFC4H
03FECFC4H
03FECFC5H
03FECFC6H
03FECFC6H
03FECFC7H
03FECFC8H
03FECFC9H
03FECFCAH
03FECFCCH
03FECFCEH
CAN2 message data byte 01 register 22
CAN2 message data byte 0 register 22
CAN2 message data byte 1 register 22
CAN2 message data byte 23 register 22
CAN2 message data byte 2 register 22
CAN2 message data byte 3 register 22
CAN2 message data byte 45 register 22
CAN2 message data byte 4 register 22
CAN2 message data byte 5 register 22
CAN2 message data byte 67 register 22
CAN2 message data byte 6 register 22
CAN2 message data byte 7 register 22
CAN2 message data length code register 22
CAN2 message configuration register 22
CAN2 message ID register 22
C2MDATA0122 R/W
C2MDATA022
C2MDATA122
C2MDATA2322
C2MDATA222
C2MDATA322
C2MDATA4522
C2MDATA422
C2MDATA522
C2MDATA6722
C2MDATA622
C2MDATA722
C2MDLC22
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF22
C2MIDL22
√
√
√
C2MIDH22
CAN2 message control register 22
C2MCTRL22
00x00000
000xx000B
03FECFE0H
03FECFE0H
03FECFE1H
03FECFE2H
03FECFE2H
03FECFE3H
03FECFE4H
03FECFE4H
03FECFE5H
03FECFE6H
03FECFE6H
03FECFE7H
03FECFE8H
03FECFE9H
03FECFEAH
03FECFECH
03FECFEEH
CAN2 message data byte 01 register 23
CAN2 message data byte 0 register 23
CAN2 message data byte 1 register 23
CAN2 message data byte 23 register 23
CAN2 message data byte 2 register 23
CAN2 message data byte 3 register 23
CAN2 message data byte 45 register 23
CAN2 message data byte 4 register 23
CAN2 message data byte 5 register 23
CAN2 message data byte 67 register 23
CAN2 message data byte 6 register 23
CAN2 message data byte 7 register 23
CAN2 message data length code register 23
CAN2 message configuration register 23
CAN2 message ID register 23
C2MDATA0123
C2MDATA023
C2MDATA123
C2MDATA2323
C2MDATA223
C2MDATA323
C2MDATA4523
C2MDATA423
C2MDATA523
C2MDATA6723
C2MDATA623
C2MDATA723
C2MDLC23
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF23
C2MIDL23
√
√
√
C2MIDH23
CAN2 message control register 23
C2MCTRL23
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
634
CHAPTER 15 CAN CONTROLLER
(48/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED000H
03FED000H
03FED001H
03FED002H
03FED002H
03FED003H
03FED004H
03FED004H
03FED005H
03FED006H
03FED006H
03FED007H
03FED008H
03FED009H
03FED00AH
03FED00CH
03FED00EH
CAN2 message data byte 01 register 24
CAN2 message data byte 0 register 24
CAN2 message data byte 1 register 24
CAN2 message data byte 23 register 24
CAN2 message data byte 2 register 24
CAN2 message data byte 3 register 24
CAN2 message data byte 45 register 24
CAN2 message data byte 4 register 24
CAN2 message data byte 5 register 24
CAN2 message data byte 67 register 24
CAN2 message data byte 6 register 24
CAN2 message data byte 7 register 24
CAN2 message data length code register 24
CAN2 message configuration register 24
CAN2 message ID register 24
C2MDATA0124 R/W
C2MDATA024
C2MDATA124
C2MDATA2324
C2MDATA224
C2MDATA324
C2MDATA4524
C2MDATA424
C2MDATA524
C2MDATA6724
C2MDATA624
C2MDATA724
C2MDLC24
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF24
C2MIDL24
√
√
√
C2MIDH24
CAN2 message control register 24
C2MCTRL24
00x00000
000xx000B
03FED020H
03FED020H
03FED021H
03FED022H
03FED022H
03FED023H
03FED024H
03FED024H
03FED025H
03FED026H
03FED026H
03FED027H
03FED028H
03FED029H
03FED02AH
03FED02CH
03FED02EH
CAN2 message data byte 01 register 25
CAN2 message data byte 0 register 25
CAN2 message data byte 1 register 25
CAN2 message data byte 23 register 25
CAN2 message data byte 2 register 25
CAN2 message data byte 3 register 25
CAN2 message data byte 45 register 25
CAN2 message data byte 4 register 25
CAN2 message data byte 5 register 25
CAN2 message data byte 67 register 25
CAN2 message data byte 6 register 25
CAN2 message data byte 7 register 25
CAN2 message data length code register 25
CAN2 message configuration register 25
CAN2 message ID register 25
C2MDATA0125
C2MDATA025
C2MDATA125
C2MDATA2325
C2MDATA225
C2MDATA325
C2MDATA4525
C2MDATA425
C2MDATA525
C2MDATA6725
C2MDATA625
C2MDATA725
C2MDLC25
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF25
C2MIDL25
√
√
√
C2MIDH25
CAN2 message control register 25
C2MCTRL25
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
635
CHAPTER 15 CAN CONTROLLER
(49/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED040H
03FED040H
03FED041H
03FED042H
03FED042H
03FED043H
03FED044H
03FED044H
03FED045H
03FED046H
03FED046H
03FED047H
03FED048H
03FED049H
03FED04AH
03FED04CH
03FED04EH
CAN2 message data byte 01 register 26
CAN2 message data byte 0 register 26
CAN2 message data byte 1 register 26
CAN2 message data byte 23 register 26
CAN2 message data byte 2 register 26
CAN2 message data byte 3 register 26
CAN2 message data byte 45 register 26
CAN2 message data byte 4 register 26
CAN2 message data byte 5 register 26
CAN2 message data byte 67 register 26
CAN2 message data byte 6 register 26
CAN2 message data byte 7 register 26
CAN2 message data length code register 26
CAN2 message configuration register 26
CAN2 message ID register 26
C2MDATA0126 R/W
C2MDATA026
C2MDATA126
C2MDATA2326
C2MDATA226
C2MDATA326
C2MDATA4526
C2MDATA426
C2MDATA526
C2MDATA6726
C2MDATA626
C2MDATA726
C2MDLC26
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF26
C2MIDL26
√
√
√
C2MIDH26
CAN2 message control register 26
C2MCTRL26
00x00000
000xx000B
03FED060H
03FED060H
03FED061H
03FED062H
03FED062H
03FED063H
03FED064H
03FED064H
03FED065H
03FED066H
03FED066H
03FED067H
03FED068H
03FED069H
03FED06AH
03FED06CH
03FED06EH
CAN2 message data byte 01 register 27
CAN2 message data byte 0 register 27
CAN2 message data byte 1 register 27
CAN2 message data byte 23 register 27
CAN2 message data byte 2 register 27
CAN2 message data byte 3 register 27
CAN2 message data byte 45 register 27
CAN2 message data byte 4 register 27
CAN2 message data byte 5 register 27
CAN2 message data byte 67 register 27
CAN2 message data byte 6 register 27
CAN2 message data byte 7 register 27
CAN2 message data length code register 27
CAN2 message configuration register 27
CAN2 message ID register 27
C2MDATA0127
C2MDATA027
C2MDATA127
C2MDATA2327
C2MDATA227
C2MDATA327
C2MDATA4527
C2MDATA427
C2MDATA527
C2MDATA6727
C2MDATA627
C2MDATA727
C2MDLC27
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF27
C2MIDL27
√
√
√
C2MIDH27
CAN2 message control register 27
C2MCTRL27
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
636
CHAPTER 15 CAN CONTROLLER
(50/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED080H
03FED080H
03FED081H
03FED082H
03FED082H
03FED083H
03FED084H
03FED084H
03FED085H
03FED086H
03FED086H
03FED087H
03FED088H
03FED089H
03FED08AH
03FED08CH
03FED08EH
CAN2 message data byte 01 register 28
CAN2 message data byte 0 register 28
CAN2 message data byte 1 register 28
CAN2 message data byte 23 register 28
CAN2 message data byte 2 register 28
CAN2 message data byte 3 register 28
CAN2 message data byte 45 register 28
CAN2 message data byte 4 register 28
CAN2 message data byte 5 register 28
CAN2 message data byte 67 register 28
CAN2 message data byte 6 register 28
CAN2 message data byte 7 register 28
CAN2 message data length code register 28
CAN2 message configuration register 28
CAN2 message ID register 28
C2MDATA0128 R/W
C2MDATA028
C2MDATA128
C2MDATA2328
C2MDATA228
C2MDATA328
C2MDATA4528
C2MDATA428
C2MDATA528
C2MDATA6728
C2MDATA628
C2MDATA728
C2MDLC28
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF28
C2MIDL28
√
√
√
C2MIDH28
CAN2 message control register 28
C2MCTRL28
00x00000
000xx000B
03FED0A0H
03FED0A0H
03FED0A1H
03FED0A2H
03FED0A2H
03FED0A3H
03FED0A4H
03FED0A4H
03FED0A5H
03FED0A6H
03FED0A6H
03FED0A7H
03FED0A8H
03FED0A9H
03FED0AAH
03FED0ACH
03FED0AEH
CAN2 message data byte 01 register 29
CAN2 message data byte 0 register 29
CAN2 message data byte 1 register 29
CAN2 message data byte 23 register 29
CAN2 message data byte 2 register 29
CAN2 message data byte 3 register 29
CAN2 message data byte 45 register 29
CAN2 message data byte 4 register 29
CAN2 message data byte 5 register 29
CAN2 message data byte 67 register 29
CAN2 message data byte 6 register 29
CAN2 message data byte 7 register 29
CAN2 message data length code register 29
CAN2 message configuration register 29
CAN2 message ID register 29
C2MDATA0129
C2MDATA029
C2MDATA129
C2MDATA2329
C2MDATA229
C2MDATA329
C2MDATA4529
C2MDATA429
C2MDATA529
C2MDATA6729
C2MDATA629
C2MDATA729
C2MDLC29
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF29
C2MIDL29
√
√
√
C2MIDH29
CAN2 message control register 29
C2MCTRL29
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
637
CHAPTER 15 CAN CONTROLLER
(51/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED0C0H
03FED0C0H
03FED0C1H
03FED0C2H
03FED0C2H
03FED0C3H
03FED0C4H
03FED0C4H
03FED0C5H
03FED0C6H
03FED0C6H
03FED0C7H
03FED0C8H
03FED0C9H
03FED0CAH
03FED0CCH
03FED0CEH
CAN2 message data byte 01 register 30
CAN2 message data byte 0 register 30
CAN2 message data byte 1 register 30
CAN2 message data byte 23 register 30
CAN2 message data byte 2 register 30
CAN2 message data byte 3 register 30
CAN2 message data byte 45 register 30
CAN2 message data byte 4 register 30
CAN2 message data byte 5 register 30
CAN2 message data byte 67 register 30
CAN2 message data byte 6 register 30
CAN2 message data byte 7 register 30
CAN2 message data length code register 30
CAN2 message configuration register 30
CAN2 message ID register 30
C2MDATA0130 R/W
C2MDATA030
C2MDATA130
C2MDATA2330
C2MDATA230
C2MDATA330
C2MDATA4530
C2MDATA430
C2MDATA530
C2MDATA6730
C2MDATA630
C2MDATA730
C2MDLC30
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C2MCONF30
C2MIDL30
√
√
√
C2MIDH30
CAN2 message control register 30
C2MCTRL30
00x00000
000xx000B
03FED0E0H
03FED0E0H
03FED0E1H
03FED0E2H
03FED0E2H
03FED0E3H
03FED0E4H
03FED0E4H
03FED0E5H
03FED0E6H
03FED0E6H
03FED0E7H
03FED0E8H
03FED0E9H
03FED0EAH
03FED0ECH
03FED0EEH
CAN2 message data byte 01 register 31
CAN2 message data byte 0 register 31
CAN2 message data byte 1 register 31
CAN2 message data byte 23 register 31
CAN2 message data byte 2 register 31
CAN2 message data byte 3 register 31
CAN2 message data byte 45 register 31
CAN2 message data byte 4 register 31
CAN2 message data byte 5 register 31
CAN2 message data byte 67 register 31
CAN2 message data byte 6 register 31
CAN2 message data byte 7 register 31
CAN2 message data length code register 31
CAN2 message configuration register 31
CAN2 message ID register 31
C2MDATA0131
C2MDATA031
C2MDATA131
C2MDATA2331
C2MDATA231
C2MDATA331
C2MDATA4531
C2MDATA431
C2MDATA531
C2MDATA6731
C2MDATA631
C2MDATA731
C2MDLC31
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxx
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C2MCONF31
C2MIDL31
√
√
√
C2MIDH31
CAN2 message control register 31
C2MCTRL31
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
638
CHAPTER 15 CAN CONTROLLER
(52/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
−
−
−
8
−
√
−
16
√
03FED200H
03FED202H
03FED206H
CAN3 global control register
C3GMCTRL
C3GMCS
R/W
R/W
R/W
0000H
0FH
CAN3 global clock select register
−
CAN3 global block transmission control
register
C3GMABT
√
0000H
03FED208H
CAN3 global block transmission delay setting
register
C3GMABTD
R/W
R/W
−
−
√
−
−
√
00H
03FED240H
03FED242H
03FED244H
03FED246H
03FED248H
03FED24AH
03FED24CH
03FED24EH
03FED250H
03FED252H
03FED253H
03FED254H
03FED256H
03FED258H
03FED25AH
03FED25CH
03FED25EH
03FED260H
03FED262H
03FED264H
03FED266H
CAN3 module mask 1 register
CAN3 module mask 2 register
CAN3 module mask 3 register
CAN3 module mask 4 register
C3MASK1L
C3MASK1H
C3MASK2L
C3MASK2H
C3MASK3L
C3MASK3H
C3MASK4L
C3MASK4H
C3CTRL
C3LEC
Undefined
R/W
R/W
R/W
−
−
−
−
−
−
√
√
√
Undefined
Undefined
Undefined
CAN3 module control register
R/W
R/W
R
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
√
−
√
−
√
−
−
√
−
−
√
√
√
−
√
−
√
−
√
√
0000H
00H
CAN3 module last error information register
CAN3 module information register
CAN3 module error counter register
CAN3 module interrupt enable register
CAN3 module interrupt status register
CAN3 module bit rate prescaler register
CAN3 module bit rate register
C3INFO
00H
C3ERC
R
0000H
0000H
0000H
FFH
C3IE
R/W
R/W
R/W
R/W
R
C3INTS
C3BRP
C3BTR
370FH
Undefined
xx02H
Undefined
xx02H
0000H
CAN3 module last in-pointer register
CAN3 module receive history list register
CAN3 module last out-pointer register
CAN3 module transmit history list register
CAN3 module time stamp register
C3LIPT
C3RGPT
C3LOPT
C3TGPT
C3TS
R/W
R
R/W
R/W
User’s Manual U17830EE1V0UM00
639
CHAPTER 15 CAN CONTROLLER
(53/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED300H
03FED300H
03FED301H
03FED302H
03FED302H
03FED303H
03FED304H
03FED304H
03FED305H
03FED306H
03FED306H
03FED307H
03FED308H
03FED309H
03FED30AH
03FED30CH
03FED30EH
CAN3 message data byte 01 register 00
CAN3 message data byte 0 register 00
CAN3 message data byte 1 register 00
CAN3 message data byte 23 register 00
CAN3 message data byte 2 register 00
CAN3 message data byte 3 register 00
CAN3 message data byte 45 register 00
CAN3 message data byte 4 register 00
CAN3 message data byte 5 register 00
CAN3 message data byte 67 register 00
CAN3 message data byte 6 register 00
CAN3 message data byte 7 register 00
CAN3 message data length code register 00
CAN3 message configuration register 00
CAN3 message ID register 00
C3MDATA0100 R/W
C3MDATA000
C3MDATA100
C3MDATA2300
C3MDATA200
C3MDATA300
C3MDATA4500
C3MDATA400
C3MDATA500
C3MDATA6700
C3MDATA600
C3MDATA700
C3MDLC00
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF00
C3MIDL00
√
√
√
C3MIDH00
CAN3 message control register 00
C3MCTRL00
00x00000
000xx000B
03FED320H
03FED320H
03FED321H
03FED322H
03FED322H
03FED323H
03FED324H
03FED324H
03FED325H
03FED326H
03FED326H
03FED327H
03FED328H
03FED329H
03FED32AH
03FED32CH
03FED32EH
CAN3 message data byte 01 register 01
CAN3 message data byte 0 register 01
CAN3 message data byte 1 register 01
CAN3 message data byte 23 register 01
CAN3 message data byte 2 register 01
CAN3 message data byte 3 register 01
CAN3 message data byte 45 register 01
CAN3 message data byte 4 register 01
CAN3 message data byte 5 register 01
CAN3 message data byte 67 register 01
CAN3 message data byte 6 register 01
CAN3 message data byte 7 register 01
CAN3 message data length code register 01
CAN3 message configuration register 01
CAN3 message ID register 01
C3MDATA0101
C3MDATA001
C3MDATA101
C3MDATA2301
C3MDATA201
C3MDATA301
C3MDATA4501
C3MDATA401
C3MDATA501
C3MDATA6701
C3MDATA601
C3MDATA701
C3MDLC01
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF01
C3MIDL01
√
√
√
C3MIDH01
CAN3 message control register 01
C3MCTRL01
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
640
CHAPTER 15 CAN CONTROLLER
(54/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED340H
03FED340H
03FED341H
03FED342H
03FED342H
03FED343H
03FED344H
03FED344H
03FED345H
03FED346H
03FED346H
03FED347H
03FED348H
03FED349H
03FED34AH
03FED34CH
03FED34EH
CAN3 message data byte 01 register 02
CAN3 message data byte 0 register 02
CAN3 message data byte 1 register 02
CAN3 message data byte 23 register 02
CAN3 message data byte 2 register 02
CAN3 message data byte 3 register 02
CAN3 message data byte 45 register 02
CAN3 message data byte 4 register 02
CAN3 message data byte 5 register 02
CAN3 message data byte 67 register 02
CAN3 message data byte 6 register 02
CAN3 message data byte 7 register 02
CAN3 message data length code register 02
CAN3 message configuration register 02
CAN3 message ID register 02
C3MDATA0102 R/W
C3MDATA002
C3MDATA102
C3MDATA2302
C3MDATA202
C3MDATA302
C3MDATA4502
C3MDATA402
C3MDATA502
C3MDATA6702
C3MDATA602
C3MDATA702
C3MDLC02
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF02
C3MIDL02
√
√
√
C3MIDH02
CAN3 message control register 02
C3MCTRL02
00x00000
000xx000B
03FED360H
03FED360H
03FED361H
03FED362H
03FED362H
03FED363H
03FED364H
03FED364H
03FED365H
03FED366H
03FED366H
03FED367H
03FED368H
03FED369H
03FED36AH
03FED36CH
03FED36EH
CAN3 message data byte 01 register 03
CAN3 message data byte 0 register 03
CAN3 message data byte 1 register 03
CAN3 message data byte 23 register 03
CAN3 message data byte 2 register 03
CAN3 message data byte 3 register 03
CAN3 message data byte 45 register 03
CAN3 message data byte 4 register 03
CAN3 message data byte 5 register 03
CAN3 message data byte 67 register 03
CAN3 message data byte 6 register 03
CAN3 message data byte 7 register 03
CAN3 message data length code register 03
CAN3 message configuration register 03
CAN3 message ID register 03
C3MDATA0103
C3MDATA003
C3MDATA103
C3MDATA2303
C3MDATA203
C3MDATA303
C3MDATA4503
C3MDATA403
C3MDATA503
C3MDATA6703
C3MDATA603
C3MDATA703
C3MDLC03
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF03
C3MIDL03
√
√
√
C3MIDH03
CAN3 message control register 03
C3MCTRL03
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
641
CHAPTER 15 CAN CONTROLLER
(55/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED380H
03FED380H
03FED381H
03FED382H
03FED382H
03FED383H
03FED384H
03FED384H
03FED385H
03FED386H
03FED386H
03FED387H
03FED388H
03FED389H
03FED38AH
03FED38CH
03FED38EH
CAN3 message data byte 01 register 04
CAN3 message data byte 0 register 04
CAN3 message data byte 1 register 04
CAN3 message data byte 23 register 04
CAN3 message data byte 2 register 04
CAN3 message data byte 3 register 04
CAN3 message data byte 45 register 04
CAN3 message data byte 4 register 04
CAN3 message data byte 5 register 04
CAN3 message data byte 67 register 04
CAN3 message data byte 6 register 04
CAN3 message data byte 7 register 04
CAN3 message data length code register 04
CAN3 message configuration register 04
CAN3 message ID register 04
C3MDATA0104 R/W
C3MDATA004
C3MDATA104
C3MDATA2304
C3MDATA204
C3MDATA304
C3MDATA4504
C3MDATA404
C3MDATA504
C3MDATA6704
C3MDATA604
C3MDATA704
C3MDLC04
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF04
C3MIDL04
√
√
√
C3MIDH04
CAN3 message control register 04
C3MCTRL04
00x00000
000xx000B
03FED3A0H
03FED3A0H
03FED3A1H
03FED3A2H
03FED3A2H
03FED3A3H
03FED3A4H
03FED3A4H
03FED3A5H
03FED3A6H
03FED3A6H
03FED3A7H
03FED3A8H
03FED3A9H
03FED3AAH
03FED3ACH
03FED3AEH
CAN3 message data byte 01 register 05
CAN3 message data byte 0 register 05
CAN3 message data byte 1 register 05
CAN3 message data byte 23 register 05
CAN3 message data byte 2 register 05
CAN3 message data byte 3 register 05
CAN3 message data byte 45 register 05
CAN3 message data byte 4 register 05
CAN3 message data byte 5 register 05
CAN3 message data byte 67 register 05
CAN3 message data byte 6 register 05
CAN3 message data byte 7 register 05
CAN3 message data length code register 05
CAN3 message configuration register 05
CAN3 message ID register 05
C3MDATA0105
C3MDATA005
C3MDATA105
C3MDATA2305
C3MDATA205
C3MDATA305
C3MDATA4505
C3MDATA405
C3MDATA505
C3MDATA6705
C3MDATA605
C3MDATA705
C3MDLC05
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF05
C3MIDL05
√
√
√
C3MIDH05
CAN3 message control register 05
C3MCTRL05
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
642
CHAPTER 15 CAN CONTROLLER
(56/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED3C0H
03FED3C0H
03FED3C1H
03FED3C2H
03FED3C2H
03FED3C3H
03FED3C4H
03FED3C4H
03FED3C5H
03FED3C6H
03FED3C6H
03FED3C7H
03FED3C8H
03FED3C9H
03FED3CAH
03FED3CCH
03FED3CEH
CAN3 message data byte 01 register 06
CAN3 message data byte 0 register 06
CAN3 message data byte 1 register 06
CAN3 message data byte 23 register 06
CAN3 message data byte 2 register 06
CAN3 message data byte 3 register 06
CAN3 message data byte 45 register 06
CAN3 message data byte 4 register 06
CAN3 message data byte 5 register 06
CAN3 message data byte 67 register 06
CAN3 message data byte 6 register 06
CAN3 message data byte 7 register 06
CAN3 message data length code register 06
CAN3 message configuration register 06
CAN3 message ID register 06
C3MDATA0106 R/W
C3MDATA006
C3MDATA106
C3MDATA2306
C3MDATA206
C3MDATA306
C3MDATA4506
C3MDATA406
C3MDATA506
C3MDATA6706
C3MDATA606
C3MDATA706
C3MDLC06
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF06
C3MIDL06
√
√
√
C3MIDH06
CAN3 message control register 06
C3MCTRL06
00x00000
000xx000B
03FED3E0H
03FED3E0H
03FED3E1H
03FED3E2H
03FED3E2H
03FED3E3H
03FED3E4H
03FED3E4H
03FED3E5H
03FED3E6H
03FED3E6H
03FED3E7H
03FED3E8H
03FED3E9H
03FED3EAH
03FED3ECH
03FED3EEH
CAN3 message data byte 01 register 07
CAN3 message data byte 0 register 07
CAN3 message data byte 1 register 07
CAN3 message data byte 23 register 07
CAN3 message data byte 2 register 07
CAN3 message data byte 3 register 07
CAN3 message data byte 45 register 07
CAN3 message data byte 4 register 07
CAN3 message data byte 5 register 07
CAN3 message data byte 67 register 07
CAN3 message data byte 6 register 07
CAN3 message data byte 7 register 07
CAN3 message data length code register 07
CAN3 message configuration register 07
CAN3 message ID register 07
C3MDATA0107
C3MDATA007
C3MDATA107
C3MDATA2307
C3MDATA207
C3MDATA307
C3MDATA4507
C3MDATA407
C3MDATA507
C3MDATA6707
C3MDATA607
C3MDATA707
C3MDLC07
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF07
C3MIDL07
√
√
√
C3MIDH07
CAN3 message control register 07
C3MCTRL07
00x00000
000xx000B
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643
CHAPTER 15 CAN CONTROLLER
(57/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED400H
03FED400H
03FED401H
03FED402H
03FED402H
03FED403H
03FED404H
03FED404H
03FED405H
03FED406H
03FED406H
03FED407H
03FED408H
03FED409H
03FED40AH
03FED40CH
03FED40EH
CAN3 message data byte 01 register 08
CAN3 message data byte 0 register 08
CAN3 message data byte 1 register 08
CAN3 message data byte 23 register 08
CAN3 message data byte 2 register 08
CAN3 message data byte 3 register 08
CAN3 message data byte 45 register 08
CAN3 message data byte 4 register 08
CAN3 message data byte 5 register 08
CAN3 message data byte 67 register 08
CAN3 message data byte 6 register 08
CAN3 message data byte 7 register 08
CAN3 message data length code register 08
CAN3 message configuration register 08
CAN3 message ID register 08
C3MDATA0108 R/W
C3MDATA008
C3MDATA108
C3MDATA2308
C3MDATA208
C3MDATA308
C3MDATA4508
C3MDATA408
C3MDATA508
C3MDATA6708
C3MDATA608
C3MDATA708
C3MDLC08
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF08
C3MIDL08
√
√
√
C3MIDH08
CAN3 message control register 08
C3MCTRL08
00x00000
000xx000B
03FED420H
03FED420H
03FED421H
03FED422H
03FED422H
03FED423H
03FED424H
03FED424H
03FED425H
03FED426H
03FED426H
03FED427H
03FED428H
03FED429H
03FED42AH
03FED42CH
03FED42EH
CAN3 message data byte 01 register 09
CAN3 message data byte 0 register 09
CAN3 message data byte 1 register 09
CAN3 message data byte 23 register 09
CAN3 message data byte 2 register 09
CAN3 message data byte 3 register 09
CAN3 message data byte 45 register 09
CAN3 message data byte 4 register 09
CAN3 message data byte 5 register 09
CAN3 message data byte 67 register 09
CAN3 message data byte 6 register 09
CAN3 message data byte 7 register 09
CAN3 message data length code register 09
CAN3 message configuration register 09
CAN3 message ID register 09
C3MDATA0109
C3MDATA009
C3MDATA109
C3MDATA2309
C3MDATA209
C3MDATA309
C3MDATA4509
C3MDATA409
C3MDATA509
C3MDATA6709
C3MDATA609
C3MDATA709
C3MDLC09
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF09
C3MIDL09
√
√
√
C3MIDH09
CAN3 message control register 09
C3MCTRL09
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
644
CHAPTER 15 CAN CONTROLLER
(58/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED440H
03FED440H
03FED441H
03FED442H
03FED442H
03FED443H
03FED444H
03FED444H
03FED445H
03FED446H
03FED446H
03FED447H
03FED448H
03FED449H
03FED44AH
03FED44CH
03FED44EH
CAN3 message data byte 01 register 10
CAN3 message data byte 0 register 10
CAN3 message data byte 1 register 10
CAN3 message data byte 23 register 10
CAN3 message data byte 2 register 10
CAN3 message data byte 3 register 10
CAN3 message data byte 45 register 10
CAN3 message data byte 4 register 10
CAN3 message data byte 5 register 10
CAN3 message data byte 67 register 10
CAN3 message data byte 6 register 10
CAN3 message data byte 7 register 10
CAN3 message data length code register 10
CAN3 message configuration register 10
CAN3 message ID register 10
C3MDATA0110 R/W
C3MDATA010
C3MDATA110
C3MDATA2310
C3MDATA210
C3MDATA310
C3MDATA4510
C3MDATA410
C3MDATA510
C3MDATA6710
C3MDATA610
C3MDATA710
C3MDLC10
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF10
C3MIDL10
√
√
√
C3MIDH10
CAN3 message control register 10
C3MCTRL10
00x00000
000xx000B
03FED460H
03FED460H
03FED461H
03FED462H
03FED462H
03FED463H
03FED464H
03FED464H
03FED465H
03FED466H
03FED466H
03FED467H
03FED468H
03FED469H
03FED46AH
03FED46CH
03FED46EH
CAN3 message data byte 01 register 11
CAN3 message data byte 0 register 11
CAN3 message data byte 1 register 11
CAN3 message data byte 23 register 11
CAN3 message data byte 2 register 11
CAN3 message data byte 3 register 11
CAN3 message data byte 45 register 11
CAN3 message data byte 4 register 11
CAN3 message data byte 5 register 11
CAN3 message data byte 67 register 11
CAN3 message data byte 6 register 11
CAN3 message data byte 7 register 11
CAN3 message data length code register 11
CAN3 message configuration register 11
CAN3 message ID register 11
C3MDATA0111
C3MDATA011
C3MDATA111
C3MDATA2311
C3MDATA211
C3MDATA311
C3MDATA4511
C3MDATA411
C3MDATA511
C3MDATA6711
C3MDATA611
C3MDATA711
C3MDLC11
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF11
C3MIDL11
√
√
√
C3MIDH11
CAN3 message control register 11
C3MCTRL11
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
645
CHAPTER 15 CAN CONTROLLER
(59/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED480H
03FED480H
03FED481H
03FED482H
03FED482H
03FED483H
03FED484H
03FED484H
03FED485H
03FED486H
03FED486H
03FED487H
03FED488H
03FED489H
03FED48AH
03FED48CH
03FED48EH
CAN3 message data byte 01 register 12
CAN3 message data byte 0 register 12
CAN3 message data byte 1 register 12
CAN3 message data byte 23 register 12
CAN3 message data byte 2 register 12
CAN3 message data byte 3 register 12
CAN3 message data byte 45 register 12
CAN3 message data byte 4 register 12
CAN3 message data byte 5 register 12
CAN3 message data byte 67 register 12
CAN3 message data byte 6 register 12
CAN3 message data byte 7 register 12
CAN3 message data length code register 12
CAN3 message configuration register 12
CAN3 message ID register 12
C3MDATA0112 R/W
C3MDATA012
C3MDATA112
C3MDATA2312
C3MDATA212
C3MDATA312
C3MDATA4512
C3MDATA412
C3MDATA512
C3MDATA6712
C3MDATA612
C3MDATA712
C3MDLC12
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF12
C3MIDL12
√
√
√
C3MIDH12
CAN3 message control register 12
C3MCTRL12
00x00000
000xx000B
03FED4A0H
03FED4A0H
03FED4A1H
03FED4A2H
03FED4A2H
03FED4A3H
03FED4A4H
03FED4A4H
03FED4A5H
03FED4A6H
03FED4A6H
03FED4A7H
03FED4A8H
03FED4A9H
03FED4AAH
03FED4ACH
03FED4AEH
CAN3 message data byte 01 register 13
CAN3 message data byte 0 register 13
CAN3 message data byte 1 register 13
CAN3 message data byte 23 register 13
CAN3 message data byte 2 register 13
CAN3 message data byte 3 register 13
CAN3 message data byte 45 register 13
CAN3 message data byte 4 register 13
CAN3 message data byte 5 register 13
CAN3 message data byte 67 register 13
CAN3 message data byte 6 register 13
CAN3 message data byte 7 register 13
CAN3 message data length code register 13
CAN3 message configuration register 13
CAN3 message ID register 13
C3MDATA0113
C3MDATA013
C3MDATA113
C3MDATA2313
C3MDATA213
C3MDATA313
C3MDATA4513
C3MDATA413
C3MDATA513
C3MDATA6713
C3MDATA613
C3MDATA713
C3MDLC13
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF13
C3MIDL13
√
√
√
C3MIDH13
CAN3 message control register 13
C3MCTRL13
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
646
CHAPTER 15 CAN CONTROLLER
(60/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED4C0H
03FED4C0H
03FED4C1H
03FED4C2H
03FED4C2H
03FED4C3H
03FED4C4H
03FED4C4H
03FED4C5H
03FED4C6H
03FED4C6H
03FED4C7H
03FED4C8H
03FED4C9H
03FED4CAH
03FED4CCH
03FED4CEH
CAN3 message data byte 01 register 14
CAN3 message data byte 0 register 14
CAN3 message data byte 1 register 14
CAN3 message data byte 23 register 14
CAN3 message data byte 2 register 14
CAN3 message data byte 3 register 14
CAN3 message data byte 45 register 14
CAN3 message data byte 4 register 14
CAN3 message data byte 5 register 14
CAN3 message data byte 67 register 14
CAN3 message data byte 6 register 14
CAN3 message data byte 7 register 14
CAN3 message data length code register 14
CAN3 message configuration register 14
CAN3 message ID register 14
C3MDATA0114 R/W
C3MDATA014
C3MDATA114
C3MDATA2314
C3MDATA214
C3MDATA314
C3MDATA4514
C3MDATA414
C3MDATA514
C3MDATA6714
C3MDATA614
C3MDATA714
C3MDLC14
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF14
C3MIDL14
√
√
√
C3MIDH14
CAN3 message control register 14
C3MCTRL14
00x00000
000xx000B
03FED4E0H
03FED4E0H
03FED4E1H
03FED4E2H
03FED4E2H
03FED4E3H
03FED4E4H
03FED4E4H
03FED4E5H
03FED4E6H
03FED4E6H
03FED4E7H
03FED4E8H
03FED4E9H
03FED4EAH
03FED4ECH
03FED4EEH
CAN3 message data byte 01 register 15
CAN3 message data byte 0 register 15
CAN3 message data byte 1 register 15
CAN3 message data byte 23 register 15
CAN3 message data byte 2 register 15
CAN3 message data byte 3 register 15
CAN3 message data byte 45 register 15
CAN3 message data byte 4 register 15
CAN3 message data byte 5 register 15
CAN3 message data byte 67 register 15
CAN3 message data byte 6 register 15
CAN3 message data byte 7 register 15
CAN3 message data length code register 15
CAN3 message configuration register 15
CAN3 message ID register 15
C3MDATA0115
C3MDATA015
C3MDATA115
C3MDATA2315
C3MDATA215
C3MDATA315
C3MDATA4515
C3MDATA415
C3MDATA515
C3MDATA6715
C3MDATA615
C3MDATA715
C3MDLC15
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF15
C3MIDL15
√
√
√
C3MIDH15
CAN3 message control register 15
C3MCTRL15
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
647
CHAPTER 15 CAN CONTROLLER
(61/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED500H
CAN3 message data byte 01 register 16
C3MDATA0116 R/W
C3MDATA016
C3MDATA116
C3MDATA2316
C3MDATA216
C3MDATA316
C3MDATA4516
C3MDATA416
C3MDATA516
C3MDATA6716
C3MDATA616
C3MDATA716
C3MDLC16
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FED500H CAN3 message data byte 0 register 16
03FED501H CAN3 message data byte 1 register 16
√
√
03FED502H
CAN3 message data byte 23 register 16
√
√
√
03FED502H CAN3 message data byte 2 register 16
03FED503H CAN3 message data byte 3 register 16
√
√
03FED504H
CAN3 message data byte 45 register 16
03FED504H CAN3 message data byte 4 register 16
03FED505H CAN3 message data byte 5 register 16
√
√
03FED506H
CAN3 message data byte 67 register 16
03FED506H CAN3 message data byte 6 register 16
03FED507H CAN3 message data byte 7 register 16
√
√
√
√
03FED508H
03FED509H
03FED50AH
03FED50CH
03FED50EH
CAN3 message data length code register 16
CAN3 message configuration register 16
CAN3 message ID register 16
C3MCONF16
C3MIDL16
√
√
√
C3MIDH16
CAN3 message control register 16
C3MCTRL16
00x00000
000xx000B
03FED520H
CAN3 message data byte 01 register 17
C3MDATA0117
C3MDATA017
C3MDATA117
C3MDATA2317
C3MDATA217
C3MDATA317
C3MDATA4517
C3MDATA417
C3MDATA517
C3MDATA6717
C3MDATA617
C3MDATA717
C3MDLC17
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FED520H CAN3 message data byte 0 register 17
03FED521H CAN3 message data byte 1 register 17
√
√
03FED522H
CAN3 message data byte 23 register 17
03FED522H CAN3 message data byte 2 register 17
03FED523H CAN3 message data byte 3 register 17
√
√
03FED524H
CAN3 message data byte 45 register 17
03FED524H CAN3 message data byte 4 register 17
03FED525H CAN3 message data byte 5 register 17
√
√
03FED526H
CAN3 message data byte 67 register 17
03FED526H CAN3 message data byte 6 register 17
03FED527H CAN3 message data byte 7 register 17
√
√
√
√
03FED528H
03FED529H
03FED52AH
03FED52CH
03FED52EH
CAN3 message data length code register 17
CAN3 message configuration register 17
CAN3 message ID register 17
C3MCONF17
C3MIDL17
√
√
√
C3MIDH17
CAN3 message control register 17
C3MCTRL17
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
648
CHAPTER 15 CAN CONTROLLER
(62/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED540H
CAN3 message data byte 01 register 18
C3MDATA0118 R/W
C3MDATA018
C3MDATA118
C3MDATA2318
C3MDATA218
C3MDATA318
C3MDATA4518
C3MDATA418
C3MDATA518
C3MDATA6718
C3MDATA618
C3MDATA718
C3MDLC18
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FED540H CAN3 message data byte 0 register 18
03FED541H CAN3 message data byte 1 register 18
√
√
03FED542H
CAN3 message data byte 23 register 18
√
√
√
03FED542H CAN3 message data byte 2 register 18
03FED543H CAN3 message data byte 3 register 18
√
√
03FED544H
CAN3 message data byte 45 register 18
03FED544H CAN3 message data byte 4 register 18
03FED545H CAN3 message data byte 5 register 18
√
√
03FED546H
CAN3 message data byte 67 register 18
03FED546H CAN3 message data byte 6 register 18
03FED547H CAN3 message data byte 7 register 18
√
√
√
√
03FED548H
03FED549H
03FED54AH
03FED54CH
03FED54EH
CAN3 message data length code register 18
CAN3 message configuration register 18
CAN3 message ID register 18
C3MCONF18
C3MIDL18
√
√
√
C3MIDH18
CAN3 message control register 18
C3MCTRL18
00x00000
000xx000B
03FED560H
CAN3 message data byte 01 register 19
C3MDATA0119
C3MDATA019
C3MDATA119
C3MDATA2319
C3MDATA219
C3MDATA319
C3MDATA4519
C3MDATA419
C3MDATA519
C3MDATA6719
C3MDATA619
C3MDATA719
C3MDLC19
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
03FED560H CAN3 message data byte 0 register 19
03FED561H CAN3 message data byte 1 register 19
√
√
03FED562H
CAN3 message data byte 23 register 19
03FED562H CAN3 message data byte 2 register 19
03FED563H CAN3 message data byte 3 register 19
√
√
03FED564H
CAN3 message data byte 45 register 19
03FED564H CAN3 message data byte 4 register 19
03FED565H CAN3 message data byte 5 register 19
√
√
03FED566H
CAN3 message data byte 67 register 19
03FED566H CAN3 message data byte 6 register 19
03FED567H CAN3 message data byte 7 register 19
√
√
√
√
03FED568H
03FED569H
03FED56AH
03FED56CH
03FED56EH
CAN3 message data length code register 19
CAN3 message configuration register 19
CAN3 message ID register 19
C3MCONF19
C3MIDL19
√
√
√
C3MIDH19
CAN3 message control register 19
C3MCTRL19
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
649
CHAPTER 15 CAN CONTROLLER
(63/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED580H
03FED580H
03FED581H
03FED582H
03FED582H
03FED583H
03FED584H
03FED584H
03FED585H
03FED586H
03FED586H
03FED587H
03FED588H
03FED589H
03FED58AH
03FED58CH
03FED58EH
CAN3 message data byte 01 register 20
CAN3 message data byte 0 register 20
CAN3 message data byte 1 register 20
CAN3 message data byte 23 register 20
CAN3 message data byte 2 register 20
CAN3 message data byte 3 register 20
CAN3 message data byte 45 register 20
CAN3 message data byte 4 register 20
CAN3 message data byte 5 register 20
CAN3 message data byte 67 register 20
CAN3 message data byte 6 register 20
CAN3 message data byte 7 register 20
CAN3 message data length code register 20
CAN3 message configuration register 20
CAN3 message ID register 20
C3MDATA0120 R/W
C3MDATA020
C3MDATA120
C3MDATA2320
C3MDATA220
C3MDATA320
C3MDATA4520
C3MDATA420
C3MDATA520
C3MDATA6720
C3MDATA620
C3MDATA720
C3MDLC20
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF20
C3MIDL20
√
√
√
C3MIDH20
CAN3 message control register 20
C3MCTRL20
00x00000
000xx000B
03FED5A0H
03FED5A0H
03FED5A1H
03FED5A2H
03FED5A2H
03FED5A3H
03FED5A4H
03FED5A4H
03FED5A5H
03FED5A6H
03FED5A6H
03FED5A7H
03FED5A8H
03FED5A9H
03FED5AAH
03FED5ACH
03FED5AEH
CAN3 message data byte 01 register 21
CAN3 message data byte 0 register 21
CAN3 message data byte 1 register 21
CAN3 message data byte 23 register 21
CAN3 message data byte 2 register 21
CAN3 message data byte 3 register 21
CAN3 message data byte 45 register 21
CAN3 message data byte 4 register 21
CAN3 message data byte 5 register 21
CAN3 message data byte 67 register 21
CAN3 message data byte 6 register 21
CAN3 message data byte 7 register 21
CAN3 message data length code register 21
CAN3 message configuration register 21
CAN3 message ID register 21
C3MDATA0121
C3MDATA021
C3MDATA121
C3MDATA2321
C3MDATA221
C3MDATA321
C3MDATA4521
C3MDATA421
C3MDATA521
C3MDATA6721
C3MDATA621
C3MDATA721
C3MDLC21
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF21
C3MIDL21
√
√
√
C3MIDH21
CAN3 message control register 21
C3MCTRL21
00x00000
000xx000B
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650
CHAPTER 15 CAN CONTROLLER
(64/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED5C0H
03FED5C0H
03FED5C1H
03FED5C2H
03FED5C2H
03FED5C3H
03FED5C4H
03FED5C4H
03FED5C5H
03FED5C6H
03FED5C6H
03FED5C7H
03FED5C8H
03FED5C9H
03FED5CAH
03FED5CCH
03FED5CEH
CAN3 message data byte 01 register 22
CAN3 message data byte 0 register 22
CAN3 message data byte 1 register 22
CAN3 message data byte 23 register 22
CAN3 message data byte 2 register 22
CAN3 message data byte 3 register 22
CAN3 message data byte 45 register 22
CAN3 message data byte 4 register 22
CAN3 message data byte 5 register 22
CAN3 message data byte 67 register 22
CAN3 message data byte 6 register 22
CAN3 message data byte 7 register 22
CAN3 message data length code register 22
CAN3 message configuration register 22
CAN3 message ID register 22
C3MDATA0122 R/W
C3MDATA022
C3MDATA122
C3MDATA2322
C3MDATA222
C3MDATA322
C3MDATA4522
C3MDATA422
C3MDATA522
C3MDATA6722
C3MDATA622
C3MDATA722
C3MDLC22
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF22
C3MIDL22
√
√
√
C3MIDH22
CAN3 message control register 22
C3MCTRL22
00x00000
000xx000B
03FED5E0H
03FED5E0H
03FED5E1H
03FED5E2H
03FED5E2H
03FED5E3H
03FED5E4H
03FED5E4H
03FED5E5H
03FED5E6H
03FED5E6H
03FED5E7H
03FED5E8H
03FED5E9H
03FED5EAH
03FED5ECH
03FED5EEH
CAN3 message data byte 01 register 23
CAN3 message data byte 0 register 23
CAN3 message data byte 1 register 23
CAN3 message data byte 23 register 23
CAN3 message data byte 2 register 23
CAN3 message data byte 3 register 23
CAN3 message data byte 45 register 23
CAN3 message data byte 4 register 23
CAN3 message data byte 5 register 23
CAN3 message data byte 67 register 23
CAN3 message data byte 6 register 23
CAN3 message data byte 7 register 23
CAN3 message data length code register 23
CAN3 message configuration register 23
CAN3 message ID register 23
C3MDATA0123
C3MDATA023
C3MDATA123
C3MDATA2323
C3MDATA223
C3MDATA323
C3MDATA4523
C3MDATA423
C3MDATA523
C3MDATA6723
C3MDATA623
C3MDATA723
C3MDLC23
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF23
C3MIDL23
√
√
√
C3MIDH23
CAN3 message control register 23
C3MCTRL23
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
651
CHAPTER 15 CAN CONTROLLER
(65/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED600H
03FED600H
03FED601H
03FED602H
03FED602H
03FED603H
03FED604H
03FED604H
03FED605H
03FED606H
03FED606H
03FED607H
03FED608H
03FED609H
03FED60AH
03FED60CH
03FED60EH
CAN3 message data byte 01 register 24
CAN3 message data byte 0 register 24
CAN3 message data byte 1 register 24
CAN3 message data byte 23 register 24
CAN3 message data byte 2 register 24
CAN3 message data byte 3 register 24
CAN3 message data byte 45 register 24
CAN3 message data byte 4 register 24
CAN3 message data byte 5 register 24
CAN3 message data byte 67 register 24
CAN3 message data byte 6 register 24
CAN3 message data byte 7 register 24
CAN3 message data length code register 24
CAN3 message configuration register 24
CAN3 message ID register 24
C3MDATA0124 R/W
C3MDATA024
C3MDATA124
C3MDATA2324
C3MDATA224
C3MDATA324
C3MDATA4524
C3MDATA424
C3MDATA524
C3MDATA6724
C3MDATA624
C3MDATA724
C3MDLC24
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF24
C3MIDL24
√
√
√
C3MIDH24
CAN3 message control register 24
C3MCTRL24
00x00000
000xx000B
03FED620H
03FED620H
03FED621H
03FED622H
03FED622H
03FED623H
03FED624H
03FED624H
03FED625H
03FED626H
03FED626H
03FED627H
03FED628H
03FED629H
03FED62AH
03FED62CH
03FED62EH
CAN3 message data byte 01 register 25
CAN3 message data byte 0 register 25
CAN3 message data byte 1 register 25
CAN3 message data byte 23 register 25
CAN3 message data byte 2 register 25
CAN3 message data byte 3 register 25
CAN3 message data byte 45 register 25
CAN3 message data byte 4 register 25
CAN3 message data byte 5 register 25
CAN3 message data byte 67 register 25
CAN3 message data byte 6 register 25
CAN3 message data byte 7 register 25
CAN3 message data length code register 25
CAN3 message configuration register 25
CAN3 message ID register 25
C3MDATA0125
C3MDATA025
C3MDATA125
C3MDATA2325
C3MDATA225
C3MDATA325
C3MDATA4525
C3MDATA425
C3MDATA525
C3MDATA6725
C3MDATA625
C3MDATA725
C3MDLC25
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF25
C3MIDL25
√
√
√
C3MIDH25
CAN3 message control register 25
C3MCTRL25
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
652
CHAPTER 15 CAN CONTROLLER
(66/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED640H
03FED640H
03FED641H
03FED642H
03FED642H
03FED643H
03FED644H
03FED644H
03FED645H
03FED646H
03FED646H
03FED647H
03FED648H
03FED649H
03FED64AH
03FED64CH
03FED64EH
CAN3 message data byte 01 register 26
CAN3 message data byte 0 register 26
CAN3 message data byte 1 register 26
CAN3 message data byte 23 register 26
CAN3 message data byte 2 register 26
CAN3 message data byte 3 register 26
CAN3 message data byte 45 register 26
CAN3 message data byte 4 register 26
CAN3 message data byte 5 register 26
CAN3 message data byte 67 register 26
CAN3 message data byte 6 register 26
CAN3 message data byte 7 register 26
CAN3 message data length code register 26
CAN3 message configuration register 26
CAN3 message ID register 26
C3MDATA0126 R/W
C3MDATA026
C3MDATA126
C3MDATA2326
C3MDATA226
C3MDATA326
C3MDATA4526
C3MDATA426
C3MDATA526
C3MDATA6726
C3MDATA626
C3MDATA726
C3MDLC26
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF26
C3MIDL26
√
√
√
C3MIDH26
CAN3 message control register 26
C3MCTRL26
00x00000
000xx000B
03FED660H
03FED660H
03FED661H
03FED662H
03FED662H
03FED663H
03FED664H
03FED664H
03FED665H
03FED666H
03FED666H
03FED667H
03FED668H
03FED669H
03FED66AH
03FED66CH
03FED66EH
CAN3 message data byte 01 register 27
CAN3 message data byte 0 register 27
CAN3 message data byte 1 register 27
CAN3 message data byte 23 register 27
CAN3 message data byte 2 register 27
CAN3 message data byte 3 register 27
CAN3 message data byte 45 register 27
CAN3 message data byte 4 register 27
CAN3 message data byte 5 register 27
CAN3 message data byte 67 register 27
CAN3 message data byte 6 register 27
CAN3 message data byte 7 register 27
CAN3 message data length code register 27
CAN3 message configuration register 27
CAN3 message ID register 27
C3MDATA0127
C3MDATA027
C3MDATA127
C3MDATA2327
C3MDATA227
C3MDATA327
C3MDATA4527
C3MDATA427
C3MDATA527
C3MDATA6727
C3MDATA627
C3MDATA727
C3MDLC27
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF27
C3MIDL27
√
√
√
C3MIDH27
CAN3 message control register 27
C3MCTRL27
00x00000
000xx000B
User’s Manual U17830EE1V0UM00
653
CHAPTER 15 CAN CONTROLLER
(67/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED680H
03FED680H
03FED681H
03FED682H
03FED682H
03FED683H
03FED684H
03FED684H
03FED685H
03FED686H
03FED686H
03FED687H
03FED688H
03FED689H
03FED68AH
03FED68CH
03FED68EH
CAN3 message data byte 01 register 28
CAN3 message data byte 0 register 28
CAN3 message data byte 1 register 28
CAN3 message data byte 23 register 28
CAN3 message data byte 2 register 28
CAN3 message data byte 3 register 28
CAN3 message data byte 45 register 28
CAN3 message data byte 4 register 28
CAN3 message data byte 5 register 28
CAN3 message data byte 67 register 28
CAN3 message data byte 6 register 28
CAN3 message data byte 7 register 28
CAN3 message data length code register 28
CAN3 message configuration register 28
CAN3 message ID register 28
C3MDATA0128 R/W
C3MDATA028
C3MDATA128
C3MDATA2328
C3MDATA228
C3MDATA328
C3MDATA4528
C3MDATA428
C3MDATA528
C3MDATA6728
C3MDATA628
C3MDATA728
C3MDLC28
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF28
C3MIDL28
√
√
√
C3MIDH28
CAN3 message control register 28
C3MCTRL28
00x00000
000xx000B
03FED6A0H
03FED6A0H
03FED6A1H
03FED6A2H
03FED6A2H
03FED6A3H
03FED6A4H
03FED6A4H
03FED6A5H
03FED6A6H
03FED6A6H
03FED6A7H
03FED6A8H
03FED6A9H
03FED6AAH
03FED6ACH
03FED6AEH
CAN3 message data byte 01 register 29
CAN3 message data byte 0 register 29
CAN3 message data byte 1 register 29
CAN3 message data byte 23 register 29
CAN3 message data byte 2 register 29
CAN3 message data byte 3 register 29
CAN3 message data byte 45 register 29
CAN3 message data byte 4 register 29
CAN3 message data byte 5 register 29
CAN3 message data byte 67 register 29
CAN3 message data byte 6 register 29
CAN3 message data byte 7 register 29
CAN3 message data length code register 29
CAN3 message configuration register 29
CAN3 message ID register 29
C3MDATA0129
C3MDATA029
C3MDATA129
C3MDATA2329
C3MDATA229
C3MDATA329
C3MDATA4529
C3MDATA429
C3MDATA529
C3MDATA6729
C3MDATA629
C3MDATA729
C3MDLC29
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF29
C3MIDL29
√
√
√
C3MIDH29
CAN3 message control register 29
C3MCTRL29
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
(68/68)
Address
Register Name
Symbol
R/W Bit Manipulation Units After Reset
1
8
16
03FED6C0H
03FED6C0H
03FED6C1H
03FED6C2H
03FED6C2H
03FED6C3H
03FED6C4H
03FED6C4H
03FED6C5H
03FED6C6H
03FED6C6H
03FED6C7H
03FED6C8H
03FED6C9H
03FED6CAH
03FED6CCH
03FED6CEH
CAN3 message data byte 01 register 30
CAN3 message data byte 0 register 30
CAN3 message data byte 1 register 30
CAN3 message data byte 23 register 30
CAN3 message data byte 2 register 30
CAN3 message data byte 3 register 30
CAN3 message data byte 45 register 30
CAN3 message data byte 4 register 30
CAN3 message data byte 5 register 30
CAN3 message data byte 67 register 30
CAN3 message data byte 6 register 30
CAN3 message data byte 7 register 30
CAN3 message data length code register 30
CAN3 message configuration register 30
CAN3 message ID register 30
C3MDATA0130 R/W
C3MDATA030
C3MDATA130
C3MDATA2330
C3MDATA230
C3MDATA330
C3MDATA4530
C3MDATA430
C3MDATA530
C3MDATA6730
C3MDATA630
C3MDATA730
C3MDLC30
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxxB
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
√
√
√
C3MCONF30
C3MIDL30
√
√
√
C3MIDH30
CAN3 message control register 30
C3MCTRL30
00x00000
000xx000B
03FED6E0H
03FED6E0H
03FED6E1H
03FED6E2H
03FED6E2H
03FED6E3H
03FED6E4H
03FED6E4H
03FED6E5H
03FED6E6H
03FED6E6H
03FED6E7H
03FED6E8H
03FED6E9H
03FED6EAH
03FED6ECH
03FED6EEH
CAN3 message data byte 01 register 31
CAN3 message data byte 0 register 31
CAN3 message data byte 1 register 31
CAN3 message data byte 23 register 31
CAN3 message data byte 2 register 31
CAN3 message data byte 3 register 31
CAN3 message data byte 45 register 31
CAN3 message data byte 4 register 31
CAN3 message data byte 5 register 31
CAN3 message data byte 67 register 31
CAN3 message data byte 6 register 31
CAN3 message data byte 7 register 31
CAN3 message data length code register 31
CAN3 message configuration register 31
CAN3 message ID register 31
C3MDATA0131
C3MDATA031
C3MDATA131
C3MDATA2331
C3MDATA231
C3MDATA331
C3MDATA4531
C3MDATA431
C3MDATA531
C3MDATA6731
C3MDATA631
C3MDATA731
C3MDLC31
√
√
√
√
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0000xxxx
Undefined
Undefined
Undefined
√
√
√
√
√
√
√
√
√
√
C3MCONF31
C3MIDL31
√
√
√
C3MIDH31
CAN3 message control register 31
C3MCTRL31
00x00000
000xx000B
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CHAPTER 15 CAN CONTROLLER
15.5.3 Register bit configuration
Table 15-17. CAN Global Register Bit Configuration
Address
03FExx00H
03FExx01H
03FExx00H
03FExx01H
03FExx02H
03FExx06H
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
0
Bit 0/8
CnGMCTRL (W)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clear GOM
0
0
0
Set EFSD Set GOM
CnGMCTRL (R)
0
0
0
0
0
EFSD
GOM
0
MBON
0
CCP1
0
CnGMCS
0
0
CCP3
0
CCP2
0
CCP0
CnGMABT (W)
Clear
ABTTRG
03FExx07H
0
0
0
0
0
0
Set
Set
ABTCLR ABTTRG
03FExx06H
03FExx07H
03FExx08H
CnGMABT (R)
CnGMABTD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ABTCLR ABTTRG
0
0
ABTD3
ABTD2
ABTD1
ABTD0
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 15 CAN CONTROLLER
Table 15-18. CAN Module Register Bit Configuration
(1/2)
Address
03FExx40H
03FExx41H
03FExx42H
03FExx43H
03FExx44H
03FExx45H
03FExx46H
03FExx47H
03FExx48H
03FExx49H
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
CnMASK1L
CM1ID[7:0]
CM1ID[15:8]
CM1ID[23:16]
CnMASK1H
CnMASK2L
CnMASK2H
CnMASK3L
0
0
0
0
0
0
0
0
0
0
CM1ID[28:24]
CM2ID[28:24]
CM3ID[28:24]
CM2ID[7:0]
CM2ID[15:8]
CM2ID[23:16]
CM3ID[7:0]
CM3ID[15:8]
CM3ID[23:16]
03FExx4AH CnMASK3H
03FExx4BH
03FExx4CH CnMASK4L
03FExx4DH
CM4ID[7:0]
CM4ID[15:8]
CM4ID[23:16]
03FExx4EH CnMASK4H
03FExx4FH
0
0
0
CM4ID[28:24]
Clear
03FExx50H
03FExx51H
03FExx50H
CnCTRL (W)
Clear AL
Clear
Clear
Clear
Clear
Clear
VALID
PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0
Set Set Set Set Set
PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0
Set
Set
AL
0
CCERC
CnCTRL (R)
CCERC
AL
VALID
PS
PS
OP
OP
OP
MODE1
MODE0
MODE2
MODE1
MODE0
03FExx51H
03FExx52H
03FExx52H
03FExx53H
03FExx54H
03FExx55H
03FExx56H
03FExx57H
03FExx56H
03FExx57H
03FExx58H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSTAT
0
TSTAT
0
CnLEC (W)
CnLEC (R)
CnINFO
0
0
0
0
LEC2
TECS0
LEC1
RECS1
LEC0
RECS0
BOFF
TECS1
CnERC
TEC[7:0]
REC[6:0]
REPS
CnIE (W)
CnIE (R)
0
0
0
0
0
0
0
0
0
0
Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0
Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0
CIE5
0
CIE4
0
CIE3
0
CIE2
0
CIE1
0
CIE0
0
CnINTS (W)
Clear
Clear
Clear
Clear
Clear
Clear
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
03FExx59H
03FExx58H
03FExx59H
0
0
0
0
0
0
0
CINTS5
0
0
CINTS4
0
0
CINTS3
0
0
CINTS2
0
0
CINTS1
0
0
CINTS0
0
CnINTS (R)
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 15 CAN CONTROLLER
(2/2)
Address
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
0
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
03FExx5AH CnBRP
03FExx5CH CnBTR
03FExx5DH
TQPRS[7:0]
0
0
0
0
0
0
TSEG1[3:0]
SJW[1:0]
0
TSEG2[2:0]
03FExx5EH CnLIPT
LIPT[7:0]
03FExx60H
CnRGPT (W)
0
0
0
0
0
0
Clear
ROVF
03FExx61H
03FExx60H
03FExx61H
03FExx62H
03FExx64H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CnRGPT (R)
RHPM
ROVF
RGPT[7:0]
LOPT[7:0]
CnLOPT
CnTGPT (W)
0
0
0
0
0
0
0
Clear
TOVF
03FExx65H
03FExx64H
03FExx65H
03FExx66H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CnTGPT (R)
CnTS (W)
THPM
TOVF
TGPT[7:0]
0
0
0
0
0
0
0
0
0
0
Clear
Clear
Clear
TSLOCK
TSSEL
TSEN
03FExx67H
Set
Set
Set
TSLOCK
TSSEL
TSEN
03FExx66H
03FExx67H
CnTS (R)
0
0
0
0
0
0
0
0
0
0
TSLOCK
0
TSSEL
0
TSEN
0
03FExx68H
to
−
Access prohibited (reserved for future use)
03FExxFFH
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 15 CAN CONTROLLER
Table 15-19. Message Buffer Register Bit Configuration
Address
03FExxx0H
03FExxx1H
03FExxx0H
03FExxx1H
03FExxx2H
03FExxx3H
03FExxx2H
03FExxx3H
03FExxx4H
03FExxx5H
03FExxx4H
03FExxx5H
03FExxx6H
03FExxx7H
03FExxx6H
03FExxx7H
03FExxx8H
03FExxx9H
Symbol
Bit 7/15
Bit 6/14
Bit 5/13
Bit 4/12
Bit 3/11
Bit 2/10
Bit 1/9
Bit 0/8
CnMDATA01m
Message data (byte 0)
Message data (byte 1)
Message data (byte 0)
Message data (byte 1)
Message data (byte 2)
Message data (byte 3)
Message data (byte 2)
Message data (byte 3)
Message data (byte 4)
Message data (byte 5)
Message data (byte 4)
Message data (byte 5)
Message data (byte 6)
Message data (byte 7)
Message data (byte 6)
Message data (byte 7)
CnMDATA0m
CnMDATA1m
CnMDATA23m
CnMDATA2m
CnMDATA3m
CnMDATA45m
CnMDATA4m
CnMDATA5m
CnMDATA67m
CnMDATA6m
CnMDATA7m
CnMDLCm
0
MDLC3
MT0
MDLC2
0
MDLC1
0
MDLC0
MA0
ID0
CnMCONFm
OWS
ID7
RTR
ID6
ID14
ID22
0
MT2
ID5
ID13
ID21
0
MT1
ID4
03FExxxAH CnMIDLm
03FExxxBH
ID3
ID2
ID1
ID15
ID23
IDE
0
ID12
ID20
ID28
ID11
ID19
ID27
ID10
ID18
ID26
ID9
ID8
03FExxxCH CnMIDHm
03FExxxDH
ID17
ID25
ID16
ID24
03FExxxEH CnMCTRLm (W)
0
0
Clear
MOW
Clear
IE
Clear
DN
Clear TRQ Clear RDY
03FExxxFH
0
0
0
0
0
0
0
0
0
MOW
0
Set IE
0
DN
0
Set TRQ
TRQ
0
Set RDY
RDY
0
03FExxxEH CnMCTRLm (R)
03FExxxFH
IE
0
MUC
03FExxx0
to
−
Access prohibited (reserved for future use)
03FExxxFH
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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CHAPTER 15 CAN CONTROLLER
15.6 Control Registers
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
(1) CAN global control register (CnGMCTRL)
The CnGMCTRL register is used to control the operation of the CAN module.
(1/2)
After reset: 0000H
R/W
Address: C0GMCTRL 03FFEC000H, C1GMCTRL 03FEC600H
C2GMCTRL 03FECC00H, C3GMCTRL 03FED200H
(a) Read
15
14
0
13
0
12
0
11
0
10
0
9
0
8
0
CnGMCTRL
MBON
7
0
6
5
4
3
2
1
0
0
0
0
0
0
EFSD
GOM
(b) Write
15
0
14
0
13
0
12
0
11
0
10
0
9
8
CnGMCTRL
Set
Set
EFSD
GOM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Clear
GOM
(a) Read
MBON
0
Bit enabling access to message buffer register, transmit/receive history registers
Write access and read access to the message buffer register and the transmit/receive history list registers is
disabled.
1
Write access and read access to the message buffer register and the transmit/receive history list registers is
enabled.
Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers
(CnMDATA0m,
CnMDATA23m,
CnMDATA1m,
CnMDATA4m,
CnMDATA01m,
CnMDATA5m,
CnMDATA2m,
CnMDATA45m,
CnMDATA3m,
CnMDATA6m,
CnMDATA7m, CnMDATA67m, CnMDLCm, CnMCONFm, CnMIDLm, CnMIDHm, and
CnMCTRLm), or registers related to transmit history or receive history (CnLOPT,
CnTGPT, CnLIPT, and CnRGPT) is disabled.
2. This bit is read-only. Even if 1 is written to MBON while it is 0, the value of MBON
does not change, and access to the message buffer registers, or registers related to
transmit history or receive history remains disabled.
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CHAPTER 15 CAN CONTROLLER
(2/2)
EFSD
Bit enabling forced shut down
0
1
Forced shut down by GOM = 0 disabled.
Forced shut down by GOM = 0 enabled.
Caution To request forced shut down, the GOM bit must be cleared to 0 immediately after the
EFSD bit has been set to 1. If access to another register (including reading the
CnGMCTRL register) is executed without clearing the GOM bit immediately after the
EFSD bit has been set to 1, the EFSD bit is forcibly cleared to 0, and the forced shut
down request is invalid.
GOM
Global operation mode bit
0
1
CAN module is disabled from operating.
CAN module is enabled to operate.
Caution The GOM bit is cleared only in the initialization mode.
(b) Write
Set EFSD
EFSD bit setting
0
1
No change in EFSD bit.
EFSD bit set to 1.
Set GOM
Clear GOM
GOM bit setting
0
1
1
0
GOM bit cleared to 0.
GOM bit set to 1.
Other than above
No change in GOM bit.
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CHAPTER 15 CAN CONTROLLER
(2) CAN global clock selection register (CnGMCS)
The CnGMCS register is used to select the CAN module system clock.
After reset: 0FH
R/W
Address: C0GMCS 03FEC002H, C1GMCS 03FEC602H
C2GMCS 03FECC02H, C3GMCS 03FED202H
7
0
6
0
5
0
4
0
3
2
1
0
CnGMCS
CCP3
CCP2
CCP1
CCP0
CCP3
CCP2
CCP1
CCP1
CAN module system clock (fCANMOD)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fCAN/1
fCAN/2
fCAN/3
fCAN/4
fCAN/5
fCAN/6
fCAN/7
fCAN/8
fCAN/9
fCAN/10
fCAN/11
fCAN/12
fCAN/13
fCAN/14
fCAN/15
fCAN/16 (Default value)
Remark fCAN = Clock supplied to CAN = fXX
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CHAPTER 15 CAN CONTROLLER
(3) CAN global automatic block transmission control register (CnGMABT)
The CnGMABT register is used to control the automatic block transmission (ABT) operation.
(1/2)
After reset: 0000H
R/W
Address: C0GMABT 03FEC006H, C1GMABT 03FEC606H
C2GMABT 03FECC06H, C3GMABT 03FED206H
(a) Read
15
0
14
0
13
0
12
0
11
0
10
0
9
8
CnGMABT
0
1
0
0
7
6
5
4
3
2
0
0
0
0
0
0
ABTCLR
ABTTRG
(a) Write
15
0
14
0
13
0
12
0
11
0
10
0
9
8
CnGMABT
Set
Set
ABTCLR
ABTTRG
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Clear
ABTTRG
Caution Before changing the normal operation mode with ABT to the initialization mode, be sure
to set the CnGMABT register to the default value (00H).
(a) Read
ABTCLR
Automatic block transmission engine clear status bit
Clearing the automatic transmission engine is completed.
The automatic transmission engine is being cleared.
0
1
Remarks 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0.
The operation is not guaranteed if the ABTCLR bit is set to 1 while the ABTTRG bit is set to
1.
2. When the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the
ABTCLR bit is automatically cleared to 0 as soon as the requested clearing processing is
complete.
ABTTRG
Automatic block transmission status bit
Automatic block transmission is stopped.
Automatic block transmission is under execution.
0
1
Caution Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the
initialization mode, the operation is not guaranteed after the CAN module has entered the
normal operation mode with ABT.
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CHAPTER 15 CAN CONTROLLER
(2/2)
(b) Write
Set ABTCLR
Automatic block transmission engine clear request bit
0
1
The automatic block transmission engine is in idle state or under operation.
Request to clear the automatic block transmission engine. After the automatic block transmission
engine has been cleared, automatic block transmission is started from message buffer 0 by setting
the ABTTRG bit to 1.
Set ABTTRG Clear ABTTRG
Automatic block transmission start bit
Request to stop automatic block transmission.
0
1
0
1
Request to start automatic block transmission.
No change in ABTTRG bit.
Other than above
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CHAPTER 15 CAN CONTROLLER
(4) CAN global automatic block transmission delay register (CnGMABTD)
The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT
is to be transmitted in the normal operation mode with ABT.
After reset: 00H
CnGMABTD
R/W
Address: C0GMABTD 03FEC008H, C1GMABTD 03FEC608H
C2GMABTD 03FECC08H, C3GMABTD 03FED208H
7
0
6
0
5
0
4
0
3
2
1
0
ABTD3
ABTD2
ABTD1
ABTD0
Data frame interval during automatic block transmission
(Unit: Data bit time (DBT))
ABTD3
ABTD2
ABTD1
ABTD0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0 DBT (default value)
25 DBT
26 DBT
27 DBT
28 DBT
29 DBT
210 DBT
211 DBT
212 DBT
Other than above
Setting prohibited
Cautions 1. Do not change the contents of the CnGMABTD register while the ABTTRG bit is set to
1.
2. The timing at which the ABT message is actually transmitted onto the CAN bus differs
depending on the status of transmission from the other station or how a request to
transmit a message other than an ABT message (message buffers 8 to 31) is made.
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CHAPTER 15 CAN CONTROLLER
(5) CAN module mask control register (CnMASKaL, CnMASKaH) (a = 1, 2, 3, or 4)
The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages by
masking part of the identifier (ID) of a message and invalidating the ID of the masked part.
(1/2)
• CANn module mask 1 register (CnMASK1L, CnMASK1H)
After reset: Undefined
R/W
Address: C0MASK1L 03FEC040H, C1MASK1L 03FEC640H
C2MASK1L 03FECC40H, C3MASK1L 03FED240H
C0MASK1H 03FEC042H, C1MASK1H 03FEC642H
C2MASK1H 03FECC42H, C3MASK1H 03FED242H
15
14
13
12
CMID12
4
11
CMID11
3
10
CMID10
2
9
CMID9
1
8
CMID8
0
CnMASK1L
CnMASK1H
CMID15
CMID14
CMID13
7
6
5
CMID7
CMID6
CMID5
CMID4
12
CMID3
11
CMID2
10
CMID1
9
CMID0
8
15
14
13
0
7
0
6
0
5
CMID28
4
CMID27
3
CMID26
2
CMID25
1
CMID24
0
CMID23
CMID22
CMID21
CMID20
CMID19
CMID18
CMID17
CMID16
• CANn module mask 2 register (CnMASK2L, CnMASK2H)
After reset: Undefined
R/W
Address: C0MASK2L 03FEC044H, C1MASK2L 03FEC644H
C2MASK2L 03FECC44H, C3MASK2L 03FED244H
C0MASK2H 03FEC046H, C1MASK2H 03FEC646H
C2MASK2H 03FECC46H, C3MASK2H 03FED246H
15
14
13
12
CMID12
4
11
CMID11
3
10
CMID10
2
9
CMID9
1
8
CMID8
0
CnMASK2L
CnMASK2H
CMID15
CMID14
CMID13
7
6
5
CMID7
CMID6
CMID5
CMID4
12
CMID3
11
CMID2
10
CMID1
9
CMID0
8
15
14
13
0
7
0
6
0
5
CMID28
4
CMID27
3
CMID26
2
CMID25
1
CMID24
0
CMID23
CMID22
CMID21
CMID20
CMID19
CMID18
CMID17
CMID16
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(2/2)
• CANn module mask 3 register (CnMASK3L, CnMASK3H)
After reset: Undefined
R/W
Address: C0MASK3L 03FEC048H, C1MASK3L 03FEC648H
C2MASK3L 03FECC48H, C3MASK3L 03FED248H
C0MASK3H 03FEC04AH, C1MASK3H 03FEC64AH
C2MASK3H 03FECC4AH, C3MASK3H 03FED24AH
15
14
13
12
CMID12
4
11
CMID11
3
10
CMID10
2
9
CMID9
1
8
CMID8
0
CnMASK3L
CnMASK3H
CMID15
CMID14
CMID13
7
6
5
CMID7
CMID6
CMID5
CMID4
12
CMID3
11
CMID2
10
CMID1
9
CMID0
8
15
14
13
0
7
0
6
0
5
CMID28
4
CMID27
3
CMID26
2
CMID25
1
CMID24
0
CMID23
CMID22
CMID21
CMID20
CMID19
CMID18
CMID17
CMID16
• CANn module mask 4 register (CnMASK4L, CnMASK4H)
After reset: Undefined
R/W
Address: C0MASK4L 03FEC04CH, C1MASK4L 03FEC64CH
C2MASK4L 03FECC4CH, C3MASK4L 03FED24CH
C0MASK4H 03FEC04EH, C1MASK4H 03FEC64EH
C2MASK4H 03FECC4EH, C3MASK4H 03FED24EH
15
14
13
12
CMID12
4
11
CMID11
3
10
CMID10
2
9
CMID9
1
8
CMID8
0
CnMASK4L
CnMASK4H
CMID15
CMID14
CMID13
7
6
5
CMID7
CMID6
CMID5
CMID4
12
CMID3
11
CMID2
10
CMID1
9
CMID0
8
15
14
13
0
7
0
6
0
5
CMID28
4
CMID27
3
CMID26
2
CMID25
1
CMID24
0
CMID23
CMID22
CMID21
CMID20
CMID19
CMID18
CMID17
CMID16
CMID28 to CMID0
0
Mask pattern setting of ID bit
The ID bits of the message buffer set by the CMID28 to CMID0 bits are compared with the ID
bits of the received message frame.
1
The ID bits of the message buffer set by the CMID28 to CMID0 bits are not compared with the
ID bits of the received message frame (they are masked).
Remark Masking is always defined by an ID length of 29 bits. If a mask is assigned to a message with a
standard ID, CMID17 to CMID0 are ignored. Therefore, only CMID28 to CMID18 of the received
ID are masked. The same mask can be used for both the standard and extended IDs.
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(6) CAN module control register (CnCTRL)
The CnCTRL register is used to control the operation mode of the CAN module.
(1/4)
After reset: 0000H
R/W
Address: C0CTRL 03FEC050H, C1CTRL 03FEC650H
C2CTRL 03FECC50H, C3CTRL 03FED250H
(a) Read
15
0
14
0
13
12
0
11
0
10
0
9
RSTAT
1
8
TSTAT
0
CnCTRL
0
5
7
6
4
3
2
CCERC
AL
VALID
PSMODE PSMODE OPMODE OPMODE OPMODE
1
0
2
1
0
(a) Write
15
14
13
0
12
11
10
9
8
CnCTRL
Set
Set
AL
Set
Set
Set
Set
Set
CCERC
PSMODE PSMODE OPMODE OPMODE OPMODE
1
0
2
1
0
7
0
6
5
4
3
2
1
0
Clear
AL
Clear
Clear
Clear
Clear
Clear
Clear
VALID
PSMODE PSMODE OPMODE OPMODE OPMODE
1
0
2
1
0
(a) Read
RSTAT
Reception status bit
0
1
Reception is stopped.
Reception is in progress.
Remark • The RSTAT bit is set to 1 under the following conditions (timing)
• The SOF bit of a receive frame is detected
• On occurrence of arbitration loss during a transmit frame
• The RSTAT bit is cleared to 0 under the following conditions (timing)
• When a recessive level is detected at the second bit of the interframe space
• On transition to the initialization mode at the first bit of the interframe space
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TSTAT
Transmission status bit
0
1
Transmission is stopped.
Transmission is in progress.
Remark • The TSTAT bit is set to 1 under the following conditions (timing)
• The SOF bit of a transmit frame is detected
• The first bit of an error flag is detected during a transmit frame
• The TSTAT bit is cleared to 0 under the following conditions (timing)
• During transition to bus-off state
• On occurrence of arbitration loss in transmit frame
• On detection of recessive level at the second bit of the interframe space
• On transition to the initialization mode at the first bit of the interframe space
CCERC
Error counter clear bit
0
1
The CnERC and CnINFO registers are not cleared in the initialization mode.
The CnERC and CnINFO registers are cleared in the initialization mode.
Remarks 1. The CCERC bit is used to clear the CnERC and CnINFO registers for re-initialization or
forced recovery from the bus-off state. This bit can be set to 1 only in the initialization mode.
2. When the CnERC and CnINFO registers have been cleared, the CCERC bit is also cleared
to 0 automatically.
3. The CCERC bit can be set to 1 at the same time as a request to change the initialization
mode to an operation mode is made.
4. The CCERC bit is read-only in the CAN sleep mode or CAN stop mode.
AL
0
Bit to set operation in case of arbitration loss
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
1
Remarks 1. The AL bit is valid only in the single-shot mode.
2. The AL bit is read-only in the CAN sleep mode or CAN stop mode.
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CHAPTER 15 CAN CONTROLLER
(3/4)
VALID
Valid receive message frame detection bit
0
1
A valid message frame has not been received since the VALID bit was last cleared to 0.
A valid message frame has been received since the VALID bit was last cleared to 0.
Remarks 1. Detection of a valid receive message frame is not dependent upon storage in the receive
message buffer (data frame) or transmit message buffer (remote frame).
2. Clear the VALID bit (0) before changing the initialization mode to an operation mode.
3. If only two CAN nodes are connected to the CAN bus with one transmitting a message frame
in the normal mode and the other in the reception mode, the VALID bit is not set to 1 before
the transmitting node enters the error passive state.
4. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is
cleared. If it is not cleared, perform clearing processing again.
PSMODE1 PSMODE0
Power save mode
0
0
1
1
0
1
0
1
No power save mode is selected.
CAN sleep mode
Setting prohibited
CAN stop mode
Caution Transition to and from the CAN stop mode must be made via CAN sleep mode. A request
for direct transition to and from the CAN stop mode is ignored.
OPMODE2
OPMODE1
OPMODE0
Operation mode
No operation mode is selected (CAN module is in the initialization mode).
Normal operation mode
0
0
0
0
0
1
0
1
0
Normal operation mode with automatic block transmission function
(normal operation mode with ABT)
0
1
1
1
0
0
1
0
1
Receive-only mode
Single-shot mode
Self-test mode
Other than above
Setting prohibited
Remark The OPMODE[2:0] bits are read-only in the CAN sleep mode or CAN stop mode.
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(4/4)
(b) Write
Set CCERC
Setting of CCERC bit
1
CCERC bit is set to 1.
Other than above CCERC bit is not changed.
Set AL
Clear AL
Setting of AL bit
0
1
1
0
AL bit is cleared to 0.
AL bit is set to 1.
Other than above
AL bit is not changed.
Clear VALID
Setting of VALID bit
0
1
VALID bit is not changed.
VALID bit is cleared to 0.
Set PSMODE0 Clear PSMODE0
Setting of PSMODE0 bit
0
1
1
0
PSMODE0 bit is cleared to 0.
PSMODE bit is set to 1.
Other than above
PSMODE0 bit is not changed.
Set PSMODE1 Clear PSMODE1
Setting of PSMODE1 bit
0
1
1
0
PSMODE1 bit is cleared to 0.
PSMODE1 bit is set to 1.
Other than above
PSMODE1 bit is not changed.
Set OPMODE0 Clear OPMODE0
Setting of OPMODE0 bit
0
1
1
0
OPMODE0 bit is cleared to 0.
OPMODE0 bit is set to 1.
Other than above
OPMODE0 bit is not changed.
Set OPMODE1 Clear OPMODE1
Setting of OPMODE1 bit
0
1
1
0
OPMODE1 bit is cleared to 0.
OPMODE1 bit is set to 1.
Other than above
OPMODE1 bit is not changed.
Set OPMODE2 Clear OPMODE2
Setting of OPMODE2 bit
0
1
1
0
OPMODE2 bit is cleared to 0.
OPMODE2 bit is set to 1.
Other than above
OPMODE2 bit is not changed.
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(7) CAN module last error information register (CnLEC)
The CnLEC register provides the error information of the CAN protocol.
After reset: 00H
R/W
Address: C0LEC 03FEC052H, C1LEC 03FEC652H
C2LEC 03FECC52H, C3LEC 03FED252H
7
0
6
0
5
0
4
0
3
0
2
1
0
CnLEC
LEC2
LEC1
LEC0
Remarks 1. The contents of the CnLEC register are not cleared when the CAN module changes from an
operation mode to the initialization mode.
2. If an attempt is made to write a value other than 00H to the CnLEC register by software, the
access is ignored.
LEC2
LEC1
LEC0
Last CAN protocol error information
0
0
0
0
0
0
1
1
0
1
0
1
No error
Stuff error
Form error
ACK error
Bit error. (The CAN module tried to transmit a recessive-level bit as part of a
transmit message (except the arbitration field), but the value on the CAN bus is a
dominant-level bit.)
1
1
0
0
0
1
Bit error. (The CAN module tried to transmit a dominant-level bit as part of a
transmit message, ACK bit, error frame, or overload frame, but the value on the
CAN bus is a recessive-level bit.)
1
1
1
1
0
1
CRC error
Undefined
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(8) CAN module information register (CnINFO)
The CnINFO register indicates the status of the CAN module.
After reset: 00H
R
Address: C0INFO 03FEC053H, C1INFO 03FEC653H
C2INFO 03FECC53H, C3INFO 03FED253H
7
0
6
0
5
0
4
3
2
1
0
CnINFO
BOFF
BOFF
TECS1
TECS0
RECS1
RECS0
Bus-off status bit
0
1
Not bus-off state (transmit error counter ≤ 255). (The value of the transmit counter is less than 256.)
Bus-off state (transmit error counter > 255). (The value of the transmit counter is 256 or more.)
TECS1
TECS0
Transmission error counter status bit
The value of the transmission error counter is less than that of the warning level (< 96).
The value of the transmission error counter is in the range of the warning level (96 to 127).
Undefined
0
0
1
1
0
1
0
1
The value of the transmission error counter is in the range of the error passive or bus-off state
(≥ 128).
RECS1
RECS0
Reception error counter status bit
The value of the reception error counter is less than that of the warning level (< 96).
The value of the reception error counter is in the range of the warning level (96 to 127).
Undefined
0
0
1
1
0
1
0
1
The value of the reception error counter is in the error passive range (≥ 128).
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(9) CAN module error counter register (CnERC)
The CnERC register indicates the count value of the transmission/reception error counter.
After reset: 0000H
R
Address: C0ERC 03FEC054H, C1ERC 03FEC654H
C2ERC 03FECC54H, C3ERC 03FED254H
15
14
REC6
6
13
REC5
5
12
REC4
4
11
REC3
3
10
REC2
2
9
8
CnERC
REPS
7
REC1
1
REC0
0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
REPS
Reception error passive status bit
0
1
Reception error counter is not error passive (< 128)
Reception error counter is error passive range (≥ 128)
REC6 to REC0
0 to 127
Reception error counter bit
Number of reception errors. These bits reflect the status of the reception error counter. The
number of errors is defined by the CAN protocol.
Remark REC7 to REC0 of the reception error counter are invalid in the reception error passive state
(RECS[1:0] = 11B).
TEC7 to TEC0
0 to 255
Transmission error counter bit
Number of transmission errors. These bits reflect the status of the transmission error counter.
The number of errors is defined by the CAN protocol.
Remark TEC7 to TEC0 of the transmission error counter are invalid in the bus-off state (BOFF = 1).
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(10) CAN module interrupt enable register (CnIE)
The CnIE register is used to enable or disable the interrupts of the CAN module.
(1/2)
After reset: 0000H
R/W
Address: C0IE 03FEC056H, C1IE 03FEC656H
C2IE 03FECC56H, C3IE 03FED256H
(a) Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
CnIE
7
6
5
4
3
2
1
0
0
0
CIE5
CIE4
CIE3
CIE2
CIE1
CIE0
(b) Write
CnIE
15
0
14
0
13
12
11
10
9
8
Set
Set
Set
Set
Set
Set
CIE5
CIE4
CIE3
CIE2
CIE1
CIE0
7
0
6
0
5
4
3
2
1
0
Clear
CIE5
Clear
CIE4
Clear
CIE3
Clear
CIE2
Clear
CIE1
Clear
CIE0
(a) Read
CIE5 to CIE0
CAN module interrupt enable bit
0
1
Output of the interrupt corresponding to interrupt status register CINTSx is disabled.
Output of the interrupt corresponding to interrupt status register CINTSx is enabled.
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(2/2)
(b) Write
Set CIE5
Clear CIE5
Setting of CIE5 bit
0
1
1
0
CIE5 bit is cleared to 0.
CIE5 bit is set to 1.
Other than above
CIE5 bit is not changed.
Set CIE4
Clear CIE4
Setting of CIE4 bit
Setting of CIE3 bit
Setting of CIE2 bit
Setting of CIE1 bit
Setting of CIE0 bit
0
1
1
0
CIE4 bit is cleared to 0.
CIE4 bit is set to 1.
Other than above
CIE4 bit is not changed.
Set CIE3
Clear CIE3
0
1
1
0
CIE3 bit is cleared to 0.
CIE3 bit is set to 1.
Other than above
CIE3 bit is not changed.
Set CIE2
Clear CIE2
0
1
1
0
CIE2 bit is cleared to 0.
CIE2 bit is set to 1.
Other than above
CIE2 bit is not changed.
Set CIE1
Clear CIE1
0
1
1
0
CIE1 bit is cleared to 0.
CIE1 bit is set to 1.
Other than above
CIE1 bit is not changed.
Set CIE0
Clear CIE0
0
1
1
0
CIE0 bit is cleared to 0.
CIE0 bit is set to 1.
Other than above
CIE0 bit is not changed.
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(11) CAN module interrupt status register (CnINTS)
The CnINTS register indicates the interrupt status of the CAN module.
After reset: 0000H
R/W
Address: C0INTS 03FEC058H, C1INTS 03FEC658H
C2INTS 03FECC58H, C3INTS 03FED258H
(a) Read
15
0
14
0
13
12
11
10
9
8
CnINTS
0
5
0
4
0
3
0
2
0
1
0
0
7
6
0
0
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
(b) Write
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
8
0
0
CnINTS
7
6
5
4
3
2
0
0
Clear
Clear
Clear
Clear
Clear
Clear
CINTS5
CINTS4
CINTS3
CINTS2
CINTS1
CINTS0
(a) Read
CINTS5 to CINTS0
CAN interrupt status bit
0
1
No related interrupt source event is pending.
A related interrupt source event is pending.
Interrupt status bit
CINTS5
Related interrupt source event
Wakeup interrupt from CAN sleep modeNote
CINTS4
Arbitration loss interrupt
CINTS3
CAN protocol error interrupt
CAN error status interrupt
CINTS2
CINTS1
Interrupt on completion of reception of valid message frame to message buffer m
Interrupt on normal completion of transmission of message frame from message buffer m
CINTS0
Note The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode by a CAN
bus operation. The CINTS5 bit is not set when the CAN sleep mode has been released by
software.
(b) Write
Clear
Setting of CINTS5 to CINTS0 bits
CINTS5 to CINTS0
0
1
CINTS5 to CINTS0 bits are not changed.
CINTS5 to CINTS0 bits are cleared to 0.
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CHAPTER 15 CAN CONTROLLER
(12) CAN module bit rate prescaler register (CnBRP)
The CnBRP register is used to select the CAN protocol layer base clock (fTQ). The communication baud rate
is set to the CnBTR register.
After reset: FFH
R/W
Address: C0BRP 03FEC05AH, C1BRP 03FEC65AH
C2BRP 03FECC5AH, C3BRP 03FED25AH
7
6
5
4
3
2
1
0
CnBRP
TQPRS7
TQPRS6
TQPRS5
TQPRS4
TQPRS3
TQPRS2
TQPRS1
TQPRS0
TQPRS7 to TQPRS0
CAN protocol layer base system clock (fTQ)
0
1
fCANMOD/1
fCANMOD/2
n
fCANMOD/(n+1)
.....
255
.....
fCANMOD/256 (default value)
Figure 15-23. CAN Module Clock
CAN module clock selection register
(CnGMCS)
0
0
0
0
CCP3 CCP2 CCP1 CCP0
f
CANMOD
f
TQ
f
CAN
CAN bit-rate
register (CnBTR)
Prescaler
Baud rate generator
TQPRS2 TQPRS1
TQPRS5 TQPRS4 TQPRS3
TQPRS0
TQPRS7 TQPRS6
CAN module bit-rate prescaler register (CnBRP)
Remark fCAN: Clock supplied to CAN = fXX
fCANMOD: CAN module system clock
fTQ: CAN protocol layer basic system clock
Caution The CnBRP register can be write-accessed only in the initialization mode.
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CHAPTER 15 CAN CONTROLLER
(13) CAN module bit rate register (CnBTR)
The CnBTR register is used to control the data bit time of the communication baud rate.
(1/2)
After reset: 370FH
R/W
Address: C0BTR 03FEC05CH, C1BTR 03FEC65CH
C2BTR 03FECC5CH, C3BTR 03FED25CH
15
0
14
0
13
SJW1
5
12
SJW0
4
11
10
TSEG22
2
9
8
CnBTR
0
3
TSEG21
1
TSEG20
0
7
6
0
0
0
0
TSEG13
TSEG12
TSEG11
TSEG10
Figure 15-24. Data Bit Time
Data bit time (DBT)
Sync segment
Prop segment
Phase segment 1
Phase segment 2
Time segment 1 (TSEG1)
Time segment 2
(TSEG2)
Sample point (SPT)
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CHAPTER 15 CAN CONTROLLER
(2/2)
SJW1
SJW0
Length of synchronization jump width
0
0
1
1
0
1
0
1
1TQ
2TQ
3TQ
4TQ (default value)
TSEG22 TSEG21 TSEG20
Length of time segment 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1TQ
2TQ
3TQ
4TQ
5TQ
6TQ
7TQ
8TQ (default value)
TSEG13 TSEG12 TSEG11 TSEG10
Length of time segment 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Setting prohibited
2TQNote
3TQNote
4TQ
5TQ
6TQ
7TQ
8TQ
9TQ
10TQ
11TQ
12TQ
13TQ
14TQ
15TQ
16TQ (default value)
Note This setting must not be made when the CnBRP register = 00H.
Remark TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock)
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(14) CAN module last in-pointer register (CnLIPT)
The CnLIPT register indicates the number of the message buffer in which a data frame or a remote frame
was last stored.
After reset: Undefined
R
Address: C0LIPT 03FEC05EH, C1LIPT 03FEC65EH
C2LIPT 03FECC5EH, C3LIPT 03FED25EH
7
6
5
4
3
2
1
0
CnLIPT
LIPT7
LIPT6
LIPT5
LIPT4
LIPT3
LIPT2
LIPT1
LIPT0
LIPT7 to LIPT0
0.....31
Last in-pointer register (CnLIPT)
When the CnLIPT register is read, the contents of the element indexed by the last in-pointer
(LIPT) of the receive history list are read. These contents indicate the number of the message
buffer in which a data frame or a remote frame was last stored.
Remark The read value of the CnLIPT register is undefined if a data frame or a remote frame has never
been stored in the message buffer. If the RHPM bit of the CnRGPT register is set to 1 after the
CAN module has changed from the initialization mode to an operation mode, therefore, the read
value of the CnLIPT register is undefined.
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CHAPTER 15 CAN CONTROLLER
(15) CAN module receive history list register (CnRGPT)
The CnRGPT register is used to read the receive history list.
(1/2)
After reset: xx02H
R/W
Address: C0RGPT 03FEC060H, C1RGPT 03FEC660H
C2RGPT 03FECC60H, C3RGPT 03FED260H
(a) Read
15
14
13
12
11
10
9
8
RGPT0
0
CnRGPT
RGPT7
RGPT6
RGPT5
RGPT4
RGPT3
RGPT2
RGPT1
1
7
0
6
0
5
0
4
0
3
0
2
0
RHPM
ROVF
(b) Write
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
CnRGPT
7
6
5
4
3
2
0
0
0
0
0
0
Clear
ROVF
(a) Read
Receive history list read pointer
RGPT7 to RGPT0
0.....31
When the CnRGPT register is read, the contents of the element indexed by the receive history list
get pointer (RGPT) of the receive history list are read. These contents indicate the number of the
message buffer in which a data frame or a remote frame has been stored.
RHPMNote 1
Receive history list pointer match
0
1
The receive history list has at least one message buffer number that has not been read.
The receive history list has no message buffer numbers that have not been read.
ROVF
0
Receive history list overflow bit
All the message buffer numbers that have not been read are preserved. All the numbers of the
message buffers in which a new data frame or remote frame has been received and stored are recorded
to the receive history list (the receive history list has a vacant element).
1
All the message buffer numbers that are recorded are preserved except the message buffer number
recorded lastNote 2. The number of the message buffer in which a new data frame or remote frame has
been received and stored is recorded to the receive history list, by overwriting the message buffer
number that was recorded last (the receive history list does not have a vacant element).
Notes 1. The read value of RGPT0 to 7 is invalid when RHPM = 1.
2. If no new data frame or remote frame is received and stored in a message buffer after the
ROVF bit has been set, the message buffer number last recorded to the receive history list is
preserved.
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CHAPTER 15 CAN CONTROLLER
(2/2)
(b) Write
Clear ROVF
Setting of ROVF bit
0
1
ROVF bit is not changed.
ROVF bit is cleared to 0.
(16) CAN module last out-pointer register (CnLOPT)
The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame
was transmitted last.
After reset: Undefined
R
Address: C0LOPT 03FEC062H, C1LOPT 03FEC662H
C2LOPT 03FECC62H, C3LOPT 03FED262H
7
6
5
4
3
2
1
0
CnLOPT
LOPT7
LOPT6
LOPT5
LOPT4
LOPT3
LOPT2
LOPT1
LOPT0
LOPT7 to LOPT0
0.....31
Last out-pointer of transmit history list (LOPT)
When the CnLOPT register is read, the contents of the element indexed by the last out-pointer
(LOPT) of the receive history list are read. These contents indicate the number of the message
buffer to which a data frame or a remote frame was transmitted last.
Remark The value read from the CnLOPT register is undefined if a data frame or remote frame has never
been transmitted from a message buffer. If the THPM bit is set to 1 after the CAN module has
changed from the initialization mode to an operation mode, therefore, the read value of the
CnLOPT register is undefined.
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(17) CAN module transmit history list register (CnTGPT)
The CnTGPT register is used to read the transmit history list.
(1/2)
After reset: xx02H
R/W
Address: C0TGPT 03FEC064H, C1TGPT 03FEC664H
C2TGPT 03FECC64H, C3TGPT 03FED264H
(a) Read
15
14
13
12
11
10
9
8
TGPT0
0
CnTGPT
CnTGPT
TGPT7
TGPT6
TGPT5
TGPT4
TGPT3
TGPT2
TGPT1
1
7
0
6
0
5
0
4
0
3
0
2
0
THPM
TOVF
15
0
14
0
13
0
12
0
11
0
10
0
9
0
1
0
8
0
0
7
6
5
4
3
2
0
0
0
0
0
0
Clear
TOVF
TGPT7 to TGPT0
0.....31
Transmit history list read pointer
When the CnTGPT register is read, the contents of the element indexed by the read pointer
(TGPT) of the transmit history list are read. These contents indicate the number of the message
buffer to which a data frame or a remote frame was transmitted last.
THPMNote 1
Transmit history pointer match
0
1
The transmit history list has at least one message buffer number that has not been read.
The transmit history list has no message buffer numbers that have not been read.
TOVF
0
Transmit history list overflow bit
All the message buffer numbers that have not been read are preserved. All the numbers of the
message buffers to which a new data frame or remote frame has been transmitted are recorded
to the transmit history list (the transmit history list has a vacant element).
1
All the message buffer numbers that are recorded are preserved except the message buffer
number recorded lastNote 2. The number of the message buffer to which a new data frame or
remote frame has been transmitted is recorded to the transmit history list, by overwriting the
message buffer number that was recorded last (the transmit history list does not have a vacant
element).
Notes 1. The read value of TGPT0 to TGPT7 is invalid when THPM = 1.3.
2. If no new data frame or remote frame is transmitted after the TOVF bit has been set, the
message buffer number last recorded to the transmit history list is preserved.
Remark Transmission from message buffers 0 to 7 is not recorded to the transmit history list in the normal
operation mode with ABT.
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(2/2)
(b) Write
Clear TOVF
Setting of TOVF bit
0
1
TOVF bit is not changed.
TOVF bit is cleared to 0.
(18) CAN module time stamp register (CnTS)
The CnTS register is used to control the time stamp function.
(1/2)
After reset: 0000H
R/W
Address: C0TS 03FEC066H, C1TS 03FEC666H
C2TS 03FECC66H, C3TS 03FED266H
(a) Read
15
0
14
0
13
0
12
0
11
0
10
9
8
0
CnTS
0
2
0
1
7
6
5
4
3
0
0
0
0
0
0
TSLOCK
TSSEL
TSEN
(b) Write
CnTS
15
0
14
0
13
0
12
0
11
0
10
9
8
Set
Set
Set
TSLOCK
TSSEL
TSEN
7
0
6
0
5
0
4
0
3
0
2
1
0
Clear
Clear
Clear
TSLOCK
TSSEL
TSEN
Remark The time stamp function must not be used when the CAN module is in the normal operation
mode with ABT.
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CHAPTER 15 CAN CONTROLLER
(2/2)
(a) Read
TSLOCK
Time stamp lock function enable bit
Time stamp lock function stopped.
0
1
The TSOUT signal is toggled each time the selected time stamp capture event occurs.
Time stamp lock function enabled.
The TSOUT output signal is locked when a data frame has been correctly received to message
buffer 0Note
.
Note The TSEN bit is automatically cleared to 0.
TSSEL
Time stamp capture event selection bit
0
1
The time capture event is SOF.
The time stamp capture event is the last bit of EOF.
TSEN
TSOUT operation setting bit
0
1
TSOUT toggle operation is disabled.
TSOUT toggle operation is enabled.
(b) Write
Set TSLOCK Clear TSLOCK
Setting of TSLOCK bit
Setting of TSSEL bit
Setting of TSEN bit
0
1
1
0
TSLOCK bit is cleared to 0.
TSLOCK bit is set to 1.
Other than above
TSLOCK bit is not changed.
Set TSSEL
Clear TSSEL
0
1
1
0
TSSEL bit is cleared to 0.
TSSEL bit is set to 1.
Other than above
TSSEL bit is not changed.
Set TSEN
Clear TSEN
0
1
1
0
TSEN bit is cleared to 0.
TSEN bit is set to 1.
TSEN bit is not changed.
Other than above
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CHAPTER 15 CAN CONTROLLER
(19) CAN message data byte register (CnMDATAxm) (x = 0 to 7)
The CnMDATAxm register is used to store the data of a transmit/receive message.
(1/2)
After reset: Undefined
R/W
Address: See Table 15-16.
15
14
13
12
11
10
9
8
CnMDATA01m
MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01 MDATA01
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CnMDATA0m
CnMDATA1m
CnMDATA23m
MDATA0
7
MDATA0
6
MDATA0
5
MDATA0
4
MDATA0
3
MDATA0
2
MDATA0
1
MDATA0
0
7
6
5
4
3
2
1
0
MDATA1
7
MDATA1
6
MDATA1
5
MDATA1
4
MDATA1
3
MDATA1
2
MDATA1
1
MDATA1
0
15
14
13
12
11
10
9
8
MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23 MDATA23
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CnMDATA2m
CnMDATA3m
MDATA2
7
MDATA2
6
MDATA2
5
MDATA2
4
MDATA2
3
MDATA2
2
MDATA2
1
MDATA2
0
7
6
5
4
3
2
1
0
MDATA3
7
MDATA3
6
MDATA3
5
MDATA3
4
MDATA3
3
MDATA3
2
MDATA3
1
MDATA3
0
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CHAPTER 15 CAN CONTROLLER
(2/2)
15
14
13
12
11
10
9
8
CnMDATA45m
MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45 MDATA45
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CnMDATA4m
CnMDATA5m
CnMDATA67m
MDATA4
7
MDATA4
6
MDATA4
5
MDATA4
4
MDATA4
3
MDATA4
2
MDATA4
1
MDATA4
0
7
6
5
4
3
2
1
0
MDATA5
7
MDATA5
6
MDATA5
5
MDATA5
4
MDATA5
3
MDATA5
2
MDATA5
1
MDATA5
0
15
14
13
12
11
10
9
8
MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67 MDATA67
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CnMDATA6m
CnMDATA7m
MDATA6
7
MDATA6
6
MDATA6
5
MDATA6
4
MDATA6
3
MDATA6
2
MDATA6
1
MDATA6
0
7
6
5
4
3
2
1
0
MDATA7
7
MDATA7
6
MDATA7
5
MDATA7
4
MDATA7
3
MDATA7
2
MDATA7
1
MDATA7
0
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CHAPTER 15 CAN CONTROLLER
(20) CAN message data length register m (CnMDLCm)
The CnMDLCm register is used to set the number of bytes of the data field of a message buffer.
After reset: 0000xxxxB
7
R/W
Address: See Table 15-16.
6
5
0
4
0
3
2
1
0
CnMDLCm
0
0
MDLC3
MDLC2
MDLC1
MDLC0
MDLC3
MDLC2
MDLC1
MDLC0
Data length of transmit/receive message
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 bytes
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
Setting prohibited
(If these bits are set during transmission, 8-byte data is transmitted
regardless of the set DLC value when a data frame is transmitted.
However, the DLC actually transmitted to the CAN bus is the DLC
value set to this register.)Note
Note The data and DLC value actually transmitted to CAN bus are as follows.
Type of transmit frame
Data frame
Length of transmit data
DLC transmitted
Number of bytes specified by DLC
MDLC[3:0]
(However, 8 bytes if DLC ≥ 8)
Remote frame
0 bytes
Cautions 1. Be sure to set bits 7 to 4 to 0000B.
2. Receive data is stored in as many CnMDATAx as the number of bytes (however, the
upper limit is 8) corresponding to DLC. CnMDATAx in which no data is stored is
undefined.
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CHAPTER 15 CAN CONTROLLER
(21) CAN message configuration register (CnMCONFm)
The CnMCONFm register is used to specify the type of the message buffer and to set a mask.
(1/2)
After reset: Undefined
R/W
Address: See Table 15-16.
7
6
5
4
3
2
0
1
0
0
CnMCONFm
OWS
RTR
MT2
MT1
MT0
MA0
OWS
0
Overwrite control bit
The message bufferNote that has already received a data frame is not overwritten by a newly received
data frame. The newly received data frame is discarded.
1
The message buffer that has already received a data frame is overwritten by a newly received data
frame.
Note The “message buffer that has already received a data frame” is a receive message buffer whose
DN bit has been set to 1.
Remark A remote frame is received and stored, regardless of the setting of OWS and DN. A remote
frame that satisfies the other conditions (ID matches, RTR = 0, TRQ = 0) is always received and
stored in the corresponding message buffer (interrupt generated, DN flag set, MDLC[3:0] bits
updated, and recorded to the receive history list).
RTR
Remote frame request bitNote
0
1
Transmit a data frame.
Transmit a remote frame.
Note The RTR bit specifies the type of message frame that is transmitted from a message buffer defined
as a transmit message buffer. Even if a valid remote frame has been received, RTR of the transmit
message buffer that has received the frame remains cleared to 0. Even if a remote frame whose ID
matches has been received from the CAN bus with the RTR bit of the transmit message buffer set
to 1 to transmit a remote frame, that remote frame is not received or stored (interrupt generated, DN
flag set, MDLC[3:0] bits updated, and recorded to the receive history list).
MT2
MT1
MT0
Message buffer type setting bit
Transmit message buffer
0
0
0
0
1
1
0
0
1
0
1
0
1
0
Receive message buffer (no mask setting)
Receive message buffer (mask 1 set)
Receive message buffer (mask 2 set)
Receive message buffer (mask 3 set)
Receive message buffer (mask 4 set)
Setting prohibited
1
1
0
0
Other than above
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CHAPTER 15 CAN CONTROLLER
(2/2)
MA0
Message buffer assignment bit
0
1
Message buffer not used.
Message buffer used.
Caution Be sure to write 0 to bits 2 and 1.
(22) CAN message ID register m (CnMIDLm, CnMIDHm)
The CnMIDLm and CnMIDHm registers are used to set an identifier (ID).
After reset: Undefined
R/W
Address: See Table 15-16.
15
14
13
ID13
5
12
ID12
4
11
ID11
3
10
ID10
2
9
8
CnMIDLm
ID15
7
ID14
6
ID9
1
ID8
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
15
IDE
7
14
0
13
0
12
ID28
4
11
ID27
3
10
ID26
2
9
8
CnMIDHm
ID25
1
ID24
0
6
5
ID23
ID22
ID21
ID20
ID19
ID18
ID17
ID16
IDE
0
Format mode specification bit
Standard format mode (ID28 to ID18: 11 bits)Note
1
Extended format mode (ID28 to ID0: 29 bits)
Note The ID17 to ID0 bits are not used.
ID28 to ID0
Message ID
Standard ID value of 11 bits (when IDE = 0)
Extended ID value of 29 bits (when IDE = 1)
ID28 to ID18
ID28 to ID0
Caution Be sure to write 0 to bits 14 and 13 of the CnMIDHm register.
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(23) CAN message control register m (CnMCTRLm)
The CnMCTRLm register is used to control the operation of the message buffer.
(1/2)
After reset: 00x000000
00000000B
R/W
Address: See Table 15-16.
(a) Read
15
0
14
13
MUC
5
12
0
11
0
10
0
9
0
8
0
CnMCTRLm
0
6
0
7
4
3
2
1
0
0
0
MOW
IE
DN
TRQ
RDY
(b) Write
15
0
14
0
13
0
12
0
11
10
0
9
8
CnMCTRLm
Set
IE
Set
Set
TRQ
RDY
7
0
6
0
5
0
4
3
2
1
0
Clear
MOW
Clear
IE
Clear
DN
Clear
TRQ
Clear
RDY
(a) Read
MUCNote
Bit indicating that message buffer data is being updated
0
1
The CAN module is not updating the message buffer (reception and storage).
The CAN module is updating the message buffer (reception and storage).
Note The MUC bit is undefined until the first reception and storage is performed.
MOW
Message buffer overwrite status bit
The message buffer is not overwritten by a newly received data frame.
The message buffer is overwritten by a newly received data frame.
0
1
Remark MOW is not set to 1 even if a remote frame is received and stored in the transmit message buffer
with DN = 1.
IE
0
Message buffer interrupt request enable bit
Receive message buffer: Valid message reception completion interrupt disabled.
Transmit message buffer: Normal message transmission completion interrupt disabled.
1
Receive message buffer: Valid message reception completion interrupt enabled.
Transmit message buffer: Normal message transmission completion interrupt enabled.
DN
0
Message buffer data update bit
A data frame or remote frame is not stored in the message buffer.
A data frame or remote frame is stored in the message buffer.
1
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(2/2)
TRQ
Message buffer transmission request bit
0
1
No message frame transmitting request that is pending or being transmitted is in the message buffer.
The message buffer is holding transmission of a message frame pending or is transmitting a message
frame.
RDY
Message buffer ready bit
0
1
The message buffer can be written by software. The CAN module cannot write to the message buffer.
Writing the message buffer by software is ignored (except a write access to the RDY, TRQ, DN, and MOW
bits). The CAN module can write to the message buffer.
Caution Do not clear the RDY bit (0) during message transmission.
(b) Write
Clear MOW
Setting of MOW bit
0
1
MOW bit is not changed.
MOW bit is cleared to 0.
Set IE
Clear IE
Setting of IE bit
0
1
1
0
IE bit is cleared to 0.
IE bit is set to 1.
Other than above
IE bit is not changed.
Clear DN
Setting of DN bit
1
0
DN bit is cleared to 0.
DN bit is not changed.
Caution Do not set the DN bit to 1 by software. Be sure to write 0 to bit 10.
Set TRQ
Clear TRQ
Setting of TRQ bit
0
1
1
0
TRQ bit is cleared to 0.
TRQ bit is set to 1.
Other than above
TRQ bit is not changed.
Set RDY
Clear RDY
Setting of RDY bit
0
1
1
0
RDY bit is cleared to 0.
RDY bit is set to 1.
Other than above
RDY bit is not changed.
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CHAPTER 15 CAN CONTROLLER
15.7 Bit Set/Clear Function
The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN
interface. An operation error occurs if the following registers are written directly. Do not write any values directly via
bit manipulation, read/modify/write, or direct writing of target values.
• CAN global control register (CnGMCTRL)
• CAN global automatic block transmission control register (CnGMABT)
• CAN module control register (CnCTRL)
• CAN module interrupt enable register (CnIE)
• CAN module interrupt status register (CnINTS)
• CAN module receive history list register (CnRGPT)
• CAN module transmit history list register (CnTGPT)
• CAN module time stamp register (CnTS)
• CAN message control register (CnMCTRLm)
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
All the 16 bits in the above registers can be read via the usual method. Use the procedure described in figure 15-
25 below to set or clear the lower 8 bits in these registers.
Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to
the bit status after set/clear operation is specified in Figure 15-26). Figure 15-25 shows how the values of set bits or
clear bits relate to set/clear/no change operations in the corresponding register.
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Figure 15-25. Example of Bit Setting/Clearing Operations
Register’s current value
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
0
1
0
Write value
set
0
1
0
1
0
0
0
1
1
1
0
0
1
0
1
0
clear
Register’s value after
write operation
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Figure 15-26. Bit Status After Bit Setting/Clearing Operations
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0
Set n
Clear n
Status of bit n after bit set/clear operation
0
0
1
1
0
1
0
1
No change
0
1
No change
Remark n = 0 to 7
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15.8 CAN Controller Initialization
15.8.1 Initialization of CAN module
Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the
CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after
CAN module operation is enabled.
The CAN module is enabled by setting the GOM bit of the CnGMCTRL register.
For the procedure of initializing the CAN module, refer to 15.16 Operation of CAN Controller.
15.8.2 Initialization of message buffer
After the CAN module is enabled, the message buffers contain undefined values. A minimum initialization for all
the message buffers, even for those not used in the application, is necessary before switching the CAN module from
the initialization mode to one of the operation modes.
• Clear the RDY, TRQ, and DN bits of the CnMCTRLm register to 0.
• Clear the MA0 bit of the CnMCONFm register to 0.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
15.8.3 Redefinition of message buffer
Redefining a message buffer means changing the ID and control information of the message buffer while a
message is being received or transmitted, without affecting other transmission/reception operations.
(1) To redefine message buffer in initialization mode
Place the CAN module in the initialization mode once and then change the ID and control information of the
message buffer in the initialization mode. After changing the ID and control information, set the CAN module
to an operation mode.
(2) To redefine message buffer during reception
Perform redefinition as shown in Figure 15-38.
(3) To redefine message buffer during transmission
To rewrite the contents of a transmit message buffer to which a transmission request has been set, perform
transmission abort processing (refer to 15.10.4 (1) Transmission abort in normal operation mode and
15.10.4 (2) Transmission abort in normal operation mode with automatic block transmission (ABT)).
Confirm that transmission has been aborted or completed, and then redefine the message buffer. After
redefining the transmit message buffer, set a transmission request using the procedure described below.
When setting a transmission request to a message buffer that has been redefined without aborting the
transmission in progress, however, the 1-bit wait time is not necessary.
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Figure 15-27. Setting Transmission Request (TRQ) to Transmit Message Buffer After Redefinition
Redefinition completed
No
Execute
transmission?
Yes
Wait for 1 bit of CAN data.
Set TRQ bit
Set TRQ bit = 1
Clear TRQ bit = 0
END
Cautions 1. When a message is received, reception filtering is performed in accordance with the ID and
mask set to each receive message buffer. If the procedure in Figure 15-38 is not observed,
the contents of the message buffer after it has been redefined may contradict the result of
reception (result of reception filtering). If this happens, check that the ID and IDE received
first and stored in the message buffer following redefinition are those stored after the
message buffer has been redefined. If no ID and IDE are stored after redefinition, redefine
the message buffer again.
2. When a message is transmitted, the transmission priority is checked in accordance with the
ID, IDE, and RTR bits set to each transmit message buffer to which a transmission request
was set.
The transmit message buffer having the highest priority is selected for
transmission. If the procedure in Figure 15-27 is not observed, a message with an ID not
having the highest priority may be transmitted after redefinition.
15.8.4 Transition from initialization mode to operation mode
The CAN module can be switched to the following operation modes.
• Normal operation mode
• Normal operation mode with ABT
• Receive-only mode
• Single-shot mode
• Self-test mode
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Figure 15-28. Transition to Operation Modes
OPMODE[2:0] = 00H
and CAN bus is busy.
[Receive-only mode]
OPMODE[2:0]=03H
OPMODE[2:0] = 00H
and CAN bus is busy.
OPMODE[2:0] = 00H
and CAN bus is busy.
[Normal operation
mode with ABT]
OPMODE[2:0] = 03H
[Single-shot mode]
OPMODE[2:0]=04H
OPMODE[2:0]=02H
OPMODE[2:0] = 00H
and interframe space
OPMODE[2:0] = 00H
and interframe space
OPMODE[2:0] = 04H
OPMODE[2:0] = 02H
OPMODE[2:0] = 00H
OPMODE[2:0] = 00H
and interframe space
OPMODE[2:0] = 00H
and CAN bus is busy.
OPMODE[2:0] = 00H
and CAN bus is busy.
and interframe space
[Normal operation
mode]
OPMODE[2:0]=01H
INIT mode
OPMODE[2:0] = 00H
OPMODE[2:0] = 05H
[Self-test mode]
OPMODE[2:0]=05H
OPMODE[2:0] = 01H
OPMODE[2:0] = 00H
and interframe space
GOM = 1
All CAN modules are
in INIT mode and GOM = 0
EFSD = 1
and GOM = 0
CAN module
channel invalid
RESET released
RESET
The transition from the initialization mode to an operation mode is controlled by the bit string OPMODE[2:0] in the
CnCTRL register.
Changing from one operation mode into another requires shifting to the initialization mode in between. Do not
change one operation mode to another directly; otherwise the operation will not be guaranteed.
Requests for transition from an operation mode to the initialization mode are held pending when the CAN bus is not
in the interframe space (i.e., frame reception or transmission is in progress), and the CAN module enters the
initialization mode at the first bit in the interframe space (the values of OPMODE[2:0] are changed to 00H). After
issuing a request to change the mode to the initialization mode, read the OPMODE[2:0] bits until their values become
000B to confirm that the module has entered the initialization mode (refer to Figure 15-36).
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
15.8.5 Resetting error counter CnERC of CAN module
If it is necessary to reset the CAN module error counter CnERC and the CAN module information register CnINFO
when re-initialization or forced recovery from the bus-off state is made, set the CCERC bit of the CnCTRL register to 1
in the initialization mode. When this bit is set to 1, the CAN module error counter CnERC and the CAN module
information register CnINFO are cleared to their default values.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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15.9 Message Reception
15.9.1 Message reception
In all the operation modes, when a message is received, a message buffer that is to store the message is searched
from all the message buffers satisfying the following conditions.
• Used as a message buffer
(MA0 bit of CnMCONFm register set to 1B.)
• Set as a receive message buffer
(MT[2:0] bits of CnMCONFm register set to 001B, 010B, 011B, 100B, or 101B.)
• Ready for reception
(RDY bit of CnMCTRLm register set to 1.)
When two or more message buffers of the CAN module receive a message, the message is stored according to
the priority explained below. The message is always stored in the message buffer with the highest priority, not in a
message buffer with a low priority. For example, when an unmasked receive message buffer and a receive message
buffer linked to mask 1 have the same ID, the message is always stored in the unmasked receive message buffer
even if this unmasked receive buffer has already received a message earlier.
Priority
Storing Condition If Same ID Is Set
1 (high)
Unmasked message buffer
DN = 0
DN = 1 and OWS = 1
DN = 0
2
Message buffer linked to mask 1
Message buffer linked to mask 2
Message buffer linked to mask 3
Message buffer linked to mask 4
DN = 1 and OWS = 1
DN = 0
3
DN = 1 and OWS = 1
DN = 0
4
DN = 1 and OWS = 1
DN = 0
5 (low)
DN = 1 and OWS = 1
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15.9.2 Receive history list function
The receive history list (RHL) function records in the receive history list the number of the receive message buffer
in which each data frame or remote frame was received and stored. The RHL consists of storage elements
equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the
receive history list get pointer (RGPT) with the corresponding CnRGPT register.
The RHL is undefined immediately after the transition of the CAN module from the initialization mode to one of the
operation modes.
The CnLIPT register holds the contents of the RHL element indicated by the value of the LIPT pointer minus 1. By
reading the CnLIPT register, therefore, the number of the message buffer that received and stored a data frame or
remote frame first can be checked. The LIPT pointer is utilized as a write pointer that indicates to what part of the
RHL a message buffer number is recorded. Any time a data frame or remote frame is received and stored, the
corresponding message buffer number is recorded to the RHL element indicated by the LIPT pointer. Each time
recording to the RHL has been completed; the LIPT pointer is automatically incremented. In this way, the number of
the message buffer that has received and stored a frame will be recorded chronologically.
The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL. This
pointer indicates the first RHL element that the CPU has not read yet. By reading the CnRGPT register by software,
the number of a message buffer that has received and stored a data frame or remote frame can be read. Each time a
message buffer number is read from the CnRGPT register, the RGPT pointer is automatically incremented.
If the value of the RGPT pointer matches the value of the LIPT pointer, the RHPM bit (receive history list pointer
match) of the CnRGPT register is set to 1. This indicates that no message buffer number that has not been read
remains in the RHL. If a new message buffer number is recorded, the LIPT pointer is incremented and because its
value no longer matches the value of the RGPT pointer, the RHPM bit is cleared. In other words, the numbers of the
unread message buffers exist in the RHL.
If the LIPT pointer is incremented and matches the value of the RGPT pointer minus 1, the ROVF bit (receive
history list overflow) of the CnRGPT register is set to 1. This indicates that the RHL is full of numbers of message
buffers that have not been read. When further message reception and storing occur, the last recorded message
buffer number is overwritten by the number of the message buffer that received and stored the new message. After
the ROVF bit has been set (1), therefore, the recorded message buffer numbers in the RHL do not completely reflect
the chronological order.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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Figure 15-29. Receive History List
Receive history list (RHL)
Receive history list (RHL)
When message buffer 6 is read
23
22
23
22
:
:
:
:
:
:
If message is stored in message
buffers 3, 4, and 8
Last in-message
pointer (LIPT)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Message buffer 8
Message buffer 4
Message buffer 3
Message buffer 7
Message buffer 2
Message buffer 9
Last in-message
pointer (LIPT)
Message buffer 7
Message buffer 2
Message buffer 9
Message buffer 6
Receive history
list get pointer
(RGPT)
Receive history
list get pointer
(RGPT)
When RHL is full
Receive history list (RHL)
Message buffer 3
Receive history list (RHL)
When message buffer 3
receives and stores more messages
Message buffer 1
Message buffer 9
23
23
22
When ROVF = 1, message
buffer number is stored
(overwritten) to element
indicated by LIPT-1.
Message buffer 9
22
ROVF is set.
:
:
:
Message buffer 5
Message buffer 8
Message buffer 4
Message buffer 3
7
6
5
4
3
2
1
0
Message buffer 5
Message buffer 8
Message buffer 4
7
6
5
4
3
2
1
0
Message buffer 3
Message buffer 7
Message buffer 2
Message buffer 9
Message buffer 7
Message buffer 2
Message buffer 9
Receive history
list get pointer
Last in-message
(RGPT)
Receive history
list get pointer
(RGPT)
Last in-message
pointer (LIPT)
pointer (LIPT)
LIPT is locked.
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15.9.3 Mask function
It can be defined whether masking of the identifier that is set to a message buffer is linked with another message
buffer.
By using the mask function, the identifier of a message received from the CAN bus can be compared with the
identifier set to a message buffer in advance. Regardless of whether the masked ID is set to 0 or 1, the received
message can be stored in the defined message buffer.
While the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not
compared with the corresponding identifier bit in the message buffer.
However, this comparison is performed for any bit whose value is defined as 0 by the mask.
For example, let us assume that all messages that have a standard-format ID, in which bits ID27 to ID25 are 0 and
bits ID24 and ID22 are 1, are to be stored in message buffer 14. The procedure for this example is shown below.
<1> Identifier to be stored in message buffer
ID28
x
ID27
0
ID26
0
ID25
0
ID24
1
ID23
x
ID22
1
ID21
x
ID20
x
ID19
x
ID18
x
x = don’t care
<2> Identifier to be configured in message buffer 14 (example)
(Using CANn message ID registers L14 and H14 (CnMIDL14 and CnMIDH14))
ID28
x
ID27
0
ID26
0
ID25
0
ID24
1
ID23
x
ID22
1
ID21
x
ID20
x
ID19
x
ID18
x
ID17
x
ID16
x
ID15
x
ID14
x
ID13
x
ID12
x
ID11
x
ID10
x
ID9
x
ID8
x
ID7
x
ID6
x
ID5
x
ID4
x
ID3
x
ID2
x
ID1
x
ID0
x
ID with ID27 to ID25 cleared to 0 and ID24 and ID22 set to 1 is registered (initialized) to message buffer 14.
Remark Message buffer 14 is set as a standard format identifier that is linked to mask 1 (MT[2:0] of
CnMCONF14 register are set to 010B).
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<3> Mask setting for CAN module 1 (mask 1) (Example)
(Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1))
CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18
1
0
0
0
0
1
0
1
1
1
CMID8
1
1
CMID7
1
CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9
1
CMID6
1
1
CMID5
1
1
CMID4
1
1
CMID3
1
1
CMID2
1
1
CMID1
1
1
CMID0
1
1
1
1: Not compared (masked)
0: Compared
The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to
CMID0 bits are set to 1.
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15.9.4 Multi buffer receive block function
The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers
sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message
buffer type.
Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and
the same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is
received, it is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting
the message buffer when subsequent messages are received.
When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time
a message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13,
and so on. Even when a data block consisting of multiple messages is received, the messages can be stored and
received without overwriting the previously received matching-ID data.
Whether a data block has been received and stored can be checked by setting the IE bit of the CnMCTRLm
register of each message buffer. For example, if a data block consists of k messages, k message buffers are
initialized for reception of the data block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled),
and the IE bit in message buffer k-1 is set to 1 (interrupts enabled). In this case, a reception completion interrupt
occurs when a message has been received and stored in message buffer k-1, indicating that MBRB has become full.
Alternatively, by clearing the IE bit of message buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a
warning that MBRB is about to overflow can be issued.
The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions
of storing data in a single message buffer.
Cautions 1. MBRB can be configured for each of the same message buffer types. Therefore, even if a
message buffer of another MBRB whose ID matches but whose message buffer type is
different has a vacancy, the received message is not stored in that message buffer, but
instead discarded.
2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the
message buffer having the highest number in the MBRB configuration, a newly received
message will not be stored in the message buffer having the lowest message buffer number.
3. MBRB operates based on the reception and storage conditions; there are no settings
dedicated to MBRB, such as function enable bits. By setting the same message buffer type
and ID to two or more message buffers, MBRB is automatically configured.
4. With MBRB, “matching ID” means “matching ID after mask”. Even if the ID set to each
message buffer is not the same, if the ID that is masked by the mask register matches, it is
considered a matching ID and the buffer that has this ID is treated as the storage destination
of a message.
5. The priority between MBRBs is mentioned in the table of 15.9.1 Message Reception.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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15.9.5 Remote frame reception
In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame
is searched from all the message buffers satisfying the following conditions.
• Used as a message buffer
(MA0 bit of CnMCONFm register set to 1B.)
• Set as a transmit message buffer
(MT[2:0] bits in CnMCONFm register set to 000B)
• Ready for reception
(RDY bit of CnMCTRLm register set to 1.)
• Set to transmit message
(RTR bit of CnMCONFm register is cleared to 0.)
• Transmission request is not set.
(TRQ bit of CnMCTRLm register is cleared to 1.)
Upon acceptance of a remote frame, the following actions are executed if the ID of the received remote frame
matches the ID of a message buffer that satisfies the above conditions.
• The DLC[3:0] bit string in the CnMDLCm register stores the received DLC value.
• CnMDATA0m to CnMDATA7m in the data area are not updated (data before reception is saved).
• The DN bit of the CnMCTRLm register is set to 1.
• The CINTS1 bit of the CnINTS register is set to 1 (if the IE bit in the CnMCTRLm register of the message buffer
that receives and stores the frame is set to 1).
• The receive completion interrupt (INTRECn) is output (if the IE bit in the CnMCTRLm register of the message
buffer that receives and stores the frame is set to 1 and if the CIE1 bit of the CnIE register is set to 1).
• The message buffer number is recorded in the receive history list.
Caution When a message buffer is searched for receiving and storing a remote frame, overwrite control
by the OWS bit of the CnMCONFm register of the message buffer and the DN bit of the
CnMCTRLm register are not affected.
If more than one transmit message buffer has the same ID and the ID of the received remote
frame matches that ID, the remote frame is stored in the transmit message buffer with the lowest
message buffer number.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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15.10 Message Transmission
15.10.1 Message transmission
In all the operation modes, if the TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the
message buffer that is to transmit a message is searched.
• Used as a message buffer
(MA0 bit of CnMCONFm register set to 1B.)
• Set as a transmit message buffer
(MT[2:0] bits of CnMCONFm register set to 000B.)
• Ready for transmission
(RDY bit of CnMCTRLm register set to 1.)
The CAN system is a multi-master communication system. In a system like this, the priority of message
transmission is determined based on message identifiers (IDs). To facilitate transmission processing by software
when there are several messages awaiting transmission, the CAN module uses hardware to check the ID of the
message with the highest priority and automatically identifies that message. This eliminates the need for software-
based priority control.
Transmission priority is controlled by the identifier (ID).
Figure 15-30. Message Processing Example
Message No. Message waiting to be transmitted
0
1
2
3
4
5
6
7
8
9
ID = 120H
ID = 229H
The CAN module transmits messages in the following sequence.
1. Message 6
2. Message 1
3. Message 8
4. Message 5
5. Message 2
ID = 223H
ID = 023H
ID = 123H
After the transmit message search, the transmit message with the highest priority of the transmit message buffers
that have a pending transmission request (message buffers with the TRQ bit set to 1 in advance) is transmitted.
If a new transmission request is set, the transmit message buffer with the new transmission request is compared
with the transmit message buffer with a pending transmission request. If the new transmission request has a higher
priority, it is transmitted, unless transmission of a message with a low priority has already started. If transmission of a
message with a low priority has already started, however, the new transmission request is transmitted later. The
highest priority is determined according to the following rules.
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Priority
1 (high)
Conditions
Description
Value of first 11 bits of ID
[ID28 to ID18]:
The message frame with the lowest value represented by the first 11 bits of the ID
is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than
the first 11 bits of a 29-bit extended ID, the 11-bit standard ID has a higher priority
than a message frame with a 29-bit extended ID.
2
Frame type
ID type
A data frame with an 11-bit standard ID (RTR bit is cleared to 0) has a higher
priority than a remote frame with a standard ID and a message frame with an
extended ID.
3
4
A message frame with a standard ID (IDE bit is cleared to 0) has a higher priority
than a message frame with an extended ID.
Value of lower 18 bits of ID
[ID17 to ID0]:
If one or more transmission-pending extended ID message frame has equal
values in the first 11 bits of the ID and the same frame type (equal RTR bit
values), the message frame with the lowest value in the lower 18 bits of its
extended ID is transmitted first.
5 (low)
Message buffer number
If two or more message buffers request transmission of message frames with the
same ID, the message from the message buffer with the lowest message buffer
number is transmitted first.
Remarks 1. If the automatic block transmission request bit ABTTRG is set to 1 in the normal operation mode
with ABT, the TRQ bit is set to 1 only for one message buffer in the ABT message buffer group.
If the TRQ bit is set to 1 for this buffer and for the message buffers that do not belong to the ABT
message buffer group, a conflict occurs. When messages are successively transmitted from the
automatic block transmission area (message buffers 0 to 7), therefore, the priority of the
transmission ID is not searched, and the messages are transmitted sequentially, starting from the
buffer with the lowest number. However, the priority among automatic block transmission messages
and message buffers other than those in the automatic block transmission area is in compliance with
the above rule.
Upon successful transmission of a message frame, the following operations are performed.
• The TRQ flag of the corresponding transmit message buffer is automatically cleared to 0.
• The transmission completion status bit CINTS0 of the CnINTS register is set to 1 (if the interrupt
enable bit (IE) of the corresponding transmit message buffer is set to 1).
• An interrupt request signal INTRRX1 is output (if the CIE0 bit of the CnIE register is set to 1 and if
the interrupt enable bit (IE) of the corresponding transmit message buffer is set to 1).
2. n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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15.10.2 Transmit history list function
The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer
in which each data frame or remote frame was received and stored. The THL consists of storage elements equivalent
to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the
transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
The THL is undefined immediately after the transition of the CAN module from the initialization mode to one of the
operation modes.
The CnLOPT register holds the contents of the THL element indicated by the value of the LOPT pointer minus 1.
By reading the CnLOPT register, therefore, the number of the message buffer that transmitted a data frame or remote
frame first can be checked. The LOPT pointer is utilized as a write pointer that indicates to what part of the THL a
message buffer number is recorded. Any time a data frame or remote frame is transmitted, the corresponding
message buffer number is recorded to the THL element indicated by the LOPT pointer. Each time recording to the
THL has been completed; the LOPT pointer is automatically incremented. In this way, the number of the message
buffer that has received and stored a frame will be recorded chronologically.
The TGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the THL. This
pointer indicates the first THL element that the CPU has not yet read. By reading the CnTGPT register by software,
the number of a message buffer that has completed transmission can be read. Each time a message buffer number
is read from the CnTGPT register, the TGPT pointer is automatically incremented.
If the value of the TGPT pointer matches the value of the LOPT pointer, the THPM bit (transmit history list pointer
match) of the CnTGPT register is set to 1. This indicates that no message buffer numbers that have not been read
remain in the THL. If a new message buffer number is recorded, the LOPT pointer is incremented and because its
value no longer matches the value of the TGPT pointer, the THPM bit is cleared. In other words, the numbers of the
unread message buffers exist in the THL.
If the LOPT pointer is incremented and matches the value of the TGPT pointer minus 1, the TOVF bit (receive
history list overflow) of the CnTGPT register is set to 1. This indicates that the THL is full of message buffer numbers
that have not been read. If a new message is received and stored, the message buffer number recorded last is
overwritten by the number of the message buffer that received and stored the new message. After the TOVF bit has
been set (1), therefore, the recorded message buffer numbers in the THL do not completely reflect the chronological
order.
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Figure 15-31. Transmit History List
Transmit history list (THL)
Transmit history list (THL)
When message buffer 6 is read
7
6
7
6
5
4
3
2
1
0
If transmission from
message buffers 3 and 4
is completed
Last
out-message
pointer (LOPT)
5
4
3
2
1
0
Message buffer 4
Message buffer 3
Last out-message
pointer (LOPT)
Message buffer 7
Message buffer 2
Message buffer 9
Message buffer 6
Message buffer 7
Message buffer 2
Message buffer 9
Transmit history list
get pointer (TGPT)
Transmit history list
get pointer (TGPT)
When THL is full
Transmit history list (THL)
Transmit history list(THL)
When transmission from message
buffer 3 is completed.
7
6
5
4
3
2
1
0
Message buffer 3
Message buffer 8
Message buffer 4
Message buffer 3
Message buffer 7
Message buffer 2
Message buffer 9
7
6
5
4
3
2
1
0
Message buffer 5
When TOVF = 1, message buffer
number is stored (overwritten) to
element indicated by LOPT-1.
TOVF is set.
Message buffer 8
Message buffer 4
Message buffer 3
Message buffer 7
Message buffer 2
Message buffer 9
Transmit
history
Transmit history list
get pointer (TGPT)
Last out-message
pointer (LOPT)
Last out-message
list get
pointer (LOPT)
pointer
(TGPT)
LOPT is locked.
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15.10.3 Automatic block transmission (ABT)
The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no
CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message
buffer numbers 0 to 7).
By setting OPMODE[2:0] of the CnCTRL register to 010B, “normal operation mode with automatic block
transmission function” (hereafter referred to as ABT mode) can be selected.
To issue an ABT transmission request, define the message buffers by software first. Set the MA0 bit (1) in all the
message buffers used for ABT, and define all the buffers as transmit message buffers by setting the MT[2:0] bits to
000B. Be sure to set the same ID for the message buffers for ATB even when that ID is being used for all the
message buffers. To use two or more IDs, set the ID of each message buffer by using the CnMIDLm and CnMIDHm
registers. Set the CnMDLCm and CnMDATA0m to CnMDATA7m registers before issuing a transmission request for
the ABT function.
After initialization of message buffers for ABT is finished, the RDY bit needs to be set (1). In the ABT mode, the
TRQ bit does not have to be manipulated by software.
After the data for the ABT message buffers has been prepared, set the ABTTRG bit to 1. Automatic block
transmission is then started. When ABT is started, the TRQ bit in the first message buffer (message buffer 0) is
automatically set to 1. After transmission of the data of message buffer 0 is finished, TRQ of the next message buffer,
message buffer 1, is set automatically. In this way, transmission is executed successively.
A delay time can be inserted by program in the interval in which the transmission request (TRQ) is automatically
set while successive transmission is being executed. The delay time to be inserted is defined by the CnGMABTD
register. The unit of the delay time is DBT (data bit time). DBT depends on the setting of the CnBRP and CnBTR
registers.
During ABT, the priority of the transmission ID is not searched. The data of message buffers 0 to 7 is sequentially
transmitted. When transmission of the data frame from message buffer 7 has been completed, the ABTTRG bit is
automatically cleared to 0 and the ABT operation is finished.
If the RDY bit of an ABT message buffer is cleared during ABT, no data frame is transmitted from that buffer, ABT
is stopped, and the ABTTRG bit is cleared. After that, transmission can be resumed from the message buffer where
ABT stopped, by setting the RDY and ABTTRG bits to 1 by software. To not resume transmission from the message
buffer where ABT stopped, the internal ABT engine can be reset by setting the ABTCLR bit to 1 while ABT mode is
stopped and ABTTRG is cleared to 0. In this case, transmission is started from message buffer 0 if the ABTCLR bit is
cleared to 0 and then the ABTTRG bit is set to 1.
An interrupt can be used to check if data frames have been transmitted from all the message buffers for ABT. To
do so, the IE bit of the CnMCTRLm register of each message buffer except the last message buffer needs to be
cleared (0).
If a transmit message buffer other than those used by the ABT function (message buffer 8 to 31) is assigned to a
transmit message buffer, the priority of the message to be transmitted is determined by the priority of the transmission
ID of the ABT message buffer whose transmission is currently held pending and the transmission ID of the message
buffers other than those used by the ABT function.
Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL).
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Cautions 1. Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1
while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.
2. If the automatic block transmission engine is cleared by setting the ABTCLR bit to 1, the
ABTCLR bit is automatically cleared immediately after the processing of the clearing
request is completed.
3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the
initialization mode, the proper operation is not guaranteed after the mode is changed from
the initialization mode to the ABT mode.
4. Do not set TRQ of the ABT message buffers to 1 by software in the normal operation mode
with ABT. Otherwise, the operation is not guaranteed.
5. The CnGMABTD register is used to set the delay time that is inserted in the period from
completion of the preceding ABT message to setting of the TRQ bit for the next ABT
message when the transmission requests are set in the order of message numbers for
each message for ABT that is successively transmitted in the ABT mode. The timing at
which the messages are actually transmitted onto the CAN bus varies depending on the
status of transmission from other stations and the status of the setting of the
transmission request for messages other than the ABT messages (message buffer 8 to
31).
6. If a transmission request is made for a message other than an ABT message and if no
delay time is inserted in the interval in which transmission requests for ABT are
automatically set (CnGMABTD = 00H), messages other than ABT messages are
transmitted. At this time, transmission does not depend on the priority of the ABT
message.
7. Do not clear the RDY bit to 0 when ABTTRG = 1.
8. If a message is received from another node in the normal operation mode with ABT, the
message may be transmitted after the time of one frame has elapsed (when CnGMABTD
register = 00H).
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15.10.4 Transmission abort process
(1) Transmission abort in normal operation mode
The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit
will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted or
not can be checked using the TSTAT bit of the CnCTRL register and the CnTGPT register, which indicate the
transmission status on the CAN bus (for details, refer to the processing in Figure 15-44).
(2) Transmission abort process except for ABT transmission in normal operation mode with automatic
block transmission (ABT)
The user can clear the ABTTRG bit of the CnGMABT register to 0 to abort a transmission request. After
checking the ABTTRG bit of the CnGMABT register = 0, clear the TRQ bit of the CnMCTRLm register to 0.
The TRQ bit will be cleared immediately if the abort was successful. Whether the transmission was
successfully aborted or not can be checked using the TSTAT bit of the CnCTRL register and the CnTGPT
register, which indicate the transmission status on the CAN bus (for details, refer to the processing in Figure
15-46).
(3) Transmission abort in normal operation mode with automatic block transmission (ABT)
To abort ABT that is already started, clear the ABTTRG bit of the CnGMABT register to 0. In this case, the
ABTTRG bit remains 1 if an ABT message is currently being transmitted and until the transmission is
completed (successfully or not), and is cleared to 0 as soon as transmission is finished. This aborts ABT.
If the last transmission (before ABT) was successful, the normal operation mode with ABT is left with the
internal ABT pointer pointing to the next message buffer to be transmitted.
In the case of an erroneous transmission, the position of the internal ABT pointer depends on the status of the
TRQ bit in the last transmitted message buffer. If the TRQ bit is set to 1 when clearing the ABTTRG bit is
requested, the internal ABT pointer points to the last transmitted message buffer (for details, refer to the
process in Figure 15-45).
When the normal operation mode with ABT is resumed after ABT has been aborted and ABTTRG is set to 1, the
next ABT message buffer to be transmitted can be determined from the following table.
Status of TRQ of ABT Message Buffer
Abort After Successful Transmission
Abort After Erroneous Transmission
Set (1)
Next message buffer in the ABT areaNote Same message buffer in the ABT area
Next message buffer in the ABT areaNote Next message buffer in the ABT areaNote
Cleared (0)
Note The above resumption operation can be performed only if a message buffer ready for ABT exists in the
ABT area. For example, an abort request that is issued while ABT of message buffer 7 is in progress is
regarded as completion of ABT, rather than abort, if transmission of message buffer 7 has been
successfully completed, even if ABTTRG is cleared to 0. If the RDY bit in the next message buffer in the
ABT area is cleared to 0, the internal ABT pointer is retained, but the resumption operation is not performed
even if ABTTRG is set to 1, and ABT ends immediately.
15.10.5 Remote frame transmission
Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame
is transmitted via the RTR bit of the CnMCONFm register. Setting (1) the RTR bit sets remote frame transmission.
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15.11 Power Saving Modes
15.11.1 CAN sleep mode
The CAN sleep mode can be used to set the CAN controller to standby mode in order to reduce power
consumption. The CAN module can enter the CAN sleep mode from all operation modes. Release of the CAN sleep
mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
In the CAN sleep mode, the CAN module does not transmit messages, even when transmission requests are
issued or pending.
(1) Entering CAN sleep mode
The CPU issues a CAN sleep mode transition request by writing 01B to the PSMODE[1:0] bits of the CnCTRL
register.
This transition request is only acknowledged only under the following conditions.
(i) The CAN module is already in one of the following operation modes
• Normal operation mode
• Normal operation mode with ABT
• Receive-only mode
• Single-shot mode
• Self-test mode
• CAN stop mode in all the above operation modes
(ii) The CAN bus state is bus idle (the 4th bit in the interframe space is recessive)Note
Note If the CAN bus is fixed to dominant, the request for transition to the CAN sleep mode is held
pending.
(iii) No transmission request is pending
If any one of the conditions mentioned above is not met, the CAN module will operate as follows.
• If the CAN sleep mode is requested from the initialization mode, the CAN sleep mode transition request
is ignored and the CAN module remains in the initialization mode.
• If the CAN bus state is not bus idle (i.e., the CAN bus state is either transmitting or receiving) when the
CAN sleep mode is requested in one of the operation modes, immediate transition to the CAN sleep
mode is not possible. In this case, the CAN sleep mode transition request has to be held pending until
the CAN bus state becomes bus idle (the 4th bit in the interframe space is recessive). In the time from
the CAN sleep mode request to successful transition, the PSMODE[1:0] bits remain 00B. When the
module has entered the CAN sleep mode, PSMODE[1:0] are set to 01B.
• If a request for transition to the initialization mode and a request for transition to the CAN sleep mode
are made at the same time while the CAN module is in one of the operation modes, the request for the
initialization mode is enabled. The CAN module enters the initialization mode at a predetermined timing.
At this time, the CAN sleep mode request is not held pending and is ignored.
• If a CAN sleep mode request is pending waiting for the CAN bus state to become bus idle while the
CAN module is in one of the operation modes, and if a request for transition to the initialization mode is
made, the pending CAN sleep mode request becomes disabled, and only the initialization mode request
is enabled (in this case, the CAN sleep mode request continues to be held pending).
• If the CAN sleep mode transition request is made while an initialization mode transition request is held
pending waiting for completion of communication in one of the operation modes, the CAN sleep mode
transition request is ignored and only the initialization mode transition request remains valid (in this
case, the CAN sleep mode request continues to be held pending).
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(2) Status in CAN sleep mode
The CAN module is in one of the following states after it enters the CAN sleep mode.
• The internal operating clock is stopped and the power consumption is minimized.
• The function to detect the falling edge of the CAN reception pin (CRXDn) remains in effect to wake up the
CAN module from the CAN bus.
• To wake up the CAN module from the CPU, data can be written to PSMODE[1:0] of the CAN module control
register (CnCTRL), but nothing can be written to other CAN module registers or bits.
• The CAN module registers can be read, except for CnLIPT, CnRGPT, CnLOPT, and CnTGPT.
• The CAN message buffer registers cannot be written or read.
• A request for transition to the initialization mode is not acknowledged and is ignored.
(3) Releasing CAN sleep mode
The CAN sleep mode is released by the following events.
• When the CPU writes 00B to the PSMODE[1:0] bits of the CnCTRL register
• A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant)
Caution If this falling edge is at the SOF of a receive frame, no receive operation, including returning
ACK, is performed on that frame. No receive operation is performed on the subsequent
frames either, unless the clock is supplied to the CAN macro.
After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode
was requested and the PSMODE[1:0] bits of the CnCTRL register are reset to 00B. If the CAN sleep mode is
released by a change in the CAN bus state, the CINTS5 bit of the CnINTS register is set to 1, regardless of the CIE bit
of the CnIE register. After the CAN module is released from the CAN sleep mode, it participates in the CAN bus
again by automatically detecting 11 consecutive recessive-level bits on the CAN bus.
When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode,
that request is ignored; the CPU has to be released from sleep mode by software first before entering the initialization
mode.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
15.11.2 CAN stop mode
The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The
CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the
CAN module in the CAN sleep mode.
The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bits of the CnCTRL register and not
by a change in the CAN bus state. No message is transmitted even when transmission requests are issued or
pending.
(1) Entering CAN stop mode
A CAN stop mode transition request is issued by writing 11B to the PSMODE[1:0] bits of the CnCTRL register.
A CAN stop mode request is only acknowledged when the CAN module is in the CAN sleep mode. In all other
modes, the request is ignored.
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Caution To set the CAN module to the CAN stop mode, the module must be in the CAN sleep mode.
To confirm that the module is in the sleep mode, check that PSMODE[1:0] = 01B, and then
request the CAN stop mode. If a bus change occurs at the CAN reception pin (CRXD) while
this process is being performed, the CAN sleep mode is automatically released. In this case,
the CAN stop mode transition request cannot be acknowledged.
(2) Status in CAN stop mode
The CAN module is in one of the following states after it enters the CAN stop mode.
• The internal operating clock is stopped and the power consumption is minimized.
• To wake up the CAN module from the CPU, data can be written to PSMODE[1:0] of the CAN module control
register (CnCTRL), but nothing can be written to other CAN module registers or bits.
• The CAN module registers can be read, except for CnLIPT, CnRGPT, CnLOPT, and CnTGPT.
• The CAN message buffer registers cannot be written or read.
• An initialization mode transition request is not acknowledged and is ignored.
(3) Releasing CAN stop mode
The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bits of the CnCTRL register.
When the initialization mode is requested while the CAN module is in the CAN stop mode, that request is
ignored; the CPU has to release the stop mode and subsequently CAN sleep mode before entering the
initialization mode.
15.11.3 Example of using power saving modes
In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power
consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to
the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Here is an example of using the power saving modes.
First, put the CAN module in the CAN sleep mode (PSMODE = 01B). Next, put the CPU in the power saving
mode. If an edge transition from recessive to dominant is detected at the CAN reception pin (CRXDn) in this status,
the CINTS5 bit in the CAN module is set to 1. If the CIE5 bit of the CnCTRL register is set to 1, a wakeup interrupt
(INTWUP) is generated. The CAN module is automatically released from the CAN sleep mode (PSMODE = 00B) and
returns to the normal operation mode. The CPU, in response to INTWUP, can release its own power saving mode
and return to the normal operation mode.
To further reduce the power consumption of the CPU, the internal clocks, including that of the CAN module, may
be stopped. In this case, the operating clock supplied to the CAN module is stopped after the CAN module is put in
the CAN sleep mode. Then the CPU enters a power saving mode in which the clock supplied to the CPU is stopped.
If an edge transition from recessive to dominant is detected at the CAN reception pin (CRXDn) in this status, the CAN
module can set the CINTS5 bit to 1 and generate the wakeup interrupt (INTWUP) even if it is not supplied with the
clock. The other functions, however, do not operate because clock supply to the CAN module is stopped, and the
module remains in the CAN sleep mode. The CPU, in response to INTWUP, releases its power saving mode,
resumes supply of the internal clocks, including the clock to the CAN module, after the oscillation stabilization time
has elapsed, and starts instruction execution. The CAN module is immediately released from the CAN sleep mode
when clock supply is resumed, and returns to the normal operation mode (PSMODE = 00B).
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15.12 Interrupt Function
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request
signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or
more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After
an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software.
Table 15-20. List of CAN Module Interrupt Sources
No.
Interrupt Status Bit
Interrupt Enable Bit
Interrupt
Interrupt Source Description
Request Signal
Name
Register
CnINTS
Name
Register
CnIE
1
CINTS0
CIE0Note
INTCnTRX
Message frame successfully transmitted from
message buffer m
2
3
4
5
6
CINTS1
CINTS2
CINTS3
CINTS4
CINTS5
CnINTS
CnINTS
CnINTS
CnINTS
CnINTS
CIE1Note
CIE2
CIE3
CIE4
CnIE
CnIE
CnIE
CnIE
CnIE
INTCnREC
INTCnERR
Valid message frame reception in message buffer m
CAN module error state interrupt (Supplement 1)
CAN module protocol error interrupt (Supplement 2)
CAN module arbitration loss interrupt
CIE5
INTCnWUP
CAN module wakeup interrupt from CAN sleep mode
(Supplement 3)
Note The IE bit (message buffer interrupt enable bit) in the CnMCTRL register of the corresponding message
buffer has to be set to 1 for that message buffer to participate in the interrupt generation process.
Supplements 1. This interrupt is generated when the transmission/reception error counter is at the warning level,
or in the error passive or bus-off state.
2. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error
occurs.
3. This interrupt is generated when the CAN module is woken up from the CAN sleep mode
because a falling edge is detected at the CAN reception pin (CAN bus transition from recessive
to dominant).
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
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15.13 Diagnosis Functions and Special Operational Modes
The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus
diagnosis functions or the operation of special CAN communication methods.
15.13.1 Receive-only mode
The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and
can be used for CAN bus analysis nodes.
For example, this mode can be used for automatic baud-rate detection. The baud rate in the CAN module is
changed until “valid reception” is detected, so that the baud rates in the module match (“valid reception” means a
message frame has been received in the CAN protocol layer without occurrence of an error and with an appropriate
ACK between nodes connected to the CAN bus). A valid reception does not require message frames to be stored in
a receive message buffer (data frames) or transmit message buffer (remote frames). The event of valid reception is
indicated by setting the VALID bit of the CnCTRL register (1).
Figure 15-32. CAN Module Terminal Connection in Receive-Only Mode
CAN macro
Tx
Rx
Fixed to
the recessive
level
CRXDn
CTXDn
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In the receive-only mode, no message frames can be transmitted from the CAN module to the CAN bus. Transmit
requests issued for message buffers defined as transmit message buffers are held pending.
In the receive-only mode, the CAN transmission pin (CTXDn) in the CAN module is fixed to the recessive level.
Therefore, no active error flag can be transmitted from the CAN module to the CAN bus even when a CAN bus error
is detected while receiving a message frame. Since no transmission can be issued from the CAN module, the
transmission error counter TEC is never updated. Therefore, a CAN module in the receive-only mode does not enter
the bus-off state.
Furthermore, ACK is not returned to the CAN bus in this mode upon the valid reception of a message frame.
Internally, the local node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN
bus.
Caution If only two CAN nodes are connected to the CAN bus and one of them is operating in the receive-
only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will
transmit an active error flag, and repeat transmitting a message frame. The transmitting node
becomes error passive after transmitting the message frame 16 times (assuming that the error
counter was 0 in the beginning and no other errors have occurred). When the message frame is
transmitted for the 17th time, the transmitting node generates a passive error flag. The receiving
node in the receive-only mode detects the first valid message frame at this point, and the VALID
bit is set to 1 for the first time.
15.13.2 Single-shot mode
In the single-shot mode, automatic re-transmission as defined in the CAN protocol is switched off. (According to the
CAN protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has
to be repeated without control by software.)
The single-shot mode disables the re-transmission of an aborted message frame transmission according to the
setting of the AL bit of the CnCTRL register. When the AL bit is cleared to 0, re-transmission upon arbitration loss and
upon error occurrence is disabled. If the AL bit is set to 1, re-transmission upon error occurrence is disabled, but re-
transmission upon arbitration loss is enabled. As a consequence, the TRQ bit in a message buffer defined as a
transmit message buffer is cleared to 0 by the following events.
• Successful transmission of the message frame
• Arbitration loss while sending the message frame (AL bit = 0)
• Error occurrence while sending the message frame
The events arbitration loss and error occurrence can be distinguished by checking the CINTS4 and CINTS3 bits of
the CnINTS register, and the type of the error can be identified by reading the LEC[2:0] bits of the CnLEC register.
Upon successful transmission of the message frame, the transmit completion interrupt bit CINTS0 of the CnINTS
register is set to 1. If the CIE0 bit of the CnIE register is set to 1 at this time, an interrupt request signal is output.
The single-shot mode can be used when emulating time-triggered communication methods (e.g., TTCAN level 1).
Caution The AL bit is only valid in Single-shot mode. It does not influence the operation of re-
transmission upon arbitration loss in the other operation modes.
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15.13.3 Self-test mode
In the self-test mode, message frame transmission and message frame reception can be tested without connecting
the CAN node to the CAN bus or without affecting the CAN bus.
In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and
reception are internally looped back. The CAN transmission pin (CTXDn) is fixed to the recessive level.
If the falling edge on the CAN reception pin (CRXDn) is detected after the CAN module has entered the CAN sleep
mode from the self-test mode, however, the module is released from the CAN sleep mode in the same manner as the
other operation modes. To keep the module in the CAN sleep mode, use the CAN reception pin (CRXDn) as a port
pin.
Figure 15-33. CAN Module Terminal Connection in Self-Test Mode
CAN macro
Tx
Rx
Fixed to
the recessive
level
CTXDn
CRXDn
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
15.14 Time Stamp Function
CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As
a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have
different frequencies).
In some applications, however, a common time base over the network (= global time base) is needed. In order to
build up a global time base, a time stamp function is used. The essential mechanism of a time stamp function is the
capture of timer values triggered by signals on the CAN bus.
15.14.1 Time stamp function
The CAN controller supports the capturing of timer values triggered by successful reception of a data frame. An
on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the CAN controller. The 16-bit
capture timer unit captures the timer value according to a trigger signal (TSOUT) for capturing that is output when a
data frame is received from the CAN controller. The CPU can retrieve the time of occurrence of the capture event,
i.e., the time stamp of the message received from the CAN bus, by reading the captured value. TSOUT can be
selected from the following two event sources and is specified by the TSSEL bit of the CnTS register.
• SOF event (start of frame)
(TSSEL = 0)
• EOF event (last bit of end of frame) (TSSEL = 1)
The TSOUT signal is enabled by setting the TSEN bit of the CnTS register to 1.
Figure 15-34. Timing Diagram of Capture Signal TSOUT
SOF
SOF
SOF
SOF
TSOUT
t
TSOUT toggles its level upon occurrence of the selected event during data frame reception (in the above timing
diagram, the SOF is used as the trigger event source). To capture a timer value by using TSOUT, the capture timer
unit must detect the capture signal at both the rising edge and falling edge.
This time stamp function is controlled by the TSLOCK bit of the CnTS register. When TSLOCK is cleared to 0,
TSOUT toggles upon occurrence of the selected event. If TSLOCK is set to 1, TSOUT toggles upon occurrence of
the selected event, but the toggle is stopped as the TSEN bit is automatically cleared to 0 when a data frame is
received and stored in message buffer 0. This suppresses the subsequent toggle occurrence by TSOUT, so that the
time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data
frame was received in message buffer 0.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Caution The time stamp function using TSLOCK stops toggle of TSOUT by receiving a data frame in
message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since
a receive message buffer cannot receive a remote frame, toggle of TSOUT cannot be stopped by
reception of a remote frame. Toggle of TSOUT does not stop when a data frame is received in a
message buffer other than message buffer 0.
For these reasons, a data frame cannot be received in message buffer 0 when the CAN module is
in the normal operation mode with ABT, because message buffer 0 must be set as a transmit
message buffer. In this operation mode, therefore, the function to stop toggle of TSOUT by
TSLOCK cannot be used.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
15.15 Baud Rate Settings
15.15.1 Bit rate setting conditions
Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller,
as follows.
(a) 5TQ ≤ SPT (sampling point) ≤ 17 TQ
SPT = TSEG1 + 1
(b) 8 TQ ≤ DBT (data bit time) ≤ 25 TQ
DBT = TSEG1 + TSEG2 + 1TQ = TSEG2 + SPT
(c) 1 TQ ≤ SJW (synchronization jump width) ≤ 4TQ
SJW ≤ DBT – SPT
(d) 4 ≤ TSEG1 ≤ 16 [3 ≤ Setting value of TSEG1[3:0] ≤ 15]
(e) 1 ≤ TSEG2 ≤ 8 [0 ≤ Setting value of TSEG2[2:0] ≤ 7]
Remark TQ = 1/fTQ (fTQ: CAN protocol layer basic system clock)
TSEG1[3:0] (Bits 3 to 0 of CANn bit rate register (CnBTR))
TSEG2[2:0] (Bits 10 to 8 of CANn bit rate register (CnBTR))
Table 15-21 shows the combinations of bit rates that satisfy the above conditions.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Table 15-21. Settable Bit Rate Combinations (1/3)
Valid Bit Rate Setting
PROP
CnBTR Register Setting Value Sampling Point
(Unit %)
DBT Length
SYNC
PHASE
PHASE
TSEG1[3:0]
TSEG2[2:0]
SEGMENT
SEGMENT
SEGMENT1
SEGMENT2
25
24
24
23
23
23
22
22
22
22
21
21
21
21
21
20
20
20
20
20
20
19
19
19
19
19
19
19
18
18
18
18
18
18
18
18
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
7
8
8
7
8
7
6
8
7
6
5
8
7
6
5
4
8
7
6
5
4
3
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
8
7
8
7
6
8
7
6
5
8
7
6
5
4
8
7
6
5
4
3
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
1111
1110
1111
1101
1110
1111
1100
1101
1110
1111
1011
1100
1101
1110
1111
1010
1011
1100
1101
1110
1111
1001
1010
1011
1100
1101
1110
1111
1000
1001
1010
1011
1100
1101
1110
1111
111
111
110
111
110
101
111
110
101
100
111
110
101
100
011
111
110
101
100
011
010
111
110
101
100
011
010
001
111
110
101
100
011
010
001
000
68.0
66.7
70.8
65.2
69.6
73.9
63.6
68.2
72.7
77.3
61.9
66.7
71.4
76.2
81.0
60.0
65.0
70.0
75.0
80.0
85.0
57.9
63.2
68.4
73.7
78.9
84.2
89.5
55.6
61.1
66.7
72.2
77.8
83.3
88.9
94.4
9
6
8
10
5
7
9
11
4
6
8
10
12
3
5
7
9
11
13
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Table 15-21. Settable Bit Rate Combinations (2/3)
Valid Bit Rate Setting
PROP
CnBTR Register Setting Value Sampling Point
(Unit %)
DBT Length
SYNC
PHASE
PHASE
TSEG1[3:0]
TSEG2[2:0]
SEGMENT
SEGMENT
SEGMENT1
SEGMENT2
17
17
17
17
17
17
17
16
16
16
16
16
16
16
15
15
15
15
15
15
14
14
14
14
14
14
13
13
13
13
13
12
12
12
12
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
7
6
5
4
3
2
1
7
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
7
6
5
4
3
2
1
7
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
1000
1001
1010
1011
1100
1101
1110
0111
1000
1001
1010
1011
1100
1101
0111
1000
1001
1010
1011
1100
0110
0111
1000
1001
1010
1011
0110
0111
1000
1001
1010
0101
0110
0111
1000
1001
110
101
100
011
010
001
000
110
101
100
011
010
001
000
101
100
011
010
001
000
101
100
011
010
001
000
100
011
010
001
000
100
011
010
001
000
58.8
64.7
70.6
76.5
82.4
88.2
94.1
56.3
62.5
68.8
75.0
81.3
87.5
93.8
60.0
66.7
73.3
80.0
86.7
93.3
57.1
64.3
71.4
78.6
85.7
92.9
61.5
69.2
76.9
84.6
92.3
58.3
66.7
75.0
83.3
91.7
6
8
10
12
14
1
3
5
7
9
11
13
2
4
6
8
10
12
1
3
5
7
9
11
2
4
6
8
10
1
3
5
7
9
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Table 15-21. Settable Bit Rate Combinations (3/3)
Valid Bit Rate Setting
PROP
CnBTR Register Setting Value
Sampling Point
(Unit %)
DBT Length
SYNC
PHASE
PHASE
TSEG1[3:0]
TSEG2[2:0]
SEGMENT
SEGMENT
SEGMENT1
SEGMENT2
11
11
11
11
10
10
10
10
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
6
8
1
3
5
7
2
4
6
1
3
5
2
4
1
3
2
1
4
3
2
1
4
3
2
1
3
2
1
3
2
1
2
1
2
1
1
1
4
3
2
1
4
3
2
1
3
2
1
3
2
1
2
1
2
1
1
1
0101
0110
0111
1000
0100
0101
0110
0111
0100
0101
0110
0011
0100
0101
0011
0100
0010
0011
0010
0001
011
010
001
000
011
010
001
000
010
001
000
010
001
000
001
000
001
000
000
000
63.6
72.7
81.8
90.9
60.0
70.0
80.0
90.0
66.7
77.8
88.9
62.5
75.0
87.5
71.4
85.7
66.7
83.3
80.0
75.0
9
9
8
8
8
7Note
7Note
6Note
6Note
5Note
4Note
Note Setting with a DBT value of 7 or less is valid only when the value of the CnBRP register is other than 00H.
Caution The values in Table 15-21 do not guarantee the operation of the network system. Thoroughly
check the effect on the network system, taking into consideration oscillation errors and delays of
the CAN bus and CAN transceiver.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
15.15.2 Representative examples of baud rate settings
Tables 15-22 and 15-23 show representative examples of baud rate settings.
Table 15-22. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (1/2)
Set Baud
Rate Value
(Unit: kbps)
Division
Ratio of
CnBRP
CnBRP
Register Set
Value
Valid Bit Rate Setting (Unit: kbps)
CnBTR Register Setting Sampling
Value
Point
(Unit: %)
Length of
DBT
SYNC
PROP
PHASE
PHASE
TSEG1
[3:0]
TSEG2
[2:0]
SEGMENT SEGMENT SEGMENT1 SEGMENT2
1000
1000
1000
500
500
500
500
500
500
500
500
500
500
250
250
250
250
250
250
250
250
250
125
125
125
125
125
125
125
125
125
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
8
8
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000011
00000011
00000011
00000011
00000011
00000011
00000011
00000011
00000011
00000111
00000111
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
2
1
7
6
5
4
3
2
1
3
2
1
7
6
5
4
3
2
1
2
1
7
6
5
4
3
2
1
2
1
3
2
1
7
6
5
4
3
2
1
3
2
1
7
6
5
4
3
2
1
2
1
7
6
5
4
3
2
1
2
1
0011
0100
0101
0111
1000
1001
1010
1011
1100
1101
0011
0100
0101
0111
1000
1001
1010
1011
1100
1101
0100
0101
0111
1000
1001
1010
1011
1100
1101
0100
0101
010
001
000
110
101
100
011
010
001
000
010
001
000
110
101
100
011
010
001
000
001
000
110
101
100
011
010
001
000
001
000
62.5
75.0
87.5
56.3
62.5
68.8
75.0
81.3
87.5
93.8
62.5
75.0
87.5
56.3
62.5
68.8
75.0
81.3
87.5
93.8
75.0
87.5
56.3
62.5
68.8
75.0
81.3
87.5
93.8
75.0
87.5
8
8
5
16
16
16
16
16
16
16
8
1
3
5
7
9
11
13
1
8
3
8
5
16
16
16
16
16
16
16
8
1
3
5
7
9
11
13
3
8
5
16
16
16
16
16
16
16
8
1
3
5
7
9
11
13
3
8
5
Caution The values in Table 15-22 do not guarantee the operation of the network system. Thoroughly
check the effect on the network system, taking into consideration oscillation errors and delays of
the CAN bus and CAN transceiver.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Table 15-22. Representative Examples of Baud Rate Settings (fCANMOD = 8 MHz) (2/2)
Set Baud
Rate Value
(Unit: kbps)
Division
Ratio of
CnBRP
CnBRP
Register Set
Value
Valid Bit Rate Setting (Unit: kbps)
CnBTR Register Setting Sampling
Value
Point
(Unit: %)
Length of
DBT
SYNC
PROP
PHASE
PHASE
TSEG1
[3:0]
TSEG2
[2:0]
SEGMENT SEGMENT SEGMENT1 SEGMENT2
100
100
4
4
00000011
00000011
00000100
00000100
00000111
00000111
00001001
00001001
00000011
00000011
00000101
00000101
00000101
00000101
00000111
00000111
00001011
00001011
00001001
00001001
00001011
00001011
00001110
00001110
00001111
00001111
00010011
00010011
00010111
00010111
00011101
00011101
20
20
16
16
10
10
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
9
7
9
3
5
3
5
7
9
5
7
9
11
5
7
3
5
7
9
7
9
7
9
6
8
5
7
3
5
3
5
6
5
4
3
3
2
2
1
8
7
5
4
3
2
3
2
2
1
8
7
6
5
4
3
4
3
3
2
3
2
2
1
6
5
4
3
3
2
2
1
8
7
5
4
3
2
3
2
2
1
8
7
6
5
4
3
4
3
3
2
3
2
2
1
1100
1101
1010
1011
0101
0110
0100
0101
1110
1111
1001
1010
1011
1100
0111
1000
0100
0101
1110
1111
1100
1101
1010
1011
1001
1010
0111
1000
0101
0110
0100
0101
101
100
011
010
010
001
001
000
111
110
100
011
010
001
010
001
001
000
111
110
101
100
011
010
011
010
010
001
010
001
001
000
70.0
75.0
75.0
81.3
70.0
80.0
75.0
87.5
66.7
70.8
68.8
75.0
81.3
87.5
75.0
83.3
75.0
87.5
66.7
70.8
70.0
75.0
75.0
81.3
73.3
80.0
75.0
83.3
70.0
80.0
75.0
87.5
100
5
100
5
100
8
100
8
100
10
10
4
100
8
83.3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
24
24
16
16
16
16
12
12
8
4
6
6
6
6
8
8
12
12
10
10
12
12
15
15
16
16
20
20
24
24
30
30
8
24
24
20
20
16
16
15
15
12
12
10
10
8
8
Caution The values in Table 15-22 do not guarantee the operation of the network system. Thoroughly
check the effect on the network system, taking into consideration oscillation errors and delays of
the CAN bus and CAN transceiver.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Table 15-23. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (1/2)
Set Baud
Rate Value
(Unit: kbps)
Division
Ratio of
CnBRP
CnBRP
Register Set
Value
Valid Bit Rate Setting (Unit: kbps)
CnBTR Register Setting Sampling
Value
Point
(Unit: %)
Length of
DBT
SYNC
PROP
PHASE
PHASE
TSEG1
[3:0]
TSEG2
[2:0]
SEGMENT SEGMENT SEGMENT1 SEGMENT2
1000
1000
1000
1000
1000
1000
1000
1000
1000
500
500
500
500
500
500
500
500
500
250
250
250
250
250
250
250
125
125
125
125
125
125
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
8
8
8
8
8
8
16
16
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000011
00000011
00000011
00000011
00000011
00000011
00000011
00000111
00000111
00000111
00000111
00000111
00000111
00001111
00001111
16
16
16
16
16
16
16
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
7
6
5
4
3
2
1
2
1
7
6
5
4
3
2
1
2
1
6
5
4
3
2
2
1
6
4
3
2
2
1
7
6
5
4
3
2
1
2
1
7
6
5
4
3
2
1
2
1
6
5
4
3
2
2
1
6
4
3
2
2
1
0111
1000
1001
1010
1011
1100
1101
0100
0101
0111
1000
1001
1010
1011
1100
1101
0100
0101
1000
1001
1010
1011
1100
0100
0101
1000
1010
1011
1100
0100
0101
110
101
100
011
010
001
000
001
000
110
101
100
011
010
001
000
001
000
101
100
011
010
001
001
000
101
011
010
001
001
000
56.3
62.5
68.8
75.0
81.3
87.5
93.8
75.0
87.5
56.3
62.5
68.8
75.0
81.3
87.5
93.8
75.0
87.5
62.5
68.8
75.0
81.3
87.5
75.0
87.5
62.5
75.0
81.3
87.5
75.0
87.5
5
7
9
11
13
3
8
5
16
16
16
16
16
16
16
8
1
3
5
7
9
11
13
3
8
5
16
16
16
16
16
8
3
5
7
9
11
3
8
5
16
16
16
16
8
3
7
9
11
3
8
5
Caution The values in Table 15-23 do not guarantee the operation of the network system. Thoroughly
check the effect on the network system, taking into consideration oscillation errors and delays of
the CAN bus and CAN transceiver.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 15 CAN CONTROLLER
Table 15-23. Representative Examples of Baud Rate Settings (fCANMOD = 16 MHz) (2/2)
Set Baud
Rate Value
(Unit: kbps)
Division
Ratio of
CnBRP
CnBRP
Register Set
Value
Valid Bit Rate Setting (Unit: kbps)
CnBTR Register Setting Sampling
Value
Point
(Unit: %)
Length of
DBT
SYNC
PROP
PHASE
PHASE
TSEG1
[3:0]
TSEG2
[2:0]
SEGMENT SEGMENT SEGMENT1 SEGMENT2
100
100
8
00000111
00000111
00001001
00001001
00001111
00001111
00010011
00000111
00000111
00001011
00001011
00001011
00001111
00001111
00010111
00010111
00011101
00011101
00010111
00010111
00011101
00011101
00011111
00011111
00100100
00100100
00100111
00100111
00101111
00101111
00111011
00111011
20
20
16
16
10
10
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
11
7
5
4
4
3
3
2
2
8
7
4
3
2
3
2
2
1
8
7
5
4
4
3
3
2
3
2
3
2
3
2
2
1
5
4
4
3
3
2
2
8
7
4
3
2
3
2
2
1
8
7
5
4
4
3
3
2
3
2
3
2
3
2
2
1
1101
1110
1010
1011
0101
0110
0100
1110
1111
1010
1011
1100
0111
1000
0100
0101
1110
1111
1101
1110
1010
1011
1010
1011
1000
1001
0111
1000
0101
0110
0100
0101
100
011
011
010
010
001
001
111
110
011
010
001
010
001
001
000
111
110
100
011
011
010
010
001
010
001
010
001
010
001
001
000
75.0
80.0
75.0
81.3
70.0
80.0
75.0
66.7
70.8
75.0
81.3
87.5
75.0
83.3
75.0
87.5
66.7
70.8
75.0
80.0
75.0
81.3
80.0
86.7
76.9
84.6
75.0
83.3
70.0
80.0
75.0
87.5
8
100
10
10
16
16
20
8
100
9
100
3
100
5
100
3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
83.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
24
24
16
16
16
12
12
8
7
8
9
12
12
12
16
16
24
24
30
30
24
24
30
30
32
32
37
37
40
40
48
48
60
60
7
9
11
5
7
3
8
5
24
24
20
20
16
16
15
15
13
13
12
12
10
10
8
7
9
9
11
7
9
8
10
6
8
5
7
3
5
3
8
5
Caution The values in Table 15-23 do not guarantee the operation of the network system. Thoroughly
check the effect on the network system, taking into consideration oscillation errors and delays of
the CAN bus and CAN transceiver.
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
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CHAPTER 15 CAN CONTROLLER
15.16 Operation of CAN Controller
Remark . n = 0 (µPD70F3231, µPD70F3232, µPD70F3233)
n = 0, 1(µPD70F3234, µPD70F3235, µPD70F3236, µPD70F3237)
n = 0 to 3 (µPD70F3238, µPD70F3239)
m = 0 to 31
Figure 15-35. Initialization
START
Set
CnGMCS register.
Set
CnGMCTRL
register (Set GOM = 1).
Set
CnBRP register,
CnBTR register.
Set
CnIE register.
Set
CnMASK register.
Initialize
message buffers.
Set
CnCTRL register (set OPMODE).
END
Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-
shot mode, self-test mode
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CHAPTER 15 CAN CONTROLLER
Figure 15-36. Re-initialization
START
Clear
OPMODE.
No
INIT mode?
Yes
Set
CnBRP register,
CnBTR register.
Initialize message buffers.
Set
CnIE register.
CnERC and
CnINFO
register clear?
No
Set
CnMASK register.
Yes
Set CCERC bit.
Set CCERC = 1
Clear CCERC = 0
Set CnCTRL register.
(Set OPMODE)
END
Caution After setting the CAN module to the initialization mode, avoid setting the module to another
operation mode immediately after. If it is necessary to immediately set the module to another
operation mode, be sure to access registers other than the CnCTRL and CnGMCTRL
registers (e.g., set a message buffer).
Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-
shot mode, self-test mode
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Figure 15-37. Message Buffer Initialization
START
No
RDY = 1?
Yes
Clear RDY bit.
Set RDY bit = 0
Clear RDY bit = 1
No
RDY = 0?
Yes
Set
CnMCONFm register.
Set
CnMIDHm register,
CnMIDLm register
No
Transmit message
buffer?
Yes
Set
CnMDLCm register.
Clear
CnMDATAm register.
Set
CnMCTRLm register.
Set RDY bit.
Set RDY bit = 1
Clear RDY bit = 0
END
Cautions 1. Before a message buffer is initialized, the RDY bit must be cleared.
2. Make the following settings for message buffers not used by the application.
• Clear the RDY, TRQ, and DN bits of the CnMCTRLm register to 0.
• Clear the MA0 bit of the CnMCONFm register to 0.
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CHAPTER 15 CAN CONTROLLER
Figure 15-38 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001B to
101B).
Figure 15-38. Message Buffer Redefinition
START
Clear VALID bit
CnCTRLCLEAR_VALID=1
No
RDY = 1?
Yes
Clear RDY bit
CnMCTRLm.SET_RDY = 0
CnMCTRLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
No
RSTAT = 0 or
VALID = 1?
Note
Yes
Wait for 4 CAN data bits
Set
message buffers
Set RDY bit
CnMCTRLm.SET_RDY = 1
CnMCTRLm.CLEAR_RDY = 0
END
Note If redefinition is performed during a message reception, confirm that a message is being received
because the RDY bit must be set after a message is completely received.
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CHAPTER 15 CAN CONTROLLER
Figure 15-39 shows the processing for a transmit message buffer during transmission (MT2 to MT0 bits of
CnMCONFm register = 000B).
Figure 15-39. Transmitting Message Buffer Redefinition
START
Transmit abort process
Clear RDY bit
CnMCTRLm.SET_RDY = 0
CnMCTRLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Data frame
Remote frame
Data frame or remote frame?
Set CnMDATAxm register
Set CnMDLCm register
Set RTR bit of CnMCONFm
register
Set CnMIDLm and CnMIDHm
registers
Set CnMDLCm register
Clear RTR bit of CnMCONFm
register
Set CnMIDLm and CnMIDHm
registers
Set RDY bit
CnMCTRLm.SET_RDY = 1
CnMCTRLm.CLEAR_RDY = 0
No
Transmit?
Yes
Wait for 1CAN data bits
Set TRQ bit
CnMCTRLm.SET_TRQ = 1
CnMCTRLm.CLEAR_TRQ = 0
END
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CHAPTER 15 CAN CONTROLLER
Figure 15-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B).
Figure 15-40. Message Transmit Processing (Normal Operation Mode)
START
No
TRQ = 0?
Yes
Clear RDY bit
CnMCTRLm.SET_RDY = 0
CnMCTRLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Data frame
Remote frame
Data frame or remote frame?
Set CnMDATAxm register
Set CnMDLCm register
Set RTR bit of CnMCONFm
register
Set CnMIDLm and CnMIDHm
registers
Set CnMDLCm register
Clear RTR bit of CnMCONFm
register
Set CnMIDLm and CnMIDHm
registers
Set RDY bit
CnMCTRLm.SET_RDY = 1
CnMCTRLm.CLEAR_RDY = 0
Set TRQ bit
CnMCTRLm.SET_TRQ = 1
CnMCTRLm.CLEAR_TRQ = 0
END
Caution The TRQ bit should be set after the RDY bit is set.
The RDY bit and TRQ bit should not be set at the same time.
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CHAPTER 15 CAN CONTROLLER
Figure 15-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000B).
Figure 15-41. Message Transmit Processing (Normal Operation Mode with ABT)
START
No
ABTTRG = 0?
Yes
Clear RDY bit
CnMCTRLm.SET_RDY = 0
CnMCTRLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Set CnMDATAxm register
Set CnMDLCm register
Clear RTR bit of CnMCONFm
register
Set CnMIDLm and CnMIDHm
registers
Set RDY bit
CnMCTRLm.SET_RDY = 1
CnMCTRLm.CLEAR_RDY = 0
No
Set all ABT transmit messages?
Yes
No
TSTAT = 0?
Yes
Set ABTTRG bit
CnGMABT.SET_ABTTRG = 1
CnGMABT.CLEAR_ABTTRG = 0
END
Remark This processing (normal operation mode with ABT) can only be applied to message buffers 0 to 7.
For message buffers other than the ABT message buffers, refer to Figure 15-40.
Caution Set (1) ABTTRG bit after TSTAT bit is clear (0) check TSTAT bit and set ABTTRG bit, must be
processing successively.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Figure 15-42. Transmission via Interrupt (Using CnLOPT register)
START
Transmit completion
interrupt processing
Read CnLOPT register
Clear RDY bit
CnMCRTLm.SET_RDY = 0
CnMCRTLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Data frame
Remote frame
Data frame or remote frame?
Set CnMDATAxm register
Set CnMDLCm register
Set RTR bit of CnMCONFm
register.
Set CnMIDLm and CnMIDHm
registers
Set CnMDLCm register,
Clear RTR bit of CnMCONFm
register.
Set CnMIDLm and CnMIDHm
registers
Set RDY bit
CnMCRTLm.SET_RDY = 1
CnMCRTLm.CLEAR_RDY = 0
Set TRQ bit
CnMCRTLm.SET_TRQ = 1
CnMCRTLm.CLEAR_TRQ = 0
END
Caution The TRQ bit should be set after the RDY bit is set.
The RDY bit and TRQ bit should not be set at the same time.
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CHAPTER 15 CAN CONTROLLER
Figure 15-43. Transmission via Interrupt (Using CnTGPT Register)
START
Transmit completion
interrupt processing
Read CnTGPT register
TOVF = 1?
No
Yes
Clear TOVF bit
CnTGPT.CLEAR_TOVF = 1
Clear RDY bit
CnMCRTLm.SET_RDY = 0
CnMCRTLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Data frame
Remote frame
Data frame or remote frame?
Set CnMDATAxm register
Set CnMDLCm register
Set CnMDLCm register
Set RTR bit of CnMCONFm
Clear RTR bit of CnMCONFm
register
register
Set CnMIDLm and CnMIDHm
Set CnMIDLm and CnMIDHm
registers
registers
Set RDY bit
CnMCRTLm.SET_RDY = 1
CnMCRTLm.CLEAR_RDY = 0
Set TRQ bit
CnMCRTLm.SET_TRQ = 1
CnMCRTLm.CLEAR_TRQ = 0
No
THPM = 1?
Yes
END
Caution The TRQ bit should be set after the RDY bit is set.
The RDY bit and TRQ bit should not be set at the same time.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Figure 15-44. Transmission via Software Polling
START
No
CINTS0 = 1?
Yes
Clear CINTS0 bit
CnINTS.CLEAR_CINTS0 = 1
Read CnTGPT register
No
TOVF = 1?
Yes
Clear TOVF bit
CnTGPT.CLEAR_TOVF bit = 1
Clear RDY bit
CnMCTRLm.SET_RDY = 0
CnMCTRLm.CLEAR_RDY = 1
No
RDY = 0?
Yes
Data frame
Remote frame
Data frame or
remote frame?
Set CnMDATAxm register
Set CnMDLCm register
Clear RTR bit of CnMCONFm
register.
Set CnMIDLm and CnMIDHm
registers
Set CnMDLCm register
Set RTR bit of CnMCONFm
Set CnMIDLm and CnMIDHm
registers
Set RDY bit
CnMCTRLm.SET_RDY = 1
CnMCTRLm.CLEAR_RDY = 0
Set TRQ bit
CnMCTRLm.SET_TRQ = 1
CnMCTRLm.CLEAR_TRQ = 0
No
THPM = 1?
Yes
END
Caution The TRQ bit should be set after the RDY bit is set.
The RDY bit and TRQ bit should not be set at the same time.
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CHAPTER 15 CAN CONTROLLER
Figure 15-45. Transmission Abort Processing (except Normal Operation Mode with ABT)
START
Clear TRQ bit
CnMCTRLm.SET_TRQ = 0
CnMCTRLm.CLEAR_TRQ = 1
Wait for 11 CAN data bits
No
TSTAT = 0?
Yes
Read CnLOPT register
Message buffer to
No
be aborted matches CnLOPT
register?
Yes
Transmit abort request
was successful
Transmission successful
END
Cautions 1. Execute transmission request abort processing by clearing the TRQ bit, not the RDY bit.
2. Before making a sleep mode transition request, confirm that there is no transmission
request left using this processing.
3. The TSTAT bit can be periodically checked by a user application.
4. In the aborting the transmission progressing, do not make a new transmission request
including other message buffer.
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CHAPTER 15 CAN CONTROLLER
In the normal operation with ABT, to abort transmit except transmission with ABT, using this processing flow.
Figure 15-46. Transmission Abort Processing Except for ABT Transmission
(Normal Operation Mode with ABT)
START
Clear ABTTRG bit
CnGMABT.SET_ABTTRG = 0
CnGMABT.CLEAR_ABTTRG = 1
No
ABTTRG = 0?
Yes
Clear TRQ bit
CnMCTRLm.SET_TRQ = 0
CnMCTRLm.CLEAR_TRQ = 1
Wait for 11 CAN data bits
No
TSTAT = 0?
Yes
Read CnLOPT register
Message buffer to
No
be aborted matches CnLOPT
register?
Yes
Transmit abort request
was successful
Transmission successful
END
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CHAPTER 15 CAN CONTROLLER
Figure 15-47 (a) shows the processing to skip resumption of transmitting a message that was stopped when
transmission of an ABT message buffer was aborted.
Figure 15-47. (a) Transmission Abort Processing (Normal Operation Mode with ABT)
START
Clear ABTTRG bit.
Set ABTTRG bit = 0
Clear ABTTRG bit = 1
No
ABTTRG = 0?
Yes
Clear TRQ bit of message
buffer whose transmission
was aborted.
Transmit abort
No
Transmission start
pointer clear?
Yes
Set ABTCLR bit.
Set ABTCLR bit = 1
Clear ABTTRG bit = 0
END
Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in
progress.
2. Make a CAN sleep mode/CAN stop mode transition request after ABTTRG is cleared
following the procedure shown in Figure 15-47 (a) or (b). When clearing a transmission
request in an area other than the ABT area, follow the procedure shown in Figure 15-46.
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Figure 15-47 (b) shows the processing to not skip resumption of transmitting a message that was stopped when
transmission of an ABT message buffer was aborted.
Figure 15-47. (b) Transmission Request Abort Processing (Normal Operation Mode with ABT)
START
Clear TRQ bit of message buffer
undergoing transmission.
Clear ABTTRG bit.
Set ABTTRG bit = 0
Clear ABTTRG bit = 1
No
ABTTRG = 0?
Yes
Transmit abort
No
Transmission start
pointer clear?
Yes
Set ABTCLR bit.
Set ABTCLR bit = 1
Clear ABTTRG bit = 0
END
Cautions 1. Do not set any transmission requests while ABT transmission abort processing is in
progress.
2. Make a CAN sleep mode/CAN stop mode request after ABTTRG is cleared following the
procedure shown in Figure 15-47 (a) or (b). When clearing a transmission request in an
area other than the ABT area, follow the procedure shown in Figure 15-46.
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CHAPTER 15 CAN CONTROLLER
Figure 15-48. Reception via Interrupt (Using CnLIPT Register)
START
Transmit abort
Read CnLIPT register.
Clear DN bit.
Clear DN bit = 1
Read CnMDATAxm, CnMDLCm,
CnMIDLm, and CnMIDHm
registers.
No
DN = 0 and
MUC = 0Note
Yes
Clear CINTS1 bit.
Clear CINTS1 bit = 1
END
Note Check the MUC and DN bits using one read access.
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CHAPTER 15 CAN CONTROLLER
Figure 15-49. Reception via Interrupt (Using CnRGPT Register)
START
Receive completion interrupt
Read CnRGPT register
No
ROVF = 1?
Yes
Clear ROVF bit
CnRGPT.Clear ROVF bit = 1
Yes
RHPM = 1?
No
Clear DN bit
CnMCTRLm.Clear DN bit = 1
Read CnMDATAxm,
CnMDLCm, CnMIDLm,
CnMIDHm registers
DN = 0
No
AND
MUC = 0Note
Yes
Read of illegal data
Read of normal data
END
Note Check the MUC and DN bits using one read access.
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CHAPTER 15 CAN CONTROLLER
Figure 15-50. Reception via Software Polling
START
No
CINTS1 = 1?
Yes
Clear CINTS1 bit
CnINTS.Clear CINTS1 bit = 1
Read CnRGPT register
No
ROVF = 1?
Yes
Clear ROVF bit
CnRGPT.Clear ROVF bit = 1
Yes
RHPM = 1?
No
Clear DN bit
CnMCTRLm.Clear DN bit = 1
Read CnMDATAxm,
CnMDLCm, CnMIDLm,
CnMIDHm registers
DN = 0
No
AND
MUC = 0Note
Yes
Read of illegal data
Read of normal data
END
Note Check the MUC and DN bits using one read access.
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CHAPTER 15 CAN CONTROLLER
Figure 15-51. Setting CAN Sleep Mode/Stop Mode
START (when PSMODE[1:0] = 00B)
Set PSMODE0 bit
CnCTRL.SET_PSMODE1 = 1
CnCTRL.CLEAR_PSMODE1 = 0
No
PSMODE0 = 1?
Yes
CAN sleep mode
Set PSMODE1 bit
CnCTRL.SET_PSMODE1 = 1
CnCTRL.CLEAR_PSMODE1 = 0
PSMODE1 = 1?
No
Yes
Yes
Request CAN sleep
mode again?
CAN stop mode
No
END
Clear OPMODE
INIT mode?
No
Yes
Access to registers other than the
CnCTRL and CnGMCTRL registers
Set CnCTRL register
(Set OPMODE)
Clear CINTS5 bit
CnINTS.CLEAR_CINTS5 = 1
Caution To abort transmission before making a request for the CAN sleep mode, perform
processing according to Figures 15-46 and 15-47.
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CHAPTER 15 CAN CONTROLLER
Figure 15-52. Clear CAN Sleep/Stop Mode
START
CAN stop mode
Clear PSMODE1 bit.
Set PSMODE1 bit = 0
Clear PSMODE1 bit = 1
Releasing CAN sleep mode
by CAN bus active
CAN sleep mode
Releasing CAN sleep mode
by user
Bus activity = 0
PSMODE0 = 0
CINTS5 = 1
Clear PSMODE0 bit.
Set PSMODE0 bit = 0
Clear PSMODE0 bit = 1
Clear CINTS5 bit.
Clear CINTS5 bit = 1
END
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CHAPTER 15 CAN CONTROLLER
Figure 15-53. Bus-Off Recovery
START
No
BOFF = 1?
Yes
Clear all TRQ bits
Set CnCTRL register
(Clear OPMODE)
Access to register other than
CnCTRL and CnGMCTRL
registers
No
Forced recovery
from bus off?
Yes
Set CCERC bit
CnCTRL.SET_CCERC bit = 1
Set CnCTRL register
(Set OPMODE)
Set CnCTRL register
(Set OPMODE)
Wait for recorvery
From bus off
END
User’s Manual U17830EE1V0UM00
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CHAPTER 15 CAN CONTROLLER
Figure 15-54. Normal Shutdown Process
START
IINIT mode
Clear GOM bit.
Set GOM bit = 0
Clear GOM bit = 1
No
GOM = 0?
Yes
Shutdown successful
GOM = 0, EFSD = 0
END
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CHAPTER 15 CAN CONTROLLER
Figure 15-55. Forced Shutdown Process
START
Set EFSD bit.
Set EFSD bit = 1
Must be a continuous write.
Clear GOM bit.
Set GOM bit = 0
Clear GOM bit = 1
No
GOM = 0?
Yes
Shutdown successful
GOM = 0, EFSD = 0
END
Caution Do not read- or write-access any registers by software between setting the EFSD bit and
clearing the GOM bit.
Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-
shot mode, self-test mode
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CHAPTER 15 CAN CONTROLLER
Figure 15-56. Error Handling
START
Error interrupt
No
CINTS2 = 1?
Yes
Check CAN module state.
(read CnINFO register)
Clear CINTS2 bit.
Clear CINTS2 bit = 1
No
CINTS3 = 1?
Yes
No
CINTS4 = 1?
Yes
Check CAN protocol error state.
(Read CnLEC register)
Clear CINTS4 bit.
Clear CINTS4 bit = 1
Clear CINTS3 bit.
Clear CINTS3 bit = 1
END
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CHAPTER 15 CAN CONTROLLER
Figure 15-57. Setting CPU Standby (from CAN Sleep Mode)
START
Set PSMODE0 bit.
CnCTRL.SET_PSMODE0 = 1
CnCTRL.CLEAR_PSMODE0 = 0
No
PSMODE0 bit = 1?
Yes
CAN sleep mode
Enable interrupts.
Disable interrupts.
No
PSMODE[1:0] bits = 01B?
Yes
Set CPU standby mode.
END
Caution Check the CAN sleep mode or not, before CPU is set to standby mode. Otherwise, until CPU
is set to standby mode, CAN sleep mode may be released by wake-up.
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CHAPTER 15 CAN CONTROLLER
Figure 15-58. Setting CPU Standby (from CAN Stop Mode)
START
Set PSMODE0 bit.
Set PSMODE0 bit = 1
Clear PSMODE0 bit = 0
No
PSMODE0 bit = 1?
Clear CINTS5 bit.
Clear CINTS5 bit = 1Note
Yes
CAN sleep mode
Set PSMODE1 bit.
Set PSMODE1 bit = 1
Clear PSMODE1 bit = 0
No
PSMODE1 bit = 1?
Yes
CAN stop mode
No
PSMODE[1:0] = 11?
Yes
Set CPU standby mode.
END
Note During wakeup interrupts
Caution The CAN stop mode can only be released by writing 01 to the CnCTRL.PSMODE1 and
CnCTRL.PSMODE0 bits. H cannot be released by changing the CAN bus.
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CHAPTER 16 DMA FUNCTION (DMA CONTROLLER)
The V850ES/FG2 and V850ES/FJ2 include a direct memory access (DMA) controller (DMAC) that executes and
controls DMA transfer. The V850ES/FE2 and V850ES/FF2 do not include a direct memory access (DMA) controller.
The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA
requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from
external input pins, or software triggers (memory refers to internal RAM or external memory).
16.1 Features
• 4 independent DMA channels
• Transfer unit: 8/16 bits
• Maximum transfer count: 65,536 (216)
• Transfer type: Two-cycle transfer
• Transfer mode: Single transfer mode
• Transfer requests
• Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts
from external input pin
• Requests by software trigger
• Transfer targets
• Internal RAM ↔ Peripheral I/O
• Peripheral I/O ↔ Peripheral I/O
• Internal RAM ↔ External memory
• External memory ↔ Peripheral I/O
• External memory ↔ External memory
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CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
Figure 16-1. Block Diagram of DMA Controller
16.2 Configuration
On-chip
Internal RAM
peripheral I/O
Internal bus
On-chip peripheral I/O bus
CPU
DMA source address
register n (DSAnH/DSAnL)
Data
control
Address
control
DMA destination address
register n (DDAnH/DDAnL)
DMA transfer count
register n (DBCn)
Count
control
DMA channel control
register n (DCHCn)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
Channel
control
DMAC
Bus interface
External bus
V850ES/SJ2
External
RAM
External
ROM
External I/O
Remark n = 0 to 3
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CHAPTER 16 DMA FUNCTION (DMA CONTROLLER)
16.3 Registers
(1) DMA source address registers 0 to 3 (DSA0 to DSA3)
The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DSAnH and DSAnL.
These registers can be read or written in 16-bit units.
After reset: Undefined
R/W
Address: DSA0H FFFFF082H, DSA1H FFFFF08AH,
DSA2H FFFFF092H, DSA3H FFFFF09AH,
DSA0L FFFFF080H, DSA1L FFFFF088H,
DSA2L FFFFF090H, DSA3L FFFFF098H
DSAnH
(n = 0 to 3)
IR
0
0
0
0
0
SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
DSAnL
(n = 0 to 3)
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
IR
0
Specification of DMA transfer source
External memory or on-chip peripheral I/O
Internal RAM
1
SA25 to SA16 Set the address (A25 to A16) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
SA15 to SA0 Set the address (A15 to A0) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0.
2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are
read. If reading and updating conflict, the value being updated may be read (see 16.13
Cautions).
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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(2) DMA destination address registers 0 to 3 (DDA0 to DDA3)
The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DDAnH and DDAnL.
These registers can be read or written in 16-bit units.
After reset: Undefined
R/W
Address: DDA0H FFFFF086H, DDA1H FFFFF08EH,
DDA2H FFFFF096H, DDA3H FFFFF09EH,
DDA0L FFFFF084H, DDA1L FFFFF08CH,
DDA2L FFFFF094H, DDA3L FFFFF09CH
DDAnH
(n = 0 to 3)
IR
0
0
0
0
0
DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
DDAnL
(n = 0 to 3)
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
IR
0
Specification of DMA transfer destination
External memory or on-chip peripheral I/O
Internal RAM
1
DA25 to DA16 Set an address (A25 to A16) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
DA15 to DA0 Set an address (A15 to A0) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0.
2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are
read. If reading and updating conflict, a value being updated may be read (see 16.13
Cautions).
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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CHAPTER 16 DMA FUNCTION (DMA CONTROLLER)
(3) DMA byte count registers 0 to 3 (DBC0 to DBC3)
The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3).
These registers hold the remaining transfer count during DMA transfer.
These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the
transfer is terminated if a borrow occurs.
These registers can be read or written in 16-bit units.
After reset: Undefined
R/W
Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H,
DBC2 FFFFF0C4H, DBC3 FFFFF0C6H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DBCn
(n = 0 to 3)
BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
BC15 to
BC0
Byte transfer count setting or remaining
byte transfer count during DMA transfer
0000H
0001H
:
Byte transfer count 1 or remaining byte transfer count
Byte transfer count 2 or remaining byte transfer count
:
Byte transfer count 65,536 (216) or remaining byte transfer count
FFFFH
The number of transfer data set first is held when DMA transfer is complete.
Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
(4) DMA addressing control registers 0 to 3 (DADC0 to DADC3)
The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n
= 0 to 3).
These registers can be read or written in 16-bit units.
Reset sets these registers to 0000H.
After reset: 0000H
R/W
Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H,
DADC2 FFFFF0D4H, DADC3 FFFFF0D6H
15
14
13
0
12
0
11
0
10
0
9
8
DADCn
(n = 0 to 3)
0
DS0
0
0
7
6
5
4
3
2
1
0
SAD1
SAD0
DAD1
DAD0
0
0
0
0
Setting of transfer data size
DS0
0
8 bits
1
16 bits
SAD1
SAD0
Setting of count direction of the transfer source address
Increment
0
0
1
1
0
1
0
1
Decrement
Fixed
Setting prohibited
DAD1
DAD0
Setting of count direction of the destination address
0
0
1
1
0
1
0
1
Increment
Decrement
Fixed
Setting prohibited
Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to 0.
2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit
data (DS0 bit = 0) is set, therefore, the lower data bus is not always used.
4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an
odd address. Transfer is always started from an address with the first bit of the lower
address aligned to 0.
5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or
destination), be sure to specify the same transfer size as the register size. For example, to
execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer.
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CHAPTER 16 DMA FUNCTION (DMA CONTROLLER)
(5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA
channel n.
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are
write-only. If bit 1 or 2 is read, the read value is always 0.)
Reset sets these registers to 00H.
After reset: 00H
R/W
Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
7
6
5
4
3
2
1
0
DCHCn
(n = 0 to 3)
TCnNote 1
0
0
0
0
INITnNote 2 STGnNote 2
Enn
TCn
Status flag indicates whether DMA transfer through DMA
channel n has completed or not
0
1
DMA transfer had not completed.
DMA transfer had completed.
It is set to 1 on the last DMA transfer completed and cleared to 0 when it is read.
If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0),
the DMA transfer status can be initialized. When re-setting the DMA
transfer status (re-setting the DDAnH, DDAnL, DSAnH, DSAnL, DBCn,
and DADCn registers) before DMA transfer is completed (before the
TCn bit is set to 1), be sure to initialize the DMA channel.
When initializing the DMA controller, however, be sure to observe the
procedure described in 16.11 Cautions.
INITn
Set the INIT bit to 1 when the Enn bit = 0.
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
STGn
Enn
Setting of whether DMA transfer through
DMA channel n is to be enabled or disabled
0
1
DMA transfer disabled
DMA transfer enabled
DMA transfer is enabled when the Enn bit is set to 1.
When DMA transfer is completed (when a terminal count is generated), this bit is
automatically cleared to 0. To abort DMA transfer, clear the Enn bit to 0 by software.
To resume, set the Enn bit to 1 again. When aborting or resuming DMA transfer,
however, be sure to observe the procedure described in 16.11 Cautions.
Notes 1. The TCn bit is read-only.
2. The INITn and STGn bits are write-only.
Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to 0.
2. Before generating a DMA transfer request by software, make sure that the TCn bit is set to
1 and then clear the TCn bit to 0.
3. If the INIT bit setting and the DMA transfer of another channel conflict, initialization may
not perform.
4. When DMA transfer is completed (when a terminal count is generated), the Enn bit is
cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are
being updated, a value indicating “transfer not completed and transfer is disabled” (TCn bit
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CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
= 0 and Enn bit = 0) may be read.
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CHAPTER 16 DMA FUNCTION (DMA CONTROLLER)
(6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt
request signals from on-chip peripheral I/O.
The interrupt request signals set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
Reset sets these registers to 00H.
After reset: 00H
R/W
Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H,
DTFR2 FFFFF814H, DTFR3 FFFFF816H
<7>
6
5
4
3
2
1
0
DTFRn
(n = 0 to 3)
DFn
0
IFCn5
IFCn4
IFCn3
IFCn2
IFCn1
IFCn0
DFnNote
DMA transfer request flag
0
1
No DMA transfer request
DMA transfer request
Note The DFn bit is a write-only bit. Write 0 to this bit to clear a DMA transfer request if an interrupt that is
specified as the cause of starting DMA transfer occurs while DMA transfer is disabled.
Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
2. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
3. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA
transfer is enabled or disabled. If DMA is enabled in this status, DMA transfer is
immediately started.
4. The number of supported DMA start factors differs depending on the product as shown in
Table 16-1. For details of the IFCn5 to IFCn0 bits, see Table 16-2 DMA Start Factors.
Table 16-1. Number of DMA Start Factors in Each Product
Part Number
Number of DMA Start Factors
Range of IFCn5 to IFCn0Note
µ PD70F3237
µ PD70F3238
µ PD70F3239
59
63
63
000000B to 111011B (INTLVI to INTCB2T)
000000B to 111111B (INTLVI to INTC3TRX)
000000B to 111111B (INTLVI to INTC3TRX)
Note Setting a value other than the value shown in the range of IFCn5 to IFCn0 is prohibited.
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Table 16-2. DMA Start Factors (1/2)
IFCn5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IFCn4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
IFCn3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
IFCn2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IFCn1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IFCn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Source
DMA request by interrupt disabled
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
INTTQ0OV
INTTQ0CC0
INTTQ0CC1
INTTQ0CC2
INTTQ0CC3
INTTP0OV
INTTP0CC0
INTTP0CC1
INTTP1OV
INTTP1CC0
INTTP1CC1
INTTP2OV
INTTP2CC0
INTTP2CC1
INTTP3OV
INTTP3CC0
INTTP3CC1
INTTM0EQ0
INTCB0R
INTCB0T
INTCB1R
INTCB1T
INTUA0R
INTUA0T
INTUA1R
INTUA1T
INTAD
INTC0ERR
INTC0WUP
INTC0REC
Remark n = 0 to 3
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Table 16-2. DMA Start Factors (2/2)
IFCn5
IFCn4
IFCn3
IFCn2
IFCn1
IFCn0
Interrupt Source
INTC0TRX
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
INTKR
INTTQ1OV
INTTQ1CC0
INTTQ1CC1
INTTQ1CC2
INTTQ1CC3
INTUA2R
INTUA2T
INTC1ERR
INTC1EWUP
INTC1REC
INTC1TRX
INTTQ2OV
INTTQ2CC0
INTTQ2CC1
INTTQ2CC2
INTTQ2CC3
INTCB2R
1
1
1
1
1
1
1
1
1
1
1
1
1
INTCB2T
INTC2RECNote
INTC2TRXNote
INTC3RECNote
INTC3TRXNote
Note µPD70F3238 and µPD70F3239 only
Remark n = 0 to 3
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16.4 DMA Bus States
16.4.1 Types of bus states
The DMAC bus states consist of the following 10 states.
(1) TI state
The TI state is an idle state, during which no access request is issued.
The DMA request signals are sampled at the rising edge of the CLKOUT signal.
(2) T0 state
DMA transfer ready state (state in which a DMA transfer request has been issued and the bus mastership is
acquired for the first DMA transfer).
(3) T1R state
The bus enters the T1R state at the beginning of a read operation in two-cycle transfer.
Address driving starts. After entering the T1R state, the bus enters the T2R state.
(4) T1RI state
The T1RI state is a state in which the bus waits for the acknowledge signal corresponding to an external
memory read request.
After entering the last T1RI state, the bus invariably enters the T2R state.
(5) T2R state
The T2R state corresponds to the last state of a read operation in two-cycle transfer, or to a wait state.
In the last T2R state, read data is sampled. After entering the last T2R state, the bus enters the T1W state or
T2RI state.
(6) T2RI state
State in which the bus is ready for DMA transfer to on-chip peripheral I/O or internal RAM (state in which the
bus mastership is acquired for DMA transfer to on-chip peripheral I/O or internal RAM).
After entering the last T2RI state, the bus invariably enters the T1W state.
(7) T1W state
The bus enters the T1W state at the beginning of a write operation in two-cycle transfer.
Address driving starts. After entering the T1W state, the bus enters the T2W state.
(8) T1WI state
State in which the bus waits for the acknowledge signal corresponding to an external memory write request.
After entering the last T1WI state, the bus invariably enters the T2W state.
(9) T2W state
The T2W state corresponds to the last state of a write operation in two-cycle transfer, or to a wait state.
In the last T2W state, the write strobe signal is made inactive.
(10) TE state
The TE state corresponds to DMA transfer completion. The DMAC generates the internal DMA transfer
completion signal and various internal signals are initialized. After entering the TE state, the bus invariably
enters the TI state.
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16.4.2 DMAC bus cycle state transition
Each time the processing for a DMA transfer is completed, the bus mastership is released.
Figure 16-2. DMAC Bus Cycle State Transition
TI
T0
T1R
T1RI
T2R
T1W
T2RI
T1WI
T2W
TE
TI
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16.5 Transfer Targets
Table 16-3 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled).
Table 16-3. Relationship Between Transfer Targets
Transfer Destination
Internal ROM
On-Chip
Internal RAM
External Memory
Peripheral I/O
On-chip peripheral I/O
Internal RAM
×
×
×
×
√
√
√
×
√
×
√
×
√
√
√
×
External memory
Internal ROM
Caution The operation is not guaranteed for combinations of transfer destination and source marked with
“×” in Table 16-3.
16.6 Transfer Modes
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
request, transfer is performed again once. This operation continues until a terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
DMA request always takes precedence.
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released
to the CPU (the new transfer request of the same channel is ignored in the transfer cycle).
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16.7 Transfer Types
As a transfer type, the 2-cycle transfer is supported.
In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle.
In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In
the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs
between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows.
<16-bit data transfer>
<1> Transfer from 32-bit bus → 16-bit bus
A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a
write cycle (16 bits).
<2> Transfer from 16-/32-bit bus to 8-bit bus
A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice.
<3> Transfer from 8-bit bus to 16-/32-bit bus
An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once.
<4> Transfer between 16-bit bus and 32-bit bus
A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once.
For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the
same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8-
bit) transfer.
Remark The bus width of each transfer target (transfer source/destination) is as follows.
• On-chip peripheral I/O: 16-bit bus width
• Internal RAM:
32-bit bus width
• External memory:
8-bit or 16-bit bus width
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16.8 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
The priorities are checked for every transfer cycle.
16.9 Time Related to DMA Transfer
The time required responding to a DMA request, and the minimum number of clocks required for DMA transfer are
shown below.
1
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note + Transfer
destination memory access (<2>)
DMA Cycle
Minimum Number of Execution Clocks
4 clocks (MIN.) + Noise elimination timeNote 2
Depends on connected memory.
<1> DMA request response time
<2> Memory access
External memory access
Internal RAM access
2 clocksNote 3
Peripheral I/O register access
3 clocks + Number of wait cycles specified by VSWC registerNote 4
Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer.
2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is
added (n = 0 to 7).
3. Two clocks are required for a DMA cycle.
4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.10
(2)).
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16.10DMA Transfer Start Factors
There are two types of DMA transfer start factors, as shown below.
(1) Request by software
If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer
is started.
To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the
preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3).
TCn bit = 0, Enn bit = 1
↓
STGn bit = 1 … Starts the first DMA transfer.
↓
Confirm that the contents of the DBCn register have been updated.
STGn bit = 1 … Starts the second DMA transfer.
↓
:
↓
Generation of terminal count … Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated.
(2) Request by on-chip peripheral I/O
If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the
DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA
channel. If two start factors are simultaneously generated for one DMA channel, only one
of them is valid. The start factor that is valid cannot be identified.
2. A new transfer request that is generated after the preceding DMA transfer request was
generated or in the preceding DMA transfer cycle is ignored (cleared).
3. The transfer request interval of the same DMA channel varies depending on the setting of
bus wait in the DMA transfer cycle, the start status of the other channels, or the external
bus hold request. In particular, as described in Caution 2, a new transfer request that is
generated for the same channel before the DMA transfer cycle or during the DMA transfer
cycle is ignored. Therefore, the transfer request intervals for the same DMA channel must
be sufficiently separated by the system. When the software trigger is used, completion of
the DMA transfer cycle that was generated before can be checked by updating the DBCn
register.
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16.11 DMA Abort Factors
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal
memory/on-chip peripheral I/O.
When the bus hold is cleared, DMA transfer is resumed.
16.12 End of DMATransfer
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn
bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the
interrupt controller (INTC) (n = 0 to 3).
The V850ES/FG2 and V850ES/FJ2 do not output a terminal count signal to an external device. Therefore, confirm
completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
16.13 Operation Timing
Figures 16-3 to 16-6 show DMA operation timing.
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Figure 16-5. Period in Which DMATransfer Request Is Ignored (1)
System clock
DMAn transfer
requestNote 1
DFn bit
Note 2
Note 2
Note 2
CPU processing
DMA0 processing
CPU processing
Mode of processing
End
processing
Preparation
for transfer
Read cycle
Write cycle
Idle
DMA transfer
Transfer request generated
after this can be acknowledged
Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit)
2. New DMA request of the same channel is ignored between when the first request is generated and
the end processing is complete.
Remark In the case of transfer between external memory spaces (multiplexed bus, no wait)
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16.14 Cautions
(1) Caution for VSWC register
When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the
VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC
register, the operation is not correctly performed (for details of the VSWC register, see 3.4.10 (1) (a) System
wait control register (VSWC)).
(2) Caution for DMA transfer executed on internal RAM
When executing the following instructions located in the internal RAM, do not execute a DMA transfer that
transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate
correctly afterward.
• Bit manipulation instruction located in internal RAM (SET1, CLR1, or NOT1)
• Data access instruction to misaligned address located in internal RAM
Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer
source/destination), do not execute the above two instructions.
(3) Caution for reading DCHCn.TCn bit (n = 0 to 3)
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific
timing. To accurately clear the TCn bit, add the following processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more
times.
(b) When reading TCn bit in interrupt servicing routine
Execute reading the TCn bit three times.
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(4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1)
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may
not be initialized. To accurately initialize the channel, execute either of the following two procedures.
(a) Temporarily stop transfer of all DMA channels
Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other
processing programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer
the value to a general-purpose register.
<3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To
clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA
transfer (transfer source/destination) is the internal RAM, execute the instruction three times.
Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of
transfer is not the internal RAM).
• Clear DCHC0.E00 bit to 0.
• Clear DCHC1.E11 bit to 0.
• Clear DCHC2.E22 bit to 0.
• Clear DCHC2.E22 bit to 0 again.
<4> Set the INITn bit of the channel to be forcibly terminated to 1.
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit
read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0.
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels
whose DMA transfer has been normally completed between <2> and <3>.
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(b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly
<1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop
operation of the on-chip peripheral I/O).
<2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by
using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the
pending request is completed.
<3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held
pending, clear the Enn bit to 0.
<4> Again, clear the Enn bit of the channel to be forcibly terminated.
If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the
internal RAM, execute this operation once more.
<5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose
register.
<6> Set the INITn bit of the channel to be forcibly terminated to 1.
<7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the
value copied in <5>. If the two values do not match, repeat operations <6> and <7>.
Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if
forced termination has been correctly completed. If not, the remaining number of transfers
is read.
2. Note that method (b) may take a long time if the application frequently uses DMA transfer for
a channel other than the DMA channel to be forcibly terminated.
(5) Procedure of temporarily stopping DMA transfer (clearing Enn bit)
Stop and resume the DMA transfer under execution using the following procedure.
<1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral
I/O).
<2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0).
If a request is pending, wait until execution of the pending DMA transfer request is completed.
<3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this
operation stops DMA transfer).
<4> Set the Enn bit to 1 to resume DMA transfer.
<5> Resume the operation of the DMA request source that has been stopped (start the operation of the on-
chip peripheral I/O).
(6) Memory boundary
The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the
DMA target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
(7) Transferring misaligned data
DMA transfer of misaligned data with a 16-bit bus width is not supported.
If an odd address is specified as the transfer source or destination, the least significant bit of the address is
forcibly assumed to be 0.
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(8) Bus arbitration for CPU
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the
CPU.
However, the CPU can access the external memory, on-chip peripheral I/O, and internal RAM to/from which
DMA transfer is not being executed.
• The CPU can access the internal RAM when DMA transfer is being executed between the external memory
and on-chip peripheral I/O.
• The CPU can access the internal RAM and on-chip peripheral I/O when DMA transfer is being executed
between the external memory and external memory.
(9) Registers/bits that must not be rewritten during DMA operation
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
[Timing of setting]
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
(10) Be sure to set the following register bits to 0.
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
(11) DMA start factor
Do not start two or more DMA channels with the same start factor. If two or more channels are started with
the same factor, a DMA channel with a lower priority may be acknowledged earlier than a DMA channel with a
higher priority.
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(12) Read values of DSAn and DDAn registers
Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0
to 3).
For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source
address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and
DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA
transfer is executed immediately after the DSAnH register is read.
(a) If DMA transfer does not occur while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Read value of DSAnL register: DSAnL = FFFFH
(b) If DMA transfer occurs while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00100000H
<4> Read value of DSAnL register: DSAnL = 0000H
(13) DMA trigger Change
When the interrupt request signal selection in the DTFR register is changed and the original interrupt request
selection is also the selection for another DMA channel, there is the possibility that a DMA transfer will
inadvertently occur.
When the setting of DTFRn register is changed, please make sure to follow the procedure shown below:
(a). In the case that the desired setting of the IFC is NOT set to a different DMA channel
<1> DMA operation of target channel, which is re-written, should be stopped (DCHCn.Enn=0)
<2> Change the setting of DTFRn register (By 8 bit operation)
<3> Confirm DTFRn.DFn=0 (The operation of the interrupt generation factor should be stopped
previously)
<4> DMA operation can be enabled (DCHCn.Enn=1)
(b). In the case that the desired setting of the IFC (DMAn) IS set to another DMA channel (DMAm)
<1> DMA operation of target channel, (DMAn) which is re-written, should be stopped (DCHCn.Enn=0).
<2> DMA operation of the channel, which has the same value for the IFCm5-0bits, should be stopped
(DCHCm.Emm=0).
<3> Change the setting of DTFRn register (By 8 bit operation)
<4> Confirm DTFRn.DFn=0 and DTFRm.DFm=0 (The operation of the interrupt generation factor should
be stopped previously)
<5> DMA operation can be enabled (DCHCn.Enn=1 and DCHCm.Enn=1)
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Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
The V850ES/Fx2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing.
An interrupt is an event that occurs independently of program execution, and an exception is an event whose
occurrence is dependent on program execution.
The V850ES/Fx2 can process interrupt request signals from the on-chip peripheral hardware and external sources.
Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an
exception event (i.e. fetching of an illegal opcode) (exception trap).
The number of supported maskable interrupt sources differs depending on the product, as shown in Table 17-1.
Table 17-1. Number of Maskable Interrupt Sources
Part Number
Number of Maskable
Interrupt Sources
Maskable InterruptsNote
V850ES/FE2
V850ES/FF2
V850ES/FG2
V850ES/FJ2
43
INTLVI to INTWT
61
72
82
INTLVI to INTMA3
INTLVI to INTCB2T
INTLVI to INTC3TRX
µ PD70F3237
µ PD70F3238, 70F3239
Note Refer to Table 17-2 for the maskable interrupts.
Caution The explanations in this chapter use the maximum of 82 maskable interrupt sources.
17.1 Features
Interrupts
• Non-maskable interrupts: 2 sources
• Maskable interrupts:
External: 15, Internal: 67 sources (Number of sources varies depending on the
product.)
• 8 levels of programmable priorities (maskable interrupts)
• Multiple interrupt control according to priority
• Masks can be specified for each maskable interrupt request
• Noise elimination, edge detection, and valid edge specification for external interrupt request signals
Exceptions
• Software exceptions: 32 sources
• Exception trap:
2 sources (illegal opcode exception, debug trap)
The interrupt/exception sources are listed in Table 17-2.
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Table 17-2. Interrupt Source List (1/3)
Type
Classification Default
Priority
Name
Trigger
Generating Exception
Handler
Address
Restored
PC
Interrupt
Control
Unit
Code
Register
Reset
Interrupt
Interrupt
−
RESET
RESET pin input
RESET
0000H
00000000H
Undefined
−
Reset input by internal source
Non-
−
−
−
−
−
NMI
NMI pin valid edge input
Pin
0010H
0020H
004nHNote 2 00000040H
005nHNote 2 00000050H
00000010H
00000020H
nextPC
nextPC Note 1
−
−
−
−
−
maskable
INTWDT2
WDT2 overflow
WDT2
Software Exception
exception
TRAP0nNote 2 TRAP instruction
TRAP1nNote 2 TRAP instruction
−
−
−
nextPC
nextPC
Exception Exception
trap
ILGOP/
DBG0
Illegal opcode/
0060H
00000060H
nextPC
DBTRAP instruction
Maskable Interrupt
0
1
INTLVI
INTP0
Low voltage detection
POCLVI
Pin
0080H
0090H
00000080H
00000090H
nextPC
nextPC
LVIIC
External interrupt pin input
edge detection (INTP0)
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PIC7
2
3
4
5
6
7
8
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
External interrupt pin input
edge detection (INTP1)
Pin
00A0H
00B0H
00C0H
00D0H
00E0H
00F0H
0100H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000100H
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
External interrupt pin input
edge detection (INTP2)
Pin
External interrupt pin input
edge detection (INTP3)
Pin
External interrupt pin input
edge detection (INTP4)
Pin
External interrupt pin input
edge detection (INTP5)
Pin
External interrupt pin input
edge detection (INTP6)
Pin
External interrupt pin input
edge detection (INTP7)
Pin
9
INTTQ0OV TMQ0 overflow
TMQ0
0110H
0120H
00000110H
00000120H
nextPC
nextPC
TQ0OVIC
TQ0CCIC0
10
INTTQ0CC0 TMQ0 capture 0/compare 0 TMQ0
match
11
12
13
INTTQ0CC1 TMQ0 capture 1/compare 1 TMQ0
match
0130H
0140H
0150H
00000130H
00000140H
00000150H
nextPC
nextPC
nextPC
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
INTTQ0CC2 TMQ0 capture 2/compare 2 TMQ0
match
INTTQ0CC3 TMQ0 capture 3/compare 3 TMQ0
match
14
15
INTTP0OV TMP0 overflow
TMP0
0160H
0170H
00000160H
00000170H
nextPC
nextPC
TP0OVIC
INTTP0CC0 TMP0 capture 0/compare 0 TMP0
match
TP0CCIC0
16
INTTP0CC1 TMP0 capture 1/compare 1 TMP0
match
0180H
00000180H
nextPC
TP0CCIC1
17
18
INTTP1OV TMP1 overflow
TMP1
0190H
01A0H
00000190H
000001AH
nextPC
nextPC
TP1OVIC
INTTP1CC0 TMP1 capture 0/compare 0 TMP1
match
TP1CCIC0
19
INTTP1CC1 TMP1 capture 1/compare 1 TMP1
match
01B0H
000001B0H
nextPC
TP1CCIC1
20
21
INTTP2OV TMP2 overflow
TMP2
01C0H
01D0H
000001C0H
000001D0H
nextPC
nextPC
TP2OVIC
INTTP2CC0 TMP2 capture 0/compare 0 TMP2
match
TP2CCIC0
Notes 1. For the restoring in the case of INTWDT2, see "17.2.3 (2) From INTWDT2 signal".
2. n = 0H to FH
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Table 17-2. Interrupt Source List (2/3)
Type
Classification Default
Priority
Name
Trigger
Generating Exception
Unit Code
Handler
Address
Restored
PC
Interrupt
Control
Register
Maskable Interrupt
22
INTTP2CC1 TMP2 capture 1/compare 1 TMP2
match
01E0H
000001E0H
nextPC
TP2CCIC1
23
24
INTTP3OV TMP3 overflow
TMP3
01F0H
0200H
000001F0H
00000200H
nextPC
nextPC
TP3OVIC
TP3CCIC0
INTTP3CC0 TMP3 capture 0/compare 0 TMP3
match
25
INTTP3CC1 TMP3 capture 1/compare 1 TMP3
match
0210H
0220H
00000210H
nextPC
TP3CCIC1
26
27
28
INTTM0EQ0 TMM0 compare match
TMM0
00000220H
00000230H
00000240H
nextPC
nextPC
nextPC
TM0EQIC0
CB0RIC
CB0TIC
INTCB0R
INTCB0T
CSIB0 reception completion CSIB0/IIC1 0230H
CSIB0 consecutive
CSIB0
0240H
transmission write enable
29
30
INTCB1R
INTCB1T
CSIB1 reception completion CSIB1
0250H
0260H
00000250H
00000260H
nextPC
nextPC
CB1RIC
CB1TIC
CSIB1 consecutive
CSIB1
transmission write enable
31
32
33
INTUA0R
INTUA0T
INTUA1R
UARTA0 reception
completion
UARTA0/
CSIB4
0270H
0280H
0290H
00000280H
00000280H
00000290H
nextPC
nextPC
nextPC
UA0RIC
UA0TIC
UA1RIC
UARTA0 transmission
enable
UARTA0/
CSIB4
UARTA1 reception
completion/UARTA1
reception error
UARTA1/
IIC2
34
INTUA1T
INTAD
UARTA1 transmission
enable
UARTA1
02A0H
000002A0H
nextPC
UA1TIC
35
36
37
38
A/D conversion completion
A/D
02BH
000002B0H
000002C0H
000002D0H
000002E0H
nextPC
nextPC
nextPC
nextPC
ADIC
INTC0ERR AFCAN0 error
AFCAN0
AFCAN0
AFCAN0
02C0H
02D0H
02E0H
C0ERRIC
C0WUPIC
C0RECIC
INTC0WUP AFCAN0 wakeup
INTC0REC AFCAN0 reception
completion
39
INTC0TRX AFCAN0 transmission
completion
AFCAN0
02F0H
000002F0H
nextPC
C0TRXIC
40
41
42
43
INTKR
INTWTI
INTWT
INTP8
Key return interrupt request KR
0300H
0310H
0320H
0330H
00000300H
00000310H
00000320H
00000330H
nextPC
nextPC
nextPC
nextPC
KRIC
WTIIC
WTIC
PIC8
Watch timer interval
WT
WT
Pin
Watch timer reference time
External interrupt pin input
edge detection (INTP8)
44
45
INTP9
External interrupt pin input
edge detection (INTP9)
Pin
0340H
0350H
00000340H
00000350H
nextPC
nextPC
PIC9
INTP10
External interrupt pin input
edge detection (INTP10)
Pin
PIC10
46
47
INTTQ1OV TMQ1 overflow
TMQ1
0360H
0370H
00000360H
00000370H
nextPC
nextPC
TQ1OVIC
INTTQ1CC0 TMQ1 capture 0/compare 0 TMQ1
match
TQ1CCIC0
48
49
50
INTTQ1CC1 TMQ1 capture 1/compare 1 TMQ1
match
0380H
0390H
03A0H
00000380H
00000390H
000003A0H
nextPC
nextPC
nextPC
TQ1CCIC1
TQ1CCIC2
TQ1CCIC3
INTTQ1CC2 TMQ1 capture 2/compare 2 TMQ1
match
INTTQ1CC3 TMQ1 capture 3/compare 3 TMQ1
match
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 17-2. Interrupt Source List (3/3)
Type
Classification Default
Priority
Name
Trigger
Generating Exception
Handler
Address
Restored
PC
Interrupt
Control
Unit
Code
Register
Maskable Interrupt
51
INTUA2R
UARTA2 reception
completion/error
UARTA2
03B0H
000003B0H
nextPC
UA2RIC
52
53
54
55
56
INTUA2T
UARTA2 transmission enable UARTA2
03C0H
03D0H
03E0H
03F0H
0400H
000003C0H
000003D0H
000003E0H
000003F0H
00000400H
nextPC
nextPC
nextPC
nextPC
nextPC
UA2TIC
INTC1ERR
AFCAN1 error
AFCAN1
AFCAN1
C1ERRIC
C1WUPIC
C1RECIC
C1TRXIC
INTC1WUP AFCAN1 wakeup
INTC1REC
INTC1TRX
AFCAN1 reception completion AFCAN1
AFCAN1 transmission
completion
AFCAN1
57
58
59
60
61
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTP11
DMA0 transfer end
DMA1 transfer end
DMA2 transfer end
DMA3 transfer end
DMA
DMA
DMA
DMA
Pin
0410H
0420H
0430H
0440H
0450H
00000410H
00000420H
00000430H
00000440H
00000450H
nextPC
nextPC
nextPC
nextPC
nextPC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
PIC11
External interrupt pin input
edge detection (INTP11)
62
63
64
INTP12
External interrupt pin input
edge detection (INTP12)
Pin
Pin
Pin
0460H
0470H
0480H
00000460H
00000470H
00000480H
nextPC
nextPC
nextPC
PIC12
PIC13
PIC14
INTP13
External interrupt pin input
edge detection (INTP13)
INTP14
External interrupt pin input
edge detection (INTP14)
65
66
INTTQ2OV
TMQ2 overflow
TMQ2
TMQ2
0490H
04A0H
00000490H
000004A0H
nextPC
nextPC
TQ2OVIC
INTTQ2CC0 TMQ2 capture 0/compare 0
match
TQ2CCIC0
67
68
69
70
71
72
INTTQ2CC1 TMQ2 capture 1/compare 1
match
TMQ2
TMQ2
TMQ2
CSIB2
CSIB2
UARTA3
04B0H
04C0H
04D0H
04E0H
04F0H
0500H
000004B0H
000004C0H
000004D0H
000004E0H
000004F0H
00000500H
nextPC
nextPC
nextPC
nextPC
nextPC
nextPC
TQ2CCIC1
TQ2CCIC2
TQ2CCIC3
CB2RIC
INTTQ2CC2 TMQ2 capture 2/compare 2
match
INTTQ2CC3 TMQ2 capture 3/compare 3
match
INTCB2R
INTCB2T
INTUA3R
CSIB2 reception
completion/error
CSIB2 continuous
CB2TIC
transmission write enable
UARTA3 reception
completion/error
UA3RIC
73
74
75
76
77
INTUA3T
UARTA3 transmission enable UARTA3
0510H
0520H
0530H
0540H
0550H
00000510H
00000520H
00000530H
00000540H
00000550H
nextPC
nextPC
nextPC
nextPC
nextPC
UA3TIC
INTC2ERR
AFCAN2 error
AFCAN2
AFCAN2
C2ERRIC
C2WUPIC
C2RECIC
C2TRXIC
INTC2WUP AFCAN2 wakeup
INTC2REC
INTC2TRX
AFCAN2 reception completion AFCAN2
AFCAN2 transmission
completion
AFCAN2
78
79
80
81
INTC3ERR
AFCAN3 error
AFCAN3
AFCAN3
0560H
0570H
0580H
0590H
00000560H
00000570H
00000580H
00000590H
nextPC
nextPC
nextPC
nextPC
C3ERRIC
C3WUPIC
C3RECIC
C3TRXIC
INTC3WUP AFCAN3 wakeup
INTC3REC
INTC3TRX
AFCAN3 reception completion AFCAN3
AFCAN3 transmission
completion
AFCAN3
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests are generated at
the same time. The highest priority is 0.
Restored PC: The value of the program counter (PC) saved to EIPC or FEPC when interrupt
servicing is started. Note, however, that the restored PC when a non-maskable or
maskable interrupt is acknowledged while one of the following instructions is being
executed does not become the nextPC (if an interrupt is acknowledged during
interrupt execution, execution stops, and then resumes after the interrupt servicing
has finished).
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, and SLD.W)
• Division instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only if an interrupt is generated before the
stack pointer is updated)
nextPC:
The PC value from which the processing starts following interrupt/exception
processing.
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated
by (Restored PC − 4).
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.2 Non-Maskable Interrupts
17.2.1 Non-maskable interrupt request signal
A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt
disabled (DI) state. An NMI is not subject to priority control and takes precedence over all the other interrupt request
signals.
This product has the following two non-maskable interrupt request signals.
• NMI pin input (NMI)
• Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2)
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no
edge detection”.
NMI function becomes valid when the PMC02 bit of the PMC0 register is set to 1 and the INTF02/INTR02 bits of
the INTF0 register is set to any value.
The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when
the WDM21 and WDM20 bits of the WDTM2 register are set to “01”.
If two or more non-maskable interrupt request signals are generated at the same time, the interrupt with the higher
priority is serviced, as follows (the interrupt request signal with the lower priority is ignored).
INTWDT2 > NMI
If a new NMI or INTWDT2 request signal is issued while a NMI is being serviced, it is serviced as follows.
(1) If new NMI request signal is issued while NMI is being serviced
The new NMI request signal is held pending, regardless of the value of the NP bit of the PSW in the CPU. The
pending NMI request signal is acknowledged after the NMI currently under execution has been serviced (after
the RETI instruction has been executed).
(2) If INTWDT2 request signal is issued while NMI is being serviced
The INTWDT2 request signal is held pending if the NP bit of the PSW remains set (1) while the NMI is being
serviced. The pending INTWDT2 request signal is acknowledged after the NMI currently under execution has
been serviced (after the RETI instruction has been executed).
If the NP bit of the PSW is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request
signal is executed (the NMI servicing is stopped).
Caution If a non-maskable interrupt request signal is generated, the values of the PC and PSW are saved
to the NMI status save registers (FEPC and FEPSW). At this time, execution can be returned by
the RETI instruction only if the interrupt was generated by the NMI signal. Execution cannot be
returned while an interrupt generated by the INTWDT2 signal is being serviced. Therefore, reset
the system after the interrupt has been serviced.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation
(a) NMI and INTWDT2 request signals generated at the same time
Main routine
INTWDT2 servicing
NMI and INTWDT2 requests
(generated simultaneously)
System reset
(b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing
Non-maskable
Non-maskable interrupt request signal generated during non-maskable interrupt servicing
interrupt being
serviced
NMI
INTWDT2
NMI
• NMI request generated during NMI servicing
• INTWDT2 request generated during NMI servicing
(NP = 1 retained before INTWDT2 request)
Main routine
NMI servicing
Main routine
NMI servicing
NMI
request
(Held pending)
NMI
request
INTWDT2
request
(Held pending)
Servicing of
pending NMI
NMI
request
INTWDT2 servicing
System reset
• INTWDT2 request generated during NMI servicing
(NP = 0 set before INTWDT2 request)
Main routine
NMI
INTWDT2
servicing
servicing
NP = 0
NMI
request
INTWDT2
request
System reset
• INTWDT2 request generated during NMI servicing
(NP = 0 set after INTWDT2 request)
Main routine
NMI
INTWDT2
servicing
servicing
INTWDT2
request
NP = 0
(Held pending)
NMI
request
System reset
INTWDT2 • NMI request generated during INTWDT2 servicing
•
INTWDT2 request generated during INTWDT2 servicing
Main routine
Main routine
INTWDT2 servicing
INTWDT2 servicing
NMI
request
(Invalid)
INTWDT2
request
(Invalid)
INTWDT2 request
INTWDT2 request
System reset
System reset
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.2.2 Operation
If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers
control to the handler routine.
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes an exception code (0010H, 0020H) to the higher halfword (FECC) of ECR.
<4> Sets the NP and ID bits of the PSW and clears the EP bit.
<5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC,
and transfers control.
The servicing configuration of a non-maskable interrupt is shown in Figure 17-2.
Figure 17-2. Servicing Configuration of Non-Maskable Interrupt
NMI input
INTC
acknowledged
Non-maskable interrupt request
CPU processing
1
PSW.NP
0
Interrupt request held pending
FEPC
Restored PC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
PSW
0010H, 0020H
1
0
1
00000010H,
00000020H
Interrupt servicing
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.2.3 Restore
(1) From NMI input
Execution is restored from NMI servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is
0 and the NP bit of the PSW is 1.
<2> Transfers control back to the address of the restored PC and PSW.
Figure 17-3 illustrates how the RETI instruction is processed.
Figure 17-3. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
1
PSW.NP
0
PC
EIPC
PC
FEPC
PSW
EIPSW
PSW
FEPSW
Original processing restored
Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during non-
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the
LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) From INTWDT2 signal
Execution cannot be returned from INTWDT2 by the RETI instruction. Execute the following software reset
processing.
Figure 22-4. Software Reset Processing
INTWDT2 occurs.
FEPC ← Software reset processing address
FEPSW ← Value that sets NP bit = 1, EP bit = 0
INTWDT2 servicing routine
↓
RETI
RETI 10 times (FEPC and FEPSWNote must be set.)
↓
Software reset processing routine
PSW ← PSW default value setting
↓
Initialization processing
Note FEPSW ← Value that sets NP bit = 1, EP bit = 0
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.2.4 NP flag
The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution.
This flag is set when a non-maskable interrupt request signal has been acknowledged, and after that, non-
maskable interrupt request is reserved.
After reset: 00000020H
PSW
0
NP EP ID SAT CY OV
S
Z
NP
0
Non-maskable interrupt servicing status
No non-maskable interrupt servicing
1
Non-maskable interrupt currently being serviced
17.2.5 Eliminating noise on NMI pin
The NMI pin has a noise eliminator that eliminates noise using analog delay. Unless the level input to the NMI pin
is held for a specific time, therefore, it cannot be detected as an edge (i.e., the edge is detected after a specific time).
The NMI pin is used to release the software STOP mode. Because the internal system clock is stopped in the
software STOP mode, noise elimination using the system clock is not performed.
17.2.6 Function to detect edge of NMI pin
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no
edge detection”.
Specify the valid edge of the NMI pin by using the INTR0 and INTF0 registers.
After reset, NMI function is not valid unless the PMC02 bit of the PMC0 register is set to 1 and the INTF02/INTR02
bits of the INTF0 register is set to any value.
To use the P00/NMI pin as an I/O port pin, specify that the valid edge of the NMI pin is “no edge detection”.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(1) External interrupt falling edge specification register 0 (INTF0)
The INTF0 register is an 8-bit register that specifies detection of the falling edge of an NMI via bit 2.
This register can be read or written in 8-bit or 1-bit units.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC00H
INTF0
0
INTF06 INTF05 INTF04 INTF03 INTF02
0
0
Remark For how to specify a valid edge, see Table 17-3.
(2) External interrupt rising edge specification register 0 (INTR0)
The INTR0 register is an 8-bit register that specifies detection of the rising edge of the NMI pin via bit 2.
This register can be read or written in 8-bit or 1-bit units.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC20H
INTR0
0
INTR06 INTR05 INTR04 INTR03 INTR02
0
0
Remark For how to specify a valid edge, see Table 17-3.
Table 17-3. NMI Valid Edge Specification
INTF02
INTR02
NMI Valid Edge Specification
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both rising and falling edges
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3 Maskable Interrupts
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/Fx2 has up to 82
maskable interrupt sources.
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged
according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using
the interrupt control registers (programmable priority control).
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt
request signals is disabled and the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the
same priority level cannot be serviced as multiple interrupts.
To enable multiple interrupt servicing, however, save EIPC and EIPSW to memory or registers before executing
the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and
EIPSW.
17.3.1 Operation
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the ID bit of the PSW and clears the EP bit.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while
another interrupt is being serviced (while PSW.NP = 1 or PSW.ID = 1) are held pending inside the INTC. In this case,
servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request
signal if either the maskable interrupt is unmasked or PSW.NP and PSW.ID are cleared to 0 by using the RETI or
LDSR instruction.
How maskable interrupts are serviced is illustrated below.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-4. Maskable Interrupt Servicing
INT input
INTC accepted
No
xxIF = 1
Yes
Interrupt requested?
No
xxMK = 0
Yes
Is the interrupt
mask released?
Priority higher than
that of interrupt currently
being serviced?
No
No
No
Yes
Priority higher
than that of other interrupt
request?
Yes
Highest default
priority of interrupt requests
with the same priority?
Yes
Maskable interrupt request
Interrupt request held pending
CPU processing
1
1
PSW.NP
0
PSW.ID
0
EIPC
EIPSW
Restored PC
PSW
Interrupt request held pending
ECR.EICC
PSW.EP
PSW.ID
Corresponding
bit of ISPRNote
PC
Exception code
0
1
1
Handler address
Interrupt servicing
Note For details of the ISPR register, see 17.3.6 In-service priority register (ISPR).
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.2 Restore
Execution is restored from maskable interrupt servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of
the PSW is 0.
<2> Transfers control to the address of the restored PC and PSW.
Figure 17-5 illustrates the processing of the RETI instruction.
Figure 17-5. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
1
PSW.NP
0
PC
PSW
Corresponding
bit of ISPRNote
EIPC
EIPSW
0
PC
PSW
FEPC
FEPSW
Restores original processing
Note For details of the ISPR register, see 17.3.6 In-service priority register (ISPR).
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the
LDSR instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.3 Priorities of maskable interrupts
The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is
being serviced. Multiple interrupt servicing can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to
each interrupt request type (default priority level) beforehand. For more information, see Table 17-2 Interrupt
Source List. Programmable priority control customizes interrupt request signals into eight levels by setting the
priority level specification flag.
Note that when an interrupt request signal is acknowledged, the ID flag of the PSW is automatically set to 1.
Therefore, when multiple interrupt servicing is to be used, clear the ID flag to 0 beforehand (for example, by placing
the EI instruction in the interrupt servicing program) to set the interrupt enable mode.
Remark xx: Identification name of each peripheral unit (see Table 17-4 Interrupt Control Registers (xxICn))
n: Peripheral unit number (see Table 17-4 Interrupt Control Registers (xxICn))
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-6. Example of Processing in Which Interrupt Request Signal Is Issued
While Another Interrupt Is Being Serviced (1/2)
Main routine
Servicing of a
Servicing of b
EI
EI
Interrupt
request b
(level 2)
Interrupt request a
(level 3)
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Servicing of c
Interrupt request c
(level 3)
Interrupt request d
(level 2)
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Servicing of d
Servicing of e
EI
Interrupt request e
(level 2)
Interrupt request f
(level 3)
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Servicing of f
Servicing of g
EI
Interrupt request
(level 1)
h
Interrupt request g
(level 1)
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Servicing of h
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. “a” to “u” in the figure are assumed names given to interrupt request signals for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request
signals.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-6. Example of Processing in Which Interrupt Request Signal Is Issued
While Another Interrupt Is Being Serviced (2/2)
Main routine
Servicing of i
EI
EI
Servicing of k
Interrupt
request j
(level 3)
Interrupt request i
(level 2)
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt request k
(level 1)
Servicing of j
Servicing of l
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Interrupt
request m
(level 3)
Interrupt request l
(level 2)
Interrupt request n
(level 1)
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of n
Servicing of m
Servicing of o
Servicing of p
EI
Servicing of q
EI
Interrupt request o
(level 3)
EI
Interrupt
request p
(level 2)
Servicing of r
Interrupt
request q
(level 1)
Interrupt
request r
(level 0)
If levels 3 to 0 are acknowledged
Servicing of s
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
Interrupt
request t
(level 2)
Note 1
Note 2
Interrupt request s
(level 1)
Interrupt request u
(level 2)
Servicing of u
Servicing of t
Notes 1. Lower default priority
2. Higher default priority
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-7. Example of Servicing Interrupt Request Signals Generated Simultaneously
Main routine
EI
Interrupt request a (level 2)
Interrupt request b (level 1)
Interrupt request c (level 1)
.
.
Interrupt request
acknowledged first according to
their priorities.
Because the priorities of b and c are
the same, b is acknowledged first
according to the default priority.
b and c are
Servicing of interrupt request b
Default priority
a > b > c
Servicing of interrupt request c
Servicing of interrupt request a
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. “a” to “c” in the figure are assumed names given to interrupt request signals for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request
signals.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.4 Interrupt control registers (xxICn)
An xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions
for each maskable interrupt request.
These registers can be read or written in 8-bit or 1-bit units.
Reset input sets these registers to 47H.
Caution Disable interrupts (DI) to read the xxIFn bit of the xxICn register. If the xxIFn bit is read while
interrupts are enabled (EI), the correct value may not be read when acknowledging an interrupt
and reading the bit conflict.
After reset: 47H
7
R/W
Address: FFFFF112H to FFFFF1B2H
6
xxICn
xxIFn
xxMKn
0
0
0
xxPRn2 xxPRn1 xxPRn0
xxIFn
Interrupt request flagNote
0
1
Interrupt request not issued
Interrupt request issued
xxMKn
Interrupt mask flag
0
1
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxPRn2 xxPRn1 xxPRn0
Interrupt priority specification bit
Specifies level 0 (highest).
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark xx: Identification name of each peripheral unit (see Table 17-4 Interrupt Control Registers (xxICn))
n: Peripheral unit number (see Table 17-4 Interrupt Control Registers (xxICn)).
The addresses and bits of the interrupt control registers are as follows.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 17-4. Interrupt Control Registers (xxICn) (1/2)
Address
Register
Bit
7
LVIIF
PIF0
6
LVIMK
PMK0
PMK1
PMK2
PMK3
PMK4
PMK5
PMK6
PMK7
TQ0OVMK
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
FFFFF110H
FFFFF112H
FFFFF114H
FFFFF116H
FFFFF118H
FFFFF11AH
FFFFF11CH
FFFFF11EH
FFFFF120H
FFFFF122H
FFFFF124H
FFFFF126H
FFFFF128H
FFFFF12AH
FFFFF12CH
FFFFF12EH
FFFFF130H
FFFFF132H
FFFFF134H
FFFFF136H
FFFFF138H
FFFFF13AH
FFFFF13CH
FFFFF13EH
FFFFF140H
FFFFF142H
FFFFF144H
FFFFF146H
FFFFF148H
FFFFF14AH
FFFFF14CH
FFFFF14EH
FFFFF150H
FFFFF152H
FFFFF154H
FFFFF156H
FFFFF158H
FFFFF15AH
FFFFF15CH
FFFFF15EH
FFFFF160H
FFFFF162H
LVIIC
PIC0
LVIPR2
PPR02
PPR12
PPR22
PPR32
PPR42
PPR52
PPR62
PPR72
LVIPR1
PPR01
PPR11
PPR21
PPR31
PPR41
PPR51
PPR61
PPR71
LVIPR0
PPR00
PPR10
PPR20
PPR30
PPR40
PPR50
PPR60
PPR70
PIC1
PIF1
PIC2
PIF2
PIC3
PIF3
PIC4
PIF4
PIC5
PIF5
PIC6
PIF6
PIC7
PIF7
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
TP3OVIC
TP3CCIC0
TP3CCIC1
TM0EQIC0
CB0RIC
CB0TIC
CB1RIC
CB1TIC
UA0RIC
UA0TIC
UA1RIC
UA1TIC
ADIC
TQ0OVIF
TQ0OVPR2 TQ0OVPR1 TQ0OVPR0
TQ0CCPR02 TQ0CCPR01 TQ0CCPR00
TQ0CCPR12 TQ0CCPR11 TQ0CCPR10
TQ0CCPR22 TQ0CCPR21 TQ0CCPR20
TQ0CCPR32 TQ0CCPR31 TQ0CCPR30
TP0OVPR2 TP0OVPR1 TP0OVPR0
TP0CCPR02 TP0CCPR01 TP0CCPR00
TP0CCPR12 TP0CCPR11 TP0CCPR10
TP1OVPR2 TP1OVPR1 TP1OVPR0
TP1CCPR02 TP1CCPR01 TP1CCPR00
TP1CCPR12 TP1CCPR11 TP1CCPR10
TP2OVPR2 TP2OVPR1 TP2OVPR0
TP2CCPR02 TP2CCPR01 TP2CCPR00
TP2CCPR12 TP2CCPR11 TP2CCPR10
TP3OVPR2 TP3OVPR1 TP3OVPR0
TP3CCPR02 TP3CCPR01 TP3CCPR00
TP3CCPR12 TP3CCPR11 TP3CCPR10
TM0EQPR02 TM0EQPR01 TM0EQPR00
TQ0CCIF0 TQ0CCMK0
TQ0CCIF1 TQ0CCMK1
TQ0CCIF2 TQ0CCMK2
TQ0CCIF3 TQ0CCMK3
TP0OVIF
TP0CCIF0
TP0CCIF1
TP1OVIF
TP1CCIF0
TP1CCIF1
TP2OVIF
TP2CCIF0
TP2CCIF1
TP3OVIF
TP3CCIF0
TP3CCIF1
TP0OVMK
TP0CCMK0
TP0CCMK1
TP1OVMK
TP1CCMK0
TP1CCMK1
TP2OVMK
TP2CCMK0
TP2CCMK1
TP3OVMK
TP3CCMK0
TP3CCMK1
TM0EQIF0 TM0EQMK0
CB0RIF
CB0TIF
CB1RIF
CB1TIF
UA0RIF
UA0TIF
UA1RIF
UA1TIF
ADIF
CB0RMK
CB0TMK
CB1RMK
CB1TMK
UA0RMK
UA0TMK
UA1RMK
UA1TMK
ADMK
CB0RPR2
CB0TPR2
CB1RPR2
CB1TPR2
UA0RPR2
UA0TPR2
UA1RPR2
UA1TPR2
ADPR2
CB0RPR1
CB0TPR1
CB1RPR1
CB1TPR1
UA0RPR1
UA0TPR1
UA1RPR1
UA1TPR1
ADPR1
CB0RPR0
CB0TPR0
CB1RPR0
CB1TPR0
UA0RPR0
UA0TPR0
UA1RPR0
UA1TPR0
ADPR0
C0ERRIC
C0WUPIC
C0RECIC
C0TRXIC
KRIC
C0ERRIF
C0WUPIF
C0RECIF
C0TRXIF
KRIF
C0ERRMK
C0WUPMK
C0RECMK
C0TRXMK
KRMK
C0ERRPR2 C0ERRPR1 C0ERRPR0
C0WUPPR2 C0WUPPR1 C0WUPPR0
C0RECPR2 C0RECPR1 C0RECPR0
C0TRXPR2 C0TRXPR1 C0TRXPR0
KRPR2
KRPR1
KRPR0
WTIIC
WTIIF
WTIMK
WTIPR2
WTIPR1
WTIPR0
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 17-4. Interrupt Control Registers (xxICn) (2/2)
Address
Register
Bit
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
FFFFF164H
FFFFF166H
FFFFF168H
FFFFF16AH
FFFFF16CH
FFFFF16EH
FFFFF170H
FFFFF172H
FFFFF174H
FFFFF176H
FFFFF178H
FFFFF17AH
FFFFF17CH
FFFFF17EH
FFFFF180H
FFFFF182H
FFFFF184H
FFFFF186H
FFFFF188H
FFFFF18AH
FFFFF18CH
FFFFF18EH
FFFFF190H
FFFFF192H
FFFFF194H
FFFFF196H
FFFFF198H
FFFFF19AH
FFFFF19CH
FFFFF19EH
FFFFF1A0H
FFFFF1A2H
FFFFF1A4H
FFFFF1A6H
FFFFF1A8H
FFFFF1AAH
FFFFF1ACH
FFFFF1AEH
FFFFF1B0H
FFFFF1B2H
WTIC
PIC8
WTIF
PIF8
WTMK
PMK8
WTPR2
PPR82
PPR92
PPR102
WTPR1
PPR81
PPR91
PPR101
WTPR0
PPR80
PPR90
PPR100
PIC9
PIF9
PMK9
PIC10
PIF10
TQ1OVIF
PMK10
TQ1OVMK
TQ1OVIC
TQ1CCIC0
TQ1CCIC1
TQ1CCIC2
TQ1CCIC3
UA2RIC
UA2TIC
TQ1OVPR2 TQ1OVPR1 TQ1OVPR0
TQ1CCPR02 TQ1CCPR01 TQ1CCPR00
TQ1CCPR12 TQ1CCPR11 TQ1CCPR10
TQ1CCPR22 TQ1CCPR21 TQ1CCPR20
TQ1CCPR32 TQ1CCPR31 TQ1CCPR30
TQ1CCIF0 TQ1CCMK0
TQ1CCIF1 TQ1CCMK1
TQ1CCIF2 TQ1CCMK2
TQ1CCIF3 TQ1CCMK3
UA2RIF
UA2TIF
C1ERRIF
C1WUPIF
C1RECIF
C1TRXIF
DMAIF0
DMAIF1
DMAIF2
DMAIF3
PIF11
UA2RMK
UA2TMK
C1ERRMK
C1WUPMK
C1RECMK
C1TRXMK
DMAMK0
DMAMK1
DMAMK2
DMAMK3
PMK11
UA2RPR2
UA2TPR2
UA2RPR1
UA2TPR1
UA2RPR0
UA2TPR0
C1ERRIC
C1WUPIC
C1RECIC
C1TRXIC
DMAIC0
DMAIC1
DMAIC2
DMAIC3
PIC11
C1ERRPR2 C1ERRPR1 C1ERRPR0
C1WUPPR2 C1WUPPR1 C1WUPPR0
C1RECPR2 C1RECPR1 C1RECPR0
C1TRXPR2 C1TRXPR1 C1TRXPR0
DMAPR02
DMAPR12
DMAPR22
DMAPR32
PPR112
DMAPR01
DMAPR11
DMAPR21
DMAPR31
PPR111
DMAPR00
DMAPR10
DMAPR20
DMAPR30
PPR110
PIC12
PIF12
PMK12
PPR122
PPR121
PPR120
PIC13
PIF13
PMK13
PPR132
PPR131
PPR130
PIC14
PIF14
PMK14
PPR142
PPR141
PPR140
TQ2OVIC
TQ2CCIC0
TQ2CCIC1
TQ2CCIC2
TQ2CCIC3
CB2RIC
CB2TIC
TQ2OVIF
TQ2OVMK
TQ2OVPR2 TQ2OVPR1 TQ2OVPR0
TQ2CCPR02 TQ2CCPR01 TQ2CCPR00
TQ2CCPR12 TQ2CCPR11 TQ2CCPR10
TQ2CCPR22 TQ2CCPR21 TQ2CCPR20
TQ2CCPR32 TQ2CCPR31 TQ2CCPR30
TQ2CCIF0 TQ2CCMK0
TQ2CCIF1 TQ2CCMK1
TQ2CCIF2 TQ2CCMK2
TQ2CCIF3 TQ2CCMK3
CB2RIF
CB2TIF
CB2RMK
CB2TMK
CB2RPR2
CB2TPR2
UA3RPR2
UA3TPR2
CB2RPR1
CB2TPR1
UA3RPR1
UA3TPR1
CB2RPR0
CB2TPR0
UA3RPR0
UA3TPR0
UA3RIC
UA3TIC
UA3RIF
UA3RMK
UA3TIF
UA3TMK
C2ERRIC
C2WUPIC
C2RECIC
C2TRXIC
C3ERRIC
C3WUPIC
C3RECIC
C3TRXIC
C2ERRIF
C2WUPIF
C2RECIF
C2TRXIF
C3ERRIF
C3WUPIF
C3RECIF
C3TRXIF
C2ERRMK
C2WUPMK
C2RECMK
C2TRXMK
C3ERRMK
C3WUPMK
C3RECMK
C3TRXMK
C2ERRPR2 C2ERRPR1 C2ERRPR0
C2WUPPR2 C2WUPPR1 C2WUPPR0
C2RECPR2 C2RECPR1 C2RECPR0
C2TRXPR2 C2TRXPR1 C2TRXPR0
C3ERRPR2 C3ERRPR1 C3ERRPR0
C3WUPPR2 C3WUPPR1 C3WUPPR0
C3RECPR2 C3RECPR1 C3RECPR0
C3TRXPR2 C3TRXPR1 C3TRXPR0
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR4, IMR5L)
The IMR0 to IMR4, IMR5L registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the
IMR0 to IMR4 and IMR5L registers is equivalent to the xxMKn bit of the xxICn register.
The IMRm register can be read or written in 16-bit units (m = 0 to 4).
The IMR5L register can be read or written in 8-bit or 1-bit units.
If the higher 8 bits of the IMRm register are used as the IMRmH register and the lower 8 bits as the IMRmL register,
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 4).
Reset input sets these registers to FFFFH.
Bits 7 to 2 of the IMR5L register are fixed to 1. If these bits are not 1, the operation cannot be guaranteed.
Reset input sets these registers to FFFFH.
Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is
manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm
register, are rewritten (as a result, the contents of the IMRm register are also rewritten).
(1/2)
After reset: FFH
R/W
Address: FFFF10AH
7
6
1
5
1
4
1
3
1
2
1
1
0
IMR5L
1
C3TRXMK C3RECMK
Caution
Set bits 7 to 2 of the IMR5L register to 1.
After reset: FFFFH
15
R/W
Address: FFFF108H
13 12
14
11
10
9
8
IMR4
C3WUPMK C3ERRMK C2TRXMK C2RECMK C2WUPMK C2ERRMK
UA3TMK
UA3RMK
7
6
5
4
3
2
1
0
CB2TMK
CB2RMK TQ2CCMK3 TQ2CCMK2 TQ2CCMK1 TQ2CCMK0 TQ2OVMK
PMK14
After reset: FFFFH
15
R/W
Address: FFFF106H
14
PMK12
6
13
PMK11
5
12
DMAMK3
4
11
DMAMK2
3
10
DMAMK1
2
9
DMAMK0
1
8
C1TRXMK
0
IMR3
PMK13
7
C1RECMK C1WUPMK C1ERRMK
UA2TMK
UA2RMK TQ1CCMK3 TQ1CCMK2 TQ1CCMK1
After reset: FFFFH
15
R/W
Address: FFFF104H
14
13
PMK10
5
12
PMK9
4
11
PMK8
3
10
WTMK
2
9
WTIMK
1
8
KRMK
0
IMR2
TQ1CCMK0 TQ1OVMK
7
6
C0TRXMK C0RECMK C0WUPMK C0ERRMK
ADMK
UA1TMK
UA1RMK
UA0TMK
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2/2)
After reset: FFFFH
15
R/W
Address: FFFF102H
14
13
CB1RMK
5
12
CB0TMK
4
11
10
9
8
IMR1
UA0RMK
7
CB1TMK
6
CB0RMK TM0EQMK0 TP3CCMK1 TP3CCMK0
3
2
1
0
TP3OVMK TP2CCMK1 TP2CCMK0 TP2OVMK TP1CCMK1 TP1CCMK0 TP1OVMK TP0CCMK1
After reset: FFFFH
15
R/W
Address: FFFF100H
13 12
14
11
10
9
8
PMK7
0
IMR0
TP0CCMK0 TP0OVMK TQ0CCMK3 TQ0CCMK2 TQ0CCMK1 TQ0CCMK0 TQ0OVMK
7
6
5
4
3
2
1
PMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
xxMKn
Interrupt mask flag setting
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Remark xx: Identification name of each peripheral unit (see Table 17-4 Interrupt Control
Registers (xxICn)).
n: Peripheral unit number (see Table 17-4 Interrupt Control Registers (xxICn))
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.6 In-service priority register (ISPR)
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt
request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal
is set to 1 and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest
priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-
maskable interrupt servicing or exception processing.
This register is read-only, in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI)
state, the value of the ISPR register after the bits of the register have been set by acknowledging
the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is
acknowledged, read the register while interrupts are disabled (DI).
After reset: 00H
7
R
Address: FFFFF1FAH
6
5
4
3
2
1
0
ISPR
ISPR7
ISPR6
ISPR5
ISPR4
ISPR3
ISPR2
ISPR1
ISPR0
ISPRn
Priority of interrupt currently acknowledged
0
1
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
Remark n = 0 to 7 (priority level)
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.7 ID flag
This is the interrupt disable flag and controls the maskable interrupt’s operating state, and stores control
information regarding enabling or disabling of interrupt request signals. The ID flag is assigned to the PSW.
After reset: 00000020H
PSW
0
NP EP ID SAT CY OV
S
Z
ID
0
Specification of maskable interrupt servicingNote
Maskable interrupt request signal acknowledgment enabled
Maskable interrupt request signal acknowledgment disabled
1
Note Interrupt disable flag (ID) function
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is also modified by
the RETI instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When
a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware.
An interrupt request signal generated during the acknowledgment disabled period (ID = 1) is
acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag is reset to 0.
17.3.8 Watchdog timer mode register 2 (WDTM2)
The WDTM2 register is a special register and can only be written in a specific sequence.
This register can be read or written in 8-bit units (for details, see CHAPTER 11 FUNCTIONS OF WATCHDOG
TIMER 2).
Reset input sets this register to 67H.
After reset: 67H
R/W
Address: FFFFF6D0H
WDTM2
0
WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
WDM21 WDM20
Selection of watchdog timer operation mode
Stops operation
0
0
1
0
1
×
Non-maskable interrupt request mode
Reset mode (initial-value)
Remark For the WDCS24 to WDCS20 bits refer to CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.3.9 Eliminating noise on INTP0 to INTP7 pins
The INTP0 to INTP7 pins have a noise eliminator that eliminates noise using analog delay. Unless the level input
to each pin is held for a specific time, therefore, it cannot be detected as a signal edge (i.e., the edge is detected after
a specific time). Noise elimination by analog delay or digital noise elimination can be selected for the INTP3 pin.
17.3.10 Function to detect edge of INTP0 to INTP14 pins
The valid edge of the INTP0 to INTP14 pins can be selected from the following four.
• Rising edge
• Falling edge
• Both edges
• No edge detection
(1) External interrupt falling edge specification register 0 (INTF0)
The INTF0 register is an 8-bit register that specifies detection of the falling edge of the non-maskable interrupt
pin (NMI) via bit 2 or external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC00H
INTF0
0
INTF06 INTF05 INTF04 INTF03 INTF02
0
0
Remark For how to specify a valid edge, see Table 17-5.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) External interrupt rising edge specification register 0 (INTR0)
The INTR0 register is an 8-bit register that specifies detection of the rising edge of the non-maskable interrupt
pin (NMI) via bit 2 or external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC20H
INTR0
0
INTR06 INTR05 INTR04 INTR03 INTR02
0
0
Remark For how to specify a valid edge, see Table 17-5.
Table 17-5. Valid Edge Specification (INTF0n, INTR0n)
INTF0n
INTR0n
Valid Edge Specification (n = 2 to 6)
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both rising and falling edges
Remark n = 2: NMI pin control
n = 3: INTP0 pin control
n = 4: INTP1 pin control
n = 5: INTP2 pin control
n = 6: INTP3 pin control
Caution Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not specified as
NMI or INTP0 to INTP3.
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(3) External interrupt falling edge specification register 1 (INTF1)
The INTF1 register is an 8-bit register that specifies detection of the falling edge of external interrupt pins
(INTP9, INTP10) via bits 0 and 1.
This register can be read or written in 8-bit or 1-bit units.
Reset input cleats this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF1n and INTR1n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC02H
INTF1
0
0
0
0
0
0
INTF11 INTF10
Remark For how to specify a valid edge, see Table 17-6.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(4) External interrupt rising edge specification register 1 (INTR1)
The INTR1 register is an 8-bit register that specifies detection of the rising edge of external interrupt pins
(INTP9, INTP10) via bits 0 and 1.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF1n and INTR1n bits to 0,
and then set the port mode.
After reset: 00H
R/W
Address: FFFFFC22H
0
0
0
0
0
0
INTR11 INTR10
INTR1
Remark For how to specify a valid edge, see Table 17-6.
Table 17-6. Valid Edge Specification (INTF1n, INTR1n)
INTF1n Bit
INTR1n Bit
Valid Edge Specification (n = 0, 1)
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both rising and falling edges
Remark n = 0: INTP9 pin control
n = 1: INTP10 pin control
Caution Be sure to clear the INTF1n and INTR1n bits to 00 when these registers are not used as
INTP9 and INTP10.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(5) External interrupt falling edge specification register 3 (INTF3)
The INTF3 register is a 16-bit register that specifies detection of the falling edge of external interrupt pins
(INTP7, INTP8) via bits 1 and 9. This register can be read or written in 16-bit units.
However, when the higher 8 bits of INTF3 register are used as the INTF3H register and the lower 8 bits as the
INTF3L register, they can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 0000H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF3n and INTR3n bits to 0, and
then set the port mode.
After reset: 0000H
15
R/W
14
Address: FFFFFC06H, FFFFFC07H
13
0
12
0
11
0
10
0
9
8
0
0
0
INTF3 (INTF3HNote
)
0
7
0
0
6
0
INTF39
1
5
4
3
2
(INTF3L)
0
0
0
0
INTF31
Note When bits 8 to 15 of the INTF3 register are read or written in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the INTF3H register
Remark For how to specify a valid edge, see Table 17-7.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(6) External interrupt rising edge specification register 3 (INTR3)
The INTR3 register is a 16-bit register that specifies detection of the rising edge of external interrupt pins
(INTP7, INTP8) via bits 1 and 9. This register can be read or written in 16-bit units.
However, when the higher 8 bits of INTR3 register are used as the INTR3H register and the lower 8 bits as the
INTR3L register, they can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 0000H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF3n and INTR3n bits to 0, and
then set the port mode.
After reset: 0000H
15
R/W
14
Address: FFFFFC26H, FFFFFC27H
13
0
12
0
11
0
10
0
9
8
0
0
0
INTR3 (INTR3HNote
)
0
7
0
0
6
0
INTR39
1
5
4
3
2
(INTR3L)
0
0
0
0
INTR31
Note When bits 8 to 15 of the INTR3 register are read or written in 8-bit or 1-bit units, specify them as
bits 0 to 7 of the INTR3H register
Remark For how to specify a valid edge, see Table 17-7.
Table 17-7. Valid Edge Specification (INTF3n, INTR3n)
INTF3n Bit
INTR3n Bit
Valid Edge Specification (n = 1, 9)
No edge detection
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both rising and falling edges
Remark n = 1: INTP7 pin control
n = 9: INTP8 pin control
Caution Be sure to clear the INTF3n and INTR3n bits to 00 when these registers are not specified as
INTP7 and INTP8.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(7) External interrupt falling edge specification register 6L (INTF6L)
The INTF6L register is an 8-bit register that specifies detection of the falling edge of external interrupt pins
(INTP11 to INTP13) via bits 0 to 2. This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF6n and INTR6n bits to 0,
and then set the port mode.
After reset: 00H
7
R/W
Address: FFFFFC0CH
6
5
0
4
0
3
0
2
1
0
INTF6L
0
0
INTF62
INTF61
INTF60
Remark For how to specify a valid edge, see Table 17-8.
(8) External interrupt rising edge specification register 6L (INTR6L)
The INTR6L register is an 8-bit register that specifies detection of the rising edge of external interrupt pins
(INTP11 to INTP13) via bits 0 to 2. This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF6n and INTR6n bits to 0,
and then set the port mode.
After reset: 00H
7
R/W
Address: FFFFFC2CH
6
5
0
4
0
3
0
2
1
0
INTR6L
0
0
INTR62
INTR61
INTR60
Remark For how to specify a valid edge, see Table 17-8.
Table 17-8. Valid Edge Specification (INTF6n, INTR6n)
INTF6n Bit
INTR6n Bit
Valid Edge Specification (n = 0 to 2)
No edge detection
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both rising and falling edges
Remark n = 0: INTP11 pin control
n = 1: INTP12 pin control
n = 2: INTP13 pin control
Caution Be sure to clear the INTF6n and INTR6n bits to 00 when these registers are not specified as
INTP11 to INTP13.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(9) External interrupt falling edge specification register 8 (INTF8)
The INTF8 register is an 8-bit register that specifies detection of the falling edge of an external interrupt pin
(INTP8) via bit 0. This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF80 and INTR80 bits to 0, and
then set the port mode.
After reset: 00H
7
R/W
Address: FFFFFC10H
6
5
0
4
0
3
0
2
0
1
0
0
INTF8
0
0
INTF80
Remark For how to specify a valid edge, see Table 17-9.
(10)External interrupt rising edge specification register 8 (INTR8)
The INTR8 register is an 8-bit register that specifies detection of the rising edge of an external interrupt pin
(INTP8) using bit 0. This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF80 and INTR80 bits to 0, and
then set the port mode.
After reset: 00H
7
R/W
Address: FFFFFC30H
6
5
0
4
0
3
0
2
0
1
0
0
INTR8
0
0
INTR80
Remark For how to specify a valid edge, see Table 17-9.
Table 17-9. Valid Edge Specification (INTF80, INTR80)
INTF80 Bit
INTR80 Bit
Valid Edge Specification
No edge detection
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Both rising and falling edges
Remark INTP14 pin control
Caution Be sure to clear the INTF80 and INTR80 bits to 00 when these registers are not specified as
INTP14.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(11)External interrupt falling edge specification register 9H (INTF9H)
The INTF9H register is an 8-bit register that specifies detection of the falling edge of external interrupt pins
(INTP4 to INTP6) via bits 5 to 7.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0,
and then set the port mode.
After reset: 00H
7
R/W
6
Address: FFFFFC13H
5
4
3
2
1
0
INTF9H
INTH915 INTF914 INTF913
0
0
0
0
0
Remark For how to specify a valid edge, see Table 17-10.
(12)External interrupt rising edge specification register 9H (INTR9H)
The INTR9H register is an 8-bit register that specifies detection of the rising edge of external interrupt pins
(INTP4 to INTP6) via bits 5 to 7.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0,
and then set the port mode.
After reset: 00H
7
R/W
6
Address: FFFFFC33H
5
4
3
2
1
0
INTR9H
INTR915 INTR914 INTR913
0
0
0
0
0
Remark For how to specify a valid edge, see Table 17-10.
Table 17-10. Valid Edge Specification (INTF9n, INTR9n)
INTF9n Bit
INTR9n Bit
Valid Edge Specification (n = 13 to 15)
0
0
1
1
0
1
0
1
No edge detected
Rising edge
Falling edge
Both rising and falling edges
Remark n = 13: INTP4 pin control
n = 14: INTP5 pin control
n = 15: INTP6 pin control
Caution Be sure to clear the INTF9n and INTR9n bits to 00 when these registers are not used as
INTP4 to INTP6.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(13)Noise elimination control register (NFC)
Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using
the NFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed 2 or 3 times.
Even when digital noise elimination is selected, using fXT as the sampling clock makes it possible to use the
INTP3 interrupt request signal to release the IDLE1, IDLE2 and Software STOP modes.
This register can be read or written in 8-bit units.
Reset input clears this register to 00H.
Caution After the sampling clock has been changed; it takes "set number by NFSTS bit" sampling clocks
to initialize the digital noise eliminator. Therefore, if an INTP3 valid edge is input within these "set
number by NFSTS bit" sampling clocks after the sampling clock has been changed, an interrupt
request signal may be generated. Therefore, be careful about the following points when using the
interrupt and DMA functions.
• When using the interrupt function, after the "set number by NFSTS bit" sampling clocks have
elapsed, enable interrupts after the interrupt request flag (bit 7 of PIC3) has been cleared.
• When using the DMA function (started by INTP3), enable DMA after "set number by NFSTS bit"
sampling clocks have elapsed.
After reset: 00H
R/W
Address: FFFFF318H
NFC
NFEN
NFSTS
0
0
0
NFC2
NFC1
NFC0
NFEN
Settings of INTP3 pin noise elimination
0
1
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
NFSTS
Setting of sampling performed for digital noise elimination
Sampling performed = 3
0
1
Sampling performed = 2
NFC2
NFC1
NFC0
Digital sampling clock
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
f
f
f
f
f
f
XX/64
XX/128
XX/256
XX/512
XX/1,024
XT (subclock)
Setting prohibited
Other than above
Remarks 1. Since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
generated if noise synchronized with the sampling clock is input.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.4 Software Exceptions
A software exception is generated when the CPU executes the TRAP instruction, and can always be
acknowledged.
17.4.1 Operation
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the EP and ID bits of the PSW.
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC,
and transfers control.
Figure 17-8 illustrates the processing of a software exception.
Figure 17-8. Software Exception Processing
TRAP instructionNote
CPU processing
EIPC
Restored PC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
PSW
Exception code
1
1
Handler address
Exception processing
Note TRAP instruction format: TRAP vector (the vector is a value from 0 to 1FH.)
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 0 to 0FH, it
becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.4.2 Restore
Execution is restored from software exception processing by the RETI instruction.
When the RETI instruction is executed, the CPU carries out the following processing and shifts control to the
restored PC’s address.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
<2> Transfers control to the address of the restored PC and PSW.
Caution DBPC and DBPSW can be access from execution of the DBTRAP instruction or illegal instruction
till execution of the DBRET instruction only.
Figure 17-9 illustrates the processing of the RETI instruction.
Figure 17-9. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
1
PSW.NP
0
PC
EIPC
PC
FEPC
PSW
EIPSW
PSW
FEPSW
Original processing restored
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during
software exception processing, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction
immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.4.3 EP flag
The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is
set when an exception occurs.
After reset: 00000020H
PSW
0
NP EP ID SAT CY OV
S
Z
EP
0
Exception processing status
Exception processing not in progress.
Exception processing in progress.
1
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850ES/FX2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
17.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
15
11 10
5 4
0
31
27 26
2322
16
× 0
0 1 1 1
to
×
×
×
×
× 1 1 1 1 1 1
×
×
×
×
×
× ×
×
×
×
× × × × ×
1 1 1 1
×: Arbitrary
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended
that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
control.
Figure 17-10 illustrates the processing of the exception trap.
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-10. Exception Trap Processing
Exception trap (ILGOP) occurs
CPU processing
DBPC
Restored PC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
PSW
1
1
1
00000060H
Exception processing
(2) Restore
Execution is restored from an exception trap by the DBRET instruction. When the DBRET instruction is
executed, the CPU carries out the following processing and controls the address of the restored PC.
<1> Loads the restored PC and PSW from DBPC and DBPSW.
<2> Transfers control to the address indicated by the restored PC and PSW.
Figure 17-11 illustrates the processing for restoring from an exception trap.
Figure 17-11. Processing of Restoration from Exception Trap
DBRET instruction
PC
DBPC
PSW
DBPSW
Jump to address of restored PC
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.5.2 Debug trap
A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always
acknowledged.
Upon occurrence of a debug trap, the CPU performs the following processing.
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW.
<4> Sets the handler address (00000060H) for the debug trap to the PC and transfers control.
Figure 17-12 illustrates the processing of the debug trap.
Figure 17-12. Debug Trap Processing
DBTRAP instruction
DBPC
Restored PC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
PSW
1
1
CPU processing
1
00000060H
Exception processing
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) Restore
Execution is restored from a debug trap by the DBRET instruction.
When the DBRET instruction is executed, the CPU carries out the following processing and transfers control to
the address of the restored PC.
<1> Reads the restored PC and PSW from DBPC and DBPSW.
<2> Transfers control to the fetched address of the restored PC and PSW.
Table 17-13 illustrates the processing for restoring from a debug trap.
Figure 17-13. Processing of Restoration from Debug Trap
DBRET instruction
PC
DBPC
PSW
DBPSW
Jump to address of restored PC
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.6 Interrupt Acknowledgment Time of CPU
Except the following cases, the interrupt acknowledgment time of the CPU is 4 clocks minimum. To input interrupt
request signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt.
• In software STOP mode
• When the external bus is accessed
• When interrupt request non-sampling instructions are successively executed (see 17.7 Periods in Which
Interrupts Are Not Acknowledged by CPU.)
• When an interrupt control register is accessed
Figure 17-14. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline)
4 system clocks
Internal clock
Interrupt request
Instruction 1
Instruction 2
IF
ID EX DF WB
IFX IDX
Interrupt acknowledgment operation
INT1 INT2 INT3 INT4
Instruction (start instruction of
interrupt service routine)
IF
IF
ID EX
Remark INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Invalid instruction fetch
Invalid instruction decode
Interrupt acknowledgment time (internal system clock)
Condition
Internal interrupt
4
External interrupt
Minimum
Maximum
4 +
The following cases are exceptions.
• In IDLE1/IDLE2/Software STOP mode
• External bus access
Analog delay time
6
6 +
• Two or more interrupt request non-sample instructions are
executed in succession
Analog delay time
• Access to peripheral I/O register and programmable
peripheral I/O register
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
17.7 Periods in Which Interrupts Are Not Acknowledged by CPU
An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store, SET1, NOT1, or CLR1 instructions for the following registers.
• Interrupt-related registers:
- Interrupt control register (xxICn), interrupt mask registers 0 to 4 (IMR0 to IMR4)
- In-service priority register (ISPR)
- Command register (PRCMD)
- Power save control register (PSC)
- On-chip debug mode register (OCDM)
- Peripheral emulation register 1 (PEMU1)
Remark xx: Identification name of each peripheral unit (see Table 17-4 Interrupt Control Registers (xxICn))
n: Peripheral unit number (see Table 17-4 Interrupt Control Registers (xxICn)).
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CHAPTER 18 KEY INTERRUPT FUNCTION
18.1 Function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0
to KR7) by setting the key return mode register (KRM).
Table 18-1. Assignment of Key Return Detection Pins
Flag
KRM0
Pin Description
Controls KR0 signal in 1-bit units
Controls KR1 signal in 1-bit units
Controls KR2 signal in 1-bit units
Controls KR3 signal in 1-bit units
Controls KR4 signal in 1-bit units
Controls KR5 signal in 1-bit units
Controls KR6 signal in 1-bit units
Controls KR7 signal in 1-bit units
KRM1
KRM2
KRM3
KRM4
KRM5
KRM6
KRM7
Figure 18-1. Key Return Block Diagram
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
INTKR
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
Key return mode register (KRM)
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CHAPTER 18 KEY INTERRUPT FUNCTION
18.2 Control Register
(1) Key return mode register (KRM)
The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
R/W
Address: FFFFF300H
KRM
KRM7
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
KRMn
Control of key return mode
0
1
Does not detect key return signal
Detects key return signal
Caution Rewrite the KRM register after once clearing the KRM register to 00H.
Remark For the alternate-function pin settings, see Table 4-25 Register Settings to Use Port
Pins as Alternate-Function Pins (3/7)
18.3 Cautions
(1) If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not generated even if the falling edge
of another pin is input.
(2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear
PFCE91 bit to 0).
(3) If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this,
change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag
(KRIC.KRIF bit) to 0, and enable interrupts (EI) or clear the mask.
(4) To use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation
with the KRM register. To switch from the key return pin to the port pin, disable the operation with the KRM
register and then set the port pin.
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CHAPTER 19 STANDBY FUNCTION
19.1 Overview
The power consumption of the system can be effectively reduced by using the standby modes in combination and
selecting the appropriate mode for the application. The available standby modes are listed below.
Table 19-1. Standby Modes
Mode
HALT mode
Functional Outline
Mode in which only the operating clock of the CPU is stopped
IDLE1 mode
Mode in which all the internal operations of the chip except the oscillator, PLLNote, and flash memory
are stopped
IDLE2 mode
Mode in which all the internal operations of the chip except the oscillator are stopped
Mode in which all the internal operations of the chip except the subclock oscillator are stopped
Mode in which the subclock is used as the internal system clock
Software STOP mode
Subclock operation mode
Sub-IDLE mode
Mode in which all the internal operations of the chip except the oscillator, PLLNote, and flash memory
are stopped, in the subclock operation mode
Note The PLL holds the previous operating status (in clock-through mode or PLL mode).
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Figure 19-1. Status Transition Diagram
RESET
RING operation
Note 3
Oscillation
stabilization wait
Each STBY
(HALT/IDLE1/IDLE2/
Software STOP)
X1 main
clock-through
PLL operation
(PLL = ON)
(PLL = ON)
Note 1
X1 main through
(PLL = OFF)
Each STBY
(HALT/IDLE1/IDLE2/
Software STOP)
SUB operation
(X1 = ON)
Each STBY
(HALT/IDLE1/IDLE2/
Software STOP)
(PLL = ON)
STBY (Sub IDLE only)
(X1 = ON)
(PLL = ON)
SUB operation
(X1 = ON)
Note 2
(PLL = OFF)
SUB operation
(X1 = OFF)
(PLL = OFF)
STBY (Sub IDLE only)
STBY (Sub IDLE only)
(X1 = OFF)
(X1 = ON)
(PLL = OFF)
(PLL = OFF)
Notes 1. PLL lockup time is required (LOCK bit of LOCKR register = 1 → 0).
2. Oscillation stabilization time must be secured by program.
Each standby -> PLL operation (PLL=ON)
Each standby -> X1 main clock-through (PLL = ON)
3. If the watchdog timer overflows (reset) while the oscillation stabilization time is being counted, the CPU
starts clock operation with the ring oscillator.
Remark For PLLS and OSTS, refer to CHAPTER 6 CLOCK GENERATION FUNCTION and CHAPTER 19.8(3)
Oscillation stabilization time selection function.
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Figure 19-2. Standby Transition from PLL Operation (PLL = ON)
Note 2
PLL operation
(PLL = ON)
Note 1
HALT mode
Software STOP mode
X1 = OFF, PLL = OFF
X1 = ON, PLL = ON
IDLE1 mode
IDLE2 mode
X1 = ON, PLL = ON
X1 = ON, PLL = OFF
Notes 1. After the lapse of the time set by the OSTS register, the CPU returns to the PLL mode.
2. After the lapse of the time set by the OSTS register, the CPU returns to the PLL mode. If the watchdog
timer overflows (reset) while the oscillation stabilization time is being counted, the CPU starts clock
operation with the ring oscillator.
Remark For OSTS, refer to CHAPTER 19.8(3) Oscillation stabilization time selection function.
Figure 19-3. Standby Transition from X1 Main Clock-Through Operation (PLL = ON)
Note 2
X1 main clock-through mode
(PLL = ON)
Note 1
HALT mode
Software STOP mode
X1 = OFF, PLL = OFF
X1 = ON, PLL = ON
IDLE1 mode
IDLE2 mode
X1 = ON, PLL = ON
X1 = ON, PLL = OFF
Notes 1. After the lapse of the time set by the OSTS register, the CPU returns to the through mode.
2. After the lapse of the time set by the OSTS register, the CPU returns to the through mode. If the
watchdog timer overflows (reset) while the oscillation stabilization time is counted, the CPU starts its
clock operation with the ring oscillator.
Remark For OSTS, refer to CHAPTER 19.8(3) Oscillation stabilization time selection function.
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Figure 19-4. Standby Transition from X1 Main Clock-Through Operation (PLL = OFF)
Note 2
X1 main clock-through mode
(PLL = OFF)
Note 1
HALT mode
Software STOP mode
X1 = OFF, PLL = OFF
X1 = ON, PLL = OFF
IDLE1 mode
IDLE2 mode
X1 = ON, PLL = OFF
X1 = ON, PLL = OFF
Notes 1. After the lapse of the time set by the OSTS register, the CPU returns to the through mode.
2. After the lapse of the time set by the OSTS register, the CPU returns to the through mode. If the
watchdog timer overflows (reset) while the oscillation stabilization time is counted, the CPU starts its
clock operation with the ring oscillator.
Remark For OSTS, refer to CHAPTER 19.8(3) Oscillation stabilization time selection function.
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Figure 19-5. Status Transition Diagram (During Subclock Operation)
Normal operation mode
(main clock operation)
Wait for oscillation
stabilization
End of counting
oscillation
stabilization time
Subclock
operation
setting
Main clock
operation
setting
ResetNote 1
Subclock operation mode
InterruptNote 2
IDLE mode
setting
ResetNote 1
Sub-IDLE mode
Notes 1. Reset by RESET pin input, WDT2RES signal, low voltage detector (LVI), and clock monitor (CLM)
2. Non-maskable interrupt request signal (NMI or INTWDT2), unmasked external interrupt request signal, or
internal maskable interrupt request signal that can operate in the sub-IDLE mode and is not masked
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19.2 HALT Mode
19.2.1 Setting and operation status
When a dedicated instruction (HALT instruction) is executed in the normal operation mode, the HALT mode is set.
In this mode, the clock oscillator continues operating, but clock supply to the CPU is stopped. Clock supply to the
other on-chip peripheral functions continues.
As a result, program execution is stopped, and the contents of the internal RAM before the HALT mode was set are
retained. However, the on-chip peripheral functions that are not dependent upon the instruction processing of the
CPU continue operating.
Table 19-3 shows the operation status in the HALT mode.
The HALT mode can reduce the average current consumption of the system if it is used with the normal operation
mode for intermittent operation.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed while an interrupt request signal is held pending, the HALT
mode is set but is released immediately by the pending interrupt request.
19.2.2 Releasing HALT mode
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input or INTWDT2 signal),
unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can
operate in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal, low voltage detector (LVI), or
clock monitor (CLM)).
When the HALT mode has been released, the normal operation mode is restored.
(1) Non-maskable interrupt request signal and unmasked maskable interrupt request signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt
routine, however, the operation is performed as follows.
(a) If an interrupt request signal having a priority lower than that of the interrupt request currently being
serviced is generated, the HALT mode is released, but the interrupt request with the lower priority is not
acknowledged. The interrupt request signal itself is held.
(b) If an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher
than that of the interrupt request currently being serviced is generated, the HALT mode is released, and
this interrupt request signal is acknowledged.
Table 19-2. Operation After HALT Mode Is Released by Interrupt Request Signal
Releasing Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler
address, or the next instruction is
executed.
The next instruction is executed.
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(2) Releasing by reset input
The operation is the same as the normal reset operation.
Table 19-3. Operation Status in HALT Mode
Setting of HALT Mode
Operation Status
Item
Without Subclock
Oscillation enabled
With Subclock
Main clock oscillator
Subclock oscillator
Ring-OSC generator
PLL
–
Oscillation enabled
Oscillation enabled
Operable
CPU
Stops operation
Operable
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Operable
Operable
Operable
Operable when other than fXT is selected
as the count clock
Operable
Operable
Watch timer
Operable when fX (divided BRG) is
selected as the count clock
Watchdog timer 2
Operable
Operable
Serial interface
CSIB0 to CSIB2
UARTA0 to UARTA3 Operable
CAN controller
Operable
Operable
Operable
A/D converter
Key interrupt function (KR)
External bus interface
Port function
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Holds status before HALT mode is set.
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before HALT mode was set.
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19.3 IDLE1 Mode
19.3.1 Setting and operation status
The IDLE1 mode is set when the PSM1 and PSM0 bits of the PSMR register are cleared to “00” and the STP bit of
the PSC register is set to 1 in the normal operation mode.
In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating, but clock supply to the CPU
and the other on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the IDLE1 mode was set
are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate on the subclock or external clock continue operating.
Table 19-5 shows the operation status in the IDLE1 mode.
The IDLE1 mode can reduce current consumption more than the HALT mode because the operations of the on-
chip peripheral functions are stopped. Because the main clock oscillator is not stopped, however, the normal mode
can be restored without having to secure oscillation stabilization time, in the same manner as in the HALT mode, when
the IDLE1 mode is released.
Caution Insert five or more NOP instructions after the store instruction that manipulates the PSC register
to set the IDLE2 mode.
19.3.2 Releasing IDLE1 mode
The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input or INTWDT2 signal),
unmasked external interrupt request signal, unmasked internal interrupt request signal of a peripheral function that
can operate in the IDLE1 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low voltage detector
(LVI), or clock monitor (CLM)).
When the IDLE1 mode has been released, the normal operation mode is restored.
Cautions 1. Interrupt request signals that are set (disabled) by the NMI1M, NMI0M, and INTM bits of the
PSC register are invalid and do not release the IDLE1 mode.
2. When digital noise elimination is selected by setting of NFC register, and the sampling clock
can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, IDLE1 mode can not
released using INTP3 pin. For detail, refer to 17.3.10 (13) Noise elimination control register.
(1) Non-maskable interrupt request signal and unmasked maskable interrupt request signal
The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt
routine, however, the operation is performed as follows.
(a) If an interrupt request signal having a priority lower than that of the interrupt request currently being
serviced is generated, the IDLE1 mode is released, but the interrupt request with the lower priority is not
acknowledged. The interrupt request signal itself is held.
(b) If an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher
than that of the interrupt request currently being serviced is generated, the IDLE1 mode is released, and
this interrupt request signal is acknowledged.
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Table 19-4. Operation After IDLE1 Mode Is Released by Interrupt Request Signal
Releasing Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler
address, or the next instruction is
executed.
The next instruction is executed.
(2) Releasing by reset input
The operation is the same as the normal reset operation.
Table 19-5. Operation Status in IDLE1 Mode
Setting of IDLE1 Mode
Operation Status
Item
Without Subclock
Oscillation enabled
With Subclock
Main clock oscillator
Subclock oscillator
Ring-OSC generator
PLL
–
Oscillation enabled
Oscillation enabled
Operable
CPU
Stops operation
Stops operation
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Stops operation (however, can be used to release standby mode).
Stops operation
Stops operation
Operable when fR/8 is selected as the
count clock
Operable when fR/8 or fXT is selected as
the count clock
Watch timer
Operable when fX (divided BRG) is
selected as the count clock
Operable
Watchdog timer 2
Operable
Serial interface
CSIB0 to CSIB2
UART0-UART3
Operable when SCKBn input clock is selected as the operating clock (n = 0 to 2)
Stop operation (However, operable when ASCKA0 input clock is selected as the
operating clock)
CAN controller
A/D converter
Stops operation
Stops operationNote
Key interrupt function (KR)
External bus interface
Port function
Operable
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Holds status before IDLE1 mode is set.
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before IDLE1 mode was set.
Note To realize low power consumption, stop the A/D converter before shifting to the IDLE1 mode.
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19.4 IDLE2 Mode
19.4.1 Setting and operation status
The IDLE2 mode is set when the PSM1 and PSM0 bits of the PSMR register are set to “10” and the STP bit of the
PSC register is set to 1 in the normal operation mode.
In the IDLE2 mode, the clock oscillator continues operating, but clock supply to the CPU, PLL, flash memory, and
the other on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the IDLE2 mode was set
are retained. Not only the CPU but also the other on-chop peripheral functions stop operating. However, the on-chip
peripheral functions that can operate on the subclock or external clock continue operating.
Table 19-7 shows the operation status in the IDLE2 mode.
The IDLE2 mode can reduce current consumption more than the IDLE1 mode because the operations of the on-
chop peripheral functions and flash memory are stopped. Because the PLL and flash memory are stopped, however,
setup time for the PLL and flash memory is required after the IDLE2 mode is released.
Caution Insert five or more NOP instructions after the store instruction that manipulates the PSC register
to set the IDLE2 mode.
19.4.2 Releasing IDLE2 mode
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input or INTWDT2 signal),
unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can
operate in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low voltage detector (LVI), or
clock monitor (CLM)). The PLL returns to the operation status before the IDLE2 mode was set.
When the IDLE2 mode has been released, the normal operation mode is restored.
Cautions 1. Interrupt request signals that are set (disabled) by the NMI1M, NMI0M, and INTM bits of the
PSC register are invalid and do not release the IDLE2 mode.
2. When digital noise elimination is selected by setting of NFC register, and the sampling clock
can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, IDLE2 mode can not
released using INTP3 pin. For detail, refer to 17.3.10 (13) Noise elimination control register.
(1) Non-maskable interrupt request signal and unmasked maskable interrupt request signal
The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt
routine, however, the operation is performed as follows.
(a) If an interrupt request signal having a priority lower than that of the interrupt request currently being
serviced is generated, the IDLE2 mode is released, but the interrupt request with the lower priority is not
acknowledged. The interrupt request signal itself is held.
(b) If an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher
than that of the interrupt request currently being serviced is generated, the IDLE2 mode is released, and
this interrupt request signal is acknowledged.
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Table 19-6. Operation After IDLE2 Mode Is Released by Interrupt Request Signal
Releasing Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal Execution branches to the handler address after the specified setup time is
secured.
Maskable interrupt request signal
Execution branches to the handler
address, or the next instruction is
executed after the specified setup
time is secured.
The next instruction is executed after
the specified setup time is secured.
(2) Releasing by reset input
The operation is the same as the normal reset operation.
Table 19-7. Operation Status in IDLE2 Mode
Setting of IDLE2 Mode
Operation Status
Item
Without Subclock
Oscillation enabled
With Subclock
Main clock oscillator
Subclock oscillator
Ring-OSC generator
PLL
–
Oscillation enabled
Oscillation enabled
Stops operation
Stops operation
Stops operation
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Stops operation (however, can be used to release standby mode).
Stops operation
Stops operation
Operable when fR/8 is selected as the
count clock
Operable when fR/8 or fXT is selected as
the count clock
Watch timer
Operable when fX (divided BRG) is
selected as the count clock
Operable
Watchdog timer 2
Operable
Serial interface
CSIB0 to CSIB2
UART0-UART3
Operable when SCKBn input clock is selected as the operating clock (n = 0 to 2)
Stop operation (However, operable when ASCKA0 input clock is selected as the
operating clock)
CAN controller
A/D converter
Stops operation
Stops operationNote
Key interrupt function (KR)
External bus interface
Port function
Operable
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Holds status before IDLE2 mode is set.
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before IDLE2 mode was set.
Note To realize low power consumption, stop the A/D converter before shifting to the IDLE2 mode.
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19.4.3 Securing setup time after release of IDLE2 mode
The main clock oscillator stops operating when the IDLE2 mode is set. Therefore, secure the setup time of ROM
(flash memory) after releasing the IDLE2 mode.
(1) Releasing by non-maskable interrupt request signal or unmasked maskable interrupt request signal
The setup time is secured by setting the OSTS register.
When a source that releases the IDLE2 mode occurs, an internal dedicated timer starts counting in
accordance with the setting of the OSTS register. When this counter overflows, the normal operation mode is
restored.
Oscillation
waveform
Main clock
IDLE mode
status
Interrupt
request
ROM circuit stops.
Counting of setup time
(2) Releasing by reset input (RESET pin input or WDT2RES occurrence)
The operation is the same as the normal reset operation.
The oscillation stabilization time is the default value of the OSTS register, 216/fX.
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19.5 Software STOP Mode
19.5.1 Setting and operation status
The software STOP mode is set when the PSM1 and PSM0 bits of the PSMR register are set to “01” or “11”, and
the STP bit of the PSC register is set to 1 in the normal operation mode.
In the software STOP mode, the subclock oscillator continues operating, but the main clock oscillator stops
operating. Moreover, clock supply to the CPU and the other on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the software STOP mode
was set are retained. Not only the CPU but also the other on-chip peripheral functions stop operating. However, the
on-chip peripheral functions that can operate on the subclock or external clock continue operating.
Table 19-9 shows the operation status in the software STOP mode.
The software STOP mode can reduce current consumption more than the IDLE2 mode because the operation of
the main clock oscillator is stopped. When the subclock oscillator, Ring-OSC, and external clock are not used, the
current consumption can be substantially reduced with only a leakage current flowing.
Caution Insert five or more NOP instructions after the store instruction that manipulates the PSC register
to set the software STOP mode.
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19.5.2 Releasing software STOP mode
The software STOP mode is released by a non-maskable interrupt request signal (NMI pin input or INTWDT2
signal), unmasked external interrupt request signal, unmasked internal interrupt request signal of a peripheral function
that can operate in the software STOP mode, or reset signal (reset by RESET pin input, WDT2RES signal, or low
voltage detector (LVI)).
When the software STOP mode has been released, the normal operation mode is restored.
Cautions 1. Interrupt request signals that are set (disabled) by the NMI1M, NMI0M, and INTM bits of the
PSC register are invalid and do not release the software STOP mode.
2. When digital noise elimination is selected by setting of NFC register, and the sampling clock
can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, Software STOP mode can
not released using INTP3 pin. For detail, refer to 17.3.10 (13) Noise elimination control
register.
(1) Non-maskable interrupt request signal and unmasked maskable interrupt request signal
The software STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable
interrupt request signal, regardless of the priority of the interrupt request signal. If the software STOP mode is
set in an interrupt routine, however, the operation is performed as follows.
(a) If an interrupt request signal having a priority lower than that of the interrupt request currently being
serviced is generated, the software STOP mode is released, but the interrupt request with the lower
priority is not acknowledged. The interrupt request signal itself is held.
(b) If an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher
than that of the interrupt request currently being serviced is generated, the software STOP mode is
released, and this interrupt request signal is acknowledged.
Table 19-8. Operation After Software STOP Mode Is Released by Interrupt Request Signal
Releasing Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal Execution branches to the handler address after the oscillation stabilization
time is secured.
Maskable interrupt request signal
Execution branches to the handler
address, or the next instruction is
executed the after the oscillation
stabilization time is secured.
The next instruction is executed after
the oscillation stabilization time is
secured.
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(2) Releasing by reset input
The operation is the same as the normal reset operation.
Table 19-9. Operation Status in Software STOP Mode
Setting of Software STOP
Mode
Operation Status
Without Subclock
Stops oscillation
With Subclock
Item
Main clock oscillator
Subclock oscillator
Ring-OSC generator
PLL
–
Oscillation enabled
Oscillation enabled
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Operable when fR/8 is selected as the
count clock
Operable when fR/8 or fXT is selected as
the count clock
Watch timer
Stops operation
Operable when fXT is selected as the
count clock
Watchdog timer 2
Operable when fR is selected as the count clock
Serial interface
CSIB0 to CSIB2
UART0-UART3
Operable when SCKBn input clock is selected as the operating clock (n = 0 to 2)
Stop operation (However, operable when ASCKA0 input clock is selected as the
operating clock)
CAN controller
A/D converter
Stops operation
Stops operationNote
Key interrupt function (KR)
External bus interface
Port function
Operable
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Holds status before software STOP mode is set.
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before software STOP mode was set.
Notes: 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically
stopped and it starts operating again after the STOP mode is released. However, in that case, the A/D
conversion results up to the second conversion after the STOP mode is released are invalid (the third
or later conversion results are valid). All the A/D conversion results before the STOP mode is set are
invalid.
2. Even if the STOP mode is set while the A/D converter is operating, the power consumption is
reduced equivalently to when the A/D converter is stopped before the STOP mode is set.
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19.5.3 Securing setup time after release of software STOP mode
The main clock oscillator stops operating when the software STOP mode is set. Therefore, secure the oscillation
stabilization time of the main clock oscillator after releasing the software STOP mode.
(1) Releasing by non-maskable interrupt request signal or unmasked maskable interrupt request signal
The oscillation stabilization time is secured by setting the OSTS register.
When a source that releases the software STOP mode occurs, an internal dedicated timer starts counting in
accordance with the setting of the OSTS register. When this counter overflows, the normal operation mode is
restored.
Oscillation
waveform
Main clock
IDLE mode
status
Interrupt
request
ROM circuit stops
Counting of setup time
(2) Releasing by reset input
The operation is the same as the normal reset operation.
The oscillation stabilization time is the default value of the OSTS register, 216/fX.
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19.6 Subclock Operation Mode
19.6.1 Setting and operation status
The subclock operation mode is set when the CK3 bit of the PCC register is set to 1 in the normal operation mode.
When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
Check that the system clock has been changed by using the CLS bit of the PCC register.
When the MCK bit of the PCC register is set to 1, the operation of the main clock oscillator is stopped.
Consequently, the entire system operates on only the subclock.
In the subclock operation mode, the subclock is used as the internal system clock, so that the current consumption
can be reduced from that in the normal operation mode. In addition, a current consumption close to that in the
software STOP mode can be realized by stopping the operation of the main clock oscillator.
Table 19-10 shows the operation status in the subclock operation mode.
Caution Changing the set value of the CK2 to CK0 bits of the PCC register is prohibited when the CK3 bit
is manipulated (0→1 or 1→0) (set the CK3 bit by using a bit manipulation instruction). For details
of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).
19.6.2 Releasing subclock operation mode
The subclock operation mode is released by clearing the CK3 bit to 0 or by a reset signal (reset by RESET pin
input, WDT2RES signal, low voltage detector (LVI), or clock monitor (CLM)).
When the main clock is stopped (MCK bit = 1), clear the MCK bit to 0, secure the oscillation stabilization time of the
main clock by software, and then clear the CK3 bit to 0.
When the subclock operation mode is released, the normal operation mode is restored.
Cautions 1. Changing the set value of the CK2 to CK0 bits of the PCC register is prohibited when the CK3
bit is manipulated (0→1 or 1→0) (set the CK3 bit by using a bit manipulation instruction). For
details of the PCC register, refer to 6.3 (1) Processor clock control register (PCC).
2. When digital noise elimination is selected, and the sampling clock can be selected from
among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, subclock operation mode can not released
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Table 19-10. Operation Status in Subclock Operation Mode
Setting of Subclock
Operation Mode
Operation Status
With Main Clock
Oscillation enabled
Without Main Clock
Item
Subclock oscillator
Ring-OSC generator
PLL
Oscillation enabled
Operable
Stops operationNote
CPU
Operable
DMA
Operable
Interrupt controller
Operable
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Operable
Stops operation
Stops operation
Operable
Operable
Operable when fR/8 or fXT is selected as
the count clock
Watch timer
Operable
Operable
Operable
Operable
Operable when fXT is selected as the
count clock
Watchdog timer 2
Operable when fR is selected as the
count clock
Serial interface
CSIB1 to CSIB2
Operable when SCKBn input clock is
selected as the operating clock (n = 0 to 2)
UART0-UART3
Stop operation (However, operable when
ASCKA0 input clock is selected as the
operating clock)
CAN controller
A/D converter
Operable
Operable
Operable
Stops operation
Stops operation
Key interrupt function (KR)
External bus interface
Port function
Refer to CHAPTER 5 BUS CONTROL FUNCTION.
Settable
Settable
Internal data
Note When stopping the main clock, be sure to stop the PLL (by clearing the PLLON bit of the PLLCTL register to 0).
Caution: When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a
register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset
(see 3.4.10 (2)).
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19.7 Sub-IDLE Mode
19.7.1 Setting and operation status
The sub-IDLE mode is set when the PSM1 and PSM0 bits of the PSMR register are set to “10” and the STP bit of
the PSC register is set to 1 in the subclock operation mode.
In the sub-IDLE mode, the clock oscillator continues operating, but clock supply to the CPU, flash memory, and the
other on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the sub-IDLE mode was set
are retained. Not only the CPU but also the other on-chip peripheral functions stop operating. However, the on-chip
peripheral functions that can operate on the subclock or external clock continue operating.
The sub-IDLE mode can reduce current consumption more than the subclock operation mode because the
operations of the CPU, flash memory, and other on-chip peripheral functions are stopped.
If the sub-IDLE mode is set after the main clock is stopped, a current consumption close to that in the software
STOP mode can be realized.
Table 19-12 shows the operation status in the sub-IDLE mode.
Caution Insert five or more NOP instructions after the store instruction that manipulates the PSC register
to set the sub-IDLE mode.
19.7.2 Releasing sub-IDLE mode
The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input or INTWDT2 signal),
unmasked external interrupt request signal, unmasked internal interrupt request of a peripheral function that can
operate in the sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES signal, low voltage detector (LVI),
or clock monitor (CLM)). The PLL returns to the operation status before the sub-IDLE mode was set.
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is restored.
When the sub-IDLE mode is released by reset, the normal operation mode is restored.
Cautions:1. Interrupt request signals that are set (disabled) by the NMI1M, NMI0M, and INTM bits of the
PSC register are invalid and do not release the sub-IDLE mode.
2. When digital noise elimination is selected by setting of NFC register, and the sampling clock
can be selected from among fXX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, sub IDLE mode can not
released using INTP3 pin. For detail, refer to 17.3.10 (13) Noise elimination control register.
(1) Non-maskable interrupt request signal and unmasked maskable interrupt request signal
The sub-IDLE mode is released by a non-maskable interrupt signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal.
If the sub-IDLE mode is set in an interrupt routine, however, the operation is performed as follows.
(a) If an interrupt request signal having a priority lower than that of the interrupt request currently being
serviced is generated, the sub-IDLE mode is released, but the interrupt request with the lower priority is
not acknowledged. The interrupt request signal itself is held.
(b) If an interrupt request signal (including a non-maskable interrupt request signal) having a priority higher
than that of the interrupt request currently being serviced is generated, the sub-IDLE mode is released,
and this interrupt request signal is acknowledged.
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Table 19-11. Operation After Sub-IDLE Mode Is Released by Interrupt Request Signal
Releasing Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler
address, or the next instruction is
executed.
The next instruction is executed.
(2) Releasing by reset input
The operation is the same as the normal reset operation.
Table 19-12. Operation Status in Sub-IDLE Mode
Setting of Sub-IDLE Mode
Operation Status
Item
With Main Clock
Oscillation enabled
Without Main Clock
Subclock oscillator
Ring-OSC generator
PLL
Oscillation enabled
Operation enabled
Stops operation
Stops operation
Stops operationNote
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP3)
Timer Q (TMQ0 to TMQ3)
Timer M (TMM0)
Watch timer
Stops operation (however, can be used to release standby mode)
Stops operation
Stops operation
Operable when fR/8 or fXT is selected as the count clock
Operation enabled
Operable when fXT is selected as the
count clock
Watchdog timer 2
Operable when fR is selected as the count clock
Serial interface
CSIB0 to CSIB2
UART0-UART3
Operable when SCKBn input clock is selected as the operating clock (n = 0 to 2)
Stop operation (However, operable when ASCKA0 input clock is selected as the
operating clock)
CAN controller
A/D converter
Stops operation
Stops operation
Operable
Key interrupt function (KR)
External bus interface
Refer to CHAPTER 5 BUS CONTROL FUNCTION (same operation status as in
IDLE1 and IDLE2 modes).
Port function
Internal data
Holds status before sub-IDLE mode is set.
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before sub-IDLE mode was set.
Note When stopping the main clock, be sure to stop the PLL (by clearing the PLLON bit of the PLLCTL register to 0).
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19.8 Control Registers
(1) Power save control register (PSC)
This is an 8-bit register that controls the standby function. The STP bit of this register specifies the standby
mode. This register is a special register and can be written only in a combination of specific sequences (refer
to 3.4.9 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF1FEH
5
4
3
0
2
0
1
0
0
PSC
0
NMI1M
NMI0M
INTM
STP
NMI1M
Standby mode release control by occurrence of INTWDT2 signal
0
1
Enable releasing standby mode by INTWDT2 signal.
Disable releasing standby mode by INTWDT2 signal.
NMI0M
Standby mode release control by NMI pin input
Enable releasing standby mode by NMI pin input.
0
1
Disable releasing standby mode by NMI pin input.
INTM
Standby mode release control by maskable interrupt request signal
Enable releasing standby mode by maskable interrupt request signal.
Disable releasing standby mode by maskable interrupt request signal.
0
1
STP
0
Setting of standby modeNote
Normal mode
Standby mode
1
Note Standby modes that can be set by the STP bit: IDLE1 mode, IDLE2 mode, software STOP mode,
and sub-IDLE mode
Caution Before setting the IDLE1, IDLE2, software STOP mode, or sub-IDLE mode, set the
PSM1 and PSM0 bits of the PSMR register.
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(2) Power save mode register (PSMR)
This is an 8-bit register that controls the operating status of the power save mode and the operation of the
clock.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF820H
5
0
4
0
3
0
2
0
1
0
PSMR
0
0
PSM1
PSM0
PSM1
PSM0
Specification of operation in software standby mode
0
0
1
1
0
1
0
1
IDLE1 mode, Sub-IDLE mode
Software STOP mode, Sub-IDLE mode
IDLE2 mode, Sub-IDLE mode
Software STOP mode
Cautions 1. Be sure to clear bits 2 to 7 to 0.
2. The PSM0 and PSM1 bits are valid only when the STP bit = 1.
Remark IDLE1: Mode used to stop all the operations except the oscillator and some circuits (flash
memory and PLL). When IDLE1 mode is released, the normal operation mode is
restored without the lapse of the oscillation stabilization time, in the same manner as
in the HALT mode.
IDLE2: In this mode, all operations except the oscillator operation are stopped. After the
IDLE2 mode is released, the normal operation mode is restored following the lapse
of the setup time specified by the OSTS register (flash memory and PLL).
Sub-IDLE: Mode used to stop all the operations except the oscillator. After the sub-IDLE mode
is released, the setup time (for flash memory and PLL) specified by the OSTS
register elapses, and then the normal operation mode is restored.
STOP: Mode used to stop all the operations except the subclock oscillator. After the
software STOP mode is released, the oscillation stabilization time specified by the
OSTS register elapses, and then the normal operation mode is restored.
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(3) Oscillation stabilization time selection function
The wait time until the oscillation stabilizes after the software STOP mode is released is controlled by the
OSTS register.
The OSTS register can be read or written 8-bit units.
Reset input sets this register to 06H.
After reset: 06H
R/W
0
Address: FFFFF6C0H
OSTS
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0 Selection of oscillation stabilization time/setup timeNote
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
210/f
211/f
212/f
213/f
214/f
215/f
216/f
X
X
X
X
X
X
X
Setting prohibited
Note The oscillation stabilization time and setup time are required when the software STOP mode and idle
mode are released, respectively.
Cautions 1. The wait time following release of the software STOP mode does not include the time until
the clock oscillation starts (“a” in the figure below) following release of the software STOP
mode, regardless of whether the software STOP mode is released by RESET input or the
occurrence of an interrupt request signal.
STOP mode release
Voltage waveform of X1 pin
a
VSS
2. Be sure to clear bits 3 to 7 to 0.
3. The oscillation stabilization time following reset release is 216/fX (because the initial value of
the OSTS register = 06H).
Remark fX = Oscillation frequency
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CHAPTER 20 RESET FUNCTION
20.1 Overview
Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
The reset function is outlined below.
(1) Five types of reset sources
• Reset function by RESET pin input
• Reset function by overflow of watchdog timer 2 (WDT2RES)
• System reset by low voltage detector (LVI) (see CHAPTER 23 LOW VOLTAGE DETECTOR)
• System reset by clock monitor (CLM) (see CHAPTER 21 CLOCK MONITOR)
• System reset by power-on clear circuit (POC) (see CHAPTER 22 POWER-ON CLEAR CIRCUIT)
It can be check reset source by reset source flag register (RESF) after reset has been released.
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
Caution: When the CPU is being operated via the internal oscillator, access to the register in which a wait
state is generated is prohibited. For the register in which a wait state is generated, refer to 3.4.10
(2) Accessing specific on-chip peripheral I/O registers.
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20.2 Register to Check Reset Source
(1) Reset source flag register (RESF)
The RESF register is a special register that can be written only by a combination of specific sequences (see
3.4.9 Special registers).
The RESF register indicates the source from which a reset signal is generated.
This register is read or written in 8-bit or 1-bit units.
RESET pin input clears this register to 00H. The default value differs if the source of reset is other than the
RESET pin signal.
After reset: 00HNote
7
R/W
6
Address: FFFFF888H
5
0
4
3
0
2
0
1
0
RESF
0
0
WDT2RF
CLMRF
LVIRF
WDT2RF
Generation of reset signal from WDT2
0
1
Not generated
Generated
CLMRF
Generation of reset signal from clock monitor
0
1
Not generated
Generated
LVIRF
Generation of reset signal from low voltage detector
0
1
Not generated
Generated
Note This register holds 00H after a reset by the RESET pin, or sets its reset flags (WDT2RF,
CLMRF, and LVIRF bits) after a reset by the WDT2RES signal, low voltage detector (LVI), or
clock monitor (CLM) (the other sources are held).
Caution Only 0 can be written to each bit. If writing 0 and flag setting (occurrence of reset)
conflict, flag setting takes precedence.
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20.3 Operation
20.3.1 Reset operation by RESET pin
When a low level is input to the RESET pin, the system is reset, and each hardware is initialized.
When the level of the RESET pin input is changed from low to high, the reset status is released.
If the reset status is released by input to the RESET pin, the oscillation stabilization time (reset value of the OSTS
register: 216/fX) elapses, and then the CPU starts program execution.
Table 20-1. Hardware Status When Signal Is Input to RESET Pin
Item
Main clock oscillator (fX)
Subclock oscillator (fXT):
X'tal
During Reset
Stops oscillation
After Reset
Starts oscillation
X'tal ->Continues oscillation
RC ->Stops oscillation
Stops oscillation
X'tal ->Continues oscillation
RC ->Starts oscillation
Starts oscillation
RC
Ring-OSC generator
Peripheral clock (fX to fX/1,024)
Stops operation
Starts operation after oscillation
stabilization time
Internal system clock (fXX), CPU clock (fCPU)
CPU
Stops operation
Starts operation after oscillation
stabilization time (initialized to fXX/8)
Initialized
Program execution starts after
oscillation stabilization time
Watchdog timer 2
Internal RAM
Stops operation
Starts operation
Undefined after a reset while power is on or if a data access to RAM (by the
CPU) and a reset input conflict (data corrupted). Otherwise, retains value
immediately before reset inputNote
.
I/O lines (port/alternate-function pins)
On-chip peripheral I/O registers
Other on-chip peripheral functions
High impedance
Initialized to specified status. OCDM register is reset (01H).
Stop operation
Start operation after oscillation
stabilization time
Note Because the V850ES/FX2 supports a boot swap function, the firmware uses part of the internal RAM after
the internal system reset is released. For details see 20.4 RAM usage after RESET release.
Caution The on-chip debug mode (flash memory products only) may be set depending on the pin status
after reset has been released. For details, refer to CHAPTER 4 PORT FUNCTIONS.
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Figure 20-1. Timing of Reset Operation by RESET Pin Input
f
X
f
CLK
Initialized to fXX/8 operation
RESET
Analog delay
(eliminated as noise)
Analog
delay
Analog
delay
Analog
delay
Internal system
reset signal
Counting of oscillation
stabilization time
Timer for oscillation
stabilization overflows
Figure 20-2. Timing of Power-on Reset Operation
VDD
f
X
f
CLK
Initialized to fXX/8 operation
RESET
Analog delay
Internal system
reset signal
Counting of oscillation
stabilization time
Must be 1
µ
s or more.
Timer for oscillation
stabilization overflows
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20.3.2 Reset operation by WDT2RES signal
If the mode in which a reset operation is performed when watchdog timer 2 overflows is set, if watchdog timer 2
overflows (generating the WDT2RES signal), the system is reset and each hardware is initialized to the specified
status.
After watchdog timer 2 overflows, the reset status lasts for a specific time (analog delay). Then the reset status is
automatically released. After the reset status is released, the oscillation stabilization time of the main clock oscillator
elapses (default value of OSTS register: 216/fX), and the CPU starts program execution.
The main clock oscillator is stopped during the reset period.
Table 20-2. Hardware Status After Generation of WDT2RES Signal
Item
Main clock oscillator (fX)
Subclock oscillator (fXT):
X'tal
During Reset
Stops oscillation
After Reset
Starts oscillation
X'tal ->Continues oscillation
RC ->Stops oscillation
Stops oscillation
X'tal ->Continues oscillation
RC ->Starts oscillation
Starts oscillation
RC
Ring-OSC generator
Peripheral clock (fX to fX/1,024)
Stops operation
Starts operation after oscillation
stabilization time
Internal system clock (fXX),
CPU clock (fCPU)
Stops operation
Starts operation after oscillation
stabilization time (initialized to fXX/8)
CPU
Initialized
Program execution starts after
oscillation stabilization time
Watchdog timer 2
Internal RAM
Stops operation
Starts operation
Undefined after a reset while power is on or if a data access to RAM (by the
CPU) and a reset input conflict (data corrupted). Otherwise, retains value
immediately before reset inputNote
.
I/O lines (port/alternate-function pins)
On-chip peripheral I/O registers
Other on-chip peripheral functions
High impedance
Initialized to specified value. OCDM register retains its value.
Stop operation
Start operation after oscillation
stabilization time
Note Because the V850ES/FX2 supports a boot swap function, the firmware uses part of the internal RAM after
the internal system reset is released. For details see 20.4 RAM usage after RESET release.
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Figure 20-3. Timing of Reset Operation by Generation of WDT2RES Signal
fX
f
CLK
Initialized to fXX/8 operation
WDT2RES
Analog delay
Internal system
reset signal
Analog delay
Counting of oscillation
stabilization time
Timer for oscillation
stabilization overflows
20.3.3 Reset operation by power-on clear (only on-chip products of the power-on clear function)
If the supply voltage falls below the voltage detected by comparison supply voltage and detection voltage when
power-on clear operation is enabled (incl. when power input), a system reset is executed, and the hardware is
initialized to the initial status.
The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the
detection voltage. Then, reset status is released automatically. After reset release, the oscillation stabilization time of
main clock oscillator (default value of OSTS register: 2^16/fx) is ensured, and CPU is started program execution. For
details, refer to CHAPTER 22 POWER-ON CLEAR.
20.3.4 Reset operation by low-voltage detector
If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a
system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status.
The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the
LVI detection voltage.
After reset release, the oscillation stabilization time of main clock oscillator (default value of OSTS register: 2^16/fx)
is ensured, and CPU is started program execution. For details, refer to CHAPTER 23 LOW-VOLTAGE DETECTOR.
20.3.5 Reset operation by clock monitor
When operation of the clock monitor is enabled, the main clock is monitored by using the internal oscillator. Then,
when oscillation stop of the main clock is detected, system reset is executed and each hardware is initialized to the
initial status. For details, refer to CHAPTER 21 CLOCK MONITOR.
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20.4 RAM usage after RESET release
Because the V850ES/Fx2 supports a boot swap function, the firmware uses part of the internal RAM after the internal
system reset is released. Therefore the contents of some areas of the RAM are not retained even when power-on
reset is executed.
The used RAM areas after RESET are for all products the
first 150 bytes at the lower side and
the last 100 bytes at the upper side.
The detailed affected addresses are:
Part number (RAM) 150 BYTE LOWER SIDE 100 BYTE UPPER SIDE
D70F3231 (6K)
D70F3232 (12K)
D70F3233 (12K)
D70F3234 (6K)
D70F3235 (12K)
D70F3236 (16K)
D70F3237 (16K)
D70F3238 (20K)
D70F3239 (20K)
3FFD800
3FFC000
3FFC000
3FFD800
3FFC000
3FFB000
3FFB000
3FFA000
3FFA000
3FFD895
3FFC095
3FFC095
3FFD895
3FFC095
3FFB095
3FFB095
3FFA095
3FFA095
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEF9B
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
3FFEFFF
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CHAPTER 21 CLOCK MONITOR
21.1 Function of Clock Monitor
The clock monitor samples the main clock by using the on-chip Ring-OSC and generates a reset request signal
when oscillation of the main clock is stopped.
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by
any means other than reset.
The clock monitor automatically stops under the following conditions.
• While oscillation stabilization time is being counted after software STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS
bit = 0 during main clock operation)
• When the sampling clock is stopped (Ring-OSC)
• When the CPU operates with Ring-OSC
21.2 Configuration of Clock Monitor
The clock monitor consists of the following hardware.
Table 21-1. Configuration of Clock Monitor
Item
Configuration
Clock monitor mode register (CLM)
Control register
Figure 21-1. CLM Block Diagram
Main clock
Internal reset signal
Ring-OSC clock
Enable/disable
CLME
Clock monitor mode
register (CLM)
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21.3 Register Controlling Clock Monitor
The clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
This register is a special register and can be written only in a combination of specific sequences (refer to 3.4.9
Special registers).
This register is used to set the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF870H
5
0
4
0
3
0
2
0
1
0
0
CLM
0
0
CLME
CLME
Clock monitor operation enable or disable
0
1
Disable clock monitor operation.
Enable clock monitor operation.
Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other
than reset.
2. If reset is occurred for clock monitor, CLME bit is clear (0), and RESF, CLMRF bit is
set (1).
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21.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
Enabling operation by setting bit 0 (CLME) of the clock monitor mode register to 1
<Stop conditions>
• While oscillation stabilization time is being counted after software STOP mode is released
• When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the
PCC.CLS bit = 0 during main clock operation)
• When the sampling clock is stopped (Ring-OSC)
• When the CPU operates using Ring-OSC
Table 21-2. Operation Status of Clock Monitor (When CLM.CLME Bit = 1, During Ring-OSC Operation)
CPU Operating Clock
Main clock
Operation Mode
Status of Main Clock
Status of Ring-OSC
Clock
Status of Clock
Monitor
HALT mode
Oscillates
Oscillates
OscillatesNote 1
OscillatesNote 1
OperatesNote 2
IDLE1 mode,
OperatesNote 2
IDLE2 mode
Software STOP mode
Sub-IDLE mode
Stops
OscillatesNote 1
OscillatesNote 1
Stops
Subclock (MCK bit of
PCC register = 0)
Oscillates
OperatesNote 2
Subclock (MCK bit of
PCC register = 1)
Sub-IDLE mode
Stops
OscillatesNote 1
Stops
Ring-OSC clock
During reset
–
–
Stops
Stops
StopsNote 1
Stops
Stops
Stops
Notes 1. Ring-OSC can be stopped by setting the RSTOP bit of the RCM register to 1 only when “Ring-OSC: Can
be stopped” is specified by an option function.
2. The clock monitor is stopped while Ring-OSC is stopped.
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(1) Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as
shown in Figure 21-2.
Figure 21-2. When Oscillation of Main Clock Is Stopped
Four Ring-OSC clocks
Main clock
Ring-OSC clock
Internal reset
signal
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CHAPTER 21 CLOCK MONITOR
(2) Operation in software STOP mode or after software STOP mode is released
If the software STOP mode is set with the CLME bit = 1, the monitor operation is stopped in the software STOP
mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the
monitor operation is automatically started.
Figure 21-3. Operation in Software STOP Mode or After Software STOP Mode Is Released
Normal
operation
CPU
operation
Software STOP Oscillation stabilization time
Normal operation
Main clock
Oscillation stabilization time
(set by OSTS register)
Oscillation stops
Ring-OSC clock
CLME
Clock monitor
status
During
monitor
Monitor stops
During monitor
(3) Operation when main clock is stopped (arbitrary)
During subclock operation (CLS bit of the PCC register = 1) or when the main clock is stopped by setting the
MCK bit of the PCC register to 1, the monitor operation is stopped until the main clock operation is started
(CLS bit of PCC register = 0). The monitor operation is automatically started when the main clock operation is
started.
Figure 21-4. Operation When Main Clock Is Stopped (Arbitrary)
Subclock operation
Main clock operation
CPU
operation
PCCMCK bit = 1
Oscillation stabilization
time count by software
Main clock
Oscillation stabilization time
(set by OSTS register)
Oscillation stops
Ring-OSC clock
CLME
Clock monitor
status
During
monitor
Monitor stops
Monitor stops
During monitor
(4) Operation while CPU is operating on Ring-OSC clock (CCLSF bit of CCLS register = 1)
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
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CHAPTER 22 POWER-ON CLEAR CIRCUIT
22.1 Functions of Power-on Clear Circuit
The power-on clear (POC) circuit has the following functions.
• Generates an internal reset signal upon power application.
• Compares the supply voltage (VDD) and detected voltage (VPOC0), and generates an internal reset signal when
VDD < VPOC0.
The following choice can be made depending on the product.
• POC is disabled.
• POC can be used (detected voltage: VPOC0 = 3.7 V (Typ.))
Caution If the internal reset signal is generated by the POC circuit, the reset source flag register (RESF) is
cleared (to 00H).
Remarks 1. This product has several hardware units that generate an internal reset signal. When reset is
effected by watchdog timer 2 (WDT2RES), the low-voltage detector (LVI), or the clock monitor
(CLM), a flag that identifies the reset source is provided in the reset source flag register (RESF). If
an internal reset signal is generated by WDT2RES, LVI, or the clock monitor, RESF is not cleared
(00H) but the corresponding flag is set (1). For details of RESF, refer to CHAPTER 20 RESET
FUNCTION.
2. The time when it consumes to the program start from the power supply input is The time from
power supply input to reset released + 16 ms in case of the frequency that is connected outside is
5 MHz. But this time is influenced by the outside factor (The condition of power supply that supplies
to microcomputer).
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CHAPTER 22 POWER-ON CLEAR CIRCUIT
22.2 Configuration of Power-on Clear Circuit
Figure 22-1 shows the block diagram of the power-on clear circuit.
Figure 22-1. Block Diagram of Power-on Clear Circuit
V
DD
+
Internal reset
signal
−
Detected
voltage source
(VPOC0
)
22.3 Operation of Power-on Clear Circuit
The power-on clear circuit compares the supply voltage (VDD) and detected voltage (VPOC0), and generates an
internal reset signal when VDD < VPOC0.
Figure 22-2. Timing of Internal Reset Signal Generation by Power-on Clear Circuit
Supply voltage
(VDD
)
POC detected
voltage (VPOC0
)
Delay
Time
Internal reset
signal
Reset period
(excluding oscillation
stabilization time)
Reset period
(excluding oscillation
stabilization time)
Reset period
(excluding oscillation
stabilization time)
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CHAPTER 23 LOW-VOLTAGE DETECTOR
23.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has the following functions.
• Compares the supply voltage (VDD) and detected voltage (VLVII) and generates an internal interrupt signal or
internal reset signal when VDD < VLVI.
• The level of the supply voltage to be detected can be changed by software (in two steps).
• Interrupt or reset signal can be selected by software.
• Can operate in STOP mode too.
• Operation can be stopped by software.
If the low-voltage detector is used to generate a reset signal, bit 0 (LVIRF) of the reset source flag register (RESF)
is set to 1 when the reset signal is generated. For details of RESF, refer to CHAPTER 20 RESET FUNCTION.
23.2 Configuration of Low-Voltage Detector
Figure 23-1 shows the block diagram of the low-voltage detector.
Figure 23-1. Block Diagram of Low-Voltage Detector
V
DD
V
DD
Low
voltage
detection
level
N-ch
Internal reset signal
+
selector
−
INTLVI
Detected voltage
source (VLVI
)
LVIF
LVIS0
LVIMD
LVION
Low voltage detection level
selection register (LVIS)
Low voltage detection
register (LVIM)
Internal bus
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CHAPTER 23 LOW-VOLTAGE DETECTOR
23.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low voltage detection register (LVIM)
• Low voltage detection level selection register (LVIS)
(1) Low voltage detection register (LVIM)
This register is a special register and can be written only in a combination of specific sequences (refer to 3.4.9
Special registers).
The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the low-
voltage detector.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF890H
5
0
4
0
3
0
2
0
1
0
LVIM
LVION
0
LVIMD
LVIF
LVION
Low voltage detection operation enable or disable
0
1
Disable operation.
Enable operation.
LVIMD
Selection of operation mode of low voltage detection
0
1
Generate interrupt request signal INTLVI when supply voltage < detected voltage.
Generate internal reset signal LVIRES when supply voltage < detected voltage.
LVIF
Low voltage detection flag
0
1
When supply voltage > detected voltage, or when operation is disabled
Supply voltage of connected power supply < detected voltage
Cautions 1. After setting the LVION bit to 1, wait for 0.2 ms (Max.) before checking the voltage
using the LVIF bit.
2. The value of the LVIF flag is output as the output signal INTLVI when the LVION bit
= 1 and LVIMD bit = 0.
3. The LVIF bit is read-only.
4. Be sure to clear bits 2 to 6 to 0.
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CHAPTER 23 LOW-VOLTAGE DETECTOR
(2) Low voltage detection level selection register (LVIS)
The LVIS register is used to select the level of low voltage to be detected.
This register can be read or written in 8-bit or 1-bit units.
Reset input clears this register to 00H.
After reset: 00H
7
R/W
6
Address: FFFFF891H
5
0
4
0
3
0
2
0
1
0
0
LVIS
0
0
LVIS0
LVIS0
Detection level
0
1
4.4 V (Typ.)
4.2 V (Typ.)
Cautions: 1. This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits are
set to 1.
2. Be sure to clear bits 7 to 1 to 0.
(3) Internal RAM data status register (RAMS)
The RAMS register is a flag register that indicates whether the internal RAM is valid or not.
This register can be read or written in 8-bit or 1-bit unitsNote 1
Reset inputNote 2 sets this register to 01H.
.
Notes 1. This register can be written only in a specific sequence.
2. Setting conditions: Detection of voltage lower than specified level
Set by instruction
Generation of reset signal by WDT2
Generation of reset signal while RAM is being accessed
Generation of reset signal by clock monitor
Clearing condition: Writing of 0 in specific sequence
After reset: 01H
7
R/W
6
Address: FFFFF892H
5
0
4
0
3
0
2
0
1
0
0
RAMS
0
0
RAMF
RAMF
Internal RAM data valid/invalid
0
1
Valid
Invalid
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CHAPTER 23 LOW-VOLTAGE DETECTOR
(4) Peripheral emulation register 1 (PEMU1)
When an in-circuit emulator is used, the operation of the RAM retention flag (RAMF bit: bit 0 of RAMS register)
can be pseudo-controlled and emulated by manipulating this register on the debugger.
This register is valid only in the emulation mode. It is invalid in the normal mode.
After reset: 00H
R/W
Address: FFFFF9FEH
7
6
0
5
0
4
0
3
0
2
1
0
0
0
PEMU1
0
EVARAMIN
EVARAMIN
Pseudo specification of RAM retention voltage detection signal
0
1
Do not detect voltage lower than RAM retention voltage.
Detect voltage lower than RAM retention voltage (set RAMF flag).
Caution This bit is not automatically cleared.
[Usage]
When an in-circuit emulator is used, pseudo emulation of RAMF is realized by rewriting this register on the
debugger.
<1> CPU break (CPU operation stops.)
<2> Set the EVARAMIN bit to 1 by using a register write command.
By setting the EVARAMIN bit to 1, the RAMF bit is set to 1 on hardware (the internal RAM data is invalid).
<3> Clear the EVARAMIN bit to 0 by using a register write command again.
Unless this operation is performed (clearing the EVARAMIN bit to 0), the RAMF bit cannot be cleared to 0
by a CPU operation instruction.
<4> Run the CPU and resume emulation.
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CHAPTER 23 LOW-VOLTAGE DETECTOR
23.4 Operation of Low-Voltage Detector
Depending on the setting of the LVIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated.
How to specify each operation is described below, together with timing charts.
23.4.1 To use for internal reset signal
<To start operation>
<1> Mask the interrupt of LVI.
<2> Select the voltage to be detected by using the LVIS0 bit.
<3> Set the LVION bit to 1 (to enable operation).
<4> Insert a wait cycle of 0.2 ms (Max.) or more by software.
<5> By using the LVIF bit, check if the supply voltage > detected voltage.
<6> Set the LVIMD bit to 1 (to generate an internal reset signal).
Caution If LVIMD is set to 1, the contents of the LVIM and LVIS registers cannot be changed until a reset
request other than LVI is generated.
Figure 23-2. Operation Timing of Low-Voltage Detector (LVIMD = 1)
Supply voltage
(VDD
)
LVI detected
voltage
POC detected
voltage
Time
Set (by instruction, refer
to <3> above.)
Clear
(by POC reset request signal)
LVION bit
Delay
Delay
Delay
Delay
Delay
LVI detected
signal
LVI reset
request signal
Clear by
instruction
LVIRF bitNote 1
Delay
Delay
Delay
POC reset
request signal
Internal reset signal
(active low)
Note 2
Notes 1. The LVIRF bit is bit 0 of the reset source flag register (RESF). For details of RESF, refer to CHAPTER
20 RESET FUNCTION.
2. During the period in which the supply voltage is the set low voltage or lower, the internal reset signal
is retained (internal reset state).
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CHAPTER 23 LOW-VOLTAGE DETECTOR
23.4.2 To use for interrupt
<To start operation>
<1> Mask the interrupt of LVI.
<2> Select the voltage to be detected by using the LVIS0 bit.
<3> Set the LVION bit to 1 (to enable operation).
<4> Insert a wait cycle of 0.2 ms (Max.) or more by software.
<5> By using the LVIF bit, check if the supply voltage > detected voltage.
<6> Clear the interrupt request flag of LVI.
<7> Unmask the interrupt of LVI.
<To stop operation>
Clear the LVION bit to 0.
Figure 23-3. Operation Timing of Low-Voltage Detector (LVIM = 0)
Supply voltage
(VDD
)
LVI detected
voltage
POC detected
voltage
Time
Set (by instruction, refer
to <3> above.)
Clear
(by POC reset request signal)
LVION bit
Delay
Delay
Delay
Delay
Delay
LVI detected
signal
Generation of
interrupt
Generation of
interrupt
request
request
INTLVI signal
LVIF bit
(bit 0 of LVIM)
Delay
Delay
Delay
POC reset
request signal
Internal reset signal
(active low)
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CHAPTER 23 LOW-VOLTAGE DETECTOR
23.5 RAM Retention Voltage Detection Operation
The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage
(including on power application), the RAMF bit is set.
When the POC function is not used and when the RAM retention voltage detection function is used, be sure to
input an external reset signal if the detected voltage falls below the operating voltage.
Figure 23-4. Operation Timing of RAM Retention Voltage Detection Function
Supply voltage
(VDD)
POC detected
voltage
RAM retention
detected voltage
Time
Clear
Delay
Delay
POC detected
voltage
Set condition
detection signal
Delay
Set
RAM retention voltage
detection signal
Set
RAM retention flag
(RAMF bit)
Cleared by
instruction
Cleared by
instruction
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CHAPTER 24 REGULATOR
24.1 Overview
This product has an on-chip regulator to lower the power consumption and noise.
This regulator supplies a voltage lower than the supply voltage VDD to the oscillator block and internal logic circuits
(except the A/D converter and I/O buffers). The output voltage of the regulator is set to 2.5 V (Typ.).
Figure 24-1. Regulator
BVDD I/O buffer
A/D converter
4.0 to 5.5 V
AVREF0
(external access port)
3.5 to 5.5 V
Note
BVDD
Flash
memory
V
DD
Regulator
REGC
Internal digital circuit
2.5 V
Main and sub
oscillators
EVDD I/O buffer (normal port)
3.5 to 5.5 V
EVDD
Bidirectional level shifter
Note: BVDD not available for V850ES/FE2 and V850ES/FF2
24.2 Operation
The regulator of this product operates in all operation modes (normal operation, HALT, IDLE1, IDLE2, software STOP,
and sub-IDLE modes, and during reset).
To stabilize the output voltage of the regulator, connect a capacitor (4.7 µF (recommended value)) to the REGC pin.
Connect the REGC pin as illustrated below.
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CHAPTER 24 REGULATOR
Figure 24-2. Connection of REGC Pin (REGC = Capacitance)
V
SS
V
DD
Input voltage
3.5 to 5.5 V
REG
Supply voltage to
oscillators/internal logic
2.5 V (Typ.)
REGC
µ
4.7
F
(recommended value)
V
SS
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CHAPTER 25 FLASH MEMORY
The following products are flash memory versions of the V850ES/Fx2
Remark: For the whole chapter it shall be agreed that V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2,
V850ES/FG2 and V850ES/FJ2.
Caution There are differences in the amount of noise tolerance and noise radiation between flash
memory versions and mask ROM versions. When considering changing from a flash memory
version to a mask ROM version during the process from experimental manufacturing to mass
production, make sure to sufficiently evaluate commercial samples (CS) (not engineering
samples (ES)) of the mask ROM versions.
• µPD70F3231, 70F3232, 70F3234 • µPD70F3233, 70F3235, 70F3237 • µPD70F3236
On-chip 128 KB flash memory
On-chip 256 KB flash memory
On-chip 384 KB flash memory
• µPD70F3238
• µPD70F3239
On-chip 376 KB flash memory
On-chip 512 KB flash memory
When fetching an instruction, 4 bytes of the flash memory can be accessed in 1 clock in the same manner as the
mask ROM versions.
The flash memory can be written mounted on the target board (on-board write), by connecting a dedicated flash
programmer to the target system.
Flash memory is commonly used in the following development environments and applications.
• For altering software after solder-mounting the V850ES/Fx2 on the target system
• For differentiating software in small-scale production of various models.
• For data adjustment when starting mass production
25.1 Features
• 4-byte/1-clock access (when instruction is fetched)
• Capacity: 512/376(384)/256/128 KB
• Write voltage: Erase/write with a single power supply
• Rewriting method
• Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board
programming)
• Rewriting flash memory by user program (self programming)
• Flash memory write prohibit function supported (security function)
• Safe rewriting of entire flash memory area by self programming using boot swap function
• Interrupts can be acknowledged during self programming.
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CHAPTER 25 FLASH MEMORY
25.1.1 Erasure unit
The units in which the 128, 256, 384, 376 or 512 KB flash memory can be erased are as follows.
(1) All-area erasure
The areas of flash memory xx000000H to xx01FFFFH, xx000000H to xx03FFFFH, xx000000H to xx05FFFFH,
xx000000H to xx05DFFFH and xx000000H to xx07FFFFH can be erased at the same time.
(2) Block erasure
The flash memory can be erased in block units
Block / Flash 128K Flash
Block 15
256K Flash
384K Flash
376K Flash
512K Flash
4 KB
Block 14
4 KB
Block 13
4 KB
Block 12
4 KB
Block 11
32 KB
32 KB
32 KB
32 KB
8 KB
60 KB
60 KB
60 KB
60 KB
8 KB
Block 10
Block 9
60 KB
60 KB
8 KB
Block 8
Block 7
8 KB
Block 6
8 KB
8 KB
8 KB
8 KB
Block 5
56 KB
56 KB
8 KB
56 KB
56 KB
8 KB
56 KB
56 KB
8 KB
56 KB
56 KB
8 KB
Block 4
Block 3
Block 2
Block 1
Block 0
8 KB
56 KB
8 KB
56 KB
8 KB
56 KB
8 KB
56 KB
8 KB
56 KB
8 KB
56 KB
56 KB
56 KB
56 KB
56 KB
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CHAPTER 25 FLASH MEMORY
25.1.2 Functional Outline
The internal flash memory of the V850ES/Fx2 can be rewritten by using the rewrite function of the dedicated flash
programmer, regardless of whether the V850ES/Fx2 has already been mounted on the target system or not (off-
board/on-board programming).
In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also
supported, so that the program cannot be changed by an unauthorized person.
The rewrite function using the user program (self programming) is ideal for an application where it is assumed that
the program is changed after production/shipment of the target system. A boot swap function that rewrites the entire
flash memory area safely is also supported. In addition, interrupt servicing is supported during self programming, so
that the flash memory can be rewritten under various conditions, such as while communicating with an external
device.
Table 25-1. Rewrite Method
Rewrite Method
Functional Outline
Operation Mode
On-board programming
Flash memory can be rewritten after the device is mounted on the target Flash memory
system, by using a dedicated flash programmer.
programming mode
Off-board programming
Self programming
Flash memory can be rewritten before the device is mounted on the
target system, by using a dedicated flash programmer and a dedicated
program adapter board (FA series).
Flash memory can be rewritten by executing a user program that has
been written to the flash memory in advance by means of off-board/on-
board programming. (During self-programming, instructions cannot be
fetched from or data access cannot be made to the internal flash
memory area. Therefore, the rewrite program must be transferred to the
internal RAM or external memory in advance).
Normal operation mode
Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
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CHAPTER 25 FLASH MEMORY
Table 25-2. Basic Functions
Function
Functional Outline
Support ( : Supported, ×: Not supported)
On-Board/Off-Board
Self Programming
Programming
Block erasure
Chip erasure
Write
The contents of specified memory blocks
are erased.
The contents of the entire memory area are
erased all at once.
×
Writing to specified addresses, and a verify
check to see if write level is secured are
performed.
Verify/checksum
Data read from the flash memory is
compared with data transferred from the
flash programmer.
×
(Can be read by user program)
Blank check
The erasure status of the entire memory is
checked.
Security setting
Use of the block erase command, chip
erase command, and program command
can be prohibited.
×
(Only values set by on-
board/off-board programming
can be retained)
The following table lists the security functions. The block erase command prohibit, chip erase command prohibit,
and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting
via on-board/off-board programming. Each security function can be used in combination with the others at the same
time.
Table 25-3. Security Functions
Function
Function Outline
Rewriting Operation When Prohibited
: Executable, ×: Not Executable)
(
On-Board/Off-Board
Programming
Self Programming
Block erase
Execution of a block erase command on all Block erase command: ×
Can always be rewritten
regardless of setting of
prohibition
command prohibit blocks is prohibited. Setting of prohibition
can be initialized by execution of a chip
erase command.
Chip erase command:
Program command:
Chip erase
Execution of block erase and chip erase
Block erase command: ×
command prohibit commands on all the blocks are prohibited. Chip erase command: ×
Once prohibition is set, setting of
prohibition cannot be initialized because
the chip erase command cannot be
executed.
Program command:
Program
Write and block erase commands on all the Block erase command: ×
command prohibit blocks are prohibited. Setting of prohibition Chip erase command:
can be initialized by execution of the chip
erase command.
Program command: ×
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CHAPTER 25 FLASH MEMORY
25.2 Writing with Flash programmer
A dedicated flash programmer can be used for on-board or off-board writing of the flash memory.
(1) On-board programming
The contents of the flash memory can be rewritten with the V850ES/Fx2 mounted on the target system. Mount
a connector that connects the dedicated flash programmer on the target system.
(2) Off-board programming
The flash memory of the V850ES/Fx2 can be written before the device is mounted on the target system, by
using a dedicated program adapter (FA series).
Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
25.3 Programming Environment
The environment necessary to write a program to the flash memory of the V850ES/Fx2 is shown below.
Figure 25-1. Environment to Write Program to Flash Memory
FLMD0
FLMD1Note
RS-232C
Axxxx
Bxxxxx
Cxxxxxx
(FSlaT sh Pro4)
A
TVE
VDD
PG-FP4
USB
V
SS
Dedicated flash
programmer
V850ES/Fx2
RESET
Host machine
UARTA0/CSIB0/CSIB3
Note Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-down resistor on the board.
A host machine is required for controlling the dedicated flash programmer.
UARTA0 or CSIB0 is used as the interface between the dedicated flash programmer and the V850ES/Fx2 to
manipulate the flash programmer by writing or erasing. To write the flash memory off-board, a dedicated program
adapter (FA series) is necessary.
Remark
The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
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CHAPTER 25 FLASH MEMORY
25.4 Communication Mode
Serial communication is performed between the dedicated flash programmer and the V850ES/Fx2 by using
UARTA0 or CSIB0 of the V850ES/Fx2.
(1) UARTA0
Transfer rate: 9,600 - 153,600 bps
Figure 25-2. Communication with Dedicated Flash Programmer (UARTA0)
FLMD0
FLMD1Note
FLMD0
FLMD1
Axxxx
Bxxxxx
V
DD
V
DD
SS
Cxxxxxx
A
TVE
(FSlaT sh Pro4)
PG-FP4
GND
RESET
RxD
V
RESET
TXDA0
RXDA0
Dedicated flash
programmer
V850ES/Fx2
TxD
Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
Cautions 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 Pin I/O
Circuit Types, I/O Buffer Power Supplies and Handling of Unused Pins). To connect a resistor,
a resistor of 1 k to 10 kΩ is recommended.
2. Please do not input high level in DRST pin.
(2) CSIB0
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Figure 25-3. Communication with Dedicated Flash Programmer (CSIB0)
FLMD0
FLMD1
FLMD0
FLMD1Note
V
DD
V
V
DD
SS
Axxxx
Bxxxxx
Cxxxxxx
A
TVE
(FSlaT sh Pro4)
GND
RESET
SI
PG-FP4
RESET
Dedicated flash
programmer
V850ES/Fx2
SOB0, SOB3
SIB0, SIB3
SCKB0, SCKB3
SO
SCK
Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
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CHAPTER 25 FLASH MEMORY
Cautions 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 Pin I/O
Circuit Types, I/O Buffer Power Supplies and Handling of Unused Pins). To connect a resistor,
a resistor of 1 k to 10 kΩ is recommended.
2
Please do not input high level in DRST pin.
(3) CSIB0 + HS
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Figure 25-4. Communication with Dedicated Flash Programmer (CSIB0+HS)
FLMD0
FLMD1
FLMD0
FLMD1Note
VDD
V
DD
Axxxx
Bxxxxx
Cxxxxxx
GND
RESET
SI
V
SS
A
TVE
(FSlaT sh Pro4)
PG-FP4
RESET
Dedicated flash
programmer
SOB0, SOB3
SIB0, SIB3
SCKB0, SCKB3
PCM0
V850ES/Fx2
SO
SCK
HS
Note Connect the FLMD1 pin to the flash programmer or connect to GND via a pull-down resistor on the board.
Cautions 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 Pin I/O
Circuit Types, I/O Buffer Power Supplies and Handling of Unused Pins). To connect a resistor,
a resistor of 1 k to 10 kΩ is recommended.
2. Please do not input high level in DRST pin.
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CHAPTER 25 FLASH MEMORY
The dedicated flash programmer outputs a transfer clock and the V850ES/Fx2 operates as a slave.
If the PG-FP4 is used as the flash programmer, it generates the following signals for the V850ES/Fx2. For details,
refer to the PG-FP4 User’s Manual (U15260E).
Table 25-4. Signal Connections of Dedicated Flash Programmer (PG-FP4)
PG-FP4
V850ES/Fx2Note 1
Pin Name
FLMD0
Processing for Connection
Signal Name
FLMD0
FLMD1
VDD
I/O
Output
Output
−
Pin Function
UARTA0
CSIB0
CSIB0 + HS,
Write enable/disable
Write enable/disable
VDD voltage generation/voltage monitor
Ground
Note 2
Note 2
Note 2
FLMD1
VDD
GND
−
VSS
Note 3
Note 3
Note 3
CLK
Output
Output
Input
Output
Output
Input
Clock output to V850ES/Fx2
Reset signal
X1, X2
×
×
×
RESET
SI/RxD
SO/TxD
SCK
RESET
Receive signal
SOB0, TXDA0
SIB0, RXDA0
SCKB0
Transmit signal
Transfer clock
×
×
HS
Handshake signal for CSIB0 + HS
communication
PCM0
×
Notes 1. V850ES/Fx2 stands for V850ES/FE2, V850ES/FF2, V850ES/FG2 and V850ES/FJ2,
2. Wire these pins as shown in Figure 25-6, or connect then to GND via pull-down resistor on board.
3. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and
supply the clock.
Remark
: Must be connected.
×: Does not have to be connected.
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CHAPTER 25 FLASH MEMORY
Figure 25-5. Example of Wiring of V850ES/FJ2 Flash Writing Adapter (FA-144GJ-UEN)
(In CSIB0 + HS Mode) (1/2)
105
100
95
90
85
80
75
110 Note 1
70
65
60
55
50
45
40
115
120
125
V850ES/FJ2
130
135
Connect to GND
Connect to VDD
140
µ
4.7
F
Note 3
25
Note 2
20
30
35
1
5
10
15
RFU-3 RFU-2 RFU-1 VDE FLMD1 FLMD0
SI
SO
SCK
X1
X2
/RESET
VPP RESERVE/HS
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CHAPTER 25 FLASH MEMORY
Figure 25-5. Example of Wiring of V850ES/FJ2 Flash Writing Adapter (FA-144GJ-UEN)
(In CSIB0 + HS Mode) (2/2)
Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor.
2. Supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines).
Here is an example of the oscillator.
Example
X1
X2
3. Pins used when UARTA0 is used.
Caution Do not input a high level to the DRST pin.
Remarks 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 Pin I/O
Circuit Types and Recommended Connection of Unused Pins).
2. This adapter is for the 144-pin plastic LQFP package.
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CHAPTER 25 FLASH MEMORY
25.5 Pin Connection
A connector must be mounted on the target system to connect the dedicated flash programmer for on-board writing.
In addition, a function to switch between the normal operation mode and flash memory programming mode must be
provided on the board.
When the flash memory programming mode is set, all the pins not used for flash memory programming are in the
same status as that immediately after reset. Therefore, all the ports go into an output high-impedance state, and the
pins must be processed correctly if the external device does not recognize the output high-impedance state.
25.5.1 FLMD0 pin
Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level
must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 25.7.5 (1)
FLMD0 pin.
In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD
write voltage is supplied to the FLMD0 pin. An example of connection of the FLMD0 pin is shown below.
Figure 25-6. Example of Connection of FLMD0 Pin
V850ES/FJ2
Dedicated flash programmer
connection pin
FLMD0
Pull-down resistor (PFLMD0
)
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CHAPTER 25 FLASH MEMORY
25.5.2 FLMD1 pin
If 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. If VDD is supplied to the FLMD0 pin, 0 V must be
input to the FLMD1 pin to set the flash memory programming mode. An example of the connection of the FLMD1 pin
is shown below.
Figure 25-7. Example of Connection of FLMD1 Pin
V850ES/FJ2
FLMD1
Other device
Pull-down resistor (RFLMD1
)
Caution If a VDD signal is input to the FLMD1 pin from other device during on-board
writing and immediately after reset, isolate this signal.
Table 25-5. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode
FLMD0
0
FLMD1
×
Operation Mode
Normal operation mode
VDD
0
Flash memory programming mode
Setting prohibited
VDD
VDD
25.5.3 Serial interface pins
The pins used by each serial interface are shown in the table below.
Table 25-6. Pins Used by Each Serial Interface
Serial Interface
Pins
CSIB0
SOB0, SIB0, SCKB0
SOB0, SIB0, SCKB0, PCM0
TXDA0, RXDA0
CSIB0 + HS
UARTA0
When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on
board, exercise care so that signal conflict and malfunction of the other device do not occur.
(1) Conflict of signals
When the dedicated flash programmer (output) is connected to a serial interface pin (input) connected to
another device (output), a signal conflict occurs. To avoid this signal conflict, isolate the connection with the
other device, or place the other device in an output high-impedance state.
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CHAPTER 25 FLASH MEMORY
Figure 25-8. Signal Conflict (Input Pin of Serial Interface)
V850ES/FJ2
Dedicated flash programmer
connection pin
Signal conflict
Input pin
Other device
Output pin
In the flash memory programming mode, the signal output by an other
device conflicts with the signal output by the dedicated flash programmer.
Isolate the signal of the other device.
(2) Abnormal operation of other device
When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output)
connected to another device (input), a signal is output to the other device, causing a malfunction. To avoid this
malfunction, isolate the connection with the other device, or set so that the signal input to the other device is
ignored.
Figure 25-9. Abnormal Operation of Other Device
V850ES/FJ2
Dedicated flash programmer
connection pin
Pin
Other device
Input pin
If the signal output by the V850ES/FJ2 affects another device in the flash
memory programming mode, isolate the signal of the other device.
V850ES/FJ2
Dedicated flash programmer
connection pin
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signal of the
other device.
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CHAPTER 25 FLASH MEMORY
25.5.4 RESET pin
When the reset signal of the dedicated flash programmer is connected to the RESET pin connected to a reset
signal generator on board, a signal conflict occurs. To avoid this signal conflict, isolate the connection with the reset
signal generator.
If a reset signal is input from the user system in flash memory programming mode, the programming operation is
not performed correctly. Do not input a reset signal other than that from the dedicated flash programmer.
Figure 25-10. Signal Conflict (RESET Pin)
V850ES/FJ2
Dedicated flash programmer
connection pin
Signal conflict
RESET
Reset signal generator
Output pin
Because the signal output by the reset signal generator conflicts with the
signal output by the dedicated flash programmer in the flash programming
mode, isolate the signal of the reset signal generator.
25.5.5 Port pins (including NMI)
All the port pins, including the pin connected to the dedicated flash programmer, go into an output high-impedance
state in the flash memory programming mode. If there is a problem such as that the external device connected to a
port prohibits the output high-impedance state, connect the port to VDD or VSS via a resistor.
25.5.6 Other signal pins
Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode.
During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high level.
25.5.7 Power supply
Supply the same power to the power supply pins (VDD, VSS, EVDD, EVSS, BVDD, BVSS, AVSS and AVREF0) as
in the normal operation mode.
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25.6 Programming Method
25.6.1 Flash memory control
The procedure to manipulate the flash memory is illustrated below.
Figure 25-11. Flash Memory Manipulation Procedure
Start
Transition to flash memory
programming mode
FLMD0 pulse supply
Select communication mode
Manipulation of flash memory
No
End?
Yes
End
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25.6.2 Selecting communication mode
In the V850ES/Fx2., the communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin
after the flash memory programming mode is set. These FLMD0 pulses are generated by the dedicated flash
programmer.
The relationship between the number of pulses and the communication mode is shown in the figure below.
Figure 25-12. Flash Memory Programming Mode
VDD
VDD
0 V
VDD
RESET (input)
0 V
VDD
FLMD1 (input)
FLMD0 (input)
RXDA0 (input)
TXDA0 (output)
0 V
VDD
0 V
(Note)
VDD
0 V
VDD
0 V
Oscillation
stabilization
Communication
mode selection
Flash control command communication
(such as erase and write)
Power
Reset
supply released
ON
Note The number of clocks to be inserted differs depending on the communication mode.
FLMD0 Pulse
Communication
Mode
Remark
8
CSIB0
CSIB0 + HS
UARTA0
-
V850ES/Fx2 operates as slave. MSB first
V850ES/FJ2 operates as slave. MSB first
Communication rate: 9,600 bps (after reset), LSB first
Setting prohibited
11
0
Others
Caution When UARTA is selected, the receive clock is calculated based on the reset command that is
sent from the dedicated flash programmer after reception of the FLMD0 pulse.
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25.6.3 Communication commands
The V850ES/Fx2. communicates with the dedicated flash programmer via commands. The commands sent by the
dedicated flash programmer to the V850ES/Fx2 are called commands, and the response signals sent by the
V850ES/Fx2 to the flash programmer are called response commands.
Figure 25-13. Communication Commands
Command
Axxxx
Bxxxxx
Cxxxxxx
STATVE
Response
(Flash Pr
PG-FP4
o4)
command
V850ES/Fx2
Dedicated flash
programmer
The following table lists the flash memory control commands of the V850ES/Fx2. All these commands are issued
by the programmer, and the V850ES/Fx2 performs the corresponding processing.
Table 25-7. Flash Memory Control Commands
Classification
Command Name
Support
Function
CSIB CSIB + HS UARTA
Blank check
Erase
Block blank check command
Chip erase command
Block erase command
Write command
√
√
√
√
√
√
√
√
√
√
√
√
Checks erasure status of entire memory.
Erases all memory contents.
Erases memory contents of specified block.
Write
Verify
Writes data by specifying write address and
number of bytes to be written, and executes
verify check.
Verify command
√
√
√
Compares input data with all memory
contents.
System setting Reset command
and control
√
√
√
√
√
√
Escapes from each status.
Sets oscillation frequency.
Oscillation frequency setting
command
Baud rate setting command
Silicon signature command
Version acquisition command
Status command
–
√
√
√
√
–
√
√
√
√
√
√
√
–
√
Sets baud rate when UART is used.
Reads silicon signature information.
Reads version information of device.
Acquires operation status.
Security setting command
Sets security of chip erasure, block erasure,
and writing.
The V850ES/Fx2 returns a response command in response to the command issued by the flash programmer. The
response commands sent by the V850ES/Fx2 are listed below.
Table 25-8. Response Commands
Response Command Name
ACK
NAK
Function
Acknowledges command/data.
Acknowledges illegal command/data.
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CHAPTER 25 FLASH MEMORY
25.7 Rewriting by Self Programming
25.7.1 Overview
The V850ES/Fx2 supports a flash macro service that allows the user program to rewrite the internal flash memory
by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user
application program, the flash memory can be rewritten by a user application transferred in advance to the internal
RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the
field.
Figure 25-14. Concept of Self Programming
Application program
Self programming library
Flash function execution Flash information
Flash macro service
Erase, write
Flash memory
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25.7.2 Features
(1) Secure self programming (boot swap function)
The V850ES/Fx2 supports a boot swap function that can exchange the physical memory of blocks 0 and 1 with
the physical memory of blocks 2 and 3. By writing the start program to be rewritten to blocks 2 and 3 in
advance and then swapping the physical memory, the entire area can be safely rewritten even if a power
failure occurs during rewriting because the correct user program always exists in blocks 0 and 1.
Figure 25-15. Rewriting Entire Memory Area (Boot Swap)
Block 15
Block 15
Block 15
Block 5
Block 5
Boot swap
Block 5
Block
Block
Block
Block
Block
4
3
2
1
0
Block
Block
Block
Block
Block
4
3
2
1
0
Block
Block
Block
Block
Block
4
3
2
1
0
Rewriting blocks
2 and 3
(2) Interrupt support
Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a
user handler written to the flash memory could not be used even if an interrupt occurred. With the
V850ES/Fx2, a user handler can be registered to an entry RAM area by using a library function, so that
interrupt servicing can be performed by internal RAM or external memory execution.
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25.7.3 Standard self programming flow
The entire processing to rewrite the flash memory by flash self programming is illustrated below.
Figure 25-16. Standard Self Programming Flow
Flash memory manipulation
Flash environment initialization processing
•
•
•
Disable accessing flash area
Disable setting of STOP mode
Disable stopping clock
Erase processing
Write processing
Flash information setting processingNote 1
Internal verify processing
All blocks end?
Yes
No
Boot area swap processingNote 2
Flash environment end processing
End of processing
Notes 1. If a security setting is not performed, flash information setting processing does not have to be
executed.
2. If boot swap is not used, flash information setting processing and boot swap processing do not have
to be executed.
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Table 25-9. Flash Function List
25.7.4 Flash functions
Function Name
Outline
Initialization of flash control macro
Erasure of only specified one block
Writing from specified address
Internal verification of specified block
Blank check of specified block
Check of FLMD pin
Support
FlashEnv
√
√
√
√
√
√
√
√
√
√
√
FlashBlockErase
FlashWordWrite
FlashBlockIVerify
FlashBlockBlankCheck
FlashFLMDCheck
FlashStatusCheck
FlashGetInfo
Status check of operation specified immediately before
Reading of flash information
FlashSetInfo
Setting of flash information
FlashBootSwap
FlashSetUserHandler
Swapping of boot area
User interrupt handler registration function
25.7.5 Pin processing
(1) FLMD0 pin
The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from
being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0
V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD
level to the FLMD0 pin during the self programming mode period via port control before the memory is
rewritten.
When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V.
Figure 25-17. Mode Change Timing
V
DD
RESET signal
FLMD0 pin
0 V
Self programming mode
V
DD
0 V
Normal
operation mode
Normal
operation mode
Caution Make sure that the FLMD0 pin is at 0 V when reset is released.
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25.7.6 Internal resources used
The following table lists the internal resources used for self programming. These internal resources can also be
used freely for purposes other than self programming.
Table 25-10. Internal Resources Used
Resource Name
Entry RAM area
Description
Routines and parameters used for the flash macro service are located in this area. The
entry program and default parameters are copied by calling a library initialization function.
(124 bytes of either internal
RAM/external RAM)
Stack area (user stack + 300 bytes)
Library code (1900 bytes)
Application program
An extension of the stack used by the user is used by the library (can be used in both the
internal RAM and external RAM).
Program entity of library (can be used anywhere other than the flash memory block to be
manipulated).
Executed as user application.
Calls flash functions.
Maskable interrupt
Can be used in user application execution status or self programming status. To use this
interrupt in the self programming status, the interrupt servicing start address must be
registered in advance by a registration function.
NMI interrupt
Can be used in user application execution status or self programming status. To use this
interrupt in the self programming status the interrupt servicing start address must be
registered in advance by a registration function.
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CHAPTER 26 OPTION FUNCTION
26.1 Mask Options
This product series has an option data area where a block subject to mask options is specified.
When writing a program to a flash memory version or a mask ROM version, be sure to set the option data
corresponding to the following option in the program at address 007AH as default data.
The data in this area cannot be rewritten during program execution.
7
6
5
0
4
0
3
0
2
1
0
007AH Subclock7 Subclock6
MP2
WDTMD1 RMOPIN
Subclock7 Subclock6
Selection of subclock
0
0
1
1
0
1
0
1
Sub-Crystal connection
Setting prohibited
Setting prohibited
RC oscillation connection
MP2
POC function for Mask ROM
0
1
Without POC function
With POC function
Remarks: 1. MP2 bit is only used for mask ROM product.
2. Setting of MP2 bit does not affect flash ROM product function.
3. For flash product POC function is distinguished by device name “M1” and “M2”.
WDTMD1
0
WDT2 mask option
Count clock for WDT2 can be selected by software and
Overflow signal can be selected from INTWDT2 or WDT2RES.
1
Count clock is fixed to Ring-OSC and
overflow signal is fixed to WDT2RES.
RMOPIN
Ring-OSC mask option
Ring-OSC can be stopped by software
Ring-OSC cannot be stopped
0
1
Caution:
Remark:
Do not make any settings other than the above.
In case of mask products, set the option data same as flash memory products.
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Some examples for possible settings are described in Table 26-1 (Selection is not complete).
Table 26-1. Example settings for mask option (assortment)
Address
007AH
Set Value
00H
Setting
Ring-OSC: Can be stopped.
WDT2: Count clock can be selected.
Overflow signal can be selected from INTWDT2 or WDT2RES.
Subclock: Crystal resonator connection
POC function for mask ROM product disabled
03H
C2H
C7H
Ring-OSC: Cannot be stopped.
WDT2:
Count clock is fixed to Ring-OSC.
Overflow signal is fixed to WDT2RES.
Subclock: Crystal resonator connection
POC function for mask ROM product disabled
Ring-OSC: Can be stopped.
WDT2:
Count clock is fixed to Ring-OSC.
Overflow signal is fixed to WDT2RES.
Subclock: RC oscillation connection
POC function for mask ROM product disabled
Ring-OSC: Cannot be stopped.
WDT2:
Count clock is fixed to Ring-OSC.
Overflow signal is fixed to WDT2RES.
Subclock: RC oscillation
POC function for mask ROM product
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
The V850ES/FE2, V850ES/FF2, V850ES/FG2 and V850ES/FJ2 include an on-chip debug unit. By connecting an
N-Wire emulator, on-chip debugging can be executed with the V850ES/FE2, V850ES/FF2, V850ES/FG2 and
V850ES/FJ2 alone.
Cautions: 1 The on-chip debug function is provided only in the flash memory version. It is not provided with
the mask ROM version. However, the OCDM register also exists in the mask ROM version and it
controls the pull-down resistor connected to the P05/INTP2 pin, so set the OCDM register even
for the mask ROM version.
2. The following debug functions are supported and whether they are usable or not differs
depending on the debugger. For details of the debugging function, refer to the user’s manual of
the debugger to be used.
27.1 Functional Outline
27.1.1 Type of on-chip debug unit
The on-chip debug unit is RCU1 (Run Control Unit 1).
27.1.2 Debug functions
(1) Debug interface
Communication with the host machine is established by using the DRST, DCK, DMS, DDI, and DDO signals
via an N-Wire emulator. The communication specifications of N-Wire are used for the interface.
(2) On-chip debug
On-chip debugging can be executed by preparing wiring and a connector for on-chip debugging on the target
system. An N-Wire emulator is used as the connector that connects the emulator.
Clear the OCDM0 bit of the OCDM register (special register) to 0 when you use on-chip debug mode. Please
refer to Table 4-3 Alternate-Function Pins of Port 0 for details.
(3) Forced reset function
The V850ES/FE2, V850ES/FF2, V850ES/FG2 AND V850ES/FJ2 can be forcibly reset.
(4) Break reset function
The CPU can be started in the debug mode immediately after reset of the CPU is released.
(5) Forced break function
Execution of the user program can be forcibly aborted (however, the illegal operation code exception handler
(first address: 00000060H) cannot be used).
(6) Hardware break function
Two breakpoints for instruction and access can be used. The instruction breakpoint can abort program
execution at any address. The access breakpoint can abort program execution by data access to any address.
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(7) Software break function
Up to four software breakpoints can be set in the internal ROM area. The number of software breakpoints that
can be set in the RAM area differs depending on the debugger to be used.
(8) Debug monitor function
A memory space for debugging that is different from the user memory space is used during debugging
(background monitor mode). The user program can be executed starting from any address.
While execution of the user program is aborted, the user resources (such as memory and I/O) can be read and
written, and the user program can be downloaded.
(9) Mask function
Each signal can be masked.
The correspondence with the mask functions of the debugger (ID850NWC) for the N-Wire emulator (IE-
V850E1-CD-NW) of NEC Electronics is shown below.
NMI0 mask function: NMI pin
NMI1 mask function: WDT2 interrupt
NMI2 mask function:
STOP mask function:
–
–
HOLD mask function: HLDRQ pin
RESET mask function: RESET pin, WDT2 reset, POC resetNote, LVI reset, clock monitor reset
DBINT mask function: –
WAIT mask function: Masks WAIT pin
Note This applies only to the products with a power-on clear function.
(10) Timer function
The execution time of the user program can be measured.
(11) Peripheral macro operation/stop selection function during break
Depending on the debugger to be used, whether the peripheral macro operates or is stopped during a break
can be selected.
• Functions that are always stopped during break
•
Clock monitor
•
Watchdog timer 2
• Functions that can operate or be stopped during break (however, each function cannot be selected
individually)
•
A/D converter
•
Timer M
•
Timer P
•
Timer Q
•
Watch timer
• Peripheral functions that continue operating during break (functions that cannot be stopped)
•
Peripheral functions other than above
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.2 Connection Circuit Example
VDD
EVDD
Note 1
DCK
DMS
DCK
DMS
DDI
DDO
DDI
DDO
DRST
DRSTNote 2
RESET
FLMD0
RESET
FLMD0Note 3
FLMD1/PDL5
GND
EVSS
IE-V850E1-CD-NW
V850ES/FJ2
Notes 1. Example of pin processing when N-Wire emulator is connected
2. A pull-down resistor is provided on chip.
3. For flash memory rewriting
27.3 Interface Signals
The interface signals are described below.
(1) DRST
This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously
initializes the debug control unit.
The IE-V850E1-CD-NW raises the DRST signal when it detects VDD of the target system after the integrated
debugger is started, and starts the on-chip debug unit of the device.
When the DRST signal goes high, a reset signal is also generated in the CPU.
When starting debugging by starting the integrated debugger, a CPU reset is always generated.
(2) DCK
This is a clock input signal. It supplies a 20 MHz clock from the IE-V850E1-CD-NW. In the on-chip debug unit,
the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its
falling edge.
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(3) DMS
This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of
the DMS signal.
(4) DDI
This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK.
(5) DDO
This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal.
(6) EVDD
This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the
signals output from the IE-V850E1-CD-NW (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a high-
impedance state.
(7) FLMD0
The flash self programming function is used for the function to download data to the flash memory via the
integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a
pull-down resistor to the FLMD0 pin.
The FLMD0 pin can be controlled in either of the following two ways.
<1> To control from IE-V850E1-CD-NW
Connect the FLMD0 signal of the IE-V850E1-CD-NW to the FLMD0 pin.
In the normal mode, nothing is driven by the IE-V850E1-CD-NW (high impedance).
During a break, the IE-V850E1-CD-NW raises the FLMD0 pin to the high level when the download
function of the integrated debugger is executed.
<2> To control from port
Connect any port of the device to the FLMD0 pin.
The same port as the one used by the user program to realize the flash self programming function may
be used.
On the console of the integrated debugger, make a setting to raise the port pin to high level before
executing the download function, or lower the port pin after executing the download function.
For details, refer to the ID850QB Ver. 2.80 Integrated Debugger Operation User’s Manual (U16973E).
(8) RESET
This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM0 bit of the OCDM
register set by the user program, on-chip debugging cannot be executed. Therefore, reset is effected by the
IE-V850E1-CD-NW, using the RESET pin, to make the DRST pin valid (initialization).
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.4 Register
(1) On-chip debug mode register (OCDM)
This register is used to select the normal operation mode or on-chip debug mode. This register is a special
register and can be written only in a combination of specific sequences (refer to 3.4.9 Special registers).
If the OCDM0 bit is 1 and if the DRST pin is high, the on-chip debug mode is selected.
This register can be read or written in 8-bit or 1-bit units.
After reset: 01HNote 1
R/W
Address: FFFFF9FCH
7
6
0
5
0
4
0
3
0
2
0
1
0
0
OCDM
0
OCDM0
OCDM0
0
Specification of alternate-function pin of on-chip debug functionNote 2
Selects normal operation mode (in which a pin that functions alternately as on-
chip debug function pin is used as a port/peripheral function pin) and disconnects
the on-chip pull-down resistor of the P05/INTP2/DRST pin.
1
When DRST pin is low:
Normal operation mode (in which a pin that functions alternately as an on-chip
debug function pin is used as a port/peripheral function pin)
When DRST pin is high:
On-chip debug mode (in which a pin that functions alternately as an on-chip
debug function pin is used as an on-chip debug mode pin)
Notes 1. RESET input sets this register to 01H.
On reset by power-on clear: OCDM0 = 0
On occurrence of internal source reset (other than power-on clear): The OCDM register holds
the value before occurrence of reset.
2. P05/INTP2/DRST
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
P55/KR5/DMS
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins
after external reset, any of the following actions must be taken.
• Input a low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit. In this case, take the following actions.
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until <1> is completed.
2. The DRST pin has an on-chip pull-down resistor. This resistor is disconnected when the
OCDM0 flag is cleared to 0. The mask ROM version does not have an on-chip debug
function but it has the above pull-down resistor. With the mask ROM version also,
therefore, the on-chip pull-down resistor must be disconnected by clearing the OCDM0 bit
to 0.
DRST
OCDM0 flag
(1: Pull-down ON, 0: Pull-down OFF)
10 to 100 kΩ
(30 kΩ (TYP.))
27.5 Operation
The on-chip debug function is made invalid under the conditions shown in the table below.
When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
OCDM0 Flag
0
1
DRST Pin
L
Invalid
Invalid
Invalid
Valid
H
Remark L: Low-level input
H: High-level input
The default value of the OCDM0 bit after the pin is reset is 1. It is therefore necessary to clear the OCDM0 bit to 0
when the on-chip debug function is not used, and until then, the DRST pin must be kept low (see Figure 27-1). The
DRST pin is internally pulled down while the OCDM0 bit is 1, and therefore, it can be left open.
After POC reset, the default value of the OCDM0 bit is 0, and the normal operation mode is selected. Therefore, it
is necessary to set the OCDM0 bit to 1 by resetting the pin to use the on-chip debug mode.
If POC reset occurs during on-chip debugging, communication with the emulator is disrupted. Therefore, POC
reset cannot be emulated (see Figure 27-2).
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
Figure 27-1. Timing Chart of Selecting Normal Operation Mode
RESET
(external reset input)
POC
(internal reset)
OCDM0
DRST
(on-chip debug reset input)
Normal operation mode
Normal operation mode
Write 0 from CPU
(to specify normal operation mode)
Figure 27-2. Timing Chart of Selecting On-Chip Debug Mode
To use the on-chip debug mode by using the power-on
clear function, input the external reset signal longer than
the power-on clear detection signal (internal reset)
RESET
(external reset input)
Occurrence of power-on clear detection
signal (internal reset) clears the OCDM0
bit to 00 (normal operation mode)
POC
(internal reset)
OCDM0
DRST
(on-chip debug reset input)
Normal operation mode
On-chip debug mode
Caution To use the on-chip debug function in a product with a power-on clear function, input a low level to
the RESET input pin for 2,000 ms or longer after power application. (After power-on, from power-
voltage is upper 4V, please release the RESET input pin.).
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.6 ROM Security Function
27.6.1 Security ID
The flash memory versions of the V850ES/FE2, V850ES/FF2, V850ES/FG2 AND V850ES/FJ2 perform
authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an
unauthorized person during on-chip debugging by the N-Wire emulator.
Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger
perform ID authentication.
• When the N-Wire emulator is started, the debugger requests ID input. When the ID code input on the debugger
and the ID code set in 0000070H to 0000079H match, the debugger starts.
• Debugging cannot be performed if the N-Wire emulator enable flag is 0, even if the ID codes match.
If the IDs match, the security is released and reading flash memory and using the N-Wire emulator are enabled.
(1) ID code
Be sure to write an ID code when writing a program to the internal ROM.
The area of the ID code is 10 bytes wide and in the range of addresses 00000070H to 00000079H.
The ID code when the memory is erased is shown below.
Address
ID Code
00000079H
00000078H
00000077H
00000076H
00000075H
00000074H
00000073H
00000072H
00000071H
00000070H
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
(2) Security bit
Bit 7 of address 00000079H enables or disables use of the N-Wire emulator.
• Bit 7 of address 00000079H
0: Disable
1: Enable
Cautions 1. If the value of address 00000079H is 00H to 7FH, the N-Wire emulator cannot be connected.
2. If the value of address 00000079H is 80H to FFH, the N-Wire emulator can be connected if the
10-byte ID code to be input when the N-Wire emulator is connected matches.
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.6.2 Setting
Example When the following values are set to addresses 0x70 to 0x79
Address
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
Value
0x12
0x34
0x56
0x78
0x9A
0xBC
0xDE
0xF1
0x23
0xD4
Flash mask option
← (See Chapter 26: Option Function.)
The following shows program examples when the CA850 is used.
[Program example 1]
Following the “ILGOP” section (address 0x60); enter the 10-byte security code and 1-byte system reserved area data
(00H).
#---------------------------------------
# ILGOP handler
#---------------------------------------
.section
"ILGOP"
-- Interrupt handler address 0x60
-- Input ILGOP handler code
.org
0x10
-- Skip handler address to 0x70
#---------------------------------------
SECURITYID (continue ILGOP handler)
#---------------------------------------
#
.word
.word
.hword
.byte
0x78563412
0xF1DEBC9A
0xD423
--0-3 byte code
--4-7 byte code
--8-9 byte code
0x00
--Flash mask option code
Caution When using the CA850 Ver. 3.00 or later, specify the option for disabling the generation of the
security ID
The security ID addition function by linker is added from the CA850 Ver. 3.00. As a result, errors
occur during linking in the above program example.
Error message:
F4264:start address (0x00000070) of section "SECURITY_ID" overlaps
previous section "ILGOP" ended before address (0xXXXXXXXX).
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
[Program example 2]
Enter the 10-byte security code using the “SECURITY_ID” section (address 0x70).
#---------------------------------------
#
SECURITY_ID
#---------------------------------------
.section
.word
"SECURITY_ID"
0x78563412
--0-3 byte code
--4-7 byte code
--8-9 byte code
.word
0xF1DEBC9A
0xD423
.hword
Caution Data that can be set to the “SECURITY_ID” section is limited to 10 bytes. For this reason, data
cannot be set to the system reserved area (0x7A) following the security code. Consequently,
when using a device that needs to set data to the system reserved area, set the security code
and system reserved area data using the method shown in “Program example 1”.
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.7 Connection to N-Wire Emulator
To connect the N-Wire emulator, a connector for emulator connection and a connection circuit must be mounted on
the target system.
Select the KEL connector, MICTOR connector (product name: 2-767004-2, Tyco Electronics AMP K.K.), or a 20-pin
general-purpose connector with a 2.54 mm pitch as the emulator connection connector. Connectors other than the
KEL connector may not be supported by some emulators. Refer to the user’s manual of the emulator to be used.
27.7.1 KEL connector
O Product name
• 8830E-026-170S (KEL): Straight type
• 8830E-026-170L (KEL): Right-angle type
Figure 27-3. Connection to N-Wire Emulator (NEC Electronics IE-V850E1-CD-NW: N-Wire Card)
Emulator connection connector
8830E-026-170S
(KEL)
N-Wire Card
Host machine
PCMCIA Card Slot
Target system
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
(1) Pin configuration
Figure 27-4 shows the pin configuration of the connector for emulator connection (target system side), and
Table 27-1 shows the pin functions.
Figure 27-4. Pin Configuration of Connector for Emulator Connection (Target System Side)
B13 A13
B12 A12
Board side
B2
A2
B1
A1
(Top View)
Caution Evaluate the dimensions of the connector when actually mounting the connector on the target
board.
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
(2) Pin functions
The following table shows the pin functions of the connector for emulator connection (target system side). “I/O”
indicates the direction viewed from the device.
Table 27-1. Pin Functions of Connector for Emulator Connection (Target System Side)
Pin No.
Pin Name
(Reserved 1)
(Reserved 2)
(Reserved 3)
(Reserved 4)
(Reserved 5)
(Reserved 6)
DDI
I/O
–
Pin Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
(Connect to GND)
–
(Connect to GND)
–
(Connect to GND)
–
(Connect to GND)
–
(Connect to GND)
–
(Connect to GND)
Input
Input
Input
Output
Input
Input
Data input for N-Wire interface
Clock input for N-Wire interface
DCK
DMS
Transfer mode select input for N-Wire interface
Data output for N-Wire interface
A10
A11
A12
DDO
DRST
On-chip debug unit reset input
RESET
Reset input. (In a system that uses only POC reset and not pin reset, some
emulators input an external reset signal as shown in Figure 27-5 to set the
OCDM0 bit to 1.)
A13
B1
FLMD0
GND
Input
–
Control signal for flash download (flash memory versions only)
–
B2
GND
–
–
B3
GND
–
–
B4
GND
–
–
B5
GND
–
–
B6
GND
–
–
B7
GND
–
–
B8
GND
–
–
B9
GND
–
–
B10
B11
B12
B13
GND
–
–
(Reserved 8)
(Reserved 9)
VDD
–
(Connect to GND)
–
(Connect to GND)
–
5 V input (for monitoring power supply to target)
Cautions 1. The connection of the pins not supported depends upon the emulator to be used.
2. The pattern of the target board must satisfy the following conditions.
• The pattern length must be 100 mm or less.
• The clock signal must be shielded by GND.
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
(3) Example of recommended circuit
An example of the recommended circuit of the connector for emulator connection (target system side) is shown
below.
Figure 27-5. Example of Recommended Emulator Connection Circuit
5 V
V850ES/FJ2
KEL connector
8830E-026-170S
5 V
A1
A2
A3
A4
A5
A6
B13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
Note 3
DD
(Reserved 1)
V
(Reserved 2)
(Reserved 3)
(Reserved 4)
(Reserved 5)
(Reserved 6)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Note 1
Note 2
Note 1
Note 1
Note 1
A7
A8
A9
A10
A11
DDI
DCK
DMS
DDO
DRST
DDI
DCK
DMS
DDO
DRST
B11
B12
(Reserved 8)
(Reserved 9)
Note 1
Note 4
A13
A12
FLMD0
RESET
FLMD0
RESET
Notes 1. The pattern length must be 100 mm or less.
2. Shield the DCK signal by enclosing it with GND.
3. This pin is used to detect power to the target board. Connect the voltage of the N-Wire interface to this
pin.
4. In a system that uses only POC reset and not pin reset, some emulators input an external reset signal as
shown in Figure 27-5 to set the OCDM0 bit to 1.
Caution The N-Wire emulator may not support a 5 V interface and may require a level shifter. Refer to the
user’s manual of the emulator to be used.
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CHAPTER 27 ON-CHIP DEBUG FUNCTION
27.8 Cautions
(1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN
(program execution), the break function may malfunction.
(2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal
is input from a pin.
(3) With a debugger that can set software breakpoints in the internal flash memory, the breakpoints temporarily
become invalid when pin reset or internal reset is effected. The breakpoints become valid again if a break
such as a hardware break or forced break is executed. Until then, no software break occurs.
(4) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset
is generated as soon as the flash memory is rewritten by DMA or read by the RAM monitor function while the
user program is being executed, the CPU and peripheral I/O may not be correctly reset.
(5) The POC reset operation cannot be emulated.
(6) When the following conditions (a) and (b) are satisfied and operation is stopped on the emulator due to a break,
etc., the watchdog timer 2 does not stop and a reset or non-maskable interrupt occurs. When a reset occurs,
the debugger hangs up.
(a) The main clock or subclock is used as the source clock for watchdog timer 2.
(b) The internal oscillation clock is stopped (RCM.RSTOP bit = 1).
To avoid this, perform either of the following.
• When an emulator is used, the internal oscillation clock is used as the source clock.
• When an emulator is used, disable the internal oscillator oscillation.
(7) When the following conditions (a) and (b) are satisfied and operation is stopped on the emulator due to a break,
etc., TMM does not stop even if the peripheral break function is set to “Break”.
(a) Either the INTWT, internal oscillation clock (fR/8), or subclock are selected as the TMM source clock.
(b) The main clock is stopped.
To avoid this, perform either of the following.
• When an emulator is used, the main clock (fXX, fXX/2, fXX/4, fXX/64, fXX/512) is used as the source clock.
• When an emulator is used, disable the main clock oscillation.
(8) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.
(9) When break command is based, and application software accesses for UARTA/CSIB/AFCAN peripheral I/O
register, to restart without reset, CSIB, UARTA and AFCAN that may be not correct operation.
(10)Do not mount a device that was used for debugging on a mass-produced product (this is because the flash
memory was rewritten during debugging and the number of rewrites of the flash memory cannot be
guaranteed).
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APPENDIX A REGISTER INDEX
(1/15)
Page
469
Symbol
ADA0CR0
Function Register Name
Unit
ADC
A/D conversion result register 0
ADA0CR0H
ADA0CR1
A/D conversion result register 0H
A/D conversion result register 1
A/D conversion result register 10
A/D conversion result register 10H
A/D conversion result register 11
A/D conversion result register 11H
A/D conversion result register 12
A/D conversion result register 12H
A/D conversion result register 13
A/D conversion result register 13H
A/D conversion result register 14
A/D conversion result register 14H
A/D conversion result register 15
A/D conversion result register 15H
A/D conversion result register 16
A/D conversion result register 16H
A/D conversion result register 17
A/D conversion result register 17H
A/D conversion result register 18
A/D conversion result register 18H
A/D conversion result register 19
A/D conversion result register 19H
A/D conversion result register 1H
A/D conversion result register 2
A/D conversion result register 20
A/D conversion result register 20H
A/D conversion result register 21
A/D conversion result register 21H
A/D conversion result register 22
A/D conversion result register 22H
A/D conversion result register 23
A/D conversion result register 23H
A/D conversion result register 2H
A/D conversion result register 3
A/D conversion result register 3H
A/D conversion result register 4
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
469
469
469
469
469
469
469
469
469
468
468
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
469
ADA0CR10
ADA0CR10H
ADA0CR11
ADA0CR11H
ADA0CR12
ADA0CR12H
ADA0CR13
ADA0CR13H
ADA0CR14
ADA0CR14H
ADA0CR15
ADA0CR15H
ADA0CR16
ADA0CR16H
ADA0CR17
ADA0CR17H
ADA0CR18
ADA0CR18H
ADA0CR19
ADA0CR19H
ADA0CR1H
ADA0CR2
ADA0CR20
ADA0CR20H
ADA0CR21
ADA0CR21H
ADA0CR22
ADA0CR22H
ADA0CR23
ADA0CR23H
ADA0CR2H
ADA0CR3
ADA0CR3H
ADA0CR4
ADA0CR4H
ADA0CR5
A/D conversion result register 4H
A/D conversion result register 5
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APPENDIX A
(2/15)
Symbol
ADA0CR5H
ADA0CR6
ADA0CR6H
ADA0CR7
ADA0CR7H
ADA0CR8
ADA0CR8H
ADA0CR9
ADA0CR9H
ADA0M0
ADA0M1
ADA0M2
ADA0PFM
ADA0PFT
ADA0S
Function Register Name
Unit
ADC
Page
469
A/D conversion result register 5H
A/D conversion result register 6
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
BCU
BCU
CPU
BCU
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
469
469
469
469
469
469
469
469
465
466
467
472
472
468
302
303
176
293
678
679
668
674
663
665
662
660
675
673
677
672
681
683
666
666
666
666
666
666
666
665
690
692
A/D conversion result register 6H
A/D conversion result register 7
A/D conversion result register 7H
A/D conversion result register 8
A/D conversion result register 8H
A/D conversion result register 9
A/D conversion result register 9H
A/D converter mode register 0
A/D converter mode register 1
A/D converter mode register 2
Power-fail comparison mode register
Power-fail comparison threshold value register
A/D converter channel specification register 0
Address wait control register
AWC
BCC
Bus cycle control register
BPC
Peripheral I/O area select control register
Bus size configuration register bus
CAN0 module bit rate prescaler register
CAN0 module bit rate register
BSC
C0BRP
C0BTR
C0CTRL
CAN0 module control register
C0ERC
CAN0 module error counter register
CAN0 global block transmission control register
CAN0 global block transmission delay setting register
CAN0 global clock select register
CAN0 global control register
C0GMABT
C0GMABTD
C0GMCS
C0GMCTRL
C0IE
CAN0 module interrupt enable register
CAN0 module information register
CAN0 module interrupt status register
CAN0 module last error information register
CAN0 module last in-pointer register
CAN0 module last out-pointer register
CAN0 module mask 1 register H
CAN0 module mask 1 register L
CAN0 module mask 2 register H
CAN0 module mask 2 register L
CAN0 module mask 3 register H
CAN0 module mask 3 register L
CAN0 module mask 4 register H
CAN0 module mask 4 register L
CAN0 message configuration register m
CAN0 message control register m
C0INFO
C0INTS
C0LEC
C0LIPT
C0LOPT
C0MASK1H
C0MASK1L
C0MASK2H
C0MASK2L
C0MASK3H
C0MASK3L
C0MASK4H
C0MASK4L
C0MCONFm
C0MCTRLm
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APPENDIX A
(3/15)
Page
687
Symbol
Function Register Name
Unit
CAN
C0MDATA01m CAN0 message data byte 01 register m
C0MDATA0m
C0MDATA1m
CAN0 message data byte 0 register m
CAN0 message data byte 1 register m
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
687
687
687
687
687
687
687
687
687
687
687
689
691
691
682
684
685
678
679
668
674
663
665
662
660
675
673
677
672
681
683
666
666
666
666
666
666
665
666
690
692
C0MDATA23m CAN0 message data byte 23 register m
C0MDATA2m
C0MDATA3m
CAN0 message data byte 2 register m
CAN0 message data byte 3 register m
C0MDATA45m CAN0 message data byte 45 register m
C0MDATA4m
C0MDATA5m
CAN0 message data byte 4 register m
CAN0 message data byte 5 register m
C0MDATA67m CAN0 message data byte 67 register m
C0MDATA6m
C0MDATA7m
C0MDLCm
C0MIDHm
C0MIDLm
C0RGPT
CAN0 message data byte 6 register m
CAN0 message data byte 7 register m
CAN0 message data length code register m
CAN0 message ID register Hm
CAN0 message ID register Lm
CAN0 module receive history list register
CAN0 module transmit history list register
CAN0 module time stamp register
CAN1 module bit rate prescaler register
CAN1 module bit rate register
C0TGPT
C0TS
C1BRP
C1BTR
C1CTRL
CAN1 module control register
C1ERC
CAN1 module error counter register
CAN1 global block transmission control register
CAN1 global block transmission delay setting register
CAN1 global clock select register
CAN1 global control register
C1GMABT
C1GMABTD
C1GMCS
C1GMCTRL
C1IE
CAN1 module interrupt enable register
CAN1 module information register
CAN1 module interrupt status register
CAN1 module last error information register
CAN1 module last in-pointer register
CAN1 module last out-pointer register
CAN1 module mask 1 register H
C1INFO
C1INTS
C1LEC
C1LIPT
C1LOPT
C1MASK1H
C1MASK1L
C1MASK2H
C1MASK2L
C1MASK3H
C1MASK3L
C1MASK4H
C1MASK4L
C1MCONFm
C1MCTRLm
CAN1 module mask 1 register L
CAN1 module mask 2 register H
CAN1 module mask 2 register L
CAN1 module mask 3 register H
CAN1 module mask 3 register L
CAN1 module mask 4 register H
CAN1 module mask 4 register L
CAN1 message configuration register m
CAN1 message control register m
916
User’s Manual U17830EE1V0UM00
APPENDIX A
(4/15)
Symbol
Function Register Name
Unit
CAN
Page
687
C1MDATA01m CAN1 message data byte 01 register m
C1MDATA0m
C1MDATA1m
CAN1 message data byte 0 register m
CAN1 message data byte 1 register m
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
687
687
687
687
687
687
687
687
687
687
687
689
691
691
682
684
685
678
679
668
674
686
663
665
662
660
675
673
677
672
681
683
666
666
666
666
666
666
666
666
690
692
C1MDATA23m CAN1 message data byte 23 register m
C1MDATA2m
C1MDATA3m
CAN1 message data byte 2 register m
CAN1 message data byte 3 register m
C1MDATA45m CAN1 message data byte 45 register m
C1MDATA4m
C1MDATA5m
CAN1 message data byte 4 register m
CAN1 message data byte 5 register m
C1MDATA67m CAN1 message data byte 67 register m
C1MDATA6m
C1MDATA7m
C1MDLCm
C1MIDHm
C1MIDLm
C1RGPT
CAN1 message data byte 6 register m
CAN1 message data byte 7 register m
CAN1 message data length code register m
CAN1 message ID register Hm
CAN1 message ID register Lm
CAN1 module receive history list register
CAN1 module transmit history list register
CAN1 module time stamp register
CAN2 module bit rate prescaler register
CAN2 module bit rate register
C1TGPT
C1TS
C2BRP
C2BTR
C2CTRL
CAN2 module control register
C2ERC
CAN2 module error counter register
Interrupt control register
C2ERRIC
C2GMABT
C2GMABTD
C2GMCS
C2GMCTRL
C2IE
CAN2 global block transmission control register
CAN2 global block transmission delay setting register
CAN2 global clock select register
CAN2 global control register
CAN2 module interrupt enable register
CAN2 module information register
CAN2 module interrupt status register
CAN2 module last error information register
CAN2 module last in-pointer register
CAN2 module last out-pointer register
CAN2 module mask 1 register H
C2INFO
C2INTS
C2LEC
C2LIPT
C2LOPT
C2MASK1H
C2MASK1L
C2MASK2H
C2MASK2L
C2MASK3H
C2MASK3L
C2MASK4H
C2MASK4L
C2MCONFm
C2MCTRLm
CAN2 module mask 1 register L
CAN2 module mask 2 register H
CAN2 module mask 2 register L
CAN2 module mask 3 register H
CAN2 module mask 3 register L
CAN2 module mask 4 register H
CAN2 module mask 4 register L
CAN2 message configuration register m
CAN2 message control register m
917
User’s Manual U17830EE1V0UM00
APPENDIX A
(5/15)
Page
687
Symbol
Function Register Name
Unit
CAN
C2MDATA01m CAN2 message data byte 01 register m
C2MDATA0m
C2MDATA1m
CAN2 message data byte 0 register m
CAN2 message data byte 1 register m
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
687
687
687
687
687
687
687
687
687
687
687
689
691
691
682
684
685
678
679
668
674
663
665
662
660
675
673
677
672
681
683
666
666
666
666
666
666
666
666
690
692
C2MDATA23m CAN2 message data byte 23 register m
C2MDATA2m
C2MDATA3m
CAN2 message data byte 2 register m
CAN2 message data byte 3 register m
C2MDATA45m CAN2 message data byte 45 register m
C2MDATA4m
C2MDATA5m
CAN2 message data byte 4 register m
CAN2 message data byte 5 register m
C2MDATA67m CAN2 message data byte 67 register m
C2MDATA6m
C2MDATA7m
C2MDLCm
C2MIDHm
C2MIDLm
C2RGPT
CAN2 message data byte 6 register m
CAN2 message data byte 7 register m
CAN2 message data length code register m
CAN2 message ID register Hm
CAN2 message ID register Lm
CAN2 module receive history list register
CAN2 module transmit history list register
CAN2 module time stamp register
CAN3 module bit rate prescaler register
CAN3 module bit rate register
C2TGPT
C2TS
C3BRP
C3BTR
C3CTRL
CAN3 module control register
C3ERC
CAN3 module error counter register
CAN3 global block transmission control register
CAN3 global block transmission delay setting register
CAN3 global clock select register
CAN3 global control register
C3GMABT
C3GMABTD
C3GMCS
C3GMCTRL
C3IE
CAN3 module interrupt enable register
CAN3 module information register
CAN3 module interrupt status register
CAN3 module last error information register
CAN3 module last in-pointer register
CAN3 module last out-pointer register
CAN3 module mask 1 register H
C3INFO
C3INTS
C3LEC
C3LIPT
C3LOPT
C3MASK1H
C3MASK1L
C3MASK2H
C3MASK2L
C3MASK3H
C3MASK3L
C3MASK4H
C3MASK4L
C3MCONFm
C3MCTRLm
CAN3 module mask 1 register L
CAN3 module mask 2 register H
CAN3 module mask 2 register L
CAN3 module mask 3 register H
CAN3 module mask 3 register L
CAN3 module mask 4 register H
CAN3 module mask 4 register L
CAN3 message configuration register m
CAN3 message control register m
918
User’s Manual U17830EE1V0UM00
APPENDIX A
(6/15)
Symbol
Function Register Name
Unit
CAN
Page
687
C3MDATA01m CAN3 message data byte 01 register m
C3MDATA0m
C3MDATA1m
CAN3 message data byte 0 register m
CAN3 message data byte 1 register m
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CAN
CSI
687
687
687
687
687
687
687
687
687
687
687
689
691
691
682
684
685
533
535
536
532
532
537
532
532
533
535
536
532
532
537
532
532
533
535
536
532
532
537
532
532
318
860
C3MDATA23m CAN3 message data byte 23 register m
C3MDATA2m
C3MDATA3m
CAN3 message data byte 2 register m
CAN3 message data byte 3 register m
C3MDATA45m CAN3 message data byte 45 register m
C3MDATA4m
C3MDATA5m
CAN3 message data byte 4 register m
CAN3 message data byte 5 register m
C3MDATA67m CAN3 message data byte 67 register m
C3MDATA6m
C3MDATA7m
C3MDLCm
C3MIDHm
C3MIDLm
C3RGPT
C3TGPT
C3TS
CAN3 message data byte 6 register m
CAN3 message data byte 7 register m
CAN3 message data length code register m
CAN3 message ID register Hm
CAN3 message ID register Lm
CAN3 module receive history list register
CAN3 module transmit history list register
CAN3 module time stamp register
CSIB0 control register 0
CB0CTL0
CB0CTL1
CB0CTL2
CB0RX
CSIB0 control register 1
CSI
CSIB0 control register 2
CSI
CSIB0 receive data register
CSIB0 receive data register L
CSIB0 status register
CSI
CB0RXL
CB0STR
CB0TX
CSI
CSI
CSIB0 transmit data register
CSIB0 transmit data register L
CSIB1 control register 0
CSI
CB0TXL
CB1CTL0
CB1CTL1
CB1CTL2
CB1RX
CSI
CSI
CSIB1 control register 1
CSI
CSIB1 control register 2
CSI
CSIB1 receive data register
CSIB1 receive data register L
CSIB1 status register
CSI
CB1RXL
CB1STR
CB1TX
CSI
CSI
CSIB1 transmit data register
CSIB1 transmit data register L
CSIB2 control register 0
CSI
CB1TXL
CB2CTL0
CB2CTL1
CB2CTL2
CB2RX
CSI
CSI
CSIB2 control register 1
CSI
CSIB2 control register 2
CSI
CSIB2 receive data register
CSIB2 receive data register L
CSIB2 status register
CSI
CB2RXL
CB2STR
CB2TX
CSI
CSI
CSIB2 transmit data register
CSIB2 transmit data register L
CPU operating clock status register
Clock monitor mode register
CSI
CB2TXL
CCLS
CSI
BCU
CM
CLM
919
User’s Manual U17830EE1V0UM00
APPENDIX A
(7/15)
Page
760
Symbol
DADC0
Function Register Name
Unit
DMA
DMA addressing control register 0
DADC1
DADC2
DADC3
DBC0
DMA addressing control register 1
DMA addressing control register 2
DMA addressing control register 3
DMA transfer count register 0
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
BCU
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
760
760
760
759
759
759
759
759
761
761
761
758
758
758
758
758
758
758
758
DBC1
DMA transfer count register 1
DBC2
DMA transfer count register 2
DBC3
DMA transfer count register 3
DCHC0
DCHC1
DCHC2
DCHC3
DDA0H
DDA0L
DDA1H
DDA1L
DDA2H
DDA2L
DDA3H
DDA3L
DMA channel control register 0
DMA channel control register 1
DMA channel control register 2
DMA channel control register 3
DMA destination address register 0H
DMA destination address register 0L
DMA destination address register 1L
DMA destination address register 1H
DMA destination address register 2H
DMA destination address register 2L
DMA destination address register 3H
DMA destination address register 3L
DMA source address register 0H
DMA source address register 0L
DMA source address register 1H
DMA source address register 1L
DSA0H
DSA0L
DSA1H
DSA1L
DSA2H
DSA2L
DSA3H
DSA3L
DTFR0
DTFR1
DTFR2
DTFR3
DWC0
IMR0
757
757
757
757
757
757
757
757
763
763
763
763
300
804
804
804
804
804
804
804
804
804
804
804
804
DMA source address register 2H
DMA source address register 2L
DMA source address register 3H
DMA source address register 3L
DMA trigger source register 0
DMA trigger source register 1
DMA trigger source register 2
DMA trigger source register 3
Data wait control register 0
Interrupt mask register 0
IMR0H
IMR0L
IMR1
Interrupt mask register 0H
Interrupt mask register 0L
Interrupt mask register 1
IMR1H
IMR1L
IMR2
Interrupt mask register 1H
Interrupt mask register 1L
Interrupt mask register 2
IMR2H
IMR2L
IMR3
Interrupt mask register 2H
Interrupt mask register 2L
Interrupt mask register 3
IMR3H
Interrupt mask register 3H
Interrupt mask register 3L
IMR3L
920
User’s Manual U17830EE1V0UM00
APPENDIX A
(8/15)
Symbol
IMR4
Function Register Name
Unit
INTC
Page
804
Interrupt mask register 4
Interrupt mask register 4H
Interrupt mask register 4L
Interrupt mask register 5L
804
804
804
808
810
812
812
812
814
815
816
809
811
813
813
813
814
815
816
806
686
828
321
686
867
868
817
903
457
196
338
338
202
338
338
258
338
338
207
338
338
207
207
IMR4H
IMR4L
IMR5L
INTF0
INTF1
INTF3
INTF3H
INTF3L
INTF6L
INTF8
INTF9H
INTR0
INTR1
INTR3
INTR3H
INTR3L
INTR6L
INTR8
INTR9H
ISPR
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
KR
External interrupt falling edge specification register 0
External interrupt falling edge specification register 1
External interrupt falling edge specification register 3
External interrupt falling edge specification register 3H
External interrupt falling edge specification register 3L
External interrupt falling edge specification register 6L
External interrupt falling edge specification register 8
External interrupt falling edge specification register 9H
External interrupt rising edge specification register 0
External interrupt rising edge specification register 1
External interrupt rising edge specification register 3
External interrupt rising edge specification register 3H
External interrupt rising edge specification register 3L
External interrupt rising edge specification register 6L
External interrupt rising edge specification register 8
External interrupt rising edge specification register 9H
In-service priority register
KRIC
Interrupt control register
KRM
Key return mode register
LOCKR
LVIIC
Lock register
BCU
Interrupt control register
INTC
LVD
LVIM
Low-voltage detection register
LVIS
Low-voltage detection level select register
Noise elimination control register
LVD
NFC
INTC
DEBUG
WDT
OCDM
OSTS
P0
On-chip debug mode register
Oscillation stabilization time select register
Port 0
PORT
TIMER
TIMER
PORT
TIMER
TIMER
PORT
TIMER
TIMER
PORT
TIMER
TIMER
PORT
PORT
P00NFC
P01NFC
P1
TIP00 noise eliminator control register
TIP01 noise eliminator control register
Port 1
P10NFC
P11NFC
P12
TIP10 noise eliminator control register
TIP11 noise eliminator control register
Port 12
P20NFC
P21NFC
P3
TIP20 noise eliminator control register
TIP21 noise eliminator control register
Port 3
P30NFC
P31NFC
P3H
TIP30 noise eliminator control register
TIP31 noise eliminator control register
Port 3H
P3L
Port 3L
921
User’s Manual U17830EE1V0UM00
APPENDIX A
(9/15)
Page
217
Symbol
Function Register Name
Unit
PORT
P4
P5
P6
Port 4
Port 5
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
BCU
221
228
228
228
237
237
237
240
246
246
246
316
260
323
262
266
270
275
275
275
869
198
211
223
232
232
232
251
251
251
211
223
252
252
252
783
783
783
783
783
783
783
783
Port 6
P6H
Port 6H
P6L
Port 6L
P7
Port 7
P7H
Port 7H
P7L
Port 7L
P8
Port 8
P9
Port 9
P9H
Port 9H
P9L
Port 9L
Processor clock control register
Port CD
PCC
PCD
PORT
BCU
PCLM
PCM
Programmable clock mode register
Port CM
PORT
PORT
PORT
PORT
PORT
PORT
LVD
PCS
Port CS
PCT
Port CT
PDL
Port DL
PDLH
PDLL
PEMU1
PFC0
PFC3L
PFC5
PFC6
PFC6H
PFC6L
PFC9
PFC9H
PFC9L
PFCE3L
PFCE5
PFCE9
PFCE9H
PFCE9L
PIC0
Port DLH
Port DLL
Peripheral emulation register 1
Port function control register 0
Port function control register 3L
Port function control register 5
Port function control register 6
Port function control register 6H
Port function control register 6L
Port function control register 9
Port function control register 9H
Port function control register 9L
Port function control expansion register 3L
Port function control expansion register 5
Port function control expansion register 9
Port function control expansion register 9H
Port function control expansion register 9L
Interrupt control register
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
INTC
Interrupt control register
PIC1
INTC
PIC10
PIC11
PIC12
PIC13
PIC14
PIC2
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
INTC
INTC
INTC
INTC
INTC
INTC
922
User’s Manual U17830EE1V0UM00
APPENDIX A
(10/15)
Page
Symbol
PIC3
Function Register Name
Unit
INTC
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
PLL control register
783
PIC4
INTC
783
783
783
783
783
783
320
322
196
202
258
208
208
208
217
221
229
229
229
238
238
238
240
247
247
247
197
203
209
209
209
218
222
230
230
230
241
248
248
248
264
268
272
PIC5
INTC
PIC6
INTC
PIC7
INTC
PIC8
INTC
PIC9
INTC
PLLCTL
PLLS
PM0
BCU
PLL lockup time specification register
Port mode register 0
BCU
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PM1
Port mode register 1
PM12
PM3
Port mode register 12
Port mode register 3
PM3H
PM3L
PM4
Port mode register 3H
Port mode register 3L
Port mode register 4
PM5
Port mode register 5
PM6
Port mode register 6
PM6H
PM6L
PM7
Port mode register 6H
Port mode register 6L
Port mode register 7
PM7H
PM7L
PM8
Port mode register 7H
Port mode register 7L
Port mode register 8
PM9
Port mode register 9
PM9H
PM9L
PMC0
PMC1
PMC3
PMC3H
PMC3L
PMC4
PMC5
PMC6
PMC6H
PMC6L
PMC8
PMC9
PMC9H
PMC9L
PMCCM
PMCCS
PMCCT
Port mode register 9H
Port mode register 9L
Port mode control register 0
Port mode control register 1
Port mode control register 3
Port mode control register 3 H
Port mode control register 3 L
Port mode control register 4
Port mode control register 5
Port mode control register 6
Port mode control register 6 H
Port mode control register 6 L
Port mode control register 8
Port mode control register 9
Port mode control register 9 H
Port mode control register 9 L
Port mode control register CM
Port mode control register CS
Port mode control register CT
923
User’s Manual U17830EE1V0UM00
APPENDIX A
(11/15)
Page
Symbol
PMCD
Function Register Name
Unit
PORT
Port mode register CD
260
Port mode control register DL
Port mode control register DLH
Port mode control register DLL
Port mode register CM
PMCDL
PMCDLH
PMCDLL
PMCM
PMCS
PMCT
PMDL
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
CPU
277
277
277
263
267
271
276
276
276
179
455
454
849
850
198
203
213
213
213
218
225
234
234
234
242
255
255
255
397
397
397
397
397
397
397
397
397
397
397
397
868
318
853
Port mode register CS
Port mode register CT
Port mode register DL
Port mode register DLH
PMDLH
PMDLL
PRCMD
PRSCM0
PRSM0
PSC
Port mode register DLL
Command register
Prescaler compare register 0
Prescaler mode register 0
Power save control register
Power save mode register
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
WT
WT
Standby
Standby
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
LVD
PSMR
PU0
PU1
PU3
PU3H
Pull-up resistor option register 3H
Pull-up resistor option register 3L
Pull-up resistor option register 4
Pull-up resistor option register 5
Pull-up resistor option register 6
Pull-up resistor option register 6H
Pull-up resistor option register 6L
Pull-up resistor option register 8
Pull-up resistor option register 9
Pull-up resistor option register 9H
Pull-up resistor option register 9L
TIQ00 noise eliminator control register
TIQ01 noise eliminator control register
TIQ02 noise eliminator control register
TIQ03 noise eliminator control register
TIQ10 noise eliminator control register
TIQ11 noise eliminator control register
TIQ12 noise eliminator control register
TIQ13 noise eliminator control register
TIQ20 noise eliminator control register
TIQ21 noise eliminator control register
TIQ22 noise eliminator control register
TIQ23 noise eliminator control register
Internal RAM data status register
Ring OSC mode register
PU3L
PU4
PU5
PU6
PU6H
PU6L
PU8
PU9
PU9H
PU9L
Q00NFC
Q01NFC
Q02NFC
Q03NFC
Q10NFC
Q11NFC
Q12NFC
Q13NFC
Q20NFC
Q21NFC
Q22NFC
Q23NFC
RAMS
RCM
BCU
RESF
Reset source flag register
RESET
924
User’s Manual U17830EE1V0UM00
APPENDIX A
(12/15)
Page
Symbol
SAR
Function Register Name
Unit
ADC
Successive approximation register
463
SELCNT0
SELCNT1
SYS
Selector operation control register 0
Selector operation control register 1
System status register
TIMER
TIMER
CPU
374
376
180
442
443
783
783
783
327
328
238
330
332
334
335
336
337
783
783
783
327
328
329
330
332
334
335
336
337
783
783
783
327
328
329
330
332
334
335
336
337
783
783
TM0CMP0
TM0CTL0
TM0EQIC0
TP0CCIC0
TP0CCIC1
TP0CCR0
TP0CCR1
TP0CNT
TMM0 compare register 0
TMM0 control register 0
TIMER
TIMER
INTC
Interrupt control register
Interrupt control register
INTC
Interrupt control register
INTC
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP0 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0OVIC
TP1CCIC0
TP1CCIC1
TP1CCR0
TP1CCR1
TP1CNT
TMP0 control register 1
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register
Interrupt control register
Interrupt control register
INTC
Interrupt control register
INTC
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP1 control register 0
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1OVIC
TP2CCIC0
TP2CCIC1
TP2CCR0
TP2CCR1
TP2CNT
TMP1 control register 1
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register
Interrupt control register
Interrupt control register
INTC
Interrupt control register
INTC
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP2 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2OVIC
TP3CCIC0
TMP2 control register 1
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register
Interrupt control register
Interrupt control register
INTC
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User’s Manual U17830EE1V0UM00
APPENDIX A
(13/15)
Page
Symbol
TP3CCIC1
TP3CCR0
TP3CCR1
TP3CNT
Function Register Name
Unit
INTC
Interrupt control register
783
TMP3 capture/compare register 0
TMP3 capture/compare register 1
TMP3 counter read buffer register
TMP3 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
327
328
329
330
332
334
335
336
337
783
783
783
783
783
383
384
385
386
387
388
390
392
393
395
396
783
783
783
783
783
383
384
385
386
387
388
390
392
393
395
396
783
783
TP3CTL0
TP3CTL1
TP3IOC0
TP3IOC1
TP3IOC2
TP3OPT0
TMP3 control register 1
TMP3 I/O control register 0
TMP3 I/O control register 1
TMP3 I/O control register 2
TMP3 option register
TP3OVIC
Interrupt control register
INTC
INTC
INTC
INTC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
Interrupt control register
Interrupt control register
Interrupt control register
Interrupt control register
INTC
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TMQ1 capture/compare register 0
TMQ1 capture/compare register 1
TMQ1 capture/compare register 2
TMQ1 capture/compare register 3
TMQ0 counter read buffer register
TMQ0 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
TQ0IOC2
TQ0OPT0
TQ0OVIC
TQ1CCIC0
TQ1CCIC1
TQ1CCIC2
TQ1CCIC3
TQ1CCR0
TQ1CCR1
TQ1CCR2
TQ1CCR3
TQ1CNT
TMQ0 control register 1
TMQ0 I/O control register 0
TMQ0 I/O control register 1
TMQ0 I/O control register 2
TMQ0 option register 0
Interrupt control register
Interrupt control register
INTC
Interrupt control register
INTC
Interrupt control register
INTC
Interrupt control register
INTC
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ1 counter read buffer register
TMQ1 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TQ1CTL0
TQ1CTL1
TQ1IOC0
TQ1IOC1
TQ1IOC2
TQ1OPT0
TQ1OVIC
TQ2CCIC0
TMQ1 control register 1
TMQ1 I/O control register 0
TMQ1 I/O control register 1
TMQ1 I/O control register 2
TMQ1 timer option register 0
Interrupt control register
Interrupt control register
INTC
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User’s Manual U17830EE1V0UM00
APPENDIX A
(14/15)
Page
Symbol
TQ2CCIC1
TQ2CCIC2
TQ2CCIC3
TQ2CCR0
TQ2CCR1
TQ2CCR2
TQ2CCR3
TQ2CNT
TQ2CTL0
TQ2CTL1
TQ2IOC0
TQ2IOC1
TQ2IOC2
TQ2OPT0
TQ2OVIC
UA0CTL0
UA0CTL1
UA0CTL2
UA0OPT0
UA0RIC
Function Register Name
Unit
INTC
Interrupt control register
Interrupt control register
Interrupt control register
783
INTC
783
783
383
384
385
386
387
388
390
392
393
395
396
783
500
502
503
504
783
507
505
783
507
500
502
503
504
783
507
505
783
507
500
502
503
504
783
507
505
783
507
500
502
INTC
TMQ2 capture/compare register 0
TMQ2 capture/compare register 1
TMQ2 capture/compare register 2
TMQ2 capture/compare register 3
TMQ2 counter read buffer register
TMQ2 control register 0
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
TIMER
INTC
TMQ2 control register 1
TMQ2 I/O control register 0
TMQ2 I/O control register 1
TMQ2 I/O control register 2
TMQ2 option register
Interrupt control register
UARTA0 control register 0
UARTA0 control register 1
UARTA0 control register 2
UARTA0 option control register 0
Interrupt control register
UART
UART
UART
UART
INTC
UA0RX
UARTA0 receive data register
UARTA0 status register
UART
UART
INTC
UA0STR
UA0TIC
Interrupt control register
UA0TX
UARTA0 transmit data register
UARTA1 control register 0
UARTA1 control register 1
UARTA1 control register 2
UARTA1 option control register 0
Interrupt control register
UART
UART
UART
UART
UART
INTC
UA1CTL0
UA1CTL1
UA1CTL2
UA1OPT0
UA1RIC
UA1RX
UARTA1 receive data register
UARTA1 status register
UART
UART
INTC
UA1STR
UA1TIC
Interrupt control register
UA1TX
UARTA1 receive data register
UARTA2 control register 0
UARTA2 control register 1
UARTA2 control register 2
UARTA2 option control register 0
Interrupt control register
UART
UART
UART
UART
UART
INTC
UA2CTL0
UA2CTL1
UA2CTL2
UA2OPT0
UA2RIC
UA2RX
UARTA2 receive data register
UARTA2 status register
UART
UART
INTC
UA2STR
UA2TIC
Interrupt control register
UA2TX
UARTA2 transmit data register
UARTA3 control register 0
UARTA3 control register 1
UART
UART
UART
UA3CTL0
UA3CTL1
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User’s Manual U17830EE1V0UM00
APPENDIX A
(15/15)
Page
Symbol
UA3CTL2
UA3OPT0
UA3RIC
UA3RX
UA3STR
UA3TIC
UA3TX
VSWC
Function Register Name
Unit
UART
UARTA3 control register 2
503
UARTA3 option control register 0
Interrupt control register
UART
INTC
UART
UART
INTC
UART
CPU
504
783
507
505
783
507
181
460
458
783
783
450
UARTA3 receive data register
UARTA3 status register
Interrupt control register
UARTA3 transmit data register
System wait control register
Watchdog timer enable register
Watchdog timer mode register 2
Interrupt control register
WDTE
WDT
WDT
INTC
INTC
WT
WDTM2
WTIC
WTIIC
Interrupt control register
WTM
Watch timer operation mode register
928
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
B.1 Conventions
(1) Register symbols used to describe operands
Register Symbol
Explanation
General-purpose registers: Used as source registers.
reg1
reg2
General-purpose registers: Used mainly as destination registers. Also used as source register in some
instructions.
reg3
General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of
multiplication results.
bit#3
immX
dispX
regID
vector
cccc
sp
3-bit data for specifying the bit number
X bit immediate data
X bit displacement data
System register number
5-bit data that specifies the trap vector (00H to 1FH)
4-bit data that shows the conditions code
Stack pointer (r3)
ep
Element pointer (r30)
listX
X item register list
(2) Register symbols used to describe opcodes
Register Symbol
Explanation
R
1-bit data of a code that specifies reg1 or regID
1-bit data of the code that specifies reg2
1-bit data of the code that specifies reg3
1-bit displacement data
r
w
d
I
1-bit immediate data (indicates the higher bits of immediate data)
1-bit immediate data
i
cccc
CCCC
bbb
L
4-bit data that shows the condition codes
4-bit data that shows the condition codes of Bcond instruction
3-bit data for specifying the bit number
1-bit data that specifies a program register in the register list
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User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(3) Register symbols used in operations
Register Symbol
Explanation
←
Input for
GR [ ]
SR [ ]
General-purpose register
System register
zero-extend (n)
Expand n with zeros until word length.
Expand n with signs until word length.
Read size b data from address a.
Write data b into address a in size c.
Read bit b of address a.
sign-extend (n)
load-memory (a, b)
store-memory (a, b, c)
load-memory-bit (a, b)
store-memory-bit (a, b, c)
saturated (n)
Write c to bit b of address a.
Execute saturated processing of n (n is a 2’s complement).
If, as a result of calculations,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H.
result
Reflects the results in a flag.
Byte (8 bits)
Byte
Halfword
Half word (16 bits)
Word (32 bits)
Word
+
Addition
–
Subtraction
ll
Bit concatenation
Multiplication
×
÷
Division
%
Remainder from division results
Logical product
Logical sum
AND
OR
XOR
Exclusive OR
NOT
Logical negation
Logical shift left
Logical shift right
Arithmetic shift right
logically shift left by
logically shift right by
arithmetically shift right by
(4) Register symbols used in execution clock
Register Symbol
Explanation
i
If executing another instruction immediately after executing the first instruction (issue).
r
l
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
If using the results of instruction execution in the instruction immediately after the execution (latency).
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User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(5) Register symbols used in flag operations
Identifier
(Blank)
Explanation
No change
0
Clear to 0
X
R
Set or cleared in accordance with the results.
Previously saved values are restored.
(6) Condition codes
Condition Name
(cond)
Condition Code
(cccc)
Condition Formula
Explanation
V
0 0 0 0
1 0 0 0
0 0 0 1
OV = 1
OV = 0
CY = 1
Overflow
NV
C/L
No overflow
Carry
Lower (Less than)
NC/NL
1 0 0 1
CY = 0
No carry
Not lower (Greater than or equal)
Z
0 0 1 0
1 0 1 0
0 0 1 1
1 0 1 1
0 1 0 0
1 1 0 0
0 1 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 1 1 1
1 1 1 1
Z = 1
Z = 0
Zero
NZ
NH
H
Not zero
(CY or Z) = 1
(CY or Z) = 0
S = 1
Not higher (Less than or equal)
Higher (Greater than)
Negative
S/N
NS/P
T
S = 0
Positive
−
Always (Unconditional)
Saturated
SA
LT
GE
LE
GT
SAT = 1
(S xor OV) = 1
(S xor OV) = 0
Less than signed
Greater than or equal signed
Less than or equal signed
Greater than signed
((S xor OV) or Z) = 1
((S xor OV) or Z) = 0
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User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
B.2 Instruction Set (in Alphabetical Order)
(1/6)
Mnemonic
Operand
Opcode
Operation
Execution
Clock
Flags
i
r
l
CY OV
S
×
×
×
Z
×
×
×
SAT
ADD
reg1,reg2
rrrrr001110RRRRR GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
imm5,reg2
r r r r r 0 1 0 0 1 0 i i i i i GR[reg2]←GR[reg2]+sign-extend(imm5)
ADDI
imm16,reg1,reg2
rrrrr110000RRRRR GR[reg2]←GR[reg1]+sign-extend(imm16)
i i i i i i i i i i i i i i i i
AND
reg1,reg2
rrrrr001010RRRRR GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
×
ANDI
imm16,reg1,reg2
rrrrr110110RRRRR GR[reg2]←GR[reg1]AND zero-extend(imm16)
i i i i i i i i i i i i i i i i
Bcond
disp9
ddddd1011dddcccc if conditions are satisfied
When conditions
2
2
2
Note 1 then PC←PC+sign-extend(disp9) are satisfied
Note 2 Note 2 Note 2
When conditions
1
1
1
1
1
4
are not satisfied
BSH
reg2,reg3
reg2,reg3
imm6
rrrrr11111100000 GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
1
1
×
×
0
0
×
×
×
×
wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
BSW
CALLT
rrrrr11111100000 GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
1
4
1
4
wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24)
0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Halfword))
CLR1
CMOV
CMP
bit#3,disp16[reg1]
reg2,[reg1]
10bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
3
3
3
×
×
Note 3 Note 3 Note 3
rrrrr111111RRRRR adr←GR[reg1]
3
3
3
0000000011100100 Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
Note 3 Note 3 Note 3
cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i if conditions are satisfied
wwwww011000cccc0 then GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
1
1
1
1
1
1
cccc,reg1,reg2,reg3 rrrrr111111RRRR
if conditions are satisfied
wwwww011001cccc0 then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
reg1,reg2
rrrrr001111RRRRR result←GR[reg2]–GR[reg1]
1
1
3
1
1
3
1
1
3
×
×
×
×
×
×
×
×
imm5,reg2
r r r r r 0 1 0 0 1 1 i i i i i result←GR[reg2]–sign-extend(imm5)
CTRET
DBRET
0000011111100000 PC←CTPC
R
R
R
R
R
R
0000000101000100 PSW←CTPSW
0000011111100000 PC←DBPC
3
3
3
R
R
R
R
0000000101000110 PSW←DBPSW
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User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(2/6)
Mnemonic
DBTRAP
Operand
Opcode
Operation
Execution
Clock
Flags
S
i
r
l
CY OV
Z
SAT
1111100001000000 DBPC←PC+2 (restored PC)
3
3
3
DBPSW←PSW
PSW.NP←1
PSW.EP←1
PSW.ID←1
PC←00000060H
DI
0000011111100000 PSW.ID←1
1
1
1
0000000101100000
DISPOSE imm5,list12
0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2)
LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
n+1 n+1 n+1
Note 4 Note 4 Note 4
repeat 2 steps above until all regs in list12 is loaded
imm5,list12,[reg1]
0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2)
LLLLLLLLLLLRRRRR GR[reg in list12]←Load-memory(sp,Word)
n+3 n+3 n+3
Note 4 Note 4 Note 4
sp←sp+4
Note 5
repeat 2 steps above until all regs in list12 is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rrrrr111111RRRRR GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01011000000 GR[reg3]←GR[reg2]%GR[reg1]
35 35 35
×
×
×
DIVH
reg1,reg2
rrrrr000010RRRRR GR[reg2]←GR[reg2]÷GR[reg1]Note 6
35 35 35
35 35 35
×
×
×
×
×
×
reg1,reg2,reg3
rrrrr111111RRRRR GR[reg2]←GR[reg2]÷GR[reg1]Note 6
wwwww01010000000 GR[reg3]←GR[reg2]%GR[reg1]
DIVHU
DIVU
EI
reg1,reg2,reg3
reg1,reg2,reg3
rrrrr111111RRRRR GR[reg2]←GR[reg2]÷GR[reg1]Note 6
wwwww01010000010 GR[reg3]←GR[reg2]%GR[reg1]
34 34 34
34 34 34
×
×
×
×
×
×
rrrrr111111RRRRR GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01011000010 GR[reg3]←GR[reg2]%GR[reg1]
1000011111100000 PSW.ID←0
1
1
1
2
1
1
1
2
1
1
1
2
0000000101100000
HALT
HSW
JARL
0000011111100000 Stop
0000000100100000
reg2,reg3
rrrrr11111100000 GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
×
0
×
×
wwwww01101000100
disp22,reg2
rrrrr11110dddddd GR[reg2]←PC+4
ddddddddddddddd0 PC←PC+sign-extend(disp22)
Note 7
JMP
JR
[reg1]
00000000011RRRRR PC←GR[reg1]
3
2
3
2
3
2
disp22
0000011110dddddd PC←PC+sign-extend(disp22)
ddddddddddddddd0
Note 7
LD.B
disp16[reg1],reg2
disp16[reg1],reg2
rrrrr111000RRRRR adr←GR[reg1]+sign-extend(disp16)
1
1
1
1
Note
11
dddddddddddddddd GR[reg2]←sign-extend(Load-memory(adr,Byte))
LD.BU
rrrrr11110bRRRRR adr←GR[reg1]+sign-extend(disp16)
Note
11
dddddddddddddd1
GR[reg2]←zero-extend(Load-memory(adr,Byte))
Notes 8, 10
933
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(3/6)
Mnemonic
LD.H
Operand
disp16[reg1],reg2
reg2,regID
Opcode
Operation
Execution
Clock
Flags
S
i
r
l
CY OV
Z
SAT
rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16)
1
1
Note
11
ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword))
Note 8
LDSR
LD.HU
LD.W
rrrrr111111RRRRR SR[regID]←GR[reg2]
Other than regID = PSW
regID = PSW
1
1
1
1
1
1
0000000000100000
×
×
×
×
×
Note 12
disp16[reg1],reg2
disp16[reg1],reg2
rrrrr111111RRRRR adr←GR[reg1]+sign-extend(disp16)
1
1
1
1
Note
11
ddddddddddddddd1 GR[reg2]←zero-extend(Load-memory(adr,Halfword)
Note 8
rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd1 GR[reg2]←Load-memory(adr,Word)
Note
11
Note 8
MOV
reg1,reg2
rrrrr000000RRRRR GR[reg2]←GR[reg1]
r r r r r 0 1 0 0 0 0 i i i i i GR[reg2]←sign-extend(imm5)
1
1
2
1
1
2
1
1
2
imm5,reg2
imm32,reg1
00000110001RRRRR GR[reg1]←imm32
i i i i i i i i i i i i i i i i
I I I I I I I I I I I I I I I I
MOVEA
MOVHI
MUL
imm16,reg1,reg2
imm16,reg1,reg2
reg1,reg2,reg3
imm9,reg2,reg3
rrrrr110001RRRRR GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
1
1
1
4
4
1
1
5
5
i i i i i i i i i i i i i i i i
rrrrr110010RRRRR GR[reg2]←GR[reg1]+(imm16 ll 016)
i i i i i i i i i i i i i i i i
rrrrr111111RRRRR GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
wwwww01000100000 Note 14
r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] ll GR[reg2]←GR[reg2]xsign-extend(imm9)
wwwww01001IIII00
Note 13
MULH
reg1,reg2
rrrrr000111RRRRR GR[reg2]←GR[reg2]Note 6xGR[reg1]Note 6
r r r r r 0 1 0 1 1 1 i i i i i GR[reg2]←GR[reg2]Note 6xsign-extend(imm5)
1
1
1
1
1
1
2
2
2
imm5,reg2
MULHI
MULU
imm16,reg1,reg2
rrrrr110111RRRRR GR[reg2]←GR[reg1]Note 6ximm16
i i i i i i i i i i i i i i i i
reg1,reg2,reg3
imm9,reg2,reg3
rrrrr111111RRRRR GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
wwwww01000100010 Note 14
1
1
4
4
5
5
r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9)
wwwww01001IIII10
Note 13
NOP
NOT
NOT1
0000000000000000 Pass at least one clock cycle doing nothing.
1
1
3
1
1
3
1
1
3
reg1,reg2
rrrrr000001RRRRR GR[reg2]←NOT(GR[reg1])
0
×
×
×
bit#3,disp16[reg1]
01bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
Note 3 Note 3 Note 3
reg2,[reg1]
rrrrr111111RRRRR adr←GR[reg1]
3
3
3
×
0000000011100010 Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
Note 3 Note 3 Note 3
934
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(4/6)
Mnemonic
Operand
Opcode
Operation
Execution
Clock
Flags
i
r
l
CY OV
S
×
×
Z
×
×
SAT
OR
reg1,reg2
imm16,reg1,reg2
rrrrr001000RRRRR GR[reg2]←GR[reg2]OR GR[reg1]
1
1
1
1
1
1
0
0
ORI
rrrrr110100RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16)
i i i i i i i i i i i i i i i i
PREPARE list12,imm5
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp–4,GR[reg in list12],Word)
LLLLLLLLLLL00001 sp←sp–4
n+1 n+1 n+1
Note 4 Note 4 Note 4
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend(imm5)
list12,imm5,
sp/immNote 15
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp–4,GR[reg in list12],Word)
n+2 n+2 n+2
Note 4 Note 4 Note 4
Note17 Note17 Note17
LLLLLLLLLLLff011 sp←sp+4
imm16/imm32
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend (imm5)
ep←sp/imm
Note 16
RETI
0000011111100000 if PSW.EP=1
0000000101000000 then PC
3
3
3
R
R
R
R
R
←EIPC
PSW ←EIPSW
else if PSW.NP=1
then PC
PSW ←FEPSW
←FEPC
else PC
←EIPC
PSW ←EIPSW
SAR
reg1,reg2
imm5,reg2
cccc,reg2
rrrrr111111RRRRR GR[reg2]←GR[reg2]arithmetically shift right
1
1
1
1
1
1
1
×
×
0
0
×
×
×
×
0000000010100000 by GR[reg1]
GR[reg2]←GR[reg2]arithmetically shift right
r r r r r 0 1 0 1 0 1 i i i i i
1
1
by zero-extend (imm5)
SASF
r r r r r 1 1 1 1 11 0 c c c c if conditions are satisfied
0000001000000000 then GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000000H
SATADD
SATSUB
reg1,reg2
imm5,reg2
reg1,reg2
rrrrr000110RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1])
r r r r r 0 1 0 0 0 1 i i i i i GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
rrrrr000101RRRRR GR[reg2]←saturated(GR[reg2]–GR[reg1])
1
1
1
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
SATSUBI imm16,reg1,reg2
rrrrr110011RRRRR GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
i i i i i i i i i i i i i i i i
SATSUBR reg1,reg2
rrrrr000100RRRRR GR[reg2]←saturated(GR[reg1]–GR[reg2])
1
1
1
1
1
1
×
×
×
×
×
SETF
cccc,reg2
r r r r r 1 1 1 1 11 0 c c c c If conditions are satisfied
0000000000000000 then GR[reg2]←00000001H
else GR[reg2]←00000000H
935
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
(5/6)
Mnemonic
SET1
Operand
Opcode
Operation
Execution
Clock
Flags
S
i
r
l
CY OV
Z
SAT
bit#3,disp16[reg1]
reg2,[reg1]
00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
3
3
3
×
Note 3 Note 3 Note 3
rrrrr111111RRRRR adr←GR[reg1]
3
3
3
×
0000000011100000 Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
Note 3 Note 3 Note 3
SHL
SHR
reg1,reg2
rrrrr111111RRRRR GR[reg2]←GR[reg2] logically shift left by GR[reg1]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
×
×
×
×
0
0
0
0
×
×
×
×
×
×
×
×
0000000011000000
GR[reg2]←GR[reg2] logically shift left
imm5,reg2
reg1,reg2
r r r r r 0 1 0 1 1 0 i i i i i
by zero-extend(imm5)
rrrrr111111RRRRR GR[reg2]←GR[reg2] logically shift right by GR[reg1]
1
0000000010000000
GR[reg2]←GR[reg2] logically shift right
imm5,reg2
disp7[ep],reg2
disp4[ep],reg2
r r r r r 0 1 0 1 0 0 i i i i i
1
by zero-extend(imm5)
SLD.B
rrrrr0110ddddddd adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
Note 9
Note 9
SLD.BU
rrrrr0000110dddd adr←ep+zero-extend(disp4)
Note 18 GR[reg2]←zero-extend(Load-memory(adr,Byte))
SLD.H
disp8[ep],reg2
disp5[ep],reg2
rrrrr1000ddddddd adr←ep+zero-extend(disp8)
Note 19 GR[reg2]←sign-extend(Load-memory(adr,Halfword))
1
1
1
1
Note 9
Note 9
SLD.HU
rrrrr0000111dddd adr←ep+zero-extend(disp5)
Notes 18, 20 GR[reg2]←zero-extend(Load-memory(adr,Halfword))
SLD.W
SST.B
SST.H
SST.W
ST.B
disp8[ep],reg2
reg2,disp7[ep]
reg2,disp8[ep]
reg2,disp8[ep]
reg2,disp16[reg1]
reg2,disp16[reg1]
rrrrr1010dddddd0 adr←ep+zero-extend(disp8)
Note 21 GR[reg2]←Load-memory(adr,Word)
1
1
1
1
1
1
1
1
1
1
1
1
Note 9
1
rrrrr0111ddddddd adr←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
rrrrr1001ddddddd adr←ep+zero-extend(disp8)
Note 19 Store-memory(adr,GR[reg2],Halfword)
1
rrrrr1010dddddd1 adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
1
rrrrr111010RRRRR adr←GR[reg1]+sign-extend(disp16)
1
dddddddddddddddd Store-memory(adr,GR[reg2],Byte)
ST.H
rrrrr111011RRRRR adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword)
Note 8
1
ST.W
STSR
reg2,disp16[reg1]
regID,reg2
rrrrr111011RRRRR adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd1 Store-memory (adr,GR[reg2], Word)
Note 8
1
1
1
1
1
1
rrrrr111111RRRRR GR[reg2]←SR[regID]
0000000001000000
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APPENDIX B INSTRUCTION SET LIST
(6/6)
Mnemonic
Operand
Opcode
Operation
Execution
Clock
Flags
i
r
l
CY OV
S
×
×
Z
×
×
SAT
SUB
reg1,reg2
rrrrr001101RRRRR GR[reg2]←GR[reg2]–GR[reg1]
rrrrr001100RRRRR GR[reg2]←GR[reg1]–GR[reg2]
1
1
5
1
1
5
1
1
5
×
×
×
×
SUBR
SWITCH
reg1,reg2
reg1
00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
PC←(PC+2) + (sign-extend
(Load-memory (adr,Halfword))
logically shift left by 1
SXB
reg1
00000000101RRRRR GR[reg1]←sign-extend
1
1
3
1
1
3
1
1
3
(GR[reg1] (7 : 0))
SXH
TRAP
reg1
00000000111RRRRR GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
vector
0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC
0000000100000000 EIPSW
←PC+4 (Restored PC)
←PSW
ECR.EICC ←Interrupt code
PSW.EP
PSW.ID
PC
←1
←1
←00000040H
(when vector is 00H to 0FH)
00000050H
(when vector is 10H to 1FH)
TST
reg1,reg2
rrrrr001011RRRRR result←GR[reg2] AND GR[reg1]
1
3
1
3
1
3
0
×
×
×
TST1
bit#3,disp16[reg1]
11bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd Z flag←Not (Load-memory-bit (adr,bit#3))
Note 3 Note 3 Note 3
reg2, [reg1]
rrrrr111111RRRRR adr←GR[reg1]
3
3
3
×
0000000011100110 Z flag←Not (Load-memory-bit (adr,reg2))
Note 3 Note 3 Note 3
XOR
reg1,reg2
rrrrr001001RRRRR GR[reg2]←GR[reg2] XOR GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
×
XORI
imm16,reg1,reg2
rrrrr110101RRRRR GR[reg2]←GR[reg1] XOR zero-extend (imm16)
i i i i i i i i i i i i i i i i
ZXB
ZXH
reg1
reg1
00000000100RRRRR GR[reg1]←zero-extend (GR[reg1] (7 : 0))
00000000110RRRRR GR[reg1]←zero-extend (GR[reg1] (15 : 0))
1
1
1
1
1
1
Notes 1. dddddddd: Higher 8 bits of disp9.
2. 3 if there is an instruction that rewrites the contents of the PSW immediately before.
3. If there is no wait state (3 + the number of read access wait states).
4. n is the total number of list12 load registers. (According to the number of wait states. Also, if there are
no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)
5. RRRRR: other than 00000.
6. The lower halfword data only are valid.
7. ddddddddddddddddddddd: The higher 21 bits of disp22.
8. ddddddddddddddd: The higher 15 bits of disp16.
9. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
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User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
r r r r r
= regID specification
RRRRR = reg2 specification
13. iiiii: Lower 5 bits of imm9.
I I I I: Higher 4 bits of imm9.
14. Do not specify the same register for general-purpose registers reg1 and reg3.
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
938
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
B.3 Description of Operating Precautions
If a conflict occurs between the decode operation of the instruction (<2> in the examples mentioned below)
immediately before the sld instruction (<3> in the examples) following a special instruction (<1> in the examples) and
an interrupt request before execution of the special instruction is complete, the execution result of the special
instruction may not be stored in a register as expected.
This situation may only occur when the same register is used as the destination register of the special instruction and
the sld instruction, and when the register value is referenced by the instruction followed by the sld instruction.
Conditions under which the conflict occurs:
The situation may occur when all the following conditions (1) to (3) are satisfied.
(1) Either condition (I) or (II) is satisfied
Condition (I):
The same register is used as the destination register of a special instruction (see below) and the subsequent sld
instruction and as the source register (reg1) of an instruction shown below followed by the sld instruction (See
Example 1).
mov reg1,reg2
not reg1,reg2 satsubr reg1,reg2
xor reg1,reg2
satsub reg1,reg2
and reg1,reg2
add reg1,reg2
satadd reg1,reg2 or reg1,reg2
tst reg1,reg2
subr reg1,reg2 sub reg1,reg2
mulh reg1,reg2
cmp reg1,reg2
Condition (II):
The same register is used as the destination register of a special instruction (see below) and the subsequent sld
instruction and as the source register (reg2) of an instruction shown below followed by the sld instruction (See
Examples 2 and 3).
not reg1,reg2
satsubr reg1,reg2 satsub reg1,reg2
satadd reg1,reg2
and reg1,reg2
add reg1,reg2
shr imm5,reg2
satadd imm5,reg2 or reg1,reg2
xor reg1,reg2
sub reg1,reg2
cmp imm5,reg2
tst reg1,reg2
subr reg1,reg2
cmp reg1,reg2
shl imm5,reg2
add imm5,reg2
sar imm5,reg2
Special instruction:
•ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu
•sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu
• Multiply instruction: mul, mulh, mulhi, mulu
(2) When the execution result of the special instruction (see above) has not been stored in the destination register
before execution of the instruction (instruction of condition (I) or (II)) immediately before the sld instruction starts in the
CPU pipeline.
(3) When the decode operation of the instruction (instruction of condition (I) or (II)) immediately before the sld
instruction and interrupt request servicing conflict.
939
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
Examples of instruction sequences that may cause the conflict:
Example 1:
<1> ld.w [r11], r10
This situation occurs when the decode operation of mov (<2>) is
done immediately before sld (<3>) and an interrupt request servicing
conflict happens before the execution of the special instruction ld
(<1>) is completed.
:
<2> mov r10, r28
<3> sld.w 0x28, r10
Example 2:
(1) ld.w [r11], r10
This situation occurs when the decode operation of comp (<2>) is
done immediately before sld (<3>) and an interrupt request servicing
conflict happens before the execution of the special instruction ld
(<1>) is completed. As a result, the compare result of comp becomes
illegal, which may cause an illegal operation of the branch instruction
bz (<4>).
:
<2> cmp imm5, r10
<3> sld.w 0x28, r10
<4> bz label
Example 3:
<1> ld.w [r11], r10
This situation occurs when the decode operation of add (<2>) is done
immediately before sld (<3>) and an interrupt request servicing
conflict happens before the execution of the special instruction ld
(<1>) is completed. As a result, the results of add and the flag
become illegal, which may cause illegal operation of the setf (<4>).
:
<2> add imm5, r10
<3> sld.w 0x28, r10
<4> setf r16
Workaround
(1) Do not use the sld instruction (e. g. by avoiding code optimization that makes use of sld).
(2) If a code sequence as described above is used (a sld instruction following an instruction that can be executed in
parallel), insert a nop instruction before the sld instruction.
(3) If a code sequence as described above is used (a sld instruction following an instruction that can be executed in
parallel), exchange the order of the previous two instructions as long as the program algorithm is not disturbed:
Example:
1. (before implementing workaround)
ld.w [r11], r10
940
User’s Manual U17830EE1V0UM00
APPENDIX B INSTRUCTION SET LIST
...
add r11, r12
mov r10, r28
sld.w 0x28, r10
2. (after implementing workaround)
ld.w [r11], r10
...
mov r10, r28
add r11, r12
sld.w 0x28, r10
(4) When assembler code is used:
Avoid the critical code sequences as described above.
Please regard this item as a usage restriction on the CPU function. A compiler that can automatically suppress the
generation of the instruction sequence that may cause the bug will be provided.
Please consult an NEC Electronics sales representative or distributor for further details.
Support for system developed:
[Support for system already developed]
When the system has already been developed a judgment is necessary whether or not the restriction applies to the
system.
Please consult an NEC Electronics sales representative or distributor for further details.
941
User’s Manual U17830EE1V0UM00
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