UPD72001L-11 [NEC]
MULTI-PROTOCOL SERIAL CONTROLLERS; 多协议串行控制器
| 型号： | UPD72001L-11 |
| 厂家： | 
NEC |
| 描述： | MULTI-PROTOCOL SERIAL CONTROLLERS |
| 文件： | 总40页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72001-11, 72001-A8
MULTI-PROTOCOL SERIAL CONTROLLERS
DESCRIPTION
The µPD72001-11 is an MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI
equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has
a transmitter function to convert the parallel data output by a data terminal into serial data and transmit this data to
a data transmission system such as a modem, and a receiver function to convert the serial data output by the data
transmission system into parallel data.
The MPSC can be used with data communications equipment with a variety of communication modes such as the
generally and widely used start-stop synchronization mode, and the HDLC mode which is used for high-speed
communication.
The µPD72001-A8 is a low-voltage model.
For this product, the following documents are separately available. Read these documents as well as this Data
Sheet.
•
User’s Manual (S12472E)
(I) (S12753E)
•
Application Notes
(II) (On preparation)
(III) (On preparation)
FEATURES
• Two sets of parallel/serial circuits supporting three modes: start-stop synchronization, character synchronization,
and bit synchronization modes
→ Easy application to a system supporting two or more communication protocols such as a protocol converter or
ISDN terminal adapter
•
•
DPLL (Digital Phase Locked Loop), baud rate generator, and crystal oscillation circuit for transmission/reception
clock
→ Helps reduce cost by decreasing the number of external circuits
Many variations with power-saving features and small package size
→ Easy application to portable terminals and high-accuracy portable terminals
The features common to the µPD72001-11 and 72001-A8 are explained as the features of the MPSC in this
document.
The information in this document is subject to change without notice.
Document No. S12184EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark
shows major revised points.
1997
©
µPD72001-11, 72001-A8
ORDERING INFORMATION
Part Number
µPD72001C-11
Package
40-pin plastic DIP (600 mil)
µPD72001G-11-22
µPD72001GC-11-3B6
µPD72001L-11
44-pin plastic QFP (10 × 10 mm) (resin thickness: 1.45 mm)
52-pin plastic QFP (14 × 14 mm) (resin thickness: 2.7 mm)
52-pin plastic QFJ (750 × 750 mil)
µPD72001C-A8
40-pin plastic DIP (600 mil)
µPD72001G-A8-22
µPD72001GC-A8-3B6
44-pin plastic QFP (10 × 10 mm) (resin thickness: 1.45 mm)
52-pin plastic QFP (14 × 14 mm) (resin thickness: 2.7 mm)
2
µPD72001-11, 72001-A8
SPECIFICATIONS
Item
Part number
Specifications
µPD72001-11
µPD72001-A8
Supply voltage
5 V ±10 %
3.3 V ±0.3 V
System clock frequency
11 MHz MAX.
8 MHz MAX. (at TA = –10 to +70 °C)
7.14 MHz MAX. (at TA = –40 to +85 °C)
Maximum transfer rate
2.2 Mbps
CMOS
1.6 Mbps (at TA = –10 to +70 °C)
1.43 Mbps (at TA = –40 to +85 °C)
Process
Internal circuit
Parallel/serial converter circuit: Full-duplex channel × 2
Transmit buffer : Double
Receive buffer : Quadruple
Interrupt control function
DMA request signal output: 2 for transmission, 2 for reception
Overrun error detection
DPLL
Baud rate generator
Crystal oscillation circuit for transmission/reception clock generation
Self-loopback test function
Standby function
General-purpose I/O pin: 4 pins × 2
Communication protocol
Start-stop
Character bit length: 5, 6, 7, 8
Stop bit length: 1, 1.5, 2
Clock rate: ×1, ×16, ×32, ×64
Parity generation, check
Framing error detection
synchronization
Break generation, detection
COP
Operation mode: Mono-sync, Bi-sync, External sync
Character bit length: 5, 6, 7, 8
(Character
Oriented
Protocol)
SYNC character bit length: 6, 8
Character synchronization: Internal/external
BCS (Block Check Sequence) generation, check:
CRC-16
CRC-CCITT
Parity generation, check
SYNC character automatic transmission, detection, rejection
BOP
Operation mode:
(Bit Oriented
Protocol)
HDLC (High-level Data Link Control)
SDLC (Synchronous Data Link Control)
SDLC Loop
Flag transmission, detection
Zero insertion, rejection
Address field detection (1 byte)
FCS (Frame Check Sequence) generation, detection
Short frame detection
Abort automatic transmission, detection
Idle detection
Go Ahead detection
Transmit number data control
Processing data format
Encode/decode of NRZ (Non-Return to Zero)
Encode/decode of NRZI (Non-Return to Zero Inverted)
Encode/decode of FM (Frequency Modulation)
Decode in Manchester mode
3
µPD72001-11, 72001-A8
PIN CONFIGURATION (Top View)
• 40-pin plastic DIP (600 mil) : µPD72001C-11, µPD72001C-A8
DCDA
D7
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CTSA
DA
XI1A/STR
XI2A/SYNCA
TR CA
DA
R
X
D6
D5
D4
D3
D2
D1
D0
X
CA
X
T
X
RTSA
DRQR
X
A
9
RESET
CLK
GND
WR
RD
C/D
B/A
PRO
PRI
INTAK
INT
CTSB
DCDB
10
11
12
13
14
15
16
17
18
19
20
VDD
DRQT
XA
DTRA/DRQT B
X
DTRB/DRQR
RTSB
X
B
TX
DB
XI2B/SYNCB
XI1B/STR CB
DB
TR CB
X
RX
X
• 44-pin plastic QFP (10 × 10 mm) : µPD72001G-11-22, µPD72001G-A8-22
44 43 42 41 40 39 38 37 36 35 34
RTSB
1
33
32
31
30
29
28
27
26
25
24
23
PRO
B/A
C/D
RD
DTRB/DRQR
DTRA/DRQT
DRQT
XB
XB
XA
2
3
4
V
DD
5
WR
GND
GND
D0
VDD
6
CLK
7
RESET
8
DRQR
RTSA
DA
XA
9
D1
10
D2
T
X
11
D3
12 13 14 15 16 17 18 19 20 21 22
IC: Internally Connected (Leave this pin unconnected)
4
µPD72001-11, 72001-A8
• 52-pin plastic QFP (14 × 14 mm) : µPD72001GC-11-3B6, µPD72001GC-A8-3B6
52 51 50 49 48 47 46 45 44 43 42 41 40
TXDA
1
39
38
37
36
35
34
33
32
31
30
29
28
27
RTSB
TXDB
TRXCA
2
XI2A/SYNCA
3
XI2B/SYNCB
XI1B/STRXCB
RXDB
XI1A/STRXCA
4
RXCA
CTSA
IC
5
6
TRXCB
IC
7
DCDA
D7
8
DCDB
CTSB
INT
9
D6
10
11
12
13
D5
INTAK
PRI
D4
D3
PRO
14 15 16 17 18 19 20 21 22 23 24 25 26
NC: No Connection
IC : Internally Connected (Leave this pin unconnected.)
• 52-pin plastic QFJ (750 × 750 mil) : µPD72001L-11
7
6
5
4
3
2
1 52 51 50 49 48 47
46
D2
NC
8
9
NC
45
44
43
42
41
40
39
38
37
36
35
34
RTSA
D1
10
11
12
13
14
15
16
17
18
19
20
DRQRXA
NC
NC
D0
RESET
CLK
GND
GND
WR
RD
VDD
VDD
DRQTXA
DTRA/DRQTXB
NC
C/D
NC
B/A
NC
DTRB/DRQRXB
NC
21 22 23 24 25 26 27 28 29 30 31 32 33
5
System CLK
CLK/Stby
Cont.
CLK
Ch.B
DB
Buf.
D7-0
Internal Bus
CR
BRG
-H,L
SR
12-15
CR/SR
8-9
CR
6-7
T
Buf.
X
RD
WR
Cont.
Sign.
SR0
R
X
0-5
10-15
RD/WR
Cont.
0-3 4-7
Buf.
T
X
RX
CLK
C/D
SR1-4
10-11
B/A
BRG
DPLL
RESET
T
X
RX
Cont.
Transmitter
R
X
CLK
CLK
DRQR
XA
XA
XB
XB
T
X
R
X
CLK
Cont.
T
X
DMA
Cont.
DRQT
DTRB/DRQR
DTRA/DRQT
µ
OSC
Receiver
INT
INTAK
PRI
INT
Ch.A
Cont.
PRO
Interface
Cont.
µPD72001-11, 72001-A8
1. PIN FUNCTIONS
The functions of the MPSC can be broadly classified into “system interface functions” that control interfacing with
the host system, and “transmission/reception functions” to transmit or receive data. This section explains the functions
of the pins of the MPSC by classifying the pins into those related to system interfacing and those related to transmission
and reception.
Hereafter, “H” (voltage level satisfying VIH in the case of an input pin, or voltage level satisfying VOH in the case
of an output pin) and “L” (voltage level satisfying VIL in the case of an input pin, or voltage level satisfying VOL in the
case of an output pin) are used to indicate the input/output status of a pin.
1.1 Pins Related to System Interface
(1) VDD
Supply voltage pin
(2) GND
GND pin
(3) RESET ... Input
This pin inputs a signal from an external device to reset the MPSC. When “L” is input to this pin for the duration
of 2 clock cycles (2tCYK) or longer, the MPSC is reset (this is called system reset).
As a result of system reset, the transmitter, receiver, and interrupt/DMA functions of the MPSC are disabled, and
the TXD pin and general-purpose output pins go high. In this case, because all bits of the control register (CR)
are also reset, CR must be set again if a system reset has been executed.
Table 1-1 shows the status of each pin at system reset, in comparison with the pin status at channel reset (CR0:
D5, D4, D3 = “0, 1, 1”).
The MPSC automatically enters the standby mode at system reset, lowering the power consumption from that
in the normal operation mode.
7
µPD72001-11, 72001-A8
Table 1-1. Pin Status at Reset
Pin Status
Pin Name
I/O
RESET (system reset)
Channel reset
WR
RD
I
I
–
–
–
–
B/A
I
–
–
C/D
I
–
–
D7 to D0
INT
I/O
O
I
–
–
High impedance
High impedance
INTAK
PRI
–
–
I
–
–
PRO
O
O
O
O
Depends on PRI
Depends on PRI
DRQTXA
DRQRXA
“L”
“L”
“L”
“L”
DTRA/DRQTXB,
DTRB/DRQRXB
DTR function, “H”
Retains current status
TXDA, TXDB
RXDA, RXDB
O
I
“H”
“H”
–
–
TRXCA, TRXCB
I/O
I
Input status
–
Retains current status
–
XI1A/STRXCA
XI1B/STRXCB
XI2A/SYNCA
XI2B/SYNCB
I/O
Input status
Retains current status
RTSA, RTSB
CTSA, CTSB
DCDA, DCDB
O
I
“H”
–
“H”
–
I
–
–
– : Undefined
(4) CLK (System Clock) ... Input
This pin inputs the system clock. The input frequency must be five times that of the data transfer rate or higher.
(5) WR (Write) ... Input
This pin inputs a write control signal for control words and transmit data. This pin is active-low.
(6) RD (Read) ... Input
This pin inputs a read control signal for status and receive data. This pin is active-low.
(7) B/A (Channel B/Channel A) ... Input
This pin inputs a signal to select a channel to be accessed when data is written or read. When this pin is “L”,
channel A is selected; when it is “H”, channel B is selected.
(8) C/D (Control/Data) ... Input
This pin inputs a signal that determines the type of the data on the data bus when the data is written or read.
8
µPD72001-11, 72001-A8
Table 1-2 shows the selection operations by WR, RD, B/A, and C/D.
Table 1-2. MPSC Control Signals and Operations
WR RD B/A C/D
Operation
L
H
L
H
L
H
L
L
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Writes transmit data to TX buffer
Reads receive data from RX buffer
Writes control register
L
L
H
L
H
L
H
H
H
L
H
Reads status register
H
×
H
L
H
L
×
×
High-impedance state or INTAK sequence
Setting prohibited
×
× : Don’s Care
(9) D7 through D0 (Data Bus) ... I/O
These pins constitute a three-state 8-bit bidirectional data bus. This data bus is connected to the data bus of
the host processor to transfer control words, status, and transmit/receive data.
(10) INT (Interrupt) ... Output (open drain)
This pin outputs an interrupt request signal. If an interrupt occurs in the MPSC, it goes low (active). Because
this is an open-drain output pin, it must be pulled up.
(11) INTAK (Interrupt Acknowledge) ... Input
This pin inputs a signal to acknowledge interrupt request signals issued by the MPSC. This pin is active-low.
This pin is used when the vector mode (CR2A: D7 = “1”) is selected, and must be pulled up to “H” when the non-
vector mode (CR2A: D7 = “0”) is selected.
(12) PRI (Priority Input) ... Input
This input pin is used for an interrupt generation request signal and for an output control signal for interrupt vectors.
In the normal operation mode, this pin provides an interrupt generation control function. During the INTAK
sequence, it provides an output control function for interrupt vectors. How this pin is used differs depending on
the interrupt mode.
(a) In vector mode (CR2A: D7 = “1”)
In the normal operation mode, the PRI pin is used to control generation of interrupts. When interrupt vector
output mode of Type A-3 or Type B-2 (CR2A: D5, D4, D3 = “0, 1, 0” or “1, 0, 0”) is selected, interrupts can
be generated regardless of whether the PRI pin is “L” or “H”.
If any other interrupt vector output mode is selected, the PRI pin must be kept “L” to enable generation of
interrupts.
During the INTAK sequence, an interrupt vector is output if “L” is input to the PRI pin in any interrupt vector
output mode, and output of the interrupt vector is disabled if “H” is input to PRI.
9
µPD72001-11, 72001-A8
(b) Non-vector mode (CR2A: D7 = “0”)
In this mode, the PRI pin controls only the generation of interrupts because the INTAK sequence is not used.
If an interrupt vector output mode other than Type A-3 and Type B-2 is selected, generation of an interrupt
signal is enabled if “L” is input to the PRI pin. The interrupt signal is not generated if “H” is input to PRI.
If an interrupt daisy chain is configured, inputting “L” to this pin indicates that a device having a higher priority
does not acknowledge interrupt processing or does not have an interrupt request, and only the MPSC with
“L” input to its PRI pin can generate an interrupt.
(13) PRO (Priority Output) ... Output
This pin is used when an interrupt daisy chain is configured. This output pin is active-low, and controls generation
of interrupts requests from a device with a lower priority. Usually, this pin is used along with the PRI pin, and
its operation is as follows:
When PRI = “H”, PRO = “H”
When PRI = “L”, PRO goes “H” if there is an interrupt request, and goes “L” if there is no interrupt request.
(14) DRQTXA (DMA Request TXA) ... Output
This pin outputs a DMA request to a DMA controller. This pin is active-high. It goes “H” if the transmitter of channel
A has entered the TX Buffer Empty status. The condition under which this pin goes “H” differs as follows depending
on the setting of the CR1 and D2 bits.
CR1: D2 = “0”: The DRQTXA pin goes “H” when the transmitter has entered the TX Buffer Empty status after
the first transmit data has been written. It does not go “H” when the transmitter has entered
the TX Buffer Empty status after reset.
CR1: D2 = “1”: The DRQTXA pin goes “H” when the transmitter has entered the TX Buffer Empty status.
This signal is reset when transmit data has been written to channel A.
(15) DRQRXA (DMA Request RXA) ... Output
This pin outputs a DMA request to a DMA controller. This pin is active-high and goes “H” if the receiver of channel
A has entered the RX Character Available status. This signal is reset only when receive data has been read from
channel A.
(16) DTRA/DRQTXB (Data Terminal Ready A/DMA Request TXB) ... Output
The function of this pin is changed as follows depending on the setting of CR2A: D1 and D0.
(a) When CR2A: D1, D0 = “0, 0” or “0, 1”
This pin functions as the DTRA pin. This pin is a general-purpose output pin and can be used to control a
modem, etc. The operation of the DTRA pin is as follows:
When CR5A: D7 = “0”, DTRA = “H”
When CR5A: D7 = “1”, DTRA = “L”
(b) When CR2A: D1, D0 = “1, 0”
This pin functions as the DRQTXB output pin. The function of this pin is the same as the DRQTXA pin, except
this pin is used with channel B.
(17) DTRB/DRQRXB (Data Terminal Ready B/DMA Request RXB) ... Output
The function of this pin changes as follows depending on the setting of CR2A: D1 and D0.
10
µPD72001-11, 72001-A8
(a) When CR2A: D1, D0 = “0, 0” or “0, 1”
This pin functions as the DTRB output pin. The function of this pin is the same as the DTRA pin, except this
pin is used with channel B.
(b) When CR2A: D1, D0 = “1, 0”
This pin functions as the DRQRXB output pin. The function of this pin is the same as the DRQRxA pin, except
this pin is used with channel B.
(18) CTSA (Clear to Send A) and CTSB (Clear to Send B) ... Input
This pin is a general-purpose input pin and can be used to control a modem, etc. Changes in the status of this
pin affect the latching operation of the E/S bit. When E/S INT is enabled (CR1: D0 = “1”), the E/S interrupt is
generated.
If the Auto Enable mode (CR3: D5 = “1”) is set, the transmitter can be controlled by using the TX Enable bit (CR5:
D3) and this pin. This is illustrated in Table 1-3.
Table 1-3. Auto Enable Mode and CTS Pin
CTS Pin
TX Enable Bit
Transmitter Status
Enabled
L
H
1
1
0
Disabled
H or L
Disabled
(19) DCDA (Data Carrier Detect A) ... Input
DCDB (Data Carrier Detect B) ... Input
These are general-purpose input pins and can be used to control a modem, etc. Changes in the status of this
pin affect the latching operation of the E/S bit. When E/S INT is enabled (CR1: D0 = “1”), the E/S interrupt is
generated.
If the Auto Enable mode (CR3: D5 = “1”) is set, the receiver can be controlled by using the RX Enable bit (CR3:
D0) and this pin. This is illustrated in Table 1-4.
Table 1-4. Auto Enable Mode and DCD Pin
DCD Pin
RX Enable Bit
Receiver Status
Enabled
L
H
1
1
0
Disabled
H or L
Disabled
(20) RTSA (Request to Send A) ... Output
RTSB (Request to Send B) ... Output
These are general-purpose output pins and can be used to control a modem, etc. The operations of these pins
differ depending on the setting of the operation protocol and the setting of the Auto Enable bit, as shown in Table
1-5.
11
µPD72001-11, 72001-A8
Table 1-5. Auto Enable Bit and RTS Pin
Function
Auto Enable Bit
RTS Cont. Bit
RTS Pin Status
Protocol
Start-stop
0
1
0
H
L
synchronization
1
When “0” from beginning
H
If set to “1” once and then reset
to “0”
If “L” while All SentNote = “0”,
and “H” if All Sent = “1”
1
0
1
L
H
L
COP/BOP
Don’t Care
Note SR1: D2
1.2 Pins Related to Transmission/Reception
(1) TXDA (Transmit Data A) and TXDB (Transmit Data B) ... Output
These pins output transmit data.
(2) RxDA (Receive Data A) and RxDB (Receive Data B) ... Input
These pins input receive data.
(3) XI1A/STRXCA (Crystal Input 1A/Source of Transmit Receive Clock A) ... Input
XI1B/STRXCB (Crystal Input 1B/Source of Transmit Receive Clock B) ... Input
The functions of these pins change depending on the setting of CR15: D7.
(a) When CR15: D7 = “0”
These pins function as the STRXC pins, and input the transmission and reception clocks, or input source
clocks to the internal BRG (Baud Rate Generator) and DPLL (Digital Phase Locked Loop).
(b) When CR15: D7 = “1”
These pins function as XI1 pins and connect one end of the crystal for transmission/reception clock source
oscillation.
(4) XI2A/SYNCA (Crystal Input 2A/Synchronization A) ... I/O
XI2B/SYNCB (Crystal Input 2B/Synchronization B) ... I/O
The functions of these pins change depending on the setting of CR15: D7.
(a) When CR15: D7 = 0
These pins function as SYNC pins. The functions of the SYNC pins differ as shown in Table 1-6, depending
on the setting of CR4.
(b) When CR15: D7 = “1”
These pins function as XI2 pins and connect one end of the crystal for transmission/reception clock source
oscillation.
12
µPD72001-11, 72001-A8
Table 1-6. Functions of SYNC Pins and Setting of CR4 (when CR15: D7 = “0”)
CR4
D5 D4
Operation Synchronization
SYNC Pin
Function
Function
Protocol
Detection Mode
D7
D6
D3
D2
Start-stop
synchro-
nization
Input
×
×
×
0
1
1
1
0
1
The SYNC pins function as general-purpose
input pins. Changes in the status of these pin
(“H” →“L” or “L” → “H”) affect the latch
operation of the Sync/Hunt bit (SR1: D4), and
cause the E/S interrupt.
COP
Internal
synchro-
nization
Output
Input
If a SYNC character is detected in the receive
character, the SYNC pins go “L” for the
duration of 1RXC cycle.
0
0
0
1
1
1
External
synchro-
nization
0
0
0
1
0
0
The SYNC pins input a signal for establishing
character synchronization. When these pins
go “L” from “H”, execution exits from the Hunt
Phase and character synchronization is
established. While SYNC input is “L”,
character synchronization is maintained.
Assembling a receive character is started at
the rising edge of the receive clock preceding
the falling of the SYNC input.
BOP
No function
×
1
0
The SYNC pins do not function.
× : Don’t Care
Caution If a pattern in which 1 bit (“0” or “1”) is inserted in between the “Sync character assigned to CR7”
and “Sync character assigned to CR6” is received while data is being assembled in the Bi-Sync
mode, an “L” pulse of about 1 bit may be generated on the SYNC pin. If the Enter Hunt command
is issued while this “L” pulse is present, the command is invalid. However, the recieve operation
of the MPSC is not affected at all by the reception of this pattern.
(5) TRXCA (Transmit Receive Clock A) ... I/O
TRXCB (Transmit Receive Clock B) ... I/O
(a) When CR15: D2 = “0”
These pins input the transmit and receive clocks. They are used to supply external transmit and receive
clocks.
[Exception] If either CR15: D6, D5 = “0, 1” or D4, D3 = “0, 1”, or both are set, the TRXCA and TRXCB pins
function as input pins, even if CR15: D2 = “1”.
(b) When CR15: D2 = “1”
These pins function as output pins. The source of the output clock can be selected from a crystal oscillation
circuit, BRG, DPLL, or transmit clock, depending on the setting of CR15: D1, D0. Under the conditions
explained in [Exception] in (a) above, they unconditionally serve as input pins, and the setting of CR15: D2,
D1, D0 is invalid.
13
Terminal adapter for ISDN
µ
PD72001-11
µ
PD98201
S-I/F
HDLC
SYNC
Dch
ASYNC
µ
Trans-
former
ISDN circuit
HDLC
SYNC
Bch
ASYNC
Bus
µ
PD72002-11
RS-232-C
D/R
µ
HDLC
SYNC
ASYNC
CPU
(with DMAC)
ROM
RAM
Personal computer
µPD72001-11, 72001-A8
3. ELECTRICAL SPECIFICATIONS
(1) µPD72001-11
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Symbol
VDD
VI
Condition
Ratings
Unit
V
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
–40 to +85
Input voltage
V
Output voltage
VO
V
Operating temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Be sure to use the product(s) within the ratings.
DC Characteristics
µPD72001-11 (TA = –40 to +85 °C, VDD = 5 V ± 10 %)
Parameter
Symbol
VIHC
VIH
Condition
CLK, STRXC, TRXC
MIN.
3.3
TYP.
MAX.
VDD + 0.5
VDD + 0.5
+0.6
Unit
V
High-level input voltage
Other pins
2.2
V
Low-level input voltage
VILC
VIL
CLK, STRXC, TRXC
Other pins
–0.5
–0.5
0.7 VDD
V
+0.8
V
High-level output voltage
Low-level output voltage
High-level input leakage current
Low-level input leakage current
High-level output leakage current
Low-level output leakage current
Supply current
VOH
VOL
ILIH
IOH = –400 µA
IOL = 2.0 mA
VI = VDD
V
0.45
10
V
µA
µA
µA
µA
mA
mA
ILIL
VI = 0 V
–10
10
ILOH
ILOL
IDD
VO = VDD
VO = 0 V
–10
40
At 11 MHz
20
In standby modeNote
1
Note System clock
: 11 MHz
: Inactive
Input pin
• High-level input voltage : (VDD – 0.3 V) to (VDD + 0.5 V)
• Low-level input voltage : 0 V to 0.3 V
Output pin
: Leave unconnected.
15
µPD72001-11, 72001-A8
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Condition
MIN.
MAX.
10
Unit
pF
fC = 1 MHz
Pins other than test pin: 0 V
CIO
20
pF
AC Characteristics
µPD72001-11 (TA = –40 to +85 °C, VDD = 5 V ± 10 %)
System interface:
Rated Value
Parameter
Symbol
Condition
Unit
MIN.
MAX.
2 000
1 000
1 000
10
Clock cycle
tCYK
tWKH
tWKL
tKR
90
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock high-pulse width
Clock low-pulse width
Clock rise time
1.5 V → 3.0 V
3.0 V → 1.5 V
Clock fall time
tKF
10
Address setup time (vs. RD ↓)
Address hold time (vs. RD ↑)
RD pulse width
tSAR
tHRA
tWRL
tDAD
0
0
120
Address → data output delay time
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
100
110
100
110
85
RD → data output delay time
tDRD
ns
RD → data float delay time
Address setup time (vs. WR ↓)
Address hold time (vs. WR ↑)
WR pulse width
tFRD
tSAW
tHWA
tWWL
tSDW
10
0
ns
ns
ns
ns
ns
0
120
100
90
0
Data setup time (vs. WR ↑)
TA = –10 to +70 °C
TA = –40 to +85 °C
Data hold time (vs. WR ↑)
tHWA
tRV
ns
ns
Recovery time between RD and WR
140
16
µPD72001-11, 72001-A8
Serial control:
Rated Value
Unit
Parameter
Symbol
Condition
MIN.
MAX.
Transmit/receive data cycle
tCYD
tCYC
tWCH
tWCL
5
tCYK
ns
STRXC, TRXC input clock cycle
90
40
40
45
STRXC, TRXC input
clock pulse width
High
Low
ns
TA = –10 to +70 °C
ns
TA = –40 to +85 °C
×1 mode, COP, BOP
×16, 32, 64 mode
TRXC is output
STRXC, TRXC ↓ → TXD delay time
tDTCTD1
tDTCTD2
tDTCTD3
tSRDRC
tHRCRD
tDRDTD1
tDRDTD2
tDTDIQ
100
300
100
ns
ns
TRXC ↓ → TXD delay time
0
0
ns
RXD setup time (vs. STRXC, TRXC ↑)
RXD hold time (vs. STRXC, TRXC ↑)
RXD → TXD delay time
When DPLL is not used
When DPLL is not used
ECHO BACK mode
Without SDLC Loop delay
TX INT mode
ns
120
ns
100
100
6
ns
ns
TXD → INT delay time
4
4
7
7
tCYK
tCYK
tCYK
tCYK
ns
TXD → DRQTX delay time
tDTDDQ
tDRCIQ
tDRCDQ
tDRDQ
TX DMA mode
6
Note
RXC ↑
RXC ↑
→ INT delay time
RX INT mode
11
Note
→ DRQRX delay time
RX DMA mode
11
RD ↓ → DRQRX ↓ delay time
WR ↓ → DRQTX ↓ delay time
120
120
tDWDQ
ns
Note Of STRXC and TRXC, the one used as the receive clock.
Interrupt control:
Rated Value
Parameter
Symbol
Condition
Unit
MIN.
MAX.
INTAK low-pulse width
tWIAL
tWIAH
120
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INTAK high-pulse width
PRI → PRO delay time
tDPIPO
tDIQPO
tDIAIQ
50
INT ↓ → PRO ↑ delay time
2nd INTAK ↓ → INT ↑ delay time
–20
+50
120
300
150
300
INT output level = 0.8 VNote
INT output level = 2.2 VNote
INT output level = 0.8 VNote
INT output level = 2.2 VNote
When vector output is enabled
SR2B read RD ↓ → INT ↑delay time
tDRDIQ
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
INTAK → data output delay time
INTAK → data float delay time
tSPIIA1
tHIAPI1
tSPIIA2
tHIAPI2
tDIAD
0
20
20
20
When vector output is disabled
120
85
tFIAD
10
Note Measured value with 2-kΩ pull-up resistor and 100-pF load capacitance connected
17
µPD72001-11, 72001-A8
Modem control:
Rated Value
Unit
Parameter
Symbol
Condition
MIN.
MAX.
CTS, DCD, SYNC pulse
width
High
Low
tWMH
tWML
2
2
tCYK
tCYK
tCYK
tCYK
CTS, DCD, SYNC → INT delay time
STRXC, TRXC ↑ → SYNC setup time
tDMIQ
2
2
TSSYRC
COP external synchronization
0
Communication control:
Rated Value
Parameter
Symbol
Condition
Unit
MIN.
MAX.
Transmit enable command
tDTETD1
tDTETD2
tSRERC
ASYNC, COP
BOP
3
7
tCYC
tCYC
tCYC
(WR ↑, CTS ↓) → TXD delay time
4
1
Receive enable command (DCD ↓)
setup time (vs. start bit, STRXC ↑,
TRXC ↑ of sync character)Note
Receive enable command (DCD ↓)
hold time (vs. STRXC ↑, TRXC ↑)Note
tHRCRE1
tHRCRE2
ASYNC
COP
7
tCYK
20tCYC
+ 8tCYK
tHRCRE3
BOP
3tCYC
+ 8tCYK
Receive clock (STRXC, TRXC)Note
hold time (vs. stop bit, MSB of CRC,
MSB of end flag)
tHRDRC1
tHRDRC2
tHRDRC3
tSRCRD1
tSRCRD2
ASYNC
COP
1
22
5
Bit
tCYC
tCYC
Bit
BOP
Receive clock (STRXC, TRXC)Note
setup time (vs. start bit, sync character)
ASYNC
COP, BOP
1
1
tCYC
Note Of STRXC and TRXC, the one used as the receive clock.
Crystal oscillation and reset
Rated Value
Parameter
Symbol
Condition
Unit
MIN.
MAX.
2000
XI1 input cycle time
RESET pulse width
tCYX
90
2
ns
tWRSL
tCYK
Caution The system clock cycle in all modes must be five times that of the data rate.
18
µPD72001-11, 72001-A8
AC Test Input/Output Waveform (except clock)
2.4
2.2
2.2
0.8
Test points
0.8
0.45
AC Test Clock Input Waveform
3.3
0.6
3.3
Test points
0.6
Load Condition
DUT
CL = 100 pF
CL includes jig capacitance
Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load
capacitance of this device to within 100 pF by inserting a buffer or by some other means.
Remark DUT: Tested device
19
µPD72001-11, 72001-A8
(2) µPD72001-A8
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Supply voltage
Symbol
VDD
VI
Condition
Ratings
Unit
V
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
–40 to +85
Input voltage
V
Output voltage
VO
V
Operating temperature
Storage temperature
TA
°C
°C
Tstg
–0 to +150
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the product(s). Be sure to use the product(s) within the ratings.
DC Characteristics (TA = –40 to +85 °C, VDD = 3.3 V ± 0.3 V)
Parameter
Symbol
VIHC
VIH
Condition
CLK, STRXC, TRXC
MIN.
0.8 VDD
1.8
TYP.
MAX.
VDD + 0.5
VDD + 0.5
0.15 VDD
+0.6
Unit
V
High-level input voltage
Other pins
CLK, STRXC, TRXC
Other pins
IOH = –400 µA
IOL = 2.0 mA
VI = VDD
V
Low-level input voltage
VILC
VIL
–0.5
–0.5
2.2
V
V
High-level output voltage
Low-level output voltage
VOH
VOL
ILIH
V
0.5
10
V
High-level input leakage current
Low-level input leakage current
µA
µA
µA
ILIL
VI = 0 V
–10
10
High-level output leakage
current
ILOH
VO = VDD
Low-level output leakage
current
ILOL
IDD
VO = 0 V
–10
µA
Supply current
At 8 MHz
5
20
1
mA
mA
In standby modeNote
Note System clock
: 8 MHz (TA = –10 to +70 °C)/7.14 MHz (TA = –40 to +85 °C)
Input pin
: Inactive
• High-level input voltage : (VDD – 0.3 V) to (VDD + 0.5 V)
• Low-level input voltage : 0 V to 0.3 V
Output pin
: Leave unconnected.
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input capacitance
I/O capacitance
Symbol
Condition
MIN.
MAX.
10
Unit
pF
CIN
CIO
fC = 1 MHz
Pins other than test pin: 0 V
20
pF
20
µPD72001-11, 72001-A8
AC Characteristics (TA = –40 to +85 °C, VDD = 3.3 V ± 0.3 V)
System interface:
Rated Value
Unit
Parameter
Symbol
Condition
TA = –10 to +70 °C
MIN.
125
140
50
MAX.
2000
2000
1000
1000
10
Clock cycle
tCYK
ns
ns
ns
ns
ns
ns
ns
TA = –40 to +85 °C
Clock high-pulse width
Clock low-pulse width
Clock rise time
tWKH
tWKL
tKR
50
1.5 V → 2.2 V
Clock fall time
tKF
2.2 V → 1.5 V
10
Address setup time (vs. RD ↓)
tSAR
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
0
5
Address hold time (vs. RD ↑)
RD pulse width
tHRA
tWRL
tDAD
tDRD
0
ns
ns
ns
ns
5
150
155
Address → data output delay time
RD → data output delay time
120
125
120
125
120
RD → data float delay time
Address setup time (vs. WR ↓)
Address hold time (vs. WR ↑)
tFRD
tSAW
tHWA
10
0
ns
ns
ns
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
0
5
WR pulse width
tWWL
tSDW
tHWD
tRV
150
155
120
125
0
ns
ns
ns
ns
Data setup time (vs. WR ↑)
Data hold time (vs. WR ↑)
Recovery time between RD and WR
5
180
190
21
µPD72001-11, 72001-A8
Serial control:
Rated Value
Unit
Parameter
Symbol
Condition
MIN.
MAX.
Transmit/receive data cycle
tCYD
tCYC
5
tCYK
ns
STRXC, TRXC input clock cycle
TA = –10 to +70 °C
125
140
50
DC
DC
DC
DC
DC
DC
140
145
300
305
100
TA = –40 to +85 °C
ns
STRXC, TRXC input
clock pulse width
tWCH
tWCL
High level
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
ns
55
ns
Low level
60
ns
65
ns
STRXC, TRXC↓ → delay time
tDTCTD1
tDTCTD2
×1 mode, COP,
ns
BOP
ns
×16, 32, 64 mode
ns
ns
TRXC↓ → TxD delay time
tDTCTD3
tSRDRC
TRXC is output
0
0
ns
RXD setup time (vs. STRXC, TRXC ↑)
When DPLL is
not used
TA = –10 to +70 °C
TA = –40 to +85 °C
TA = –10 to +70 °C
TA = –40 to +85 °C
ns
5
ns
RXD hold time (vs. STRXC, TRXC ↑)
RXD → TXD delay time
tHRCRD
When DPLL is
not used
140
145
ns
ns
tDRDTD1
tDRDTD2
tDTDIQ
tDTDDQ
tDRCIQ
tDRCDQ
tDRDQ
ECHO BACK mode
100
100
6
ns
Without SDLC Loop delay
TX INT mode
ns
TXD → INT delay time
4
4
7
7
tCYK
tCYK
tCYK
tCYK
ns
TXD → DRQTX delay time
TX DMA mode
6
Note
RxC ↑
RxC ↑
→ INT delay time
RX INT mode
11
Note
→ DRQRX delay time
RX DMA mode
11
RD ↓ → DRQRX ↓ delay time
WR ↓ → DRQTX ↓ delay time
140
140
tDWDQ
ns
Note Of STRXC and TRXC, the one used as the receive clock.
22
µPD72001-11, 72001-A8
Interrupt control:
Rated Value
Unit
Parameter
Symbol
Condition
MIN.
150
150
MAX.
INTAK low-pulse width
tWIAL
tWIAH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INTAK high-pulse width
PRI → PRO delay time
tDPIPO
tDIQPO
tDIAIQ
50
INT↓ → PRO ↑ delay time
2nd INTAK ↓ → INT ↑ delay time
–20
+50
120
300
170
180
350
INT output level = 0.8 VNote
INT output level = 1.8 VNote
SR2B read RD ↓ → INT ↑ delay time
tDRDIQ
INT output level
= 0.8 VNote
TA = –10 to +70 °C
TA = –40 to +85 °C
INT output level = 1.8 VNote
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
tSPIIA1
tHIAPI1
tSPIIA2
tHIAPI2
When vector output is enabled
0
20
20
20
25
When vector output
is disabled
TA = –10 to +70 °C
TA = –40 to +85 °C
INTAK → data output delay time
INTAK → data float delay time
tDIAD
120
130
tFIAD
10
Note Measured value with 2-kΩ pull-up resistor and 100-pF load capacitance connected
Modem control:
Rated Value
Parameter
Symbol
Condition
Unit
MIN.
MAX.
CTS, DCD, SYNC
pulse width
High
Low
tWMH
tWML
2
2
tCYK
tCYK
tCYK
tCYK
CTS, DCD, SYNC → INT delay time
STRXC, TRXC ↑ → SYNC setup time
tDMIQ
tSSYRC
2
2
COP external synchronization
0
23
µPD72001-11, 72001-A8
Communication control:
Rated Value
Unit
Parameter
Symbol
Condition
MIN.
MAX.
Transmit enable command (WR ↑,
CTS ↓) → TXD delay time
tDTETD1
tDTETD2
tSRERC
ASYNC, COP
BOP
3
7
tCYC
tCYC
tCYC
4
1
Receive enable command (DCD ↓)
setup time (vs. start bit, STRXC ↑,
TRXC ↑ of sync character)Note
Receive enable command (DCD ↓)
hold time (vs. STRXC ↑, TRXC ↑)Note
tHRCRE1
tHRCRE2
ASYNC
COP
7
tCYK
20 tCYC
+ 8tCYK
tHRCRE3
BOP
3tCYC
+ 8tCYK
Receive clock (STRXC, TRXC)Note
hold time (vs. start bit, MSB of CRC,
MSB of end flag)
tHRDRC1
tHRDRC2
tHRDRC3
tSRCRD1
tSRCRD2
ASYNC
COP
1
22
5
Bit
tCYC
tCYC
Bit
BOP
Receive clock (STRXC, TRXC)Note
setup time (vs. start bit, sync character)
ASYNC
COP, BOP
1
1
tCYC
Note Of STRXC and TRXC, the one used as the receive clock.
Crystal oscillation and reset:
Rated Value
Parameter
XI1 input cycle time
Symbol
Condition
Unit
ns
MIN.
MAX.
1000
1000
tCYX
TA = –10 to +70 °C
TA = –40 to +85 °C
125
140
2
RESET pulse width
tWRSL
tCYK
Caution The system clock cycle in all modes must be five times that of the data rate.
24
µPD72001-11, 72001-A8
AC Test Input Waveform (except clock)
2.2
0.5
1.8
0.6
1.8
0.6
Test points
AC Test Clock Input Waveform
0.8 VDD
0.8 VDD
Test points
0.15 VDD
0.15 VDD
Load Condition
DUT
CL = 100 pF
CL includes jig capacitance
Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load
capacitance of this device to within 100 pF by inserting a buffer or by any other means.
Remark DUT: Tested device
25
µPD72001-11, 72001-A8
Clock Timing
t
CYK
t
WKH
t
WKL
CLK
t
KF
t
KR
Read Cycle Timing
C/D, B/A
t
SAR
t
HRA
t
WRL
RD
t
DRD
t
FRD
Hi-Z
Hi-Z
D7-0
t
DAD
Write Cycle Timing
C/D, B/A
t
SAW
t
HWA
t
WWL
WR
t
SDW
t
HWD
Hi-Z
Hi-Z
D7-0
Read/Write Cycle Timing (except transfer of transmit/receive data)
t
RV
RD, WR
26
µPD72001-11, 72001-A8
Transmit Cycle Timing
t
CYC
t
WCL
t
WCH
STR
X
CA/B
CA/B
TRX
t
CYD
t
DTCTD3
T
XDA/B
t
DTDIQ
INT
t
DTDDQ
DRQT A/B
X
Receive Cycle Timing
t
CYC
t
WCL
t
WCH
STR
X
CA/B
CA/B
TRX
t
HRCRD
t
CYD
t
SRDRC
RXDA/B
t
DRCIQ
INT
t
DRCDQ
DRQR A/B
X
27
µPD72001-11, 72001-A8
Transmitter Enable Timing
CTS
WR
t
DTETD1, tDTETD2
TXD
Receiver Enable Timing
STR
X
C
C
TRX
RX
D
Note
t
SRERC
DCD
Note LSB of the first receive data (SYNC, flag)
Receive Clock Setting Timing
a. In ASYNC mode
STR
X
C
C
TRX
t
SRCRD1
Start bit
RXD
b. In COP/BOP mode
STR
X
X
C
C
TR
t
SRCRD2
RX
D
Note
Note LSB of sync pattern (SYNC, flag)
28
µPD72001-11, 72001-A8
DCD Timing, Receive Clock Hold Timing
a. In ASYNC mode
21 tDCY
STRXC
TRXC
tHRDRC1
Stop bit
RXD
tHRCRE1
DCD
b. COP/BOP mode
STR
X
C
C
TRX
t
HRDRC2, tHRDRC3
RXD
Note
t
HRCRE2, tHRCRE3
DCD
Note This bit is the MSB of BCS in the COP mode and MSB of the end flag in the BOP mode.
In ECHO BACK Mode and LOOP Mode
R
X
D
D
t
DRDTD1, tDRDTD2
T
X
29
µPD72001-11, 72001-A8
DMA Cycle Timing
DRQT
X
A/B
A/B
DRQR
X
t
DRDQ
RD
t
DWDQ
WR
PRO Output Timing
PRI
INT
t
DPIPO
t
DIQPO
PRO
INTAK Cycle Timing
PRI
(when vector
output is disabled)
t
t
SPIIA2
SPIIA1
t
HIAPI2
PRI
(when vector
output is enabled)
t
WIAH
t
HIAPI1
INTAK
RD
t
WIAL
t
DIAD
t
FIAD
Hi-Z
Hi-Z
D7-0
INT
t
DIAIQ
t
DRDIQ
30
µPD72001-11, 72001-A8
E/S Timing
t
WML
t
WMH
CTSA/B, DCDA/B, SYNCA/B
t
DMIQ
INT
SYNC Input Timing (external synchronization mode)
STR
X
X
CA/B
CA/B
TR
Last Bit of
SYNC Character
1st Bit of
Data Character
t
SSYRC
SYNCA/B Note
Note SYNCA/B input must be cleared to “0” at the rising edge of RXC two clock cycles after the last bit of the SYNC
character.
XI1 Input Timing
t
CYX
XI1
RESET Pulse
RESET
t
WRSL
31
µPD72001-11, 72001-A8
4. PACKAGE
40PIN PLASTIC DIP (600 mil)
40
21
20
1
A
K
L
I
J
H
M
G
R
C
F
M
D
N
B
NOTES
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
53.34 MAX.
2.54 MAX.
2.54 (T.P.)
2.100 MAX.
0.100 MAX.
0.100 (T.P.)
2) ltem "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
1.2 MIN.
3.6±0.3
0.047 MIN.
0.142±0.012
0.020 MIN.
0.170 MAX.
0.226 MAX.
0.600 (T.P.)
0.520
0.51 MIN.
4.31 MAX.
5.72 MAX.
15.24 (T.P.)
13.2
J
K
L
+0.10
0.25
+0.004
0.010
M
–0.05
–0.003
N
R
0.25
0.01
0~15°
0~15°
P40C-100-600A-1
32
µPD72001-11, 72001-A8
44 PIN PLASTIC QFP ( 10)
A
B
33
34
23
22
detail of lead end
44
1
12
11
G
M
H
I
J
K
N
L
P44G-80-22-2
NOTE
ITEM
MILLIMETERS
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
+0.017
13.6 0.4
10.0 0.2
10.0 0.2
13.6 0.4
1.0
A
B
C
D
F
0.535
–0.016
+0.008
–0.009
0.394
0.394
0.535
0.039
0.039
0.014
0.006
+0.008
–0.009
+0.017
–0.016
1.0
G
H
I
+0.004
–0.005
0.35 0.10
0.15
J
0.8 (T.P.)
1.8 0.2
0.031 (T.P.)
+0.008
K
L
0.071
–0.009
+0.009
1.0 0.2
0.039
–0.008
+0.10
+0.004
M
N
P
0.15
0.006
–0.05
–0.003
0.15
0.006
+0.005
1.45 0.1
0.05 0.05
1.65 MAX.
0.057
–0.004
Q
S
0.002 0.002
0.065 MAX.
33
µPD72001-11, 72001-A8
52 PIN PLASTIC QFP ( 14)
A
B
27
26
39
40
detail of lead end
52
1
14
13
G
M
I
H
J
K
N
L
P52GC-100-3B6,3BH-2
NOTE
ITEM
A
MILLIMETERS
INCHES
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
17.6 0.4
14.0 0.2
14.0 0.2
17.6 0.4
1.0
0.693 0.016
+0.009
B
0.551
–0.008
+0.009
C
0.551
–0.008
D
F
0.693 0.016
0.039
G
H
I
1.0
0.039
+0.004
0.40 0.10
0.20
0.016
–0.005
0.008
J
1.0 (T.P.)
1.8 0.2
0.039 (T.P.)
+0.008
K
0.071
–0.009
+0.009
L
0.8 0.2
0.031
–0.008
+0.10
+0.004
M
N
P
0.15
0.006
–0.05
–0.003
0.10
0.004
2.7
0.106
Q
S
0.1 0.1
3.0 MAX.
0.004 0.004
0.119 MAX.
34
µPD72001-11, 72001-A8
52 PIN PLASTIC QFJ ( 750 mil)
A
B
52
1
E
F
T
Q
K
M
M
N
P
P52L-50A1-2
NOTE
ITEM
MILLIMETERS
20.1 0.2
19.12
INCHES
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
+0.009
A
B
C
D
E
F
0.791
–0.008
0.753
0.753
0.791
0.076
0.024
0.173
0.110
19.12
+0.009
–0.008
20.1 0.2
1.94 0.15
0.6
+0.007
–0.006
+0.009
–0.008
G
H
I
4.4 0.2
2.8 0.2
0.9 MIN.
3.4
+0.009
–0.008
0.035 MIN.
0.134
J
K
M
N
P
Q
T
1.27 (T.P.)
0.40 0.10
0.12
0.050 (T.P.)
+0.004
0.016
–0.005
0.005
+0.009
18.04 0.20
0.15
0.710
–0.008
0.006
R 0.8
R 0.031
+0.10
+0.004
U
0.20
0.008
–0.05
–0.002
35
µPD72001-11, 72001-A8
5. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following conditions.
For details on the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Surface mount type
•
µPD72001G-11-22 : 44-pin plastic QFP (10 × 10 mm)
µPD72001G-A8-22: 44-pin plastic QFP (10 × 10 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Condition
Condition Symbol
Package peak temperature: 235 °C, Time: 30 seconds MAX.
(210 °C MIN.), Number of times: 2 MAX., Number of days: 7Note
(After that, prebaking for 10 hours at 125 °C is necessary.)
<Precaution>
IR35-107-2
VP15-107-2
WS60-107-1
Products other than in heat-resistance trays (such as those packaged
in a magazine, taping, or non-heat-resistance tray) cannot be baked
while they are in their package.
VPS
Package peak temperature: 215 °C, Time: 40 seconds MAX.
(200 °C MIN.), Number of times: 2 MAX., Number of days: 7Note
(After that, prebaking for 10 hours at 125 °C is necessary.)
<Precaution>
Products other than in heat-resistance trays (such as those packaged
in a magazine, taping, or non-heat-resistance tray) cannot be baked
while they are in their package.
Wave soldering
Solder bath temperature: 260 °C MAX., Time: 10 seconds MAX.,
Number of times: 1, Preheating temperature: 120 °C MAX.
(package surface temperature), Number of days: 7Note
(After that, prebaking for 10 hours at 125 °C is necessary.)
<Precaution>
Products other than in heat-resistance trays (such as those packaged
in a magazine, taping, or non-heat-resistance tray) cannot be baked
while they are in their package.
Partial heating
Pin temperature: 300 °C MAX., Time: 3 seconds MAX.
—
(per side of device)
Note The number of days the product can be stored at 25 °C, 65 % RH MAX. after the dry pack has been opened.
Caution Do not use two or more soldering methods in combination (except partial heating).
36
µPD72001-11, 72001-A8
•
µPD72001GC-11-3B6 : 52-pin plastic QFP (14 × 14 mm)
µPD72001GC-A8-3B6: 52-pin plastic QFP (14 × 14 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Condition
Package peak temperature: 235 °C, Time: 30 seconds MAX.
Condition Symbol
IR35-00-3
VP15-00-3
WS60-00-1
(210 °C MIN.), Number of times: 3 MAX.
VPS
Package peak temperature: 215 °C, Time: 40 seconds MAX.
(200 °C MIN.), Number of times: 3 MAX.
Wave soldering
Solder bath temperature: 260 °C MAX., Time: 10 seconds MAX.,
Number of times: 1
Preheating temperature: 120 °C MAX. (package surface temperature)
Partial heating
Pin temperature: 300 °C MAX., Time: 3 seconds MAX.
—
(per side of device)
Caution Do not use two or more soldering methods in combination (except partial heating).
•
µPD72001L-11: 52-pin plastic QFJ (750 × 750 mil)
Recommended
Soldering Method
Soldering Condition
Condition Symbol
VPS
Package peak temperature: 215 °C, Time: 40 seconds MAX.
(200 °C MIN.), Number of times: 1
VP15-00-1
—
Partial heating
Pin temperature: 300 °C MAX., Time: 3 seconds MAX.
(per side of device)
Through-hole type
µPD72001C-11 : 40-pin plastic DIP (600 mil)
•
µPD72001C-A8: 40-pin plastic DIP (600 mil)
Soldering Method
Soldering Condition
Wave soldering (pins only)
Partial heating
Solder bath temperature: 260 °C MAX., Time: 10 seconds MAX.
Pin temperature: 300 °C MAX., Time: 3 seconds MAX.
(per pin)
Caution When soldering this product using of wave soldering, exercise care that the solder does not come
in direct contact with the package.
37
µPD72001-11, 72001-A8
[MEMO]
38
µPD72001-11, 72001-A8
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
39
µPD72001-11, 72001-A8
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed : µPD72001-A8
License needed
: µPD72001-11
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
相关型号：
UPD720100AS1-2C-A
USB Bus Controller, CMOS, PBGA176, 15 X 15 MM, 0.80 MM PITCH, PLASTIC, FBGA-176
NEC
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