UPD720130_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD720130

USB2.0 to IDE Bridge

The µPD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The µPD720130 complies

with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The

µPD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine

(SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only

protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC

processor which is in the µPD720130. The software to control the µPD720130 is located in an embedded ROM. In

the future, the µPD720130 will be released to support external Flash Memory / EEPROM™ option to update function

by firmware.

Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.

µPD720130 User’s Manual: S16412E

FEATURES

•

Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)

Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)

USB2.0 high-speed bus powered device capability

Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)

One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver

USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)

Automatic chirp assertion and full-/high-speed mode change

USB Reset, Suspend and Resume signaling detection

Supports power control functionality for IDE device as CD-ROM and HDD

Supports set feature (TEST_MODE) functionality

System Clock is generated by 30 MHz X’tal

2.5 V and 3.3 V power supply

ORDERING INFORMATION

Part Number

Package

µPD720130GC-9EU

100-pin plastic TQFP (fine pitch) (14 × 14)

µPD720130GC-9EU-SIN

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S16302EJ3V0DS00 (3rd edition)

Date Published June 2003 NS CP (K)

Printed in Japan

The mark shows major revised points.

2002

µPD720130

BLOCK DIAGRAM

EPC2_V2

RAM

4 Kbytes×2

ROM

8 Kbytes

PHY_V2

CPU Core

(V30MZ)

USB Bus

IDE Bus

DCC

Bus Bridge

DMAC

IDEC_V2

GPIO

or

FSIO

Timer

INTC

FSIO

PIO

Serial

ROM

Direct Bus

Direct Command Bus

Ext. Bus (Data 8-bit Bus) or PIO

V30MZ

RAM

: CISC CPU core

: 8-Kbyte work RAM for firmware

: 8-Kbyte ROM for built-in firmware

: USB2.0 transceiver with serial interface engine

: Endpoint controller

ROM

PHY_V2

EPC_V2

IDEC_V2

DCC

: IDE controller

: ATA direct command controller

: Internal / external bus controller and DMA controller

: Interrupt controller (82C59 like)

: General purpose 8-bit I/O controller

: Multipurpose 14-bit I/O controller

: Flexible serial I/O

Bus Bridge

INTC

GPIO

PIO

FSIO

2

Data Sheet S16302EJ3V0DS

µPD720130

PIN CONFIGURATION (TOP VIEW)

• 100-pin plastic TQFP (fine pitch) (14 × 14)

µPD720130GC-9EU

µPD720130GC-9EU-SIN

V

DD25

DD33

75

70

65

V

DD25

DD33

1

5

XIN

CMB_STATE

PIO5

XOUT

VSS

CMB_BSY

PWR

RESETB

V

DD33

CLC

IRQ0

MD0

SPD

V

SS

MD1

10

15

20

25

DV0

IDECS1B

IDECS0B

IDEA2

DV1

DCC

PIO14

PIO15

GPIO0

IDEA0

IDEA1

VSS

60

55

V

SS

IDEINT

IDEDAKB

IDEIORDY

IDEIORB

TEST0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

TEST1

TEST3

V

DD33

DD25

V

DD33

DD25

3

Data Sheet S16302EJ3V0DS

µPD720130

Pin No.

1

Pin Name

V^DD25

Pin No.

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Pin Name

V^SS

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

Pin Name

V^DD25

Pin No.

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pin Name

V^SS

2

V^DD33

IDEIOWB

IDEDRQ

IDED15

IDED0

V^DD33

DPC

SDA

SCL

3

XIN

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

V^SS

4

XOUT

V^SS

5

TEST2

V^DD25

RPU

6

RESETB

V^DD33

7

IDED14

IDED1

IDED13

IDED2

V^DD25

8

IRQ0

V^DD25

V^SS

9

MD0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

MD1

RSDP

DP

IDECS1B

IDECS0B

IDEA2

IDEA0

IDEA1

V^SS

GPIO0

PIO15

PIO14

DCC

V^SS

V^DD33

DM

IDED12

IDED3

IDED11

IDED4

IDED10

V^DD33

RSDM

V^SS

DV1

DV0

AV^DD25

AV^SS

RREF

AV^SS(R)

AV^DD25

AV^SS

V^DD25

VBUS

SMC

V^SS

IDEINT

IDEDAKB

IDEIORDY

IDEIORB

TEST0

TEST1

TEST3

V^DD33

V^SS

SPD

IDED5

IDED9

IDED6

IDED8

IDED7

IDERSTB

V^SS

CLC

PWR

CMB_BSY

PIO5

CMB_STATE

V^DD33

V^DD25

Remark AV^SS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ.

4

Data Sheet S16302EJ3V0DS

µPD720130

1. PIN INFORMATION

(1/2)

Pin Name

I/O

Buffer Type

Active

Level

Function

XIN

I

2.5 V Input

System clock input or oscillator In

Oscillator out

XOUT

O

2.5 V Output

RESETB

MD(1:0)

IDECS(1:0)B

IDEA(2:0)

IDEINT

IDEDAKB

IDEIORDY

IDEIORB

IDEIOWB

IDEDRQ

IDED(15:0)

IDERSTB

DCC

I

3.3 V Schmitt Input

3.3 V Input

Low

Asynchronous reset signaling

Function mode setting

I

O (I/O)

I (I/O)

O (I/O)

I (I/O)

O (I/O)

I (I/O)

I/O

5 V tolerant Output

5 V tolerant Input

5 V tolerant Output

5 V tolerant Input

5 V tolerant Output

5 V tolerant Input

5 V tolerant I/O

5 V tolerant Output

3.3 V Input

Low

IDE host chip select

IDE address bus

High

Low

High

Low

High

IDE interrupt request from device to host

IDE DMA acknowledge

IDE IO channel ready

IDE IO read strobe

IDE IO write strobe

IDE DMA request from device to host

IDE data bus

O (I/O)

I (I/O)

O (I/O)

I (I/O)

O (I/O)

I/O

Low

IDE reset from host to device

IDE controller operational mode setting

Device select

DV(1:0)

CLC

3.3 V Input

System clock setting

PWR

3.3 V Input

Bus powered /self-powered select

Combo IDE bus busy

CMB_BSY

CMB_STATE

DPC

3.3 V Output

3.3 V Input

Combo IDE bus state

3.3 V Output

Power control signaling for IDE device

Serial ROM data signaling

Serial ROM clock signaling

VBUS monitoring

SDA

3.3 V I/O

SCL

I/O

3.3 V I/O

VBUS

I

5 V Schmitt Input ^Note

USB high speed D+ I/O

USB high speed D− I/O

DP

I/O

USB’s high speed D+ signal

USB’s high speed D− signal

DM

I/O

RSDP

O

USB full speed D+ Output

USB’s full speed D+ signal

USB’s full speed D− signal

USB’s 1.5 kΩ pull-up resistor control

Reference resistor

USB full speed D− Output

RSDM

O

RPU

A

USB Pull-up control

Analog

RREF

A

SPD

I (I/O)

I

3.3 V Input

NEC private

SMC

Scan mode control

TEST(3:0)

I

Test mode setting

Note

VBUS pin may be used to monitor for VBUS line even if V^DD33, V^DD25, and AV^DD25are shut off. System must

ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is

not exceeded.

5

Data Sheet S16302EJ3V0DS

µPD720130

(2/2)

Pin Name

I/O

Buffer Type

Active

Level

Function

GPIO(7:0)

I/O

I

3.3 V Schmitt I/O

General purpose IO port (for future extension)

IO port (for future extension)

External interrupt input (for future extension)

2.5 V V^DDfor Analog circuit

2.5 V V^DD

PIO(15:14)

PIO(5)

IRQ0

3.3 V I/O

3.3 V Schmitt I/O

3.3 V Schmitt Input

High

AV^DD25

V^DD25

V^DD33

3.3 V V^DD

AV^SS

V^SSfor Analog circuit

V^SS

Remarks 1. “5 V tolerant“ means that the buffer is 3.3 V buffer with 5 V tolerant circuit.

2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they

do not need to be considered in normal use.

6

Data Sheet S16302EJ3V0DS

µPD720130

2. FUNCTION INFORMATION

USB to IDE system can be realized by the µPD720130, Serial ROM which has USB vender ID, product ID, etc,

and power control circuit. The µPD720130 can be selected bus powered mode or self powered mode. If all power

consumption for USB to IDE system is less than the specification of bus powered device, it will be possible to realize

high-speed capable bus powered system. The µPD720130 has some features for bus powered system. Also, some

system may control target IDE device by two IDE controllers. At the time, IDE bus arbitration should be required to

each IDE controller. The µPD720130 has a feature of IDE bus arbitration, too.

The setting of IDE controller in the µPD720130 is controlled by data in serial ROM or external pin setting. If there

is any inconsistency between data in serial ROM and external pin setting, the data in serial ROM is higher priority than

external pin setting.

2.1

Data in Serial ROM

The µPD720130 loads some data such as Vendor ID, Product ID and some additional USB related information,

etc from serial ROM when the µPD720130 is initialized. Example of data in serial ROM is as follows. ExPinReset

and ExPinSet fields hold data which is related to the external pin setting.

Table 2-1. Data in Serial ROM

Data size

1 Word

1 Byte

Symbol

Description

Control for descriptor overwrite

Flags

ExPinReset

PWR, CLC, DCC, DV[1:0] Reset bit map field

PWR, CLC, DCC, DV[1:0] Set bit map field

idVendor field in Device descriptor

1 Byte

ExPinSet

1 Word

1 Byte

idVendor

idProduct

idProduct field in Device descriptor

bcdDevice

bcdDevice field in Device descriptor

MaxPower BUS

MaxPower Self

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

TxMode Reset

TxMode Set

MaxPower field in Configuration descriptor for Bus powered mode

MaxPower field in Configuration descriptor for Self powered mode

bInterfaceClass field in Interface descriptor

bInterfaceSubClass field in Interface descriptor

bInterfaceProtocol field in Interface descriptor

IDE transmission type such as Ultra DMA 66 Reset bit map field

IDE transmission type such as Ultra DMA 66 Set bit map field

String descriptor for Manufacturer

1 Byte

1 Word

32 Bytes

ManufactureString

ProductString

SerialString

String descriptor for Product

String descriptor for Device serial number

7

Data Sheet S16302EJ3V0DS

µPD720130

2.2

External Pin Setting

Usually, serial ROM should be used to keep Vendor ID, Product ID and some additional USB related

information. And then, the external pin setting of the µPD720130 is not so important to realize USB to IDE bridge

system. The recommended external pin setting is as follows.

Table 2-2. Recommended External Pin Setting

Pin Name

Setting

MD1

MD0

SCL

SDA

DV1

DV0

CLC

PWR

DCC

1

0

Pull Up ^{Note 1}

Pull Up

“L” clamp

Pull Down ^{Note 2}

“L” clamp

“H” clamp

“L” clamp

GPIO(7:0)

PIO(14:15)

PIO5

SPD

TEST(3:0)

SMC

IRQ0

Notes 1. If serial ROM size is more than 2 Kbytes, SCL should be pull down.

2. If target IDE device is not fixed, it is preferable that DCC pin can

switch pull-up or pull-down.

The setting for any other pins such as CMB_BSY, CMB_STATE depends on USB2.0 to IDE Bridge system.

For example, if two IDE controllers control one target IDE device and one of two IDE controllers is the µPD720130,

CMB_BSY and CMB_STATE are used to handshake between two IDE controller chips. On the other hand, when

the µPD720130 is only controller of target IDE device, CMB_BSY should be opened and CMB_STATE should be

clamped to “L”.

8

Data Sheet S16302EJ3V0DS

µPD720130

2.3

Control Bit in Serial ROM or External Pin Setting

The following tables show IDE status and control bit in serial ROM or external pin setting.

Table 2-3. DV1/DV0, CLC, PWR Setting

No.

Device Power

Bus Powered

Internal

Clock

ATA/ATAPI

Setting in Serial ROM or External Pin

PWR

1

CLC

1

DV1

1

DV0

1

0

7.5 MHz

60 MHz

No device connected

ATA

1

0

2

ATAPI

1

0

1

3

Reserved

1

0

4

No device connected

ATA

1

0

1

5

1

0

1

0

6

ATAPI

1

0

1

7

Reserved

1

0

8

Self Powered

No device connected

Combo (ATA)

Combo (ATAPI)

Reserved

0

1

9

0

1

0

10

11

12

13

14

15

0

1

0

1

0

1

0

No device connected

ATA

0

1

0

1

0

ATAPI

0

1

Auto device detect

0

Remark Setting No. 0, 3, 4, 7, 8, 11, and 12 are prohibited to use.

9

Data Sheet S16302EJ3V0DS

µPD720130

Table 2-4. DV1/DV0, DCC Setting

Condition

Mode

DCC

DCC Setting

in Serial

ROM

Description

DV1

1

DV0

0

Target

Device

Setting

ATA

0

1

0

1

0

1

0

1

No setting

Reset

Ultra, Multi Word DMA are disabled

Ultra, Multi Word DMA are enabled.

Ultra, Multi Word DMA are disabled

Ultra, Multi Word DMA are enabled.

Ultra DMA is disabled

Set

No setting

Reset

Set

0

1

ATAPI

No setting

Reset

Ultra DMA is disabled

Set

Ultra, Multi Word DMA are enabled.

Ultra DMA is disabled

No setting

Reset

Set

Ultra, Multi Word DMA are enabled.

Ultra, Multi Word DMA are disabled

Ultra, Multi Word DMA are enabled.

Ultra, Multi Word DMA are disabled

Ultra, Multi Word DMA are enabled.

Ultra DMA is disabled

0

Auto

ATA

No setting

Reset

device

detect

Set

No setting

Reset

Set

ATAPI

No setting

Reset

Ultra DMA is disabled

Set

Ultra, Multi Word DMA are enabled.

Ultra DMA is disabled

No setting

Reset

Set

Ultra, Multi Word DMA are enabled.

Remark PIO mode 0-4 are always enabled.

10

Data Sheet S16302EJ3V0DS

µPD720130

2.4

Combo Mode Function

The µPD720130 can be used to realize that two IDE controller chips control one target IDE device in one

system. To realize IDE bus arbitration between two IDE controller chips, the µPD720130 has CMB_BSY and

CMB_STATE. Combo mode is enabled when PWR = 0 and CLC = 1.

CMB_BSY and CMB_STATE connect to other IDE controller chip as follows.

Figure 2-1. CMB_BSY and CMB_STATE Connection between Two IDE Controller Chips

µ

Other IDE controller

PD720130

IDE Bus Grant

CMB_STATE

CMB_BSY

IDE Bus Request

Table 2-5. Description of CMB_BSY and CMB_STATE

Pin Name

Direction

IN

Value

Description

CMB_STATE

0

1

0

1

Other IDE controller does not require or does not use IDE bus.

Other IDE controller requires or is using IDE bus.

The µPD720130 does not require or does not use IDE bus.

The µPD720130 requires or is using IDE bus.

CMB_BSY

OUT

11

Data Sheet S16302EJ3V0DS

µPD720130

The IDE bus arbitration will be done by following sequence. The µPD720130 will confirm whether other

IDE controller requires or is using IDE bus or not. If other IDE controller does not require or does not use IDE

bus, the µPD720130 will use IDE bus.

Figure 2-2. IDE Bus Arbitration Sequence

START

Chip Init

Other IDE controller requires or

is using IDE bus.

CMB_STATE = 1?

Yes.

No.

CMB_BSY = 1

CMB_STATE = 0?

Yes.

No.

µ

The PD720130 can not use IDE bus

CMB_BSY = 0

IDE bus is used

µ

by the PD720130

END

12

Data Sheet S16302EJ3V0DS

µPD720130

2.5

Power Control

To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the µPD720130 has

two internal system clock mode. One is 7.5 MHz for bus-powered mode and the other is 60 MHz for self-powered

mode. The µPD720130 controls the power state by events as follows. The word with under line shows event.

The Italic word shows the power state.

Figure 2-3. Power State Control

(a) Bus-powered Mode

Vbus OFF

Power OFF

Vbus ON

Connect

Hardware Reset

Idle Mode

Power = PRESET

Default State

Bus Reset

FS CONNECT

HS CONNECT

FS Enumeration

State

Power = PENUM_FS

HS Enumeration

State

Power = PENUM_HS

Resume

Suspend

Set Configuration

Suspend

Resume

Suspend

Configured

Suspend

Mode

Configured

State

Suspend

Mode

State

Resume

Suspend

Power = PSPND

Suspend

Resume

FS Operation

State

HS Operation

State

Power = PHS_B

Power = PFS_B

(b) Self-powered Mode

Power OFF

Power ON

Hardware Reset

Disconnect

Mode

Vbus ON

Connect

Default

State

Vbus OFF

Idle Mode

Power = PRESET

CMB_STATE = 0

CMB_STATE = 1

Bus Reset

IDE Bus

Release

State

FS CONNECT

HS CONNECT

Power = PCOMBO

FS Enumeration

State

Power = PENUM_FS

HS Enumeration

State

Power = PENUM_HS

Resume

Suspend

Resume

Suspend

Resume

Suspend

Resume

Suspend

Set Configuration

Configured

State

Suspend

Mode

Configured

State

Suspend

Mode

Power = PSPND

Resume

HS Operation

State

FS Operation

State

Power = PFS_S

Power = PHS_S

13

Data Sheet S16302EJ3V0DS

µPD720130

To realize bus-powered USB2.0 to IDE Bridge system, the power consumption for IDE device should be

controlled by the power state of the µPD720130. The µPD720130 has DPC pin to control IDE device’s power

circuit. DPC pin’s output level relates to USB device states. DPC should be pull up to 3.3 V because DPC

output becomes high impedance state until the µPD720130 is initialized.

Figure 2-4. DPC Pin to Control IDE Device’s Power Circuit

High impedance state

Default

Un-configured

Configured

Suspend

Configured

Normal

Operation

DPC

Operation

Power ON

Hardware Reset

Set

Configuration

Suspend

Occured

Resume

Occured

Bus Reset

Following reference circuit can cut off power supply to IDE device during the µPD720130 is under default

and un-configured state. Also, the power supply to IDE device is disabled during suspend state, too.

Power consumption of total system under default, un-configured, and suspend state can be reduced by

DPC pin.

Figure 2-5. Power Control Circuit Example

Power supply rail

IDE Device

Power

3.3 V

IN

OUT

Regulator

µ

PD720130

Pull

Up

P-Channel Switch

DPC

ON

14

Data Sheet S16302EJ3V0DS

µPD720130

3. ELECTRICAL SPECIFICATIONS

3.1

Buffer List

•

2.5 V oscillator interface

XIN, XOUT

•

3.3 V input buffer

MD(1:0), TEST(3:0), SMC

3.3 V schmitt input buffer

RESETB, IRQ0

3.3 V input buffer with enable (OR type)

DCC, DV(1:0), SPD, CLC, PWR, CMB_STATE

3.3 V I^OL= 6 mA 3-state output buffer

CMB_BSY, DPC

3.3 V I^OL= 3 mA bi-directional schmitt buffer with input enable (OR-type)

GPIO(7:0), PIO5, SDA, SCL

3.3 V I^OL= 6 mA bi-directional buffer with input enable (OR-type)

PIO(15:14)

5 V schmitt input buffer

VBUS

5 V I^OL= 6 mA 3-state output buffer

IDECS(1:0)B, IDEA(2:0), IDEDAKB, IDEIORB, IDEIOWB, IDERSTB

5 V I^OL= 6 mA bi-directional buffer with input enable (OR-type)

IDED(15:0), IDEINT, IDEIORDY, IDEDRQ

USB interface

DP, DM, RSDP, RSDM, RREF, RPU

Remark Above, “5 V” refers to a 3.3 V buffer with 5-V tolerant circuit. Therefore, it is possible to have a 5-V

connection for an external bus, but the output level will be only up to 3.3 V, which is the V^DD33voltage.

15

Data Sheet S16302EJ3V0DS

µPD720130

3.2

Terminology

Terms Used in Absolute Maximum Ratings

Parameter

Symbol

Meaning

Power supply voltage

V^DD33, V^DD25Indicates voltage range within which damage or reduced reliability will not result when

power is applied to a V^DDpin.

Input voltage

Output voltage

Output current

V^I

V^O

I^O

Indicates voltage range within which damage or reduced reliability will not result when

power is applied to an input pin.

Indicates voltage range within which damage or reduced reliability will not result when

power is applied to an output pin.

Indicates absolute tolerance value for DC current to prevent damage or reduced

reliability when a current flows out of or into an output pin.

Operating temperature

Storage temperature

T^A

Indicates the ambient temperature range for normal logic operations.

T^stg

Indicates the element temperature range within which damage or reduced reliability

will not result while no voltage or current are applied to the device.

Terms Used in Recommended Operating Range

Parameter

Power supply voltage

High-level input voltage

Symbol

Meaning

V^DD33, V^DD25Indicates the voltage range for normal logic operations occur when V^SS= 0 V.

V^IH

Indicates the voltage, which is applied to the input pins of the device, is the voltage

indicates that the high level states for normal operation of the input buffer.

* If a voltage that is equal to or greater than the “Min.” value is applied, the input

voltage is guaranteed as high level voltage.

Low-level input voltage

V^IL

Indicates the voltage, which is applied to the input pins of the device, is the voltage

indicates that the low level states for normal operation of the input buffer.

* If a voltage that is equal to or lesser than the “Max.” value is applied, the input

voltage is guaranteed as low level voltage.

Hysteresys voltage

Input rise time

Input fall time

V^H

t^ri

Indicates the differential between the positive trigger voltage and the negative trigger

voltage.

Indicates allowable input rise time to input pins. Input rise time is transition time from

0.1 × V^DDto 0.9 × V^DD.

t^fi

Indicates allowable input fall time to input pins. Input fall time is transition time from

0.9 × V^DDto 0.1 × V^DD.

Terms Used in DC Characteristics

Parameter

Symbol

Meaning

Off-state output leakage

current

I^OZ

Indicates the current that flows from the power supply pins when the rated power

supply voltage is applied when a 3-state output has high impedance.

Output short circuit current

I^OS

Indicates the current that flows when the output pin is shorted (to GND pins) when

output is at high-level.

Input leakage current

I^I

Indicates the current that flows when the input voltage is supplied to the input pin.

Low-level output current

I^OL

Indicates the current that flows to the output pins when the rated low-level output

voltage is being applied.

High-level output current

I^OH

Indicates the current that flows from the output pins when the rated high-level output

voltage is being applied.

16

Data Sheet S16302EJ3V0DS

µPD720130

3.3

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol

V^DD33

Condition

3.3 V power supply rail

2.5 V power supply rail

Rating

Unit

V

−0.5 to +4.6

−0.5 to +3.6

−0.5 to +6.6

Power supply voltage

V^DD25

V^I

V

3.0 V ≤ V^DD33≤ 3.6 V

V^I< V^DD33+ 3.0 V

Input voltage, 5 V buffer

Input voltage, 3.3 V buffer

Input voltage, 2.5 V buffer

Output voltage, 5 V buffer

Output voltage, 3.3 V buffer

Output voltage, 2.5 V buffer

V

3.0 V ≤ V^DD33≤ 3.6 V

V^I< V^DD33+ 1.0 V

−0.5 to +4.6

−0.5 to +3.6

−0.5 to +6.6

−0.5 to +4.6

−0.5 to +3.6

V^I

V

2.3 V ≤ V^DD25≤ 2.7 V

V^I< V^DD25+ 0.9 V

V^I

3.0 V ≤ V^DD33≤ 3.6 V

V^O< V^DD33+ 3.0 V

V^O

3.0 V ≤ V^DD33≤ 3.6 V

V^O< V^DD33+ 1.0 V

2.3 V ≤ V^DD25≤ 2.7 V

V^O< V^DD25+ 0.9 V

Output current, 5 V buffer

Output current, 3.3 V buffer

I^O

I^OL= 6 mA

I^OL= 3 mA

20

mA

°C

10

0 to +70

−65 to +150

Operating ambient temperature

Storage temperature

T^A

°C

T^stg

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameters. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions

that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions indicated for DC characteristics and AC characteristics represent the

quality assurance range during normal operation.

Two Power Supply Rails Limitation

The µPD720130 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply

rail is stable at V^DDlevel. And, there will be difference between the time of V^DD25and V^DD33. The µPD720130

requires that V^DD25should be stable before V^DD33becomes stable. At this case, the system must ensure that the

absolute maximum ratings for V^I/ V^Oare not exceeded. System reset signaling should be asserted more than

specified time after both V^DD25and V^DD33are stable.

17

Data Sheet S16302EJ3V0DS

µPD720130

Recommended Operating Ranges

Parameter

Symbol

V^DD33

Condition

Min.

3.0

2.3

Typ.

3.3

2.5

Max.

3.6

Unit

V

Operating voltage

3.3 V for V^DD33pins

2.5 V for V^DD25pins

2.5 V for AV^DD25pins

V^DD25

V^IH

2.7

V

2.7

V

High-level input voltage

5.0 V high-level input voltage

3.3 V high-level input voltage

2.5 V high-level input voltage

Low-level input voltage

5.0 V low-level input voltage

3.3 V low-level input voltage

2.5 V low-level input voltage

Hysteresis voltage

2.0

1.7

5.5

V

V^DD33

V^DD25

V^IL

0

0.8

0.7

V

V^H

5 V hysteresis voltage

3.3 V hysteresis voltage

Input rise time

0.3

0.2

1.5

1.0

V

t^ri

Normal buffer

0

200

10

ns

Schmitt buffer

ms

Input fall time

t^fi

Normal buffer

0

200

10

ns

Schmitt buffer

ms

18

Data Sheet S16302EJ3V0DS

µPD720130

DC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70°C)

Control Pin Block

Parameter

Off-state output current

Output short circuit current

Low-level output current

5.0 V low-level output current

3.3 V low-level output current

High-level output current

5.0 V high-level output current

3.3 V high-level output current

Input leakage current

Symbol

I^OZ

Condition

Min.

Max.

10

Unit

µA

V^O= V^DD33,V^DD25or V^SS

Note

−250

I^OS

I^OL

mA

V^OL= 0.4 V

6.0

3.0

mA

I^OH

−2.0

−6.0

−3.0

V^OH= 2.4 V

mA

I^I

10

µA

3.3 V buffer

V^I= V^DDor V^SS

5.0 V buffer

Note The output short circuit time is one second or less and is only for one pin on the LSI.

19

Data Sheet S16302EJ3V0DS

µPD720130

USB Interface Block

Parameter

Symbol

R^S

Conditions

Min.

Max.

Unit

Ω

Serial Resistor between DP (DM) and

RSDP (RSDM)

38.61

39.39

Ω

Output pin impedance

Z^HSDRV

R^PU

Includes R^Sresistor

40.5

49.5

1.5 kΩ 5% consists of

resistance of transistor and

pull-up resistor

Bus pull-up resistor on upstream facing

port

1.485

1.515

Termination voltage for upstream facing

port pull-up

VTERM

3.0

3.6

V

Input Levels for Full-speed:

High-level input voltage (drive)

High-level input voltage (floating)

Low-level input voltage

V^IH

V^IHZ

V^IL

2.0

2.7

3.6

0.8

V

(D+) − (D−)

Differential input sensitivity

Differential common mode range

Output Levels for Full-speed:

High-level output voltage

Low-level output voltage

V^DI

0.2

0.8

V^CM

Includes V^DIrange

2.5

R^Lof 14.25 kΩ to V^SS

R^Lof 1.425 kΩ to 3.6 V

V^OH

2.8

0.0

0.8

1.3

3.6

0.3

V

V^OL

SE1

V^OSE1

V^CRS

Output signal crossover point voltage

Input Levels for High-speed:

2.0

High-speed squelch detection threshold

(differential signal)

V^HSSQ

VHSDSC

V^HSCM

100

525

−50

150

625

mV

High-speed disconnect detection threshold

(differential signal)

+500

High-speed data signaling common mode

voltage range

High-speed differential input signaling level

Output Levels for High-speed:

High-speed idle state

See Figure 3-4.

−10.0

+10.0

V^HSOI

mV

High-speed data signaling high

High-speed data signaling low

Chirp J level (differential signal)

Chirp K level (differential signal)

V^HSOH

V^HSOL

V^CHIRPJ

V^CHIRPK

360

440

−10.0

+10.0

700

1100

−900

−500

20

Data Sheet S16302EJ3V0DS

µPD720130

Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed

Differential Input Voltage Range

Differential Output

Crossover

Voltage Range

−1.0

0.0

0.2 0.4

0.6 0.8

1.0 1.2 1.4

1.6 1.8 2.0 2.2

2.4 2.6

2.8

3.0

3.2

4.6

Input Voltage Range (V)

Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver

V

DD−3.3

V

DD−2.8

V

DD−2.3

V

DD−1.8

V

DD−1.3

V

DD−0.8

VDD−0.3 VDD

0

−20

−40

Min.

Max.

−60

−80

V

OUT (V)

Figure 3-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver

80

Max.

Min.

60

40

20

0

0.5

1

1.5

2.5

3

2

V

OUT (V)

21

Data Sheet S16302EJ3V0DS

µPD720130

Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM

Level 1

+400 mV

Differential

Point 3

Point 1

Point 4

Point 2

0 V

Differential

Point 5

Point 6

−400 mV

Differential

Level 2

0%

Unit Interval

100%

Figure 3-5. Receiver Measurement Fixtures

Test Supply Voltage

+

15.8 Ω

50 Ω

To 50 Ω Inputs of a

USB

Connector

Nearest

Device

Vbus

D+

D-

Coax

High Speed Differential

Oscilloscope, or 50 Ω

Outputs of a High Speed

Differential Data Generator

−

15.8 Ω

50 Ω

Coax

Gnd

143 Ω

Pin Capacitance

Parameter

Symbol

C^IN

Condition

V^DD= 0 V, T^A= 25°C

f^C= 1 MHz

Min.

4

Max.

Unit

pF

Input capacitance

Output capacitance

I/O capacitance

6

C^OUT

C^IO

4

pF

Unmeasured pins returned to 0 V

4

pF

22

Data Sheet S16302EJ3V0DS

µPD720130

Power Consumption

(1) The power consumption when device works as bus-powered mode

Symbol

Condition

Max.

V^DD33

Unit

V^DD25

AV^DD25

P^ENUM-BUS

The power consumption under unconfigured stage

High-speed operating

Full-speed operating

57

23

3

4

10

mA

P^W-BUS

The power consumption when device works

High-speed operating

Full-speed operating

110

113

22

13

10

mA

µA

P^W_SPD-BUS

The power consumption under suspend state

10

235

5

(2) The power consumption when device works as self-powered mode

Symbol

Condition

Max.

V^DD33

Unit

V^DD25

AV^DD25

P^ENUM-SELF

The power consumption under unconfigured stage

High-speed operating

Full-speed operating

85

60

5

10

mA

P^W-SELF

The power consumption when device works

High-speed operating

Full-speed operating

120

113

25

13

10

mA

P^W_SPD-SELF

P^W_UNP

The power consumption under suspend state

The power consumption under unplug state

The power consumption under combo mode

The device is releasing the IDE bus.

50

87

90

5

3

5

mA

10

P^W_COM

23

Data Sheet S16302EJ3V0DS

µPD720130

AC Characteristics (VDD33 = 3.0 to 3.6 V, VDD25 = 2.3 to 2.7 V, TA = 0 to +70°C)

System Clock Ratings

Parameter

Symbol

f^CLK

Condition

Min.

Typ.

30

Max.

Unit

−500

+500

Clock frequency

X’tal

MHz

ppm

−500

+500

Oscillator block

30

50

MHz

%

ppm

Clock duty cycle

t^DUTY

45

55

Remarks 1. Recommended accuracy of clock frequency is 100 ppm.

2. Required accuracy of X’tal or Oscillator block is including initial frequency accuracy, the spread of

X’tal capacitor loading, supply voltage, temperature, and aging, etc.

System Reset signaling

Parameter

Symbol

t^rst

Conditions

Min.

2

Max.

Unit

µs

Reset active time

USB Interface Block

(1/2)

Unit

Parameter

Full-speed Source Electrical Characteristics

Symbol

Conditions

Min.

Max.

Rise time (10% - 90%)

t^FR

C^L= 50 pF,

R^S= 36 Ω

4

20

ns

Fall time (90% - 10%)

t^FF

C^L= 50 pF,

R^S= 36 Ω

Differential rise and fall time matching

t^FRFM

(t^FR/t^FF)

90

111.11

%

Full-speed data rate for device which are

high-speed capable

t^FDRATHS

Average bit rate

11.9940

12.0060

Mbps

Frame interval

t^FRAME

t^RFI

0.9995

1.0005

42

ms

ns

Consecutive frame interval jitter

No clock adjustment

Source jitter total (including frequency

tolerance):

−3.5

−4.0

+3.5

+4.0

To next transition

t^DJ1

t^DJ2

ns

For paired transitions

−2

+5

Source jitter for differential transition to

SE0 transition

t^FDEOP

ns

Receiver jitter:

−18.5

−9

+18.5

+9

To next transition

For paired transitions

t^JR1

t^JR2

ns

Source SE0 interval of EOP

Receiver SE0 interval of EOP

t^FEOPT

t^FEOPR

t^FST

160

82

175

ns

Width of SE0 interval during differential

transition

14

24

Data Sheet S16302EJ3V0DS

µPD720130

(2/2)

Parameter

Symbol

Conditions

Min.

Max.

Unit

High-speed Source Electrical Characteristics

Rise time (10% - 90%)

Fall time (90% - 10%)

t^HSR

500

ps

t^HSF

Driver waveform

See Figure 3-6.

t^HSDRAT

High-speed data rate

479.760

480.240

Mbps

µs

Microframe interval

t^HSFRAM

124.9375

125.0625

Consecutive microframe interval difference

t^HSRFI

4 high-

speed

Bit

times

Data source jitter

See Figure 3-6.

See Figure 3-4.

Receiver jitter tolerance

Device Event Timings

Time from internal power good to device

pulling D+ beyond V^IHZ(min.) (signaling

attached)

t^SIGATT

100

ms

Debounce interval provided by USB

system software after attach

tATTDB

Inter-packet delay for full-speed

t^IPD

2

Bit

times

Inter-packet delay for device response

w/detachable cable for full-speed

tRSPIPD1

6.5

Bit

times

µs

High-speed detection start time from

suspend

t^SCA

2.5

µs

ms

µs

Sample time for suspend vs reset

Time to detect bus suspend state

Power down under suspend

t^CSR

t^SPD

t^SUS

t^RHS

100

875

3.125

10

3.000

Reversion time from suspend to high-

speed

1.333

Drive Chirp K width

t^CKO

t^FCA

t^SSC

t^FSC

t^CSI

1

ms

µs

Finish Chirp K assertion

7

Start sequencing Chirp K-J-K-J-K-J

Finish sequencing Chirp K-J

Detect sequencing Chirp K-J width

Sample time for sequencing Chirp

Reversion time to high-speed

High-speed detection start time

Reset completed time

100

−100

−500

2.5

1

µs

t^SCS

t^RHA

t^HDS

t^DRS

2.5

500

ms

µs

2.5

10

3000

ms

25

Data Sheet S16302EJ3V0DS

µPD720130

IDE Interface Block

PIO mode

Parameter

Symbol

t⁰

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Unit

ns

Cycle time (min.)

600

70

383

50

240

30

180

30

80

70

30

10

20

5

120

25

70

25

20

10

20

5

Address setup time (min.)

t¹

t²

16 bits DIOR/DIOW pulse width (min.)

8 bits DIOR/DIOW pulse width (min.)

DIOR/DIOW recovery time (min.)

DIOW data setup time (min.)

DIOW data hold time (min.)

DIOR data setup time (min.)

DIOR data hold time (min.)

165

290

−

125

290

−

100

290

−

t²ⁱ

t³

60

30

50

5

45

20

35

5

30

15

20

5

t⁴

t⁵

t⁶

DIOR 3-state delay time (max.)

Address hold time (min.)

t^6Z

t⁹

30

20

0

30

15

0

30

10

0

30

10

0

30

10

0

IORDY read data valid time (min.) ^Note

IORDY setup time (min.) ^Note

IORDY pulse width (max.) ^Note

IORDY Inactive to Hi-Z time (max.) ^Note

t^RD

t^A

t^B

t^C

35

1250

5

35

1250

5

35

1250

5

35

1250

5

35

1250

5

Note IORDY is an option in mode 0 - 2. IORDY is essential in modes 3 and 4.

Multi Word DMA mode

Parameter

Symbol

t⁰

Mode 0

480

215

150

5

Mode 1

150

80

60

5

Mode 2

120

70

50

5

Unit

ns

Cycle time (min.)

DIOR/DIOW pulse width (min.)

DIOR data access time (max.)

DIOR data hold time (min.)

DIOR data setup time (min.)

DIOW data setup time (min.)

DIOW data hold time (min.)

DMACK setup time (min.)

t^D

t^E

t^F

t^Gr

t^Gw

t^H

100

20

30

15

0

20

10

0

t^I

0

DMACK hold time (min.)

t^J

20

5

DIOR negate pulse width (min.)

DIOW negate pulse width (min.)

DIOR-DMARQ delay time (max.)

DIOW-DMARQ delay time (max.)

DMACK 3-state delay time (max.)

CS setup time (min.)

t^Kr

t^Kw

t^Lr

t^Lw

t^Z

50

40

25

30

10

25

35

25

10

215

120

40

20

t^M

t^N

50

CS hold time (min.)

15

26

Data Sheet S16302EJ3V0DS

µPD720130

Ultra DMA mode

Parameter

Symbol

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Unit

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Average cycle time for 2 cycles

Minimum cycle time for 2 cycles

Cycle time for 1 cycle

t^2CYC

t^CYC

t^DS

240

235

114

15

5

-

160

156

75

10

5

-

120

117

55

7

-

90

86

39

7

-

60

57

25

5

-

ns

-

Data setup time on receive side

Data hold time on receive side

Data setup time on transmit side

Data hold time on transmit side

First STROBE time

-

t^DH

-

5

-

5

-

5

-

t^DVS

t^DVH

t^FS

70

6

-

48

6

-

34

6

-

20

6

-

6

-

6

-

0

230

0

200

0

170

0

130

0

120

Interlock time with limitation

Minimum interlock time

t^LI

0

150

0

150

0

150

0

100

0

100

t^MLI

t^UI

20

0

-

20

0

-

20

0

-

20

0

-

20

0

-

Interlock time without limitation

Output release time

t^AZ

-

10

-

10

-

10

-

10

-

10

-

Output delay time

t^ZAH

t^ZAD

20

0

20

0

20

0

20

0

20

0

Output stabilization time

(from release)

-

Envelope time

t^ENV

t^SR

t^RFS

t^RP

20

-

70

50

75

-

20

-

70

30

60

-

20

-

70

20

50

-

20

-

55

NA

60

-

20

-

55

NA

60

-

ns

STROBE DMARDY delay time

Last STROBE time

Pause time

-

160

-

125

-

100

-

100

-

100

-

IORDY pull-up time

IORDY wait time

t^IORYZ

t^ZIORY

t^ACK

t^SS

20

-

20

-

20

-

20

-

20

-

0

DMACK setup/hold time

STROBE STOP time

20

50

-

20

50

-

20

50

-

20

50

-

20

50

-

27

Data Sheet S16302EJ3V0DS

µPD720130

Serial ROM interface Block

Parameter

Symbol

t^SCL

Conditions

Min.

Max.

100

Unit

KHz

µs

Clock frequency

Clock pulse width low

Clock pulse width high

Clock Low to data valid

Start hold time

t^LOW

4.7

4.0

100

4.0

4.7

0

µs

t^HIGH

t^AA

4500

ns

µs

t^HD.STA

t^SU.STA

t^HD.DAT

t^SU.DAT

t^DH

µs

Start setup time

Data in hold time

Data in setup time

Data out hold time

Stop setup time

ns

µs

0.2

50

ns

µs

t^SU.STO

t^BUF

4.7

10

Time the bus must be free before a new

transmission can start

Write cycle time

t^WR

10

ms

28

Data Sheet S16302EJ3V0DS

µPD720130

Figure 3-6. Transmit Waveform for Transceiver at DP/DM

Level 1

+400 mV

Differential

Point 3

Point 4

0 V

Differential

Point 1

Point 2

Point 5

Point 6

−400 mV

Differential

Level 2

Unit Interval

0%

100%

Figure 3-7. Transmitter Measurement Fixtures

Test Supply Voltage

+

15.8 Ω

50 Ω

To 50 Ω Inputs of a

High Speed Differential

Oscilloscope, or 50 Ω

Outputs of a High Speed

Differential Data Generator

−

USB

Connector

Nearest

Device

Vbus

D+

D-

Coax

15.8 Ω

50 Ω

Coax

Gnd

143 Ω

29

Data Sheet S16302EJ3V0DS

µPD720130

Timing Diagram

System reset timing

t

rst

RESETB

Remark After RESET is negated, this chip read the serial ROM first. Do not reset while the serial ROM is read. The

serial ROM is completed to read below time, after RESET is negated.

5 + 0.1197 × bytes (serial ROM size) + 0.5678 (ms)

Example In the case of 512 bytes: 66.855 ms, in the case of 8 Kbytes: 986.15 ms

USB power-on and connection events

Hub port

power OK

Reset recovery

time

Attatch detected

Hub port

power-on

≥ 4.01 V

USB system software

reads device speed

V

BUS

IH(min)

IH

V

D+

or

D−

t

SIGATT

10 ms

t

ATTDB

USB differential data jitter for full-speed

t

PERIOD

Crossover

Points

Differential

Data Lines

Consecutive

Transitions

N × t^PERIOD+ tDJ1

Paired

Transitions

N × t^PERIOD+ tDJ2

30

Data Sheet S16302EJ3V0DS

µPD720130

USB differential-to-EOP transition skew and EOP width for full-speed

t

PERIOD

Crossover

Point Extended

Crossover

Point

Differential

Data Lines

Diff. Data-to-

SE0 Skew

N × t^PERIOD+ tFDEOP

Source EOP Width: t^FEOPT

Receiver EOP Width: tFEOPR

USB receiver jitter tolerance for full-speed

t

PERIOD

Differential

Data Lines

tJR

t

JR1

tJR2

Consecutive

Transitions

N × t^PERIOD+ tJR1

Paired

Transitions

N × t^PERIOD+ tJR2

USB connection sequence on full-speed system bus

Pull-up is active.

Reversion to full-speed mode

Chirp K device out

FSJ

USB bus

tHDS

tSCA

tCKO

tSCS

tFCA

tDRS

T0

USB connection sequence on high-speed system bus

Pull-up is active.

Reversion to high-speed mode

Reset Complete

Chirp state from host/hub

Chirp K device out

K

J

K

J

K

J

K

J

FSJ

USB bus

t

SCA

tHDS

tCKO

tRHA

tSSC tCSI

tFSC

tFCA

tSCS

T⁰

31

Data Sheet S16302EJ3V0DS

µPD720130

USB reset sequence from suspend state on full-speed system bus

Pull-up is active.

Chirp K device out

FSJ

USB bus

tSCA

tCKO

tDRS

tSCS

tFCA

T⁰

USB reset sequence from suspend state on high-speed system bus

Chrip state from host/hub

Reversion to high-speed mode

Reset Complete

Pull-up is active.

FSJ

Chirp K device out

K

J

K

J

K

J

K

J

USB bus

tSCA

t

CKO

t

RHA

t

SSC

t

CSI

t

FSC

t

FCA

t

SCS

T

0

USB suspend and resume on full-speed system bus

FS EOP

USB bus

FSJ

FSK

FSJ

tSPD

Note time required to relock PLL

and stabilize oscillator.

Power will be down

tSUS

USB suspend and resume on high-speed system bus

Reversion to full-speed mode

High-speed packet

Reversion to high-speed mode

High-speed packet

FSJ

FSK

USB bus

t

RHS

t

SPD

t

tCSR

t

SUS

Note time required to relock PLL

and stabilize oscillator.

Power will be down

T0

32

Data Sheet S16302EJ3V0DS

µPD720130

IDE PIO mode timing

IDECS1B, IDECS0B

H

L

IDEEA2-IDEEA0

t

1

t

9

t

0

IDEIORB

IDEIOWB

H

L

t

2i

t

2

t

3

t

4

IDED15-IDED0

(WRITE)

H

L

t

6

6Z

t

5

t

IDED15-IDED0

(READ)

H

L

t

A

t

C

t

RD

IDEIORDY

H

L

t

B

IDE multi word DMA mode timing

H

IDECS1B, IDECS0B

L

H

IDEDRQ

L

t

M

t

N

t

Lr/tLw

IDEDAKB

H

L

t

0

t

I

t

D

t

Kr/tKw

t

J

IDEIORB

IDEIOWB

H

L

t

E

t

Gr

t

F

t

Z

IDED15-IDED0

(READ)

H

L

t

Gw

t

H

IDED15-IDED0

(WRITE)

H

L

IDE ultra DMA mode data-in timing

H

IDEDRQ

L

tUI

tSS

H

IDEDAKB

L

tLI tLI

tMLI

tFS

tZAD

tACK

tENV

tACK

IDEIOWB

(STOP)

H

L

tFS

tZAD

tACK

tLI

IDEIORDY

(HDMARDY)

H

L

tZIORY

t

2CYC

tIORYZ

tDVH

IDEIORB

(DSTROBE)

H

L

tDVS

tCYC

tDVH

tZAH

t

CYC

DVS

t

AZ

H

L

tAZ

IDED15-IDED0

IDECS1B, IDECS0B

IDEA2-IDEA0

Data

CRC

t

ACK

tACK

H

L

t

ACK

H

L

33

Data Sheet S16302EJ3V0DS

µPD720130

IDE ultra DMA mode data-in stop timing

H

IDEDRQ

L

H

IDEDAKB

L

t

RP

IDEIOWB

(STOP)

H

L

t

SR

IDEIORB

(HDMARDY)

H

L

t

RFS

IDEIORDY

(DSTROBE)

H

L

H

L

IDED15-IDED0

IDE ultra DMA mode data-in end timing

H

IDEDRQ

L

t

LI

t

MLI

H

IDEDAKB

L

t

ACK

IDEIOWB

(STOP)

H

L

t

ZAH

t

RP

t

AZ

IDEIORB

(HDMARDY)

H

L

t

IORYZ

t

RPS

t

LI

t

MLI

IDEIORDY

(DSTROBE)

H

L

t

DVS DVH

t

H

L

IDED15-IDED0

CRC

t

ACK

IDECS1B, IDECS0B

IDEA2-IDEA0

H

L

IDE ultra DMA mode data-out timing

H

IDEDRQ

L

t

RP

t

UI

H

IDEDAKB

L

_ACKtENV

LI

t

ACK

t

MLI

t

UI

t

LI

IDEIOWB

(STOP)

H

L

t

IORYZ

t

RFS

IDEIORDY

(DDMARDY)

t

ZIORY

ACK

H

L

t

LI

t

ACK

t

2CYC

t

MLI

IDEIORB

(HSTROBE)

H

L

t

DVS

t

t^CD^YV^CH

t

DVS

t

CYC

t

DVH

H

L

Data

CRC

IDED15-IDED0

IDECS1B, IDECS0B

IDEA2-IDEA0

t

ACK

t

ACK

H

L

t

ACK

H

L

34

Data Sheet S16302EJ3V0DS

µPD720130

IDE ultra DMA mode data-out stop timing

H

IDEDRQ

L

t

RP

H

IDEDAKB

L

IDEIOWB

(STOP)

H

L

t

SR

IDEIORB

(HDMARDY)

H

L

t

RFS

IDEIORDY

(DSTROBE)

H

L

H

L

IDED15-IDED0

IDE ultra DMA mode data-out end timing

H

IDEDRQ

L

t

LI

t

MLI

H

IDEDAKB

L

t

LI

t

ACK

IDEIOWB

(STOP)

H

L

t

IORYZ

t

SS

tLI

IDEIORB

(HDMARDY)

H

L

t

ACK

IDEIORDY

(DSTROBE)

H

L

t

DVS DVH

t

H

L

CRC

IDED15-IDED0

t

ACK

IDECS1B, IDECS0B

IDEA2-IDEA0

H

L

IDE ultra DMA mode data skew timing

t2CYC

IDEIORB

(Output side)

H

L

tCYC

tDVH

tCYC

tDVS

H

L

IDED15-IDED0

(Output side)

Data

↓

Delay, skew, etc., by cable

IDEIORDY

(Input side)

H

L

tDS

tDH

IDED15-IDED0

(Input side)

H

L

Output side

Input side

xSTROBE

DD0

:

DD15

35

Data Sheet S16302EJ3V0DS

µPD720130

Serial ROM access timing

tHIGH

tLOW

SCL

tSU.STA

tHD.STA

tHD.DAT

tSU.DAT

tSU.STO

SDA

(Output)

tAA

tDH

tBUF

SDA

(Input)

Serial ROM write cycle timing

PIO1

8th bit

ACK

PIO0

Word n

t

WR

Stop

condition

Start

condition

36

Data Sheet S16302EJ3V0DS

µPD720130

4. PACKAGE DRAWING

• µPD720130GC-9EU

100-PIN PLASTIC TQFP (FINE PITCH) (14x14)

A

B

75

76

51

50

detail of lead end

S

P

C

D

T

R

L

100

1

26

25

U

Q

F

J

G

M

H

I

K

S

N

S

M

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

G

H

I

16.0 0.2

14.0 0.2

16.0 0.2

1.0

0.22 0.05

0.08

J

0.5 (T.P.)

1.0 0.2

0.5

K

L

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.0

0.1 0.05

+4°

3°

R

−3°

S

T

U

1.1 0.1

0.25

0.6 0.15

P100GC-50-9EU

37

Data Sheet S16302EJ3V0DS

µPD720130

• µPD720130GC-9EU-SIN

100-PIN PLASTIC TQFP (FINE PITCH) (14x14)

A

B

75

76

51

50

detail of lead end

S

C

D

Q

R

100

1

26

25

F

G

J

M

H

I

K

P

N

S

L

M

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

16.0 0.2

14.0 0.2

16.0 0.2

1.0

G

1.0

+0.05

0.22

H

−0.04

I

J

0.10

0.5 (T.P.)

1.0 0.2

0.5 0.2

K

L

+0.055

M

0.145

−0.045

N

P

Q

0.10

1.0 0.1

0.1 0.05

+7°

3°

R

S

−3°

1.27 MAX.

S100GC-50-9EU-2

38

Data Sheet S16302EJ3V0DS

µPD720130

5. RECOMMENDED SOLDERING CONDITIONS

The µPD720130 should be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales

representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

µPD720130GC-9EU: 100-pin plastic TQFP (Fine pitch) (14 × 14)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less

IR35-103-2

Exposure limit: 3 days^Note(after that, prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time: 3 seconds or less (per pin row)

–

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

µPD720130GC-9EU-SIN: 100-pin plastic TQFP (Fine pitch) (14 × 14)

Soldering Method

Infrared reflow

Soldering Conditions

Symbol

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less

IR35-103-2

Exposure limit: 3 days^Note(after that, prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time: 3 seconds or less (per pin row)

–

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

39

Data Sheet S16302EJ3V0DS

µPD720130

[MEMO]

40

Data Sheet S16302EJ3V0DS

µPD720130

[MEMO]

41

Data Sheet S16302EJ3V0DS

µPD720130

[MEMO]

42

Data Sheet S16302EJ3V0DS

µPD720130

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

43

Data Sheet S16302EJ3V0DS

µPD720130

EEPROM is a trademark of NEC Electronics Corporation.

USB logo is a trademark of USB Implementers Forum, Inc.

•

The information in this document is current as of June, 2003. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or

data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all

products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD720130
厂家：	NEC
描述：	USB2.0 to IDE Bridge USB2.0转IDE桥接
文件：	总44页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD720130 [NEC]

相关型号：

UPD720130GC-9EU

UPD720130GC-9EU

UPD720130GC-9EU-A

UPD720130GC-9EU-A

UPD720130GC-9EU-SIN

UPD720130GC-9EU-SIN

UPD720130GC-9EU-SIN-A

UPD720133

UPD720133GB-YEU

UPD720133GB-YEU-A

UPD720133GB-YEU-A

UPD720133GB-YEU-Y