UPD72107L [NEC]

LAP-B CONTROLLER(Link Access Procedure Balanced mode); LAP -B控制器（链路访问过程平衡模式）


型号：	UPD72107L
厂家：	NEC
描述：	LAP-B CONTROLLER(Link Access Procedure Balanced mode) LAP -B控制器（链路访问过程平衡模式）微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
文件：	总32页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD72107

LAP-B CONTROLLER

Link Access Procedure Balanced mode

The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single

chip.

FEATURES

• Memory-based interface

Memory-based command

Memory-based status

• Complied with ITU-T recommended X.25 (LAP-B84

edition)

HDLC frame control

Memory-based transmit/receive data

• MAX.4 Mbps serial transfer rate

• NRZ, NRZI coding

Sequence control

Flow control

• ITU-T recommended X.75 supported

• TTC standard JT-T90 supported

• Optional functions

Option frame

Global address frame

Error check deletion frame

• Powerful test functions

Data loopback function

Loopback test link function

Frame trace function

• Abundant statistical information

• Detailed mode setting function

• Modem control function

• On-chip DMAC (Direct Memory Access Controller)

24-bit address

Byte/word transfer enabled (switch with external pin)

ORDERING INFORMATION

Part Number

µPD72107CW

µPD72107GC-3B9

µPD72107L

Package

64-pin plastic shrink DIP (750 mils)

80-pin plastic QFP (14 x 14 mm)

68-pin plastic QFJ (950 x 950 mils)

The information in this document is subject to change without notice.

Document No. S12962EJ5V0DS00 (5th edition)

Date Published October 1998 N CP(K)

Printed in Japan

1998

µPD72107

BLOCK DIAGRAM

D0-D7

A16D8

TxC

TxD

RTS

CTS

-A23D15

A0-A15

IORD

IOWR

MRD

Internal controller

TxFIFO

Transmitter

MWR

UBE

Bus

interface

ASTB

AEN

READY

HLDRQ

HLDAK

CRQ

Internal bus

INT

CLRINT

B/W

Receiver

RxFIFO

DMAC

RxC

RxD

VCC

GND

RESET

CLK

Name

Function

Bus interface

An interface between the µPD72107 and external memory or external host processor

Internal controller

Manages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block

DMAC

Controls the transfer of data on the external memory to the internal controller or transmitter block,

and controls the writing of data in the internal controller or receiver block to the external memory

(Direct Memory

Access Controller)

TxFIFO

A 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block

A 32-byte buffer for when receive data is sent from the receiver block to the DMAC

Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data

Receives HDLC frame and writes internal data to RxFIFO

RxFIFO

Transmitter

Receiver

Internal bus

An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,

and bus interface block

µPD72107

PIN CONFIGURATION (Top View)

64-pin plastic shrink DIP (750 mils)

µPD72107CW

RxC

RxD

TxC

TxD

CTS

RTS

CRQ

AEN

ASTB

READY

HLDAK

HLDRQ

CLRINT

INT

RESET

B/W

UBE

MWR

MRD

GND

IOWR

IORD

CLK

GND

V^CC

A10

A11

A12

A13

A14

A15

A16D8

A17D9

A23D15

A22D14

A21D13

A20D12

A19D11

A18D10

µPD72107

80-pin plastic QFP (14 × 14 mm)

µPD72107GC-3B9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

HLDRQ

HLDAK

READY

ASTB

AEN

A23D15

A22D14

A21D13

A20D12

A19D11

A18D10

CRQ

RTS

A17D9

A16D8

A15

RxC

RxD

A14

TxC

TxD

CTS

A13

A12

A11

A10

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

µPD72107

68-pin plastic QFJ (950 × 950 mils)

µPD72107L

68 67 66 65 64 63 62 61

RESET

CLRINT

INT

B/W

UBE

MWR

MRD

GND

IOWR

IORD

CLK

GND

V^CC

VCC

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

µPD72107

1. PINS

1.1 Pin Functions

SDIP

QFP

QFJ

Active

Level

–

Pin Name

I/O

–

Function

Pin No. Pin No. Pin No.

V^CC

+5 V power supply

Ground (0 V)

GND

–

Note that there is more than one ground pin.

CLK

–

System clock input

(Clock)

RESET

(Reset)

Input clock of 1 MHz to 8.2 MHz.

Initializes the internal µPD72107. Active width of

more than 7 CLK clock cycles is required (clock

input is required).

After reset, this pin becomes a bus slave.

Pull up to high level when using in normal operation.

–

(Pull Up)

When bus master

(Chip Select)

Set to disable.

When bus slave

Read/write operation from the host processor at low

level is enabled.

MRD

When bus master

(Memory Read)

3-state

Reads the data of the external memory at low level.

When bus slave

High impedance

MWR

When bus master

(Memory Write)

3-state

Writes the data to the external memory at low level.

When bus slave

High impedance

IORD

This pin is used when the external host processor

reads the contents of the internal registers of the

µPD72107.

(I/O Read)

IOWR

This pin is used when the external host processor

writes the data to the internal registers of the

µPD72107.

(I/O Write)

ASTB

This pin is used to latch the address output from

the µPD72107 externally.

(Address Strobe)

µPD72107

SDIP

QFP

QFJ

Active

Level

–

Pin Name

I/O

–

Function

Pin No. Pin No. Pin No.

1, 7,

11, 15,

20, 21,

29, 40,

41, 50,

51, 55,

61, 69,

Use this pin open.

(No Connection)

–

Do not connect anything to this pin.

(Internally

Connected)

UBE

I/O

L/H

When bus master (output)

(Upper Byte

Enable)

3-state

The signal output from this pin changes according

to the input value of the B/W pin.

• Byte transfer mode (B/W = 0)

UBE is always high impedance.

• Word transfer mode (B/W = 1)

Indicates that valid data is either in pins D0 to D7

or pins A16D8 to A23D15 (or both).

UBE

D0 to D7 A16D8 to A23D15

When bus slave (input)

UBE pin becomes input, and indicates that valid

data is either in pins D0 to D7 or pins A16D8 to

A23D15.

UBE

D0 to D7 A16D8 to A23D15

µPD72107

SDIP

Pin No. Pin No. Pin No.

11 24 12

QFP

QFJ

Active

Level

L/H

Pin Name

I/O

Function

B/W

Specifies the data bus that accesses the external

memory when bus master.

(Byte/Word)

B/W = 0

B/W = 1

Byte units (8 bits)

Word units (16 bits)

After power-on, fix the status of the B/W pin.

In the case of word access, the lower data bus is the

contents data of even addresses.

READY

(Ready)

An input signal that is used to extend the MRD and

MWR signal widths output by the µPD72107 to

adapt to low-speed memory. When the READY

signal is low level, the MRD and MWR signals

maintain active low. Do not change the READY

signal at any time other than the specified setup/

hold time.

HLDRQ

–

A hold request signal to the external host processor.

WhenaDMAoperationisperformedintheµPD72107,

this signal is activated to switch from bus slave to

bus master.

(Hold Request)

HLDAK

A hold acknowledge signal from the external host

processor. When the µPD72107 detects that this

signal is active, the bus slave switches to bus

master, and a DMA operation is started.

When bus master, this signal enables the latched

higher addresses and outputs them to system ad-

dress bus. This signal is also used for disabling

other system bus drivers.

(Hold Acknowledge)

AEN

(Address Enable)

A0, A1

15, 16

30, 31

17, 18

I/O

Bidirectional 3-state address lines.

3-state

When bus master (output)

Indicatethelower2-bitaddressesofmemoryaccess.

When bus slave (input)

Input addresses when the external host processor

I/O accesses the µPD72107.

A2 to A15

17 to 30 32 to 47 19 to 32

–

When bus master

(except

40, 41)

3-state

Output bit 2 to bit 15 of memory access addresses.

When bus slave

Become high impedance.

µPD72107

SDIP

Pin No. Pin No. Pin No.

A16D8 to A23D15 31 to 38 48 to 58 33 to 41

QFP

QFJ

Active

Level

–

Pin Name

I/O

Function

Bidirectional 3-state address/data buses. Multiplex

pins of the higher 16 bits to 23 bits of addresses

and the higher 8 bits to 15 bits of data.

Bidirectional 3-state data buses.

(except 50,(except 35) 3-state

51, 55)

D0 to D7

39 to 46 59 to 67 42 to 49

(except 61)

I/O

–

3-state

When bus master

Whenwritingtoexternalmemory, thesepinsbecome

input if reading at output.

When bus slave

Usually, these pins become high impedance. When

theexternalhostprocessorreadsI/OoftheµPD72107,

the internal register data is output.

CRQ

A signal requesting command execution to the

µPD72107 by the external host processor. The

µPD72107 starts fetching commands from on the

external memory at the rising edge of this signal.

An interrupt signal from the µPD72107 to the

external host processor.

(Command

Request)

INT

(Interrupt)

CLRINT

A signal inactivating the INT signal being output by

theµPD72107. TheµPD72107generatestheCLRINT

signal in the LSI internal circuit at the rising edge of

this signal, and forcibly makes the INT output signal

low.

(Clear Interrupt)

CTS

–

A general-purpose input pin.

(Clear To Send)

TheµPD72107reportsthe“CTSpinchangedetection

status” to the external host processor when the

input level of this pin is changed in the general-

purpose input/output pin support (setting RSSL to

1 by the “system initialization command”). The

change of input level is recognized only when the

same level is sampled twice in succession after

sampling in 8-ms cycles and detecting the change.

Moreover, when the external host processor issues

a “general-purpose input/output pin read command”

to the µPD72107, the µPD72107 reports the pin

information of this pin to the external host processor

bya“general-purposeinput/outputpinreadresponse

status”.

The change can be detected even in the clock input

stop status of TxC and RxC.

µPD72107

SDIP

Pin No. Pin No. Pin No.

64 10 68

QFP

QFJ

Active

Level

–

Pin Name

RTS

I/O

Function

A general-purpose output pin.

(Request To Send)

The output value of this pin can be changed by

issuingan“RTSpinwritecommand”fromtheexternal

host processor to the µPD72107. Moreover, when

theexternalhostprocessorissuesa“general-purpose

input/output pin read command” to the µPD72107,

the µPD72107 reports the pin information of this pin

to the external host processor by a “general-purpose

input/output pin read response status”.

–

A general-purpose input pin.

(Carrier Detect)

The µPD72107 reports the “CD pin change detection

status” to the external host processor when the

input level of this pin is changed in the general-

purpose input/output pin support (setting RSSL to

1 by the “system initialization command”). The

change of input level is recognized only when the

same level is sampled twice in succession after

sampling in 8-ms cycles and detecting the change.

Moreover, when the external host processor issues

a “general-purpose input/output pin read command”

to the µPD72107, the µPD72107 reports the pin

information of this pin to the external host processor

bya“general-purposeinput/outputpinreadresponse

status”.

The change can be detected even in the clock input

stop status of TxC and RxC.

TxD

–

A serial transmit data output pin.

(Transmit Data)

TxC

I/O

When CLK is set to 01 or 10 by “operation mode

setting LCW” (output)

(Transmit Clock)

3-state

Outputs a clock that divides by 16 the input signal

of the RxC pin or CLK pin made by the µPD72107.

Caution TxC becomes input because CLK = 00

is the default after reset. It becomes

output after setting CLK to 01 or 10 by

“operation mode setting LCW”.

When CLK is set to 00 by “operation mode setting

LCW” (input)

Inputs transmit clock externally.

Remark LCW: abbreviation for Link Command Word

µPD72107

SDIP

QFP

QFJ

Active

Level

–

Pin Name

RxD

I/O

Function

Pin No. Pin No. Pin No.

A serial receive data input pin.

(Receive Data)

RxC

–

When CLK is set to 01 or 10 by “operation mode

setting LCW”

(Receive Clock)

Sixteen times the clock input of the transmit/receive

clock for the on-chip DPLL of the µPD72107

When CLK is set to 00 by “operation mode setting

LCW”

One time the clock input of the receive clock

Remark LCW: abbreviation for Link Command Word

1.2 Pin Status after Reset of µPD72107

The status of the output pins and input/output pins after reset in the µPD72107 is as shown in Table 1-1.

Table 1-1. Pin Status after Reset

Pin Number

During Reset

Pin Name

I/O

64-pin SDIP

80-pin QFP

68-pin QFJ

Note

TxC

TxD

I/O

High impedance

Note

15, 16

17 to 30

30, 31

17, 18

19 to 32

A0, A1

I/O

High impedance

Note

32 to 47

A2 to A15

(except 40, 41)

31 to 38

39 to 46

48 to 58

33 to 41

A16D8 to A23D15

D0 to D7

I/O

High impedance

(except 50, 51, 55)

(except 35)

Note

59 to 67

42 to 49

I/O

(except 61)

Note

MRD

MWR

UBE

High impedance

I/O

High impedance

INT

HLDRQ

ASTB

AEN

RTS

Note 3-state

Remarks 1. The status after reset is released is the same as the status during reset.

2. Input low level to the RESET pin for more than 7 clocks of the system clock.

µPD72107

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = +25°C)

Parameter

Power supply voltage

Input voltage

Symbol

VDD

Conditions

Ratings

–0.5 to +7.0

Unit

–0.5 to VDD + 0.3

–40 to +85

Output voltage

Operating ambient temperature

Storage temperature

°C

Tstg

–40 to +125

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

DC Characteristics (T^A= –40 to +85°C, VDD = 5 V ±10%)

Parameter

Input voltage, low

Symbol

VILC

VIL

Conditions

MIN.

–0.5

+3.3

+2.2

TYP.

MAX.

+0.8

Unit

CLK pin

Other pins

+0.8

Input voltage, high

VIHC

VIH

CLK and PU pins

Other pins

VDD + 0.3

0.4

Output voltage, low

Output voltage, high

Power supply current

Input leakage current

Output leakage current

VOL

VOH

IDD

IOL = 2.5 mA

IOH = –400 µA

At operation

0.7 × VDD

µA

ILI

0 V ≤ VIN ≤ VDD

0 V ≤ VOUT ≤ VDD

±10

ILO

Capacitance (TA = +25°C, VDD = 0 V)

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

fC = 1 MHz

–

Output capacitance

I/O capacitance

CIO

Unmeasured pins returned to 0 V

µPD72107

AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%)

When bus master (1)

Parameter

CLK cycle time

Symbol

tCYK

tKKL

Conditions

MIN.

121

MAX.

1000

Unit

CLK low-level time

CLK high-level time

CLK rise time

tKKH

tKR

1.5 – 3.0 V

3.0 – 1.5 V

CLK fall time

tKF

Load condition

DUT

C^L= 50 pF

CL includes jig capacitance.

Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load

capacitance of this device to within 50 pF by inserting a buffer or by some other means.

Remark DUT: device under test

AC test input/output waveform (except clock)

2.4 V

2.2 V

0.8 V

2.2 V

0.8 V

Test points

0.4 V

System clock

tKF

tKR

tKKL

3.0 V

CLK

1.5 V

tKKH

tCYK

µPD72107

When bus master (2)

Parameter

Symbol

tDHQH

tDHQL

tSHA

Conditions

MIN.

MAX.

Unit

HLDRQ ↑ delay time (vs. CLK ↓)

HLDRQ ↓ delay time (vs. CLK ↑)

HLDAK setup time (vs. CLK ↑)

HLDAK hold time (vs. CLK ↑)

AEN ↑ delay time (vs. CLK ↓)

AEN ↓ delay time (vs. CLK ↑)

ASTB ↑ delay time (vs. CLK ↑)

ASTB high-level width

100

tHHA

tDAEH

tDAEL

tDSTH

tSTSTH

tDSTL

tDA

100

tKKH–15

ASTB ↓ delay time (vs. CLK ↓)

100

ADR/UBE/MRD/MWR delay time

(vs. CLK ↑)

ADR/UBE/MRD/MWR float time

tFA

(vs. CLK ↑)

ADR setup time (vs. ASTB ↓)

ADR hold time (vs. ASTB ↓)

tSAST

tHSTA

tKKH–35

tKKL–20

MRD ↓ delay time (vs. ADR float) tDAR

MRD ↓ delay time (vs. CLK ↑)

MRD low-level width

tDRL

tRRL2

tDRH

tSDR

tHRD

tDWL

tWWL2

tDWH

tSRY

tHRY

2tCYK–50

MRD ↑ delay time (vs. CLK ↑)

Data setup time (vs. MRD ↑)

Data hold time (vs. MRD ↑)

MWR ↓ delay time (vs. CLK ↑)

MWR low-level width

100

2tCYK–50

MWR ↑ delay time (vs. CLK ↑)

READY setup time (vs. CLK ↑)

READY hold time (vs. CLK ↑)

CLK

tDHQL

tDHQH

HLDRQ

tSHA

tHHA

HLDAK

AEN

tDAEH

tDAEL

tDSTL

tDSTH

ASTB

tSTSTH

tDA

Hi-Z

Address

A16D8-A23D15

Output data

tSAST

tHSTA

A0, A1/A2-A15

UBE

Address

tWWL2

MWR

tDWL

tHRY

tDWH

READY

tFA

tSRY

Hi-Z

Address

Input data

A16D8-A23D15

tDAR

tSDR

tDRH

tFA

tDA

tHRD

MRD

tRRL2

tDRL

µPD72107

When bus slave (1)

Parameter

Symbol

tWWL

Conditions

MIN.

100

MAX.

Unit

IOWR low-level width

CS low-level hold time

tHWCS

(vs. IOWR ↑)

ADR/UBE/CS low-level setup time tSAW

(vs. IOWR ↓)

ADR/UBE hold time (vs. IOWR ↑)

Data setup time (vs. IOWR ↑)

Data hold time (vs. IOWR ↑)

IORD low-level width

tHWA

tSDW

tHWD

tRRL

tSAR

100

150

ADR/CS low-level setup time

(vs. IORD ↓)

ADR/CS low-level hold time

tHRA

(vs. IORD ↑)

Data delay time (vs. IORD ↓)

Data float time (vs. IORD ↑)

RESET low-level width

tDRD

120

100

tFRD

tRSTL

tSVDD

tSYWR

tRVWR

7tCYK

1000

2tCYK

200

VDD setup time (vs. RESET ↑)

RESET ↑ –1st • IOWR/IORD

IOWR/IORD recovery time

µPD72107

When bus slave

SAW

WWL

HWCS

IOWR

HWA

A0-A23

UBE

SDW

HWD

D0-D15

A0-A23

SAR

HRA

RRL

IORD

DRD

FRD

Hi-Z

D0-D15

SVDD

RSTL

RESET

SYWR

IORD/IOWR

RVWR

IORD

IOWR

RVWR

µPD72107

When bus slave (2)

Parameter

Symbol

Conditions

MIN.

–20

MAX.

Unit

IOWR/IORD high-level setup time

tSWR

(vs. HLDAK ↑)

IOWR/IORD high-level hold time

tHWR

100

(vs. AEN ↓)

HLDAK

tSWR

IOWR/IORD

AEN

tHWR

IOWR/IORD

When bus slave (3)

Parameter

Symbol

tCLCLH

tDIH

Conditions

MIN.

100

MAX.

Unit

CLRINT high-level width

INT ↑ delay time (vs. CLK ↑)

INT ↓ delay time (vs. CLRINT ↑)

CRQ high-level width

100

tDIL

tCRCRH

100

CLK

CLRINT

tCLCLH

INT

tDIH

tDIL

CRQ

tCRCRH

µPD72107

Serial block (1)

Parameter

Symbol

tCYS

Conditions

MIN.

250

110

MAX.

Unit

TxC/RxC cycle time

When on-chip DPLL is not used

TxC/RxC low-level time

TxC/RxC high-level time

TxC/RxC rise time

tSSL

tSSH

tSR

TxC/RxC fall time

tSF

TxD delay time (vs. TxC ↓)

RxD setup time (vs. RxC ↑)

RxD hold time (vs. RxC ↑)

tDTXD

tSRXD

tHRXD

100

Serial clock (when on-chip DPLL is not used)

tSF

tSR

tSSL

2.2 V

TxC/RxC

0.8 V

t^SSH

tCYS

TxC (input)

TxD

tDTXD

RxC

tSRXD

tHRXD

RxD

µPD72107

Serial block (2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

RxC cycle time

tCYR

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

30.3

125

1000

RxC low-level time

RxC high-level time

RxC rise time

tSSRL

tSSRH

tSRR

tSRF

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

RxC fall time

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

Transmit/receive data cycle

tCYD

When on-chip DPLL is used (source clock = RxC)

When on-chip DPLL is used (source clock = CLK)

500

2000

16000

TxC low-level time

tTCTCL

tTCTCH

tDTCTD

tHTCTD

When on-chip DPLL is used

0.5tCYD–25

TxC high-level time

TxD delay time (vs. TxC ↓)

TxD hold time (vs. TxC ↑)

0.5tCYD–25

Serial clock (when on-chip DPLL is used)

tCYR

tSSRL

tSSRH

tSRR

tSRF

RxC

TxC

TxD

tTCTCL

tTCTCH

tHTCTD

tDTCTD

tCYD

µPD72107

Serial block (3)

Parameter

Symbol

tDRTH

tDRTL

tSCD

Conditions

MIN.

MAX.

100

Unit

RTS ↑ delay time (vs. CLK ↑)

RTS ↓ delay time (vs. CLK ↑)

CD setup time (vs. CLK ↑)

CD hold time (vs. CLK ↑)

CTS setup time (vs. CLK ↑)

CTS hold time (vs. CLK ↑)

100

tHCD

tSCT

tHCT

CLK

RTS

tDRTL

tDRTH

tHCD

tSCD

tHCT

CTS

tSCT

µPD72107

3. APPLICATION CIRCUIT EXAMPLE

(1) Connection with SIFC (µPD98201)

PD98201

PD72107

TxD

RxD

BINA

BOUT1

BCLK

LAP-B

SIFC

TxC

RxC

PD72107 System Configuration Example (Local Memory Type)

Local memory 64 Kbytes

UBE

A0-A15

D0-D15

Host processor

PD72107

MEMR

MEMW

IOR

MRD

MWR

IORD

IOWR

PD71086

IOW

Decoder

AB0-AB7

PD71086

A0-A15

D0-D7

AB8-AB15

AB16-AB19

BHE

PD71086

A16D8-A23D15

UBE

DB0-DB15

PD71086

D0-D15

AEN

INT

Local

bus request

INT

Access

contention

resolution

circuit

HLDRQ

HLDAK

WAIT

PD72107 System Configuration Example (Main Memory Sharing Type)

Host processor

PD72107

INT

INTP

PD70116

PD71059

INT

IORD

IOWR

INTAK

RD WR D0-D7

MRD

MWR

HLDRQ

HLDAK

AEN

HLDRQ

HLDAK

ASTB

D0-D7

Decoder

A16-A19

STB OE

OE STB

PD71082

A16D8-A23D15

A16-A19

AD8-AD15

PD71082×3

A0-A15

UBE

A0-A15

AD0-AD7

UBE

BUF R/W

BUFEN

D8-D15

PD71086×2

D0-D7

RD WR

CS UBE D0-D7 D8-D15

Memory

µPD72107

5. PACKAGE DRAWINGS

64 PIN PLASTIC SHRINK DIP (750 mil)

NOTES

ITEM MILLIMETERS

INCHES

+0.028

1. Controlling dimension

millimeter.

+0.68

58.0

2.283

–0.008

–0.20

2. Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

1.78 MAX.

0.070 MAX.

0.070 (T.P.)

1.778 (T.P.)

3. Item "K" to center of leads when formed parallel.

+0.004

0.020

0.50±0.10

–0.005

0.9 MIN.

3.2±0.3

0.035 MIN.

0.126±0.012

0.020 MIN.

0.51 MIN.

+0.011

0.159

+0.26

4.05

–0.008

–0.20

5.08 MAX.

0.200 MAX.

0.750 (T.P.)

19.05 (T.P.)

+0.009

0.669

17.0±0.2

–0.008

+0.004

0.010

+0.10

0.25

–0.003

–0.05

0.17

0.007

0 to 15°

P64C-70-750A,C-3

µPD72107

80 PIN PLASTIC QFP (14x14)

detail of lead end

C D

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.13 mm (0.005 inch) of

its true position (T.P.) at maximum material condition.

17.2±0.4

14.0±0.2

0.677±0.016

+0.009

0.551

–0.008

+0.009

0.551

14.0±0.2

–0.008

17.2±0.4

0.825

0.677±0.016

0.032

0.825

0.032

+0.004

0.012

0.30±0.10

–0.005

0.13

0.005

0.65 (T.P.)

1.6±0.2

0.026 (T.P.)

0.063±0.008

+0.009

0.031

0.8±0.2

–0.008

+0.004

0.006

+0.10

0.15

–0.003

–0.05

0.10

0.004

+0.005

0.106

2.7±0.1

–0.004

0.1±0.1

5°±5°

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

S80GC-65-3B9-5

µPD72107

68 PIN PLASTIC QFJ (950 x 950 mil)

C D

ITEM MILLIMETERS

INCHES

25.2±0.2

0.992±0.008

+0.004

0.953

24.20±0.1

−0.005

+0.004

0.953

24.20±0.1

−0.005

25.2±0.2

0.992±0.008

NOTES

1. Controlling dimension

+0.007

0.076

1.94±0.15

−0.006

millimeter.

0.6

0.024

+0.009

0.173

2. Each lead centerline is located within 0.12 mm of

its true position (T.P.) at maximum material condition.

4.4±0.2

−0.008

+0.009

2.8±0.2

0.110

−0.008

0.9 MIN.

0.035 MIN.

+0.004

0.134

3.4±0.1

−0.005

1.27 (T.P.)

0.050 (T.P.)

+0.003

0.42±0.08

0.017

−0.004

0.12

0.005

+0.009

23.12±0.2

0.910

−0.008

0.006

0.15

R 0.8

R 0.031

+0.08

0.22

+0.003

0.009

−0.07

−0.004

P68L-50A1-3

µPD72107

6. RECOMMENDED SOLDERING CONDITIONS

The µPD72107 should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

Forsolderingmethodsandconditionsotherthanthoserecommendedbelow, contactyourNECsalesrepresentative.

Surface mounting type

• µPD72107GC-3B9: 80-pin plastic QFP (14 × 14 mm)

Soldering Method

Infrared reflow

Soldering Conditions

Recommended Condition Symbol

IR35-00-3

Package peak temperature: 235°C, Time: 30 sec. Max.

(at 210°C or higher), Count: three times or less

VPS

Package peak temperature: 215°C, Time: 40 sec. Max.

(at 200°C or higher), Count: three times or less

VP15-00-3

WS60-00-1

Wave soldering

Solder bath temperature: 260°C, Time: 10 sec. Max.,

Count: one time, Preheating temperature: 120°C Max.

(package surface temperature)

Partial heating

Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)

–

Caution Do not use different soldering methods together (except for partial heating).

• µPD72107L: 68-pin plastic QFJ (950 × 950 mils)

Soldering Method

VPS

Soldering Conditions

Recommended Condition Symbol

VP15-00-1

Package peak temperature: 215°C, Time: 40 sec. Max.

(at 200°C or higher), Count: one time

Partial heating

Pin temperature: 300°C Max., Duration: 3 sec. Max. (per pin row)

–

Insertion type

• µPD72107CW: 64-pin plastic shrink DIP (750 mils)

Soldering Method

Soldering Conditions

Wave soldering (pin only)

Partial heating

Solder bath temperature: 260°C Max., Time: 10 sec. Max.

Pin temperature: 300°C Max., Duration: 3 sec. Max. (per a pin)

Caution Wave soldering must be applied only to pins. Be sure to avoid jet soldering the package body.

µPD72107

[MEMO]

µPD72107

[MEMO]

µPD72107

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to VDD or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

µPD72107

The export of this product from Japan is prohibited without governmental license. To export or re-export this product from

a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5

UPD72107L [NEC]

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