UPD75104AGC_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75104A, 75108A

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

µPD75108A is a 4-bit single-chip CMOS microcomputer having a data processing capability comparable to

that of an 8-bit microcomputer. Operating at high speeds, the microcomputer allows data to be manipulated

in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O

manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different

supply voltage, outputs that can directly drive LEDs, and analog inputs, µPD75108A is suitable for controlling

such small equipments as cameras and VCRs.

Detailed functions are described in the following user’s manual. Be sure to read it for designing.

µPD751XX Series User’s Manual: IEM-922

FEATURES

• Internal memory

• Program memory (ROM)

: 8064 × 8 bits (µPD75108A)

: 4096 × 8 bits (µPD75104A)

• Data memory (RAM)

: 512 × 4 bits (µPD75108A)

: 320 × 4 bits (µPD75104A)

• Architecture “75X” rivaling 8-bit microcomputers

• 43 systematically organized instructions

• A wealth of bit manipulation instructions

• 8-bit data transfer, compare, operation, increment, and decrement instructions

• 1-byte relative branch instructions

• GETI instruction executing 2-/3-byte instruction with one byte

• High speed. Minimum instruction execution time: 0.95 µs (at 4.19 MHz, 5V)

• Instruction execution time change function: 0.95 µs/1.91 µs/15.3 µs (at 4.19 MHz)

• I/O port pins as many as 58

• Three channels of 8-bit timers

• 8-bit serial interface

• Multiplexed vector interrupt function

Unless there are differences among µPD75104A and 75108A functions, µPD75108A is treated as the

representative model throughout this manual.

The information in this document is subject to change without notice.

The mark ★ shows major revised points.

Document No. IC-2568A

(O. D. No. IC-7080B)

Date Published January 1994 P

Printed in Japan

NEC Corporation 1989

µPD75104A, 75108A

ORDERING INFORMATION

Part Number

Package

Quality Grade

µPD75104AGC-xxx-AB8

µPD75108AGC-xxx-AB8

64-pin plastic QFP ( 14 mm)

Standard

Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

µPD75104A, 75108A

FUNCTIONAL OUTLINE

Item

Specifications

Number of Basic Instructions

43

Minimum Instruction

Execution Time

Changeable in three steps: 0.95 µs, 1.91 µs, and 15.3 µs at 4.19 MHz

ROM

RAM

8064 × 8 bits (µPD75108A), 4096 × 8 bits (µPD75104A)

512 × 4 bits (µPD75108A), 320 × 4 bits (µPD75104A)

(4 bits × 8 ) × 4 banks or (8 bis x 4 ) x 4 banks

Internal Memory

General-Purpose Register

Accumulator

Three accumulators selectable according to the bit length of manipulated data:

• 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA)

58 port pins

• CMOS input pins (Pull-up resistor can be conneced to 4 out of 10 pins

in bit units.): 10

• CMOS I/O pins (can directly drive LEDs. Pull-up resistors can be connected to

24 out of 32 pins in bit units.): 32

I/O Port

• Medium voltage N-ch open-drain I/O pins: 12

(can directly drive LEDs. Pull-up resistors can be connected in bit units.)

• Comparator input pins (4-bit accuracy): 4

• 8-bit timer/event counter × 2

Timer/Counter

Serial Interface

• 8-bit basic interval timer (can be used as watchdog timer)

• 8 bits

• LSB first/MSB first mode selectable

• Two transfer modes (transfer/reception and reception only modes)

Vector Interrupt

Test Input

External: 3, Internal: 4

External: 2

Standby

• STOP and HALT modes

• Various bit manipulation instructions (set, reset, test, Boolean operation)

• 8-bit data transfer, compare, operation, increment, and decrement

• 1-byte relative branch instructions

Instruction Set

• GETI instruction constituting 2 or 3-byte instruction with 1 byte

• Power-ON reset circuit (mask option)

Others

• Bit manipulation memory (bit sequential buffer: 16 bits)

Package

• 64-pin plastic QFP ( 14 mm)

3

µPD75104A, 75108A

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)...............................................................................................

2. BLOCK DIAGRAM ...........................................................................................................................

3. PIN FUNCTIONS..............................................................................................................................

6

7

8

9

3.1

3.2

3.3

3.4

3.5

PORT PINS.............................................................................................................................................

PINS OTHER THAN PORTS.................................................................................................................

PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 10

RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 12

NOTES ON USING THE P00/INT4, AND RESET PINS...................................................................... 13

4. MEMORY CONFIGURATION .......................................................................................................... 14

5. PERIPHERAL HARDWARE FUNCTIONS........................................................................................ 19

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

PORTS .................................................................................................................................................... 19

CLOCK GENERATOR CIRCUIT ............................................................................................................ 20

CLOCK OUTPUT CIRCUIT .................................................................................................................... 21

BASIC INTERVAL TIMER ..................................................................................................................... 22

TIMER/EVENT COUNTER ..................................................................................................................... 22

SERIAL INTERFACE .............................................................................................................................. 24

PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .................................................... 26

BIT SEQUENTIAL BUFFER .... 16 BITS ............................................................................................... 27

POWER-ON FLAG (MASK OPTION) .................................................................................................... 27

6. INTERRUPT FUNCTIONS................................................................................................................ 27

7. STANDBY FUNCTIONS .................................................................................................................. 29

8. RESET FUNCTION........................................................................................................................... 30

9. INSTRUCTION SET ......................................................................................................................... 33

10. APPLICATION EXAMPLES.............................................................................................................. 42

10.1 VCR CAMERA ........................................................................................................................................ 42

11. MASK OPTION SELECTION ........................................................................................................... 43

4

µPD75104A, 75108A

12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44

13. CHARACTERISTIC DATA (REFERENCE VALUE) .......................................................................... 54

14. PACKAGE DRAWINGS ................................................................................................................... 59

15. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 60

APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS ........................ 61

APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 62

APPENDIX C. RELATED DOCUMENTS .............................................................................................. 63

5

µPD75104A, 75108A

1. PIN CONFIGURATION (TOP VIEW)

• 64-Pin Plastic QFP ( 14 mm)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P83

P82

P81

P80

P93

P92

P91

P90

1

2

48

47

46

45

44

43

P41

P42

P43

P30

P31

P32

P33

3

4

µ

5

6

7

42

41

40

39

38

37

36

35

34

33

8

V

DD

V

SS

9

NC

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

10

11

12

P140

P141

P142

13

14

15

16

P143

P130

P131

P132

PTH02

PTH01

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P00-P03 : Port 0

P10-P13 : Port 1

P20-P23 : Port 2

P30-P33 : Port 3

P40-P43 : Port 4

P50-P53 : Port 5

P60-P63 : Port 6

P70-P73 : Port 7

P80-P83 : Port 8

P90-P93 : Port 9

P120-P123 : Port 12

P130-P133 : Port 13

P140-P143 : Port 14

SCK

: Serial Clock Input/Output

: Serial Output

SO

SI

: Serial Input

PTO0, PTO1

PCL

: Timer Output

: Clock Output

PTH00-PTH03 : Comparator Input

INT0, INT1, INT4: External Vector Interrupt Input

INT2, INT3

TI0, TI1

X1, X2

RESET

NC

: External Test Input

: Timer Input

: Oscillation Pin

: Reset Input

: No Connection

: Positive Power Supply

: GND

V^DD

V^SS

6

µPD75104A, 75108A

3. PIN FUNCTIONS

3.1

PORT PINS

I/O

8-Bit

Pin Name

I/O

Shared with:

Function

At Reset

Input

Circuit

I/O

Type*¹

P00

P01

Input

I/O

INT4

SCK

SO

B

F

4-bit input port (PORT 0)

P02

I/O

E

B

P03

Input

SI

x

P10

INT0

INT1

INT2

INT3

PTO0

PTO1

PCL

—

P11

Input

4-bit input port (PORT 1)

4-bit I/O port (PORT 2)

Input*²

B -A

P12

P13

P20*³

P21*³

P22*³

P23*³

I/O

Input

E

x

4-bit programmable I/O port (PORT 3)

Can be specified for input or output bitwise.

4-bit I/O port (PORT 4)

P30-P33*³

—

P40-P43*³

P50-P53*³

I/O

—

Input*²

E-A

o

4-bit I/O port (PORT 5)

4-bit programmable I/O port (PORT 6)

Can be specified for input or output bitwise.

4-bit I/O port (PORT 7)

P60-P63*³

I/O

—

Input*²

E-A

P70-P73*³

P80-P83*³

P90-P93*³

I/O

Input*²

E-A

—

4-bit I/O port (PORT 8)

4-bit I/O port (PORT 9)

4-bit N-ch open-drain I/O port (PORT 12)

Built-in pull-up resistors can be specified in bit

units (by mask option).

P120-P123*³

P130-P133*³

P140-P143*³

I/O

—

Input*²

M

Open-drain withstanding voltage: 12 V

4-bit N-ch open-drain I/O port (PORT 13)

Built-in pull-up resistors can be specified in bit

units (by mask option).

o

Open-drain withstanding voltage: 12 V

4-bit N-ch open-drain I/O port (PORT 14)

Built-in pull-up resistors can be specified in bit

units (by mask option).

–

Open-drain withstanding voltage: 12 V

*1: Circles indicate Schmitt trigger input pins.

2: With pull-up resistor connected: high level

Without pull-up resistor connected: high impedance

3: Can directly drive LEDs.

8

µPD75104A, 75108A

3.2

PINS OTHER THAN PORTS

I/O

Pin Name

I/O

Shared with:

—

Function

At Reset

—

Circuit

Type*¹

PTH00-PTH03

TI0

Input

4-bit variable threshold voltage analog input port

External event pulse inputs for timer/event counter.

Also serves as edge-detected vector interrupt input.

1-bit input also possible.

N

B

Input

—

TI1

PTO0

PTO1

SCK

SO

P20

P21

P01

P02

P03

I/O

Outputs for timer/event counter

Input

E

I/O

Serial clock I/O

Input

F

E

B

Serial data output

SI

Input

Serial data input

Edge-detected vectored interrupt input (both rising and

falling edges detected)

INT4

Input

P00

Input

B

INT0

INT1

INT2

INT3

PCL

P10

P11

P12

P13

P22

Edge-detected vectored interrupt inputs (valid

edge selectable)

Input*²

B -A

Input

I/O

Edge-detected testable inputs (rising edge detected)

Input*²

Input

B -A

E

Clock output

Crystal/ceramic system clock oscillator connections.

Input external clock to X1, and signal in reverse phase

with X1 to X2.

X1, X2

—

RESET

NC

Input

—

System reset input (low level active type)

No Connection

—

B

—

V^DD

—

Positive power supply

V^SS

—

GND

*1: Circles indicate Schmitt trigger input pins.

2: With pull-up resistor connected: high level

Without pull-up resistor connected: high impedance

9

µPD75104A, 75108A

3.3

PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the µPD75108A.

TYPE A

TYPE D

V^DD

VDD

data

P-ch

P–ch

OUT

IN

output

disable

N–ch

N-ch

Push – pull output that can be set in a output

high– impedance state (both P–ch and N–ch are off)

Input buffer of CMOS standard

TYPE B

TYPE E

data

IN/OUT

IN

Type D

output

disable

Type A

I/O circuit consisting of Type D push-pull output circuit

and Type A input buffer

Schmitt trigger input with hysteresis characteristics

TYPE D

TYPE E-A

VDD

Pull-up resistor

(mask option)

VDD

Pull-up resistor

(mask option)

data

IN/OUT

Type D

output

IN

disable

Type A

I/O circuit consisting of Type D push-pull output and Type

A input buffer

Schmitt trigger input with hysteresis characteristics

10

µPD75104A, 75108A

TYPE F

TYPE N

Comparator

data

IN

+

–

IN/OUT

Type D

output

disable

Type B

V

^REF(threshold voltage)

I/O circuit consisting of Type D push-pull output circuit

and Type B Schmitt trigger input

TYPE M

V

DD

Pull-up resistor

(mask option)

IN/OUT

N-ch

data

(+12 V

withstand)

output

disable

Medium-voltage input buffer

(+12 V withstand)

11

µPD75104A, 75108A

3.4

RECOMMENDED PROCESSING OF UNUSED PINS

Recommended connections

PTH00-PTH03

TI0

TI1

P00

Connect to V^SSor VDD

Connect to VSS

P01-P03

P10-P13

Connect to VSS or VDD

• Connect to VDD when a pull-up resistor is provided.

• Connect to VSS when a pull-up resistor is not provided.

P20-P23

P30-P33

P40-P43

P50-P53

•

Input: Connect to VSS

Output: Open

•

When a pull-up resistor is provided:

P60-P63

P70-P73

P80-P83

Input: Connect to VDD

Output: Open

When a pull-up resistor is not provided:

P90-P93

Input: Connect to V^SSor VDD

Output: Open

P120-P123

P130-P133

P140-P143

RESET

NC

Connect to V^DD*

Open or connect to VDD

*: Connect this pin to the VDD pin only when a power-ON reset circuit

is provided as a mask option.

12

µPD75104A, 75108A

3.5

NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode,

in which the internal fuctions of the µPD75108A are tested (solely used for IC tests), is provided to the P00/

INT4 and RESET pins.

If a voltage exceeding V^DDis applied to either of these pins, the µPD75108A is put into test mode. Therefore,

even when the µPD75108A is in normal operation, if noise exceeding the VDD is input into any of these pins,

the µPD75108A will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up

to these pins and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot

be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

• Connect a diode across P00/INT4 and

RESET, and VDD.

• Connect a capacitor across P00/INT4 and

, and VDD.

RESET

VDD

P00/INT4, RESET

13

µPD75104A, 75108A

4. MEMORY CONFIGURATION

• Program memory (ROM) ... 8064 × 8 bits (0000H-1F7FH) : µPD75108A

... 4096 × 8 bits (0000H-0FFFH) : µPD75104A

• 0000H, 0001H : Vector table to which address from which program is started is written after reset

• 0002H-000BH: Vector table to which address from which program is started is written after interrupt

• 0020H-007FH : Table area referenced for GETI instruction

• Data memory (RAM)

• Data area ....512 × 4 bits (000H–1FFH): µPD75108A

320 × 4 bits (000H-13FH) : µPD75104A

• Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)

14

µPD75104A, 75108A

(a) µPD75108A

Address

7

6

5

0

0000H MBE RBE

0002H MBE RBE

0004H MBE RBE

0006H MBE RBE

0008H MBE RBE

000AH MBE RBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0/INT1 start address (upper 5 bits)

INT0/INT1 start address (lower 8 bits)

INTSIO start address (upper 5 bits)

INTSIO start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 5 bits)

INTT1 start address (lower 8 bits)

0

CALL ! addr

instruction

subroutine

entry address

CALLF

! faddr

instruction

entry

address

BR ! addr

instruction

branch address

BR $addr

instruction

relational

branch address

-15 to -1,

+2 to +16

0020H

BRCB

GETI instruction reference table

! caddr

instruction

branch

007FH

0080H

address

Branch destination

address and

subroutine entry

address for

07FFH

0800H

GETI instruction

0FFFH

1000H

BRCB ! caddr

instruction

branch address

1F7FH

Fig. 4-1 Program Memory Map (1/2)

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC

with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

15

µPD75104A, 75108A

(b) µPD75104A

Address

7

6

5

0

4

0

0000H MBE RBE

0002H MBE RBE

0004H MBE RBE

0006H MBE RBE

0008H MBE RBE

000AH MBE RBE

Internal reset start address (upper 4 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 4 bits)

INTBT/INT4 start address (lower 8 bits)

INT0/INT1 start address (upper 4 bits)

INT0/INT1 start address (lower 8 bits)

INTSIO start address (upper 4 bits)

INTSIO start address (lower 8 bits)

INTT0 start address (upper 4 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 4 bits)

INTT1 start address (lower 8 bits)

0

CALL ! addr

instruction

subroutine

entry address

CALLF

! faddr

instruction

entry

BR $addr

instruction

relational

address

branch address

-15 to -1,

+2 to +16

BRCB ! caddr

instruction

branch address

0020H

GETI instruction reference table

007FH

0080H

Branch destination

address and

subroutine entry

address for

07FFH

0800H

GETI instruction

0FFFH

Fig. 4-1 Program Memory Map (2/2)

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC

with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

16

µPD75104A, 75108A

(a) µPD75108A

Memory bank

Bank 0

Data memory

000H

01FH

General-purpose

register area

(32 × 4)

Stack area

256× 4

Data memory

Static RAM

(512× 4)

0FFH

100H

256× 4

Bank 1

1FFH

F80H

Not provided

128× 4

Bank 15

Peripheral hardware area

FFFH

Fig. 4-2 Data Memory Map(1/2)

17

µPD75104A, 75108A

(b) µPD75104A

Memory bank

Data memory

000H

01FH

General-purpose

register area

(32 × 4)

Stack area

Bank 0

Data

area

256× 4

Static RAM

(320× 4)

0FFH

100H

Bank 1

× 4

64

13FH

Not provided

F80H

128× 4

Bank 15

Peripheral hardware area

FFFH

Fig. 4-2 Data Memory Map(2/2)

18

µPD75104A, 75108A

5. PERIPHERAL HARDWARE FUNCTIONS

5.1

I/O ports are classified into the following 3 kinds:

• CMOS input (PORT0, 1)

PORTS

:

8

• CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9): 32

• N-ch open-drain input/output (PORT12, 13, 14) : 12

Total

: 52

Table 5-1 Port Function

Port

(Symbol)

Function

Operation and Features

Remarks

Shared witn SI, SO, SCK, and

PORT0

PORT1

Can always be read or tested regardless of operation INT4 pins

4-bit input

mode of shared pin

Shared with INT0 to 3 pins each

bit can be connected to pull-up

resistor by mask otion.

Each bit of Port 6 pins can be

connected to pull-up resistor by

mask option

PORT3

PORT6

Can be set in input or output mode bitwise

Shared with PTO0, PTO1, and

PCL pins.

PORT2

PORT4

PORT5

PORT7

PORT8

PORT9

4-bit I/O*

Can be set in input or output mode in 4-bit units.

Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs

to input or output 8-bit data

Each bit can be connected to pull-

up resistor by mask option

PORT12

PORT13

PORT14

4-bit I/O*

Can be set in input or output mode in 4-bit units.

Ports 12 and 13 can be used in pairs to input or

output 8-bit data

Each bit can be connected to

pull-up resistor by mask option

(N-ch open-drain.

12V)

*: Can directly drive LED.

19

µPD75104A, 75108A

5.2

CLOCK GENERATOR CIRCUIT

The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and

peripheral hardware. In addition, this circuit can change the instruction execution time.

• 0.95 µs/1.91 µs/15.3 µs (operating at 4.19 MHz)

· Basic interval timer (BT)

· Clock output circuit

· Timer/event counter

· Serial interface

X1

X2

X1

X2

1/8 to 1/4096

System clock

generator

circuit

f

^XXor

Frequency divider

X

1/2 1/16

Oscillation

stops

Frequency

divider

Φ

1/4

· CPU

· Clock output

circuit

PCC

PCC0

PCC1

PCC2

PCC3

4

HALT F/F

S

HALT*

STOP*

R

Q

Clears

PCC2,

PCC3

STOP F/F

Wait release signal from BT

RES (internal reset) signal

S

Q

R

Standby release signal from

interrupt control circuit

Remarks 1: fXX= Crystal/ceramic oscillator

2: f = External clock frequency

X

3: * indicates the instruction execution

4: PCC: Processor clock control register

5: One clock cycle (t^CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC

★

characteristics in 12. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

20

µPD75104A, 75108A

5.3

CLOCK OUTPUT CIRCUIT

The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output

clock pulses to the remote control output, peripheral LSIs, etc.

•

Clock output (PCL) : Φ, 524 kHz, 262 kHz (operating at 4.19 MHz)

From the

clock

generator

Φ

Output

buffer

f

XX/2³

XX/2⁴

Selector

PCL/P22

PORT2.2

Bit 2 of PMGB

Port 2 input/

output mode

specification

bit

P22 output

latch

CLOM3 CLOM2 CLOM1 CLOM0 CLOM

4

Internal bus

Fig. 5-2 Clock Output Circuit Configuration

21

µPD75104A, 75108A

5.4

BASIC INTERVAL TIMER

The basic interval timer has these functions:

• Interval timer operation which generates a reference time interrupt

• Watchdog timer application which detects a program runaway

• Selects the wait time for releasing the standby mode and counts the wait time

• Reads out the count value

From the

clock generator

Clear

f

XX/2⁵

f

XX/2⁷

Set

signal

BT

interrupt

request flag

Basic interval timer

(8-bit frequency divider circuit)

MPX

Vector

interrupt

request

signal

f

XX/2⁹

BT

IRQBT

f

XX/2¹²

3

Wait release signal

for standby release

BTM3

BTM2 BTM1

4

BTM0

BTM

*SET1

8

Internal bus

Remarks : *: Instruction execution

Fig. 5-3 Basic Interval Timer Configuration

5.5

µPD75108A contains two channels of timer/event counters.

These two channels are almost identical in terms of configuration and function except the count pulse (CP) that

TIMER/EVENT COUNTER

can be selected and the function to supply clocks to the serial interface.

The functions of the timer/event counter include:

•

Programmable interval timer operation

Output of square wave at an arbitrary frequency to PTOn pin

Event counter operation

Input of TIn pin signal as external interrupt input signal

Dividing TIn pin input by N to output to PTOn pin (frequency divider operation)

Supply of serial shift clock to serial interface circuit (channel 0 only)

Reading counting status

22

µPD75104A, 75108A

5.6

SERIAL INTERFACE

The µPD75108A is equipped with clock 8-bit serial interface that operates in the following two modes:

•

Operation stop mode

Three-line serial I/O mode

24

µPD75104A, 75108A

5.7

PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)

µPD75108A is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold

voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6.

The threshold voltage (V^REF) can be changed in 16 steps (VDD × 0.5/16 – VDD × 15.5/16), and analog signals can be

directly input.

When V^REFis set to VDD × 7.5/16, the programmable threshold port can also be used as a digital signal input port.

Input buffer

+

–

PTH00

PTH01

PTH02

PTH03

+

–

+

–

+

–

Operates

/stops

PTH0

V

DD

PTHM7

1

R

PTHM6

PTHM5

PTHM4

PTHM3

PTHM2

PTHM1

PTHM0

2

MPX

V

REF

8

1

2

R

4

PTHM

Fig. 5-6 Programmable Threshold Port Configuration

26

µPD75104A, 75108A

5.8

BIT SEQUENTIAL BUFFER .... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this

buffer is very useful for processing long data in bit units.

Address bit

Symbol

FC3H

FC2H

FC1H

FC0H

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

BSB3

BSB2

BSB1

BSB0

L register L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

DECS L

INCS L

Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.

Fig. 5-7 Bit Sequential Buffer Format

5.9

POWER-ON FLAG (MASK OPTION)

The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal

has been generated (see Fig. 8-1).

The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation

instruction. However, it cannot be set by the SET1 instruction.

6. INTERRUPT FUNCTIONS

The µPD75108A has 7 different interrupt sources and can perform multiplexed interrupt processing with

priority assigned. In addition to that, the µPD75108A is also provided with two types of edge detection testable

inputs.

The interrupt control circuit of the µPD75108A has these functions:

• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).

• The interrupt start address can be arbitrarily set.

• Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).

• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

27

µPD75104A, 75108A

7. STANDBY FUNCTIONS

The µPD75108A has two different standby modes (STOP mode and HALT mode) to reduce the power

consumption of the microcomputer chip while waiting for program execution.

Table 7-1 Each Status in Standby Mode

STOP Mode

STOP instruction

HALT Mode

HALT instruction

Setting Instruction

Clock Oscillator

Clock oscillation stops

Stops

Only CPU clock Φ is stopped

circuit

Basic Interval

Timer

Operates (sets IRQBT at reference

time intervals)

Operates only when input of external

SCK or output of TO0 is selected as

serial clock (where external TI0 is input

to timer/event counter 0)

Operates when serial clock other

than Φ is specified

Serial Interface

Operation

Status

Timer/Event

Counter

Operates only when TIn pin input

signal is specified as count clock

Operates

Outputs when clock other than CPU

Clock output circuit

CPU

Stops

clock Φ is used

Stops

Release Signal

Interrupt request signal enabled by interrupt enable flag, or RESET input

29

µPD75104A, 75108A

8. RESET FUNCTION

The reset (RES) signal generator circuit is configured as shown in Figure 8-1.

RESET

Internal reset signal

(RES)

Mask

option

SWB

Power-ON

reset

generator

circuit

SWA

Execution of bit

manipulation

instruction*

Power-ON

flag (PONF)

*: PONF cannot be set to 1 by SET1 instruction.

Fig. 8-1 Reset Signal Generator Circuit

ThePower-ONresetgeneratorcircuitgeneratesaninternalresetsignalwhenthesupplyvoltagerises. Thispulse

can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK

OPTION SELECTION.)

The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs.

8-2 and 8-3, respectively.

Wait*

Supply voltage

0 V

(approx. 31.3 ms: 4.19 MHz)

Internal reset signal

(RES)

HALT mode

Operation mode

Internal reset operation

*: The wait time does not include the time required after the RES signal has been generated until the

oscillation starts.

Fig. 8-2 Reset by Power-ON Reset Circuit

30

µPD75104A, 75108A

Wait*

(31.3 ms: 4.19 MHz)

RESET input

Operation mode

or standby mode

HALT mode

Operation mode

Internal reset operation

*: The wait time does not include the time required after the RES signal has been generated until the

oscillation starts.

Fig. 8-3 Reset by RESET Signal

The status of each internal hardware device after the reset operation has been performed is shown in Table 8-

1.

Table 8-1 Hardware Device Status After Reset (1/2)

RESET input during

standby mode

Power-ON Reset or RESET

Input during Operation

Hardware

Lower 5 bits of program

memory address 0000H are

set to PC12-8,*¹and

contents of address 0001H

are set to PC7-0.

Lower 5 bits of program

memory address 0000H

are set to PC12-8,*¹and

contents of address 0001H

are set to PC7-0.

Program Counter (PC)

Carry Flag (CY)

Retained

Undefined

Skip Flags (SK0-SK2)

0

PSW

Interrupt Status Flags (IST0, IST1)

Bit 6 of program memory

address 0000H is set in

RBE, and bit 7 is set in

MBE.

Bit 6 of program memory

address 0000H is set in

RBE, and bit 7 is set in

MBE.

Bank Enable Flags (MBE, RBE)

Stack Pointer (SP)

Undefined

Data Memory (RAM)

Retained*²

Undefined

General-Purpose Registers (X,A,H,L,D,E,B,C)

Bank Selector Registers (MBS, RBS)

Retained

Undefined

0, 0

Counter (BT)

Undefined

Basic interval timer

Mode Register (BTM)

Counter (Tn)

0

Modulo Register (TMODn)

Mode Register (TMn)

TOEn, TOFn

FFH

Timer/Event Counter

(n = 0, 1)

0

0, 0

0

0, 0

Undefined

0

Shift Register (SIO)

Mode Register (SIOM)

Retained

0

Serial Interface

*1: PC11-8 for µPD75104A

2: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input.

31

µPD75104A, 75108A

Table 8-1 Hardware Device Status After Reset (2/2)

RESET input during

standby mode

Power-ON Reset or RESET

Input during Operation

Hardware

Processor Clock Control Register

(PCC)

0

Clock Generator Circuit,

Clock Output Circuit

Clock Output Mode Register

(CLOM)

0

Interrupt Request Flags

(IRQxxx)

Reset (0)

Interrupt Enable Flags (IExxx)

Priority Selector Register (IPS)

0

Interrupt

INT0, 1 Mode Registers

(IM0, IM1)

0, 0

Output Buffer

Output Latch

Off

Cleared (0)

0

Off

Cleared (0)

0

Digital Port

I/O Mode Registers

(PMGA, PMGB, PMGC)

PTH00-PTH03 Input Latches

Mode Register (PTHM)

Undefined

Analog Port

0

Retained

0

Power-ON Flag (PONF)

1 or undefined*

0

Bit Sequential Buffer (BSB0-BSB3)

*: Power-ON reset: 1

RESET input during operation: undefined

32

µPD75104A, 75108A

9. INSTRUCTION SET

(1) Operand representation and description

Describe one or more operands in the operand field of each instruction according to the operand

representation and description methods of the instruction (for details, refer to RA75X Assembler Package

User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from

several operands. The uppercase characters, +, and – are keywords and must be described as is.

Describe an appropriate numeric value or label as immediate data.

The symbols in the register and flag symbols can be described as labels in the places of mem, fmem,

pmem, and bit (for details, refer toµPD751XX Series User‘s Manual (IEM-922)). However, fmem and pmem

restricts the label that can be described.

Representation

Description

X, A, B, C, D, E, H, L

reg

reg1

X, B, C, D, E, H, L

rp

XA, BC, DE, HL

rp1

rp2

rp'

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA', BC', DE', HL'

BC, DE, HL, XA', BC', DE', HL'

rp'1

rpa

rpa1

HL, HL+, HL–, DE, DL

DE, DL

n4

n8

4-bit immediate data or label

8-bit immediate data or label

mem

bit

8-bit immediate data or label*

2-bit immediate data or label

fmem

pmem

FB0H to FBFH, FF0H to FFFH immediate data or label

FC0H to FFFH immediate data or label

addr

µPD75104A 0000H to 0FFFH immediate data or label

µPD75108A 0000H to 1F7FH immediate data or label

12-bit immediate data or label

caddr

faddr

taddr

11-bit immediate data or label

20H to 7FH immediate data (where bit0 = 0) or label

PORTn

IExxx

RBn

PORT0 - PORT9, PORT12 - PORT14

IEBT, IESIO, IET0, IET1, IE0 - IE4

RB0 - RB3

MBn

MB0, MB1, MB15

*: Only even address can be described as mem for 8-bit data processing.

33

µPD75104A, 75108A

(2) Legend of operation field

A

: A register; 4-bit accumulator

B

: B register; 4-bit accumulator

: C register; 4-bit accumulator

: D register; 4-bit accumulator

: E register; 4-bit accumulator

: H register; 4-bit accumulator

: L register; 4-bit accumulator

: X register; 4-bit accumulator

: Register pair (XA); 8-bit accumulator

: Register pair (BC); 8-bit accumulator

: Register pair (DE); 8-bit accumulator

: Register pair (HL); 8-bit accumulator

: Expansion register pair (XA')

: Expansion register pair (BC')

: Expansion register pair (DE')

: Expansion register pair (HL')

: Program counter

C

D

E

H

L

X

XA

BC

DE

HL

XA'

BC'

DE'

HL'

PC

SP

CY

: Stack pointer

: Carry flag; or bit accumulator

PSW : Program status word

MBE

RBE

: Memory bank enable flag

: Register bank enable flag

PORTn : Port n (n = 0 - 9, 12 - 14)

IME

IPS

: Interrupt mask enable flag

: Interrupt priority selection register

IExxx : Interrupt enable flag

RBS

: Register bank selection register

MBS : Memory bank selection register

PCC

.

: Processor clock control register

: Delimiter of address and bit

: Contents addressed by xx

: Hexadecimal data

(xx)

xxH

34

µPD75104A, 75108A

(3) Symbols in addressing area field

.

*1

MB = MBE MBS

(MBS = 0, 1, 15)

*2

*3

MB = 0

MBE = 0 : MB = 0 (00H-7FH)

MB = 15 (80H-FFH)

Data memory

addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

*4

MB = 15, fmem = FB0H-FBFH,

FF0H-FFFH

*5

*6

MB = 15, pmem = FC0H-FFFH

µPD75104A addr = 0000H-0FFFH

µPD75108A addr = 0000H-1F7FH

*7

*8

addr = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

Program memory

addressing

µPD75104A caddr = 0000H-0FFFH (PC11 = 0)

µPD75108A caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1F7FH (PC12 = 1)

faddr = 0000H-07FFH

*9

*10

taddr = 0020H-007FH

Remarks • MB indicates memory bank that can be accessed.

• In *2, MB = 0 regardless of MBE and MBS.

• In *4 and *5, MB = 15 regardless of MBE and MBS.

• *6 to *10 indicate areas that can be addressed.

(4) Machine cycle field

In this field, S indicates the number of machine cycles required when an instruction having a skip

function skips. The value of S varies as follows:

• When no instruction is skipped ........................................................................ S = 0

• When 1-byte or 2-byte instruction is skipped................................................. S = 1

• When 3-byte instruction (BR ! adder or CALL ! adder) is skipped .............. S = 2

Note : The GETI instruction is skipped in one machine cycle.

One machine cycle equals to one cycle of the CPU clock Φ, (= t^CY), and can be changed in three steps

depending on the setting of the processor clock control register (PCC).

35

µPD75104A, 75108A

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Conditions

Operand

Bytes

Operation

tions

monics

les

Transfer MOV

A, #n4

1

2

1

2

1

2

1

2

1

2

1

A ← n4

String effect A

reg1, #n4

XA, #n8

HL, #n8

2

reg1 ← n4

XA ← n8

HL ← n8

rp2 ← n8

A ← (HL)

2

String effect A

String effect B

2

rp2, #n8

A, @HL

2

1

*1

*2

*1

*3

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

@HL, A

2+S

1

A ← (HL), then L ← L+1

A ← (HL), then L ← L–1

A ← (rpa1)

L = 0

L = FH

2

XA ← (HL)

1

(HL) ← A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

2

(HL) ← XA

2

A ← (mem)

2

XA ← (mem)

(mem) ← A

2

(mem) ← XA

A ← reg

2

XA, rp'

2

XA ← rp'

reg1, A

2

reg1 ← A

rp'1, XA

A, @HL

2

rp'1 ← XA

XCH

1

A ↔ (HL)

*1

*2

*1

*3

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

A, mem

XA, mem

A, reg1

2+S

1

A ↔ (HL), then L ← L+1

A ↔ (HL), then L ← L–1

A ↔ (rpa1)

L = 0

L = FH

2

XA ↔ (HL)

2

A ↔ (mem)

2

XA ↔ (mem)

A ↔ reg1

1

XA, rp'

2

XA ↔ rp'

MOVT

XA, @PCDE

3

• µPD75104A

Table

Refer-

ence

XA ← (PC11-8+DE)ROM

• µPD75108A

XA ← (PC12-8+DE)ROM

XA, @PCXA

1

3

• µPD75104A

XA ← (PC11-8+XA)ROM

• µPD75108A

XA ← (PC12-8+XA)ROM

36

µPD75104A, 75108A

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Conditions

Operand

Bytes

Operation

tions

monics

les

Bit

MOV1

CY, fmem.bit

CY, pmem.@L

2

CY ← (fmem.bit)

*4

*5

*1

transfer

2

CY ← (pmem7-2+L3-2.bit(L1-0))

CY ← (H+mem3-0.bit)

CY, @H+mem.

bit

2

fmem.bit, CY

pmem.@L, CY

2

(fmem.bit) ← CY

*4

*5

*1

(pmem7-2+L3-2.bit(L1-0)) ← CY

(H+mem3-0.bit) ← CY

@H+mem.bit,

CY

Arith-

metic

opera-

tion

ADDS

A, #n4

XA, #n8

A, @HL

XA, rp’

rp’1, XA

A, @HL

XA, rp’

rp’1, XA

A, @HL

XA, rp’

rp’1, XA

A, @HL

XA, rp’

rp’1, XA

A, #n4

A, @HL

XA, rp’

rp’1, XA

A, #n4

A, @HL

XA, rp’

rp’1, XA

A, #n4

A, @HL

XA, rp’

rp’1, XA

A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1+S

2+S

1+S

2+S

1

A ← A+n4

carry

XA ← XA+n8

carry

A ← A+(HL)

*1

XA ← XA+rp’

rp’1 ← rp’1+XA

A, CY ← A+(HL)+CY

XA, CY ← XA+rp’+CY

rp’1, CY ← rp’1+XA+CY

A ← A-(HL)

ADDC

SUBS

SUBC

AND

2

1+S

2+S

1

borrow

XA ← XA-rp’

rp’1 ← rp’1-XA

A, CY ← A-(HL)-CY

XA, CY ← XA-rp’-CY

rp’1,CY ← rp’1-XA-CY

2

A ← A

n4

1

A ← A

(HL)

*1

2

XA ← XA

rp’

XA

2

rp’1 ← rp’1

OR

2

A ← A

n4

(HL)

1

A ← A

2

XA ← XA

rp’1 ← rp’1

rp’

XA

2

XOR

2

A ← A

n4

(HL)

1

A ← A

2

XA ← XA

rp’1 ← rp’1

rp’

XA

2

RORC

NOT

1

CY ← A0, A3 ← CY, An-1 ← An

A ← A

Accumulator

Manipulation

A

2

Incre-

ment/

decre-

ment

INCS

reg

1+S

2+S

1+S

2+S

reg ← reg+1

reg = 0

rp1

rp1 ← rp1+1

rp1 = 00H

(HL) = 0

@HL

(HL) ← (HL)+1

(mem) ← (mem)+1

reg ← reg-1

*1

*3

mem

(mem) = 0

reg = FH

rp’ = FFH

DECS

reg

rp’

rp’ ← rp’-1

37

µPD75104A, 75108A

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Conditions

Operand

Bytes

Operation

tions

monics

les

2+S

1+S

2+S

1

Com-

pare

SKE

reg, #n4

2

1

2

1

2

Skip if reg = n4

reg = n4

@HL, #n4

A, @HL

Skip if (HL) = n4

*1

(HL) = n4

A = (HL)

XA = (HL)

A = reg

Skip if A = (HL)

XA, @HL

A, reg

Skip if XA = (HL)

Skip if A = reg

XA, rp’

Skip if XA = rp’

XA = rp’

Carry

flag

SET1

CLR1

CY

CY ← 1

CY

1

CY ← 0

Manipu- SKT

CY

1+S

1

Skip if CY = 1

CY = 1

lation

NOT1

CY

CY ← CY

Memory/ SET1

Bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

2

(mem.bit) ← 1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*4

*5

2

(fmem.bit) ← 1

Manipu-

lation

2

(pmem7-2 + L3-2.bit(L1-0)) ← 1

(H + mem3-0.bit) ← 1

(mem.bit) ← 0

2

CLR1

2

(fmem.bit) ← 0

2

(pmem7-2 + L3-2.bit(L1-0)) ← 0

(H+mem3-0.bit) ← 0

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (pmem7-2+L3-2.bit (L1-0)) = 1

Skip if (H + mem3-0.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0

Skip if (H + mem3-0.bit) = 0

Skip if (fmem.bit) = 1 and clear

2

SKT

SKF

2+S

(mem.bit) = 1

(fmem.bit) = 1

(pmem.@L) = 1

(@H+mem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(pmem.@L) = 0

(@H+mem.bit) = 0

(fmem.bit) = 1

(pmem.@L) = 1

SKTCLR fmem.bit

pmem.@L

Skip if (pmem7-2+L3-2.bit

(L1-0)) = 1 and clear

@H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

2

2+S

2

Skip if (H+mem3-0.bit) = 1 and clear

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

(@H+mem.bit) = 1

AND1

OR1

CY ← CY

(fmem.bit)

2

(pmem7-2+L3-2.bit(L1-0))

(H+mem3-0.bit)

(fmem.bit)

2

CY

←

CY

2

CY ← CY (pmem7-2+L3-2.bit (L1-0))

2

CY

←

CY

(H+mem3-0.bit)

(fmem.bit)

XOR1

2

CY ← CY

(pmem7-2+L3-2.bit (L1-0))

2

CY ← CY (H+mem3-0.bit)

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Operand

Bytes

—

Operation

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Branch

BR

addr

—

• µPD75104A

*6

PC^11-0← addr

The most suitable instruction

is selectable from among

BRCB ! caddr, and BR $ addr

depending on the assembler.

• µPD75108A

PC^12-0← addr

The most suitable instruction

is selectable from among BR

! addr, BRCB ! caddr, and BR

$ addr depending on the

assembler.

! addr

$ addr

3

1

3

2

• µPD75108A

PC12-0 ← addr

*6

*7

• µPD75104A

PC11-0 ← addr

• µPD75108A

PC12-0 ← addr

BRCB

! caddr

PCDE

2

3

2

3

• µPD75104A

*8

PC11-0 ← caddr11-0

• µPD75108A

PC12-0 ← PC12 + caddr11-0

BR

• µPD75104A

PC11-0 ← PC11-8 + DE

• µPD75108A

PC12-0 ← PC12-8 + DE

PCXA

! addr

• µPD75104A

PC11-0 ← PC11-8 + XA

• µPD75108A

PC12-0 ← PC12-8 + XA

Subrou- CALL

tine/

• µPD75104A

*6

(SP-4)(SP-1)(SP-2) ← PC11-0

(SP-3) ← MBE, RBE, 0, 0

PC11-0 ← addr, SP ← SP-4

Stack

Control

• µPD75108A

(SP-4)(SP-1)(SP-2) ← PC11-0

(SP-3) ← MBE, RBE, 0, PC12

PC12-0 ← addr, SP ← SP-4

39

µPD75104A, 75108A

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Operand

Bytes

2

Operation

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Subrou-

tine/

CALLF ! faddr

2

• µPD75104A

*9

(SP-4)(SP-1)(SP-2) ← PC^11-0

(SP-3) ← MBE, RBE, 0, 0

PC11-0 ←0, faddr, SP ← SP-4

Stack

Control

(Cont‘d)

• µPD75108A

(SP-4)(SP-1)(SP-2) ← PC11-0

(SP-3) ← MBE, RBE, 0, PC12

PC12-0 ← 00, faddr, SP ← SP-4

RET

1

3

3+S

3

• µPD75104A

MBE, RBE, x, x ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

SP ← SP+4

• µPD75108A

MBE, RBE, x, PC12 ← (SP+1)

PC^11-0← (SP)(SP+3)(SP+2)

SP ← SP+4

RETS

• µPD75104A

Unconditioned

MBE, RBE, x, x ← (SP+1)

PC^11-0← (SP)(SP+3)(SP+2)

SP ← SP+4, then skip unconditionally

• µPD75108A

MBE, RBE, x, PC12 ← (SP+1)

PC^11-0← (SP)(SP+3)(SP+2)

SP ← SP+4, then skip unconditionally

RETI

• µPD75104A

MBE, RBE, x, x ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

• µPD75108A

MBE, RBE, x, PC12 ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

PUSH

POP

rp

1

2

1

2

(SP-1)(SP-2) ← rp, SP ← SP-2

BS

(SP-1) ← MBS, (SP-2) ← RBS,

SP ← SP-2

rp

1

2

1

2

rp ← (SP+1)(SP), SP ← SP+2

BS

MBS ← (SP+1), RBS ← (SP),

SP ← SP+2

40

µPD75104A, 75108A

Ma-

chine

Cyc-

Instruc- Mne-

Addressing

Area

Skip

Conditions

Operand

Bytes

Operation

tions

monics

les

2

1

2

3

Inter-

rupt

EI

2

1

2

1

IME (IPS.3) ← 1

IExxx

IExxx ← 1

Control DI

IME (IPS.3) ← 0

IExxx ← 0

IExxx

I/O

IN*

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

A ← PORTn

(n = 0-9, 12-14)

XA

← PORTn+1,PORTn (n = 4, 6, 8, 12)

OUT*

HALT

PORTn ← A

(n = 2-9, 12-14)

PORTn+1, PORTn ← XA(n = 4, 6, 8, 12)

Set HALT Mode (PCC.2 ← 1)

Set STOP Mode (PCC.3 ← 1)

No Operation

CPU

Control STOP

NOP

Special SEL

RBn

RBS ← n (n = 0-3)

MBn

taddr

MBS ← n (n = 0, 1, 15)

GETI

• µPD75104A

*10

• Where TBR instruction,

PC^11-0← (taddr)3-0+(taddr+1)

.........................................................

• Where TCALL instruction,

(SP-4)(SP-1)(SP-2) ← PC^11-0

(SP-3) ← MBE, RBE, 0, 0

PC11-0 ← (taddr)3-0+(taddr+1)

SP ← SP-4

.........................................................

.............................

Depends on

• Except for TBR and TCALL

instructions,

referenced

instruction

Instruction execution of

(taddr)(taddr+1)

• µPD75108A

• Where TBR instruction,

PC12-0 ← (taddr)4-0+(taddr+1)

.........................................................

• Where TCALL instruction,

(SP-4)(SP-1)(SP-2) ← PC11-0

(SP-3) ← MBE, RBE, 0, PC12

PC12-0 ← (taddr)4-0+(taddr+1)

SP ← SP-4

.........................................................

.............................

Depends on

• Except for TBR and TCALL

instructions,

referenced

instruction

Instruction execution of

(taddr)(taddr+1)

*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.

Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition.

★

41

µPD75104A, 75108A

10. APPLICATION EXAMPLES

10.1 VCR CAMERA

µPD75108A

High-

current

output

Key matrix

(including

message

input)

Operation

mode LED

indicator

System control/

editing

function

Reel pulse

INT

Battery sensor

Servo

system

control

circuit

Comparator

input

Sensor circuit

Exposure sensor

Tape start/end

sensor

Motor

plunger

driver

circuit,

etc.

Power-

down

detector

INT

On-screen

display

controller

12 V

Audio video system

control circuit

42

µPD75104A, 75108A

11. MASK OPTION SELECTION

µPD75108A has the following mask options. Options to be built in can be selected.

(1) Pin

Mask Option

P10 - P13

P40 - P43

P50 - P53

P60 - P63

P70 - P73

P80 - P83

P90 - P93

P120 - P123

P130 - P133

Pull-down resistor can be built in bitwise.

P140 - P143

(2) Power-ON reset generation circuit, power-ON flag (PONF)

One from the following three ways can be selected.

Switching Selection

(Refer to Fig. 8-1.)

Mask Option Specification

Internal Reset Signal

(RES)

Power-On Reset

Power-On Flag

(PONF)

Generator Circuit

SWA

ON

SWB

ON

Provided

Generates automatically

Not generate autoamtically

—

Not provided

ON

OFF

Not provided

OFF

43

µPD75104A, 75108A

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Parameter

Symbol

VDD

Conditions

Ratings

Unit

V

Supply Voltage

-0.3 to +7.0

VI1

VI2*¹

Other than ports 12 to 14

-0.3 to VDD+0.3

V

Input Voltage

Ports 12 to 14

w/pull-up

resistor

V

Open drain

-0.3 to +13

V

Output Voltage

VO

IOH

-0.3 to VDD+0.3

V

High-Level Output

Current

1 pin

-15

mA

°C

All pins

1 pin

-30

Low-Level Output

Current

IOL*²

Peak

rms

30

15

Total of ports 0, 2 to 4, 12 to 14 Peak

rms

100

60

Total of ports 5 to 9

Peak

rms

100

60

Operating Temperature

Storage Temperature

Topt

Tstg

-40 to +85

-65 to +150

°C

*1: The power supply impedance (pull-up resistor) must be 50 kΩ or higher when a voltage higher than

10 V is applied to ports 12 to 14.

2: rms = Peak value x √Duty

Note: Even if one of the parametrs exceed its absolute maximum rating even momentarily, the quality

of the product may be degraded. The absolute maximum rating therefore specifies the upper or

lower limit of the value at which the product can be used without physical damages. Be sure not

to exceed or fall below this value when using the product.

★

44

µPD75104A, 75108A

OSCILLATOR CIRCUIT CHARACTERISTICS

(T^a= -40 to +85°C, VDD = 2.7 to 6.0 V)

Recommended

Oscillator

Ceramic

Item

Conditions

MIN.

2.0

TYP. MAX. Unit

Constants

Oscillation

VDD = Oscillation

voltage range

3

*

5.0

MHz

frequency(fXX)*¹

Oscillation stabiliza- After VDD come to

X1

X2

tion time*²

MIN. of oscillation

voltage range

4

ms

C1

C2

3

Crystal

Oscillation

*

2.0

10

4.19

5.0

MHz

ms

frequency (fXX)*¹

X1

Oscillation stabiliza- VDD = 4.5 to 6.0 V

tion time*²

C1

C2

30

ms

External Clock

X1 input frequency

(fX)*¹

3

2.0

MHz

X1

X1 input high-,

low-level widths

(tXH, tXL)

100

250

ns

µ

PD74HCU04

*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics

of the oscillator circuit. For instruction execution time, refer to AC Characteristics.

2: Time required for oscillation to stabilize after V^DDhas come to MIN. of oscillation voltage range

or the STOP mode has been released.

★

3: When the oscillation frequency is 4.19 MHz < f^xx≤ 5.0 MHz, do not select PCC = 0011 as the

instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short

of the rated minimum value of 0.95 µs.

Note: When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line

in the figures as follows to avoid adverse influences on the wiring capacity:

• Keep the wiring length as short as possible.

• Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity

of lines through which a high alternating current flows.

• Always keep the ground point of the capacitor of the osccillator circuit at the same potential

as V^SS. Do not connect the ground pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

45

µPD75104A, 75108A

RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS

RECOMMENDED CERAMIC OSCILLATORS

External

Capacitance (pF)

Oscillation

Voltage Range (V)

Manufacturer

Product Name

C1

C2

30

MIN.

2.7

MAX.

6.0

CSA 2.00MG

CSA 4.19MG

CSA 4.19MGU

CST 4.19T

30

Murata Mfg.

Co., Ltd.

30

3.0

2.7

3.0

6.0

30

Provided

100

33

Provided

100

KBR-2.0MS

KBR-4.0MS

KBR-4.19MS

KBR-4.9152M

Kyoto Ceramic

Co., Ltd.

33

RECOMMENDED CRYSTAL OSCILLATOR

External

Capacitance (pF)

Oscillation

Voltage Range (V)

Manufacturer

Kinseki

Product Name

HC-49/U

C1

22

C2

22

MIN.

2.7

MAX.

6.0

Note: Use a crystal oscillator with an equivalent series resistance of 80Ω or less.

46

µPD75104A, 75108A

DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)

Item

Symbol

Conditions

Other than below

Ports 0, 1, TI0, 1, RESET

MIN.

TYP.

MAX.

Unit

V

VIH1

0.7VDD

VDD

High-Level

VIH2

VIH3

0.8 VDD

0.7 VDD

VDD-0.5

0

VDD

V

Input Voltage

Pull-up resistor

Open drain

Ports 12 to 14

12

V

VIH4

VIL1

VIL2

VIL3

X1, X2

VDD

V

Other than below

0.3 VDD

0.2 VDD

0.4

V

Low-Level Input Voltage

High-Level Output Voltage

Ports 0, 1, TI0, 1, RESET

X1, X2

0

V

0

V

VDD = 4.5 to 6.0 V,IOH = -1 mA

IOH = -100 µA

VDD-1.0

VDD-0.5

V

VOH

V

VDD =

Ports 0, 2 to 9, IOL = 15 mA

Ports 12 to 14, IOL = 10 mA

0.35

2.0

0.4

0.5

3

V

4.5 to 6.0 V

V

Low-Level Output Voltage VOL

VDD = 4.5 to 6.0 V, IOL = 1.6 mA

V

IOL = 400 µA

V

ILIH1

Other than below

µA

VIN = VDD

High-Level Input Leakage

ILIH2

X1,X2

20

–3

–20

3

Current

ILIH3

VIN = 12 V

VIN = 0 V

Ports 12 to 14 (open drain)

Low-Level Input

Leakage Current

High-Level Output

Leakage Current

ILIL1

ILIL2

Other than X1, X2

X1, X2

ILOH1

ILOH2

ILOL

VOUT = VDD

VOUT = 12 V

VOUT = 0 V

Other than below

Ports 12 to 14 (open drain)

20

–3

Low-Level Output

Leakage Current

VDD = 5 V±10%

15

10

40

70

80

kΩ

mA

µA

Ports 1, 4 to 9,

and 12 to 14

Internal Pull-Up Resistor

RL

4.19MHz

crystal

VDD = 5 V±10%*²

VDD = 3 V±10%*³

3

9

IDD1

0.55

600

200

0.1

1.5

1800

600

10

Supply Current*¹

oscillator

HALT

VDD = 5 V±10%

VDD = 3 V±10%

IDD2

IDD3

C1 = C2 = 22pF mode

µA

STOP mode, VDD = 3 V±10%

µA

*1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator

circuit is not included.

2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011.

3: When the low-speed mode is set by setting the PCC to 0000.

47

µPD75104A, 75108A

CAPACITANCE (Ta = 25°C, VDD = 0 V)

Parameter

Input Capacitance

Output Capacitance

Symbol

Conditions

MIN.

TYP. MAX. Unit

CIN

f = 1 MHz

Pins other than thosemeasured are at 0 V

15

pF

COUT

C^IO

Input/Output

Capacitance

COMPARATOR CHARACTERISTICS (Ta = -40 to +85^°C, VDD = 4.5 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP. MAX. Unit

Comparison Accuracy

VACOMP

±100

mV

Threshold Voltage

PTH Input voltage

VTH

0

VDD

V

VIPTH

Comparator circuit

current dissipation

PTHM7 is set to “1”

1

mA

POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85°C)

Parameter

Symbol

Conditions

MIN.

4.5

TYP. MAX. Unit

Power-On Reset

High-Level

VDDH

6.0

0.2

V

Operating Voltage

Power-On Reset

Low-Level

V^DDL

0

10

1

V

µs

s

Operating Voltage

Supply Voltage

Rise Time

1

tr

*

Supply Voltage

Off Time

t^off

Power-On Reset Circuit

Current Dissipation*²

IDDPR

VDD = 5 V±10%

10

2

100

20

µA

VDD = 2.5 V

*1: 2¹⁷/fXX (31.3 ms at fXX = 4.19 MHz)

2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated.

V

DDH

V

DD

V

DDL

t

off

t

r

Note: Apply power gradually and smoothly.

48

µPD75104A, 75108A

AC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)

Parameter

Symbol

t^CY

Conditions

VDD = 4.5 to 6.0 V

MIN.

0.95

TYP. MAX. Unit

32

µs

CPU Clock Cycle Time*

(Minimum Instruction

Execution Time = 1

Machine Cycle)

3.8

32

µs

VDD = 4.5 to 6.0 V

0

1

MHz

kHz

µs

TI0, TI1 Input Frequency

fTI

275

tTIH,

t_TIL

0.48

TI0, TI1 Input High-/

Low-Level Width

1.8

0.8

µs

ns

µs

ns

Input

Output

Input

0.95

3.2

SCK Cycle Time

tKCY

Output

Input

3.8

VDD = 4.5 to 6.0 V

0.4

tKH,

tKL

Output

Input

tKCY/2-50

1.6

SCK High-/Low-Level

Width

Output

tKCY/2-150

100

SI Setup Time

tSIK

(vs. SCK↑)

SI Hold Time

t^KSI

400

ns

(vs. SCK↑)

VDD = 4.5 to 6.0 V

300

ns

SCK ↓→ SO Output

delay Time

t^KSO

1000

INT0 to INT4

tINTH,

5

µs

High-/Low-Level Width

RESET Low-Level Width

tINTL

tRSL

*: The cycle time of the CPU clock (Φ) is

determined by the input frequency of

the ceramic or crystal oscillator circuit

and the set value of the processor clock

control register.

t

CY vs. VDD

40

32

7

6

The t^CYvs. VDD characteristics are as

shown on the right.

5

Operation

guaranteed

range

4

3

2

µ

1

0.5

0

1

2

3

4

5

6

V

DD [V]

49

µPD75104A, 75108A

AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET)

0.7 V^DD

0.3 VDD

0.7 VDD

0.3 VDD

Measuring

points

CLOCK TIMING

1/fX

tXL

tXH

X1 input

V

DD –0.5

0.4

TI INPUT TIMING

1/fTI

tTIL

tTIH

VDD

0.8

TI0, TI1

0.2 VDD

50

µPD75104A, 75108A

SERIAL TRANSFER TIMING

tKCY

tKL

tKH

0.8 V^DD

0.2 V^DD

SCK

tSIK

tKSI

0.8 V^DD

0.2 V^DD

SI

Input data

t

KSO

Output data

SO

INTERRUPT INPUT TIMING

tINTL

tINTH

0.8 V^DD

0.2 V^DD

INT0 to INT4

RESET INPUT TIMING

tRSL

RESET

0.2 V^DD

51

µPD75104A, 75108A

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

(T^a= –40 to +85°C)

Parameter

Symbol

V^DDDR

Conditions

MIN.

2.0

TYP. MAX. Unit

Data Retention Supply

Voltage

6.0

10

V

Data Retention Supply

Current*¹

IDDDR

VDDDR = 2.0 V

0.1

µA

Release Signal Set Time tSREL

0

µs

ms

Oscillation Stabilization

Wait Time*²

tWAIT

Released by RESET

2¹⁷/fX

3

Released by interrupt request

*

*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and

comparator circuit is not included

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3 BTM2 BTM1 BTM0 Wait time ( ): fXX = 4.19 MHz

–

0

1

0

1

0

1

0

1

2²⁰/fXX (approx. 250 ms)

2¹⁷/fXX (approx. 31.3 ms)

2¹⁵/fXX (approx. 7.82 ms)

2¹³/fXX (approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

Internal reset operation

HALT mode

STOP mode

Operation

mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction

execution

RESET

tWAIT

52

µPD75104A, 75108A

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

HALT mode

STOP mode

Operation

mode

Data retention mode

V

DD

VDDDR

tSREL

STOP instruction execution

Standby release signal

(interrupt request)

tWAIT

53

µPD75104A, 75108A

13. CHARACTERISTIC DATA (REFERENCE VALUE)

I

DD vs. VDD Characteristics (crystal oscillation)

a

(T = 25˚C)

5000

High-speed mode [0011]

Medium-speed mode [0010]

Low-speed mode [0000]

1000

500

HALT mode [0100]

µ

100

50

STOP mode [1000]

When power-ON

reset circuit and

power-ON flag are

incorporated.

10

5

Figure in [ ] indicates

set values of PCC.

X1

X2

Crystal

1

oscillation

4.194304 MHz

22 pF

0.5

22 pF

0

1

2

3

4

5

6

Supply voltage VDD [V]

I

DD vs. fXX Characteristics (crystal oscillation)

(V_DD= 5.0 V, T

a

= 25˚C)

3.0

2.5

2.0

Figure in [ ] indicates

set values of PCC.

High-speed mode [0011]

X1

X2

C

1

C

2

Medium-speed mode [0010]

Low-speed mode [0000]

1.5

1.0

0.5

0

HALT mode [0100]

0

1

2

3

4

5

f

^XX[MHz]

54

µPD75104A, 75108A

I

DD vs. VDD Characteristics (ceramic oscillation)

a

(T = 25˚C)

5000

High-speed mode [0011]

Medium-speed mode [0010]

Low-speed mode [0000]

HALT mode [0100]

1000

500

µ

100

50

STOP mode [1000]

When power-ON

reset circuit and

power-ON flag are

incorporated.

10

5

Figure in [ ] indicates

set values of PCC.

X1

X2

Ceramic

1

oscillation

4.19 MHz

30 pF

0.5

30 pF

0

1

2

3

4

5

6

Supply voltage VDD [V]

I

DD vs. fXX Characteristics (ceramic oscillation)

(V_DD= 5.0 V, T = 25˚C)

a

3.0

2.5

2.0

1.5

Figure in [ ] indicates

set values of PCC.

High-speed mode [0011]

X1

X2

C

1

C

2

Medium-speed mode [0010]

Low-speed mode [0000]

1.0

0.5

0

HALT mode [0100]

0

1

2

3

4

5

f

^XX[MHz]

55

µPD75104A, 75108A

I

DD vs. f

X

Characteristics (external clock)

(V_DD= 5.0 V, T = 25˚C)

a

3.0

2.5

2.0

Figures in [ ] indicates

set values of PCC.

X1

X2

µPD74HCU04

High-speed mode [0011]

µ

Medium-speed mode [0010]

Low-speed mode [0000]

1.5

1.0

0.5

0

HALT mode [0100]

0

1

2

3

4

5

f_X[MHz]

f

TI vs. VDD Characteristics

1000

500

Operation guaranteed

range

100

50

0

1

2

3

4

5

6

7

V_DD[V]

56

µPD75104A, 75108A

V

OL vs. IOL (Ports 0 and 2 to 9) Characteristics

V

DD = 5 V

DD = 4 V

V

DD = 6 V

30

20

10

V

DD = 3 V

0

1

2

3

4

V

^OL[V]

V

OL vs. IOL (Ports 12 to 14) Characteristics

V

DD = 6 V

VDD = 5 V

30

V

^DD= 4 V

20

V

DD = 3 V

10

0

1

2

3

4

V

^OL[V]

57

µPD75104A, 75108A

V

OH vs. IOH (Ports 0 and 2 to 9) Characteristics

V

DD = 6 V

V DD = 5 V

–15

–10

V

DD = 4 V

V

DD = 3 V

–5

0

1

2

3

4

V

^DD- V ^OH[V]

58

µPD75104A, 75108A

14. PACKAGE DRAWINGS

64 PIN PLASTIC QFP ( 14)

A

B

48

49

33

32

detail of lead end

64

1

17

16

G

H

M

I

J

K

N

L

P64GC-80-AB8-3

NOTE

ITEM

A

MILLIMETERS

INCHES

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at

maximum material condition.

±

17.6 0.4

0.693 0.016

+0.009

±

B

14.0 0.2

0.551

–0.008

+0.009

±

C

14.0 0.2

0.551

–0.008

±

D

F

0.693 0.016

17.6 0.4

1.0

0.039

G

H

I

0.039

+0.004

±

0.35 0.10

0.014

–0.005

0.15

0.006

J

0.8 (T.P.)

0.031 (T.P.)

±

K

1.8 0.2

0.071 0.008

+0.009

±

0.031

L

0.8 0.2

–0.008

+0.10

+0.004

0.15

M

N

P

0.006

–0.05

–0.003

0.10

2.55

0.004

0.100

±

Q

S

0.1 0.1

±

0.004 0.004

2.85 MAX.

0.112 MAX.

59

µPD75104A, 75108A

15. RECOMMENDED SOLDERING CONDITIONS

It is recommended that µPD75104A, 75106A, and 75108A be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document "Semiconductor

Devices Mounting Manual" (IEI-616).

For other soldering methods and conditions, please consult NEC.

Table 15-1 Soldering Conditions of Surface Mount Type

(1) µPD75108AGC - xxx - AB8: 64-pin plastic QFP ( 14 mm)

Symbol for Recommended

Soldering Method

Infrared Reflow

Soldering Conditions

Condition

IR30-00-1

Package peak temperature: 230°C, time: 30 seconds max.

(210°C min.), number of times: 1

VPS

Package peak temperature: 215°C, time: 40 seconds max.

(200°C min.), number of times: 1

VP15-00-1

WS60-00-1

Wave Soldering

Soldering bath temperature: 260°C max., time: 10 seconds

max., number of times: 1,

pre-heating temperature: 120°C max. (package surface

temperature)

Pin Partial Heating

Pin temperature: 300°C max.,

—

time: 3 seconds max. (per side)

(2) µPD75104AGC - xxx - AB8: 64-pin plastic QFP ( 14 mm)

Symbol for Recommended

Condition

Soldering Method

Infrared Reflow

Soldering Conditions

Package peak temperature: 230°C, time: 30 seconds max.

(210°C min.), number of times: 1, number of days: 2 days^*,

IR30-162-1

VP15-162-1

WS60-162-1

(afterwards, 16 hours of prebaking at 125°C is required.)

VPS

Package peak temperature: 215°C, time: 40 seconds max.

(200°C min.), number of times: 1, number of days: 2 days^*,

(afterwards, 16 hours of prebaking at 125°C is required.)

Wave Soldering

Soldering bath temperature: 260°C max., time: 10 seconds

max., number of times: 1, pre-heating temperature: 120°C

max. (package surface temperature), number of days:

2 days^*, (afterwards, 16 hours of prebaking at 125°C is

required.)

Pin Partial Heating

Pin temperature: 300°C max.,

—

time: 3 seconds max. (per side)

*: This means the number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max.

Caution: Do not use two or more soldering methods in combination (except the pin partial heating method).

Notice

A model that can be soldered under the more stringent conditions (infrared reflow peak temperature:

235°C, number of times: 2, and an extended number of days) is also available.

For details, consult NEC.

60

µPD75104A, 75108A

APPENDIX B. DEVELOPMENT TOOLS

The following development support tools are readily available to support development of systems using

µPD75108A:

Hardware IE-75000-R*¹

IE-75001-R

In-circuit emulator for 75X series

IE-75000-R-EM*²

Emulation board for IE-75000-R and IE-75001-R

EP-75108AGC-R

Emulation prove for µPD75104AGC and 75108AGC. It is provided with a 64-

pin conversion socket, EV-9200GC-64

Host machine

EV-9200GC-64

IE Control Program

Software

PC-9800 series (MS-DOS^TMVer.3.30 to Ver.5.00A*³)

IBM PC/AT^TM(PC DOS^TMVer.3.1)

RA75X Relocatable

Assembler

*1: Maintenance product

2: Not provided with IE-75001-R.

3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.

Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).

62

µPD75104A, 75108A

APPENDIX C. RELATED DOCUMENTS

★

63

µPD75104A, 75108A

[MEMO]

64

µPD75104A, 75108A

GENERAL NOTES ON CMOS DEVICES

STATIC ELECTRICITY (ALL MOS DEVICES)

➀

Exercise care so that MOS devices are not adversely influenced by static electricity while being

handled.

The insulation of the gates of the MOS device may be destroyed by a strong static charge.

Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,

or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use

grounding when assembling the MOS device system. Do not leave the MOS device on a plastic

plate and do not touch the pins of the device.

Handle boards on which MOS devices are mounted similarly .

PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices.

➁

Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its

input pin, intermediate level input may be generated due to noise, and an inrush current may flow

through the device, causing the device to malfunction. Therefore, fix the input level of the device

by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an

output pin (whose timing is not specified), each pin should be connected to V^DDor GND through

a resistor.

Refer to “Processing of Unused Pins” in the documents of each devices.

STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application.

➂

Since the characteristics of an MOS device are determined by the quantity of injection at the

molecular level, the initial status of the device is not controlled during the production process. The

output status of pins, I/O setting, and register contents upon power application are not guaranteed.

However, the items defined for reset operation and mode setting are subject to guarantee after

the respective operations have been executed.

When using a device with a reset function, be sure to reset the device after power application.

65

µPD75104A, 75108A

[MEMO]

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which

may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other

intellectual property rights of third parties b y or arising from use of a device described herein or any

other liability arising from use of such device. No license, either express, implied or otherwise, is granted

under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,

nuclear reactor control systems and life support systems. If customers intend to use NEC devices for

above applications or they intend to use "Standard" quality grade NEC devices for the applications not

intended by NEC, please contact our sales people in advance.

Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime system, etc.

M4 92.6

MS-DOS is a trademark of Microsoft Corporation.

PC DOS and PC/AT are trademarks of IBM Corporation.

66


型号：	UPD75104AGC
厂家：	NEC
描述：	4-BIT SINGLE-CHIP MICROCOMPUTER 4位单片机微控制器和处理器外围集成电路计算机时钟
文件：	总66页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD75104AGC [NEC]

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