UPD75218CW-XXX [NEC]
Microcontroller, 4-Bit, MROM, 6MHz, MOS, PDIP64, 0.750 INCH, PLASTIC, SDIP-64;
| 型号： | UPD75218CW-XXX |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 4-Bit, MROM, 6MHz, MOS, PDIP64, 0.750 INCH, PLASTIC, SDIP-64 计算机 |
| 文件： | 总62页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75218
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM,
I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses,
a serial interface and a vectored interrupt function integrated on a single chip.
It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/
watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with
many functions and to decrease performance costs.
The µPD75218 has larger ROM and RAM capacity than its predecessor, µPD75217. So several codes required
before have been reduced to only one code in the µPD75218 specifications.
The one-time PROM product, µPD75P218 and various development tools (IE-75001-R, assembler, etc.) are
available for system development evaluation or small production.
The following manual provides detailed description of the functions of theµPD75218. Be sure to read this manual
when you design an application system.
µPD75218 User’s Manual: IEU-692
FEATURES
• On-chip large-capacity ROM and RAM
• Program memory (ROM): 32K × 8 bits
• Data memory (RAM)
: 1K × 4 bits
• Architecture equal to that of an 8-bit microcomputer
• High-speed operation: Minimum instruction execution time : 0.67 µs (when the microcomputer operates at
6.0 MHz)
• Instruction execution time variable function realizing a wide range of operating voltages
• On-chip programmable fluorescent indication panel (FIP) controller/driver
• Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
• Interrupt function with importance attached to applications
• For power-off detection
• For reception of remote-controller signal
• Product with an on-chip PROM : µPD75P218 (on-chip EPROM : WQFN package)
The information in this document is subject to change without notice.
Document No. IC-3035
Major changes in this version are indicated by stars (★) in the margins.
(O. D. No. IP-8484)
Date Published November 1993 P
Printed in Japan
© NEC Corporation 1993
µPD75218
ORDERING INFORMATION
Part number
Package
Quality grade
µPD75218CW-×××
64-pin plastic shrink DIP (750 mil)
Standard
Standard
µPD75218GF-×××-3BE
64-pin plastic QFP (14 × 20 mm)
Remark ××× is a ROM code.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications
LIST OF FUNCTIONS
Item
Function
ROM: 32640 × 8 bits, RAM: 1024 × 4 bits
Built-in memory
®
• CMOS input : 8 lines
I/O line (including FIP dual-
function pins and excluding
FIP dedicated pins)
• CMOS I/O
: 20 lines (LED drive: 8 lines)
• CMOS output : 1 line (PWM/pulse output)
P-ch open-drain output with high withstand voltage and high current: 4 lines (LED drive)
33 lines
•
• 0.67 µs, 1.33 µs, 10.7 µs (with main system clock operating at 6.0 MHz)
• 0.95 µs, 1.91 µs, 15.3 µs (with main system clock operating at 4.19 MHz)
• 122 µs (with subsystem clock operating at 32.768 kHz)
Instruction cycle
• Number of segments : 9 to 16 segments
FIP controller/driver
• Number of digits
• Dimmer function
: 9 to 16 digits
: 8 levels
• Mask option for pull-down resistors
• Key scan interrupt generation
• Timer/pulse generator : 14-bit PWM output enabled
Timer
• Watch timer
• Timer/event counter
• Basic interval timer
: Buzzer output enabled
4 channels
: Watchdog timer application capability
• MSB start/LSB start switchable
Serial interface
• Serial bus configuration capability
External : 3, Internal : 5
External : 1, Internal : 1
Vectored interrupt
Test input
• Ceramic/crystal oscillator for main system clock oscillation : 6.0 MHz standard
• Ceramic/crystal oscillator for main system clock oscillation : 4.19 MHz standard
System clock oscillator
• Crystal oscillator for subsystem clock oscillation
: 32.768 kHz standard
• High withstand-voltage port (pull-down resistor)
• Port 6 (pull-down resistor)
Mask option
–40 to +85 °C
Operating temperature range
Operating supply voltage
Package
2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 20 mm)
2
µPD75218
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .........................................................................................
2. BLOCK DIAGRAM ......................................................................................................................
3. PIN FUNCTIONS ........................................................................................................................
5
6
7
7
3.1
3.2
3.3
3.4
3.5
3.6
PORT PINS ......................................................................................................................................
NON-PORT PINS ............................................................................................................................
PIN INPUT/OUTPUT CIRCUIT LIST..............................................................................................
HANDLING UNUSED PINS ...........................................................................................................
NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN .........................................................
NOTES ON USE OF THE XT1, XT2 AND P50 PIN ......................................................................
8
9
10
11
11
4. MEMORY CONFIGURATION .................................................................................................... 12
5. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
PORTS..............................................................................................................................................
CLOCK GENERATOR......................................................................................................................
BASIC INTERVAL TIMER ...............................................................................................................
WATCH TIMER ..............................................................................................................................
TIMER/EVENT COUNTER .............................................................................................................
TIMER/PULSE GENERATOR .........................................................................................................
SERIAL INTERFACE .......................................................................................................................
FIP CONTROLLER/DRIVER............................................................................................................
15
16
17
18
19
20
21
23
6. INTERRUPT FUNCTIONS .......................................................................................................... 24
7. STANDBY FUNCTIONS ............................................................................................................. 26
8. RESET FUNCTIONS ................................................................................................................... 27
9. INSTRUCTION SET .................................................................................................................... 29
10. MASK OPTION SELECTION...................................................................................................... 38
11. APPLICATION BLOCK DIAGRAM ............................................................................................. 39
11.1 VCR TIMER TUNER ........................................................................................................................
11.2 COMPACT DISK PLAYER ..............................................................................................................
11.3 ECR...................................................................................................................................................
39
40
41
3
µPD75218
12. ELECTRICAL SPECIFICATIONS ............................................................................................... 42
★
★
13. CHARACTERISTIC CURVES (FOR REFERENCE)..................................................................... 53
14. PACKAGE DIMENSIONS ........................................................................................................... 55
15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 57
APPENDIX A FUNCTIONS OF µPD752×× SERIES PRODUCTS ................................................ 58
APPENDIX B DEVELOPMENT TOOLS ......................................................................................... 59
APPENDIX C RELATED DOCUMENTS ........................................................................................ 60
★
4
µPD75218
1. PIN CONFIGURATION (TOP VIEW)
S3
S2
S1
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
VDD
S4
S5
S6
S7
S8
S9
VPRE
VLOAD
T15/S10
T14/S11
T13/S12/PH0
T12/S13/PH1
T11/S14/PH2
T10/S15/PH3
T9
T8
T7
T6
T5
T4
T3
S0
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20
9
10
11
12
13
14
15
16
17
18
19
20
21
22
µ
P21
P22
P23/BUZ
P30
P31
P32
P33
P60
P61
P62
23
42
T2
P63
P40
P41
P42
P43
PPO
X1
24
25
26
27
28
29
30
31
41
40
39
38
37
36
35
34
T1
T0
RESET
P53
P52
P51
P50
XT2
X2
VSS
32
33
XT1
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
P41
P42
P43
PPO
X1
32
31
30
29
28
27
26
25
24
23
22
21
20
P01/SCK
P00/INT4
S0
53
54
55
56
57
58
59
60
61
62
63
64
S1
S2
X2
S3
µ
PD75218GF-× × ×-3BE
VSS
VDD
S4
XT1
XT2
P50
P51
P52
P53
S5
S6
S7
S8
S9
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
5
Port 0
Port 1
4
4
P00–P03
P10–P13
Basic interval
timer
SP(8)
SBS(4)
CY
Program counter (15)
ALU
INTBT
Port 2
Port 3
Port 4
Port 5
Port 6
4
4
4
4
4
P20–P23
P30–P33
P40–P43
P50–P53
P60–P63
TI0/P13
Timer/event
counter #0
Bank
INTT0
Timer/pulse
generator
General register
PPO
ROM
Program memory
32640 × 8 bits
INTTPG
SI/P03
SO/P02
SCK/P01
RAM
Decode and control
Data memory
1024 × 4 bits
Serial interface
10
4
T0–T9
INTSIO
T10/S15/PH3–
T13/S12/PH0
INT0/P10
INT1/P11
INT2/P12
FIP
controller/
driver
T14/S11,
T15/S10
2
Interrupt control
S0–S9
10
INTW
f
/2N
X
INT4/P00
V
V
PRE
System clock
generator
LOAD
CPU clock
Φ
Watch timer
Clock divider
Standby control
Sub
Main
INTKS
Port H
µ
4
PH0–PH3
BUZ/P23
XT1 XT2 X1 X2
V
DD
VSS RESET
µPD75218
3. PIN FUNCTIONS
3.1 PORT PINS
Dual-
8-bit
I/O
Input / output
circuit typeNote
Pin
I/O
Function
4-bit input port (PORT0)
After reset
Input
function pin
×
P00
P01
Input
Input/output
Input/output
Input
INT4
SCK
SO
B
F
P02
G
B
B
P03
SI
P10
INT0
INT1
INT2
TI0
Noise elimination function available
Noise elimination function available
Input
Input
Input
P11
P12
4-bit input port (PORT1)
P13
4-bit input/output port (PORT2)
P20
Input/
–––
×
E
output
P21
–––
P22
–––
P23
BUZ
–––
Input/
Programmable 4-bit input/ output port (PORT3).
Input/output specifiable in 1-bit units.
Input
Input
Input
Input
P30 to P33
E
E
E
V
output
●
×
Input/
P40 to P43
P50 to P53
P60 to P63
–––
–––
–––
4-bit input/output port (PORT4).
LED direct drive capability.
output
Input/
4-bit input/output port (PORT5).
LED direct drive capability.
output
Programmable 4-bit input/output port (PORT6).
Input/output specifiable in 1-bit units.
On-chip pull-down resistor available (mask
option). Suitable for key input.
Input/
output
×
4-bit P-ch open-drain output port with high
withstand voltage and high current (PORTH).
LED direct drive capability. On-chip pull-down
resistor available (mask option).
I
PH0
PH1
PH2
PH3
Output
T13/S12
T12/S13
T11/S14
T10/S15
Low level
(with an on-
chip pull-
down resistor)
or high
impedance.
Note The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
7
µPD75218
3.2 NON-PORT PINS
Dual-
Input / output
circuit typeNote
After reset
Pin
I/O
Function
function pin
Output
FIP controller/ Output pins with high withstand voltage Low level
–––
I
T0 to T9
(with an on-
driver output and high current for digit output
chip pull-
pins.
down
resistor ) or
high
impedance
(without a
pull-down
resistor)
Output pins with high withstand voltage
and high current also used for digit/seg-
ment output
T10/S15 to
T13/S12
PH3 to PH0
Pull-down
resistor can
be incorpo-
rated in bit
units (mask
option).
Extra pins can be used as PORTH.
Output pins with high withstand voltage
and high current also used for digit/
segment output
T14/S11,
T15/S10
–––
Static output also possible.
S9
Highwithstand-voltageoutputforsegment
output. Static output also possible.
High withstand-voltage output for segment
output
S0 to S8
PPO
Output
Input
–––
Timer/pulse generator pulse output
High
D
impedance
–––
External event pulse input for timer/event counter
Serial clock input/output
TI0
SCK
SO
P13
P01
P02
B
F
Input
Input
Input/output
Input/output
Serial data output or serial data input/output
Serial data input or normal input
G
SI
Input
Input
P03
P00
Input
–––
B
B
INT4
Edge-detected vectored interrupt input (rising and falling
edge detection).
–––
Edge-detected vectored interrupt input with noise
INT0
Input
P10
B
elimination function (detection edge selection possible).
INT1
INT2
BUZ
P11
P12
P23
–––
Input
Edge-detected testable input (rising edge detection).
B
E
Fixed frequency output (for buzzer or system clock
trimming).
Input
Input/output
–––
–––
X1
X2
Input
–––
–––
Crystal/ceramic connection pin for main system clock
–––
oscillation.
External clock input to X1 and its inverted clock input to
X2.
Crystal connection pin for subsystem clock oscillation.
External clock input to XT1. Leave XT2 open.
–––
XT1
Input
–––
–––
–––
XT2
Input
–––
System reset input (low level active).
RESET
VPRE
–––
–––
B
I
★
FIP controller/driver output buffer power supply.
–––
–––
–––
–––
–––
–––
–––
FIP controller/driver pull-down resistor connection pin.
Positive power supply.
–––
–––
–––
I
VLOAD
VDD
–––
–––
VSS
GND potential.
Note The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
8
µPD75218
3.3 PIN INPUT/OUTPUT CIRCUIT LIST
Type A
Type F
Data
V
DD
IN/OUT
Type D
Type B
Output
disable
P-ch
IN
N-ch
Input/output circuit consisting of type D push-pull output
and type B schmitt trigger input
CMOS-specified input buffer
Type B
Type G
V
DD
P-ch output
disable
P-ch
Data
IN/OUT
IN
N-ch
Type B
Schmitt trigger input having hysteresis characteristics
Type D
Input/output circuit capable of switching between push-pull
output and N-ch open-drain output (with P-ch off).
Type V
VDD
Data
Data
IN/OUT
P-ch
Type D
Output
disable
OUT
Output
disable
N-ch
Type A
Pull-down
resistor
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
(Mask option)
Type E
Type I
V
DD
V
DD
Data
IN/OUT
Type D
Output
disable
Data
P-ch
P-ch
OUT
Pull-down resistor
(Mask option)
N-ch
Type A
V
LOAD
V
PRE
Input/output circuit consisting of type D push-pull output
and type A input buffer
9
µPD75218
3.4 HANDLING UNUSED PINS
Pin
P00/INT4
Recommended connection
Connect to VSS
P01/SCK
Connect to VSS or VDD
P02/SO
P03/SI
P10/INT0 to P12/INT2
P13/TI0
Connect to VSS
P20 to P22
P23/BUZ
Input state : Connect to VSS or VDD
Output state : Leave open
P30 to P33
P40 to P43
P50 to P53
P60 to P63
PPO
Leave open
S0 to S9
T15/S10 to T14/S11
T0 to T9
T10/S15/PH3 to T13/S12/PH0
XT1
Connect to VSS or VDD
Leave open
XT2
VLOAD when there is no on-
chip load resistor
Connect to VSS or VDD
10
µPD75218
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN
P00/INT4 and RESET pins have the function (especially for IC test) to test µPD75218 internal operations in addition
to the functions described in sections 3.1 and 3.2.
The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4
and RESET pins causing errors.
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
against noise using the following external components.
•
Connecting a diode between the pins and VDD
•
Connecting a capacitor between the pins and VDD
VDD
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once/second or less).
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
becomes fast).
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
P50 pin as shown below.
µPD75218
P50
XT1
XT2
0.0068 µF
32.768 kHz
11
µPD75218
4. MEMORY CONFIGURATION
• Program memory (ROM): 32640 words × 8 bits
•
•
•
0000H and 0001H: Vector table which contains the program start address after reset
0002H to 000FH : Vector table which contains the program start addresses when interrupts occur
0020H to 007FH : Table area referenced by a GETI instruction
• Data memory
•
Data area
: 1024 words × 4 bits (000H to 3FFH)
•
Peripheral hardware area : 128 words × 4 bits (F80H to FFFH)
12
µPD75218
Fig. 4-1 Program Memory Map
Internal reset start address
MBE RBE
(high-order 6 bits)
0000H
Internal reset start address (low-order 8 bits)
(high-order 6 bits)
INTBT/INT4 start address (low-order 8 bits)
0002H MBE RBE INTBT/INT4 start address
MBE RBE INT0 start address
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
(high-order 6 bits)
(low-order 8 bits)
0004H
0006H
Entry address
specified in
CALLF !faddr
instruction
INT0 start address
INT1 start address
INT1 start address
MBE RBE
Branch address
specified in BRA !addr
instruction
0008H MBE RBE INTSO start address
INTSO start address
Branch address
Branch address
specified in CALLA !addr
instruction
000AH MBE RBE INTT0 start address
INTT0 start address
specified in
BRCB !caddr
instruction
MBE RBE INTTPG start address
INTTPG start address
000CH
Relative branch address
specified in BR $addr
instruction (–15 to –1,
+2 to +16)
MBE RBE
000EH
INTKS start address
INTKS start address
Branch address
specified in BR !addr
instruction
Branch address
specified in CALL !addr
instruction
0020H
GETI instruction reference table
007FH
0080H
Branch/call
address specified
in GETI instruction
07FFH
0800H
0FFFH
1000H
Branch address speci-
fied in BRCB !caddr
instruction
1FFFH
2000H
Branch address speci-
fied in BRCB !caddr
instruction
2FFFH
3000H
Branch address speci-
fied in BRCB !caddr
instruction
3FFFH
4000H
Branch address speci-
fied in BRCB !caddr
instruction
4FFFH
5000H
Branch address speci-
fied in BRCB !caddr
instruction
5FFFH
6000H
Branch address speci-
fied in BRCB !caddr
instruction
6FFFH
7000H
Branch address speci-
fied in BRCB !caddr
instruction
7F7FH
Caution The start address of an interrupt vector shown above consists of 14 bits. So the start address must be
set within a 16K-byte space (0000H to 3FFFH).
Remark In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed
is enabled by BR PCDE and BR PCXA instructions.
13
µPD75218
Fig. 4-2 Data Memory Map
Data memory
Memory bank
000H
General
register
(32 × 4)
area
01FH
0
1
020H
256 × 4
0FFH
100H
Stack
area
256 × 4
(64 × 4)
1BFH
1C0H
Display
data
memory,
etc.
Data area
Static RAM
(1024 × 4)
1FFH
200H
256 × 4
2
3
2FFH
300H
256 × 4
3 FFH
Not contained
F80H
FFFH
Peripheral
hardware area
15
128 × 4
14
µPD75218
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
The µPD75218 has the following three types of I/O port:
• 8 CMOS input pins (PORT0 and PORT1)
• 20 CMOS I/O pins (PORT2, PORT3, PORT4, PORT5, and PORT6)
• 4 P-ch open-drain output pins with high withstand voltage and high current (PORTH)
Total: 32 pins
Table 5-1 Functions of Ports
Port
Function
Operation and feature
Always read or test possible irrespective of the dual-function Shares the pins with SI, SO, SCK
pin operating mode. and INT4.
Always read or test possible, P10 and P11 are inputs with the Shares the pins with INT0 to
Remarks
PORT0
4-bit input
PORT1
noise elimination function.
INT2 and TI0.
PORT2
PORT4
PORT5
4-bit
Can be set to the input or output mode in 4-bit units.
Ports 4 and 5 can input/output data in pairs in 8-bit units.
Ports 4 and 5 can directly drive LEDs.
P23 shares the pin with BUZ.
input/output
PORT3
PORT6
Can be set bit-wise to the input or output mode. Port 6 can
incorporate a pull-down resistor by mask option.
PORTH
4-bit output
P-ch open-drain output port with high withstand voltage and Shares the pins with T10/S15 to
high current. Can drive an FIP and LED directly. Can T13/S12.
incorporate a pull-down resistor in bit units by mask option.
15
µPD75218
5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
0.67 µs, 1.33 µs, 10.7 µs (main system clock: 6.0 MHz)
0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
122 µs (subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
XT1
• FIP controller
• Basic interval timer (BT)
• Timer/event counter
• Serial interface
• Watch timer
• INT0 noise eliminator
f
XT
Subsystem
clock generator
Watch timer
XT2
X1
Timer/pulse
generator
1/8 to 1/4096
Main system
clock generator
fXX
Frequency divider
f
X
X2
1/2 1/6
SCC
Oscillation
stop
Frequency
divider
SCC3
1/4
Φ
SCC0
PCC
• CPU
• INT0 noise eliminator
• INT1 noise eliminator
PCC0
PCC1
4
HALT F/F
S
PCC2
PCC3
HALTNote
STOPNote
Q
R
PCC2 and
PCC3
clear
Wait release signal from BT
RES signal (internal reset)
STOP F/F
Q
S
Note Instruction execution
R
Standby release signal from
interrupt control circuit
Remarks 1. fX = Main system clock frequency
2. fXT = Subsystem clock frequency
3. fXX = System clock frequency
4. Φ = CPU clock
5. PCC: Processor clock control register
6. SCC: System clock control register
7. 1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in
★
Chapter 12.
16
µPD75218
5.3 BASIC INTERVAL TIMER
The basic interval timer has the following functions:
•
•
•
•
Interval timer operation to generate reference time
Watchdog timer application to detect inadvertent program loop
Wait time select and count upon standby mode release
Count contents read
Fig. 5-2 Basic Interval Timer Configuration
From clock
generator
Clear
Clear
f
f
f
XX/25
XX/27
XX/29
Set
Basic interval timer
(8-bit frequency divider)
BT interrupt
request flag
MPX
Vectored
interrupt
request
signal
BT
IRQBT
f
XX/212
3
Wait release
signal during
standby release
BTM3
BTM2
BTM1
BTM0 BTM
SET1Note
4
8
Internal bus
Note Instruction execution
17
µPD75218
5.4 WATCH TIMER
The µPD75218 incorporates one channel of watch timer. The watch timer has the following functions:
•
Sets the test flag (IRQW) at 0.5 sec intervals.
The standby mode can be released by IRQW.
•
•
•
0.5 second interval can be set with the main system clock and subsystem clock.
The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.
The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound
and trim the system clock oscillator frequency.
•
Since the frequency divider can be cleared, the watch can be started from zero second.
Fig. 5-3 Watch Timer Block Diagram
f
W
27
(256 Hz : 3.91 ms)
INTW
IRQW
set signal
f
XX
Selector
f
W
214
128
(32.768 kHz)
From
clock
generator
f
W
Selector
Frequency divider
Clear
(32.768 kHz)
2 Hz
0.5 sec
f
XT
(32.768 kHz)
f
16
W
(2.048 kHz)
Output buffer
P23/BUZ
WM
WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3
Bit 2 of PMGB
P23
Port 2
output
latch
input/output
mode
8
Internal bus
Remark Values when fXX is 4.194304 MHz and fXT is 32.768 kHz are indicated in parentheses.
Caution When the main system clock operates at 6.0 MHz, a time interval of 0.5 second cannot be produced.
Before producing this time interval, the main system clock must be changed to the subsystem clock.
18
µPD75218
5.5 TIMER/EVENT COUNTER
The µPD75218 incorporates one channel of timer/event counter. The timer/event counter has the following
functions:
•
Program interval timer operation
•
•
Event counter operation
Count state read function
Fig. 5-4 Timer/Event Counter Block Diagram
Internal bus
SET1Note
8
8
8
TM0
TMOD0
Modulo register (8)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
8
Match
Comparator (8)
INTT0
IRQT0
set signal
Input buffer
8
T0
P13/TI0
Count register (8)
Clear
MPX
CP
From clock
generator
Timer operation start
(See Fig. 5-1.)
IRQT0
clear
Note Instruction execution
19
µPD75218
5.6 TIMER/PULSE GENERATOR
The µPD75218 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse
generator. The timer/pulse generator has the following functions:
(a) Functions available in the timer mode
•
•
8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels
Square wave output to PPO pin
(b) Functions available in the PWM pulse generation mode
•
14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable
to tuning)
215
fX
•
Fixed time interval (
= 5.46 ms when the microcomputer operates at 6.0 MHz)Note interrupt generation
If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.
Note 7.81 ms when the microcomputer operates at 4.19 MHz
Caution If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result.
To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode
register.
Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal bus
8
8
MODL
MODH
Modulo register L (8)
Modulo register H (8)
TPGM3
(Set to 1)
INTTPG
IRQTPG
set signal
Modulo latch H (8)
8
Match
Output buffer
PPO
Comparator (8)
8
T F/F
Selector
Set
Frequency
divider
CP
fX
1/2
Prescalar select latch (5)
Clear
Count register (8)
Clear
TPGM4 TPGM5 TPGM7
TPGM1
20
µPD75218
Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)
Internal bus
8
8
MODH
MODL
(2)
Modulo register H (8)
Modulo register L (8)
TPGM3
MODH (8)
Modulo latch (14)
MODL7-2 (6)
Output buffer
TPGM1
1/2
PWM pulse generator
Selector
TPGM5
PPO
fX
Frequency divider
INTTPG
(IRQTPG set signal)
215
TPGM7
(
= 5.46 ms : when f
is 6.0 MHz)Note
X
f
X
Note 7.81 ms when the microcomputer operates at 4.19 MHz.
5.7 SERIAL INTERFACE
The serial interface has the following functions:
•
•
•
Clock synchronous 8-bit send/receive operation (simultaneous send/receive)
Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output)
Start LSB/MSB switching
These functions facilitate data communication with another microcomputer of µPD7500 series or 78K series via
a serial bus and coupling with peripheral devices.
21
Fig 5-7 Serial Interface Block Diagram
Internal bus
8
SET1Note 2
8
8
P03/SI
SIO0
SIO7
SIO
SIOM
Shift register (8)
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
Note 1
SO output
latch
P02/SO
INTSIO
IRQSIO
Overflow
Serial clock
counter (3)
set signal
IRQSIO
clear signal
Clear
Serial start
P01/SCK
R
S
Q
Φ
f
f
XX/24
MPX
XX/210
µ
Notes 1. CMOS output and N-ch open-drain output switchable output buffer.
2. Instruction execution
µPD75218
5.8 FIP CONTROLLER/DRIVER
The FIP controller/driver in the µPD75218 has the same functions as that in its predecessor, µPD75216A:
• The FIP controller/driver outputs the segment signal by automatically reading display data (DMA operation)
and automatically generates the digit signal.
• The FIP controller/driver can control the FIP of 9 to 16 segments and 9 to 16 digits with the display mode register
(DSPM) and the digit select register (DIGS) (within the range of up to 26 display outputs).
• The display outputs unused for dynamic display can be used as static outputs.
• The dimmer function provides eight levels of intensity.
• Such hardware is contained that a key scan application is possible.
•
A key scan interrupt (IRQKS) is caused. (A key scan timing is detected.)
•
Key scan data can be output from key scan registers (KS0 and KS1) onto a segment output pin.
• A high-voltage output pin (40 V) is provided which can directly drive the FIP.
•
Pins dedicated to segments (S0 to S9): VOD = 40 V, IOD = 3 mA
•
Digit output pins (T0 to T15): VOD = 40 V, IOD = 15 mA
• A mask option enables a pull-down resistor to be incorporated for each bit.
Fig. 5-8 FIP Controller/Driver Block Diagram
Internal bus
Key scan
flag (KSF)
4
4
4
Display
mode
register
Digit
select
register
Dimmer
select
register
Display data memory
(64 × 4 bits)
Key scan registers
(KS0 and KS1)
Port H
12
4
Digit signal
generator
IRQKS
generation
signal
Segment data latch (16)
4
4
Selector
10
2
2
4
4
Selector
4
10
2
Output buffer with a high withstand voltage
10
2
4
10
S0-S9
T15/S10
T13/S12/PH0-
T0-T9
V
LOAD
V
PRE
and T14/S11 T10/S15/PH3
Caution The FIP controller/driver can only operate at the high and intermediate speeds (PCC = 0011B or 0010B)
of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode.
Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode
or the standby mode.
23
µPD75218
6. INTERRUPT FUNCTIONS
The µPD75218 has eight types of interrupt sources and can generate multiple interrupts with priority order.
It is also equipped with two types of test sources. INT2 is an edge detected testable input.
The µPD75218 interrupt control circuit has the following functions:
•
Hardware-controlled vectored interrupt function which can control interrupt acknowledge with the interrupt
enable flag (IE×××) and the interrupt master enable flag (IME).
•
•
•
•
Function of setting any interrupt start address.
Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).
Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.)
Standby mode release function (Interrupts to be released can be selected by interrupt enable flags.)
24
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal bus
4
2
2
2
(IME)
IPS
IST
IM1
IM0
Interrupt enable flag (IEXXX
)
Decoder
INT
IRQBT
IRQ4
BT
Both edges
detection
circuit
INT4/
P00
VRQn
Edge
INT0/
P10
Note
detection
circuit
IRQ0
Edge
INT1/
P11
Vector
table
address
generator
circuit
Note
IRQ1
detection
circuit
Priority control
circuit
INTSIO
IRQSIO
IRQT0
IRQTPG
IRQKS
IRQW
IRQ2
INTT0
INTTPG
INTKS
INTW
Standby release
signal
Rising edge
detection
circuit
INT2/
P12
Note Noise eliminator
µ
µPD75218
7. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the µPD75218 to decrease power consump-
tion in the program standby mode.
Table 7-1 Operation Status in Standby Mode
HALT mode
HALT instruction
STOP mode
STOP instruction
Set instruction
Setting enabled only for main system
clock
Setting enabled for either main system
clock or subsystem clock
System clock when set
Oscillator stops only for main system
clock
Stops only for CPU clock Φ (oscillation
Clock oscillator
continued)
Operation stopped
Operation continued (IRQBT set at reference
time intervals)
Basic interval timer
Serial interface
Operation enabled only when external
SCK input is selected for serial clock
Operation enabled when serial clock other
than Φ is specified
Operation enabled only when TI0 pin
input is specified for count clock
Operation enabled
Timer/event counter
Operation stopped
Operation enabled
Timer/pulse generator
Watch timer
Operation enabled only fXT is selected for Operation enabled
count clock
Operation disabled (display off mode set before disabling)
Operation stopped
FIP controller/driver
CPU
Interrupt request signals (except INT0, INT1, and INT2) from operable hardware
enabled by interrupt enable flags, or RESET input.
Release signal
26
µPD75218
8. RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig. 8-1.
Fig. 8-1 Reset Signal Generator
Internal reset signal
(RES)
RESET
Fig. 8-2 shows the reset operation.
Fig. 8-2 Reset Operation by RESET Input
Wait
(21.8 ms/when the microcomputer
operates at 6.0 MHz)Note
RESET input
Normal operation
mode
Normal operation mode or
standby mode
HALT mode
Internal reset operation
Note 31.3 ms when the microcomputer operates at 4.19 MHz
Table 8-1 lists the hardware statuses after reset operation.
27
µPD75218
Table 8-1 Hardware Statuses after Reset Operation
RESET input in standby mode
Hardware
Program counter (PC)
RESET input during operation
Set the low-order six bits at
address 0000H in program
memory to PC13-8, set the
contents of address 0001H to
PC7-0, and set PC14 to zero.
Set the low-order six bits at
address 0000H in program
memory to PC13-8, set the
contents of address 0001H to
PC7-0, and set PC14 to zero.
PSW Carry flag (CY)
Skip flag (SK0-SK2)
Retained
Undefined
0
0
0
0
Interrupt status flag (IST0, IST1)
Bank enable flag (MBE, RBE)
Set bit 6 of address 0000H in
program memory to RBE and
set bit 7 to MBE.
Set bit 6 of address 0000H in
program memory to RBE and
set bit 7 to MBE.
Stack pointer (SP)
Undefined
Undefined
Undefined
Stack bank selection register (SBS)
Data memory (RAM)
Undefined
Note
Retained
Undefined
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Basic interval timer Counter (BT)
Mode register (BTM)
Retained
Undefined
0, 0
0, 0
Undefined
Undefined
0
0
Timer/event counter
0
0
Counter (T0)
FFH
FFH
Modulo register (TMOD0)
Mode register (TM0)
Modulo register (MODH, MODL)
Mode register (TPGM)
Mode register (WM)
Shift register (SIO)
0
0
Timer/pulse
generator
Retained
Undefined
0
0
0
Clock timer
0
Serial interface
Retained
Undefined
Set bit 4 to 1 and other bits to 0. Set bit 4 to 1 and other bits to 0.
Mode register (SIOM)
Clock generator
Interrupt
0
0
Processor clock control
register (PCC)
0
0
System clock control register
(SCC)
Reset (0)
Reset (0)
Interrupt request flag (IRQ×××)
Interrupt enable flag (IE×××)
Priority specification flag (IPS)
0
0
0
0
0, 0
0, 0
INT0/INT1 mode register (IM0,
IM1)
Digital port
PORT H
Off
Off
Output buffer
Output latch
Cleared (0)
Cleared (0)
0
Retained
0
0
I/O mode register (PMGA, PMGB)
Output latch
Undefined
0
1000B
0
FIP controller/driver Display mode register (DSPM)
Digit selection register (DIGS)
Dimmer selection register (DIMS)
Display data memory
1000B
0
Retained
Off
Undefined
Off
Output buffer
Note Data from address 0F8H to address 0FDH in the data memory becomes undefined by RESET input.
28
µPD75218
9. INSTRUCTION SET
(1) Representation format and description method of operands
An operand is described in the operand field of each instruction according to the description method
corresponding to the operand representation format of the instruction (refer to "RA75X Assembler Package
User's Manual, Language" (EEU-1363) for details). When two or more elements are described in the
description method field, select one of them. Uppercase letters, a plus sign (+), and a minus sign (-) are
keywords, so they can be used without alteration.
Specify an appropriate numeric value or label for immediate data.
Representa-
Description method
tion format
reg
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
reg1
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
BC, DE, HL, XA’, BC’, DE’, HL’
HL, HL+, HL-, DE, DL
DE, DL
rp’1
rpa
rpa1
n4
4-bit immediate data or label
8-bit immediate data or label
n8
Note
mem
bit
8-bit immediate data or label
2-bit immediate data or label
fmem
pmem
addr1
addr
caddr
faddr
taddr
PORTn
IE×××
RBn
MBn
FB0H-FBFH/FF0H-FFFH immediate data or label
FC0H-FFFH immediate data or label
0000H-7F7FH immediate data or label
0000H-3F7FH immediate data or label
12-bit immediate data or label
11-bit immediate data or label
20H-7FH immediate data (bit 0 = 0) or label
PORT0-PORT6
IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4
RB0-RB3
MB0, MB1, MB2, MB3, MB15
Note Only even addresses can be specified for 8-bit data processing.
29
µPD75218
(2) Legend
A
: A register, 4-bit accumulator
: B register, 4-bit accumulator
: C register, 4-bit accumulator
: D register, 4-bit accumulator
: E register, 4-bit accumulator
: H register, 4-bit accumulator
: L register, 4-bit accumulator
: X register, 4-bit accumulator
: Register pair (XA), 8-bit accumulator
: Register pair (BC), 8-bit accumulator
: Register pair (DE), 8-bit accumulator
: Register pair (HL), 8-bit accumulator
: Extended register pair (XA’)
: Extended register pair (BC’)
: Extended register pair (DE’)
: Extended register pair (HL’)
: Program counter
B
C
D
E
H
L
X
XA
BC
DE
HL
XA’
BC’
DE’
HL’
PC
SP
CY
: Stack pointer
: Carry flag, bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn: Port n (n = 0 to 6)
IME
IPS
: Interrupt master enable flag
: Interrupt priority specification register
IE××× : Interrupt enable flag
RBS : Register bank select register
MBS : Memory bank select register
PCC : Processor clock control register
.
: Address/bit delimiter
: Contents addressed by ××
: Hexadecimal data
(××)
××H
30
µPD75218
(3) Explanation of the symbols in the addressing area field
MB = MBE•MBS
*1
(MBS = 0, 1, 2, 3, or 15)
MB = 0
*2
*3
MBE = 0: MB = 0 (00H-7FH)
MB = 15 (80H-FFH)
Data memory
addressing
MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15)
MB = 15, fmem = FB0H-FBFH or
FF0H-FFFH
*4
MB = 15, pmem = FC0H-FFFH
addr = 0000H-3F7FH
*5
*6
*7
addr = (Current PC) - 15 to (Current PC) - 1 or
(Current PC) + 2 to (Current PC) + 16
caddr = 0000H-0FFFH (PC14,13,12 = 000B) or
1000H-1FFFH (PC14,13,12 = 001B) or
2000H-2FFFH (PC14,13,12 = 010B) or
3000H-3FFFH (PC14,13,12 = 011B) or
4000H-4FFFH (PC14,13,12 = 100B) or
5000H-5FFFH (PC14,13,12 = 101B) or
6000H-6FFFH (PC14,13,12 = 110B) or
7000H-7F7FH (PC14,13,12 = 111B)
*8
Program
memory
addressing
faddr = 0000H-07FFH
taddr = 0020H-007FH
addr1 = 0000H-7F7FH
*9
*10
*11
Remarks 1. MB indicates an accessible memory bank.
2. For *2, MB is always 0 irrespective of MBE and MBS.
3. For *4 and *5, MB is always 15 irrespective of MBE and MBS.
4. *6 to *11 indicate each addressable area.
(4) Explanation of the machine cycle column
S represents the number of machine cycles required when a skip instruction with the skip function performs
a skip operation. S assumes one of the following values:
• When no skip operation is performed
: S = 0
• When a 1-byte instruction or 2-byte instruction is skipped : S = 1
• When a 3-byte instruction is skipped
: S = 2
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of the CPU clock Φ (= tCY), and three types of times are available for
selection according to the PCC setting.
31
µPD75218
Number Machine
of bytes cycle
Address- Skip
Operand
A,#n4
Mnemonic
MOV
Operation
Instruction
Transfer
ing area
condition
1
2
2
2
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
2
2
1
2
1
1
1
1
A ← n4
StringeffectA
1
reg1,#n4
XA,#n8
reg1 ← n4
XA ← n8
HL ← n8
rp2 ← n8
A ← (HL)
2
StringeffectA
Stringeffect B
2
HL,#n8
2
rp2,#n8
A,@HL
2
1
*1
*1
*1
*2
*1
*1
*1
*3
*3
*3
*3
A,@HL+
A,@HL-
A,@rpa1
XA,@HL
@HL,A
A ← (HL), then L ← L + 1
A ← (HL), then L ← L - 1
A ← (rpa1)
L = 0
2 + S
L = FH
2 + S
1
XA ← (HL)
2
(HL) ← A
1
@HL,XA
A,mem
(HL) ← XA
2
A ← (mem)
2
XA,mem
mem,A
XA ← (mem)
(mem) ← A
2
2
mem,XA
A,reg
(mem) ← XA
A ← reg
2
2
XA,rp’
XA ← rp’
2
reg1,A
reg1 ← A
2
rp’1,XA
A,@HL
rp’1 ← XA
2
XCH
A ↔ (HL)
1
*1
*1
*1
*2
*1
*3
*3
A,@HL+
A,@HL-
A,@rpa1
XA,@HL
A,mem
A ↔ (HL), then L ← L + 1
A ↔ (HL), then L ← L - 1
A ↔ (rpa1)
L = 0
2 + S
L = FH
2 + S
1
2
2
2
1
2
3
3
3
3
XA ↔ (HL)
A ↔ (mem)
XA,mem
A,reg1
XA ↔ (mem)
A ↔ reg1
XA,rp’
XA ↔ rp’
MOVT
XA,@PCDE
XA,@PCXA
XA, @BCDE
XA, @BCXA
XA ← (PC14-8+DE)ROM
XA ← (PC14-8+XA)ROM
XA ← (BCDE)ROM
XA ← (BCXA)ROM
Table
reference
*11
*11
32
µPD75218
Number Machine
of bytes cycle
Address- Skip
Operand
Mnemonic
MOV1
Operation
CY ← (fmem.bit)
Instruction
ing area
condition
CY,fmem.bit
CY,pmem.@L
CY,@H+mem.bit
fmem.bit,CY
pmem.@L,CY
@H+mem.bit,CY
A,#n4
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
*4
2
Bit
transfer
*5
2
CY ← (pmem7-2+L3-2.bit(L1-0))
CY ← (H+mem3-0.bit)
(fmem.bit) ← CY
*1
2
2
*4
*5
2
(pmem7-2+L3-2.bit(L1-0)) ← CY
(H+mem3-0.bit) ← CY
A ← A + n4
2
*1
carry
carry
carry
carry
carry
ADDS
1 + S
Arithme-
tic/logical
XA,#n8
A,@HL
2 + S
XA ← XA + n8
*1
*1
*1
*1
1 + S
A ← A + (HL)
XA,rp’
2 + S
XA ← XA + rp’
rp’1,XA
A,@HL
2 + S
rp’1 ← rp’1 + XA
ADDC
SUBS
SUBC
AND
1
A,CY ← A + (HL) + CY
XA,CY ← XA + rp’ + CY
rp’1,CY ← rp’1 + XA + CY
A ← A - (HL)
XA,rp’
2
rp’1,XA
A,@HL
2
borrow
borrow
borrow
1 + S
XA,rp’
2 + S
XA ← XA - rp’
rp’1,XA
A,@HL
2 + S
rp’1 ← rp’1 - XA
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
A,CY ← A - (HL) - CY
XA,CY ← XA - rp’ - CY
rp’1,CY ← rp’1 - XA - CY
XA,rp’
rp’1,XA
A,#n4
A ← A
n4
A,@HL
*1
*1
*1
A ← A
(HL)
XA,rp’
XA ← XA
rp’
XA
rp’1,XA
A,#n4
rp’1 ← rp’1
OR
A ← A
n4
(HL)
rp’
XA
A,@HL
A ← A
XA,rp’
XA ← XA
rp’1 ← rp’1
rp’1,XA
A,#n4
XOR
A ← A
n4
(HL)
A,@HL
A ← A
XA,rp’
XA ← XA
rp’1 ← rp’1
rp’
XA
rp’1,XA
A
Accumula-
tor manipu-
lation
RORC
NOT
CY ← A0, A3 ← CY, An-1 ← An
A ← A
A
33
µPD75218
Number
of bytes
Machine
cycle
Address- Skip
Operand
Mnemonic
INCS
Operation
reg ← reg + 1
Instruction
ing area
condition
reg = 0
1 + S
1 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1 + S
2 + S
2 + S
2 + S
1
reg
rp1
1
1
2
2
1
2
2
2
1
2
2
2
1
1
1
1
Increment/
decrement
rp1 = 00H
(HL) = 0
rp1 ← rp1 + 1
(HL) ← (HL) + 1
(mem) ← (mem) + 1
reg ← reg - 1
rp’ ← rp’ - 1
Skip if reg = n4
Skip if (HL) = n4
Skip if A = (HL)
Skip if XA = (HL)
Skip if A = reg
Skip if XA = rp’
CY ← 1
@HL
mem
reg
*1
*3
(mem) = 0
reg = FH
rp’ = FFH
reg = n4
(HL) = n4
A = (HL)
XA = (HL)
A = reg
DECS
SKE
rp’
reg,#n4
@HL,#n4
A,@HL
XA,@HL
A,reg
XA,rp’
CY
Compari-
son
*1
*1
*1
XA = rp’
SET1
CLR1
SKT
Carry flag
manipula-
tion
1
CY ← 0
CY
CY = 1
1 + S
1
Skip if CY = 1
CY ← CY
CY
NOT1
CY
34
µPD75218
Number
of bytes
Machine
cycle
Address- Skip
Operand
mem.bit
Mnemonic
SET1
Operation
(mem.bit) ← 1
Instruction
ing area
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*11
condition
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
2
Memory
bit
(fmem.bit) ← 1
fmem.bit
2
manipula-
tion
(pmem7-2+L3-2.bit(L1-0)) ← 1
(H+mem3-0.bit) ← 1
pmem.@L
2
@H+mem.bit
mem.bit
2
(mem.bit) ← 0
CLR1
SKT
SKF
2
2
(fmem.bit) ← 0
fmem.bit
(pmem7-2+L3-2.bit(L1-0)) ← 0
(H+mem3-0.bit) ← 0
pmem.@L
2
2
@H+mem.bit
mem.bit
Skip if (mem.bit) = 1
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H+mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
Skip if (fmem.bit) = 1
fmem.bit
Skip if (pmem7-2+L3-2.bit(L1-0)) = 1
Skip if (H+mem3-0.bit) = 1
Skip if (mem.bit) = 0
pmem.@L
@H+mem.bit
mem.bit
Skip if (fmem.bit) = 0
fmem.bit
Skip if (pmem7-2+L3-2.bit(L1-0)) = 0
Skip if (H+mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
Skip if (H+mem3-0.bit) = 1 and clear
pmem.@L
@H+mem.bit
fmem.bit
SKTCLR
AND1
OR1
pmem.@L
@H+mem.bit
CY,fmem.bit
CY,pmem.@L
CY,@H+mem.bit
CY,fmem.bit
CY,pmem.@L
CY,@H+mem.bit
CY,fmem.bit
CY,pmem.@L
CY,@H+mem.bit
addr1
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
(fmem.bit)
(pmem7-2+L3-2.bit(L1-0))
(H+mem3-0.bit)
(fmem.bit)
2
2
2
(pmem7-2+L3-2.bit(L1-0))
(H+mem3-0.bit)
(fmem.bit)
2
2
XOR1
BR
2
(pmem7-2+L3-2.bit(L1-0))
(H+mem3-0.bit)
2
2
PC14-0 ← addr1
—
Branch
(The assembler selects an appropri-
ate instruction from the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr
instructions.)
PC14-0 ← addr
$addr
!addr
PCDE
PCXA
BCDE
BCXA
!addr1
!caddr
1
3
2
2
2
2
3
2
2
3
3
3
3
3
3
2
*7
*6
PC14 ← 0, PC13-0 ← !addr
PC14-0 ← PC14-8 + DE
PC14-0 ← PC14-8 + XA
PC14-0 ← BCDE
PC14-0 ← BCXA
PC14-0 ← !addr1
BRA
*11
*8
PC14-0 ← PC14,13,12 + caddr11-0
BRCB
35
µPD75218
Number Machine
of bytes cycle
Address- Skip
Operand
!addr
Mnemonic
CALL
Operation
Instruction
ing area
condition
Subrou-
tine stack
control
3
3
2
1
1
4
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
*6
PC14 ← 0, PC13-0 ← addr, SP ← SP - 6
3
3
CALLA
CALLF
RET
!addr1
!faddr
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
*11
*9
PC14-0 ← addr1, SP ← SP - 6
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
PC14-0 ← 0000, faddr, SP ← SP - 6
3
×,×,MBE,RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
×,PC14,PC13,PC12 ← (SP+1)
SP ← SP + 6
Uncondition-
ally
RETS
3 + S
×,×,MBE,RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
×,PC14,PC13,PC12 ← (SP+1)
SP ← SP + 6
then skip unconditionally
RETI
1
3
×,PC14,PC13,PC12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP + 6
PUSH
1
2
1
2
(SP-1)(SP-2) ← rp, SP ← SP - 2
rp
BS
(SP-1) ← MBS, (SP-2) ← RBS, SP ←
SP - 2
POP
rp
1
2
1
2
rp ← (SP+1)(SP), SP ← SP + 2
MBS ← (SP+1), RBS ← (SP), SP ←
BS
SP + 2
Interrupt
control
EI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IME(IPS.3) ← 1
IE××× ← 1
IE×××
DI
IME(IPS.3) ← 0
IE××× ← 0
IE×××
Note
IN
A,PORTn
XA,PORTn
PORTn,A
PORTn,XA
A ← PORTn (n=0 to 6)
XA ← PORTn+1,PORTn (n=4)
PORTn ← A (n=2 to 6)
PORTn+1,PORTn ← XA (n=4)
I/O
Note
OUT
Note MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.
36
µPD75218
Number Machine
of bytes cycle
Address- Skip
Operand
Mnemonic
Operation
Instruction
ing area
condition
Set HALT mode (PCC.2 ← 1)
Set STOP mode (PCC.3 ← 1)
No operation
2
2
1
2
2
1
2
2
1
2
2
3
HALT
STOP
NOP
SEL
CPU
control
RBS ← n (n=0-3)
RBn
Special
MBS ← n (n=0,1,2,3,15)
MBn
Note
• For a TBR instruction
PC13-0 ← (taddr)5-0 + (taddr+1)
PC14 ← 0
*10
GETI
taddr
• For a TCALL instruction
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0, PC14, PC13, PC12
(SP-2) ← ×,×,MBE,RBE
4
PC13-0 ← (taddr)5-0 + (taddr+1)
SP ← SP-6 PC14 ← 0
Depends
• For an instruction other than TBR
and TCALL
3
upon the
referenced
instruction.
Executes the instruction in
(taddr)(taddr+1).
Note The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI
instructions.
37
µPD75218
10. MASK OPTION SELECTION
The µPD75218 has the following mask options enabling or disabling on-chip components.
Pin
Mask option
Pull-up resistor incorporation enabled in bit units
P60 to P63
T0/T9
T10/S15/PH3 to T13/S12/PH0
T14/S11, T15/S10
S0 to S9
XT1, XT2
The feedback resistor for the subsystem clock oscillator can be
removed
Cautions 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by
removing the feedback resistor from the oscillator.
2. The feedback resistor must be incorporated when the subsystem clock is used.
38
µPD75218
11. APPLICATION BLOCK DIAGRAM
11.1 VCR TIMER TUNER
Main power supply
Power
+
V
Super capacitor
V
DD
SS
failure
INT4
PPO
10
T0–T9
detection
Fluorescent indication panel (FIP)
LPF
S0–S15 16
Electronic
tuner
16 segments × 10 digits
µ
PD75218
Timer
Tuner
Remote-
controller
signal
reception
Tape counter
Tape count pulse
Tape up/down
INT1
Key matrix
(16 × 4)
PORT6
INT0
SCK
SCK
SO
System
controller
SO
SI
microcomputer
Remote-controller
signal
µPD75104 or µPD75106
µPC2800A
EEPROM™
µPD6252
µPD6253
µPD6254
BUZ
XT2
BZ
Piezoelectric buzzer
X1
X2
XT1
39
µPD75218
11.2 COMPACT DISK PLAYER
14
T0–T13
SIO
SCK
SI/SO
Servo
control IC
Fluorescent indication panel (FIP)
S0–S11 12
12 segments × 14 digits
Loading
circuit
µPD75218
Key matrix
(12 × 4)
PORT6
INT0
BUZ
BZ
Remote-controller
signal
µPC2800A
X1
X2
40
µPD75218
11.3 ECR
Main power supply
+
VDD
VSS
Power
failure
INT4
16
T0–T15
detection
Fluorescent indication panel (FIP)
S0–S9 10
10 segments × 16 digits
RAM
µ
PD75218
Key matrix
(10 × 4)
Printer
PPO
XT2
BZ
X1
X2
XT1
41
µPD75218
★
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
Parameter
Symbol
Conditions
Rating
Unit
–0.3 to +7.0
V
V
VDD
VLOAD
VPRE
VI
VDD – 40 to VDD + 0.3
Power supply voltage
VDD – 11 to VDD + 0.3
V
–0.3 to VDD + 0.3
V
Input voltage
–0.3 to VDD + 0.3
V
VO
Pins except display output pins
Display output pins
Output voltage
VDD – 40 to VDD + 0.3
V
VOD
–15
–15
mA
mA
mA
mA
mA
mA
mA
mW
mW
°C
Per pin except display output pins
Per pin for S0 to S9
–30
Output high current
Output low current
IOH
Per pin for T0 to T15
Total of pins except display output pins
Total of display output pins
Per pin
–20
–120
17
IOL
PT
60
Total of pins
450
Plastic QFP
Note 1
Total loss
600
Plastic shrink DIP
Topt
Tstg
–40 to +85
–65 to +150
Operatingtemperature
Storage temperature
°C
OPERATING SUPPLY VOLTAGE (Ta = –40 to +85 °C)
Min.
Max.
Parameter
Conditions
Unit
Note 2
Note 3
4.5
V
V
V
V
CPU
6.0
6.0
6.0
6.0
Display controller
4.5
Timer/pulse generator
Note 2
2.7
Other hardware
42
µPD75218
Notes 1. Calculation of total loss
Design so that the sum of the following three power consumption values for the µPD75218CW/GF will be
less than the total loss PT (It is recommended to use the system with 80 % or less of the rating).
➀
➁
CPU loss
: Given as VDD (Max.) × IDD1 (Max.)
Output pin loss
: There are normal output pin loss and display output pin loss. It is necessary
to add a loss derived from the flow of maximum current to each output pin.
➂
Pull-down register loss: Power loss due to a pull-down resistor incorporated in the display output
pin by mask option.
Example Suppose 4-LED output with 9 segments and 11 digits, VDD = 5 V + 10 % and 4.19 MHz oscillation and let
a maximum of 3 mA, 15 mA and, 10 mA flow to a segment pin, timing pin and LED output pin, respectively.
Further, let the voltage of fluorescent display tube (VLOAD voltage) be –30 V and normal voltage be small.
➀
➁
CPU loss : 5.5 V × 9.0 mA = 49.5 mW
Pin loss : Segment pin ..... 2 V × 3 mA × 9 = 54 mW
Timing pin ......... 2 V × 15 mA = 30 mW
10
× 2 V × 10 mA × 4 = 53 mW
LED output ........
15
(30 + 5.5 V)2
➂
Pull-down resistor loss ........
× 10 = 504.1 mW
25 kΩ
PT = ➀ + ➁ + ➂ = 690.6 mW
In this example, the power consumption of 690.6 mW is higher than the allowable total loss for the shrink
DIP package (600 mW). It is necessary to decrease power consumption by decreasing the number of on-
chip pull-down resistors. In this example, power consumption can be adjusted to 577.8 mW by
incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally
mounting pull-down resistors to the 2 remaining segment outputs.
2. Except the system clock oscillator, display controller and timer/pulse generator.
3. The operating voltage range varies depending on the cycle time. Refer to the AC characteristics.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
Unit
Max.
Parameter
Symbol
Conditions
Min.
Typ.
Input capacitance
CIN
pF
pF
pF
pF
15
15
35
15
Except display output
Display output
f = 1 MHz
0 V for pins other than pins
to be measured
Output capacitance
Input /output capacitance
COUT
CIO
43
µPD75218
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
constants
Resonator
Ceramic
resonator
Note 3
Parameter
Min.
2.0
Max.
6.2
Typ.
Unit
MHz
Conditions
VDD = Oscillation
voltage range
Oscillator
frequency
X1
X2
Note 1
(fXX)
4
ms
Oscillation
settling time
Note 2
After VDD reaches
Min. of the oscilla-
tion voltage range
C1
C1
C2
C2
6.2
MHz
4.19
2.0
Crystal
resonator
Note 3
Oscillator
frequency
X1
X2
Note 1
(fXX)
10
30
ms
ms
Oscillation
settling time
Note 2
VDD = 4.5 to 6.0 V
2.0
MHz
External
clock
X1 input
6.2
frequency
X1
X2
Note 1
(fX)
ns
100
X1 input
high/low
level width
(tXH, tXL)
250
µPD74HCU04
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item
of AC characteristics for the instruction execution time.
2. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min.
of the oscillation voltage range or after the STOP mode is released.
3. See "Recommended Parameters for the Oscillation Circuit" for the resonators.
Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the
portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity.
•
•
The wiring must be as short as possible.
Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be
kept away as far as possible.
•
•
The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It
must not be grounded to ground patterns carrying a large current.
No signal must be taken from the oscillator.
44
µPD75218
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
constants
Resonator
Crystal
resonator
Note 3
Conditions
Parameter
Min.
32
Typ.
Max.
35
Unit
kHz
Oscillator
frequency
32.768
XT1
XT2
Note 1
(fXT)
330 kΩ
Oscillation
settling time
Note 2
VDD = 4.5 to 6.0 V
1.0
2
s
s
C3
C4
10
V
DD
XT1 input
frequency
(fXT)
32
10
kHz
External
clock
100
32
XT1
XT2
Leave open
XT1 input
high/low
µs
level width
(tXTH, tXTL)
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item
of AC characteristics for the instruction execution time.
2. The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min.
of the oscillation voltage range.
3. Recommended resonators are listed on the next page.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the
portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity.
•
•
The wiring must be as short as possible.
Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be
kept away as far as possible.
•
•
The grounding point of the capacitor of the oscillator must have the same potential as that of VDD.
It must not be grounded to ground patterns carrying a large current.
No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator
has low amplification to minimize current consumption and is more likely to malfunction due to noise
than the main system clock oscillator.
45
µPD75218
RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT
When a ceramic resonator is used for the main system clock (Ta = -40 to +70 ˚C)
External capacitance Oscillation voltage
Manu-
facturer
Oscillation frequency
(MHz)
(pF)
range (V)
Product name
Min.
C1
C2
30
Max.
6.0
Murata
Mfg.
CSA×××MG
2.00 to 2.44
2.45 to 3.50
2.51 to 6.00
2.45 to 3.50
2.51 to 6.00
30
Built-in
30
2.7
CST×××MG
Built-in
30
CSA×××MG093
CST×××MGW093
CSA×××MGU
CST×××MGWU
CSA×××MG
Built-in
30
Built-in
30
Built-in
30
Built-in
30
3.0
3.3
CST×××MGW
CSA×××MG
Built-in
30
Built-in
30
CST×××MGW
Built-in
Built-in
When a ceramic resonator is used for the main system clock (Ta = -20 to +80 ˚C)
External capacitance Oscillation voltage
Manu-
facturer
Oscillation frequency
(MHz)
(pF)
range (V)
Product name
Min.
C1
C2
47
Max.
6.0
Kyocera
KBR-2.0MS
2.0
4.0
47
33
2.7
KBR-4.0MWS
KBR-4.19MWS
KBR-4.19MSA
KBR-4.19MKS
PBRC 4.19A
33
4.19
Built-in
33
Built-in
33
Built-in
33
Built-in
33
KBR-6.0MWS
KBR-6.0MSA
KBR-6.0MKS
PBRC 6.00A
6.0
Built-in
33
Built-in
33
Built-in
33
Built-in
33
When a crystal resonator is used for the main system clock (Ta = -20 to +70 ˚C)
External capacitance Oscillation voltage
Oscillation frequency
(MHz)
Manu-
facturer
(pF)
C1
18
range (V)
Min.
Product name
HC-49/U-S
C2
18
Max.
6.0
Kinseki
3.072 to 6.000
2.7
When a crystal resonator is used for the subsystem clock (Ta = -15 to +60 ˚C)
External capacitance and
Oscillation voltage
range (V)
Oscillation
frequency (MHz)
Manu-
resistance
C1 (pF) C2 (pF)
18 18
Product name
KF-38G
facturer
Min.
R (kΩ)
Max.
6.0
Kyocera
32.768
220
4.0
Caution When finely adjusting the oscillation frequency of a crystal resonator, adjust external capacitance C1 or
C3.
46
µPD75218
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Conditions
Min.
Unit
Typ.
Max.
VIH1
VIH2
VIH3
VIH4
0.7VDD
0.75VDD
VDD–0.4
0.65VDD
0.7VDD
0
Input high voltage
Except below
Ports 0, 1, RESET
X1, X2, XT1
Port 6
V
V
VDD
VDD
V
VDD
VDD = 4.5 to 6.0 V
V
VDD
V
VDD
Except below
VIL1
VIL2
VIL3
V
0.3VDD
0.2VDD
0.4
Input low voltage
Ports 0, 1, 6, RESET
X1, X2, XT1
0
V
0
V
VDD = 4.5 to 6.0 V, IOH = –1 mA VDD–1.0
V
Output high voltage
Output low voltage
VOH
All output pins
IOH = –100 µA
VDD = 4.5 to 6.0 V, IOL = 15 mA
VDD = 4.5 to 6.0 V, IOL = 1.6 mA
IOL = 400 µA
VDD–0.5
V
Ports 4, 5
VOL
V
2.0
0.4
0.5
3
0.5
All output pins
V
V
ILIH1
ILIH2
ILIL1
ILIL2
ILOH
ILOL1
ILOL2
Input high leakage
current
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
kΩ
kΩ
kΩ
mA
mA
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
Except X1,X2,XT1
X1, X2, XT1
VIN = VDD
20
–3
Input low leakage
current
Except X1,X2,XT1
VIN = 0 V
–20
3
X1, X2, XT1
VOUT = VDD
VOUT = 0 V
Output high leakage current
All output pins
Output low leakage
current
Except display output
Display output
S0 to S9
–3
–10
VOUT = VLOAD = VDD – 35 V
VPRE = VDD – 9 ±1 VNote 1
–3
–1.5
–15
–7
VDD =
IOD
–5.5
–3.5
–22
–15
80
Display output current
4.5 to 6.0 V
VOD =
VPRE = 0 V
VPRE = VDD – 9 ±1 VNote 1
T0 to T15
VDD – 2 V
VPRE = 0 V
RP6
20
Port 6
VIN = VDD
VDD = 4.5 to 6.0 V
200
1000
135
13.5
1.8
Built-in pull-down
resistor (mask option)
20
RL
Display output
25
VOD – VLOAD = 35 V
70
4.0
0.55
600
200
3.0
0.45
550
180
40
Note 3
Note 4
Note 2
IDD1
6.0 MHz crys-
tal oscillation
C1 = C2 = 15pF
VDD = 5 V ±10 %
VDD = 3 V ±10 %
Supply current
VDD = 5 V ±10 %
VDD = 3 V ±10 %
Note 3
1800
600
9.0
IDD2
IDD1
IDD2
HALT mode
VDD = 5 V ±10 %
4.19 MHz crys-
tal oscillation
C1 = C2 = 15pF
Note 4
VDD = 4 V ±10 %
1.5
1800
600
120
15
HALT mode VDD = 5 V ±10 %
VDD = 3 V ±10 %
IDD3
IDD4
VDD = 3 V ±10 %
32 kHz crystal
oscillationNote 5
HALT mode VDD = 3 V ±10 %
5
IDD5
XT1 = 0 V
STOP mode
VDD = 5 V ±10 %
VDD = 3 V ±10 %
20
0.5
0.1
10
47
µPD75218
Notes 1. The following external circuit is recommended.
µPD75218
+5 V
VDD
RD9. 1EL
RD9. 1EL : Zener diode (NEC)
VPRE
Zener voltage = 8.29 to 9.30 V
68 kΩ
VLOAD
–30 V
VSS
2. Current to the on-chip pull-down resistor (mask option) is not included.
3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode.
4. When the PCC register is set to 0000 and is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock
with main system clock oscillation stopped.
48
µPD75218
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)
Parameter
Symbol
tCY
Conditions
VDD = 4.5 to 6.0 V
Min.
0.67
Typ.
122
Max.
Unit
µs
µs
µs
32
32
Operation with main
system clock
CPU clock cycle time
(minimum instruction
execution time = 1
2.6
114
125
Operation with sub-
system clock
Note 1
machine cycle)
VDD = 4.5 to 6.0 V
MHz
kHz
µs
0.6
0
0
fTI
TI0 input frequency
165
tTIH,
tTIL
0.83
3
TI0 input high and low-
level widths
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
µs
Input
SCK cycle time
0.8
0.95
tKCY
µs
µs
Output
Input
µs
3.2
3.8
0.4
µs
Output
µs
tKH,
tKL
VDD = 4.5 to 6.0 V
Input
SCK high and low-level
widths
ns
µs
Output
Input
tKCY/2–50
1.6
Output
ns
ns
t
KCY/2–150
tSIK
tKSI
100
SI setup time (referred to
SCK↑)
SI hold time (referred to
ns
400
SCK↑)
VDD = 4.5 to 6.0 V
300
Delay from SCK↓ to SO
output
tKSO
ns
ns
µs
µs
µs
1000
Note 2
Interrupt input high and
low-level widths
tINTH,
tINTL
INT0
INT1
2tCY
10
INT2,
INT4
RESET low-level width
10
µs
tRSL
t
CY VS
V
DD
Notes 1. CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resona-
tor, the system clock control register (SCC)
and the processor clock control register (PCC).
The cycle time tCY characteristics for power
supply voltage VDD when the main system
clock is in operation is shown on the right.
2. 2tCY or 128/fXX is set by interrupt mode register
(IM0) setting.
(Operation with main system clock)
40
32
30
6
5
Guaranteed operation
range
4
3
µ
2
1
0.5
0
1
2
3
4
5
6
Power supply voltage VDD [V]
49
µPD75218
AC Timing Measurement Values (Except X1 and XT1 Inputs)
0.75VDD
Test points
0.2VDD
0.75VDD
0.2VDD
Clock Timing
1/fX
t
XL
t
XH
X1 input
VDD - 0.4 V
0.4 V
1/fXT
t
XTL
t
XTH
XT1 input
VDD - 0.4 V
0.4 V
TI0 Timing
1/fTI
t
TIL
t
TIH
TI0
50
µPD75218
Serial Transfer Timing
tKCY
tKH
t
KL
SCK
t
SIK
tKSI
SI
Input data
t
KSO
SO
Output data
Interrupt Input Timing
tINTL
tINTH
INT0, INT1,
INT2 and INT4
RESET Input Timing
tRSL
RESET
51
µPD75218
DATA RETENTION CHARACTERISTICS FOR DATA MEMORY AT LOW SUPPLY VOLTAGE IN STOP MODE
(Ta = –40 to +85 °C)
Parameter
Symbol
Conditions
Min.
2.0
Typ.
Max.
Unit
Data retention supply voltage
6.0
10
V
VDDDR
IDDDR
tSREL
Note 1
Data retention supply current
VDDDR = 2.0 V
0.1
µA
µs
Release signal set time
0
17
Note 2
tWAIT
Release by RESET
2
/fX
ms
ms
Oscillation settling time
Release by interrupt request
Note 3
Notes 1. Current to the on-chip pull-down resistor (mask option) is not included.
2. Oscillation settling time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
3. According to the setting of the basic interval timer mode register (BTM) (See below.)
BTM3
—
BTM2
BTM1
BTM0
Settling time (values at fXX = 6.0 MHz in parentheses)
20
0
0
1
1
0
1
0
1
0
1
1
1
2
2
2
2
/fXX (approx. 175 ms)
/fXX (approx. 21.8 ms)
/fXX (approx. 5.46 ms)
/fXX (approx. 1.37 ms)
17
15
13
—
—
—
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Normal operation
mode
STOP mode
Data retention mode
V
DD
t
SREL
VDDDR
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Normal operation
mode
STOP mode
Data retention mode
V
DD
t
SREL
V
DDDR
STOP instruction execution
Standby release signal
(Interrupt request)
t
WAIT
52
µPD75218
★
13. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs VDD (Main system clock: 6.0 MHz)
(T
a = 25 ˚C)
PCC = 0011
PCC = 0010
5000
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
500
µ
Subsystem clock
Normal operation
mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation
Subsystem clock
HALT mode
10
5
X1
X2 XT1
XT2
Crystal
Crystal
resonator
6.0 MHz
resonator
32.768 kHz
330 kΩ
15 pF
15 pF
15 pF
15 pF
1
0
1
2
3
4
5
6
7
Supply voltage
VDD (V)
53
µPD75218
IDD vs VDD (Main system clock: 4.19 MHz)
(Ta = 25 ˚C)
5000
PCC = 0011
PCC = 0010
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
500
µ
Subsystem clock
Normal operation
mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation
Subsystem clock
HALT mode
10
5
X1
X2 XT1
XT2
Crystal
Crystal
resonator
4.19 MHz
resonator
32.768 kHz
330 kΩ
15 pF
15 pF
15 pF
15 pF
1
0
1
2
3
4
5
6
7
Supply voltage
VDD (V)
54
µPD75218
14. PACKAGE DIMENSIONS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
32
1
A
K
L
F
D
M
R
B
C
M
N
NOTE
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P64C-70-750A,C-1
55
µPD75218
64 PIN PLASTIC QFP (14×20)
A
B
detail of lead end
51
52
33
32
S
C
D
R
Q
64
1
20
19
F
H
I
M
J
G
K
L
M
P
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
23.6±0.4
20.0±0.2
14.0±0.2
0.929±0.016
+0.008
0.795
–0.009
+0.009
0.551
–0.008
D
F
17.6±0.4
1.0
0.693±0.016
0.039
G
1.0
0.039
+0.004
0.016
H
0.40±0.10
–0.005
I
0.20
0.008
J
1.0 (T.P.)
0.039 (T.P)
+0.008
0.071
K
L
1.8±0.2
0.8±0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
5°±5°
3.0 MAX.
0.004±0.004
5°±5°
0.119 MAX.
P64GF-100-3B8,3BE,3BR-2
56
µPD75218
15. RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product.
For the details of the recommended soldering conditions refer to our document SMD Surface Mount Technology
Manual(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
Table 15-1 Soldering Conditions for Surface-Mount Devices
µPD75218GF-×××-3BE: 64-pin plastic QFP (14 × 20 mm)
Soldering process
Wave soldering
Soldering conditions
Symbol
WS60-202-1
Temperature in the soldering vessel: 260 ˚C or less
Soldering time: 10 seconds or less
Number of soldering processes: 1
Pre-heating temperature: 120 ˚C max.
(package surface temperature)
Note
Exposure limit
: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
IR30-202-1
VP15-202-1
–
Infrared ray reflow
Peak package’s surface temperature: 230 ˚C
Reflow time: 30 seconds or less (at 210 ˚C or more)
Number of reflow processes: 1
Note
Exposure limit
: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
VPS
Peak package’s surface temperature: 215 ˚C
Reflow time: 40 seconds or less (at 200 ˚C or more)
Number of reflow processes: 1
Note
Exposure limit
: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
Partial heating method
Terminal temperature: 300 ˚C or less
Flow time: 3 seconds or less (one side per device)
Note Exposure limit before soldering after dry-pack package is opened.
Storage conditions: Temperature of 25 ˚C and maximum relative humidity at 65 % or less
Caution Do not apply more than a single process at once, except for "Partial heating method."
Table 15-2 Soldering Conditions for Inserted Devices
µPD75218CW-×××: 64-pin plastic shrink DIP (750 mil)
Soldering conditions
Soldering process
Temperature in the soldering vessel: 260 °C or less
Wave soldering (only for leads)
Soldering time: 10 seconds or less
Terminal temperature: 260 °C or less
Partial heating method
Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not
contact the main body of the package.
Notice
Other versions of the products are available. For these versions, the recommended reflow
soldering conditions have been mitigated as follows:
Higher peak temperature (235 °C), two-stage, and longer exposure limit.
Contact an NEC representative for details.
57
µPD75218
APPENDIX A FUNCTIONS OF µPD752×× SERIES PRODUCTS
Item
µPD75218
µPD75P218
µPD75216A
16256 × 8
512 × 4
µPD75217
24448 × 8
768 × 4
ROM
RAM
32640 × 8
1024 × 4
Instruction
cycle
0.95 µs/1.91 µs/15.3 µs (When the mi-
crocomputer operates at 4.19 MHz)
0.67 µs/1.33 µs/10.7 µs (When the micro-
computer operates at 6.0 MHz)
0.95 µs/1.91 µs/15.3 µs (When the micro-
computer operates at 4.19 MHz)
When main
system clock is
selected
122 µs (When the microcomputer operates at 32.768 kHz)
Whensub-system
clock is selected
33
8
Total number of
I/O lines
I/O lines
including
FIP dual-
function
pins and
excluding
FIP dedi-
cated pins
CMOS input
lines
20: 8 lines for driving LED
CMOS I/O lines
Port 6: Pull-down resistors contained (mask option)
Port6: Nopull-down
resistors contained
1: Timer/pulse generator output
CMOS output
lines
4 lines for driving LED: Pull-down resistors contained
(mask option)
P-ch open-drain
output with high
withstandvoltage
and high current
No pull-down
resistors contained
FIP controller/
driver
26 lines: 40 V max.
Output with high
withstand
voltage
Whether built-in pull-down resistors are used or the pins are
used as open-drain output is selected bit by bit (mask option).
S0-S8,T0-T9:
Built-in pull-down
resistors used
S9,T10-T15:
Open-drain output
9 to 16
9 to 16
Number of
segments
Number of digits
Timer
•
•
•
•
Timer/event counter
Basic interval timer
Timer/pulse generator : 14-bit PWM output is possible.
Watch timer : Buzzer output is possible.
: Watchdog timer operation is possible.
4 channels
Serial interface
MSB or LSB first can be selected. Serial bus can be configured.
External: 3, internal: 5
Vectored interrupt
Test input
External: 1, internal: 1
System clock oscillator
• When main system clock is selected:
6.0 MHz (the µPD75218 and µPD75P218 only)
4.19 MHz
2 built-in circuits
• When subsystem clock is selected: 32.768 kHz
Incorporated
(mask option)
None
Power-on reset circuit
Possible (2 V)
-40 to +85 °C
2.7 to 6.0 V
Data retention at low supply voltage
Operating temperature range
Operating supply voltage
Package
-40 to +70 °C
★
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin ceramic WQFN (the µPD75P218 only)
58
µPD75218
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for developing systems including the µPD75218:
Note 1
IE-75000-R
IE-75001-R
In-circuit emulator for the 75X series
Note 2
IE-75000-R-EM
Emulation board for the IE-75000-R and IE-75001-R
EP-75216ACW-R
EP-75216AGF-R
Emulation probe for the µPD75218CW
Emulation probe for the µPD75218GF. A 64-pin conversion socket, the EV-9200G-64, is attached
to the probe.
EV-9200G-64
PG-1500
PROM programmer
PA-75P216ACW
PA-75P218GF
PA-75P218KB
PROM programmer adapter for the µPD75P218CW. Connected to the PG-1500.
PROM programmer adapter for the µPD75P218GF. Connected to the PG-1500.
PROM programmer adapter for the µPD75P218KB. Connected to the PG-1500.
Host machine
IE control program
PG-1500 controller
TM
Note 3
• PC-9800 series (MS-DOS
Ver. 3.30 to Ver. 5.00A
Ver. 3.1)
)
TM
TM
• IBM PC/AT
(PC DOS
RA75X relocatable
assembler
Notes 1. Maintenance service only
2. Not contained in the IE-75001-R
3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A.
Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.
59
µPD75218
APPENDIX C RELATED DOCUMENTS
Documents related to the device
Document name
Document No.
User’s manual
75X series selection guide
IEU-692
IF-1027
Documents related to development tools
Document name
Document No.
IE-75000-R/IE-75001-R User’s Manual
IE-75000-R-EM User’s Manual
EP-75216ACW-R User’s Manual
EP-75216AGF-R User’s Manual
PG-1500 User’s Manual
EEU-1416
EEU-1294
EEU-1321
EEU-1309
EEU-1335
EEU-1346
Operation
Language
RA75X Assembler Package User’s Manual
EEU-1363
EEU-1291
PG-1500 Controller User’s Manual
Other related documents
Document name
Document No.
Package Manual
IEI-1213
IEI-1207
IEI-1209
IEI-1203
IEI-1201
MEI-1202
SMD Surface Mount Technology Manual
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
Guide to Quality Assurance for Semiconductor Devices
Caution The above documents may be revised without notice. Use the latest versions when you design an
application system.
60
µPD75218
Cautions on CMOS Devices
1
Countermeasures against static electricity for all MOSs
Caution When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or
storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal
cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during
assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
2
CMOS-specific handling of unused input pins
Caution Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an
intermediate-level input may be caused by noise. This allows current to flow in the CMOS
device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input
level. Since unused pins may function as output pins at unexpected times, each unused
pin should be separately connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
3
Statuses of all MOS devices at initialization
Caution The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted
in molecules, the initial status cannot be determined in the manufacture process. NEC
has no responsibility for the output statuses of pins, input and output settings, and the
contents of registers at power on. However, NEC assures operation after reset and items
for mode setting if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
61
µPD75218
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
EEPROM is a trademark of NEC Corporation.
FIP is a trademark of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are a trademarks of IBM Corporation.
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