UPD753012GC_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD753012, 753016, 753017

4-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD753017 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing

capability comparable to that of an 8-bit microcontroller.

It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with

the conventional µPD75316B, and can provide high-speed operation. It can be supplied in a small plastic TQFP

package (12 × 12 mm) and is suitable for small sets using LCD panels.

For details of functions refer to the following User’s Manual.

µPD753017 User’s Manual : U11282E

FEATURES

•

Low voltage operation: VDD = 2.2 to 5.5 V

· Can be driven by two 1.5 V batteries

On-chip memory

•

Capable of high-speed operation and variable in-

struction execution time for power saving

· 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation)

· 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation)

· 122 µs (at 32.768 kHz operation)

•

· Program memory (ROM):

12288 × 8 bits (µPD753012)

16384 × 8 bits (µPD753016)

24576 × 8 bits (µPD753017)

· Data memory (RAM):

•

Internal programmable LCD controller/driver

Small plastic TQFP (12 × 12 mm)

· Suitable for small sets such as cameras

One-time PROM: µPD75P3018

1024 × 4 bits

•

APPLICATION

Remote controllers, camera-contained VCRs, cameras, gas meters, etc.

ORDERING INFORMATION

Part number

Package

µPD753012GC-XXX-3B9

µPD753012GK-XXX-BE9

µPD753016GC-XXX-3B9

µPD753016GK-XXX-BE9

µPD753017GC-XXX-3B9

µPD753017GK-XXX-BE9

80-pin plastic QFP (14 × 14 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm)

80-pin plastic QFP (14 × 14 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm)

80-pin plastic QFP (14 × 14 mm)

80-pin plastic TQFP (fine pitch) (12 × 12 mm)

Remark XXX indicates a ROM code suffix.

In this document, unless otherwise specified, the description is made based on µPD753017

as typical product.

The information in this document is subject to change without notice.

Document No. U10140EJ2V0DS00 (2nd edition)

Date Published December 1997 N

Printed in Japan

The mark shows major revised points.

1995

©

µPD753012, 753016, 753017

FUNCTIONAL OUTLINE

Parameter

Function

Instruction execution time

• 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation)

• 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation)

• 122 µs (subsystem clock: at 32.768 kHz operation)

On-chip memory

ROM 12288 × 8 bits (µPD753012)

16384 × 8 bits (µPD753016)

24576 × 8 bits (µPD753017)

RAM 1024 × 4 bits

General-purpose register

• 4-bit operation: 8 × 4 banks

• 8-bit operation: 4 × 4 banks

Input/

output

port

CMOS input

8

16

8

On-chip pull-up resistors can be specified by using software: 23

CMOS input/output

CMOS output

Also used for segment pins

N-ch open-drain

input/output

8

Withstands 13 V, on-chip pull-up resistors can be specified by using mask

option

Total

40

LCD controller/driver

• Segment number selection : 24/28/32 segments (can be changed to CMOS

output port in 4 time-unit; max. 8)

• Display mode selection

: Static 1/2 duty (1/2 bias)

1/3 duty (1/2 bias)

1/3 duty (1/3 bias)

1/4 duty (1/3 bias)

On-chip split resistor for LCD drive can be specified by using mask option

Timer

5 channels

• 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter,

carrier generator, or timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface

• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer

Clock output (PCL)

16 bits

•

Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

Buzzer output (BUZ)

• 2, 4, 32 kHz

(main system clock: at 4.19 MHz operation

or subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)

Vectored interrupts

Test input

External: 3, Internal: 5

External: 1, Internal: 1

System clock oscillator

• Ceramic or crystal oscillator for main system clock oscillation

• Crystal oscillator for subsystem clock oscillation

Standby function

Power supply voltage

Package

STOP/HALT mode

V^DD= 2.2 to 5.5 V

• 80-pin plastic QFP (14 × 14 mm)

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

2

µPD753012, 753016, 753017

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ...................................................................................................5

2. BLOCK DIAGRAM...............................................................................................................................7

3. PIN FUNCTION ....................................................................................................................................8

3.1 Port Pins ......................................................................................................................................8

3.2 Pins Other than Port Pins ........................................................................................................10

3.3 Pin Input/Output Circuits .........................................................................................................12

3.4 Recommended Connection for Unused Pins .........................................................................14

4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ......................................15

4.1 Differences between Mk I Mode and Mk II Mode ....................................................................15

4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................16

5. MEMORY CONFIGURATION ............................................................................................................17

6. PERIPHERAL HARDWARE FUNCTIONS .......................................................................................21

6.1 Digital Input/Output Ports ........................................................................................................21

6.2 Clock Generator ........................................................................................................................22

6.3 Subsystem Clock Oscillator Control Functions ....................................................................23

6.4 Clock Output Circuit .................................................................................................................24

6.5 Basic Interval Timer/Watchdog Timer.....................................................................................25

6.6 Watch Timer ..............................................................................................................................26

6.7 Timer/Event Counter.................................................................................................................27

6.8 Serial Interface ..........................................................................................................................31

6.9 LCD Controller/Driver ...............................................................................................................33

6.10 Bit Sequential Buffer … 16 Bits ...............................................................................................35

7. INTERRUPT FUNCTION AND TEST FUNCTION ...........................................................................36

8. STANDBY FUNCTION.......................................................................................................................38

9. RESET FUNCTION ............................................................................................................................39

10. MASK OPTION ..................................................................................................................................42

11. INSTRUCTION SETS AND THEIR OPERATIONS ........................................................................43

12. ELECTRICAL SPECIFICATIONS......................................................................................................55

13. PACKAGE DRAWINGS.....................................................................................................................68

14. RECOMMENDED SOLDERING CONDITIONS................................................................................70

3

µPD753012, 753016, 753017

APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................72

APPENDIX B DEVELOPMENT TOOLS .................................................................................................74

APPENDIX C RELATED DOCUMENTS .................................................................................................78

4

µPD753012, 753016, 753017

1. PIN CONFIGURATION (TOP VIEW)

•

80-pin plastic QFP (14 × 14 mm)

µPD753012GC-XXX-3B9, 753016GC-XXX-3B9,

µPD753017GC-XXX-3B9

•

80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µPD753012GK-XXX-BE9, 753016GK-XXX-BE9,

µPD753017GK-XXX-BE9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

S12

S13

1

P60/KR0

X2

2

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

S14

3

X1

S15

4

IC^Note

S16

5

XT2

S17

6

XT1

S18

V

DD

7

S19

P33

8

S20

P32

9

S21

P31/SYNC

P30/LCDCL

P23/BUZ

10

11

12

13

14

15

16

17

18

19

20

S22

S23

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

P22/PCL/PTO2

P21/PTO1

P20/PTO0

P13/TI0

P12/INT2/TI1/TI2

P11/INT1

P10/INT0

P03/SI/SB1

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Note Connect the IC (Internally Connected) pin directly to V^DD.

5

µPD753012, 753016, 753017

Pin Name

P00-P03

P10-P13

P20-P23

P30-P33

P40-P43

P50-P53

P60-P63

P70-P73

BP0-BP7

KR0-KR7

SCK

: Port 0

V^LC0-VLC2

BIAS

: LCD Power Supply 0-2

: LCD Power Supply Bias Control

: LCD Clock

: Port 1

: Port 2

LCDCL

SYNC

: Port 3

: LCD Synchronization

: Timer Input 0-2

: Port 4

TI0-TI2

PTO0-PTO2

BUZ

: Port 5

: Programmable Timer Output 0-2

: Buzzer Clock

: Port 6

: Port 7

PCL

: Programmable Clock

: Bit Port

INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4

: Key Return

: Serial Clock

: Serial Input

: Serial Output

: Serial Bus 0, 1

: Reset Input

: Segment Output 0-31

INT2

X1, X2

XT1, XT2

V^DD

: External Test Input 2

: Main System Clock Oscillation 1, 2

: Subsystem Clock Oscillation 1, 2

: Positive Power Supply

: Ground

SI

SO

SB0, SB1

RESET

S0-S31

V^SS

IC

: Internally Connected

COM0-COM3 : Common Output 0-3

6

µPD753012, 753016, 753017

3. PIN FUNCTION

3.1 Port Pins (1/2)

Dual

8-bit

I/O

I/O Circuit

Pin Name

P00

Input/Output

Function

At Reset

Input

Note 1

Function Pin

TYPE

Input

INT4

SCK

4-bit input port (PORT0).

×

B

For P01 to P03, on-chip pull-up resistors

can be specified in software in 3-bit units.

P01

Input/Output

Input

F -A

F -B

M -C

B -C

P02

SO/SB0

SI/SB1

INT0

P03

P10

4-bit input port (PORT1).

input

Input

On-chip pull-up resistors can be specified

in software in 4-bit units.

P11

INT1

P12

TI1/TI2/INT2

TI0

Noise eliminator can be selected (Only

P10/INT0)

P13

P20

Input/Output

PTO0

PTO1

PCL/PTO2

BUZ

4-bit input/output port (PORT2).

On-chip pull-up resistors can be specified

in software in 4-bit units.

E-B

M-D

P21

P22

P23

Programmable 4-bit input/output port

(PORT3).

P30

LCDCL

SYNC

–

P31

This port can be specified input/output in

bit units.

P32

On-chip pull-up resistor can be specified in

software in 4-bit units.

P33

–

P40-P43^{Note 2}

–

High level

(when pull-up

resistors are

contained) or

high

N-ch open-drain 4-bit input/output port

(PORT4).

A pull-up resistor can be contained bit-wise

(mask option).

impedance

Withstand voltage is 13 V in open-drain mode.

P50-P53^{Note 2}

–

N-ch open-drain 4-bit input/output port

(PORT5).

High level

(when pull-up

resistors are

provided) or

high

A pull-up resistor can be contained bit-wise

(mask option).

impedance

Withstand voltage is 13 V in open-drain mode.

Notes 1. Circled characters indicate the Schmitt-trigger input.

2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),

low level input leakage current increases when input or bit manipulation instruction is executed.

8

µPD753012, 753016, 753017

3.1 Port Pins (2/2)

Dual

8-bit

I/O

I/O Circuit

Pin Name

P60

Input/Output

Function

At Reset

Input

Note 1

Function Pin

TYPE

Programmable 4-bit input/output port

(PORT6).

Input/Output

Output

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

S24

S25

S26

S27

S28

S29

S30

S31

F -A

H-A

P61

P62

P63

P70

P71

P72

P73

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

This port can be specified for input/output

bit-wise.

On-chip pull-up resistors can be specified

in software in 4-bit units.

Input

4-bit input/output port (PORT7).

On-chip pull-up resistors can be specified

in software in 4-bit units.

×

Note 2

1-bit output port (BIT PORT)

Also used for segment output pins.

Output

Notes 1. Circled characters indicate the Schmitt-trigger input.

2. For BP0 to BP7, VLC1 is selected as an input source.

The output levels differ depending on BP0 to BP7 and the external circuit of the V^LC1.

Example BP0 to BP7 are connected each other internally in the µPD753017 as shown below. Therefore, the

output levels of BP0 to BP7 are determined by the levels of R¹, R2, and R3

V

DD

µ

PD753017

R2

BP0

BP1

ON

V

LC1

R

1

R3

9

µPD753012, 753016, 753017

3.2 Pins Other than Port Pins (1/2)

Dual

I/O Circuit

Pin Name

TI0

Input/Output

Input

Function

At Reset

Note 1

Function Pin

TYPE

P13

Inputs external event pulses to the timer/event

counter.

Input

B -C

TI1

P12/INT2

TI2

PTO0

PTO1

PTO2

PCL

BUZ

Output

P20

P21

Timer/event counter output

Clock output

Input

E-B

P22/PCL

P22/PTO2

P23

Any frequency output (for buzzer output

or system clock trimming)

SCK

Input/Output

P01

P02

Serial clock input/output

Input

F -A

F -B

SO/SB0

Serial data output

Serial bus data input/output

SI/SB1

INT4

P03

P00

P10

Serial data input

M -C

B

Serial bus data input/output

Input

Edge detection vectored interrupt input (both

rising edge and falling edge detection)

Input

Edge detection vectored

interrupt input (detection

edge can be selected)

Noise eliminator can be

selected. (Only P10/INT0)

With noise eliminator

asynchronous selection

possible

INT0

B -C

Asynchronous

INT1

P11

INT2

Input

Output

–

P12/TI1/TI2 Edge-detection-testable input

Input

Note 2

–

B -C

F -A

G-D

H-A

G-B

–

KR0-KR3

KR4-KR7

S0-S23

P60-P63

Falling edge detection testable input

P70-P73

–

Segment signal output

Common signal output

S24-S31

COM0-COM3

V^LC0-VLC2

BP0-BP7

–

LCD drive power

On-chip split resistor is enable (mask option).

BIAS

Output

–

Output for external split resistor disconnect

Clock output for externally expanded driver

Clock output for externally expanded driver sync

Note 3

Input

–

Note 4

LCDCL

P30

P31

–

E-B

–

Note 4

SYNC

X1

X2

Input

–

Crystal/ceramic connection pin for the main

system clock oscillator. When inputting the

external clock, input the external clock to pin

X1, and the reverse phase of the external clock

to pin X2.

Notes 1. Circled characters indicate the Schmitt trigger input.

2. Each displays output selects the following V^LCXas input source.

S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0.

3. When a split resistor is contained .......

Low level

When no split resistor is contained ...... High impedance

4. These pins are provided for future system expansion. At present, these pins are used only as pins

P30 and P31.

10

µPD753012, 753016, 753017

3.2 Pins Other than Port Pins (2/2)

Dual

I/O Circuit

Pin Name

XT1

Input/Output

Function

At Reset

–

Note

Function Pin

TYPE

Input

–

Crystal connection pin for the subsystem clock os-

cillator. When the external clock is used, input the

external clock to pin XT1. In this case, pin XT2 must

be left unconnected. Pin XT1 can be used as a 1-

bit input (test) pin.

XT2

RESET

IC

Input

–

System reset input (low level active)

Internally connected. Connect directly to VDD.

Positive power supply

–

B

–

VDD

VSS

GND

Note Circled characters indicate the Schmitt trigger input.

11

µPD753012, 753016, 753017

3.3 Pin Input/Output Circuits

The µPD753017 pin input/output circuits are shown schematically.

TYPE A

TYPE D

VDD

data

P-ch

OUT

P-ch

IN

N-ch

output

disable

N-ch

Push-pull output that can be placed in output

high impedance (both P-ch, N-ch off).

CMOS specification input buffer.

TYPE B

TYPE E-B

VDD

P.U.R.

enable

P-ch

IN

data

IN/OUT

Type D

output

disable

Type A

Schmitt trigger input having hysteresis characteristic.

P.U.R. : Pull-Up Resistor

TYPE F-A

TYPE B-C

VDD

V

DD

P.U.R.

P-ch

P.U.R.

enable

P.U.R.

enable

P-ch

data

IN/OUT

Type D

output

disable

IN

Type B

P.U.R. : Pull-Up Resistor

12

µPD753012, 753016, 753017

TYPE F-B

TYPE H-A

V

DD

P.U.R.

P-ch

P.U.R.

enable

SEG

data

IN/OUT

Type G-D

output

disable

(P)

V

DD

P-ch

IN/OUT

data

bit port

data

output

disable

N-ch

Type D

output

disable

(N)

disable

P.U.R. : Pull-Up Resistor

TYPE G-B

TYPE M-C

V

DD

V

LC0

LC1

P.U.R.

enable

P-ch

P-ch N-ch

IN/OUT

OUT

data

N-ch

COM

data

output

disable

N-ch P-ch

VLC2

N-ch

P.U.R. : Pull-Up Resistor

TYPE G-D

TYPE M-D

VDD

P.U.R.

(Mask Option)

V

LC0

LC1

IN/OUT

data

N-ch

(+13 V

withstand

voltage)

output

disable

V

DD

P-ch N-ch

Input

instruction

P-ch

P.U.R.^Note

OUT

Voltage

limitation

circuit

SEG

data

N-ch

(+13 V withstand voltage)

VLC2

P.U.R. : Pull-Up Resistor

This pull-up resistor operates only when an input

instruction is executed if the pull-up resistor is not

connected by the mask option. (When the pin

is at low level, current flows from V^DDto the pin.)

Note

13

µPD753012, 753016, 753017

3.4 Recommended Connection for Unused Pins

Table 3-1. List of Recommended Connection for Unused Pins

Recommended Connection

Connect to VSS or VDD.

P00/INT4

P01/SCK

Independently connect to VSS or VDD via resistor.

P02/SO/SB0

P03/SI/SB1

P10/INT0, P11/INT1

P12/TI1/TI2/INT2

P13/TI0

Connected to V^SS.

Connect to VSS or VDD.

P20/PTO0

P21/PTO1

P22/PTO2/PCL

P23/BUZ

Input state : Individually connect to V^SSor VDD via

resistor.

Output state: Leave unconnected.

P30/LCDCL

P31/SYNC

P32

P33

P40-P43

Input state : Connect to V^SS.

P50-P53

Output state: Connected to VSS. (Do not connect the

pull-up resistor by mask option).

P60/KR0-P63/KR3

Input state

:

Individually connected to VSS or VDD via

resistor

.

P70/KR4-P73/KR7

S0-S23

Output state: Leave unconnected.

Leave unconnected.

S24/BP0-S31/BP7

COM0-COM3

V^LC0-VLC2

Connect to VSS.

BIAS

Only if all of VLC0-VLC2 are unused, connect to VSS.

In other cases, leave unconnected.

XT1

XT2

IC

Connect to VSS.

Leave unconnected.

Directly connect to VDD.

14

µPD753012, 753016, 753017

4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE

4.1 Differences between Mk I Mode and Mk II Mode

The CPU of µPD753017 has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by the bit 3 of the stack bank select register (SBS).

•

Mk I mode: Upward compatible with µPD75316B.

Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes.

Mk II mode: Incompatible with µPD75316B.

Can be used in all the 75XL CPU’s including those products whose ROM capacity is more

than 16K bytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I Mode

Mk II Mode

Program memory (bytes)

•

µPD753012 : 12288

•

µPD753012 : 12288

µPD753016 : 16384

µPD753017 : 24576

µPD753016, 753017 : 16384

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

3-machine cycles

2-machine cycles

4-machine cycles

3-machine cycles

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL

series. This mode enhances the software compatibility with products which have more

than 16K bytes.

When Mk II mode is selected, the number of stack bytes (usable area) in the execution

of a subroutine call instruction increases by 1 per stack compared to Mk I mode.

Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction

takes another machine cycle. Therefore, when more importance is attached to RAM

utilization or throughput than software compatibility, use the Mk I mode.

15

µPD753012, 753016, 753017

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.

The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be

initialized to 10XXB^Noteat the beginning of a program. When using the Mk II mode, it must be initialized to 00XXB^Note

.

Figure 4-1. Stack Bank Select Register Format

3

2

1

0

Address

F84H

Symbol

SBS

SBS3 SBS2 SBS1 SBS0

Stack area specification

0

1

0

1

0

1

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

0 must be set in the bit 2 position.

0

Mode switching specification

0

1

Mk II mode

Mk I mode

Note The desired numbers must be set in the XX positions.

Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk

I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the

Mk II mode.

16

µPD753012, 753016, 753017

5. MEMORY CONFIGURATION

•

Program memory (ROM) ............... 12288 × 8 bits (µPD753012)

............... 16384 × 8 bits (µPD753016)

............... 24576 × 8 bits (µPD753017)

•

Data memory (RAM)

·

Data area …1024 words × 4 bits (000H to 3FFH)

Peripheral hardware area…128 × 4 bits (F80H to FFFH)

Figure 5-1. Program Memory Map (1/3)

(a) µPD753012

7

6

5

0

0000H

0002H

0004H

0006H

0008H

000AH

000CH

RBE Internal reset start address

MBE

(high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

MBE RBE INTBT/INT4 start address

INTBT/INT4 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

MBE RBE INT0 start address

INT0 start address

Branch address of

BR BCXA, BR BCDE,

BR !addr1, BRA !addr1^Note

or CALLA !addr1^Note

instruction

CALLF !faddr

instruction

entry address

MBE RBE INT1 start address

INT1 start address

BRCB !caddr

instruction

branch address

MBE RBE INTCSI start address

INTCSI start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

CALL !addr instruction

subroutine entry address

INTT0 start address

MBE RBE

INTT0 start address

(Iow-order 8 bits)

(high-order 6 bits)

INTT1, INTT2 start address

MBE RBE

INTT1, INTT2 start address (Iow-order 8 bits)

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

0020H

GETI instruction reference table

Branch destination

007FH

0080H

address and

subroutine entry

address when GETI

instruction is executed

07FFH

0800H

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

Note Can be used in Mk II mode only.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE, BR PCXA instruction.

17

µPD753012, 753016, 753017

Figure 5-1. Program Memory Map (2/3)

(b) µPD753016

7

6

5

0

0000H

0002H

0004H

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (Iow-order 8 bits)

Branch address of

BR BCXA, BR BCDE,

BR !addr, BRA !addr1^Note

or CALLA !addr1^Note

instruction

INT0 start address

(high-order 6 bits)

(Iow-order 8 bits)

CALLF !faddr

instruction

entry address

0006H

0008H

MBE RBE

INT1 start address

INTCSI start address

INTT0 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

BRCB !caddr

instruction

branch address

CALL !addr instruction

subroutine entry address

000AH

000CH

MBE RBE INTT1,INTT2 start address (high-order 6 bits)

INTT1,INTT2 start address (Iow-order 8 bits)

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

0020H

GETI instruction reference table

007FH

0080H

Branch destination

address and

subroutine entry

address when GETI

instruction is executed

07FFH

0800H

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

3000H

BRCB !caddr instruction

branch address

3FFFH

Note Can be used in Mk II mode only.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE, BR PCXA instruction.

18

µPD753012, 753016, 753017

Figure 5-1. Program Memory Map (3/3)

(c) µPD753017

7

6

5

0

MBE RBE Internal reset start address (high-order 6 bits)

Internal reset start address (Iow-order 8 bits)

0000H

0002H

0004H

MBE RBE INTBT/INT4 start address

INTBT/INT4 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

CALLF !faddr

instruction

entry address

MBE RBE INT0 start address

INT0 start address

0006H

0008H

000AH

000CH

MBE RBE INT1 start address

INT1 start address

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

(high-order 6 bits)

(Iow-order 8 bits)

BRCB !caddr

instruction

branch address

MBE RBE INTCSI start address

INTCSI start address

BR !addr

instruction

branch address

MBE RBE INTT0 start address

INTT0 start address

BR BCDE

BR BCXA

branch address

CALL !addr

instruction

branch address

MBE RBE INTT1,INTT2 start address (high-order 6 bits)

INTT1,INTT2 start address (Iow-order 8 bits)

BRA !addr1^Note

instruction

branch address

GETI instruction

branch/call

address

0020H

GETI instruction reference table

CALLA !addr1^Note

instruction

007FH

0080H

branch address

07FFH

0800H

BR $addr instruction

relative branch address

(–15 to –1, +2 to +16)

0FFFH

1000H

BRCB !caddr instruction

branch address

1FFFH

2000H

BRCB !caddr instruction

branch address

2FFFH

3000H

BRCB !caddr instruction

branch address

3FFFH

4000H

BRCB !caddr instruction

branch address

4FFFH

5000H

BRCB !caddr instruction

branch address

5FFFH

Note Can be used in Mk II mode only.

Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H-

3FFFH).

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE, BR PCXA instruction.

19

µPD753012, 753016, 753017

Figure 5-2. Data Memory Map

Data memory

Memory bank

000H

(32 × 4)

General-purpose register area

01FH

020H

0

256 × 4

(224 × 4)

0FFH

100H

256 × 4

(224 × 4)

1DFH

1E0H

1

(32 × 4)

Display data memory

1FFH

200H

Stack area^Note

Data area

static RAM

(1024 × 4)

256 × 4

2

2FFH

300H

256 × 4

3

3FFH

F80H

Not incorporated

Peripheral

hardware area

128 × 4

15

FFFH

Note For stack area, one memory bank can be selected among memory bank 0-3.

20

µPD753012, 753016, 753017

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 Digital Input/Output Ports

There are four types of I/O ports as follows.

· CMOS input (PORT0, 1)

:

8

· CMOS input/output (PORT2, 3, 6, 7)

· N-channel open-drain input/output (PORT4, 5)

· Bit port output (BP0-BP7)

Total

: 16

:

8

40

Table 6-1. Types and Features of Digital Ports

Port (Pin Name)

Function

Operation & Features

Remarks

PORT0

(P00-P03)

4-bit input

Dual function pins also function as output pins depending on

the operation mode when the serial interface function is used.

Also used for the INT4,

SCK, SO/SB0, SI/SB1 pins.

PORT1

(P10-P13)

Dedicated 4-bit I/O port

Also used for the INT0-

INT2 and TI0-TI2 pins.

PORT2

(P20-P23)

4-bit I/O

Can be set to input mode or output mode in 4-bit

units.

Also used for the PTO0-

PTO2, PCL, BUZ pins.

PORT3

(P30-P33)

Can be set to input mode or output mode in 1/4 bit

units.

Also used for the LCDCL,

SYNC pins.

PORT4

(P40-P43)

4-bit I/O

Can be set to input mode

or output mode in 4-bit

units.

Ports 4 and 5 are paired

and data can be input/

output in 8-bit units.

On-chip pull-up resistor can

be specified bit-wise by

mask option.

(N-channel

open-drain,

13 V

PORT5

(P50-P53)

withstanding)

PORT6

(P60-P63)

4-bit I/O

Can be set to input mode

or output mode in 1/4-bit

units.

Ports 6 and 7 are paired

and data can be input/

output in 8-bit units.

Also used for the KR0-KR3

pins.

PORT7

(P70-P73)

Can be set to input mode

or output mode in 4-bit

units.

Also used for the KR4-KR7

pins.

BP0-BP7

1-bit output

Outputs data bit-wise. Can be switched to LCD drive

segment output S24-S31 by software.

—

21

µPD753012, 753016, 753017

6.2 Clock Generator

Operation of the clock generator is determined by the processor clock control register (PCC) and system clock

control register (SCC).

The two clocks, the main system clock and subsystem clock, are available.

The instruction excution time can be altered.

• 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (main system clock : at 4.19 MHz operation)

• 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (main system clock : at 6.0 MHz operation)

• 122 µs (subsystem clock : at 32.768 kHz operation)

Figure 6-1. Clock Generator Block Diagram

· Basic interval timer (BT)

XT1

· Timer/event counter

· Serial interface

· Watch timer

· LCD controller/driver

· INT0 noise eliminator

· Clock output circuit

VDD

LCD controller/driver

Watch timer

Subsystem

clock oscillator

fXT

XT2

X1

1/1~1/4096

Divider

VDD

f

X

Main system

clock oscillator

X2

1/2 1/41/16

Selector

WM.3

SCC

Oscillation

stop

Divider

1/4

SCC3

SCC0

Selector

Φ

· CPU

· INT0 noise eliminator

· Clock output circuit

PCC

PCC0

PCC1

4

HALT F/F

S

PCC2

PCC3

HALT^Note

STOP^Note

R

Q

PCC2,

PCC3

Clear

STOP F/F

Wait release signal from BT

S

Q

RESET signal

R

Standby release signal from

interrupt control circuit

Note Instruction execution

Remarks 1. f^X= Main system clock frequency

2. fXT = Subsystem clock frequency

3. Φ = CPU clock

4. PCC: Processor Clock Control Register

5. SCC: System Clock Control Register

6. One clock cycle (t^CY) of Φ equal to one machine cycle of the instruction.

22

µPD753012, 753016, 753017

6.3 Subsystem Clock Oscillator Control Functions

The µPD753017 subsystem clock oscillator has the following two control functions.

•

Selects by software whether an on-chip feedback resistor is to be used or not^Note

.

Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply current

is high (V^DD≥ 2.7 V).

Note When not using the subsystem clock, set SOS.0 to 1 in software (on-chip feedback resistor is not used),

connect XT1 to V^SS, and leave XT2 unconnected, so that the current consumption of the subsystem clock

oscillator can be reduced.

The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS).

(Refer to Figure 6-2.)

Figure 6-2. Subsystem Clock Oscillator

V

DD

SOS.0

Feedback resistor

Inverter

µ

PD753017

SOS.1

XT1

XT2

V

DD

23

µPD753012, 753016, 753017

6.4 Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the P22, PTO2, and PCL pins to the remote

control waveform outputs and peripheral LSI’s, etc.

•

Clock output (PCL) : Φ, 524, 262, 65.5 kHz (at 4.19 MHz operation)

Φ, 750, 375, 93.8 kHz (at 6.0 MHz operation)

Figure 6-3. Clock Output Circuit Block Diagram

From clock

generator

From timer/event

Φ

counter (channel 2)

Output buffer

f

X

/2³

/2⁴

Selector

PCL/PTO2/P22

f

X

/2⁶

PORT2.2

Bit 2 of PMGB

P22

output latch

Port 2 I/O mode

specification bit

CLOM3

0

CLOM1 CLOM0 CLOM

4

Internal bus

Remark Special care has been taken in designing the chip so that small-width pulses may not be output

when switching clock output enable/disable.

24

µPD753012, 753016, 753017

6.5 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

•

Interval timer operation to generate a reference time interrupt

Watchdog timer operation to detect a runaway of program and reset the CPU

Selects and counts the wait time when the standby mode is released

Reads the contents of counting

Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram

From clock

generator

Clear

fX

/2⁵

/2⁷

/2⁹

BT

Basic interval timer

(8-bit frequency divider)

Set

MPX

interrupt

request flag

Vectored

interrupt

IRQBT request signal

BT

f

/2¹²

X

3

Wait release signal

when standby is

released.

Internal reset

signal

WDTM

1

BTM3 BTM2 BTM1 BTM0 BTM

4

SET1^Note

8

SET1^Note

Internal bus

Note Instruction execution

25

µPD753012, 753016, 753017

6.6 Watch Timer

The µPD753017 has one channel of watch timer. The watch timer has the following functions.

•

Sets the test flag (IRQW) with 0.5 sec interval.

The standby mode can be released by the IRQW.

0.5 sec interval can be created by both the main system clock and subsystem clock. Take f^X= 4.194304

MHz for the main system clock frequency and f^XT= 32.768 kHz for the subsystem clock.

Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the

fast feed mode.

Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23 and BUZ pins, usable for buzzer and trimming

of system clock frequencies.

Clears the frequency divider to make the clock start with zero seconds.

Figure 6-5. Watch Timer Block Diagram

fW

(512 Hz : 1.95 ms)

2⁶

f^LCD

f^W

(256 Hz : 3.91 ms)

2⁷

f^X

128

Selector

f^W

fW

INTW

IRQW

set signal

2¹⁴

From

clock

generator

(32.768 kHz)

Selector

Divider

2 Hz

0.5 sec

f^XT

4 kHz 2 kHz

(32.768 kHz)

f^W

2³

fW

Clear

2⁴

Selector

Output buffer

P23/BUZ

WM

PORT2.3

PMGB bit 2

Port 2 input/

P23

output latch

WM7

0

WM5 WM4 WM3 WM2 WM1 WM0

output mode

8

Bit test instruction

Internal bus

The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz.

26

µPD753012, 753016, 753017

6.7 Timer/Event Counter

The µPD753017 has three channels of timer/event counter. The timer/event counter has the following functions.

•

Programmable interval timer operation

Square wave output of any frequency to the PTOn pin

Event counter operation

Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided

frequency to the PTOn pin (frequency divider operation).

Supplies the serial shift clock to the serial interface circuit.

Calls the counting status.

•

The timer/event counter operates in the following four modes as set by the mode register.

Table 6-2. Operation Modes of Timer/Event Counter

Channel

Channel 0 Channel 1 Channel 2

Mode

8-bit timer/event counter mode

Note

Gate control function

PWM pulse generator mode

16-bit timer/event counter mode

Gate control function

×

Note

Carrier generator mode

Note Used for gate control signal generation

27

µPD753012, 753016, 753017

6.8 Serial Interface

The µPD753017 is provided with an 8-bit clocked serial interface. This serial interface operates in the following

four modes:

· Operation stop mode

· 3-wire serial I/O mode

· 2-wire serial I/O mode

· SBI mode

31

µPD753012, 753016, 753017

6.9 LCD Controller/Driver

The µPD753017 incorporates a display controller which generates segment and common signals according to

the display data memory contents and incorporates segment and common drivers which can drive the LCD panel

directly.

The µPD753017 LCD controller/driver functions are as follows:

•

Display data memory is read automatically by DMA operation and segment and common signals are

generated.

Display mode can be selected from among the following five:

<1> Static

<2> 1/2 duty (time multiplexing by 2), 1/2 bias

<3> 1/3 duty (time multiplexing by 3), 1/2 bias

<4> 1/3 duty (time multiplexing by 3), 1/3 bias

<5> 1/4 duty (time multiplexing by 4), 1/3 bias

•

A frame frequency can be selected from among four in each display mode.

A maximum of 32 segment signal output pins (S0-S31) and four common signal output pins (COM0-COM3).

The segment signal output pins (S24-S27 and S28-S31) can be changed to the output ports in 4-pin units.

Split-resistor can be incorporated to supply LCD drive power. (Mask option)

· Various bias methods and LCD drive voltages can be applicable.

· When display is off, current flow to the split resistor is cut.

Display data memory not used for display can be used for normal data memory.

It can also operate by using the subsystem clock.

•

33

µPD753012, 753016, 753017

6.10 Bit Sequential Buffer … 16 Bits

The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be

easily performed by changing the address specification and bit specification in sequence, therefore it is useful

when processing a long data bit-wise.

Figure 6-11. Bit Sequential Buffer Format

Address

Bit

FC3H

FC2H

FC1H

FC0H

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

Symbol

BSB3

BSB2

BSB1

BSB0

L = BH

L = 7H

L register

L = FH

L = CH

L = 8H

L = 4H

L = 0H

L = 3H

DECS L

INCS L

Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register.

2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.

35

µPD753012, 753016, 753017

7. INTERRUPT FUNCTION AND TEST FUNCTION

µPD753017 has eight types of interrupt sources and two types of test sources. Among the test sources, INT2

is provided with two testable inputs for edge detection.

µPD753017 has the following functions in the interrupt controller.

(1) Interrupt function

•

Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the

interrupt enable flag (IEXXX) and interrupt master enable flag (IME).

Can set any interrupt start address.

•

Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register

(IPS).

•

Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software.

Release the standby mode. A release interrupt can be selected by the interrupt enable flag.

(2) Test function

•

Test request flag (IRQXXX) generation can be checked by software.

Release the standby mode. The test source to be released can be selected by the test enable flag.

36

µPD753012, 753016, 753017

8. STANDBY FUNCTION

In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the µPD753017.

Table 8-1. Operation Status in Standby Mode

STOP Mode

STOP instruction

HALT Mode

HALT instruction

Set instruction

System clock when set

Settable only when the main system

clock is used.

Settable both by the main system

clock and subsystem clock.

Operation Clock generator

status

Only the main system clock stops

oscillation.

Only the CPU Φ halts (oscillation

continues).

Note 1

Basic interval timer

Operation stops

Operation.

BT mode : Sets IRQBT at reference

time intervals.

WT mode: Generates reset signal

when BT overflows.

Note 1

Serial interface

Operable only when an external SCK

input is selected as the serial clock.

Operable

Note 1

Timer/event counter

Operable only when a signal input to

the TI0-TI2 pins is specified as the

count clock.

Operable

Watch timer

Operable when f^XTis selected as the

count clock.

Operable

LCD controller/driver

External interrupt

Operable only when f^XTis selected as

the LCDCL.

The INT1, 2, and 4 are operable.

Only the INT0 is not operated.^{Note 2}

CPU

The operation stops.

Release signal

Interrupt request signal sent from the operable hardware enabled by the

interrupt enable flag or RESET signal input.

Notes 1. Cannot operate only when the main system clock stops.

2. Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode

register(IM0).

38

µPD753012, 753016, 753017

9. RESET FUNCTION

There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/

watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-

1 shows the circuit diagram of the above two inputs.

Figure 9-1. Configuration of Reset Function

RESET

Internal reset signal

Reset signal sent from the basic

interval timer/watchdog timer

WDTM

Internal bus

The µPD753017 is set by the RESET signal generated and each device is initialized as listed in Table 9-1.

Figure 9-2 shows the timing chart of the reset operation.

Figure 9-2. Reset Operation by RESET Signal Generation

Wait ^Note

RESET

signal

generated

Operation mode or

standby mode

HALT mode

Operation mode

Internal reset operation

Note The following two times can be selected by the mask option.

2¹⁷/fX (21.8 ms : at 6.00 MHz operation, 31.3 ms : at 4.19 MHz operation)

2¹⁵/fX (5.46 ms : at 6.00 MHz operation, 7.81 ms : at 4.19 MHz operation)

39

µPD753012, 753016, 753017

Table 9-1. Status of Each Device After Reset (1/2)

RESET Signal Generation

in Standby Mode

RESET Signal Generation

in Operation

Hardware

Program counter (PC)

µPD753012,

Sets the low-order 6 bits of

program memory’s address

Sets the low-order 6 bits of

program memory’s address

753016

0000H to the PC13-PC8 and the 0000H to the PC13-PC8 and the

contents of address 0001H to

the PC7-PC0.

contents of address 0001H to

the PC7-PC0.

µPD753017

Sets the low-order 7 bits of

program memory’s address

Sets the low-order 7 bits of

program memory’s address

0000H to the PC14-PC8 and the 0000H to the PC14-PC8 and the

contents of address 0001H to

the PC7-PC0.

contents of address 0001H to

the PC7-PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0-SK2)

0

Interrupt status flag (IST0)

Bank enable flag (MBE, RBE)

Sets the bit 6 of program

memory’s address 0000H to

the RBE and bit 7 to the MBE.

Sets the bit 6 of program

memory’s address 0000H to

the RBE and bit 7 to the MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

Data memory (RAM)

1000B

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Bank select register (MBS, RBS)

Held

Undefined

0, 0

Basic interval/

watchdog

timer

Counter (BT)

Undefined

Mode register (BTM)

Watchdog timer enable flag (WDTM)

Counter (T0)

0

Timer/event

counter (T0)

0

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT F/F

FFH

0

FFH

0

0, 0

0

0, 0

0

Timer/event

counter (T1)

Counter (T1)

Modulo register (TMOD1)

Mode register (TM1)

TOE1, TOUT F/F

FFH

0

FFH

0

0, 0

0

0, 0

0

Timer/event

counter (T2)

Counter (T2)

Modulo register (TMOD2)

FFH

High level period setting modulo

register (TMOD2H)

Mode register (TM2)

TOE2, TOUT F/F

REMC, NRZ, NRZB

TGCE

0

0, 0

0, 0, 0

0

0, 0

0, 0, 0

0

Watch timer

Mode register (WM)

0

40

µPD753012, 753016, 753017

Table 9-1. Status of Each Device After Reset (2/2)

RESET Signal Generation

in Standby Mode

RESET Signal Generation

in Operation

Hardware

Serial interface

Shift register (SIO)

Held

Undefined

Operating mode register (CSIM)

SBI control register (SBIC)

0

Slave address register (SVA)

Processor clock control register (PCC)

System clock control register (SCC)

Clock output mode register (CLOM)

Held

Undefined

Clock generator,

clock output

circuit

0

Sub-oscillator control register (SOS)

0

LCD controller

/driver

Display mode register (LCDM)

0

Display control register (LCDC)

Interrupt request flag (IRQXXX)

Interrupt enable flag (IEXXX)

Interrupt master enable flag (IME)

INT0, 1, 2 mode registers (IM0, IM1, IM2)

Priority selection register (IPS)

Output buffer

0

Interrupt

Reset (0)

function

0

0, 0, 0

0

Digital port

Off

Output latch

Cleared (0)

I/O mode registers (PMGA, PMGB)

Pull-up resistor setting register (POGA)

0

Bit sequential buffer (BSB0-BSB3)

Held

Undefined

41

µPD753012, 753016, 753017

10. MASK OPTION

The µPD753017 has the following mask options.

•

Mask option of P40 to P43 and P50 to P53

An on-chip pull-up resistor can be selected.

<1> Specifies an on-chip pull-up resistor in bit units.

<2> Does not specify an on-chip pull-up resistor.

Mask option of V^LC0to VLC2 and BIAS pins

An on-chip split resistor for LDC driving can be selected.

<1> Does not specify an on-chip divider resistor

<2> Specifies four 10-kΩ (typ.) on-chip split resistors at the same time.

<3> Specifies four 100-kΩ (typ.) on-chip split resistors at the same time.

•

Standby function mask option

Wait time can be selected by RESET signai input.

<1> 2¹⁷/fX (21.8 ms: at fX = 6.0 MHz, 31.3 ms: at fX = 4.19 MHz)

<2> 2¹⁵/fX (5.46 ms: at fX = 6.0 MHz, 7.81 ms: at fX = 4.19 MHz)

Subsystem clock mask option

Selectable an on-chip feedback resistor can be used/cannot be used

<1> Make an on-chip feedback resistor usable

(Switch on-chip feedback resistor ON/OFF in software)

<2> Make an on-chip feedback resistor unusable

(Disconnects on-chip feedback resistor in hardware)

42

µPD753012, 753016, 753017

11. INSTRUCTION SETS AND THEIR OPERATIONS

(1) Operand identifiers and methods of use

Operands are written in the operand column of each instruction in accordance with the method of use for

the operand identifier of the instruction. For details, refer to RA75X Assembler Package User’s Manual—

Language (U12385E). If there are several elements, one of them is selected. Capital letters and the +

and – symbols are key words and are written as they are.

For immediate data, appropriate numbers and labels are written.

Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be written.

However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to

User’s Manual.

Identifier

Format

reg

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

reg1

rp

XA, BC, DE, HL

BC, DE, HL

BC, DE

rp1

rp2

rp'

XA, BC, DE, HL, XA’, BC’, DE’, HL’

BC, DE, HL, XA’, BC’, DE’, HL’

rp'1

rpa

HL, HL+, HL–, DE, DL

DE, DL

rpa1

n4

n8

4-bit immediate data or label

8-bit immediate data or label

Note

mem

bit

8-bit immediate data or label

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

FC0H-FFFH immediate data or label

pmem

addr

0000H-2FFFH immediate data or label (µPD753012)

0000H-3FFFH immediate data or label (µPD753016, 753017)

0000H-5FFFH immediate data or label

addr1

caddr

faddr

12-bit immediate data or label

11-bit immediate data or label

taddr

20H-7FH immediate data (where bit 0 = 0) or label

PORTn

IEXXX

RBn

PORT0-PORT7

IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW

RB0-RB3

MBn

MB0, MB1, MB2, MB3, MB15

Note mem can be only used even address in 8-bit data processing.

43

µPD753012, 753016, 753017

(2) Legend in explanation of operation

A

: A register, 4-bit accumulator

: B register

B

C

: C register

D

: D register

E

: E register

H

: H register

L

: L register

X

: X register

XA

BC

DE

HL

XA’

BC’

DE’

HL’

PC

SP

CY

PSW

MBE

RBE

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

: XA’ expanded register pair

: BC’ expanded register pair

: DE’ expanded register pair

: HL’ expanded register pair

: Program counter

: Stack pointer

: Carry flag, bit accumulator

: Program status word

: Memory bank enable flag

: Register bank enable flag

PORTn : Port n (n = 0-7)

IME

IPS

: Interrupt master enable flag

: Interrupt priority selection register

: Interrupt enable flag

IEXXX

RBS

MBS

PCC

.

: Register bank selection register

: Memory bank selection register

: Processor clock control register

: Separation between address and bit

: The contents addressed by XX

: Hexadecimal data

(XX)

XXH

44

µPD753012, 753016, 753017

(3) Explanation of symbols under addressing area column

*1

MB = MBE•MBS

(MBS = 0-3, 15)

*2

*3

MB = 0

MBE = 0 : MB = 0 (00H-7FH)

MB = 15 (F80H-FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0-3, 15)

*4

*5

*6

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

µPD753012

addr = 0000H-2FFFH

addr = 0000H-3FFFH

µPD753016

753017

*7

µPD753012

753016

addr = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

753017

(In Mk I mode)

µPD753017

addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

(In Mk II mode)

*8

µPD753012

caddr = 0000H-0FFFH(PC13, 12 = 00B) or

1000H-1FFFH(PC13, 12 = 01B) or

2000H-2FFFH(PC13, 12 = 10B)

µPD753016

caddr = 0000H-0FFFH(PC13, 12 = 00B) or

1000H-1FFFH(PC13, 12 = 01B) or

2000H-2FFFH(PC13, 12 = 10B) or

3000H-3FFFH(PC13, 12 = 11B)

Program memory addressing

µPD753017

caddr = 0000H-0FFFH(PC14, 13, 12 = 000B) or

1000H-1FFFH(PC14, 13, 12 = 001B) or

2000H-2FFFH(PC14, 13, 12 = 010B) or

3000H-3FFFH(PC14, 13, 12 = 011B) or

4000H-4FFFH(PC14, 13, 12 = 100B) or

5000H-5FFFH(PC14, 13, 12 = 101B)

*9

faddr = 0000H-07FFH

taddr = 0020H-007FH

*10

*11

µPD753012

µPD753016

µPD753017

addr1 = 0000H-2FFFH

addr1 = 0000H-3FFFH

addr1 = 0000H-5FFFH

Remarks 1. MB indicates memory bank that can be accessed.

2. In *2, MB = 0 independently of how MBE and MBS are set.

3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.

4. *6 to *11 indicate the areas that can be addressed.

45

µPD753012, 753016, 753017

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.

The value of S varies as follows.

•

When no skip is made: S = 0

When the skipped instruction is a 1- or 2-byte instruction: S = 1

When the skipped instruction is a 3-byte instruction^Note: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of CPU clock Φ (= t^CY); time can be selected from among four

types by setting PCC.

46

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

MOV

Operand

Operation

Skip Condition

String effect A

Area

Transfer

instruction

A, #n4

1

2

1

2

1

2

1

2

1

2

1

2

A ← n4

reg1, #n4

XA, #n8

HL, #n8

rp2, #n8

A, @HL

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

reg1 ← n4

XA ← n8

HL ← n8

rp2 ←n8

A ← (HL)

2

String effect A

String effect B

2

1

*1

*2

*1

*3

2+S

1

A ←(HL), then L ←L+1

A ←(HL), then L ←L–1

A ← (rpa1)

L = 0

L = FH

2

XA ← (HL)

1

(HL) ← A

2

(HL) ← XA

2

A ← (mem)

2

XA ← (mem)

(mem) ← A

2

(mem) ← XA

A ← reg

2

XA, rp’

2

XA ←rp’

reg1, A

2

reg1 ← A

rp’1, XA

A, @HL

A, @HL+

A, @HL–

A, @rpa1

XA, @HL

A, mem

XA, mem

A, reg1

2

rp’1 ←XA

XCH

1

A ↔ (HL)

*1

*2

*1

*3

2+S

1

A ↔ (HL), then L ←L+1

A ↔ (HL), then L ←L–1

A ↔ (rpa1)

L = 0

L = FH

2

XA ↔ (HL)

2

A ↔ (mem)

2

XA ↔ (mem)

A ↔ reg1

1

XA, rp’

2

XA ↔ rp’

47

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

Operand

Operation

Skip Condition

Area

Table

MOVT^{Note 1}XA, @PCDE

1

3

XA ← (PC13–8+DE)ROM

• µPD753017

XA ← (PC^14–8+DE)ROM

XA, @PCXA

XA ← (PC13–8+XA)ROM

• µPD753017

XA ← (PC^14–8+XA)ROM

XA, @BCDE^{Note 2}

XA ← (B1,0+CDE)ROM

*6

• µPD753017

XA ← (B^2–0+CDE)ROM

*11

XA, @BCXA^{Note 2}

XA ← (B1,0+CXA)ROM

*6

• µPD753017

*11

XA ← (B^2–0+CXA)ROM

Bit transfer

MOV1

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

fmem.bit, CY

pmem.@L, CY

@H+mem.bit, CY

A, #n4

2

1

2

1

2

1

2

1

2

1

2

CY ← (fmem.bit)

*4

*5

*1

*4

*5

*1

CY ← (pmem^7–2+L3–2.bit(L1–0))

CY ← (H+mem^3–0.bit)

(fmem.bit) ← CY

2

(pmem^7–2+L3–2.bit(L1–0)) ← CY

(H+mem^3–0.bit) ← CY

A ← A+n4

2

Operation

ADDS

1+S

2+S

1+S

2+S

1

carry

XA, #n8

XA ← XA+n8

A, @HL

A ← A+(HL)

*1

XA, rp’

XA ← XA+rp’

rp’1, XA

rp’1 ← rp’1+XA

ADDC

SUBS

SUBC

A, @HL

A, CY ← A+(HL)+CY

XA, CY ← XA+rp’+CY

rp’1, CY ← rp’1+XA+CY

A ← A–(HL)

XA, rp’

2

rp’1, XA

2

A, @HL

1+S

2+S

1

borrow

XA, rp’

XA ← XA–rp’

rp’1, XA

rp’1 ← rp’1–XA

A, @HL

A, CY ← A–(HL)–CY

XA, CY ← XA–rp’–CY

rp’1, CY ← rp’1–XA–CY

XA, rp’

2

rp’1, XA

2

Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. Only the following bits are valid for the B register.

µPD753012, 753016 : low-order 2 bits

µPD753017

: low-order 3 bits

Remark PC¹⁴is fixed to 0 when the µPD753017 is set in the Mk I mode.

48

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

AND

Operand

Operation

Skip Condition

Area

Operating

instructions

A, #n4

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

A ← A n4

A, @HL

XA, rp’

rp’1, XA

A, #n4

A, @HL

XA, rp’

rp’1, XA

A, #n4

A, @HL

XA, rp’

rp’1, XA

A

A ← A (HL)

XA ← XA rp’

rp’1 ← rp’1 XA

A ← A n4

*1

2

OR

2

1

A ← A (HL)

XA ← XA rp’

rp’1 ← rp’1 XA

A ← A n4

*1

2

XOR

2

1

A ← A (HL)

XA ← XA rp’

rp’1 ← rp’1 XA

2

Accumulator RORC

manipulation

instructions

1

CY ← A

A ← A

0, A

3

← CY, An–1 ← A

n

NOT

A

2

Increment

and

Decrement

instructions

INCS

reg

1+S

2+S

1+S

2+S

1+S

2+S

1

reg ← reg+1

rp1 ← rp1+1

reg=0

rp1

rp1=00H

(HL)=0

@HL

(HL) ← (HL)+1

(mem) ← (mem)+1

reg ← reg–1

rp’ ← rp’–1

*1

*3

mem

(mem)=0

reg=FH

rp'=FFH

reg=n4

DECS

reg

rp’

Comparison SKE

instruction

reg, #n4

@HL, #n4

A, @HL

XA, @HL

A, reg

XA, rp’

CY

Skip if reg = n4

Skip if (HL) = n4

Skip if A = (HL)

Skip if XA = (HL)

Skip if A = reg

Skip if XA = rp’

CY ← 1

*1

(HL) = n4

A = (HL)

XA = (HL)

A=reg

XA=rp’

Carry flag

manipulation

instruction

SET1

CLR1

SKT

CY

1

CY ← 0

CY

1+S

1

Skip if CY = 1

CY ← CY

CY=1

NOT1

CY

49

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

SET1

Operand

Operation

Skip Condition

Area

Memory bit

manipulation

instructions

mem.bit

2

(mem.bit) ←1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

fmem.bit

(fmem.bit) ←1

pmem.@L

2

(pmem^7–2+L3–2.bit(L1–0)) ←1

(H+mem^3–0.bit) ←1

@H+mem.bit

mem.bit

2

CLR1

2

(mem.bit) ←0

fmem.bit

2

(fmem.bit) ←0

pmem.@L

2

(pmem^7–2+L3–2.bit(L1–0)) ←0

(H+mem^3–0.bit) ←0

@H+mem.bit

mem.bit

2

SKT

2+S

2

Skip if (mem.bit)=1

(mem.bit)=1

fmem.bit

Skip if (fmem.bit)=1

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

(mem.bit)=0

pmem.@L

Skip if (pmem^7–2+L3–2.bit(L1–0))=1

Skip if (H+mem^3–0.bit)=1

Skip if (mem.bit)=0

@H+mem.bit

mem.bit

SKF

fmem.bit

Skip if (fmem.bit)=0

(fmem.bit)=0

(pmem.@L)=0

(@H+mem.bit)=0

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

pmem.@L

Skip if (pmem^7–2+L3–2.bit(L1–0))=0

Skip if (H+mem^3–0.bit)=0

Skip if (fmem.bit)=1 and clear

Skip if (pmem^7–2+L3–2.bit(L1–0))=1 and clear

Skip if (H+mem^3–0.bit)=1 and clear

CY ← CY (fmem.bit)

@H+mem.bit

fmem.bit

SKTCLR

AND1

OR1

pmem.@L

@H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

2

CY ← CY (pmem^7–2+L3–2.bit(L1–0))

CY ← CY (H+mem^3–0.bit)

CY ← CY (fmem.bit)

2

CY ← CY (pmem^7–2+L3–2.bit(L1–0))

CY ← CY (H+mem^3–0.bit)

CY ← CY (fmem.bit)

2

XOR1

2

CY ← CY (pmem7–2+L3–2.bit(L1–0))

CY ← CY (H+mem3–0.bit)

2

50

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

BR^{Note 1}

Operand

Operation

Skip Condition

Area

Branch

addr

–

PC13–0 ← addr

*6

instructions

Select appropriate instruction from

among BR !addr, BRCB !caddr, and

BR $addr according to the assembler

being used.

BR !addr

BRCB !caddr

BR $addr

addr1

–

• µPD753017

*11

PC^14–0← addr1

Select appropriate instruction from

among BR !addr, BRA !caddr1 BRCB

!caddr, and BR $addr according to

the assembler being used.

BR !addr

BRA !addr1

BRCB !caddr

BR $addr

!addr

3

PC^13–0← addr

*6

*7

• µPD753017

PC¹⁴← 0, PC13–0 ← addr

$addr

1

2

PC^13–0← addr

$addr1

• µPD753017

PC^14–0← addr1

PCDE

2

3

PC^13–0← PC13–8+DE

• µPD753017

PC^14–0← PC14–8+DE

PCXA

PC^13–0← PC13–8+XA

• µPD753017

PC14–0 ← PC14–8+XA

BCDE^{Note 2}

PC13–0 ← B1,0+CDE

*6

• µPD753017

PC^14–0← B2–0+CDE

*11

BCXA^Note2

PC13–0 ← B1,0+CXA

*6

• µPD753017

*11

PC^14–0← B2–0+CXA

BRA^Note1

!addr

3

• µPD753012, 753016

PC^13–0← addr

*6

!addr1

• µPD753017

*11

PC^14–0← addr1

Notes 1. The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. Only the following bits are valid for the B register.

µPD753012, 753016 : low-order 2 bits

µPD753017

: low-order 3 bits

Remark PC¹⁴is fixed to 0 when the µPD753017 is set in the Mk I mode.

51

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

BRCB^Note

Operand

Operation

Skip Condition

Area

Branch

instructions

!caddr

2

3

2

3

PC13–0 ← PC13,12+caddr11-0

*8

• µPD753017

PC^14–0← PC14,13,12+caddr11–0

Subroutine

stack control

instructions

CALLA^Note!addr

• µPD753012, 753016

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC^13–0

(SP–2) ← ×, ×, MBE, RBE

*6

*11

*6

PC^13–0← addr, SP ← SP–6

!addr1

!addr

• µPD753017

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC^14–0

(SP–2) ← ×, ×, MBE, RBE

PC^14–0← addr1, SP ← SP–6

CALL^Note

3

4

(SP–4)(SP–1)(SP–2) ← PC11–0

(SP–3) ← MBE, RBE, PC¹³, PC12

PC13–0 ← addr, SP ← SP–4

• µPD753012, 753016

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC^13–0

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← addr, SP ← SP–6

4

• µPD753017

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC^14–0

(SP–2) ← ×, ×, MBE, RBE

PC14 ← 0, PC^13–0← addr, SP ← SP–6

CALLF^Note!faddr

2

3

(SP–4)(SP–1)(SP–2) ← PC11–0

(SP–3) ← MBE, RBE, PC¹³, PC12

PC13–0 ← 000+faddr, SP ← SP–4

*9

• µPD753012, 753016

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, 0, PC^13–0

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← 000+faddr, SP ← SP–6

3

• µPD753017

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC^14–0

(SP–2) ← ×, ×, MBE, RBE

PC^14–0← 0000+faddr, SP ← SP–6

Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

Remark PC¹⁴is fixed to 0 when the µPD753017 is set in the Mk I mode.

52

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

RET^Note

Operand

Operation

Skip Condition

Area

Subroutine

stack control

instructions

1

3

MBE, RBE, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2),

SP ← SP+4

• µPD753012, 753016

×, ×, MBE, RBE ← (SP+4)

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

• µPD753017

×, ×, MBE, RBE ← (SP+4)

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

RETS^Note

1

3+S

MBE, RBE, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2),

SP ← SP+4

Unconditional

then skip unconditionally

• µPD753012, 753016

×, ×, MBE, RBE ← (SP+4)

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

then skip unconditionally

• µPD753017

×, ×, MBE, RBE ← (SP+4)

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2), SP ← SP+6

then skip unconditionally

RETI^Note

1

3

MBE, RBE, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

• µPD753012, 753016

0, 0, PC¹³, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

• µPD753017

0, PC¹⁴, PC13, PC12 ← (SP+1)

PC^11–0← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

Remark PC¹⁴is fixed to 0 when the µPD753017 is set in the Mk I mode.

53

µPD753012, 753016, 753017

Number

of Machine

Cycles

Instruction

Group

Number

of Bytes

Addressing

Mnemonic

PUSH

Operand

Operation

Skip Condition

Area

Subroutine

stack control

instructions

rp

1

2

1

2

1

2

1

2

1

2

1

2

3

(SP–1)(SP–2) ← rp, SP ← SP–2

(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2

rp ← (SP+1)(SP), SP ← SP+2

MBS ← (SP+1), RBS ← (SP), SP ← SP+2

IME(IPS.3) ← 1

BS

rp

POP

EI

BS

Interrupt

control

instructions

IEXXX

IEXXX ← 1

DI

IME(IPS.3) ← 0

IEXXX

IEXXX ← 0

Input/output

instructions

IN^{Note 1}

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

A ← PORTn

(n = 0-7)

(n = 4, 6)

(n = 2-7)

(n = 4, 6)

XA ← PORTn+1, PORTn

PORTn ← A

OUT^{Note 1}

PORTn+1, PORTn ← XA

Set HALT mode (PCC.2 ← 1)

Set STOP mode (PCC.3 ← 1)

No operation

CPU control HALT

instruction

STOP

NOP

Special

instruction

SEL

RBn

MBn

RBS ← n

MBS ← n

(n = 0-3)

(n = 0-3, 15)

GETI^{Notes 2, 3}taddr

• When TBR instruction

*10

PC^13–0← (taddr)5–0+(taddr+1)

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – –

• When TCALL instruction

(SP–4)(SP–1)(SP–2) ← PC^11–0

(SP–3) ← MBE, RBE, PC13, PC12

PC13–0 ← (taddr)5–0+(taddr+1)

SP ← SP–4

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – –

• When instruction other than TBR and

TCALL instructions

(taddr) (taddr+1) instruction is executed

Depending on

the reference

instruction

1

3

• µPD753017

• When TBR instruction

PC^13–0← (taddr)5–0+(taddr+1)

PC14 ← 0

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – –

4

• When TCALL instruction

(SP–5)(SP–6)(SP–3)(SP–4) ← 0, PC^14–0

(SP–2) ← ×, ×, MBE, RBE

PC^13–0← (taddr)5–0+(taddr+1)

SP ← SP–6, PC14 ← 0

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – – –

3

• When instruction other than TBR and

TCALL instructions

(taddr) (taddr+1) instruction is executed

Depending on

the reference

instruction

Notes 1. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and

MBS must be set to 15.

2. The shaded area is applicable only to the Mk II mode. The other area is applicable only to Mk I mode.

3. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

Remark PC¹⁴is fixed to 0 when the µPD753017 is set in the Mk I mode.

54

µPD753012, 753016, 753017

12. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25 ˚C)

Parameter

Supply voltage

Symbol

VDD

Conditions

Ratings

–0.3 to +7.0

–0.3 to VDD +0.3

–0.3 to +14

–0.3 to VDD +0.3

–10

Unit

V

Input voltage

VI1

Other than ports 4 and 5

V

VI2

Ports 4 Pull-up resistor provided

V

and 5

N-ch open drain

V

Output voltage

VO

IOH

V

High-level output current

Per pin

mA

˚C

Total of all pins

Per pin

–30

Low-level output current

IOL

30

Total of all pins

200

Operating ambient

temperature

TA

–40 to +85

Storage temperature

T^stg

–65 to +150

˚C

Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality

of the product may be impaired. The absolute maximum ratings are values that may physically

damage the product(s). Be sure to use the product(s) within the ratings.

Capacitance (T^A= 25 ˚C, VDD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

CIN

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f = 1 MHz

Pins other than tested pins: 0 V

COUT

C^IO

15

pF

15

pF

55

µPD753012, 753016, 753017

Main System Clock Oscillator Characteristics (TA = –40 to +85 ˚C)

Recommended

Constants

Oscillator

Parameter

Conditions

MIN. TYP. MAX.

Unit

Ceramic

oscillator

Oscillation frequency

(fX)^{Note 1}

VDD = 2.2 to 5.5 V

1.0

6.0^{Note 2}MHz

X1

X2

Oscillation

stabilization time^{Note 3}

After VDD has

4

ms

C1

C2

reached MIN. value of

oscillation voltage

range

V

DD

Crystal

oscillator

Oscillation frequency

(fX)^{Note 1}

VDD = 2.2 to 5.5 V

1.0

6.0^{Note 2}MHz

X1

X2

Oscillation

VDD = 4.5 to 5.5 V

VDD = 2.2 to 5.5 V

VDD = 1.8 to 5.5 V

10

30

ms

C1

C2

stabilization time^{Note 3}

V

DD

External

clock

X1 input frequency

(fX)^{Note 1}

1.0

6.0^{Note 4}MHz

X1

X2

X1 input high-,

low-level widths

(tXH, tXL)

VDD = 1.8 to 5.5 V

83.3

500

ns

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator

only. For the instruction execution time, refer to AC Characteristics.

2. When the oscillation frequency is 4.7 MHz < f^X≤ 6.0 MHz at 2.2 V ≤ VDD < 2.7 V, assign a value other

than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle

falls short of the rated value of 0.85 µs.

3. The oscillation stabilization time is the time required for oscillation to stabilize after V^DDhas been

applied or STOP mode has been released.

4. When the X1 input frequency is 4.19 MHz < f^X≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, assign a value other

than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle

falls short of the rated value of 0.95 µs.

Caution When using the main system clock oscillator, wire the portion enclosed by the dotted line in

the above figure as follows to prevent adverse influence from wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with any other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator at the same potential as V^DD.

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract any signal from the oscillator.

56

µPD753012, 753016, 753017

Subsystem Clock Oscillator Characteristics (TA = –40 to +85 ˚C)

Recommended

Constants

Oscillator

Parameter

Conditions

MIN. TYP. MAX.

Unit

kHz

Crystal

oscillator

Oscillation frequency

(fXT)^{Note 1}

VDD = 2.2 to 5.5 V

32

32.768

35

XT1

XT2

R

Oscillation

VDD = 4.5 to 5.5 V

VDD = 2.2 to 5.5 V

VDD = 1.8 to 5.5 V

1.0

2

s

C3

C4

stabilization time^{Note 2}

10

V

DD

External

clock

XT1 input frequency

(fXT)^{Note 1}

32

5

100

kHz

XT1

XT2

XT1 input high-,

low-level widths

(tXTH, tXTL)

VDD = 1.8 to 5.5 V

15

µs

Notes 1. The oscillation frequency shown above indicate characteristics of the oscillator only. For the instruction

execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after V^DDhas been

applied.

Caution When using the subsystem clock oscillator, wire the portion enclosed by the dotted line in the

above figure as follows to prevent adverse influence from to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with any other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator at the same potential as V^DD.

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract any signal from the oscillator.

The subsystem clock oscillator has a low amplification factor to reduce current dissipation and

is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost

care in wiring the subsystem clock oscillator.

57

µPD753012, 753016, 753017

Recommended Oscillator Constants

Ceramic oscillator (T^A= –40 to +85 ˚C)

Recommended

Frequency Circuit Constant

(MHz) (pF)

Oscillation

Voltage Range

(VDD)

Manufacturer

Part Number

Remark

C1

100

–

C2

100

–

MIN.

2.7

MAX.

5.5

Murata Mfg.

Co., Ltd.

CSB1000J^Note

CSA2.00MG040

CST2.00MG040

CSA4.19MG

1.0

Rd = 5.6 kΩ

2.0

Capacitor-contained model

4.19

30

–

30

–

2.5

2.2

2.7

2.5

5.5

CST4.19MGW

CSA4.19MGU

CST4.19MGWU

CSA6.00MG

30

–

30

–

6.0

30

–

30

–

CST6.00MGW

CSA6.00MGU

CST6.00MGWU

KBR-1000F/Y

KBR-2.0MS

30

–

30

–

Capacitor-contained model

–20 to +85 ˚C

Kyocera Corp.

1.0

220

82

33

220

82

33

2.9

3.1

2.7

5.5

2.0

KBR-4.19MSA

KBR-4.19MKS

PBRC 4.19A

PBRC 4.19B

KBR-6.0MSA

KBR-6.0MKS

PBRC 6.00A

PBRC 6.00B

FCR2.0MC3

4.19

–

Capacitor-contained model

–20 to +85 ˚C

6.0

33

2.8

5.5

–20 to +85 ˚C

–

Capacitor-contained model

–20 to +85 ˚C

TDK Corp.

2.0

30

2.0

2.5

2.7

5.5

FCR4.19MC5

FCR6.0MC5

4.19

6.0

Note When using the CSB1000J (1.00 MHz) by Murata Mfg. Co., Ltd. as a ceramic oscillator, a limiting resistor

(Rd = 5.6 kΩ) is necessary (refer to the figure below). The resistor is not necessary when using the other

recommended oscillators.

Example of recommended main system clock oscillator (when using CSB1000J by Murata Mfg. Co., Ltd.)

X1

X2

Rd

C2

CSB1000J

C1

V

DD

58

µPD753012, 753016, 753017

DC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

Low-level output

current

Symbol

Conditions

MIN.

TYP.

MAX.

15

Unit

mA

IOL

Per pin

Total of all pins

120

High-level input

voltage

VIH1

VIH2

VIH3

Ports 2, 3

2.7 V ≤ VDD ≤ 5.5 V 0.7 VDD

2.2 V ≤ VDD < 2.7 V 0.9 VDD

2.7 V ≤ VDD ≤ 5.5 V 0.8 VDD

2.2 V ≤ VDD < 2.7 V 0.9 VDD

2.7 V ≤ VDD ≤ 5.5 V 0.7 VDD

2.2 V ≤ VDD < 2.7 V 0.9 VDD

VDD

V

Ports 0, 1, 6, 7, RESET

VDD

Ports 4, 5 Pull-up resistor

provided

VDD

N-ch open drain 2.7 V ≤ VDD ≤ 5.5 V 0.7 VDD

2.2 V ≤ VDD < 2.7 V 0.9 VDD

VDD – 0.1

13

VIH4

VIL1

X1, XT1

VDD

Low-level input

voltage

Ports 2, 3, 4, 5

Ports 0, 1, 6, 7, RESET

X1, XT1

2.7 V ≤ VDD ≤ 5.5 V

2.2 V ≤ VDD < 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.2 V ≤ VDD < 2.7 V

0

0.3 VDD

0.1 VDD

0.2 VDD

0.1 VDD

0.1

0

VIL2

0

VIL3

VOH

High-level output

voltage

SCK, SO, ports 0, 2, 3, 6, 7, BP0 to 7

IOH = –1 mA

VDD – 0.5

Low-level output

voltage

VOL1

SCK, SO, ports 0, 2, 3, 4,

5, 6, 7, BP0 to 7

IOL = 15 mA

0.2

2.0

V

VDD = 4.5 to 5.5 V

IOL = 1.6 mA

0.4

V

VOL2

SB0, 1

N-ch open drain

0.2 VDD

Pull-up resistor ≥ 1 kΩ

Pins other than X1, XT1

X1, XT1

High-level input

leakage current

ILIH1

ILIH2

ILIH3

ILIL1

ILIL2

I^LIL3

VIN = VDD

3

20

–3

–20

–3

µA

VIN = 13 V Ports 4, 5 (N-ch open drain)

VIN = 0 V Pins other than X1, XT1, ports 4 and 5

Low-level input

leakage current

X1, XT1

Ports 4, 5 (N-ch open drain)

When input instruction is not executed

Ports 4, 5 (N-ch open

drain)

When input instruction

–30

–27

–8

µA

VDD = 5 V

–10

–3

is executed

VDD = 3 V

High-level output

ILOH1

VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 7,

ports 4, 5 (with on-chip pull-up resistor),

BP0 to 7

3

leakage current

Low-level output

leakage current

Internal pull-up

resistor

ILOH2

ILOL

VOUT = 13 V Ports 4, 5 (N-ch open drain)

VOUT = 0 V

20

–3

µA

RL1

RL2

VIN = 0 V

Ports 0, 1, 2, 3, 6, 7 (except P00 pin)

Ports 4, 5 (mask option)

50

15

100

30

200

60

kΩ

59

µPD753012, 753016, 753017

DC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

LCD drive voltage

LCD divider

Symbol

VLCD

Conditions

MIN.

2.2

50

5

TYP.

MAX.

VDD

Unit

V

RLCD1

RLCD2

VODC

100

10

200

20

kΩ

V

resistor^{Note 1}

LCD output voltage

deviation^{Note 2}

(common)

IO = ±5µA

IO = ±1µA

VLCD0 = VLCD

0

±0.2

VLCD1 = VLCD × 2/3

VLCD2 = VLCD × 1/3

2.2 V ≤ VLCD ≤ VDD

LCD output voltage

deviation^{Note 2}

(segment)

VODS

0

±0.2

V

Supply current^{Note 3}

IDD1

IDD2

IDD1

IDD2

IDD3

6.00 MHz^{Note 4}

crystal

VDD = 5.0 V ± 10 %^{Note 5}

VDD = 3.0 V ± 10 %^{Note 6}

1.9

0.4

0.72

0.27

1.5

0.25

0.7

0.23

12

6.0

1.3

2.1

0.8

4.0

0.75

2.0

0.7

35

12

24

18

12

25

9

mA

µA

oscillation

C1 = C2

HALT

mode

VDD = 5.0 V ± 10 %

VDD = 3.0 V ± 10 %

= 22 pF

4.19 MHz^{Note 4}

crystal

VDD = 5.0 V ± 10 %^{Note 5}

VDD = 3.0 V ± 10 %^{Note 6}

oscillation

C1 = C2

HALT

mode

Low-

VDD = 5.0 V ± 10 %

= 22 pF

VDD = 3.0 V ± 10 %

VDD = 2.5 V ± 10 %

32.768

kHz^{Note 7}

voltage

4.5

12

crystal

mode^{Note 8}VDD = 3.0 V, TA = 25 ˚C

Low current

oscillation

VDD = 3.0 V ± 10 %

6

dissipation

9

mode^Note

VDD = 3.0 V, TA = 25 ˚C

6

IDD4

HALT

mode

Low-

V

DD = 3.0 V ± 10 %

DD = 2.5 V ± 10 %

8.5

3

voltage

mode^{Note 8}

V

DD = 3.0 V, T

A

= 25 ˚C

DD = 3.0 V ± 10 %

= 25 ˚C

8.5

3.5

0.05

0.02

17

12

7

Low power

dissipation

V

mode^Note

9

V

DD = 3.0 V, T

A

IDD5

XT1 = 0 V VDD = 5.0 V ± 10 %

10

5

STOP

VDD = 3.0 V ± 10 %

mode^{Note 10}

TA = 25 ˚C

3

Notes 1. Either RLCD1 or RLCD2 can be selected by mask option.

2. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and

common outputs and the output voltage.

3. The current flowing through the internal pull-up resistor and the LCD split resistor is not included.

4. Including the case when the subsystem clock oscillates.

5. When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

6. When the device operates in low-speed mode with PCC set to 0000.

7. When the device operates on the subsystem clock, with the system clock control register (SCC) set

to 1001 and oscillation of the main system clock stopped.

8. When 0000 is assigned to the sub-oscillator control register (SOS).

9. When 0010 is assigned to the SOS.

10. When the sub-oscillator feedback resistor is not used with the SOS set to 00X1 (X: don’t care).

60

µPD753012, 753016, 753017

AC Characteristics (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

CPU clock cycle time^{Note 1}

(minimum instruction

execution time = 1

machine cycle)

Symbol

Conditions

MIN.

TYP.

MAX.

64

Unit

µs

When using

ceramic or

crystal

tCY

VDD = 2.7 to 5.5 V 0.67

0.85

Operates

with main

system

clock

64

µs

When using

external

clock

VDD = 2.7 to 5.5 V 0.67

VDD = 1.8 to 5.5 V 0.95

64

µs

64

µs

Operates with subsystem clock

VDD = 2.7 to 5.5 V

114

0

122

125

1

µs

TI0, TI1, TI2 input frequency fTI

MHz

kHz

µs

0

275

TI0, TI1, TI2 high-, low-level

widths

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

1.8

Note 2

10

µs

Interrupt input high-,

low-level widths

tINTH, tINTL

INT0

IM02 = 0

IM02 = 1

µs

INT1, 2, 4

KR0-7

10

µs

10

µs

RESET low-level width

t^RSL

10

µs

Notes 1. The cycle time of the CPU clock (Φ) is

determined by the oscillation frequency

of the connected oscillator (and exter-

nal clock), the system clock control

register (SCC), and processor clock

control register (PCC).

t

CY vs VDD

(with main system clock)

70

64

60

6

5

The figure on the right shows the sup-

ply voltage V^DDvs. cycle time tCY char-

acteristics when the device operates

with the main system clock.

Operation guaranteed range

4

3

µ

2. 2t^CYor 128/fX depending on the setting

of the interrupt mode register (IM0).

2

1

0.95

0.85

0.67

0.5

0

1

2

3

4

5

5.5 6

1.8 2.2 2.7

Supply voltage VDD [V]

Remark The shaded portion is guaranteed

only when using the external clock.

61

µPD753012, 753016, 753017

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T^A= –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY1/2–50

tKCY1/2–150

150

TYP.

MAX.

Unit

ns

tKCY1

SCK high-, low-level widths

tKL1,

tKH1

VDD = 2.7 to 5.5 V

SI^{Note 1}setup time (vs. SCK ↑) tSIK1

500

SI^{Note 1}hold time (vs. SCK ↑)

tKSI1

400

600

SCK ↓ → SO^{Note 1}output

tKSO1

RL = 1 kΩ^{Note 2}

VDD = 2.7 to 5.5 V

0

250

delay time

CL = 100 pF

0

1000

Notes 1. Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode.

2. R^Land CL respectively indicate the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (T^A= –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

400

600

0

TYP.

MAX.

Unit

ns

tKCY2

SCK high-, low-level widths

tKL2,

tKH2

VDD = 2.7 to 5.5 V

SI^{Note 1}setup time (vs. SCK ↑) tSIK2

SI^{Note 1}hold time (vs. SCK ↑) tKSI2

SCK ↓ → SO^{Note 1}output

tKSO2

RL = 1 kΩ^{Note 2}

VDD = 2.7 to 5.5 V

300

delay time

C^L= 100 pF

0

1000

Notes 1. Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

62

µPD753012, 753016, 753017

SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

1300

3800

tKCY3/2–50

tKCY3/2–150

150

TYP.

MAX.

Unit

ns

tKCY3

SCK high-, low-level widths

tKL3,

tKH3

tSIK3

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(vs. SCK ↑)

500

SB0, 1 hold time (vs. SCK ↑) tKSI3

tKCY3/2

0

SCK ↓ → SB0, 1 output

delay time

tKSO3

RL = 1 kΩ^Note

VDD = 2.7 to 5.5 V

250

CL = 100 pF

0

1000

SCK ↑ → SB0, 1 ↓

SB0, 1 ↓ → SCK ↓

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

tSBH

tKCY3

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

SBI mode (SCK ··· external clock input (slave)): (T^A= –40 to +85 ˚C, VDD = 2.2 to 5.5 V)

Parameter

SCK cycle time

Symbol

Conditions

VDD = 2.7 to 5.5 V

MIN.

800

3200

400

1600

100

150

tKCY4/2

0

TYP.

MAX.

Unit

ns

tKCY4

SCK high-, low-level widths

tKL4,

tKH4

tSIK4

VDD = 2.7 to 5.5 V

SB0, 1 setup time

(vs. SCK ↑)

SB0, 1 hold time (vs. SCK ↑) tKSI4

SCK ↓ → SB0, 1 output

delay time

tKSO4

RL = 1 kΩ^Note

VDD = 2.7 to 5.5 V

300

CL = 100 pF

0

1000

SCK ↑ → SB0, 1 ↓

SB0, 1 ↓ → SCK ↓

SB0, 1 low-level width

SB0, 1 high-level width

tKSB

tSBK

tSBL

t^SBH

tKCY4

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

63

µPD753012, 753016, 753017

AC timing test points (except X1 and XT1 inputs)

VIH (MIN.)

VIL (MAX.)

VIH (MIN.)

VIL (MAX.)

VOH (MIN.)

V^OL(MAX.)

VOH (MIN.)

V^OL(MAX.)

Clock timing

1/f

X

t

XL

t

XH

VDD – 0.1 V

X1 input

0.1 V

1/fXT

t

XTL

t

XTH

VDD – 0.1 V

XT1 input

0.1 V

TI0, TI1, TI2 timing

1/fTI

t

TIL

t

TIH

TI0, TI1, TI2

64

µPD753012, 753016, 753017

Serial transfer timing

3-wire serial I/O mode

t

KCY1

t

KL1

t

KH1

SCK

t

SIK1

t

KSI1

Input data

SI

t

KSO1

Output data

SO

2-wire serial I/O mode

t

KCY2

t

KL2

t

KH2

SCK

t

SIK2

t

KSI2

SB0, 1

t

KSO2

65

µPD753012, 753016, 753017

Serial transfer timing

Bus release signal transfer

t

KCY3, 4

t

KL3, 4

t

KH3, 4

SCK

t

SIK3, 4

t

KSB

t

SBL

t

SBH

t

SBK

t

KSI3, 4

SB0, 1

t

KSO3, 4

Command signal transfer

t

KCY3, 4

t

KL3, 4

t

KH3, 4

SCK

t

SIK3, 4

t

KSB

t

SBK

t

KSI3, 4

SB0, 1

t

KSO3, 4

Interrupt input timing

t

INTL

t

INTH

INT0, 1, 2, 4

KR0-7

RESET input timing

t

RSL

RESET

66

µPD753012, 753016, 753017

Data retention characteristics of data memory in STOP mode and at low supply voltage

(T^A= –40 to +85 ˚C)

Parameter

Release signal setup time

Oscillation stabilization

wait time^{Note 1}

Symbol

Conditions

MIN.

0

TYP.

MAX.

Unit

µs

tSREL

tWAIT

Released by RESET

Note 2

Note 3

ms

Released by interrupt request

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

2. Either 2¹⁷/fX or 2¹⁵/fX can be selected by mask option.

3. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

Wait Time

BTM3

BTM2

BTM1

BTM0

fx = 4.19 MHz

fx = 6.0 MHz

–

0

1

0

1

0

1

0

1

2²⁰/fx (approx. 250 ms)

2¹⁷/fx (approx. 31.3 ms)

2¹⁵/fx (approx. 7.82 ms)

2¹³/fx (approx. 1.95 ms)

2²⁰/fx (approx. 175 ms)

2¹⁷/fx (approx. 21.8 ms)

2¹⁵/fx (approx. 5.46 ms)

2¹³/fx (approx. 1.37 ms)

Data retention timing (when STOP mode released by RESET)

Internal reset operation

Oscillation stabilization wait time

Operation mode

STOP mode

Data retention mode

VDD

tSREL

STOP instruction execution

RESET

tWAIT

Data retention timing (standby release signal: when STOP mode released by interrupt signal)

Oscillation stabilization wait time

STOP mode

Operation mode

Data retention mode

t

SREL

VDD

V

DDDR

STOP instruction execution

Standby release signal

(interrupt request)

t

WAIT

67

µPD753012, 753016, 753017

13 . PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14x14)

A

B

60

61

41

40

detail of lead end

S

C D

R

Q

21

20

80

1

F

P

J

G

M

H

I

K

M

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.13 mm (0.005 inch) of

its true position (T.P.) at maximum material condition.

A

B

17.2±0.4

14.0±0.2

0.677±0.016

+0.009

0.551

–0.008

+0.009

0.551

C

14.0±0.2

–0.008

D

F

17.2±0.4

0.825

0.677±0.016

0.032

G

0.825

0.032

+0.004

0.012

H

0.30±0.10

–0.005

I

0.13

0.005

J

K

0.65 (T.P.)

1.6±0.2

0.026 (T.P.)

0.063±0.008

+0.009

0.031

L

0.8±0.2

–0.008

+0.004

0.006

+0.10

0.15

M

–0.003

–0.05

N

P

0.10

0.004

+0.005

0.106

2.7±0.1

–0.004

Q

R

S

0.1±0.1

5°±5°

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

S80GC-65-3B9-5

68

µPD753012, 753016, 753017

80 PIN PLASTIC TQFP (FINE PITCH) (12×12)

A

B

60

41

61

40

detail of lead end

C

D

S

Q

R

80

21

1

20

F

P

M

G

H

I

J

K

M

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.10 mm (0.004 inch) of

its true position (T.P.) at maximum material condition.

A

14.00±0.20

0.551±0.008

+0.009

0.472

B

12.00±0.20

–0.008

+0.009

0.472

C

12.00±0.20

–0.008

D

F

14.00±0.20

1.25

0.551±0.008

0.049

G

1.25

0.049

+0.05

0.22

H

0.009±0.002

–0.04

I

0.10

0.004

J

0.50 (T.P.)

0.020 (T.P.)

+0.009

0.039

K

L

1.00±0.20

0.50±0.20

–0.008

+0.008

0.020

–0.009

+0.055

0.145

M

0.006±0.002

–0.045

N

P

Q

R

S

0.10

0.004

1.05

0.041

0.10±0.05

5°±5°

0.004±0.002

5°±5°

1.27 MAX.

0.050 MAX.

P80GK-50-BE9-5

69

µPD753012, 753016, 753017

14. RECOMMENDED SOLDERING CONDITIONS

Solder the µPD753017 under the following recommended conditions.

For the details on the recommended soldering conditions, refer to Information Document Semiconductor

Device Mounting Technology Manual (C10535E).

For the soldering methods and conditions other than those recommended, consult NEC.

Table 14-1. Soldering Conditions of Surface Mount Type

(1) µPD753012GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm)

µPD753016GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm)

µPD753017GC-XXX-3B9: 80-pin plastic QFP (14 × 14 mm)

Symbol of

Soldering Method

Infrared reflow

VPS

Soldering Conditions

Recommended

Condition

Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.),

Number of times: 3 max.

IR35-00-3

VP15-00-3

WS60-00-1

Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.),

Number of times: 3 max.

Wave soldering

Solder bath temperature: 260 ˚C max., Time: 10 seconds max.,

Number of times: 1

Preheating temperature: 120 ˚C max. (package surface temperature)

Partial heating

Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device)

–

Caution Do not use two or more soldering methods in combination (except partial heating).

70

µPD753012, 753016, 753017

(2) µPD753012GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µPD753016GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

µPD753017GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

Symbol of

Recommended

Condition

Soldering Method

Infrared reflow

Soldering Conditions

Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.),

Number of times: 2 max., Number of days: 7^Note(After that, prebaking

is necessary at 125 ˚C for 10 hours.)

IR35-107-2

VP15-107-2

–

Products other than those packed in heat-resistant trays (such as those

packed in a magazine, taping, or non-heat-resistant tray) cannot be baked

while they are in their packaging.

VPS

Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.),

Number of times: 2 max., Number of days: 7^Note(After that, prebaking

is necessary at 125 ˚C for 10 hours.)

Products other than those packed in heat-resistant trays (such as those

packed in a magazine, taping, or non-heat-resistant tray) cannot be baked

while they are in their packaging.

Pin partial heating

Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device)

Note The number of days for storage after the dry pack has been opened. The storing conditions are

25 ˚C, 65% RH max.

Caution Do not use two or more soldering methods in combination (except partial heating).

71

µPD753012, 753016, 753017

APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST

Parameter

Program memory

µPD75316B

µPD753017

µPD75P3018

Mask ROM

0000H-3F7FH

(16256 × 8 bits)

Mask ROM

0000H-5FFFH

(24576 × 8 bits)

One-time PROM

0000H-7FFFH

(32768 × 8 bits)

Data memory

CPU

000H-3FFH

(1024 × 4 bits)

Standard CPU

75XL CPU

Instruction

execution

time

When main system

clock is selected

0.95, 1.91, 15.3 µs

(at 4.19 MHz operation)

•

0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation)

0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation)

When subsystem

clock is selected

122 µs (32.768 kHz operation)

connection

44

P12/INT2

P21

P12/INT2/TI1/TI2

P21/PTO1

47

48

P22/PCL

P30-P33

IC

P22/PCL/PTO2

50-53

P30/MD0-P33/MD3

57

V

PP

Stack

SBS register

None

SBS.3 = 1: Mk I mode selection

SBS.3 = 0: Mk II mode selection

Stack area

000H-0FFH

2-byte stack

n00H-nFFH (n = 0-3)

Subroutine call

instruction stack

operation

Mk I mode: 2-byte stack

Mk II mode: 3-byte stack

Instruction

BRA !addr1

CALLA !addr1

Unavailable

Mk I mode: unavailable

Mk II mode: available

MOVT XA, @BCDE

MOVT XA, @BCXA

BR BCDE

Available

BR BCXA

CALL !addr

3 machine cycles

2 machine cycles

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles

Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

CALLF !faddr

Timer

3 channels

5 channels

• Basic interval timer:

1 channel

• 8-bit timer/event counter:

1 channel

• Basic interval timer/watchdog timer: 1 channel

• 8-bit timer/event counter: 3 channels

(can be used as 16-bit timer/event counter, carrier generator,

or timer with gate)

• Watch timer: 1 channel

72

µPD753012, 753016, 753017

Parameter

Clock output (PCL)

µPD75316B

µPD753017

µPD75P3018

Φ, 524, 262, 65.5 kHz

(Main system clock:

at 4.19 MHz operation)

• Φ, 524, 262, 65.5 kHz

(Main system clock: at 4.19 MHz operation)

• Φ, 750, 375, 93.8 kHz

(Main system clock: at 6.0 MHz operation)

BUZ output

2 kHz

• 2, 4, 32 kHz

(Main system clock:

at 4.19 MHz operation)

(Main system clock: at 4.19 MHz operation or

subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz

(Main system clock: at 6.0 MHz operation)

Serial interface

3 modes are available

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit

• 2-wire serial I/O mode

• SBI mode

SOS

register

Feedback resistor cut flag

(SOS.0)

None

Provided

Sub-oscillator current cut

flag (SOS.1)

Register bank selection register (RBS)

Standby release by INT0

Vectored interrupt

None

Yes

No

Yes

External: 3, internal: 3

External: 3, internal: 5

Supply voltage

V

DD = 2.0 to 6.0 V

= –40 to +85˚C

VDD = 2.2 to 5.5 V

Operation ambient temperature

Package

T

A

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

• 80-pin plastic QFP (14 × 14 mm)

73

µPD753012, 753016, 753017

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD753017. The 75XL series

uses a common relocatable assembler, in combination with a device file matching each machine.

Language processor

RA75X relocatable assembler

Part Number

Host Machine

(product name)

OS

Distribution media

3.5-inch 2HD

5-inch 2HD

PC-9800 series

MS-DOS^TM

Ver. 3.30 to

Ver. 6.2^Note

µS5A13RA75X

µS5A10RA75X

IBM PC/AT^TMand

compatible machines

Refer to

3.5-inch 2HC

5-inch 2HC

µS7B13RA75X

µS7B10RA75X

OS for IBM PC

Device file

Part Number

(product name)

Host Machine

OS

Distribution media

3.5-inch 2HD

5-inch 2HD

PC-9800 series

MS-DOS^TM

Ver. 3.30 to

Ver. 6.2^Note

µS5A13DF753017

µS5A10DF753017

3.5-inch 2HC

5-inch 2HC

µS7B13DF753017

µS7B10DF753017

IBM PC/AT and

compatible machines

Refer to

OS for IBM PC

Note Ver. 5.00 and later have the task swap function, but cannot be used for this software.

Remark

The operation of the assembler and device file is guaranteed only on the above host machines and

OSs.

74

µPD753012, 753016, 753017

PROM write tools

Hardware

PG-1500

PG-1500 is a PROM programmer which enables you to program single chip microcomputers

containing PROM by stand-alone or host machine operation by connecting an attached

board and optional programmer adapter to PG-1500.

It also enables you to program typical PROM devices of 256K bits to 4M bits.

PA-75P316BGC

PA-75P316BGK

PG-1500 controller

PROM programmer adapter for µPD75P3018GC. Connect the programmer adapter to PG-

1500 for use.

PROM programmer adapter for µPD75P3018GK. Connect the programmer adapter to PG-

1500 for use.

Software

PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500

is controlled on the host machine.

Part number

(product name)

Host machine

OS

Distribution media

3.5-inch 2HD

5-inch 2HD

PC-9800 series

MS-DOS

Ver. 3.30 to

Ver. 6.2^Note

µS5A13PG1500

µS5A10PG1500

3.5-inch 2HC

5-inch 2HC

µS7B13PG1500

µS7B10PG1500

IBM PC/AT and

compatible machines

Refer to

OS for IBM PC

Note Ver.5.00 and later have the task swap function, but it cannot be used for this software.

Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

75

µPD753012, 753016, 753017

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

µPD753017.

The system configurations are described as follows.

Hardware

IE-75000-RNote1

In-circuit emulator for debugging the hardware and software when developing the

application systems that use the 75X series and 75XL series. When developing a

µPD753017 subseries, the emulation board IE-75300-R-EM and emulation probe that

are sold separately must be used with the IE-75000-R.

By connecting with the host machine and the PROM programmer, efficient debugging

can be made.

It contains the emulation board IE-75000-R-EM which is connected.

IE-75001-R

In-circuit emulator for debugging the hardware and software when developing the

application systems that use the 75X series and 75XL series. When developing a

µPD753017 sub-series, the emulation board IE-75300-R-EM and emulation probe which

are sold separately must be used with the IE-75001-R.

It can debug the system efficiently by connecting the host machine and PROM program-

mer.

IE-75300-R-EM

EP-753017GC-R

Emulation board for evaluating the application systems that use the µPD753017

subseries. It must be used with the IE-75000-R or IE-75001-R.

Emulation probe for the µPD753017GC.

It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates

connection to a target system.

EV-9200GC-80

EP-753017GK-R

Emulation probe for the µPD753017GK.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates

TGK-080SDW^{Note 2}connection to a target system.

Software

IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix

I/F and controls the above hardware on a host machine.

Host machine

Part number

(product name)

OS

Distribution media

PC-9800 series

MS-DOS

3.5-inch 2HD

5-inch 2HD

µS5A13IE75X

µS5A10IE75X

Ver. 3.30 to

Ver. 6.2^{Note 3}

3.5-inch 2HC

5-inch 2HC

µS7B13IE75X

µS7B10IE75X

IBM PC/AT and its

compatible machines

Refer to

OS for IBM PC

Notes 1. Maintenance parts

2. This is a product of Tokyo Eletech Corp. (Tokyo 03-5295-1661)

When purchasing this product, consult your NEC distributor.

3. Ver.5.00 and later have the task swap function, but it cannot be used for this software.

Remark The operation of the IE control program is guaranteed only on the above host machines and OSs.

76

µPD753012, 753016, 753017

OS for IBM PC

The following IBM PC OS’s are supported.

OS

Version

PC DOS^TM

Ver. 3.1 to Ver. 6.3

J6.1/V ^Noteto J6.3/V ^Note

MS-DOS

Ver. 5.0 to Ver. 6.22

5.0/V ^Noteto 6.2/V ^Note

IBM DOS^TM

J5.02/V ^Note

Note Only English version is supported.

Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software.

77

µPD753012, 753016, 753017

APPENDIX C RELATED DOCUMENTS

Some of the following related documents are preliminary.

Device Related Documents

Document No.

Document Name

Japanese

U10140J

U10956J

U11282J

IEM-5598

U10453J

English

U10140E (This manual)

U10956E

µPD753012, 753016, 753017 Data Sheet

µPD75P3018 Data Sheet

µPD753017 User’s Manual

µPD753017 Instruction

U11282E

–

75XL Series Selection Guide

U10453E

Development Tool Related Documents

Document No.

Document Name

Japanese

EEU-846

U11354J

EEU-967

U11940J

U12622J

U12385J

EEU-704

English

IE-75000 R/IE-75001-R User’s Manual

EEU-1416

U11354E

EEU-1494

U11940E

EEU-1346

EEU-1363

EEU-1291

IE-75300-R-EM User’s Manual

Hardware

EP-753017GC/GK-R User’s Manual

PG-1500 User’s Manual

RA75X Assembler Package

User’s Manual

Operation

Language

PG-1500 Controller User’s Manual

PC-9800 Series

(MS-DOS) Base

Software

IBM PC Series

(PC DOS) Base

EEU-5008

U10540E


型号：	UPD753012GC
厂家：	NEC
描述：	4-BIT SINGLE-CHIP MICROCONTROLLER 4位单片微控制器微控制器
文件：	总80页 (文件大小：563K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD753012GC [NEC]

相关型号：

UPD753012GC-XXX-3B9

UPD753012GK

UPD753012GK-XXX-BE9

UPD753016

UPD753016A

UPD753016AGC

UPD753016AGC-XXX-3B9

UPD753016AGC-XXX-3B9-A

UPD753016AGC-XXX-3B9-A

UPD753016AGC-XXX-8BT-A

UPD753016AGK

UPD753016AGK-XXX-9EU