UPD75308BGF_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75304B,75306B,75308B

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The µPD75308B is a 75X Series 4-bit single-chip microcomputer capable of the same data processing as an

8-bit microcomputer.

It is a low voltage operation version of the µPD75308 with on-chip LCD controller/driver. Operation at an

ultra-low voltage of 2.0 V is possible. An ultra small-sized plastic QFP (12 × 12 mm) is also provided and it is

perfect for small-sized set that uses an LCD panel.

Functions, etc., are described in detail in the User's Manual. Please be sure to read this manual when

carrying out design work.

µPD75308 User's Manual: IEM-5016

FEATURES

• Ultra-low-voltage operation possible: VDD = 2.0 to 6.0 V

• Can be driven by two 1.5 V manganese batteries.

• On-chip memory

• Program memory (ROM) : 8064 × 8 bit (µPD75308B)

: 6016 × 8 bit (µPD75306B)

: 4096 × 8 bit (µPD75304B)

• Data memory (RAM)

: 512 × 4 bit

• Instruction execution time adjustment function convenient in high-speed operation and power saving

• 0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation)

• 122 µs (32.768 kHz operation)

• Built-in programmable LCD controller/driver

• LCD drive voltage: 2.0 V to V^DD

• An ultra small-sized plastic QFP (12 × 12 mm) is provided.

• Suitable for small-sized set, such as a camera.

• On-chip PROM products available

• On-chip one-time PROM products : µPD75P308, 75P316A

• On-chip EPROM products

: µPD75P308, 75P316B

APPLICATIONS

Remote control, integrated camera type VCR, camera, gas meter, etc.

Unless there are any particular functional differences, the µPD75308B is described in this document as a

representative product.

The information in this document is subject to change without notice.

Document No. IC-2913C

The mark ★ shows major revised points.

(O. D. No. IC-8082D)

Date Published January 1994 P

Printed in Japan

µPD75304B,75306B,75308B

ORDERING INFORMATION

Ordering Code

Package

Quality Grade

µPD75304BGC-×××-3B9

µPD75304BGF-×××-3B9

µPD75304BGK-×××-BE9

µPD75306BGC-×××-3B9

µPD75306BGF-×××-3B9

µPD75306BGK-×××-BE9

µPD75308BGC-×××-3B9

µPD75308BGF-×××-3B9

µPD75308BGK-×××-BE9

80-pin plastic QFP (■14 mm)

80-pin plastic QFP (14 × 20 mm)

Standard

80-pin plastic TQFP(fine pitch)(■12 mm)

80-pin plastic QFP (■14 mm)

80-pin plastic QFP (14 × 20 mm)

80-pin plastic TQFP(fine pitch)(■12 mm))

80-pin plastic QFP (■14 mm)

Standard

80-pin plastic QFP (14 × 20 mm)

80-pin plastic TQFP(fine pitch)(■12 mm)

Remarks ××× is the ROM code number.

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

µPD75304B,75306B,75308B

FUNCTION OUTLINE (1/2)

Item

Function

Number of basic instructions

41

0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation)

122 µs (subsystem clock: 32.768 kHz operation)

Instruction cycle

ROM

8064 × 8 bits (µPD75308B), 6016× 8 bits (µPD75306B), 4096× 8 bits (µPD75304B)

512 × 4 bits

On-chip memory

RAM

• 4-bit manipulation: 8 (B, C, D, E, H, L, X, A)

• 8-bit manipulation: 4 (BC, DE, HL, XA)

General register

• Bit accumulator (CY)

• 4-bit accumulator (A)

• 8-bit accumulator (XA)

Accumulators

Instruction set

• Various bit manipulation instructions

• Efficient 4-bit data manipulation instructions

• 8-bit data transfer instructions

• GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1

byte

8

CMOS input

Pull-up by software possible : 23

16

CMOS input/output

40

I/O lines

8

CMOS output

Used with segment pin

N-ch open-drain

input/output

10 V withstand voltage, pull-up by mask option

possible : 8

• Number of segments selection: 24/28/32 segments (4/8 can be switched at bit

port output.)

• Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),

1/4 duty

LCD controller/driver

Supply voltage range

• LCD drive division resistor can be incorporated by mask option

VDD = 2.0 to 6.0 V

• 8-bit timer/event counter

• Clock source: 4 stages

• Event count possible

Timer

3 channels

• 8-bit basic interval timer

• Standard clock generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms

(4.19 MHz operation)

• Watchdog timer application possible

3

µPD75304B,75306B,75308B

FUNCTION OUTLINE (2/2)

Item

Function

• Watch timer

• 0.5 seconds time interval generation

• Count clock source: Main system clock and subsystem clock

switchable

3 channels

Timer

• Fast watch mode (3.9 ms time interval generation)

• Buzzer output possible (2 kHz)

• Three modes application possible

• 3-wire serial I/O mode

• 2-wire serial I/O mode

• SBI mode

8-bit serial interface

Bit sequential buffer

Clock output function

• LSB top/MSB top switchable

Special bit manipulation memory: 16 bits

• Perfect for remote control application

Timer/event counter output (PTO0): Arbitrary frequency square wave output

Clock output (PCL): Φ, 524, 262, 65.5 kHz (4.19 MHz operation)

Buzzer output (BUZ): 2 kHz (4.19 MHz or 32.768 kHz operation)

• External: 3

• Internal: 3

Vectored interrupt

Test input

• External: 1

• Internal: 1

• Main system clock oscillation ceramic/crystal oscillation circuit: 4.194304 MHz

• Subsystem clock oscillation crystal oscillation circuit: 32.768 kHz

System clock oscillator

Standby

STOP/HALT mode

• 80-pin plastic QFP (14 × 20 mm)

• 80-pin plastic QFP (■14 mm)

Package

• 80-pin plastic TQFP (fine pitch) (■12 mm)

4

µPD75304B,75306B,75308B

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)...............................................................................................

6

8

2. BLOCK DIAGRAM............................................................................................................................

3. PIN FUNCTIONS ..............................................................................................................................

3.1 PORT PINS ..............................................................................................................................................

3.2 NON-PORT PINS .....................................................................................................................................

3.3 PIN INPUT/OUTPUT CIRCUITS ..............................................................................................................

3.4 RECOMMENDED CONNECTION OF UNUSED PINS .............................................................................

9

11

13

15

16

3.5

PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ...........................................................

4. MEMORY CONFIGURATION .......................................................................................................... 16

5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 21

5.1 PORTS .....................................................................................................................................................

5.2 CLOCK GENERATOR ...............................................................................................................................

5.3 CLOCK OUTPUT CIRCUIT .......................................................................................................................

5.4 BASIC INTERVAL TIMER ........................................................................................................................

5.5 WATCH TIMER ........................................................................................................................................

5.6 TIMER/EVENT COUNTER .......................................................................................................................

5.7 SERIAL INTERFACE .................................................................................................................................

5.8 LCD CONTROLLER/DRIVER ....................................................................................................................

5.9 BIT SEQUENTIAL BUFFER ......................................................................................................................

21

22

23

24

25

26

28

30

32

6. INTERRUPT FUNCTION ................................................................................................................. 32

7. STANDBY FUNCTION .................................................................................................................... 34

8. RESET FUNCTION .......................................................................................................................... 35

9. INSTRUCTION SET ......................................................................................................................... 37

10. MASK OPTION SELECTION ............................................................................................................ 45

11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 46

12. PACKAGE INFORMATION .............................................................................................................. 64

13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 67

APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS .............................................................. 70

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 72

APPENDIX C. RELATED DOCUMENTS .............................................................................................. 73

5

µPD75304B,75306B,75308B

1. PIN CONFIGURATION (TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1

2

3

4

5

6

7

8

9

P60/KR0

X2

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

60

59

58

X1

57

56

55

54

53

52

NC

XT2

XT1

µ

VDD

P33

P32

10

11

12

13

14

15

16

17

18

19

20

51

50

49

48

47

46

45

44

43

42

41

P31/SYNC

P30/LCDCL

P23/BUZ

P22/PCL

P21

S22

S23

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

P20/PTO0

P13/TI0

P12/INT2

P11/INT1

P10/INT0

P03/SI/SB1

S31/BP7

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

6

µPD75304B,75306B,75308B

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P70/KR4

P63/KR3

S12

S13

1

2

64

63

S14

S15

S16

S17

S18

P62/KR2

P61/KR1

P60/KR0

X2

3

62

4

5

6

7

61

60

59

58

X1

µ

S19

S20

S21

S22

NC

XT2

XT1

8

9

57

56

55

54

53

52

51

50

49

48

47

46

45

10

11

12

13

14

15

16

17

18

19

20

VDD

S23

P33

P32

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

COM0

P31/SYNC

P30/LCDCL

P23/BUZ

P22/PCL

P21

P20/PTO0

P13/TI0

P12/INT2

P11/INT1

21

22

23

24

44

43

42

41

COM1

COM2

COM3

P10/INT0

P03/SI/SB1

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P00 to 03 : Port 0

P10 to 13 : Port 1

P20 to 23 : Port 2

P30 to 33 : Port 3

P40 to 43 : Port 4

P50 to 53 : Port 5

P60 to 63 : Port 6

P70 to 73 : Port 7

S0 to 31

: Segment Output 0 to 31

COM0 to 3 : Common Output 0 to 3

V^LC0-2

BIAS

LCDCL

SYNC

TI0

PTO0

BUZ

PCL

INT0, 1, 4

INT2

X1, 2

XT1, 2

NC

: LCD Power Supply 0 to 2

: LCD Power Supply Bias Control

: LCD Clock

: LCD Synchronization

: Timer Input 0

: Programmable Timer Output 0

: Buzzer Clock

: Programmable Clock

: External Vectored Interrupt 0, 1, 4

: External Test Input 2

: Main System Clock Oscillation 1, 2

: Subsystem Clock Oscillation 1, 2

: No Connection

BP0 to 7

KR0 to 7

SCK

: Bit Port

: Key Return

: Serial Clock

: Serial Input

: Serial Output

: Serial Bus 0, 1

: Reset Input

SI

SO

SB0,1

RESET

7

µPD75304B,75306B,75308B

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

Dual-

Function Pin

After

Reset

I/O Circuit

Type *1

Function

Pin Name

Input/Output

8-bit I/O

INT4

SCK

SO/SB0

SI/SB1

INT0

INT1

INT2

TI0

B

P00

P01

Input

4-bit input port (PORT 0)

On-chip pull-up resistor can be specified for

P01 to P03 as a 3-bit unit by software.

F - A

F - B

M - C

Input/output

×

Input

P02

P03

With noise elimination function

P10

P11

4-bit input port (PORT 1)

On-chip pull-up resistor can be specified as a

4-bit unit by software.

B - C

E - B

Input

×

P12

P13

PTO0

—

P20

P21

4-bit input/output port (PORT 2)

On-chip pull-up resistor can be specified as a

4-bit unit by software.

Input/output

PCL

P22

BUZ

LCDCL

SYNC

—

P23

P30 *2

P31 *2

P32 *2

P33 *2

Programmable 4-bit input/output port (PORT 3)

Input/output can be specified bit-wise.

On-chip pull-up resistor can be specified as a

4-bit unit by software.

—

High level (on-

chip pull-up

resistor) or high-

impedance

N-ch open-drain 4-bit input/output port (PORT

4)

On-chip pull-up resistor can be specified bit-

wise (mask option).

—

M

Input/output

P40 to P43 *2

P50 to P53 *2

Open-drain: 10 V withstand voltage

High level (on-

chip pull-up

resistor) or high-

impedance

N-ch open-drain 4-bit input/output port (PORT

5)

On-chip pull-up resistor can be specified bit-

wise (mask option).

Open-drain: 10 V withstand voltage

*

1.

: Schmitt trigger input

2. LED direct drive possible

9

µPD75304B,75306B,75308B

3.1 PORT PINS (2/2)

After

Reset

Dual-

Function Pin

I/O Circuit

Type *1

Pin Name

Function

Input/Output

Input/output

8-bit I/O

P60

P61

P62

P63

P70

P71

P72

P73

BP0

BP1

BP2

BP3

BP4

BP5

BP6

BP7

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

S24

S25

S26

S27

S28

S29

S30

S31

Programmable 4-bit input/output port (PORT 6)

Input/output can be specified bit-wise.

On-chip pull-up resistor can be specified as a

4-bit unit by software.

Input

F - A

4-bit input/output port (PORT 7)

On-chip pull-up resistor can be specified as a

4-bit unit by software.

Input/output

F - A

Output

1-bit output port (BIT PORT)

Also used as segment output pin.

×

* 2

G - C

Output

*

1.

: Schmitt trigger input

2. BP0 to BP7 select V^LC1as the input source.

However, the output level depends on BP0 to BP7 and VLC1 external circuit.

Example BP0 to BP7 are connected mutually within the µPD75308B. Therefore, the output level of BP0 to BP7

is determined by the value of R¹, R2 and R3.

µPD75308B

V

DD

R2

BP0

BP1

ON

V

LC1

R1

R3

10

µPD75304B,75306B,75308B

3.2 NON-PORT PINS

Dual-

Function Pin

I/O Circuit

Type *1

After

Reset

Input/Output

Pin Name

Function

Input

P13

P20

P22

B - C

E - B

TI0

PTO0

PCL

External event pulse input pin to timer/event counter

Timer/event counter output pin

Clock output pin

Input

Input/output

Fixed frequency output pin (for buzzer or system clock

trimming)

E - B

F - A

F - B

Input

P23

P01

BUZ

SCK

Input/output

Serial clock input/output pin

Serial data output pin

Serial bus input/output pin

P02

P03

SO/SB0

SI/SB1

Input/output

Serial data input pin

Serial bus input/output pin

Input

M - C

B

Edge detection vectored interrupt input pin (both rising

edge and falling edge detection effective)

P00

P10

INT4

Input

Clock synchronous

system

Edge detection vectored

interrupt input pin (detection

INT0

INT1

Input

B - C

edge selectable)

Asynchronous

P11

P12

Edge detection testable input

pin (rising edge detection)

INT2

Asynchronous

Input/output

Output

P60 to P63

P70 to P73

—

F - A

G - A

G - C

G - B

KR0 to KR3

KR4 to KR7

S0 to S23

Parallel falling edge detection testable input pin

Segment signal output pin

Input

*2

Output

BP0 to BP7

—

S24 to S31

Segment signal output pin

*2

Output

COM0 to COM3

Common signal output pin

*2

LCD drive power supply pin

On-chip split resistor (mask option)

V^LC0to V^LC2

—

Output

—

BIAS

External split resistor cut output pin

*3

Input/output

P30

E - B

LCDCL *4

External expansion driver drive clock output pin

Input

External expansion driver synchronization clock output

P31

—

Input/output

Input

—

E - B

—

SYNC *4

Main system clock oscillation crystal/ceramic connection

pin. For external clock, the external clock signal is input

to X1 and its opposite phase is input to X2.

X1, X2

Subsystem clock oscillation crystal connection pin. For

external clock, the external clock signal is input to XT1

and XT2 is opened. XT1 can be used as a 1-bit input

(test) pin.

XT1

XT2

Input

—

B

System reset input pin

NO CONNECTION

—

RESET

Input

—

NC *5

—

V^DD

VSS

—

Positive power supply pin

GND potential pin

*

1.

: Schmitt trigger input

2. Display outputs are selected with VLCX shown below as the input source.

S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0

However, the level of each display output depends on the display output and VLCX external circuit.

11

µPD75304B,75306B,75308B

*

3. On-chip split resistor ........ Low level

No on-chip split resistor ... High-impedance

4. Pins provided for system expansion. Currently, only used as P30 and P31.

5. If a printed wiring board is shared with the µPD75P316A/75P316B, the NC pin should be connected to

V^DD.

12

µPD75304B,75306B,75308B

3.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuits of each pin of the µPD75308B are shown by in abbreviated form.

TYPE D (For TYPE E-B, F-A)

TYPE A (For TYPE E-B)

V

DD

V^DD

data

P-ch

OUT

IN

output

disable

N-ch

Push-pull output that can be made high-impedance output

(P-ch and N-ch OFF)

CMOS Standard Input Buffer

TYPE B

TYPE E-B

VDD

P.U.R.

enable

P-ch

data

IN/OUT

IN

Type D

Type A

output

disable

P.U.R.

:

Pull-Up Resistor

Schmitt-Trigger Input with Hysteresis Characteristic

TYPE B-C

TYPE F-A

VDD

P.U.R.

VDD

P.U.R.

enable

P.U.R.

P-ch

P.U.R.

enable

data

P-ch

IN/OUT

Type D

Type B

output

disable

IN

P.U.R. : Pull-Up Resistor

P.U.R.

:

Pull-Up Resistor

13

µPD75304B,75306B,75308B

TYPE F-B

TYPE G-C

V

DD

P.U.R.

P-ch

VDD

P.U.R.

enable

P-ch

V

DD

V

LC0

output

disable

(P)

P-ch

V

LC1

IN/OUT

data

P-ch

SEG

output

disable

OUT

N-ch

data/Bit Port data

output

disable

(N)

V

LC2

N-ch

P.U.R.

:

Pull-Up Resistor

TYPE G-A

TYPE M

V

DD

P.U.R.

enable

(Mask Option)

IN/OUT

V^LC0

P-ch

data

VLC1

N-ch

P-ch

output

disable

SEG

data

OUT

N-ch

VLC2

N-ch

Middle-High Voltage Input Buffer

(+10 V Withstand Voltage)

P.U.R.

:

Pull-Up Resistor

TYPE G-B

TYPE M-C

VDD

V

LC0

P-ch

P.U.R.

P-ch

IN/OUT

VLC1

P.U.R.

enable

N-ch

P-ch

OUT

data

N-ch

COM

data

output

disable

N-ch P-ch

VLC2

N-ch

P.U.R.

:

Pull-Up Resistor

14

µPD75304B,75306B,75308B

3.4 RECPMMENDED CONNECTION OF UNUSED PINS

★

Table 3-1 Connection of Unused Pins

Recommended Connection

Connect to VSS

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

Connect to VSS or VDD

Connect to VSS

P10/INT0-P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30/LCDCL

P31/SYNC

Input state

:

Connect to VSS or VDD

Outputstate : Leave open

P32

P33

P40 to P43

P50 to P53

P60/KR0 to P63/KR3

P70/KR4 to P73/KR7

S0 to S23

S24/BP0 to S31/BP7

COM0 to COM3

VLC0 to VLC2

Leave open

Connect to VSS

Connect to VSS only when VLC0 to VLC2

are all unused; otherwise leave open

BIAS

XT1

XT2

Connect to V_SSor V_DD

Leave open

15

µPD75304B,75306B,75308B

★

3.5

PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN

In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the

test mode for testing internal µPD75308B operation (for IC testing).

The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if

noise exceeding V^DDis applied during normal operation, the test mode may be entered, making it impossible

for normal operation to continue.

For example, misoperation may result if inter-wiring noise is applied to the P00/INT4 or RESET pin due to

the length of the wiring from these pins, and the pin voltage exceeds V^DD.

Wiring should therefore be carried out so that inter-wiring noise is suppressed as far as possible. If it is

completely impossible to suppress noise, noise prevention measures should be taken using an external compo-

nent as shown below.

o Diode connected between

o Capacitor connected between

P00/INT4 or RESET and V^DD

VDD

Diode with

Small VF

VDD

V^DD

P00/INT4, RESET

4. MEMORY CONFIGURATION

• Program memory (ROM) ... 8064 × 8 bits (0000H to 1F7FH): µPD75308B

6016 × 8 bits (0000H to 177FH): µPD75306B

4096 × 8 bits (0000H to 0FFFH): µPD75304B

• 0000H to 0001H: Vector table in which the program start address after a reset is written.

• 0002H to 000BH: Vector table in which program start addresses in case of interrupts are written.

• 0020H to 007FH: Table area referenced by the GETI instruction.

• Data memory

• Data area ... 512 × 4 bits (000H to 1FFH)

• Peripheral hardware area ... 128 × 4 bits (F80H to FFFH)

16

µPD75304B,75306B,75308B

Fig. 4-1 Program Memory Map

(a) µPD75308B

Address

7

6

0

5

0

0000H MBE

0002H MBE

0004H MBE

0006H MBE

0008H MBE

000AH MBE

Internal Reset Start Address (High-Order 5 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 5 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0 Start Address (High-Order 5 Bits)

INT0 Start Address (Low-Order 8 Bits)

INT1 Start Address (High-Order 5 Bits)

INT1 Start Address (Low-Order 8 Bits)

INTCSI Start Address (High-Order 5 Bits)

INTCSI Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 5 Bits)

INTT0 Start Address (Low-Order 8 Bits)

0

CALL !addr

Instruction

Subroutine

Entry Address

CALLF

! faddr

Instruction

Entry

Address

BR !addr

Instruction

Branch Address

BRCB

! caddr

Instruction

Branch

Address

BR $addr

Instruction

Relative

Branch Address

(-15 to -1,

≈

+2 to +16)

0020H

GETI Instruction Reference Table

007FH

0080H

Branch Destination

Address and

Subroutine Entry Address

by GETI Instruction

≈

07FFH

0800H

≈

0FFFH

1000H

BRCB

! caddr

Instruction

Branch

Address

≈

1F7FH

17

µPD75304B,75306B,75308B

(b) µPD75306B

Address

7

6

0

5

0

0000H MBE

0002H MBE

0004H MBE

0006H MBE

0008H MBE

000AH MBE

Internal Reset Start Address (High-Order 5 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 5 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0 Start Address (High-Order 5 Bits)

INT0 Start Address (Low-Order 8 Bits)

INT1 Start Address (High-Order 5 Bits)

INT1 Start Address (Low-Order 8 Bits)

INTCSI Start Address (High-Order 5 Bits)

INTCSI Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 5 Bits)

INTT0 Start Address (Low-Order 8 Bits)

0

CALL !addr

Instruction

Subroutine

Entry Address

CALLF

! faddr

Instruction

Entry

Address

BR !addr

Instruction

Branch Address

BRCB

! caddr

Instruction

Branch

Address

BR $addr

Instruction

Relative

≈

Branch Address

(-15 to -1,

+2 to +16)

0020H

GETI Instruction Reference Table

007FH

0080H

Branch Destination

Address and

Subroutine Entry Address

by GETI Instruction

≈

07FFH

0800H

≈

0FFFH

1000H

BRCB

! caddr

Instruction

Branch

Address

≈

177FH

18

µPD75304B,75306B,75308B

(c) µPD75304B

Address

7

6

0

5

0

0000H MBE

0002H MBE

0004H MBE

0006H MBE

0008H MBE

000AH MBE

Internal Reset Start Address (High-Order 4 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 4 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0 Start Address (High-Order 4 Bits)

INT0 Start Address (Low-Order 8 Bits)

INT1 Start Address (High-Order 4 Bits)

INT1 Start Address (Low-Order 8 Bits)

INTCSI Start Address (High-Order 4 Bits)

INTCSI Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 4 Bits)

INTT0 Start Address (Low-Order 8 Bits)

0

CALL !addr

Instruction

Subroutine

Entry Address

CALLF

! faddr

Instruction

Entry

Address

BR !caddr

Instruction

Branch Address

BR $addr

Instruction

Relative

Branch Address

(-15 to -1,

≈

+2 to +16)

0020H

GETI Instruction Reference Table

007FH

0080H

Branch Destination

Address and

Subroutine Entry Address

by GETI Instruction

≈

07FFH

0800H

≈

0FFFH

19

µPD75304B,75306B,75308B

Fig. 4-2 Data Memory Map

Data Memory

Memory Bank

000H

General

Register Area

(8 × 4)

007H

008H

0

Stack Area

256 × 4

(248 × 4)

0FFH

100H

Data Area

Static RAM

(512 × 4)

256 × 4

(224 × 4)

1

1DFH

1E0H

Display Data Memory Area

(32 × 4)

1FFH

Not On-Chip

F80H

Peripheral Hardware Area

15

128 × 4

FFFH

20

µPD75304B,75306B,75308B

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

There are four kinds of I/O ports, as follows.

• CMOS input (PORT0, 1)

: 8

• CMOS input/output (PORT2, 3, 6, 7) : 16

• N-ch open drain (PORT4, 5)

• CMOS output (BP0 to BP7)

:

8

Total

40

Fig. 5-1 Port Functions

Port (Symbol)

Function

Operation/Features

Remarks

Dual function as INT4, SCK, SO/

SB0 & SI/SB1 pins

PORT 0

PORT 1

PORT 2

PORT 7

PORT 3 *

PORT 6

Always readable or testable irrespective of

dual-function pin operating mode.

4-bit input

Dual function as pins INT0 to

INT2 & TI0

Dual function as PTO0, PCL &

BUZ pins

Can be set to input or output mode as 4-bit

unit. Ports 6 & 7 can be paired for 8-bit data

input/output.

Dual function as pins KR4 to

KR7

4-bit input/output

Dual function as LCDCL & SYNC

pins

Can be set to input or output mode bit-wise.

Dual function as pins KR0 to

KR3

4-bit input/output

(N-ch open-drain

10 V withstand

voltage)

Incorporation of pull-up resistor

can be specified bit-wise by

mask option.

Can be set to input or output mode as 4-bit

unit. Ports 4 & 5 can be paired for 8-bit data

input/output.

PORT 4 *

PORT 5 *

Outputs data bit-wise. Switchable by

software with LCD drive segment outputs

S24 to S31.

Small drive capability.

For CMOS load drive.

BP0 to BP7

1-bit output

*

Direct LED drive capability

21

µPD75304B,75306B,75308B

5.2 CLOCK GENERATOR

The operation of the clock generator is determined by the processor clock control register (PCC) and system

clock control register (SCC).

There are two kinds of clock, the main system clock and subsystem clock, and the instruction execution time

can be changed.

• 0.95 µs/1.91 µs/15.3 µs (4.19 MHz main system clock operation)

• 122 µs (32.768 kHz subsystem clock operation)

Fig. 5-1 Clock Generator Block Diagram

• Basic Interval Timer (BT)

• Timer/Event Counter

• Serial Interface

XT1

V

DD

Subsystem

Clock Oscil-

lation Circuit

LCD Controller/

Driver

Watch Timer

f

XT

• Watch Timer

• LCD Controller/Driver

• INT0 Noise Elimination Circuit

• Clock Output Circuit

XT2

X1

V

DD

Main System

Clock Oscil-

lation Circuit

fX

1/8 to 1/4096

Frequency Divider

X2

1/2 1/16

Oscil-

lation

Stop

WM. 3

SCC

Frequency

Divider

SCC3

Φ

1/4

SCC0

PCC

• CPU

• INT0 Noise

Elimination Circuit

• Clock Output Circuit

PCC0

PCC1

PCC2

PCC3

4

HALT F/F

S

HALT *

STOP *

R

Q

PCC2,

PCC3

Clear

Wait Release Signal from BT

RESET Signal

STOP F/F

Q

S

R

Standby Release Signal from

Interrupt Control Circuit

Remarks 1. fX = Main system clock frequency

2. f^XT= Subsystem clock frequency

3. PCC: Processor clock control register

4. SCC: System clock control register

5. * indicates instruction execution.

6. One Φ clock cycle (tCY) is one machine cycle. See "AC CHARACTERISTICS" in 11. "ELECTRICAL

SPECIFICATIONS" for details of t^CY.

★

22

µPD75304B,75306B,75308B

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit is a circuit which outputs a clock pulse from P22/PCL pin and is used to supply clock

pulses to remote control outputs or peripheral LSI’s.

• Clock output (PCL) : Φ 524, 262, 65.5 kHz (at 4.19 MHz operation)

• Buzzer output (BUZ): 2 kHz (at 4.19 MHz or 32.768 kHz operation)

The configuration of the clock output circuit is shown below.

Fig. 5-2 Clock Output Circuit Configuration

From Clock

Generator

Φ

/2³

/2⁴

Output Buffer

f

X

Selector

f

PCL/P22

fX

/2⁶

PORT2.2

Bit 2 of PMGB

Bit Specified

P22

Output Latch

In Port 2

Input/Output

Mode

CLOM3

0

CLOM1 CLOM0CLOM

4

Internal Bus

Remarks Consideration is given so that a low amplitude pulse is not output when switching between clock

output enable and disable.

23

µPD75304B,75306B,75308B

5.4 BASIC INTERVAL TIMER

The basic interval timer includes the following functions.

• It operates as an interval timer which generates reference time interrupts.

• It can be applied as a watchdog timer which detects when a program is out of control.

• Selects and counts wait times when the standby mode is released.

• It reads count contents.

Fig. 5-3 Basic Interval Timer Configuration

From Clock

Generator

Clear

f

X

/2⁵

/2⁷

Set

Basic Interval Timer

(8-Bit Frequency Divider)

BT Interrupt

Request Flag

MPX

Vectored

Interrupt

Request

Signal

f

X

/2⁹

/2¹²

BT

IRQBT

3

Wait Release

Signal During

Standby Release

BTM3

BTM2

BTM1

BTM0

BTM

*SET1

4

8

Internal Bus

Remarks * indicates instruction execution.

24

µPD75304B,75306B,75308B

5.5 WATCH TIMER

The µPD75308B incorporates a single watch timer channel. The watch timer has the following functions.

• Sets test flags (IRQW) at 0.5 second intervals. The standby mode can be released with IRQW.

• 0.5 sec. time intervals can be created in either the main system clock or the subsystem clock.

• In the fast watch mode, time intervals which are 128 times normal (3.91 ms) can be set, making this

function convenient for program debugging and testing.

• A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin for use in generating buzzer sounds and

trimming system clock oscillation frequencies.

• The frequency divider can be cleared, so this clock can be started at 0 second.

Fig. 5-4 Watch Timer Block Diagram

f

W

2⁶

(512 Hz : 1.95 ms)

f

LCD

f

W

2⁷

(256 Hz : 3.91 ms)

INTW

IRQW

Set Signal

f

W

Selector

f

W

2¹⁴

128

(32.768 kHz)

From

Clock

Generator

f

W

Selector

Frequency Divider

Clear

(32.768 kHz)

2Hz

f

XT

0.5 sec

(32.768 kHz)

f

16

W

(2.048 kHz)

Output Buffer

P23/BUZ

WM

PORT2.3

Bit 2 of PMGB

P23

Port 2

Input/Output

Mode

Output

WM7

0

8

WM3 WM2

WM1

WM0

Latch

Bit Test Instruction

Internal Bus

Remarks Values in parentheses are when f^X= 4.194304 MHz and fXT = 32.768 kHz.

25

µPD75304B,75306B,75308B

5.6 TIMER/EVENT COUNTER

The µPD75308B incorporates a single timer/event counter channel. The timer/event counter has the following

functions.

• Operates as a programmable interval timer.

• Outputs square waves in the desired frequency to the PTO0 pin.

• Operates as an event counter.

• Divides the TI0 pin input into N divisions and outputs it to the PTO0 pin (frequency divider operation).

• Supplies a serial shift clock to the serial interface circuit.

• Count status read function.

26

µPD75304B,75306B,75308B

5.7 SERIAL INTERFACE

The µPD75308B incorporates a clocked 8-bit serial interface. The serial interface has the following three

modes.

• 3-wire serial I/O mode

• 2-wire serial I/O mode

• SBI mode (serial bus interface mode)

28

µPD75304B,75306B,75308B

5.8 LCD CONTROLLER/DRIVER

The µPD75308B has an on-chip display controller which generates segment signals and common signals in

accordance with data in display data memory as well as a segment driver and common driver capable of

directly driving the LCD panel.

The configuration of the LCD controller/driver is shown in Fig. 5-7

The functions of the on-chip LCD controller/driver of the µPD75308B are as follows.

• Display data memory are read automatically through DMA operations and segment signals and common

signals are generated.

• 5 different display modes can be selected.

➀ Static

➁ 1/2 duty (1/2 bias)

➂ 1/3 duty (1/2 bias)

4 1/3 duty (1/3 bias)

➄ 1/4 duty (1/3 bias)

• In each of the display modes, 4 types of frame frequency can be selected.

• The segment signal output is a maximum of 32 segments (S0 to S31) and 4 common outputs (COM0 to

COM3).

• Segment signal outputs (S24 to S27, S28 to S31) are in 4-segment units and they can be switched for use

as output ports (BP0 to BP3, BP4 to BP7).

• Split resistors can be built-in for the LCD driver power supply (mask option).

•

Conformity to various bias methods and LCD driver voltages is possible.

When the display is OFF, the current flowing to the split resistors is cut.

• Display data memory not used for the display can be used as ordinary data memory.

• Operation by the subsystem clock is also possible.

.

30

µPD75304B,75306B,75308B

5.9 BIT SEQUENTIAL BUFFER ..... 16 BITS

The bit sequential buffer is special data memory for bit manipulations and can be used easily particularly for

bit manipulations where addresses and bit specifications are changed sequentially, so it is convenient for

processing data with long bit lengths bit-wise.

Fig. 5-8 Bit Sequential Buffer Format

FC3H

2

FC2H

2

FC1H

3

FC0H

3

Address

Bit

3

1

0

3

1

0

2

1

0

2

1

0

Symbol

BSB3

BSB2

BSB1

BSB0

L Register

L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

DECS L

INCS L

Remarks In pmem.@L addressing, the specified bit corresponding to the L register is moved.

6. INTERRUPT FUNCTION

The µPD75218has 8 interrupt sources, and prioritized multiple interrupts are possible.

There are also two test sources, of which INT2 is an edge-detected testable input.

The µPD75218 interrupt control circuit has the following functions

• Hardware control vectored interrupt function that can control interrupt acceptance by interrupt flag

(IE×××) and interrupt master enable flag (IME).

• Arbitrary setting of interrupt start address.

• Multiple interrupt function with priority specifiable by the interrupt priority selection register (IPS).

• Interrupt request flag (IRQ×××) test function (interrupt generation confirmation by software possible).

• Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag

possible).

32

µPD75304B,75306B,75308B

7. STANDBY FUNCTION

To reduce the power consumption during program wait, the µPD75308B has two standby modes: STOP

mode and HALT mode.

Table 7-1 Operation Status at Standby Mode

STOP Mode

STOP instruction

HALT Mode

HALT instruction

Setting instruction

Main system clock or subsystem

clock settable

Only main system clock settable

System clock at setting

Only main system clock oscillation

stopped

Only CPU clock Φ stopped

Clock oscillator

(oscillation continued)

Operating (IRQBT set at reference time

Basic interval timer

Stopped

intervals)*

Operable only when external SCK

input selected as serial clock

Operable*

Serial interface

Operable only when TI0 pin input

specified as count clock

Timer/event counter

Operable only when fXT selected as

count clock

Operable

Watch timer

Operable only when fXT selected as

LCDCL

LCD controller

INT1, 2, 4: Operable

Only INT0 inoperable

External interrupt

CPU

Stopped

Interrupt request signal from operable

hardware enabled by interrupt enable

flag, or RESET input

Interrupt request signal from operable

hardware enabled by interrupt enable

flag, or RESET input

Release signal

*

In-operable only with main system clock oscillation stopped.

34

µPD75304B,75306B,75308B

8. RESET FUNCTION

The µPD75308B is reset and the hardware is initialized as shown in Table 8-1 by RESET input. The reset

operation timing is shown in Fig. 8-1.

Fig. 8-1 Reset Operation by RESET Input

Wait

(31.3 ms/4.19 MHz)

RESET Input

Operating Mode or Standby

Mode

HALT Mode

Operating Mode

Internal Reset Operation

Table 8-1 Status of Each Hardware after Resetting (1/2)

RESET Input in Standby

RESET Input during

Operation

Hardware

Mode

Low-order 5(4)*1 bits of

program memory address

0000H are set in PC12(11)*1

to 8 and the contents of

address 0001H are set in

PC7 to 0.

Low-order 5(4)*1 bits of

program memory address

0000H are set in

Program counter (PC)

Carry flag (CY)

PC12(11)*1 to 8 and the

contents of address 0001H

are set in PC7 to 0.

Held

0

Undefined

0

Skip flag (SK0 to 2)

PSW

0

Interrupt status flag (IST0)

Bit 7 of program memory

address 0000H is set in

MBE.

Bit 7 of program memory

address 0000H is set in

MBE.

Bank enable flag (MBE)

Undefined

Stack pointer (SP)

Undefined

Data memory (RAM)

Held*2

General register

Undefined

0

Held

0

(X, A, H, L, D, E, B, C)

Bank selection register (MBS)

*

1. Figures in parentheses apply to the µPD75304B.

2. Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.

35

µPD75304B,75306B,75308B

Table 8-1 Status of Each Hardware after Resetting (2/2)

RESET Input in Standby

Mode

RESET Input during

Operation

Hardware

Undefined

Counter (BT)

Undefined

Basic interval

timer

0

Mode register (BTM)

0

Counter (To)

0

FFH

Modulo register (TMOD0)

Mode Register (TM0)

Timer/event

counter

FFH

0

0,0

TOE0, TOUT F/F

0,0

0

Mode register (WM)

Watch timer

0

Held

Shift register (SIO)

Undefined

Serial interface

0

Operating mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Processor clock control register (PCC)

System clock control register (SCC)

Clock output mode register (CLOM)

Display mode register (LCDM)

Display control register (LCDC)

Interrupt request flag (IRQ×××)

Interrupt enable flag (IE×××)

Interrupt master enable flag (IME)

INT0, 1, 2 mode registers (IM0, 1, 2)

Output buffer

0

Held

Undefined

0

Clock generator,

clock output

circuit

0

LCD controller

0

Reset (0)

0

Interrupt function

0, 0, 0

OFF

Clear (0)

0

0, 0, 0

OFF

Clear (0)

0

Output latch

Digital port

I/O mode register (PMGA, B)

Pull-up resistor specification register

(POGA)

0

Bit sequential buffer (BSB0 to 3)

Undefined

Held

36

µPD75304B,75306B,75308B

9. INSTRUCTION SET

(1) Operand identifier and description

The operand is described in the operand field of each instruction in accordance with the description for the

operand identifier of the instruction. (See the RA75X Assembler Package User's Manual Language Volume

(EEU-730) for details.) When there are multiple elements in the description, one of the elements is selected.

Upper case letters and symbols (+,–) are keywords and are described unchanged.

For immediate data, a suitable value or label is described.

Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (See the

µPD75308 User’s Manual (IEM-5016) for details). However, there are restrictions on the labels for which fmem

and pmem can be used (see the table on the previous page).

Identifier

Description

reg

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

regl

rp

XA, BC, DE, HL

BC, DE, HL

BC, DE

rpl

rp2

rpa

HL, DE, DL

DE, DL

rpal

n4

n8

4-bit immediate data or label

8-bit immediate data or label

mem*

8-bit immediate data or label

2-bit immediate data or label

bit

fmem

pmem

FB0H to FBFH, FF0H to FFFH immediate data or label

FC0H to FFFH immediate data or label

µPD75304B

µPD75306B

µPD75308B

0000H to 0FFFH immediate data or lebel

0000H to 177FH immediate data or lebel

0000H to 1F7FH immediate data or lebel

addr

caddr

faddr

taddr

12-bit immediate data or label

11-bit immediate data or label

20H to 7FH immediate data (however, bit0 = 0) or label

PORTn

IE×××

MBn

PORT 0 to PORT 7

IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW

MB0, MB1, MB15

*

Only an even address can be written for mem in the case of 8-bit data processing.

37

µPD75304B,75306B,75308B

(2) Operation description legend

A

: A register; 4-bit accumulator

B

: B register;

C

: C register;

D

: D register;

E

: E register;

H

: H register;

L

: L register;

X

: X register; 4-bit accumulator

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

XA

BC

DE

HL

PC

SP

CY

PSW

MBE

PORTn

IME

IE×××

MBS

PCC

•

: Register pair (DE)

: Register pair (HL)

: Program counter

: Stack pointer

: Carry flag; bit accumulator

: Program status word

: Memory bank enable flag

: Portn (n = 0 to 7)

: Interrupt master enable flag

: Interrupt enable flag

: Memory bank selection register

: Processor clock control register

: Address, bit delimiter

: Contents addressed by ××

: Hexadecimal data

(××)

××H

38

µPD75304B,75306B,75308B

(3) Description of addressing area field symbols

*1

*2

MB = MBE • MBS (MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (00H to 7FH)

MB = 15 (80H to FFH)

Data memory

addressing

*3

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H to FBFH,

FF0H to FFFH

*4

*5

MB = 15, pmem = FC0H to FFFH

µPD75304B

µPD75306B

µPD75308B

addr=0000H to 0FFFH

addr=0000H to 177FH

addr=0000H to 1F7FH

*6

*7

addr = (Current PC) –15 to (Current PC) –1

(Current PC) + 2 to (Current PC) + 16

µPD75304B

µPD75306B

caddr= 0000H to 0FFFH

Program memory

addressing

caddr= 0000H to 0FFFH (PC¹²=0) or

1000H to 177FH (PC12=1)

*8

caddr=0000H to 0FFFH (PC12=0) or

1000H to 1F7FH (PC12=1)

µPD75308B

faddr = 0000H to 07FFH

taddr = 0020H to 007FH

*9

*10

Remarks 1. MB indicates the accessible memory bank.

2. For *2, MB = 0 without regard to MBE and MBS.

3. For *4 and *5, MB = 15 without regard to MBE and MBS.

4. *6 to *10 indicate the addressable area.

(4) Explanation of machine cycle field

S shows the number of machine cycles required when skip is performed by an instruction with skip. The

value of S changes as follows:

• No skip ....................................................................................................................................................................... S = 0

• When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1

• When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instruction)............................. S = 2

Note One machine cycle is required to skip a GETI instruction.

One machine cycle is equivalent to one cycle (=t^CY) of the CPU clock Φ. Three times can be selected by PCC

setting.

39

µPD75304B,75306B,75308B

Address-

Mne-

Machine

Cycles

Note

Operand

Skip Condition

ing Area

Bytes

Operation

monic

A, #n4

A ← n4

Stack A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

regl, #n4

XA, #n8

HL, #n8

rp2, #n8

A, @HL

A, @rpal

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

regl ← n4

XA ← n8

Stack A

Stack B

HL ← n8

rp2 ← n8

*1

*2

*1

*3

A ← (HL)

A ← (rpal)

XA ← (HL)

(HL) ← A

MOV

(HL) ← XA

A ← (mem)

XA ← (mem)

(mem) ← A

(mem) ← XA

A ← reg

XA, rp

XA ← rp

regl, A

regl ← A

rpl, XA

rpl ← XA

A, @HL

A, @rpal

XA, @HL

A, mem

XA, mem

A,regl

*1

*2

*1

*3

A ↔ (HL)

A ↔ (rpal)

XA ↔ (HL)

A ↔ (mem)

XA ↔ (mem)

A ↔ regl

XCH

XA, rp

XA ↔ rp

● µPD75304B

XA ← (PC11–8 + DE)ROM

XA, @PCDE

XA, @PCXA

1

3

● µPD75306B, 75308B

XA ← (PC12–8 + DE)ROM

MOVT

ADDS

● µPD75304B

XA ← (PC11–8 + XA)ROM

● µPD75306B, 75308B

XA ← (PC12–8 + XA)ROM

A, #n4

carry

1

1 + S

1

A ← A + n4

A, @HL

*1

carry

A ← A + (HL)

ADDC

SUBS

SUBC

A, CY ← A + (HL) + CY

A ← A – (HL)

borrow

1 + S

1

A, CY ← A – (HL) – CY

Note Instruction Group

40

µPD75304B,75306B,75308B

Note Mne-

Machine

Cycles

Address-

Bytes

Operand

Operation

Skip Condition

1

monic

AND

OR

ing Area

A, #n4

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

A ← A n4

A ← A (HL)

A ← A n4

A ← A (HL)

A ← A n4

A ← A (HL)

A, @HL

A, #n4

*1

2

A, @HL

A, #n4

1

2

XOR

A, @HL

A

1

RORC

NOT

1

CY ← A⁰, A3 ← CY, An–1 ← An

A ← A

A

2

reg

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1

reg ← reg + 1

reg = 0

INCS

@HL

(HL) ← (HL) + 1

*1

*3

(HL) = 0

(mem) = 0

reg = FH

reg = n4

(HL) = n4

A = (HL)

A = reg

mem

(mem) ← (mem) + 1

reg ← reg – 1

DECS

reg

reg, #n4

@HL, #n4

A, @HL

A, reg

Skip if reg = n4

Skip if (HL) = n4

*1

SKE

Skip if A = (HL)

Skip if A = reg

SET1

CLR1

SKT

CY

CY ← 1

CY

1

CY ← 0

CY

1 + S

1

Skip if CY = 1

CY = 1

NOT1

CY

CY ← CY

mem.bit

fmem.bit

pmem.@L

@H + mem.bit

mem.bit

fmem.bit

pmem.@L

@H + mem.bit

mem.bit

fmem.bit

pmem.@L

@H + mem.bit

mem.bit

fmem.bit

pmem.@L

@H + mem.bit

2

(mem.bit) ← 1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

2

(fmem.bit) ← 1

SET1

CLR1

SKT

2

(pmem^7–2+ L3–2.bit (L1–0)) ← 1

(H + mem3–0.bit) ← 1

(mem.bit) ← 0

2

(fmem.bit) ← 0

2

(pmem7–2 + L3–2.bit (L1–0)) ← 0

(H + mem^3–0.bit) ← 0

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1

Skip if (H + mem3–0.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (pmem7–2 + L3–2.bit (L1–0)) = 0

Skip if (H + mem3–0.bit) = 0

2

2 + S

(mem.bit) = 1

(fmem.bit) = 1

(pmem.@L) = 1

(@H + mem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(pmem.@L) = 0

(@H + mem.bit) = 0

SKF

Note 1. Instruction Group

2. Accumulator operation

3. Increment and decrement

4. Carry flag operation

41

µPD75304B,75306B,75308B

Machine

Cycles

Address-

Mne-

Note

Bytes

Operand

Operation

Skip Condition

ing Area

monic

fmem.bit

2

2 + S Skip if (fmem.bit) = 1 and clear

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

(fmem.bit) = 1

pmem.@L

2 + S Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1 and clear

2 + S Skip if (H + mem^3–0.bit) = 1 and clear

(pmem.@L) = 1

(@H + mem.bit) = 1

SKTCLR

AND1

OR1

@H + mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H + mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H + mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H + mem.bit

2

CY ← CY (fmem.bit)

CY ← CY (pmem7–2 + L3–2.bit (L1–0))

CY ← CY (H + mem^3-0.bit)

CY ← CY (fmem.bit)

CY ← CY (pmem^7–2+ L3–2.bit (L1–0))

CY ← CY (H + mem3-0.bit)

CY ← CY (fmem.bit)

CY ← CY (pmem^7–2+ L3–2.bit (L1–0))

CY ← CY (H + mem^3-0.bit)

XOR1

● µPD75304B

PC11–0 ← addr

(The assembler selects the optimum

instruction from among the BRCB !caddr,

and BR $addr instructions.)

addr

—

*6

● µPD75306B, 75308B

PC12–0 ← addr

(The assembler selects the optimum

instruction from among the BR !addr, BRCB

!caddr, and BR $addr instructions.)

BR

● µPD75306B, 75308B

PC12–0 ← addr

*6

*7

!addr

$addr

3

1

3

2

● µPD75304B

PC11–0 ← addr

● µPD75306B, 75308B

PC12–0 ← addr

● µPD75304B

PC11–0 ← caddr11–0

!caddr

!addr

BRCB

CALL

2

3

2

3

*8

*6

● µPD75306B, 75308B

PC12–0 ← PC12 + caddr11–0

● µPD75304B

(SP – 4) (SP – 1) (SP – 2) ← PC11–0

(SP – 3) ← MBE, 0, 0, 0

PC11–0 ← addr, SP ← SP – 4

● µPD75306B, 75308B

(SP – 4) (SP – 1) (SP – 2) ← PC11–0

(SP – 3) ← MBE, 0, 0, PC12

PC12–0 ← addr, SP ← SP – 4

Note Instruction Group

42

µPD75304B,75306B,75308B

Address-

Mne-

Note

1

Machine

Cycles

Bytes

Operand

Operation

Skip Condition

ing Area

monic

● µPD75304B

(SP – 4) (SP – 1) (SP – 2) ← PC11–0

(SP – 3) ← MBE, 0, 0, 0

PC11–0 ← 0, faddr, SP ← SP – 4

*9

2

!faddr

CALLF

● µPD75306B, 75308B

(SP – 4) (SP – 1) (SP – 2) ← PC11–0

(SP – 3) ← MBE, 0, 0, PC12

PC12–0 ← 00, faddr, SP ← SP – 4

● µPD75304B

MBE, ×, ×, × ← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4

RET

3

1

● µPD75306B, 75308B

MBE, ×, ×, PC¹²← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4

● µPD75304B

MBE, ×, ×, × ← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4 the skip unconditionally

RETS

Unconditional

3+S

● µPD75306B, 75308B

MBE, ×, ×, PC12 ← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4 the skip unconditionally

● µPD75304B

MBE, ×, ×, × ← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

RETI

3

● µPD75306B, 75308B

MBE, ×, ×, PC12 ← (SP + 1)

PC11–0 ← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

rp

1

2

1

2

1

2

1

2

(SP – 1) (SP – 2) ← rp, SP ← SP – 2

(SP – 1) ← MBS, (SP – 2) ← 0, SP ← SP – 2

rp ← (SP + 1) (SP), SP ← SP + 2

MBS ← (SP + 1), SP ← SP + 2

IME ← 1

PUSH

POP

EI

BS

rp

BS

IE × × ×

IE × × × ← 1

IME ← 0

DI

IE × × × ← 0

Note 1. Instruction Group

2. Interrupt control

43

µPD75304B,75306B,75308B

Machine

Cycles

Note

1

Address-

Mne-

Bytes

Operand

Operation

Skip Condition

ing Area

monic

A, PORTn

2

1

2

1

2

A ← PORTⁿ

(n = 0–7)

IN*

XA, PORTn

PORTn, A

XA ← PORTn+1, PORTn

PORTn ← A

(n = 4, 6)

(n = 2–7)

(n =4, 6)

OUT*

PORTn, XA

PORTn+1, PORTn ← XA

Set HALT Mode (PCC.2 ← 1)

Set STOP Mode (PCC.3 ← 1)

No Operation

HALT

STOP

NOP

SEL

MBn

MBS ← n (n = 0, 1, 15)

● µPD75304B

• TBR Instruction

PC11-0 ← (taddr) 3–0 + (taddr + 1)

-----------------------------

-----------------------------------------------------------------

• TCALL Instruction

(SP – 4) (SP – 1) (SP – 2) ← PC^11–0

(SP – 3) ← MBE, 0, 0, 0

PC11–0 ← (taddr) 3–0 ← (taddr + 1)

SP ← SP – 4

-----------------------------------------------------------------

• Other than TBR and TCALL Instruction

-----------------------------

Conforms to

referenced

instruction.

Execution of an instruction addressed at

(taddr) and (taddr + 1)

GETI

taddr

1

3

*10

● µPD75306, 75308BB

• TBR Instruction

PC12-0 ← (taddr) 4–0 + (taddr + 1)

-----------------------------------------------------------------

-----------------------------

• TCALL Instruction

(SP – 4) (SP – 1) (SP – 2) ← PC11–0

(SP – 3) ← MBE, 0, 0, PC12

PC12–0 ← (taddr) 4–0 ← (taddr + 1)

SP ← SP – 4

-----------------------------

Conforms to

-----------------------------------------------------------------

• Other than TBR and TCALL Instruction

Execution of an instruction addressed at

(taddr) and (taddr + 1)

referenced

instruction.

*

At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance.

Note 1. Instruction Group

2. CPU control

Remarks The TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table

definition.

44

µPD75304B,75306B,75308B

10. MASK OPTION SELECTION

The following pin mask options are available.

Pin Functions

Mask Options

P40 to P43,

P50 to P53

V^LC0to VLC2,

BIAS

● Pull-up resistor incorporated (specifiable bit-wise)

● No pull-up resistor (specifiable bit-wise)

● LCD drive power supply split resistor incorporated (specifiable as 4-bit unit)

● No LCD drive power supply split resistor (specifiable as 4-bit unit)

45

µPD75304B,75306B,75308B

11. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)

PARAMETER

SYMBOL

TEST CONDITIONS

RATING

UNIT

V

Power supply

voltage

VDD

VI1

–0.3 to +7.0

Except ports 4 and 5

–0.3 to V^DD+0.3

V

Input voltage

On-chip pull-up resistor

Open–drain

–0.3 to VDD +0.3

V

V12

VO

IOH

Ports 4 and 5

–0.3 to +11

V

Output voltage

–0.3 to VDD +0.3

V

Output current

high

One pin

All pins

–15

–30

30

mA

Peak value

rms

One pin

15

Peak value

100

60

Output current low

IOL*

Total of ports 0, 2, 3 and 5

Total of ports 4, 6, and 7

rms

Peak value

rms

100

60

Operating

temperature

–40 to +85

°C

Topt

Tstg

Storage

temperature

–65 to +150

*

Rms is calculated using the following expression: [rms] = [peak value] × √duty

CAPACITANCE (Ta = 25 °C, VDD = 0 V)

PARAMETER

Input capacitance

Output capacitance

I/O capacitance

SYMBOL

CIN

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

pF

15

f = 1 MHz

Unmeasured pins returned to 0 V.

COUT

pF

CIO

pF

46

µPD75304B,75306B,75308B

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

RECOMMENDED

CONSTANT

TEST

RESONATOR

PARAMETER

Oscillator

MIN.

1.0

TYP.

MAX.

UNIT

MHz

CONDITIONS

5.0*3

frequency (f^x)*1

X1

X2

After VDD

reached the

MIN. of the

oscillation

voltage

Ceramic

resonator*3

Oscillation

stabilization time*2

C2

C1

4

ms

V

DD

range

Oscillator

frequency (f^x)*1

1.0

4.19

5.0*3

MHz

ms

X1

X2

VDD = 4.5

to 6.0 V

10

Crystal

resonator*3

Oscillation

C2

C1

stabilization time*2

30

ms

V

DD

X1 input

frequency (f^x)*1

1.0

5.0*3

MHz

X1

X2

External

clock

X1 input

high-/low-level

width (tXH, tXL)

100

500

ns

µPD74HCU04

*

1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the

instruction execution time refer to the AC characteristics.

2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V^DDor releasing the

STOP mode.

3. When the oscillation frequency is 4.19 MHz < f^X≤ 5.0 MHz, PCC = 0011 should not be selected as the

instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s, and the

specification MIN. value of 0.95 µs will not be achieved.

★

47

µPD75304B,75306B,75308B

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

RECOMMENDED

CONSTANT

TEST

MIN.

32

TYP.

MAX.

UNIT

RESONATOR

PARAMETER

CONDITIONS

Oscillator

frequency (f^XT)

32.768

1.0

35

2

kHz

s

XT1

XT2

VDD = 4.5

to 6.0 V

R

Crystal

resonator

Oscillation

stabilization time*

C3

C4

10

s

V

DD

XT1 input

frequency (f^XT)

32

5

100

kHz

XT1

XT2

Leave

Open

External

clock

XT1 input high-/

low-level width

(tXTH,tXTL)

15

µs

*

This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage

range.

Note

When the main system clock and subsystem clock oscillators are used, the following should be noted

concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring

capacitance, etc.

★

• The wiring should be kept as short as possible.

• No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current.

• The oscillator capacitor grounding point should be at the same potential as V^DD. Do not ground to a

ground pattern carrying a high current.

• A signal should not be taken from the oscillator.

The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption

current, and is more prone to misoperation due to noise than the main system clock oscillator. Particu-

lar care is therefore required with the wiring method when the subsystem clock is used.

48

µPD75304B,75306B,75308B

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2)

PARAMETER

SYMBOL

VIH1

TEST CONDITIONS

MIN.

0.7 VDD

0.8 VDD

0.7 VDD

VDD –0.5

0

TYP.

MAX.

VDD

UNIT

Ports 2 and 3

V

V^IH2

Ports 0,1,6,7, RESET

Ports 4 and 5

VDD

Input voltage

high

On-chip pull-up resistor

Open–drain

VDD

V^IH3

10

VIH4

VIL1

V^IL2

VIL3

X1, X2, XT1

VDD

Ports 2, 3, 4 and 5

Ports 0, 1, 6, 7 RESET

X1, X2, XT1

0.3 VDD

0.2 VDD

0.4

Input voltage

low

0

VDD = 4.5 to 6.0 V

IOH = –1 mA

VDD –1.0

V

Ports 0, 2,3, 6, 7,

BIAS

VOH1

VOH2

I^OH= -100 µA

VDD –0.5

V^DD–2.0

V

Output voltage

high

VDD = 4.5 to 6.0 V

IOH = –100 µA

BP0 to BP7

(with 2 IOH outputs)

IOH = –30 µA

VDD –1.0

V

Ports 3, 4 and 5

V^DD= 4.5 to 6.0 V

IOL = 15 mA

0.5

2.0

Ports

0, 2, 3, 4, 5, 6 and 7

VDD = 4.5 to 6.0 V

IOL = 1.6 mA

0.4

0.5

V

VOL1

I^OL= 400 µA

Output voltage

low

Open–drain

pull-up resistor ≥ 1 kΩ

SB0, 1

0.2 VDD

1.0

V

V^DD= 4.5 to 6.0 V

IOL = 100 µA

BP0 to BP7

(with 2 IOL outputs)

VOL2

IOL = 50 µA

1.0

3

V

I^L1H1

Other than below

X1, X2, XT1

µA

VIN = VDD

VIN = 10 V

VIN = 0 V

ILIH2

20

Input leakage

current high

Ports 4 and 5

(when open–drain)

I^LIH3

20

µA

ILIL1

ILIL2

Other than below

X1, X2, XT1

–3

–20

3

µA

Input leakage

current low

ILOH1

VOUT = VDD

VOUT = 10 V

VOUT = 0 V

Other than below

Output leakage

current high

Ports 4 and 5

(when open–drain)

ILOH2

ILOL

20

–3

µA

Output leakage

current low

49

µPD75304B,75306B,75308B

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (2/2)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

15

TYP.

40

MAX.

80

UNIT

kΩ

V

Ports 0, 1, 2, 3, 6

and 7 (Except P00)

VIN = 0 V

VDD = 5.0 V ±10%

VDD = 3.0 V ±10%

VDD = 5.0 V ±10%

VDD = 3.0 V ±10%

RL1

30

300

70

On-chip pull-up

resistor

15

40

Ports 4 and 5

R^L2

V^OUT= VDD –2.0 V

10

60

LCD drive voltage

LCD split resistor

VLCD

RLCD

2.0

VDD

60

0

100

150

kΩ

LCD output voltage

deviation*1

(common)

VODC

IO = ±5 µA

IO = ±1 µA

±0.2

V

VLCD0 = VLCD

VLCD1 = VLCD × 2/3

VLCD2 = VLCD × 1/3

2.7 V ≤ V^LCD≤ VDD

LCD output voltage

deviation

V^ODS

0

±0.2

V

(segment)

VDD = 5 V ±10%*4

VDD = 3 V ±10%*5

3.0

0.4

600

180

40

9

mA

µA

IDDI

4.19 MHz*3

crystal oscillation

C1 = C2 = 22 pF

1.2

V^DD= 5 V ±10%

1800

540

120

HALT

mode

IDD2

µA

DD

V

= 3 V ±10%

I^DD3

VDD = 3 V ±10%

µA

Supply current*2

32 kHz*6

crystal oscillation

HALT

mode

VDD = 3 V ±10%

IDD4

12

36

µA

V^DD= 5 V ±10%

1

25

15

5

µA

XT1 = 0 V

STOP mode

IDD5

0.5

V^DD=

3 V ±10%

Ta = 25 °C

*

1. The voltage deviation is the difference between the output voltage and the segment or common output

desired value (V^LCDn; n= 0, 1, 2).

2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.

3. Including oscillation of the subsystem clock.

4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-

speed mode.

5. When PCC is set to 0000 and the device is operated in the low-speed mode.

6. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem

clock, with main system clock oscillation stopped.

50

µPD75304B,75306B,75308B

AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

0.95

3.8

TYP.

122

MAX.

64

UNIT

µs

CPU clock

cycle time

(minimum

instruction

Operating on main

system clock

64

µs

tCY

Operating on

execution time)*1

114

125

µs

subsystem clock

VDD = 4.5 to 6.0 V

0

1

MHz

kHz

µs

TI0 input

frequency

f^TI

275

VDD = 4.5 to 6.0 V

0.48

1.8

*2

10

tTIH,

t^TIL

TI0 input width

high/low

µs

INT0

µs

tINTH,

tINTL

Interrupt input

width high/low

INT1, 2, 4

KR0 to KR7

µs

RESET width low

tRSL

µs

*

1. The CPU clock (Φ ) cycle time (minimum

instruction execution time) is determined by

the oscillatior frequency of the connected

resonator, the system clock control register

t

CY vs VDD

(Operating on Main System Clock)

70

(SCC) and the processor clock control register

(PCC). The figure at the right indicates the

cycle time t^CYversus supply voltage VDD

characteristic with the main system clock

operating.

64

30

6

5

Guaranteed

Operation Range

4

3

2. 2t^CYor 128/fX is set by setting the interrupt

mode register (IM0).

2

1

0.5

0

1

2

3

4

5

6

Supply Voltage VDD [V]

51

µPD75304B,75306B,75308B

SERIAL TRANSFER OPERATION

2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = –40 to +85 °C, V^DD= 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY1

3800

ns

VDD = 4.5 to 6.0 V

tKCY1/2-50

t^KCY1/2-150

ns

tKL1

tKH1

SCK width high/

low

ns

SI setup time

(to SCK↑)

tSIK1

tKSI1

150

400

ns

SI hold time

(from SCK↑)

SO output

delay time

from SCK↓

V^DD= 4.5 to 6.0 V

250

ns

RL = 1 kΩ,

CL = 100 pF*

t^KSO1

1000

2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)

PARAMETER

SYMBOL

t^KCY2

TEST CONDITIONS

V^DD= 4.5 to 6.0 V

MIN.

800

TYP.

MAX.

UNIT

ns

SCK cycle time

3200

400

ns

V^DD= 4.5 to 6.0 V

ns

t^KL2

tKH2

SCK width high/

low

1600

ns

SI setup time

(to SCK↑)

tSIK2

tKSI2

100

400

ns

SI hold time

(from SCK ↑)

SO output

delay time

from SCK↓

V^DD= 4.5 to 6.0 V

300

ns

RL = 1 kΩ,

C^L= 100 pF*

tKSO2

1000

*

RL and CL are load resistor and load capacitance of the SO output line.

52

µPD75304B,75306B,75308B

SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

PARAMETER

SYMBOL

t^KCY3

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

TYP.

MAX.

UNIT

ns

SCK cycle time

3800

ns

VDD = 4.5 to 6.0 V

tKCY3/2-50

tKCY3/2-150

ns

tKL3

tKH3

SCK width high/

low

ns

SB0, 1 setup time

(to SCK ↑)

tSIK3

tKSI3

150

ns

SB0, 1 hold time

(from SCK ↑)

tKCY3/2

SB0, 1 output

delay time from

SCK ↓

VDD = 4.5 to 6.0 V

0

250

ns

RL = 1 kΩ,

C^L= 100 pF*

tKSO3

0

1000

SB0, 1 ↓ from SCK ↑

SCK from SB0, 1 ↓

SB0, 1 width low

SB0, 1 width high

t^KSB

tSBK

t^SBL

tSBH

tKCY3

SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

V^DD= 4.5 to 6.0 V

MIN.

800

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY4

3200

400

ns

VDD = 4.5 to 6.0 V

ns

tKL4

tKH4

SCK width high/

low

1600

ns

SB0, 1 setup time

(to SCK ↑)

tSIK4

tKSI4

100

ns

SB0, 1 hold time

(from SCK ↑)

tKCY4/2

SB0, 1 output

delay time from

SCK ↓

VDD = 4.5 to 6.0 V

0

300

ns

RL = 1 kΩ,

CL = 100 pF*

tKSO4

0

1000

SB0, 1 ↓ from SCK ↑

SCK ↓ from SB0, 1 ↓

SB0, 1 width low

tKSB

tSBK

tSBL

tSBH

tKCY4

SB0, 1 width high

*

RL and CL are load resistor and load capacitance of the SB0, 1 output lines.

53

µPD75304B,75306B,75308B

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) (1/2)

PARAMETER

SYMBOL

VIH1

TEST CONDITIONS

Ports 2 and 3

MIN.

0.8 VDD

0.8 V^DD

VDD –0.3

0

TYP.

MAX.

VDD

UNIT

V

VIH2

Ports 0, 1, 6, 7, RESET

Ports 4 and 5

VDD

Input voltage

high

On-chip pull-up resistor

Open–drain

VDD

VIH3

10

V^IH4

VIL1

VIL2

VIL3

X1, X2, XT1

VDD

Ports 2, 3, 4 and 5

Ports 0, 1, 6, 7, RESET

X1, X2, XT1

0.2 VDD

0.3

Input voltage

low

0

Ports 0, 2, 3, 6,

7, BIAS

VOH1

VOH2

IOH = –100 µA

IOH = –10 µA

IOL = 400 µA

VDD –0.5

VDD –0.4

V

Output voltage

high

BP0 to BP7 (with

2 IOH outputs)

Ports 0, 2, 3, 4, 5

6, and 7

0.5

0.2 VDD

0.4

V^OL1

Output voltage

low

Open–drain,

pull-up resistor ≥ 1 kΩ

SB0, 1

V

BP0 to BP7

(with 2 I^OLoutputs)

V^OL2

IOL = 10 µA

I^LIH1

Other than below

X1, X2, XT1

3

µA

VIN = VDD

VIN = 10 V

VIN = 0 V

Input leakage

current high

ILIH2

20

Ports 4 and 5

(with open–drain)

I^LIH3

20

µA

I^LIL1

ILIL2

Other than below

X1, X2, XT1

–3

–20

3

µA

Input leakage

current low

ILOH1

VOUT = VDD

Other than below

Output leakage

current high

Ports 4 and 5

(with open–drain)

ILOH2

ILOL

VOUT = 10 V

20

–3

µA

Output leakage

current low

VOUT = 0 V

54

µPD75304B,75306B,75308B

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) (2/2)

PARAMETER

SYMBOL

TEST CONDITIONS

Ports 0, 1, 2, 3, 6

and 7 (Except P00) VDD = 2.5 V ±10%

VIN = 0 V

MIN.

50

TYP.

MAX.

600

UNIT

RL1

kΩ

On-chip pull-up

resistor

Ports 4 and 5

V^OUT= VDD –1.0 V

RL2

VDD = 2.5 V ±10%

10

60

kΩ

LCD drive voltage

LCD split resistor

V^LCD

2.0

60

VDD

V

RLCD

100

150

kΩ

LCD output voltage

deviation *1

(common)

VODC

V^ODS

IDDI

IO = ±5 µA

0

±0.2

V

VLCDO = VLCD

VLCD1 = VLCD × 2/3

VLCD2 = VLCD × 1/3

LCD output

voltage deviation

(segment)

2.0 V ≤ VLCD ≤ VDD

IO = ±1 µA

VDD = 3 V ±10%*4

4.19 MHz*3

crystal oscillation

C1 = C2 = 22 pF

low-speed mode

0.4

0.3

180

120

40

1.2

0.9

540

360

120

75

36

27

15

5

mA

µA

VDD = 2.5 V ±10%*4

HALT VDD = 3 V ±10%

I^DD2

IDD3

IDD4

mode VDD = 2.5 V ±10%

VDD = 3 V ±10%

Supply current*2

VDD = 2.5 V ±10%

32 kHz*5

crystal oscillation

25

HALT VDD = 3 V ±10%

12

mode VDD = 2.5 V ±10%

9

0.5

0.4

VDD = 3 V ±10%

Ta = 25 °C

XT1 = 0 V

STOP mode

IDD5

15

5

VDD = 2.5 V

±10%

Ta = 25°C

*

1. The voltage deviation is the difference between the output voltage and the segment or common output

desired value (V^LCDn; n = 0, 1, 2).

2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.

3. Including oscillation of the subsystem clock.

4. When PCC is set to 0000 and the device is operated in the low-speed mode.

5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem

clock, with main system clock oscillation stopped.

55

µPD75304B,75306B,75308B

AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

PARAMETER SYMBOL TEST CONDITIONS

V^DD= 2.7 to 6.0 V

MIN.

3.8

5

TYP.

MAX.

64

UNIT

µs

Operation on main

system clock

VDD = 2.0 to 6.0 V

64

µs

CPU clock

cycle time

(minimum

instruction

t^CY

Ta = –40 to + 60 °C

VDD = 2.2 to 6.0 V

3.4

64

µs

execution time)*1

Operation on

114

122

125

subsystem clock

TI0 input

frequency

fTI

0

275

kHz

TI0 input width

high/low

t^TIH,

tTIL

1.8

µs

INT0

*2

10

µs

Interrupt input

width high/low

tINTH,

t^INTL

INT1, 2, 4

KR0 to KR7

RESET width low

t^RSL

*

1. The CPU clock (Φ ) cycle time (minimum

instruction execution time) is determined by

the oscillatior frequency of the connected

resonator, the system clock control register

t

CY vs VDD

(Operating on Main System Clock)

70

64

30

(SCC) and the processor clock control register

(PCC). The figure at the right indicates the

cycle time t^CYversus supply voltage VDD

characteristic with the main system clock

operating.

6

5

Guaranteed

4

3

Operation Range

2. 2t^CYor 128/fX is set by setting the interrupt

mode register (IM0).

2

1

0.5

0

1

2

3

4

5

6

Supply Voltage VDD [V]

56

µPD75304B,75306B,75308B

SERIAL TRANSFER OPERATION

2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = –40 to +85 °C, V^DD= 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY1

3800

ns

VDD = 4.5 to 6.0 V

tKCY1/2-50

tKCY1/2-150

ns

tKL1

tKH1

SCK width high/

low

ns

SI setup time

(to SCK ↑)

t^SIK1

250

400

ns

SI hold time

(from SCK ↑)

tKSI1

SO output

delay time

from SCK ↓

V^DD= 4.5 to 6.0 V

250

ns

RL = 1 kΩ,

CL = 100 pF*

tKSO1

1000

2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

V^DD= 4.5 to 6.0 V

MIN.

800

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY2

3200

400

ns

VDD = 4.5 to 6.0 V

ns

tKL2

tKH2

SCK width high/

low

1600

ns

SI setup time

(to SCK↑)

tSIK2

tKSI2

100

400

ns

SI hold time

(from SCK↑)

SO output

delay time

from SCK↓

V^DD= 4.5 to 6.0 V

300

ns

RL = 1 kΩ,

CL = 100 pF*

tKSO2

1000

*

RL and CL are load resistor and load capacitance of the SO output line.

57

µPD75304B,75306B,75308B

SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

VDD = 4.5 to 6.0 V

MIN.

1600

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY3

3800

ns

V^DD= 4.5 to 6.0 V

tKCY3/2-50

t^KCY3/2-150

ns

tKL3

tKH3

SCK width high/

low

ns

SB0, 1 setup

time (to SCK↑)

tSIK3

tKSI3

250

ns

SB0, 1 hold

time (from SCK↑)

tKCY3/2

SB0, 1 output

delay time

from SCK↓

VDD = 4.5 to 6.0 V

0

250

ns

RL = 1 kΩ,

C^L= 100 pF*

t^KSO3

0

1000

SB0, 1 ↓ from SCK↑

SCK from SB0, 1 ↓

SB0, 1 width low

SB0, 1 width high

tKSB

tSBK

t^SBL

tSBH

tKCY3

SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

V^DD= 4.5 to 6.0 V

MIN.

800

TYP.

MAX.

UNIT

ns

SCK cycle time

tKCY4

3200

400

ns

V^DD= 4.5 to 6.0 V

ns

tKL4

tKH4

SCK width high/

low

1600

ns

SB0, 1 setup

time (to SCK ↑)

tSIK4

100

ns

SB0, 1 hold

time (from SCK ↑)

t^KSI4

tKCY4/2

SB0, 1

output delay

time from SCK ↓

VDD = 4.5 to 6.0 V

0

300

ns

RL = 1 kΩ,

CL = 100 pF*

tKSO4

0

1000

SB0, 1 ↓ from SCK ↑

SCK↓ from SB0, 1 ↓

SB0, 1 width low

tKSB

tSBK

tSBL

tSBH

tKCY4

SB0, 1 width high

*

RL and CL are load resistor and load capacitance of the SB0, 1 output lines.

58

µPD75304B,75306B,75308B

AC Timing Test Point (Excluding X1 and XT1 inputs)

0.8 VDD

0.2 VDD

Test Points

0.2 VDD

Clock Timings

1/fX

t

XL

tXH

VDD -0.5 V

0.4 V

X1 Input

1/f^XT

t

XTL

t

XTH

VDD -0.5 V

0.4 V

XT1 Input

TI0 Timing

1/f^TI

t

TIL

tTIH

TI0

59

µPD75304B,75306B,75308B

Serial Transfer Timing

3-wired serial I/O mode:

t

KCY1

t

KL1

t

KH1

SCK

t

SIK1

t

KSI1

Input Data

SI

t

KSO1

SO

Output Data

2-wired serial I/O mode:

tKCY2

tKL2

tKH2

SCK

tSIK2

tKSI2

SB0,1

t

KSO2

60

µPD75304B,75306B,75308B

Serial Transfer Timing

Bus release signal transfer:

t

KCY3,4

t

KL3,4

t

KH3,4

SCK

t

SIK3,4

t

KSB

t

SBL

t

SBH

t

SBK

t

KSI3,4

SB0,1

t

KSO3,4

Command signal transfer:

tKCY3,4

t

KL3,4

tKH3,4

SCK

t

SIK3,4

tKSB

tSBK

t

KSI3,4

SB0,1

tKSO3,4

Interrupt Input Timing

tINTL

t

INTH

INT0,1,2,4

KR0-7

RESET Input Timing

t

RSL

RESET

61

µPD75304B,75306B,75308B

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to 85 °C)

PARAMETER

SYMBOL

VDDDR

TEST CONDITIONS

MIN.

2.0

TYP.

0.3

MAX.

6.0

UNIT

V

Data retention supply voltage

Data retention supply current*1

Release signal setup time

IDDDR

VDDDR = 2.0 V

15

µA

µs

t^SREL

0

Release by RESET

2¹⁷/fx

ms

Oscillation stabilization

wait time*2

tWAIT

Release by interrupt request

*3

*

1. Current which flows in the on-chip pull-up resistor is not included.

2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent

unstable operation at the oscillation start.

3. Depends on the basic interval timer mode register (BTM) setting (table below).

WAIT TIME

BTM3

BTM2

BTM1

BTM0

(Figures in parentheses are for operation at fx = 4.19 MHz)

—

0

1

0

1

0

1

0

1

2²⁰/fx (approx. 250 ms)

2¹⁷/fx (approx. 31.3 ms)

2¹⁵/fx (approx. 7.82 ms)

2¹³/fx (approx. 1.95 ms)

62

µPD75304B,75306B,75308B

Data Retention Timing (STOP mode release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode

Operating

Mode

Data Retention Mode

V

DD

V

DDDR

t

SREL

STOP Instruction Execution

RESET

tWAIT

Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)

HALT Mode

STOP Mode

Operating

Mode

Data Retention Mode

V

DD

VDDDR

t

SREL

STOP Instruction Execution

Standby Release Signal

(Interrupt Request)

t

WAIT

63

µPD75304B,75306B,75308B

12. PACKAGE INFORMATION

80 PIN PLASTIC QFP ( 14)

A

B

60

61

41

40

detail of lead end

21

20

80

1

G

M

I

H

J

K

N

L

S80GC-65-3B9-3

NOTE

ITEM

A

MILLIMETERS

INCHES

Each lead centerline is located within 0.13

mm (0.005 inch) of its true position (T.P.) at

maximum material condition.

±

17.2 0.4

0.677 0.016

+0.009

±

B

14.0 0.2

0.551

–0.008

+0.009

±

C

14.0 0.2

0.551

–0.008

±

D

F

0.677 0.016

17.2 0.4

0.8

0.031

G

H

I

0.031

+0.004

±

0.30 0.10

0.012

–0.005

0.13

0.005

J

0.65 (T.P.)

0.026 (T.P.)

±

K

1.6 0.2

0.063 0.008

+0.009

±

0.031

L

0.8 0.2

–0.008

+0.10

+0.004

0.15

M

N

P

0.006

–0.05

–0.003

0.10

2.7

0.004

0.106

±

Q

S

0.1 0.1

±

0.004 0.004

3.0 MAX.

0.119 MAX.

64

µPD75304B,75306B,75308B

80 PIN PLASTIC QFP (14×20)

A

B

41

40

64

65

detail of lead end

25

24

80

1

G

H

M

N

I

J

K

L

P80GF-80-3B9-2

NOTE

ITEM

MILLIMETERS

INCHES

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at

maximum material condition.

±

A

B

C

D

F

23.6 0.4

0.929 0.016

+0.009

±

20.0 0.2

0.795

–0.008

+0.009

±

14.0 0.2

0.551

–0.008

±

0.693 0.016

17.6 0.4

1.0

0.8

0.039

G

H

I

0.031

+0.004

±

0.35 0.10

0.014

–0.005

0.15

0.006

J

0.8 (T.P.)

0.031 (T.P.)

+0.008

±

K

L

1.8 0.2

0.071

–0.009

+0.009

±

0.031

0.8 0.2

–0.008

+0.10

+0.004

0.15

M

N

P

Q

S

0.006

–0.05

–0.003

0.15

2.7

0.006

0.106

±

0.1 0.1

0.004 0.004

3.0 MAX.

0.119 MAX.

65

µPD75304B,75306B,75308B

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

A

B

60

41

61

40

detail of lead end

80

21

1

20

G

M

I

J

H

K

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.10 mm (0.004 inch) of

its true position (T.P.) at maximum material condition.

+0.009

A

B

C

D

14.0±0.2

12.0±0.2

14.0±0.2

0.551

0.472

0.551

–0.008

+0.009

–0.008

+0.009

–0.008

+0.009

–0.008

F

1.25

0.049

G

+0.05

0.22

H

0.009±0.002

–0.04

I

0.10

0.004

J

0.5 (T.P.)

0.020 (T.P.)

+0.009

0.039

K

L

1.0±0.2

0.5±0.2

–0.008

+0.008

0.020

–0.009

+0.055

M

0.145

0.006±0.002

–0.045

N

P

Q

R

S

0.10

1.05

0.004

0.041

0.05±0.05

5°±5°

0.002±0.002

5°±5°

1.27 MAX.

0.050 MAX.

P80GK-50-BE9-4

66

µPD75304B,75306B,75308B

★

13. RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the conditions recommended below.

For details of recommended soldering conditions, refer to the information document "Surface Mount

Technology Manual (IEI 1207)".

For soldering methods and conditions other than those recommended, please contact our salesman.

Table 13-1 Surface Mount Type Soldering Conditions

(1) µPD75304BGC-×××-3B9: 80-Pin Plastic QFP (■14 mm)

µPD75306BGC-×××-3B9: 80-Pin Plastic QFP (■14 mm)

µPD75308BGC-×××-3B9: 80-Pin Plastic QFP (■14 mm)

Soldering Method

Infrared reflow

Soldering ConditionsRecommended

Condition Symbol

IR30-207-1

Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above)

Number of applications: one

Time limit: 7 days* (thereafter 20 hours 125°C prebaking required)

Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above)

Number of applications: one

VPS

VP15-207-1

Time limit: 7 days* (thereafter 20 hours 125°C prebaking required)

Pin part temperature: 300°C or less

Pin part heating

Duration: 3 sec. max. (per side of device)

(2) µPD75304BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

µPD75306BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

µPD75308BGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

Soldering Method

Infrared reflow

VPS

Soldering ConditionsRecommended

Condition Symbol

IR30-00-1

Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above)

Number of applications: one

Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above)

VP15-00-1

Number of applications: one

Solder bath temperature: 260°C or less Duration: 10 sec. max.

Number of applications: one

Wave soldering

Pin part heating

WS60-00-1

Preparatory heating temperature: 120°C max. (package surface temperature)

Pin part temperature: 300°C or less

Duration: 3 sec. max. (per side of device)

*

For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.

Note Use of more than one soldering method should be avoided (except in the case of pin part heating).

67

µPD75304B,75306B,75308B

(3) µPD75304BGK-×××-3B9: 80-Pin Plastic TQFP (■12 mm)

µPD75306BGK-×××-3B9: 80-Pin Plastic TQFP (■12 mm)

µPD75308BGK-×××-3B9: 80-Pin Plastic TQFP (■12 mm)

Soldering Method

Infrared reflow

Soldering ConditionsRecommended

Package peak temperature: 230°C Duration: 30 sec. max. (210°C or above)

Condition Symbol

IR30-161-1

VP15-161-1

Number of applications: one

Time limit: 1 day* (thereafter 16 hours 125°C prebaking required)

Package peak temperature: 215°C Duration: 40 sec. max. (200°C or above)

Number of applications: one

VPS

Time limit: 1 day* (thereafter 16 hours 125°C prebaking required)

Pin part temperature: 300°C or less

Pin part heating

Duration: 3 sec. max. (per side of device)

*

For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.

Note Use of more than one soldering method should be avoided (except in the case of pin part heating).

NOTICE

Recommended soldering conditions have been improved for some of these products.

(Improvements: Relaxation of infrared reflow peak temperature (235°C, number of applications (two),

time limit, etc.)

Please contact your NEC sales representative for details.

68

µPD75304B,75306B,75308B

[MEMO]

69

µPD75304B,75306B,75308B

APPENDIX A. DIFFERENCES AMONG SERIES PRODUCTS

★

Product Name

µPD75304/75306/75308

µPD75312/75316

µPD75P308

µPD75P316

Item

Supply voltage range

2.0 to 6.0 V

5V±5%

EPROM/One-

time

One-time

PROM

ROM configuration

Mask ROM

4096/6016/8064

Program memory (bytes)

12160/16256

512

8064

16256

Data memory (× 4 bits)

0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation)

122 µs (subsystem clock: 32.768 kHz operation)

Instruction cycle

CMOS input

8

Pull-up resistor incorporation spesifiable by software: 23

16

CMOS input/output

Input/output

ports

40

8

Used with segment pin

CMOS output

10 V withstand voltage. Pull-up

resistor incorporation spesifiable by

mask option.

10 V withstand voltage. Pull-up

resistor incorporation spesifiable

by mask option

N-ch open–drain

input/output

(without pull-up resistor)

• Common output: Static – 1/4 duty selected

• Segment output: Max. 32

LCD controller/driver

LCD drive split resistor can be incorporated by

mask option.

No LCD drive split resistor.

LCD drive voltage

Timer/counter

2.0 to VDD

• 8-bit timer/event counter

• 8-bit basic interval timer

• Watch timer

• NEC standard serial bus interface (SBI)

• Clock synchronous serial interface

Serial interface

• External: 3

• Internal: 3

Vectored interrupt

• External: 1

• Internal: 1

Test input

Clock output (PCL)

Buzzer output (BUZ)

Φ, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)

2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz

operation)

80-pin plastic QFP

(14 × 20 mm)

80-pin plastic QFP

(14 × 20 mm)

80-pin ceramic

WQFN (LCC with

window)

Package

80-pin plastic QFP (14 × 20 mm)

µPD75P316

µPD75P308

On-chip PROM product

µPD75P316A

70

µPD75304B,75306B,75308B

Product Name

µPD75304B/75306B/75308B µPD75312B

µPD75316B

µPD75P316B* µPD75P316A

Item

2.0 to 6.0 V

Supply voltage range

ROM configuration

One-time

PROM

EPROM/One-

time

Mask ROM

4096/6016/8064

512

12160

16256

Program memory (bytes)

1024

Data memory (× 4 bits)

0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz operation)

122 µs (subsystem clock: 32.768 kHz operation)

Instruction cycle

CMOS input

8

Pull-up resistor incorporation spesifiable by software: 23

16

CMOS input/output

Input/output

ports

40

CMOS output

8

Used with segment pin

10 V withstand voltage. Pull-

up resistor incorporation

spesifiable by mask option

10 V withstand voltage. Pull-up resistor

incorporation spesifiable by mask option.

(without pull-up resistor)

N-ch open–drain

input/output

• Common output: Static – 1/4 duty selected

• Segment output: Max. 32

LCD controller/driver

LCD drive split resistor can be incorporat-

ed by mask option.

No LCD drive split resistor.

LCD drive voltage

Timer/counter

2.0 to VDD

• 8-bit timer/event counter

• 8-bit basic interval timer

• Watch timer

• NEC standard serial bus interface (SBI)

• Clock synchronous serial interface

Serial interface

Vectored interrupt

Test input

• External: 3

• Internal: 3

• External: 1

• Internal: 1

Φ, 524 kHz, 262 kHz, 65.5 kHz (main system clock: 4.19 MHz operation)

Clock output (PCL)

Buzzer output (BUZ)

2 kHz (Main system clock: in 4.19 MHz operation or subsystem clock: in 32.768 kHz

operation)

80-pin

ceramic

WQFN

80-pin plastic

QFP

(14 × 20 mm)

80-pin plastic QFP

• (14 × 20 mm)

• (■14mm)

80-pin plastic QFP (■14mm)

80-pin plastic TQFP(■12mm)

Package

80-pin

plastic TQFP(■12mm)

GF package: µPD75P316A

GC/GK package: µPD75P316B

µPD75P316B

On-chip PROM product

Under development

*

71

µPD75304B,75306B,75308B

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD75304B/75306B/

75308B.

IE-75000-R*1

75X series in-circuit emulator

IE-75001-R

Emulation board for the IE-75000-R or IE-75001-R

IE-75000-R-EM*2

Emulation probe for the µPD75304BGF, 75306BGF and 75308BGF.

EP-75308GF-R

An 80-pin conversion socket (EV-9200G-80) is also provided.

EV-9200G-80

EV-9200GC-80

EV-9500GK-80

Emulation probe for the µPD75304BGC, 75306BGC and 75308BGC.

EP-75308BGC-R

EP-75308BGK-R

An 80-pin conversion socket (EV-9200GC-80) is also provided.

Emulation probe for the µPD75304BGK, 75306BGK and 75308BGK.

An 80-pin conversion adapter (EV-9200GK-80) is also provided.

PROM programmer

PG-1500

PROM programmer adapter for the µPD75P316AGF, connected to the

PA-75P308GF

PG-1500.

PROM programmer adapter for the µPD75P316BGC, connected to the

PA-75P316BGC

PA-75P316BGK

PG-1500.

PROM programmer adapter for the µPD75P316BGK, connected to the

PG-1500.

IE Control Program

PG-1500 Controller

Host machines

PC-9800 series (MS-DOS™ Ver. 3.30 to Ver. 5.00A*3)

IBM PC/AT™(PC DOS™ Ver. 3.1)

RA75X Relocatable Assembler

*

1. Maintenance product

2. Not incorporated in the IE-75001-R.

3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this

software.

Remarks Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.

72

µPD75304B,75306B,75308B

APPENDIX C. RELATED DOCUMENTS

Device Related Documents

Document Name

User's Manual

Document Number

IEM-5016

Instruction Application Table

IEM-994

IEM-5035

IEM-5041

IF-151

Application Note

75X Series Selection Guide

Development Tools Documents

Document Name

Document Number

EEU-846

IE-75000-R/IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75308GF-R User's Manual

EP-75308BGC-R User's Manual

EP-75308BGK-R User's Manual

PG-1500 User's Manual

EEU-673

EEU-689

EEU-825

EEU-838

EEU-651

Operation

Language

EEU-731

EEU-730

EEU-704

RA75X Assembler Package User's Manual

PG-1500 Controller User's Manual


型号：	UPD75308BGF
厂家：	NEC
描述：	4-BIT SINGLE-CHIP MICROCOMPUTER 4位单片机计算机
文件：	总76页 (文件大小：565K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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