UPD75402A_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD75402A(A)

4 BIT SINGLE-CHIP MICROCOMPUTER

The µPD75402A(A) is a CMOS single-chip microcomputer which uses the 75X series architecture. It operates

at high speed with a minimum instruction execution time of 0.95 µs.

The µPD75P402 is also available for system development evaluation. It contains one-time PROM instead

of mask ROM used in the µPD75402A(A).

The following user's manual describes the details of the functions of the µPD75402A(A). Be sure to read

it before designing an application system.

µPD75402A User's Manual: IEU-644

FEATURES

• More reliable than the µPD75402A

• High-speed operation with a minimum instruction execution time of 0.95 µs (when the microcomputer

operates at 4.19 MHz)

• Low voltage and low-speed instruction execution time of 15.3 µs (when the microcomputer operates at

4.19 MHz)

• Memory mapping by on-chip peripheral hardware

• NEC standard serial bus interface (SBI)

• 8-bit basic interval timer (watchdog timer applicable)

• Interrupt function

•

Three vectored interrupts (one external and two internal interrupts)

One external test input

• Clock output function (remote controller output applicable)

• Capable of specifying the incorporation of 16 pull-up resistors by software

APPLICATIONS

Electronic units for automobiles, and suchlike

ORDERING INFORMATION

Part number

Package

Quality grade

Special

µPD75402AC(A)-×××

µPD75402ACT(A)-×××

µPD75402AGB(A)-×××-3B4

28-pin plastic DIP (600 mil)

28-pin plastic shrink DIP (400 mil)

44-pin plastic QFP (10 × 10 mm)

Special

Remark ××× indicates the ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

Document No. IC-2841B

(O.D.No. IC-8273B)

Major changes in this revision are indicated by stars ( ) in the margins.

Date Published November 1993 P

Printed in Japan

NEC CORPORATION 1991

1

©

1990

µPD75402A(A)

DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75402A

Product

µPD75402A(A)

µPD75402A

Standard

Item

Quality grade

Special

FUNCTIONAL OVERVIEW

Item

Function

Number of basic

instructions

37

Minimum instruction

execution time

•

0.95, 1.91, or 15.3 µs (when operating at 4.19 MHz)

Switchable among three speeds

Built-in

ROM

RAM

1920 × 8 bits

memory

64 × 4 bits

General register

I/O line

4 bits × 4 or 8 bits × 2 (memory mapping)

•

CMOS input ports

CMOS I/O ports

:

6 lines

: 12 lines (8 lines can drive the LED directly.)

N-ch open-drain I/O ports : 4 lines (All lines can drive the LED directly.)

Pull-up resistor

Clock output

•

Capable of controlling the incorporation of 16 pull-up resistors by software

Capable of controlling the incorporation of 4 pull-up resistors by mask option

•

1.05 MHz, 524 kHz, or 65.5 kHz (when operating at 4.19 MHz)

Applicable to remote controller output

Timer/counter

Serial interface

8-bit basic interval timer (watchdog timer applicable)

•

8 bits

Two transfer modes (three-wire synchronous mode and SBI mode)

Vectored interrupt

Test input

One external and two internal interrupts

One external input (See Chapter 6 for details.)

STOP/HALT mode

Standby

Instruction set

•

Bit manipulation instructions (set, clear, test, and Boolean operation)

1-byte relative branch instructions

4-bit operation instructions (add, Boolean operation, and compare)

4- and 8-bit transfer instructions

Package

•

28-pin plastic DIP (600 mil)

28-pin plastic shrink DIP (400 mil)

44-pin plastic QFP (10 × 10 mm)

2

µPD75402A(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ......................................................................................

2. BLOCK DIAGRAM ......................................................................................................................

3. PIN FUNCTIONS .......................................................................................................................

4

6

7

3.1

3.2

3.3

3.4

3.5

3.6

PORT PINS .....................................................................................................................................

NON-PORT PINS ...........................................................................................................................

PIN INPUT/OUTPUT CIRCUITS ..................................................................................................

SELECTION OF A MASK OPTION ...........................................................................................

HANDLING UNUSED PINS .........................................................................................................

NOTES ON USING THE P00 AND RESET PINS .................................................................

8

10

11

4. MEMORY CONFIGURATION ................................................................................................... 12

5. PERIPHERAL HARDWARE FUNCTIONS................................................................................ 14

5.1

5.2

5.3

5.4

5.5

PORTS..............................................................................................................................................

CLOCK GENERATOR ....................................................................................................................

CLOCK OUTPUT CIRCUIT ...........................................................................................................

BASIC INTERVAL TIMER ............................................................................................................

SERIAL INTERFACE ......................................................................................................................

14

15

16

17

18

6. INTERRUPT FUNCTION ........................................................................................................... 20

7. STANDBY FUNCTION .............................................................................................................. 22

8. RESET FUNCTION .................................................................................................................... 23

9. INSTRUCTION SET ................................................................................................................... 25

10. ELECTRICAL CHARACTERISTICS ........................................................................................... 29

11. PACKAGE DIMENSIONS.......................................................................................................... 38

12. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 42

APPENDIX A DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75P402 ................... 43

APPENDIX B DEVELOPMENT TOOLS......................................................................................... 44

APPENDIX C RELATED DOCUMENTS ........................................................................................ 45

★

3

µPD75402A(A)

1. PIN CONFIGURATION (TOP VIEW)

28-pin plastic DIP (600 mil), 28-pin plastic shrink DIP (400 mil)

^NoteNC

RESET

1

2

3

4

5

28

27

26

25

24

V

DD

X1

P00

X2

P01/SCK

P02/SO/SB0

P12/INT2

P10/INT0

µ

P03/SI

P50

6

7

23

22

P23

P22/PCL

P51

P52

P53

P30

P31

P32

8

21

20

19

18

17

16

15

P21

P20

P63

P62

P61

P60

P33

9

10

11

12

13

14

VSS

P00 - P03 : Port 0

P10 and P12: Port 1

P20 - P23 : Port 2

P30 - P33 : Port 3

P50 - P53 : Port 5

P60 - P63 : Port 6

SCK

: Serial clock I/O

SO/SB0 : Serial output/input-output

SI

: Serial input

: Clock output

PCL

INT0

INT2

: External vectored interrupt input

: External test input

X1 and X2: Oscillating pins

RESET

V^DD

: Reset input

: Power supply

: Ground

V^SS

NC

: No connection

Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

directly to the V^SSpin.

4

µPD75402A(A)

44-pin plastic QFP (10 × 10 mm)

44 43 42 41 40 39 38 37 36 35 34

33

P30

P31

P32

NC

1

2

3

4

P01/SCK

P00

32

31

30

RESET

NC ^Note

V

SS

5

6

7

29

28

27

NC

µPD75402AGB(A)-×××-3B4

P33

P60

P61

NC

8

26

25

24

23

V

DD

9

X1

X2

NC

10

11

12 13 14 15 16 17 18 19 20 21 22

Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

(pin 30) directly to the V^SSpin.

5

µPD75402A(A)

3. PIN FUNCTIONS

3.1 PORT PINS

Dual-

I /O

Function

function pin

P00

P01

P02

P03

P10

Input

I/O

–

SCK

SO/SB0

SI

4-bit input port (port 0)

P01 to P03 allow the connection of built-in pull-up resistors to be

specified in units of three bits by software.

I/O

Input

INT0

2-bit input port (port 1)

P10 connects with the built-in noise eliminator using a sampling clock.

P12 connects with the built-in noise eliminator using an analog delay.

P12 allows the connection of built-in pull-up resistor to be specified by

software.

P12

INT2

P20

P21

I/O

–

4-bit I/O port (port 2)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

P22

PCL

–

P23

P30 - P33

–

Programmable 4-bit I/O port (port 3)

Allow I/O specification bit by bit.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

Can directly drive LED.

P50 - P53

P60 - P63

4-bit N-ch open-drain I/O port (port 5)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified bit by

bit by mask option.

–

Can directly drive LED.

4-bit I/O port (port 6)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

Can directly drive LED.

Remarks 1. The µPD75402A(A) cannot perform 8-bit I/O with two ports as a pair.

2. See Chapter 8 for each pin status during resetting.

7

µPD75402A(A)

3.2 NON-PORT PINS

Dual-

I /O

Function

function pin

INT0

Input

P10

Edge detection vectored interrupt request input pin (A detected edge

can be selected by the mode register.)

Connects with the built-in noise eliminator using a sampling clock.

INT2

SI

Input

I/O

P12

P03

Edge detection external test input pin (A rising edge is detected.)

Serial data input pin

Serial data output pin

Serial clock I/O pin

Serial bus I/O pin

Clock output pin

SO

P02/SB0

P01

SCK

SB0

PCL

X1, X2

I/O

P02/SO

P22

I/O

Input

–

Pin for connection to a crystal/ceramic resonator for system clock

generation. An external clock is applied to X1, and its reverse phase to

X2.

RESET

Input

–

System reset input pin, which connects with the built-in noise elimina-

tor using an analog delay.

VDD

VSS

–

Positive power supply pin

Ground potential pin

No connection

Note

NC

Remark See Chapter 8 for each pin status during resetting.

Note Connect the NC pin directly to the V^SSpin when the µPD75402A(A) shares the printed circuit board

with the µPD75P402 in emulation.

3.3 PIN INPUT/OUTPUT CIRCUITS

The I/O circuits of the µPD75402A(A) are roughly shown on the next and subsequent pages.

Table 1-1 I/O Circuit Type of Pin

I/O type

P20, P21, and P23

P22/PCL

I/O type

E-B

P00

B

P01/SCK

P02/SO/SB0

P03/SI

F

-A

-B

-C

P30 - P33

P50 - P53

P60 - P63

RESET

E-B

M

B

P10 /INT0

P12/INT2

E-B

B

-C

Remark The types in circles have a Schmitt-triggered input.

8

µPD75402A(A)

(1/2)

Type A (For type E-B)

Type D (For type E-B, F-A)

V

DD

V

DD

Data

P-ch

OUT

IN

Output

disable

N-ch

Push-pull output which can be set to high-impedance output

(off for both P-ch and N-ch)

CMOS input buffer

Type B

Type E-B

VDD

P.U.R.

P-ch

P.U.R.

enable

IN

Data

IN/OUT

Type D

Type A

Output

disable

P.U.R.: Pull-Up Resistor

Schmitt trigger input with hysteresis

Type F-A

Type B-C

VDD

V

DD

P.U.R.

P-ch

P.U.R.

enable

P.U.R.

enable

P-ch

Data

IN/OUT

Type D

Output

disable

IN

Type B

P.U.R.: Pull-Up Resistor

9

µPD75402A(A)

(2/2)

Type F-B

Type M

VDD

P.U.R.

enable

(Mask option)

P.U.R.

IN/OUT

P.U.R.

enable

P-ch

Output

disable

(P)

VDD

Data

N-ch

(Withstand

voltage:

+10 V)

P-ch

Output

disable

IN/OUT

Data

Output

disable

N-ch

Output

disable

(N)

Input buffer with an intermediate

withstand voltage of +10 V

P.U.R.: Pull-Up Resistor

3.4 SELECTION OF A MASK OPTION

The following mask options are provided for pins:

P50 - P53

Pull-up resistors connected

1

(Either can be specified bit by bit.)

No pull-up resistors connected

2

10

µPD75402A(A)

3.5 HANDLING UNUSED PINS

P00

Recommended connection method

Connected to the V^SSpin

P01 - P03

•

When a pull-up resistor is contained

Connected to the VDD pin

P10, P12

•

When a pull-up resistor is not contained

Connected to the VSS or VDD pin

•

When a pull-up resistor is contained

Input mode : Connected to the VDD pin

Output mode : Open

P20 - P23

P30 - P33

P50 - P53

When a pull-up resistor is not contained

Input mode : Connected to the VSS or VDD pin

Output mode : Open

P60 - P63

NC

Note

Open or directly connected to the V^SSpin

Note When the µPD75402A(A) shares the printed circuit board with the µPD75P402, connect the NC pin

directly to V^SSpin.

3.6 NOTES ON USING THE P00 AND RESET PINS

The P00 and RESET pins have the test mode selecting function for testing the internal operation of the

µPD75402A(A) (IC test), besides the functions shown in Sections 3.1 and 3.2.

Applying a voltage exceeding V^DDto the P00 and/or RESET pin causes the µPD75402A(A) to enter the test

mode. When noise exceeding V^DDcomes in during normal operation, the device is switched to the test mode.

For example, when the wiring from the P00 or RESET pin is too long, noise voltage induced on the wiring

is applied to the pin, driving the voltage at the pin above V^DD, which may cause malfunction.

When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If

noise yet arises, use an external part to suppress it as shown below.

•

Connect a capacitor between the pin and VDD.

•

Connect a diode with low VF (0.3 V or lower)

between the pin and V^DD.

V

DD

VDD

Diode with

V

DD

V

DD

low V

F

P00, RESET

11

µPD75402A(A)

4. MEMORY CONFIGURATION

• Program memory (ROM): 1920 × 8 bits (000H to 77FH)

•

000H and 001H: Vector table which contains the program start address after reset

•

002H to 009H : Vector table which contains the program start addresses when interrupts occur

• Data memory

•

Data area

: 64 × 4 bits (000H to 03FH)

•

Peripheral hardware area: 128 × 4 bits (F80H to FFFH)

Fig. 4-1 Program Memory Map

7

0

6

0

5

0

4

0

3

0

Address

000H

Reset start address

(three high-order bits)

001H

002H

003H

004H

Reset start address (eight low-order bits)

INTBT start address

(three high-order bits)

0

Entry address specified in

CALLF !faddr instruction

INTBT start address (eight low-order bits)

INT0 start address

(three high-order bits)

0

005H

INT0 start address (eight low-order bits)

Branch address specified in

BRCB !caddr instruction

Relative branch address specified in

BR $addr instruction

INTCSI start address

(three high-order bits)

008H

009H

0

–15 to –1,

+2 to +16

INTCSI start address (eight low-order bits)

77FH

12

µPD75402A(A)

Fig. 4-2 Data Memory Map

000H

General register

area

(4 × 4)

003H

004H

Data area

Static RAM

(64 × 4)

Bank 0

(64 × 4)

020H

03FH

Stack area

(32 × 4)

No memory

F80H

Peripheral

hardware

area

Bank 15

128 × 4

FFFH

13

µPD75402A(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

The µPD75402A(A) has the following three types of I/O port:

• 6 CMOS input pins (PORT0 and PORT1)

• 12 CMOS I/O pins (PORT2, PORT3, and PORT6)

• 4 N-ch open-drain I/O pins (PORT5)

Total: 22 pins

Table 5-1 Functions of Ports

Port name

PORT0

Operation and feature

Remarks

Also used for SO/SB0, SI, SCK, INT0, and

Function

4-bit Input

Allows read and test at any

PORT1

time regardless of the operation INT2.

modes of dual function pins.

Note

PORT3

Allows input or output mode

setting bit by bit.

—

4-bit I/O

PORT2

PORT6

Allows input or output mode

setting in units of 4 bits.

Port 2 is also used for PCL.

Note

PORT5

Allows input or output mode

setting in units of 4 bits.

This port can incorporate a pull-up

resistor as a mask option bit by bit.

4-bit I/O (N-ch

open-drain I/O

with a withstand

voltage of 10 V)

Note PORT3, PORT5, and PORT6 can directly drive the LED.

14

µPD75402A(A)

5.2 CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC).

The instruction execution time is variable.

• 0.95 µs, 1.91 µs, 15.3 µs (when fXX is 4.19 MHz.)

Fig. 5-1 Block Diagram of the Clock Generator

· Basic interval timer (BT)

· Clock output circuit

· Serial interface

· INT0 noise eliminator

X1

X2

1/16 to 1/512

VDD

System

clock

oscillator

f

XX or f

X

Frequency divider

1/2 1/16

Oscillation

stops.

Frequency

divider

Φ

1/4

· CPU

PCC

· INT0 noise

eliminator

· Clock output

circuit

PCC0

PCC1

HALT flip-

flop

4

PCC2

PCC3

S

HALT*

STOP*

R

Q

All bits are

cleared.

RESET input rising edge

detection signal

STOP flip-

flop

PCC2 is

cleared.

Q

S

R

RESET input falling

edge detection signal

Standby release signal

from interrupt control circuit

Remarks 1. fXX = Crystal/ceramic oscillated frequency

2. f^X= External clock frequency

3. Φ = CPU clock

4. An asterisk (*) indicates instruction execution.

5. PCC: Processor clock control register

6. One clock cycle (t^CY) of Φ is equal to one machine cycle of an instruction. See AC

characteristics of Chapter 10 for details of t^CY.

15

µPD75402A(A)

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit, which outputs clock pulses from pin P22/PCL, is used for supplying clock pulses

for peripheral LSIs or for remote control output.

•

Clock output (PCL): 1.05 MHz, 524 kHz, 65.5 kHz (when f^XXis 4.19 MHz).

Fig. 5-2 shows the configuration of the clock output circuit.

Fig. 5-2 Configuration of the Clock Output Circuit

From the clock

generator

Φ

Output

buffer

Selector

P22/PCL

X

f

X

/2⁶

PORT2.2

Bit 2 of PMGB

Port 2 input/

output mode

specification bit

P22 output

latch

CLOM3

0

CLOM1 CLOM0 CLOM

4

Internal bus

Remark The clock output circuit is designed not to output high-frequency pulses when clock output is

switched between the enable and disable states.

16

µPD75402A(A)

5.4 BASIC INTERVAL TIMER

The basic interval timer provides the following functions:

•

Interval timer operation that generates a reference time interrupt

Can be used as a watchdog timer for detecting program crashes

Reading the count value

Fig. 5-3 Configuration of the Basic Interval Timer

From the

clock

Clear

generator

f

XX /2⁵

BT

interrupt

request flag

Set

Basic interval timer

(8-bit frequency divider)

MPX

Vectored

interrupt

request

signal

f

XX /2⁹

BT

IRQBT

BTM3

BTM2

1

BTM

4

8

Internal bus

17

µPD75402A(A)

5.5 SERIAL INTERFACE

The serial interface has the following modes:

•

Three-wire serial I/O mode (MSB is transferred first.)

SBI mode (MSB is transferred first.)

The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many

other types of peripheral I/O devices.

The SBI mode enables communication with two or more devices.

18

µPD75402A(A)

6. INTERRUPT FUNCTION

The µPD75402A(A) has three interrupt sources and each of them has the interrupt vector table.

The µPD75402A(A) is also provided with one edge-sensitive testable input signal.

When a vectored interrupt request is issued, the PC and PSW are saved in the stack, and the contents of

the vector table which corresponds to the issued vectored interrupt are set in the PC as a start address. The

program branches to the interrupt service routine. These operations are performed automatically by the

hardware.

The flag is set by detecting the edge of the testable input signal, but a vectored interrupt request is not

issued.

During execution of the interrupt service routine, the µPD75402A(A) does not accept the other interrupt

requests. Unlike the other 75X series, the µPD75402A(A) cannot handle multiple interrupts.

The interrupt control circuit of the µPD75402A(A) has the following functions.

•

Vectored interrupt function under hardware control which can determine whether to accept an interrupt

by an interrupt enable flag (IE×××) and an interrupt master enable flag (IME).

Any interrupt start address can be set.

•

Test function of an interrupt request flag (IRQ×××) (Software can confirm that an interrupt occurs.)

Release of the standby (HALT) mode (An interrupt to be released by an interrupt enable flag can be selected

from interrupts other than INT0.)

20

µPD75402A(A)

7. STANDBY FUNCTION

To reduce the power consumption when the program is in the wait state, theµPD75402A(A) has two standby

modes, STOP and HALT.

Table 7-1 Operation Statuses in the Standby Mode

STOP mode

STOP instruction

HALT mode

HALT instruction

Instruction to be used to

set mode

Oscillation of the system clock stops.

Operation stops.

Opera-

tion

Clock generator

Only the CPU clock (Φ) stops, but

oscillation continues.

status

Basic interval

timer

Operates. (IRQBT is set at every refer-

ence time interval.)

Operable only when the external SCK

input is selected for the serial clock.

Serial interface

Operable

Operation stops.

Clock output

circuit

Clocks other than CPU clock (Φ) can be

output.

INT2 pin is usable.

External

interrupt

INT2 pin is usable.

INT0 pin cannot be used.

Operation stops.

RESET input

CPU

Release signal

RESET input or interrupt request signals

enabled by the interrupt enable flags

22

µPD75402A(A)

8. RESET FUNCTION

When a low level signal is input to the RESET input pin, the state changes to the system reset. Table 8-1

shows the statuses of the hardware.

When the RESET signal rises from the low level to the high level, the reset state is released. The three low-

order bits of the reset vector table whose address is 000H is set in bits 10 to 8 of the program counter (PC)

and the contents of the reset vector table whose address is 001H is set in bits 7 to 0 of the PC. The program

branches to that address and starts execution, i.e., the reset start address is programmable.

Initialize contents of registers in a program if necessary.

The RESET pin connects to the Schmitt-trigger circuit whose threshold level has hysteresis in the chip. This

pin is also connected to the noise eliminator using an analog delay to eliminate narrow noise and prevent

errors caused by noise. (See Fig. 8-1.)

For the power-on reset operation, be sure to allow sufficient time for oscillation to settle between power

on and acceptance of the reset signal (see Fig. 8-2).

Fig. 8-1 Acceptance of the Reset Signal

RESET

The instruction which

is stored at the reset

branch address is executed.

Content of the reset

vector table is set

to the PC

Analog

delay

Analog

delay

Analog

delay

(the initialization of the PC).

Elimination

as noise.

This low level

signal is accepted released.

as the reset signal.

The reset is

Fig. 8-2 Power-On Reset Operation

VDD

RESET

Oscillation

settling time

The instruction which is stored

at the reset branch address is

executed.

Analog

delay

Content of the reset vector

table is set to the PC

(the initialization of the PC).

The reset

is released.

23

µPD75402A(A)

Table 8-1 Hardware Statuses after Reset Operations

Hardware

Program counter (PC)

RESET input in standby mode

RESET input during operations

Set the three low-order bits of

address 000H in program

memory in PC bits 10 to 8 and

set the contents of address

001H in PC bits 7 to 0.

address 000H in program

memory in PC bits 10 to 8 and

set the contents of address

001H in PC bits 7 to 0.

PSW

Carry flag (CY)

Retained

Undefined

Skip flag (SK0 - SK2)

0

Interrupt status flag (IST0)

0

Stack pointer (SP)

Undefined

Note

Data memory (RAM)

General register (X, A, H, L)

Retained

Undefined

Retained

Undefined

Basic interval

timer

Counter (BT)

Undefined

Mode register (BTM)

0

Serial

Shift register (SIO)

Retained

Undefined

interface

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

0

Retained

0

Undefined

0

Clock genera-

tor and clock

output circuit

Processor clock control register

(PCC)

Clock output mode register

(CLOM)

0

Interrupt

Reset (0)

Interrupt request flag (IRQ×××)

Interrupt enable flag (IE×××)

0

Interrupt master enable flag

(IME)

INT0 mode register (IM0)

Output buffer

0

Digital I/O

port

Off

Cleared (0)

0

Off

Cleared (0)

0

Output latch

I/O mode register

(PMGA, PMGB)

Pull-up resistor specification

register (POGA)

0

States of pins

P00 - P03, P10, P12, P20 - P23,

P30 - P33, P60 - P63

Used as inputs

P50 - P53

•

High level when pull-up

resistor is built in

•

High level when pull-up

resistor is built in

High impedance when

open drain is used in the

internal circuit

High impedance when

open drain is used in the

internal circuit

Note Data in the data memory whose addresses are 38H to 3DH is not defined when the standby mode

is released by the RESET input signal.

24

µPD75402A(A)

9. INSTRUCTION SET

(1) Representation format and description method of operands

An operand is described in the operand field of each instruction according to the description method

corresponding to the operand representation format of the instruction refer to"RA75X Assembler Package

User's Manual, Language" (EEU-1363) for details. When two or more elements are described in the

description method field, select one of them. Upper-case letters, a number sign (#), and at mark (@), an

exclamation mark (!), and a dollar sign ($) are keywords, so they can be used without alteration.

Specify an appropriate numeric value or label for immediate data.

The symbols of registers and flags can be used as labels instead of mem, fmem, and bit (refer to the

"µPD75402A User's Manual" (IEU-644) for details). Some labels, however, cannot be specified in fmem.

Representation format

Description method

reg

X, A, H, L

X, H, L

reg1

rp

XA, HL

n4

n8

4-bit immediate data or label

8-bit immediate data or label

Note

mem

bit

8-bit immediate data or label

2-bit immediate data or label

fmem

FB0H - FBFH/FF0H - FFFH immediate data or label

addr

11-bit immediate data or label

caddr

faddr

PORT0 - PORT3, PORT5, PORT6

IEBT, IECSI, IE0, IE2

PORTn

IE×××

Note Only an even address can be written in mem when 8-bit data is processed.

(2) Legend

A

: A register, 4-bit accumulator

: H register

H

L

: L register

X

: X register

XA

HL

PC

SP

CY

: Register pair (XA), 8-bit accumulator

: Register pair (HL)

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW : Program status word

PORTn: Port n (n = 0 to 3, 5, 6)

IME : Interrupt master enable flag

IE××× : Interrupt enable flag

PCC : Processor clock control register

·

: Address/bit delimiter

(××)

: Contents addressed by ××

××H : Hexadecimal data

25

µPD75402A(A)

(3) Explanation of the symbols in the addressing area field

*1

*2

MB = 0

MB = 0 (00H - 3FH)

MB = 15 (80H - FFH)

Data memory

addressing

*3

MB = 15, fmem = FB0H - FBFH or

FF0H - FFFH

*4

*5

addr = 000H - 77FH

addr = (Current PC) – 15 to (Current PC) – 1 or

(Current PC) + 16 to (Current PC) + 2

Program memory

addressing

*6

*7

caddr = 000H - 77FH

faddr = 000H - 77FH

Remarks 1. MB indicates an accessible memory bank.

2. *4 to *7 indicate each addressable area.

(4) Explanation of the machine cycle field

S indicates the number of machine cycles required for a skip instruction to perform skipping. The following

shows the values of S.

•

When the next instruction is not skipped, S is 0.

When the next instruction is skipped, S is 1.

A machine cycle is equal to one cycle (= t^CY) of CPU clock Φ. A PCC setting determines the machine cycle.

It can be set to one of three different periods.

26

µPD75402A(A)

Instruc-

tion

Number Ma-

Address- Skip

Mne-

Operand

of

chine

Operation

ing area

condition

monic

group

bytes

cycle

Transfer

instruc-

tion

A, #n4

1

2

1

2

1

2

1

String A

String B

MOV

A ← n4

XA, #n8

HL, #n8

A, @HL

@HL, A

A, mem

XA, mem

mem, A

mem, XA

A, @HL

A, mem

XA, mem

A, reg1

XA, @PCXA

A, #n4

2

XA ← n8

HL ← n8

A ← (HL)

(HL) ← A

A ← (mem)

2

1

*1

*2

*1

*2

1

2

XA ← (mem)

(mem) ← A

2

(mem) ← XA

A ↔ (HL)

1

XCH

2

A ↔ (mem)

2

XA ↔ (mem)

A ↔ reg1

1

MOVT

ADDS

3

XA ← (PC^10-8+ XA)ROM

A ← A + n4

1 + S

carry

Arithme-

tic/

A, @HL

A

1 + S

*1

A ← A + (HL)

A, CY ← A + (HL) + CY

logical

instruc-

tion

ADDC

AND

OR

1

A ← A

(HL)

XOR

RORC

Accumu-

lator

CY ← A0, A3 ← CY, An–1 ← An

manipu-

lation

A

2

NOT

A ← A

instruc-

tion

Incre-

ment/

decre-

ment

reg

1

2

1 + S

2 + S

reg = 0

INCS

reg ← reg + 1

mem

*2

*1

(mem) = 0

(mem) ← (mem) + 1

reg ← reg – 1

instruc-

tion

reg

1

2

1 + S

2 + S

reg = FH

reg = n4

DECS

SKE

Skip if reg = n4

Compari-

son

reg, #n4

instruc-

tion

Skip if A = (HL)

A, @HL

1

1 + S

A = (HL)

Carry flag

manipu-

lation

CY

1

SET1

CLR1

SKT

CY ← 1

CY ← 0

1 + S

1

CY = 1

Skip if CY = 1

CY ← CY

instruc-

tion

NOT1

27

µPD75402A(A)

Instruc-

tion

Number Ma-

Address- Skip

Mne-

Operand

of

chine

Operation

ing area

condition

monic

group

bytes

cycle

Memory

bit

mem.bit

2

–

2

*2

*3

*2

*3

*2

*3

*2

*3

*4

SET1

(mem.bit) ← 1

fmem.bit

mem.bit

2

(fmem.bit) ← 1

manipu-

lation

instruc-

tion

CLR1

SKT

SKF

(mem.bit) ← 0

fmem.bit

mem.bit

2

(fmem.bit) ← 0

2 + S

2

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (fmem.bit) = 1 and clear

(mem.bit) = 1

(fmem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

fmem.bit

mem.bit

fmem.bit

CY, fmem.bit

addr

(

fmem.bit) = 1

SKTCLR

AND1

OR1

CY ← CY

(fmem.bit)

2

XOR1

BR

Branch

instruc-

tion

–

PC10-0 ← addr

(The assembler selects an

appropriate instruction from the

BRCB !caddr and BR $addr

instructions.)

$addr

!caddr

!faddr

1

2

*5

*6

*7

PC^10-0← addr

PC10-0 ← caddr

BRCB

Subrou-

tine

CALLF

(SP – 4)(SP – 1)(SP – 2) ← 0, PC10-0

(SP – 3) ← 0000

stack

PC10-0 ← faddr, SP ← SP – 4

control

instruc-

tion

1

3

3 + S

3

RET

×, PC^10-0← (SP)(SP + 3)(SP + 2)

SP ← SP + 4

Uncondition-

ally

RETS

RETI

×, PC10-0 ← (SP)(SP + 3)(SP + 2)

SP ← SP + 4, then skip unconditionally

×, PC10-0 ← (SP)(SP + 3)(SP + 2)

PSW ← (SP + 4)(SP + 5), SP ← SP + 6

rp

1

2

1

2

PUSH

POP

EI

(SP – 1)(SP – 2) ← rp, SP ← SP – 2

rp ← (SP + 1)(SP), SP ← SP + 2

IME (IPS.3) ← 1

Interrupt

control

instruc-

tion

IE×××

IE××× ← 1

DI

IME (IPS.3) ← 0

IE×××

IE××× ← 0

Input/

output

instruc-

tion

IN

A, PORTn

A ← PORTn

(n = 0 - 3, 5, 6)

(n = 2, 3, 5, 6)

2

OUT

PORTn, A

PORT n ← A

CPU

2

1

2

1

HALT

STOP

NOP

Set HALT mode (PCC.2 ← 1)

Set STOP mode (PCC.3 ← 1)

No operation

control

instruction

28

µPD75402A(A)

10. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (Ta = 25 ˚C)

Parameter

Supply voltage

Input voltage

Symbol

V^DD

Conditions

Rated value

Unit

V

–0.3 to +7.0

VI1

Ports other than port 5

–0.3 to V^DD+ 0.3

V

VI2

Port 5

Built-in pull-up resistor

Open drain

–0.3 to V^DD+ 0.3

V

–0.3 to +11.0

V

Output voltage

VO

IOH

–0.3 to VDD + 0.3

V

High-level output

current

Each pin

–15

mA

˚C

Total of all output pins

–30

Note

Low-level output

current

IOL

One pin of port 0, 3, 5, or 6

Peak value

rms

30

15

One pin of port 2

Peak value

rms

20

10

Total of all pins of ports 0, 3,

and 5 (excl. P33)

Peak value

rms

100

60

Total of all pins of ports 2, 6,

and P33

Peak value

rms

100

60

Operating

Topt

Tstg

–40 to +85

temperature

Storage tempera-

ture

–65 to +150

˚C

Note Calculate rms with [rms] = [peak value] × duty.

√

Caution Absolute maximum ratings are rated values beyond which some physical damages may be

caused to the product; if any of the parameters in the table above exceeds its rated value even

for a moment, the quality of the product may deteriorate. Be sure to use the product within the

rated values.

29

µPD75402A(A)

CHARACTERISTICS OF THE OSCILLATION CIRCUIT (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V)

Recommended

constant

Typ.

Max.

Unit

MHz

Resonator

Parameter

Conditions

Min.

2.0

Note 3

5.0

Ceramic

Oscillator

frequency

VDD = oscillation

voltage range

resonator

X1

X2

Note 1

(fXX)

4

ms

MHz

ms

Oscillation

After VDD reaches

MIN. of the oscilla-

tion voltage range

C1

C2

settling time

Note 2

Note 3

4.19

5.0

Crystal

Oscillator

frequency

2.0

Note 1

(fXX)

10

Oscillation

VDD = 4.5 to 6.0 V

settling time

Note 2

Note 3

MHz

ns

External

clock

X1 input

2.0

frequency

X1

X2

Note 1

(f^X)

250

X1 input

high/low

level width

(tXH, tXL)

100

µPD74HCU04

Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See

the item of AC characteristics for the instruction execution time.

2. The oscillation settling time means the time required for the oscillation to settle after V^DDis applied

or after the STOP mode is released.

3. When 4.19 MHz < f^X≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When

PCC = 0011, one machine cycle falls short of 0.95 µs, the minimum value for the standard.

★

Caution When the clock oscillator is used, conform to the following guidelines when wiring at the

portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring

capacity.

• The wiring must be as short as possible.

• Other signal lines must not run in these areas.

• Any line carrying a high fluctuating current must be kept away as far as possible.

• The grounding point of the capacitor of the oscillator must have the same potential as that

of V^SS. It must not be grounded to ground patterns carrying a large current.

• No signal must be taken from the oscillator.

CAPACITANCE (T^a= 25 ˚C, V DD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

C^IN

Conditions

Min.

Typ.

Max.

15

Unit

pF

f = 1 MHz

0 V for pins other than pins to be

measured

COUT

CIO

15

pF

15

pF

30

µPD75402A(A)

DC CHARACTERISTICS (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V)

Conditions

Ports 2, 3, and 6

Ports 0 and 1, and RESET

Min.

0.7V^DD

0.8VDD

0.7VDD

VDD – 0.5

0

Parameter

Symbol

VIH1

Typ.

Max.

VDD

Unit

V

High-level input

voltage

VIH2

VDD

V

Port 5

Built-in pull-up resistor

Open drain

VIH3

VDD

V

10

V

X1 and X2

VIH4

VIL1

VIL2

VIL3

VOH

V^DD

V

Ports 2, 3, 5, and 6

Ports 0 and 1, and RESET

X1 and X2

Low-level input

voltage

0.3VDD

0.2VDD

0.4

V

0

V

0

V

Ports 0, 2,

3, and 6

VDD = 4.5 to 6.0 V, IOH = –1 mA

I^OH= –100

V^DD– 1.0

V^DD– 0.5

High-level output

voltage

V

µ

A

V

Ports 3, 5,

and 6

VDD = 4.5 to 6.0 V, IOL = 15 mA

Low-level output

voltage

VOL

0.6

2.0

V

Ports 0, 2,

3, 5, and 6

VDD = 4.5 to 6.0 V, IOL = 1.6 mA

0.4

0.5

V

IOL = 400 µA

SB0 (Open

drain)

Pull-up resistor : 1 kΩ or

0.2V^DD

more VDD = 4.5 to 6.0 V

V^IN= VDD

Other than X1 and X2

X1 and X2

High-level input

leakage current

ILIH1

ILIH2

ILIH3

ILIL1

ILIL2

ILOH1

ILOH2

ILOL

3

µA

20

– 3

– 20

3

VIN = 10 V

V^IN= 0 V

Port 5 (open drain)

Other than X1 and X2

X1 and X2

Low-level input

leakage current

V^OUT= VDD

VOUT = 10 V

VOUT = 0 V

Other than port 5

Port 5 (open drain)

High-level output

leakage current

20

– 3

Low-level output

leakage current

Ports 0, 1, 2, 3, and

6 (excl. P00 and

P10) VIN = 0 V

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

VDD = 5.0 V ±10 %

15

30

Built-in pull-up

resistor

RL1

40

80

kΩ

300

Port 5

15

10

RL2

IDD1

IDD2

IDD3

70

60

kΩ

VOUT = VDD – 2.0 V

VDD = 3.0 V ±10 %

Note 2

VDD = 5.0 V ±10 %

4.19 MHz

crystal

Power supply

2.5

0.5

500

150

0.5

0.1

8

mA

Note 1

current

Note 3

VDD = 3.0 V ±10 %

1.5

1500

450

20

resonance

C1 = C2 =

22 pF

VDD = 5.0 V ±10 %

VDD = 3.0 V ±10 %

HALT

mode

µA

VDD = 5.0 V ±10 %

STOP

mode

VDD =

10

3.0 V ±10 %

Ta = 25 ˚C

5

Notes 1. This current excludes the current which flows through the built-in pull-up resistors.

2. Value when the processor clock control resistor (PCC) is set to 0011 and the µPD75402A(A) is

operated in the high-speed mode

3. Value when the PCC is set to 0000 and the µPD75402A(A) is operated in the low-speed mode

31

µPD75402A(A)

AC CHARACTERISTICS (Ta = –40 to +85 ˚C, V DD = 2.7 to 6.0 V, VSS = 0 V)

Parameter

Unit

Symbol

t^CY

Conditions

V^DD= 4.5 to 6.0 V

Min.

0.95

3.8

Typ.

Max.

Note 1

µs

CPU clock cycle time

32

(minimum instruction execu-

tion time = one machine cycle)

µs

32

Note 2

10

µs

Interrupt input high/low level

width

tINTH, tINTL

tRSL

INT0

INT2

RESET low-level width

10

t

CY vs. VDD

40

32

Notes 1. The cycle time of the CPU clock (Φ)

(minimuminstructionexecutiontime)

depends on the connected resonator

frequency and the setting of the proc-

essor clock control register (PCC).

The figure on the right side shows

the cycle time t^CYcharacteristics for

the supply voltage V^DD.

7

6

5

Guaranteed operating

range

4

µ

3

2

2. This value is 2t^CYor 128/fXX according

to the setting of the interrupt mode

register (IM0).

1

0.5

0

1

2

3

4

5

6

Supply voltage V^DD[V]

32

µPD75402A(A)

Serial transfer operation

Three-wire serial I/O mode (SCK ··· Internal clock output):

Conditions

VDD = 4.5 to 6.0 V

Parameter

Min.

1600

Typ.

Max.

Unit

ns

Symbol

t^KCY1

SCK cycle time

3800

ns

VDD = 4.5 to 6.0 V

SCK high/low level

width

tKCY1/2 – 50

tKCY1/2 – 150

150

ns

tKL1

tKH1

tSIK1

ns

SI setup time

(referred to SCK↑)

SI hold time

400

ns

tKSI1

(referred to SCK↑)

VDD = 4.5 to 6.0 V

0

ns

Delay from SCK↓ to

tKSO1

RL = 1 kΩ,

250

Note

SO output

CL = 100 pF

1000

Note R^Land CL are the resistance and capacitance of the SO output line load respectively.

Three-wire serial I/O mode (SCK ··· External clock input):

Symbol

Min.

800

Typ.

Max.

Unit

ns

Parameter

Conditions

V^DD= 4.5 to 6.0 V

tKCY2

SCK cycle time

3200

400

ns

tKL2

tKH2

tSIK2

ns

SCK high/low level

width

V^DD= 4.5 to 6.0 V

1600

100

ns

SI setup time

(referred to SCK↑)

tKSI2

400

ns

SI hold time

(referred to SCK↑)

tKSO2

0

300

ns

Delay from SCK↓ to

VDD = 4.5 to 6.0 V

R^L= 1 kΩ,

Note

SO output

CL = 100 pF

1000

Note RL and CL are the resistance and capacitance of the SO output line load respectively.

33

µPD75402A(A)

SBI mode (SCK ··· Internal clock output (master)):

Symbol

Conditions

V^DD= 4.5 to 6.0 V

Parameter

Min.

1600

Typ.

Max.

Unit

ns

tKCY3

SCK cycle time

3800

ns

tKL3

tKH3

tSIK3

V^DD= 4.5 to 6.0 V

SCK high/low level

width

tKCY3/2 – 50

tKCY3/2 – 150

150

ns

SB0 setup time

(referred to SCK↑)

tKSI3

tKCY3/2

ns

SB0 hold time

(referred to SCK↑)

tKSO3

0

250

ns

Delay from SCK↓ to

VDD = 4.5 to 6.0 V

SB0 output

0

1000

tKSB

tSBK

tSBL

tSBH

t^KCY3

tKCY3

DelayfromSCK↑ toSB0↓

DelayfromSB0↓ toSCK

SB0 low-level width

SB0 high-level width

SBI mode (SCK ··· External clock input (slave)):

Symbol

t^KCY4

Conditions

VDD = 4.5 to 6.0 V

Parameter

Min.

800

Typ.

Max.

Unit

ns

SCK cycle time

3200

400

ns

tKL4

tKH4

tSIK4

VDD = 4.5 to 6.0 V

SCK high/low level

width

ns

1600

100

ns

SB0 setup time

(referred to SCK↑)

tKSI4

t^KCY4/2

ns

SB0 hold time

(referred to SCK↑)

tKSO4

VDD = 4.5 to 6.0 V

0

300

ns

RL = 1 kΩ,

Delay from SCK↓ to

Note

CL = 100 pF

SB0 output

0

1000

tKSB

tSBK

tSBL

tSBH

t^KCY4

tKCY4

DelayfromSCK↑ toSB0↓

DelayfromSB0↓ toSCK↓

SB0 low-level width

SB0 high-level width

Note R^Land CL are the resistance and capacitance of the SO output line load respectively.

34

µPD75402A(A)

AC Timing Measurement Points (Excluding X1 Input)

0.8V^DD

0.2VDD

0.8VDD

0.2VDD

Measurement

point

Clock Timing

1/f

X

tXL

t

XH

V

DD – 0.5 V

X1 input

0.4 V

Serial Transfer Timing

Three-wire serial I/O mode:

t

KCY1

t

KL1

t

KH1

SCK

t

SIK1

t

KSI1

Input data

SI

t

KSO1

SO

Output data

35

µPD75402A(A)

Serial Transfer Timing

Bus release signal transfer:

t

KCY3, 4

t

KL3, 4

tKH3, 4

SCK

t

SIK3, 4

t

KSI3, 4

t

KSB

tSBL

t

SBH

t

SBK

SB0

t

KSO3, 4

Command signal transfer:

tKCY3, 4

tKL3, 4

tKH3, 4

SCK

t

SIK3, 4

tKSI3, 4

tKSB

tSBK

SB0

t

KSO3, 4

Interrupt Input Timing

tINTL

tINTH

INT0, INT2

RESET Input Timing

t

RSL

RESET

36

µPD75402A(A)

DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE

(T^a= –40 to +85 ˚C)

Symbol

V^DDDR

Parameter

Min.

2.0

Typ.

0.1

Max.

6.0

Unit

V

Conditions

Data hold supply

voltage

IDDDR

Data hold supply

current

10

V^DDDR= 2.0 V

µA

tSRS

tOS

RESET setup time

0

µs

Oscillation settling

time

4

ms

After VDD reaches the oscillation

voltage range when the ceramic

resonator is connected

10

ms

After VDD reaches the oscillation

voltage range when the crystal is

connected

Data Hold Timing (STOP Mode Release by RESET)

HALT mode

STOP mode

Data hold mode

Operating mode

VDD

V

DDDR

tSRS

STOP instruction execution

RESET

t

OS

37

µPD75402A(A)

11. PACKAGE DIMENSIONS

28 PIN PLASTIC DIP (600 mil)

28

15

1

14

A

K

L

F

M

R

C

B

M

D

N

NOTES

1) Each lead centerline is located within 0.25 mm (0.01 inch)

of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

INCHES

1.500 MAX.

0.100 MAX.

0.100 (T.P.)

+0.004

A

B

C

38.10 MAX.

2.54 MAX.

2.54 (T.P.)

2) Item "K" to center of leads when formed parallel.

D

0.50±0.10

0.020

–0.005

F

G

H

I

1.2 MIN.

3.6±0.3

0.047 MIN.

0.142±0.012

0.020 MIN.

0.170 MAX.

0.226 MAX.

0.600 (T.P.)

0.520

0.51 MIN.

4.31 MAX.

5.72 MAX.

15.24 (T.P.)

13.2

J

K

L

+0.10

0.25

+0.004

0.010

M

–0.05

–0.003

N

R

0.25

0.01

0

‘15

0

‘15

P28C-100-600A1-1

38

µPD75402A(A)

28PIN PLASTIC SHRINK DIP (400 mil)

28

15

1

14

A

K

L

I

J

F

C

H

M

R

M

D

N

B

G

NOTES

ITEM MILLIMETERS

INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

A

B

C

28.46 MAX.

2.67 MAX.

1.778 (T.P.)

1.121 MAX.

0.106 MAX.

0.070 (T.P.)

2) ltem "K" to center of leads when formed parallel.

+0.004

0.020

D

0.50±0.10

–0.005

F

G

H

I

0.9 MIN.

3.2±0.3

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.400 (T.P.)

0.339

0.51 MIN.

4.31 MAX.

5.08 MAX.

10.16 (T.P.)

8.6

J

K

L

+0.10

0.25

+0.004

0.010

M

–0.05

–0.003

N

R

0.17

0.007

0~15°

P28C-70-400A-1

39

µPD75402A(A)

44 PIN PLASTIC QFP ( 10)

A

B

23

22

33

34

detail of lead end

S

C

D

R

Q

12

11

44

1

F

G

J

M

I

H

K

M

P

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.15 mm (0.006 inch) of

its true position (T.P.) at maximum material condition.

+0.017

A

B

C

D

13.6±0.4

10.0±0.2

13.6±0.4

0.535

0.394

0.535

–0.016

+0.008

–0.009

+0.008

–0.009

+0.017

–0.016

F

1.0

0.039

G

+0.004

–0.005

H

0.35±0.10

0.014

I

0.15

0.006

J

0.8 (T.P.)

0.031 (T.P)

+0.008

0.071

K

L

1.8±0.2

0.8±0.2

–0.009

+0.009

0.031

–0.008

+0.10

0.15

+0.004

0.006

M

–0.05

–0.003

N

P

Q

R

S

0.10

0.004

2.7

0.106

0.1±0.1

5°±5°

3.0 MAX.

0.004±0.004

5°±5°

0.119 MAX.

P44GB-80-3B4-3

40

µPD75402A(A)

PACKAGE DIMENSIONS OF THE 44-PIN CERAMIC QFP FOR ES (REF. DWG.) (UNIT: MM)

11.43

8.0

44

34

1

33

11

23

12

22

0.15

0.8

0.32

(Bottom)

Cautions 1. Find the location of pin 1 by checking the location of pin 17, which is connected to the metal cap.

2. The metal cap is connected to pin 17. The electrical level of the metal cap is V^SS(GND).

3. Theleadlengthhasnotbeenspecifiedbecauseleadsarecutwithoutanydetailedspecifications.

41

µPD75402A(A)

12. RECOMMENDED SOLDERING CONDITIONS

The following conditions shall be met when soldering the µPD75402A(A).

For details of the recommended soldering conditions, refer to our document "SMD Surface Mount

Technology Manual" (IEI-1207).

Please consult with our sales offices in case other soldering process is used, or in case soldering is done

under different conditions.

Table 12-1 Soldering Conditions for Surface-Mount Devices

µPD75402AGB(A)-×××-3B4: 44-pin plastic QFP (10 × 10 mm)

Symbol

IR30-00-1

Soldering process

Infrared ray reflow

Soldering conditions

Peak package’s surface temperature: 230 ˚C

Reflow time: 30 seconds or less (210 ˚C or more)

Number of reflow processes: 1

VP15-00-1

WS60-00-1

VPS

Peak package’s surface temperature: 215 ˚C

Reflow time: 40 seconds or less (200 ˚C or more)

Number of reflow processes: 1

Wave soldering

Solder temperature: 260 ˚C or less

Flow time: 10 seconds or less

Number of flow processes: 1

Preheating temperature: 120 ˚C max. (measured on the package

surface)

—

Partial heating method

Terminal temperature: 300 ˚C or less

Flow time: 3 seconds or less (for each side of device)

Caution Do not apply more than a single process at once, except for “Partial heating method.”

Table 12-2 Soldering Conditions for Insertion-Mount Devices

µPD75402AC(A)-×××: 28-pin plastic DIP (600 mil)

µPD75402ACT(A)-×××: 28-pin plastic shrink DIP (400 mil)

Soldering process

Soldering conditions

Solder temperature: 260 ˚C or less

Wave soldering

(Only for leads)

Flow time: 10 seconds or less

Partial heating method

Terminal temperature: 260 ˚C or less

Flow time: 10 seconds or less

Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does

not come in contact with the main body of the package.

Notice

Other versions of the products are available. For these versions, the recommended reflow

soldering conditions have been mitigated as follows:

Higher peak temperature (235 °C), two-stage, and longer exposure limit.

Contact an NEC representative for details.

42

µPD75402A(A)

APPENDIX A DIFFERENCES BETWEEN THE µPD75402A(A) AND µPD75P402

Product

µPD75402A(A)

µPD75P402

Item

One-time PROM

Masked ROM

ROM

22

6

I/O ports Input

I/O

16

(Pull-up resistors can be connected by software.)

12

4 (No pull-up resistors can be connected.)

N-ch I/O

4 (Pull-up resistors can be connected by

mask option.)

VPP, PROM program-

ming pin

Provided

Not provided

Electrical Operating

5 V ±10 %

2.7 to 6.0 V

charac-

teristics

supply

voltage

Operating

tempera-

ture

-10 to +70 ˚C

Standard

-40 to +85 ˚C

Special

Quality grade

43

µPD75402A(A)

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for developing systems including the µPD75402A(A)

Note 1

IE-75000-R

IE-75001-R

In-circuit emulator for the 75X series

Note 2

IE-75000-R-EM

EP-75402C-R

EP-75402GB-R

Emulation board for the IE-75000-R and IE-75001-R

Emulation probe for the µPD75402AC(A) and µPD75402ACT(A)

Emulation probe for the µPD75402AGB(A). A 44-pin conversion socket, the EV-9200G-44,

is attached to the probe.

EV-9200G-44

PG-1500

PROM programmer

PA-75P402CT

PROM programmer adapter for the µPD75P402C and µPD75P402CT. Connected to the

PG-1500.

PA-75P402GB

PROM programmer adapter for the µPD75P402GB. Connected to the PG-1500.

Host machine

IE control program

PG-1500 controller

TM

Note 3

• PC-9800 series (MS-DOS

Ver. 3.30 to Ver. 5.00A

Ver. 3.1)

)

TM

• IBM PC/AT

(PC DOS

RA75X relocatable

assembler

Notes 1. Maintenance service only

2. Not contained in the IE-75001-R

3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and

Ver. 5.00A.

Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.

44

µPD75402A(A)

★

APPENDIX C RELATED DOCUMENTS

Documents related to the device

Document name

User’s manual

Document No.

IEU-644

IEA-638

IF-1027

Application note

75X series selection guide

Documents related to development tools

Document name

Document No.

IE-75000-R/IE-75001-R User’s Manual

IE-75000-R-EM User’s Manual

EP-75402C-R User’s Manual

EP-75402GB-R User’s Manual

PG-1500 User’s Manual

EEU-1416

EEU-1294

EEU-701

EEU-702

EEU-1335

EEU-1346

Operation

Language

RA75X Assembler Package User’s Manual

EEU-1363

EEU-1291

PG-1500 Controller User’s Manual


型号：	UPD75402A
厂家：	NEC
描述：	4 BIT SINGLE-CHIP MICROCOMPUTER 4位单片机计算机
文件：	总48页 (文件大小：502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD75402A [NEC]

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UPD75402ACT-XXX

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UPD75402AGB(A)-XXX-3B4

UPD75402AGB-XXX-3B4