UPD780344_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD78F0034A, 78F0034AY

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD78F0034A is a member of the µPD780034A Subseries in the 78K/0 Series, and is equivalent to the

µPD780034A but with flash memory in place of internal ROM.

The µPD78F0034AY is a member of the µPD780034AY Subseries, featuring flash memory in place of the internal

ROM of the µPD780034AY.

The µPD78F0034A incorporates flash memory, which can be programmed and erased while mounted on the board.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual: U14046E

78K/0 Series Instruction User’s Manual: U12326E

FEATURES

•

Pin-compatible with mask ROM versions (except VPP pin)

Flash memory:

32 KB^Note

Internal high-speed RAM: 1,024 bytes^Note

Supply voltage: VDD = 1.8 to 5.5 V

Note The flash memory and internal high-speed RAM capacities can be changed with the memory size switching

register (IMS).

Remark For the differences between the flash memory and the mask ROM versions, refer to 4. DIFFERENCES

BETWEEN µPD78F0034A, 78F0034AY, AND MASK ROM VERSIONS.

ORDERING INFORMATION

Part Number

Package

Internal ROM

µPD78F0034ACW

64-pin plastic SDIP (19.05 mm (750))

64-pin plastic LQFP (10 × 10)

64-pin plastic LQFP (14 × 14)

64-pin plastic QFP (14 × 14)

64-pin plastic TQFP (12 × 12)

64-pin plastic SDIP (19.05 mm (750))

64-pin plastic LQFP (10 × 10)

64-pin plastic LQFP (14 × 14)

64-pin plastic QFP (14 × 14)

64-pin plastic TQFP (12 × 12)

Flash memory

µPD78F0034AGB-8EU

µPD78F0034AGC-8BS

µPD78F0034AGC-AB8

µPD78F0034AGK-9ET

µPD78F0034AYCW

µPD78F0034AYGB-8EU

µPD78F0034AYGC-8BS

µPD78F0034AYGC-AB8

µPD78F0034AYGK-9ET

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. U14040EJ4V0DS00 (4th edition)

Date Published April 2002 N CP(K)

Printed in Japan

The mark

shows major revised points.

1999, 2000

©

µPD78F0034A, 78F0034AY

78K/0 SERIES LINEUP

The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Y subseries products are compatible with I²C bus.

Control

µ

EMI-noise reduced version of the PD78078

PD78075B

µ

100-pin

80-pin

µ

PD78054 with timer and enhanced external interface

PD78078

µ

PD78078Y

PD78070A

PD78070AY

µ

ROMless version of the PD78078

µ

PD78078Y with enhanced serial I/O and limited function

PD780018AY

µ

PD780058

µ

PD78058F

PD78054

µ

PD78054 with enhanced serial I/O

PD780058Y

PD78058FY

PD78054Y

µ

EMI-noise reduced version of theµPD78054

µ

80-pin

PD78018F with UART and D/A converter, and enhanced I/O

PD780024A with expanded RAM

80-pin

µ

PD780065

µ

80-pin

PD780034A with timer and enhanced serial I/O

PD780024A with enhanced A/D converter

PD78018F with enhanced serial I/O

PD780078Y

PD780034AY

PD780024AY

µ

64-pin

PD780078

PD780034A

PD780024A

PD78014H

PD78018F

PD78083

µ

EMI-noise reduced version of the PD78018F

µ

Basic subseries for control

PD78018FY

64-pin

µ

On-chip UART, capable of operating at low voltage (1.8 V)

42/44-pin

Inverter control

PD780988

64-pin

On-chip inverter control circuit and UART. EMI-noise reduced.

µ

VFD drive

µ

PD78044F with enhanced I/O and VFD C/D. Display output total: 53

For panel control. On-chip VFD C/D. Display output total: 53

PD78044F with N-ch open-drain I/O. Display output total: 34

Basic subseries for driving VFD. Display output total: 34

100-pin

80-pin

PD780208

PD780232

PD78044H

PD78044F

µ

78K/0

Series

µ

LCD drive

µ

PD780344 with enhanced A/D converter

µ

PD780354Y

PD780344Y

100-pin

120-pin

100-pin

PD780354

PD780344

µ

PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.

µ

PD780338

PD780328

PD780318

µ

PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.

PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.

PD780308Y

PD78064Y

µ

PD78064 with enhanced SIO, and expanded ROM and RAM

EMI-noise reduced version of the PD78064

PD780308

µ

PD78064B

PD78064

Basic subseries for driving LCDs, on-chip UART

µ

Bus interface supported

100-pin

80-pin

µ

PD780948

PD78098B

On-chip CAN controller

µ

PD78054 with IEBus^TMcontroller

80-pin

64-pin

PD780702Y

PD780703Y

PD780833Y

µ

On-chip IEBus controller

On-chip CAN controller

On-chip controller compliant with J1850 (Class 2)

Specialized for CAN controller function

PD780816

µ

Meter control

PD780958

100-pin

80-pin

µ

For industrial meter control

On-chip automobile meter controller/driver

For automobile meter driver. On-chip CAN controller

PD780852

µ

80-pin

PD780828B

µ

Remark VFD (Vacuum Fluorescent Display) is referred to as FIP^TM(Fluorescent Indicator Panel) in some

documents, but the functions of the two are the same.

2

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

The major functional differences among the subseries are listed below.

• Non-Y subseries

VDD

MIN.

Value

Function

ROM

Timer

8-Bit 10-Bit 8-Bit

Serial Interface

I/O

External

Expansion

√

Capacity

Subseries Name

8-Bit 16-Bit Watch WDT A/D A/D D/A

(Bytes)

Control µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch

µPD78078 48 K to 60 K

–

2 ch 3 ch (UART: 1 ch)

88 1.8 V

µPD78070A

–

61 2.7 V

µPD780058 24 K to 60 K 2 ch

µPD78058F 48 K to 60 K

µPD78054 16 K to 60 K

µPD780065 40 K to 48 K

µPD780078 48 K to 60 K

µPD780034A 8 K to 32 K

µPD780024A

3 ch (time-division UART: 1 ch) 68 1.8 V

3 ch (UART: 1 ch)

69 2.7 V

2.0 V

–

4 ch (UART: 1 ch)

3 ch (UART: 2 ch)

3 ch (UART: 1 ch)

60 2.7 V

52 1.8 V

51

2 ch

1 ch

–

8 ch

–

8 ch

µPD78014H

2 ch

53

µPD78018F 8 K to 60 K

µPD78083 8 K to 16 K

–

1 ch (UART: 1 ch)

3 ch (UART: 2 ch)

33

–

Inverter µPD780988 16 K to 60 K 3 ch Note

1 ch

–

8 ch

–

47 4.0 V

√

control

VFD

drive

µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch

2 ch

74 2.7 V

40 4.5 V

68 2.7 V

–

µPD780232 16 K to 24 K 3 ch

–

4 ch

8 ch

µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch

µPD78044F 16 K to 40 K

1 ch

2 ch

LCD

drive

µPD780354 24 K to 32 K 4 ch 1 ch 1 ch 1 ch

µPD780344

–

8 ch

–

8 ch

–

3 ch (UART: 1 ch)

66 1.8 V

–

µPD780338 48 K to 60 K 3 ch 2 ch

µPD780328

10 ch 1 ch 2 ch (UART: 1 ch)

54

62

70

µPD780318

µPD780308 48 K to 60 K 2 ch 1 ch

µPD78064B 32 K

8 ch

–

3 ch (time-division UART: 1 ch) 57 2.0 V

2 ch (UART: 1 ch)

µPD78064 16 K to 32 K

Bus

µPD780948 60 K

2 ch 2 ch 1 ch 1 ch 8 ch

1 ch

–

3 ch (UART: 1 ch)

79 4.0 V

69 2.7 V

√

interface µPD78098B 40 K to 60 K

2 ch

–

supported

µPD780816 32 K to 60 K

2 ch

12 ch

–

2 ch (UART: 1 ch)

46 4.0 V

69 2.2 V

Meter

µPD780958 48 K to 60 K 4 ch 2 ch

–

1 ch

–

control

Dash-

board

control

µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch

µPD780828B 32 K to 60 K

–

3 ch (UART: 1 ch)

56 4.0 V

59

Note 16-bit timer: 2 channels

10-bit timer: 1 channel

Data Sheet U14040EJ4V0DS

3

µPD78F0034A, 78F0034AY

• Y subseries

ROM

Capacity

(Bytes)

VDD

MIN.

Value

Function

Subseries Name

Timer

8-Bit 10-Bit 8-Bit

Serial Interface

I/O

External

Expansion

√

8-Bit 16-Bit Watch WDT A/D A/D D/A

Control µPD78078Y 48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch

µPD78070AY

–

2 ch 3 ch (UART: 1 ch, I²C: 1 ch) 88 1.8 V

–

61 2.7 V

µPD780018AY 48 K to 60 K

µPD780058Y 24 K to 60 K 2 ch

µPD78058FY 48 K to 60 K

µPD78054Y 16 K to 60 K

µPD780078Y 48 K to 60 K

µPD780034AY 8 K to 32 K

µPD780024AY

–

3 ch (I²C: 1 ch)

88

2 ch 3 ch (time-division UART: 1 ch, I²C: 1 ch

3 ch (UART: 1 ch, I²C: 1 ch)

)

68 1.8 V

69 2.7 V

2.0 V

2 ch

1 ch

–

8 ch

–

4 ch (UART: 2 ch, I²C: 1 ch)

52 1.8 V

3 ch (UART: 1 ch, I²C: 1 ch) 51

8 ch

–

µPD78018FY 8 K to 60 K

2 ch (I²C: 1 ch)

53

–

LCD

drive

µPD780354Y 24 K to 32 K 4 ch 1 ch 1 ch 1 ch

µPD780344Y

–

8 ch

4 ch (UART: 1 ch,

I²C: 1 ch)

66 1.8 V

8 ch

–

µPD780308Y 48 K to 60 K 2 ch

µPD78064Y 16 K to 32 K

3 ch (time-division UART: 1 ch, I²C: 1 ch) 57 2.0 V

2 ch (UART: 1 ch, I²C: 1 ch)

Bus

µPD780701Y 60 K

µPD780703Y

3 ch 2 ch 1 ch 1 ch 16 ch

–

4 ch (UART: 1 ch, I²C: 1 ch)

67 3.5 V

interface

supported

µPD780833Y

65 4.5 V

Remark Functions other than the serial interface are common to both the Y and non-Y subseries.

4

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

OVERVIEW OF FUNCTIONS

Part Number

µPD78F0034A

µPD78F0034AY

Item

Note

Internal

memory

Flash memory

32 KB

Note

High-speed RAM

1,024 bytes

64 KB

Memory space

General-purpose registers

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

On-chip minimum instruction execution time cycle variable function

0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation)

When main system

clock selected

When subsystem

clock selected

122 µs (@ 32.768 kHz operation)

Instruction set

I/O ports

• 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

Total:

51

• CMOS input:

• CMOS I/O:

8

39

• N-ch open-drain I/O (5 V withstand voltage): 4

A/D converter

Serial interface

• 10-bit resolution × 8 channels

• Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V

• UART mode:

1 channel

• UART mode:

1 channel

• 3-wire serial I/O mode: 2 channels

• 3-wire serial I/O mode: 1 channel

2

• I C bus mode

(multimaster supporting):1 channel

Timers

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 2 channels

• Watch timer:

1 channel

• Watchdog timer:

Timer outputs

Clock output

3 (8-bit PWM output capable: 2)

• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz

(@ 8.38 MHz operation with main system clock)

• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)

Buzzer output

1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)

Vectored interrupt

sources

Maskable

Internal: 13, external: 5

Internal: 1

Non-maskable

Software

1

Test inputs

Internal: 1, external: 1

VDD = 1.8 to 5.5 V

TA = –40 to +85°C

Supply voltage

Operating ambient temperature

Package

• 64-pin plastic SDIP (19.05 mm (750))

• 64-pin plastic LQFP (10 × 10)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic QFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

Note The capacities of the flash memory and the internal high-speed RAM can be changed with the memory size

switching register (IMS).

Data Sheet U14040EJ4V0DS

5

µPD78F0034A, 78F0034AY

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ..............................................................................................

7

2. BLOCK DIAGRAM .......................................................................................................................... 10

3. PIN FUNCTIONS ............................................................................................................................. 11

3.1 Port Pins ................................................................................................................................................. 11

3.2 Non-Port Pins......................................................................................................................................... 12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.................................................. 14

4. DIFFERENCES BETWEEN µPD78F0034A, 78F0034AY, AND MASK ROM VERSIONS .......... 17

5. MEMORY SIZE SWITCHING REGISTER (IMS)............................................................................ 19

6. FLASH MEMORY PROGRAMMING .............................................................................................. 20

6.1 Selection of Communication Mode..................................................................................................... 20

6.2 Flash Memory Programming Functions............................................................................................. 22

6.3 Connection of Flashpro III ................................................................................................................... 22

7. ELECTRICAL SPECIFICATIONS................................................................................................... 24

8. PACKAGE DRAWINGS .................................................................................................................. 47

9. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 52

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 54

APPENDIX B. RELATED DOCUMENTS............................................................................................. 61

6

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

1. PIN CONFIGURATION (TOP VIEW)

•

64-pin plastic SDIP (19.05 mm (750))

µPD78F0034ACW, 78F0034AYCW

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P67/ASTB

P66/WAIT

2

3

P65/WR

4

P64/RD

5

P75/BUZ

6

P74/PCL

7

P73/TI51/TO51

P72/TI50/TO50

P71/TI01

8

9

P51/A9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

V

SS1

X1

X2

VSS0

VDD0

VPP

P30

P31

XT1

XT2

P32/SDA0^{Note 1}

P33/SCL0^{Note 1}

P34/SI31^{Note 2}

P35/SO31^{Note 2}

P36/SCK31^{Note 2}

P20/SI30

RESET

AV^DD

AVREF

P10/ANI0

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

AVSS

P21/SO30

P22/SCK30

P23/RxD0

P24/TxD0

P25/ASCK0

VDD1

Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034AY Subseries.

2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034A Subseries.

Cautions 1. Connect the V^PPpin directly to VSS0 or VSS1 in normal operation mode.

2. Connect the AVSS pin to VSS0.

Remark When the µPD78F0034A and 78F0034AY are used in application fields that require reduction of the

noise generated from inside the microcontroller, the implementation of noise reduction measures, such

as supplying voltage to V^DD0and VDD1 individually and connecting VSS0 and VSS1 to different ground lines,

is recommended.

Data Sheet U14040EJ4V0DS

7

µPD78F0034A, 78F0034AY

•

64-pin plastic LQFP (10 × 10)

•

64-pin plastic QFP (14 × 14)

µPD78F0034AGB-8EU, 78F0034AYGB-8EU

64-pin plastic LQFP (14 × 14)

µPD78F0034AGC-AB8, 78F0034AYGC-AB8

64-pin plastic TQFP (12 × 12)

µPD78F0034AGC-8BS, 78F0034AYGC-8BS

µPD78F0034AGK-9ET, 78F0034AYGK-9ET

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

V^SS0

1

P71/TI01

P70/TI00/TO0

P03/INTP3/ADTRG

P02/INTP2

P01/INTP1

P00/INTP0

VSS1

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

3

4

5

6

7

8

X1

9

X2

VDD0

10

11

12

13

14

15

16

V^PP

P30

XT1

P31

XT2

P32/SDA0^{Note 1}

P33/SCL0^{Note 1}

P34/SI31^{Note 2}

P35/SO31^{Note 2}

RESET

AVDD

AVREF

P10/ANI0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034AY Subseries.

2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034A Subseries.

Cautions 1. Connect the V^PPpin directly to VSS0 or VSS1 in normal operation mode.

2. Connect the AVSS pin to VSS0.

Remark When the µPD78F0034A and 78F0034AY are used in application fields that require reduction of the

noise generated from inside the microcontroller, the implementation of noise reduction measures, such

as supplying voltage to V^DD0and VDD1 individually and connecting VSS0 and VSS1 to different ground lines,

is recommended.

8

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

A8 to A15:

AD0 to AD7:

ADTRG:

Address bus

Address/data bus

AD trigger input

Analog input

Asynchronous serial clock

Address strobe

Analog power supply

Analog reference voltage

Analog ground

Buzzer clock

External interrupt input

Port 0

P70 to P75:

PCL:

Port 7

Programmable clock

Read strobe

Reset

RD:

ANI0 to ANI7:

ASCK0:

RESET:

RxD0:

Receive data

ASTB:

SCK30, SCK31, SCL0: Serial clock

AV^DD:

SDA0:

Serial data

Serial input

Serial output

AV^REF:

SI30, SI31:

SO30, SO31:

AV^SS:

BUZ:

TI00, TI01, TI50, TI51: Timer input

INTP0 to INTP3:

P00 to P03:

P10 to P17:

P20 to P25:

P30 to P36:

P40 to P47:

P50 to P57:

P64 to P67:

TO0, TO50, TO51:

TxD0:

Timer output

Transmit data

Port 1

V^DD0, VDD1:

V^PP:

Power supply

Port 2

Programming power supply

Ground

Port 3

V^SS0, VSS1:

WAIT:

Port 4

Wait

Port 5

WR:

Write strobe

Port 6

X1, X2:

Crystal (main system clock)

Crystal (subsystem clock)

XT1, XT2:

Data Sheet U14040EJ4V0DS

9

µPD78F0034A, 78F0034AY

2. BLOCK DIAGRAM

TI00/TO0/P70

16-bit timer/

event counter

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

P00 to P03

P10 to P17

P20 to P25

P30 to P36

P40 to P47

P50 to P57

P64 to P67

P70 to P75

TI01/P71

8-bit timer/

event counter 50

TI50/TO50/P72

8-bit timer/

event counter 51

TI51/TO51/P73

Watchdog timer

Watch timer

Flash

memory

(32 KB)

78K/0

CPU core

SI30/P20

SO30/P21

SCK30/P22

Serial

interface 30

SI31/P34

SO31/P35

SCK31/P36

Serial

interface 31^{Note 1}

RAM

(1,024

bytes)

RxD0/P23

TxD0/P24

ASCK0/P25

AD0/P40 to

AD7/P47

A8/P50 to

A15/P57

UART0

SDA0/P32

SCL0/P33

I²C bus^{Note 2}

External access

RD/P64

WR/P65

ANI0/P10 to

ANI7/P17

AV^DD

WAIT/P66

ASTB/P67

A/D converter

AVSS

AVREF

RESET

X1

INTP0/P00 to

INTP3/P03

System control

X2

Interrupt control

Buzzer output

XT1

XT2

BUZ/P75

PCL/P74

Clock output

control

V

DD0

V

DD1

V

SS0

V

SS1

V

PP

Notes 1. Incorporated only in the µPD78F0034A

2. Incorporated only in the µPD78F0034AY

10

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

P00

I/O

Port 0

INTP0

4-bit I/O port.

P01

INTP1

Input/output can be specified in 1-bit units.

P02

INTP2

An on-chip pull-up resistor can be specified by software.

P03

INTP3/ADTRG

ANI0 to ANI7

P10 to P17

Input Port 1

8-bit input-only port.

Port 2

Input

P20

I/O

SI30

6-bit I/O port.

P21

SO30

SCK30

RxD0

TxD0

ASCK0

–

Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by software.

P22

P23

P24

P25

P30

I/O

Port 3

N-ch open-drain I/O port.

Input

7-bit I/O port.

LEDs can be driven directly.

P31

Input/output can be specified

in 1-bit units.

Note 1

P32

SDA0

Note 1

P33

SCL0

Note 2

P34

An on-chip pull-up resistor can be

specified by software.

SI31

Note 2

P35

SO31

Note 2

P36

SCK31

P40 to P47

I/O

Port 4

Input

AD0 to AD7

8-bit I/O port.

Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by software.

Interrupt request flag KRIF is set to 1 by falling edge detection.

P50 to P57

Port 5

A8 to A15

8-bit I/O port.

LEDs can be driven directly.

Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by software.

P64

P65

P66

P67

Port 6

RD

4-bit I/O port.

WR

Input/output can be specified in 1-bit units.

An on-chip pull-up resistor can be specified by software.

WAIT

ASTB

Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034AY Subseries.

2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034A Subseries.

Data Sheet U14040EJ4V0DS

11

µPD78F0034A, 78F0034AY

3.1 Port Pins (2/2)

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

P70

P71

P72

P73

P74

P75

I/O

Port 7

TI00/TO0

TI01

6-bit I/O port.

Input/output can be specified in 1-bit units.

TI50/TO50

TI51/TO51

PCL

An on-chip pull-up resistor can be specified by software.

BUZ

3.2 Non-Port Pins (1/2)

Pin Name

I/O

Function

After Reset

Input

Alternate

Function

INTP0

INTP1

INTP2

INTP3

SI30

Input External interrupt request input by which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified.

P00

P01

P02

P03/ADTRG

P20

Input Serial interface serial data input.

Input

Note 1

SI31

P34

Note 2

SDA0

I/O

Serial interface serial data input/output

Input

P32

SO30

Output Serial interface serial data output.

P21

Note 1

SO31

P35

SCK30

I/O

Serial interface serial clock input/output.

Input

P22

Note 1

SCK31

P36

Note 2

SCL0

P33

RxD0

TxD0

ASCK0

TI00

Input Serial data input for asynchronous serial interface.

Output Serial data output for asynchronous serial interface.

Input Serial clock input for asynchronous serial interface.

Input

P23

P24

P25

Input External count clock input to 16-bit timer/event counter 0.

Capture trigger signal input to capture register 01 (CR01) of 16-bit timer/

event counter 0.

P70/TO0

TI01

Capture trigger signal input to capture register 00 (CR00) of 16-bit timer/

event counter 0.

P71

TI50

External count clock input to 8-bit timer/event counter 50.

External count clock input to 8-bit timer/event counter 51.

Output 16-bit timer/event counter 0 output.

P72/TO50

P73/TO51

P70/TI00

P72/TI50

P73/TI51

P74

TI51

TO0

Input

TO50

TO51

PCL

8-bit timer/event counter 50 output (shared with 8-bit PWM output).

8-bit timer/event counter 51 output (shared with 8-bit PWM output).

Output Clock output (for trimming of main system clock and subsystem clock).

Output Buzzer output.

Input

BUZ

P75

AD0 to AD7

I/O

Lower address/data bus for extending memory externally.

P40 to P47

Notes 1. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034A Subseries.

2. SDA0 and SCL0 are incorporated only in the µPD78F0034AY Subseries.

12

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

3.2 Non-Port Pins (2/2)

Pin Name

I/O

Function

After Reset

Alternate

Function

A8 to A15

RD

Output Higher address bus for extending memory externally.

Output Strobe signal output for read operation of external memory.

Strobe signal output for write operation of external memory.

Input Inserting wait for accessing external memory.

Input

P50 to P57

P64

WR

P65

WAIT

ASTB

Input

P66

Output Strobe output which externally latches address information output to

ports 4 and 5 to access external memory.

P67

ANI0 to ANI7 Input A/D converter analog input.

Input

–

P10 to P17

ADTRG

AVREF

AVDD

Input A/D converter trigger signal input.

P03/INTP3

Input A/D converter reference voltage input.

–

A/D converter analog power supply.

Set the voltage equal to VDD0 or VDD1.

–

AVSS

–

A/D converter ground potential.

–

Set the voltage equal to VSS0 or VSS1.

RESET

X1

Input System reset input.

–

Input Connecting crystal resonator for main system clock oscillation.

X2

–

XT1

XT2

VDD0

VSS0

VDD1

VSS1

VPP

Input Connecting crystal resonator for subsystem clock oscillation.

–

Positive power supply voltage for ports.

Ground potential of ports.

Positive power supply (except ports).

Ground potential (except ports).

Applying high-voltage for program write/verify. Connect directly to VSS0

or VSS1 in normal operation mode.

Data Sheet U14040EJ4V0DS

13

µPD78F0034A, 78F0034AY

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output configuration of each type, refer to Figure 3-1 .

Table 3-1. Types of Pin I/O Circuits (1/2)

Pin Name

P00/INTP0

I/O Circuit Type

8-C

I/O

Recommended Connection of Unused Pins

Input: Independently connect to VSS0 via a resistor.

Output: Leave open.

P01/INTP1

P02/INTP2

P03/INTP3/ADTRG

P10/ANI0 to P17/ANI7

P20/SI30

25

Input

I/O

Directly connect to VDD0 or VSS0.

8-C

5-H

8-C

Input: Independently connect to VDD0 or VSS0 via a

resistor.

P21/SO30

Output: Leave open.

P22/SCK30

P23/RxD0

P24/TxD0

5-H

8-C

P25/ASCK0

P30, P31

13-P

13-R

I/O

Input: Independently connect to VDD0 via a resistor.

Output: Leave open.

Note 1

P32/SDA0

Note 1

P33/SCL0

Note 2

P34/SI31

8-C

5-H

8-C

5-H

Input: Independently connect to VDD0 or VSS0 via a

resistor.

Note 2

P35/SO31

Output: Leave open.

Note 2

P36/SCK31

P40/AD0 to P47/AD7

I/O

Input: Independently connect to VDD0 via a resistor.

Output: Leave open.

P50/A8 to P57/A15

P64/RD

5-H

I/O

Input: Independently connect to VDD0 or VSS0 via a

resistor.

Output: Leave open.

P65/WR

P66/WAIT

P67/ASTB

P70/TI00/TO0

P71/TI01

8-C

5-H

P72/TI50/TO50

P73/TI51/TO51

P74/PCL

P75/BUZ

Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034AY Subseries.

2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034A Subseries.

14

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Table 3-1. Types of Pin I/O Circuits (2/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

–

RESET

XT1

2

Input

16

Directly connect to VDD0.

Leave open.

XT2

–

AVDD

AVREF

AVSS

VPP

–

Directly connect to VDD0 or VDD1.

Directly connect to VSS0 or VSS1.

Data Sheet U14040EJ4V0DS

15

µPD78F0034A, 78F0034AY

Figure 3-1. Pin I/O Circuits

TYPE 2

TYPE 13-R

IN/OUT

Data

Output disable

N-ch

IN

VSS0

Schmitt-triggered input with hysteresis characteristics

TYPE 5-H

TYPE 16

VDD0

Feedback

cut-off

Pullup

enable

P-ch

VDD0

Data

P-ch

IN/OUT

Output

disable

N-ch

VSS0

XT1

XT2

Input

enable

TYPE 25

TYPE 8-C

VDD0

P-ch

N-ch

Pullup

enable

Comparator

P-ch

+

–

V

DD0

VSS0

Data

IN

P-ch

V

REF (threshold voltage)

IN/OUT

Input

enable

Output

disable

N-ch

VSS0

TYPE 13-P

IN/OUT

Data

Output disable

N-ch

V

SS0

Input

enable

16

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

4. DIFFERENCES BETWEEN µPD78F0034A, 78F0034AY, AND MASK ROM VERSIONS

The µPD78F0034A and 78F0034AY are products provided with a flash memory which enables writing, erasing,

and rewriting of programs with device mounted on the target system.

The functions of the µPD78F0034A (except the functions specified for flash memory) can be made the same as

those of the mask ROM versions by setting the memory size switching register (IMS).

Tables 4-1 and 4-2 show the differences between the µPD78F0034A, 78F0034AY and the mask ROM versions.

Table 4-1. Differences Between µPD78F0034A and Mask ROM Versions

Item

µPD78F0034A

Mask ROM Versions

Note

µPD780034A Subseries

µPD780024A Subseries

Internal ROM structure

Internal ROM capacity

Flash memory

Mask ROM

32 KB

µPD780031A: 8 KB

µPD780032A: 16 KB

µPD780033A: 24 KB

µPD780034A: 32 KB

µPD780021A: 8 KB

µPD780022A: 16 KB

µPD780023A: 24 KB

µPD780024A: 32 KB

Internal high-speed RAM capacity

1,024 bytes

µPD780031A: 512 bytes

µPD780032A: 512 bytes

µPD780021A: 512 bytes

µPD780022A: 512 bytes

µPD780033A: 1,024 bytes µPD780023A: 1,024 bytes

µPD780034A: 1,024 bytes µPD780024A: 1,024 bytes

Minimum instruction execution time

Minimum instruction execution time variable function incorporated

When main system clock is selected 0.24 µs/0.48 µs/0.95 µs/

1.91 µs/3.81 µs

0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs

(operation at 12 MHz, VDD = 4.5 to 5.5 V)

(operation at 8.38 MHz,

VDD = 4.0 to 5.5 V)

When subsystem clock is selected 122 µs (32.768 kHz)

Clock output

• 65.5 kHz, 131 kHz,

262 kHz, 524 kHz,

• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz,

1.25 MHz, 3 MHz, 6 MHz, 12 MHz

(operation at 12 MHz with main system clock)

• 32.768 kHz

1.05 MHz, 2.10 MHz,

4.19 MHz, 8.38 MHz

(operation at 8.38 MHz

with main system clock)

• 32.768 kHz

(operation at 32.768 kHz with subsystem clock)

(operation at 32.768 kHz

with subsystem clock)

Buzzer output

1.02 kHz, 2.5 kHz,

1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz

4.10 kHz, 8.19 kHz

(operation at 12 MHz with main system clock)

(operation at 8.38 MHz

with main system clock)

A/D converter resolution

10 bits

8 bits

Mask option specification of on-chip

pull-up resistor for pins P30 to P33

Not available

Available

IC pin

Not provided

Provided

VPP pin

Not provided

Electrical specifications,

Refer to the data sheet of individual products.

recommended soldering conditions

Note The µPD78F0034A can be used as the flash memory version of the µPD780024A Subseries.

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then mass

producing it with the mask ROM version, be sure to conduct sufficient evaluations on the

commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.

Data Sheet U14040EJ4V0DS

17

µPD78F0034A, 78F0034AY

Table 4-2. Differences Between µPD78F0034AY and Mask ROM Versions

Item

µPD78F0034AY

Mask ROM Versions

µPD780034AY Subseries µPD780024AY Subseries

Mask ROM

Note

Internal ROM structure

Internal ROM capacity

Flash memory

32 KB

µPD780031AY: 8 KB

µPD780032AY: 16 KB

µPD780033AY: 24 KB

µPD780034AY: 32 KB

µPD780021AY: 8 KB

µPD780022AY: 16 KB

µPD780023AY: 24 KB

µPD780024AY: 32 KB

Internal high-speed RAM capacity

1,024 bytes

µPD780031AY: 512 bytes

µPD780032AY: 512 bytes

µPD780021AY: 512 bytes

µPD780022AY: 512 bytes

µPD780033AY: 1,024 bytes µPD780023AY: 1,024 bytes

µPD780034AY: 1,024 bytes µPD780024AY: 1,024 bytes

Minimum instruction execution time

Minimum instruction execution time variable function incorporated

When main system clock is selected 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs

(operation at 8.38 MHz, VDD = 4.0 to 5.5 V)

When subsystem clock is selected 122 µs (32.768 kHz)

Clock output

• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz

(operation at 8.38 MHz with main system clock)

• 32.768 kHz

(operation at 32.768 kHz with subsystem clock)

Buzzer output

1.02 kHz, 2.5 kHz, 4.10 kHz, 8.19 kHz

(operation at 8.38 MHz with main system clock)

A/D converter resolution

10 bits

8 bits

Mask option specification of on-chip

pull-up resistor for pins P30 and P31

Not available

Available

IC pin

Not provided

Provided

VPP pin

Not provided

Electrical specifications,

Refer to the data sheet of individual products.

recommended soldering conditions

Note The µPD78F0034AY can be used as the flash memory version of the µPD780024AY Subseries.

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then mass

producing it with the mask ROM version, be sure to conduct sufficient evaluations on the

commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.

18

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

5. MEMORY SIZE SWITCHING REGISTER (IMS)

IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.

By setting memory size switching register (IMS), the internal memory of the µPD78F0034A and 78F0034AY can be

mapped identically to that of a mask ROM version.

IMS is set with an 8-bit memory manipulation instruction.

RESET input sets IMS to CFH.

Caution The initial value of IMS is setting disabled (CFH). Be sure to set C8H or the value of the target

mask ROM version at the moment of initial setting.

Figure 5-1. Format of Memory Size Switching Register

7

6

5

4

0

3

2

1

0

Address

FFF0H

After reset

CFH

R/W

IMS RAM2 RAM1 RAM0

ROM3 ROM2 ROM1 ROM0

ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity

0

1

0

1

0

1

0

1

0

8 KB

16 KB

24 KB

32 KB

Other than above

Setting prohibited

RAM2 RAM1 RAM0 Selection of Internal High-Speed RAM Capacity

0

1

0

512 bytes

1,024 bytes

Other than above

Setting prohibited

Table 5-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions.

Table 5-1. Set Value of Memory Size Switching Register

Target Mask ROM Versions

µPD780031A, 780031AY

µPD780032A, 780032AY

µPD780033A, 780033AY

µPD780034A, 780034AY

IMS Set Value

42H

44H

C6H

C8H

Data Sheet U14040EJ4V0DS

19

µPD78F0034A, 78F0034AY

6. FLASH MEMORY PROGRAMMING

Writing to flash memory can be performed without removing the memory from the target system (on board

programming). Writing is performed with the dedicated flash programmer (Flashpro III (part No.: FL-PR3 and PG-

FP3)) connected to the host machine and the target system.

Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro III.

Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

6.1 Selection of Communication Mode

Writing to a flash memory is performed using Flashpro III in a serial communication. Select one of the

communication modes in Tables 6-1 and 6-2. The selection of the communication mode is made by using the format

shown in Figure 6-1. Each communication mode is selected by the number of V^PPpulses shown in Tables 6-1 and

6-2.

Table 6-1. List of Communication Mode (µPD78F0034A)

Communication Mode

3-wire serial I/O

Channels

Pin Used

VPP Pulses

2

SI30/P20

0

1

SO30/P21

SCK30/P22

SI31/P34

SO31/P35

SCK31/P36

UART

1

RxD0/P23

TxD0/P24

8

Pseudo 3-wire serial I/O

P72/TI50/TO50

(serial clock input)

P71/TI01

12

(serial data output)

P70/TI00/TO0

(serial data input)

Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 6-1.

20

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Table 6-2. List of Communication Mode (µPD78F0034AY)

Communication Mode

3-wire serial I/O

Channels

Pin Used

VPP Pulses

1

SI30/P20

0

SO30/P21

SCK30/P22

2

I C bus

1

SDA0/P32

SCL0/P33

4

UART

RxD0/P23

TxD0/P24

8

Pseudo 3-wire serial I/O

P72/TI50/TO50

(serial clock input)

P71/TI01

12

(serial data output)

P70/TI00/TO0

(serial data input)

Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 6-2.

Figure 6-1. Format of Communication Mode Selection

V

PP pulses

10 V

V

DD

VPP

1

2

n

V

SS

V

DD

RESET

Flash write mode

V

SS

Data Sheet U14040EJ4V0DS

21

µPD78F0034A, 78F0034AY

6.2 Flash Memory Programming Functions

Operations such as writing to flash memory are performed by various command/data transmission and reception

operations according to the selected communication mode. Table 6-3 shows major functions of flash memory

programming.

Table 6-3. Major Functions of Flash Memory Programming

Function

Description

Used to stop write operation and detect transmission cycle.

Compares the entire memory contents with the input data.

Erases the entire memory contents.

Reset

Batch verify

Batch erase

Batch blank check

High-speed write

Checks the deletion status of the entire memory.

Performs write to the flash memory based on the write start address and the number of data

to be written (number of bytes).

Continuous write

Status

Performs continuous write based on the information input with high-speed write operation.

Used to confirm the current operating mode and operation end.

Oscillation frequency setting Sets the frequency of the resonator.

Erase time setting

Baud rate setting

Sets the memory erase time.

Sets the communication rate for UART mode

2

I C mode setting

Sets standard/high-speed mode for I C bus mode

Silicon signature read

Outputs the device name and memory capacity, and device block information.

6.3 Connection of Flashpro III

The connection of Flashpro III and the µPD78F0034A or 78F0034AY differs according to the communication mode

(3-wire serial I/O, UART, pseudo 3-wire serial I/O, and I²C bus). The connection for each communication mode is

shown in Figures 6-2 to 6-5, respectively.

Figure 6-2. Connection of Flashpro III in 3-Wire Serial I/O Mode

µ

PD78F0034A,

µ

PD78F0034AY

Flashpro III

VPP

VDD

V

PP

V

DD

RESET

SCK

RESET

SCK3n

SI3n

SO

SI

SO3n

GND

V

SS

Remark µPD78F0034A: n = 0, 1

µPD78F0034AY: n = 0

22

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Figure 6-3. Connection of Flashpro III for UART Mode

µ

PD78F0034A,

µ

Flashpro III

PD78F0034AY

V

PP

VPP

VDD

V

DD

RESET

SO

RESET

RxD0

SI

TxD0

GND

V

SS

Figure 6-4. Connection of Flashpro III for Pseudo 3-Wire Serial I/O Mode

µ

PD78F0034A,

µ

PD78F0034AY

Flashpro III

V

PP

VPP

VDD

V

DD

RESET

SCK

SO

P72

(serial clock input)

P70

(serial data input)

SI

P71

(

serial data output)

GND

V

SS

Figure 6-5. Connection of Flashpro III for I²C Bus Mode (µPD78F0034AY only)

Flashpro III

µ

PD78F0034AY

VPP

VDD

V

PP

V

DD

RESET

SCL0

SDA0

SO

SI

GND

V

SS

Data Sheet U14040EJ4V0DS

23

µPD78F0034A, 78F0034AY

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Symbol

VDD

Conditions

Ratings

–0.3 to +6.5

Unit

V

Supply voltage

VPP

–0.3 to +10.5

V

Note

AVDD

AVREF

AVSS

V^I1

–0.3 to VDD + 0.3

–0.3 to +0.3

V

Note

V

Note

Input voltage

P00 to P03, P10 to P17, P20 to P25, P34 to P36,

P40 to P47, P50 to P57, P64 to P67, P70 to P75,

X1, X2, XT1, XT2, RESET

–0.3 to VDD + 0.3

V

VI2

VO

P30 to P33

N-ch open drain

–0.3 to +6.5

V

Output voltage

–0.3 to VDD + 0.3

Note

Analog input voltage V^AN

P10 to P17

Per pin

Analog input pin

AVSS –0.3 to AVREF + 0.3

Note

and –0.3 to VDD + 0.3

Output current, high IOH

–10

–15

mA

Total for P00 to P03, P40 to P47, P50 to P57,

P64 to P67, P70 to P75

Total for P20 to P25, P30 to P36

–15

20

mA

Output current, low

IOL

Per pin for P00 to P03, P20 to P25, P34 to P36,

P40 to P47, P64 to P67, P70 to P75

Per pin for P30 to P33, P50 to P57

30

50

mA

Total for P00 to P03, P40 to P47, P64 to P67,

P70 to P75

Total for P20 to P25

20

mA

°C

Total for P30 to P36

100

Total for P50 to P57

100

Operating ambient

temperature

TA

During normal operation

During flash memory programming

–40 to +85

+10 to +40

–40 to +125

°C

Storage

Tstg

°C

temperature

Note 6.5 V or below

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions

that ensure that the absolute maximum ratings are not exceeded.

24

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Capacitance (TA = 25°C, VDD = VSS = 0 V)

Parameter Symbol

Input C^IN

Conditions

MIN.

TYP.

MAX.

15

Unit

pF

f = 1 MHz

Unmeasured pins returned to 0 V.

capacitance

I/O

C^IO

f = 1 MHz

P00 to P03, P20 to P25,

15

pF

capacitance

Unmeasured pins

returned to 0 V.

P34 to P36, P40 to P47,

P50 to P57, P64 to P67,

P70 to P75,

P30 to P33

20

pF

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Main System Clock Oscillator Characteristics (T^A= –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator

Recommended Circuit

Parameter

Conditions

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

MIN.

1.0

TYP. MAX.

Unit

Ceramic

8.38

5.0

4

MHz

VPP X2

X1

Oscillation

resonator

Note 1

R1

frequency (fX)

Oscillation

1.0

C2

C1

ms

MHz

ms

After VDD reaches oscil-

lation voltage range MIN.

Note 2

stabilization time

Crystal

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

1.0

8.38

5.0

VPP X2

X1

Oscillation

resonator

Note 1

frequency (fX)

C2

C1

10

Oscillation

Note 2

stabilization time

30

External

clock

1.0

50

8.38

5.0

MHz

ns

X1 input

X2

X1

Note 1

frequency (fX)

500

X1 input high-/low-level

width (tXH, tXL)

µ

PD74HCU04

85

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor to the same potential as V^SS1.

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the system is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Data Sheet U14040EJ4V0DS

25

µPD78F0034A, 78F0034AY

Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

32

TYP. MAX.

Unit

kHz

Crystal

32.768

35

V

PP

XT2 XT1

R2

Oscillation

resonator

Note 1

frequency (fXT)

Oscillation

C4

C3

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

1.2

2

s

Note 2

stabilization time

10

External

clock

32

5

38.5

kHz

µs

X1 input

XT2

XT1

Note 1

frequency (fXT)

15

X1 input high-/low-level

width (tXTH, tXTL)

µPD74HCU04

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after V^DDreaches oscillator voltage MIN.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor to the same potential as V^SS1.

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

26

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Recommended Oscillator Constant

Main System Clock: Ceramic Resonator (T^A= –40 to +85°C)

Manufacturer

Part Number

Frequency

(MHz)

1.00

Recommended Circuit Constant

Oscillation Voltage Range

C1 (pF)

100

C2 (pF)

100

R1 (kΩ)

MIN. (V)

1.9

1.8

2.7

3.0

4.5

1.8

4.0

MAX. (V)

5.5

Murata Mg. Co., Ltd. CSBFB1M00J58

CSBLA1M00J58

2.2

0

1.00

100

CSTCC2M00G56

CSTLS2M00G56

CSTCC3M58G53

CSTLS3M58G53

CSTCR4M00G53

CSTLS4M00G53

CSTCR4M19G53

CSTLS4M19G53

CSTCR4M91G53

CSTLS4M91G53

CSTCR5M00G53

CSTLS5M00G53

CSTCE8M00G52

CSTLS8M00G53

CSTLS8M00G53093

CSTCE8M38G52

CSTLS8M38G53

CSTLS8M38G53093

CSTCE10M0G52

CSTLS10M0G53

CSTLS10M0G53093

CSTCE12M0G52

CSTLA12M0T55

2.00

On chip

On-chip

On chip

On-chip

2.00

0

3.58

0

3.58

0

4.00

0

4.00

0

4.19

0

4.19

0

4.91

0

4.91

0

5.00

0

5.00

0

8.00

0

8.00

0

8.00

0

8.38

0

8.38

0

8.38

0

10.00

12.00

3.58

0

CSTLA12M0T55093

0

TDK

CCR3.58MC3

CCR4.19MC3

CCR5.0MC3

CCR8.0MC5

CCR8.38MC5

0

4.19

0

5.00

0

8.00

0

8.38

0

Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.

Oscillationfrequencyprecisionisnotguaranteed. Forapplicationsrequiringoscillationfrequency

precision, the oscillation frequency must be adjusted on the implementation circuit. For details

please contact directly the manufacturer of the resonator you will use.

Data Sheet U14040EJ4V0DS

27

µPD78F0034A, 78F0034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

–1

Unit

mA

Output current,

high

IOH

Per pin

All pins

–15

10

Output current,

low

IOL

Per pin for P00 to P03, P20 to P25, P34 to P36,

P40 to P47, P64 to P67, P70 to P75

Per pin for P30 to P33, P50 to P57

Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75

Total for P20 to P25

15

20

mA

V

10

Total for P30 to P36

70

Total for P50 to P57

70

Input voltage,

high

VIH1

P10 to P17, P21, P24,

P35, P40 to P47,

P50 to P57, P64 to P67,

P74, P75

VDD = 2.7 to 5.5 V

0.7VDD

0.8VDD

VDD

VDD = 1.8 to 5.5 V

VDD = 2.7 to 5.5 V

VDD

V

V^IH2

P00 to P03, P20, P22,

P23, P25, P34, P36,

P70 to P73, RESET

0.8VDD

VDD

V

VDD = 1.8 to 5.5 V

VDD = 2.7 to 5.5 V

0.85VDD

VIH3

VIH4

VIH5

VIL1

P30 to P33

0.7VDD

0.8VDD

VDD – 0.5

VDD – 0.2

0.8VDD

0.9VDD

0

5.5

V

(N-ch open-drain)

X1, X2

VDD = 2.7 to 5.5 V

VDD = 1.8 to 5.5 V

VDD = 4.0 to 5.5 V

VDD

XT1, XT2

VDD

Input voltage,

low

P10 to P17, P21, P24,

P35, P40 to P47,

P50 to P57, P64 to P67,

P74, P75

VDD = 2.7 to 5.5 V

VDD = 1.8 to 5.5 V

0.3VDD

0

0.2VDD

V

VIL2

VIL3

P00 to P03, P20, P22,

P23, P25, P34, P36,

P70 to P73, RESET

VDD = 2.7 to 5.5 V

VDD = 1.8 to 5.5 V

0

0.2VDD

V

0.15VDD

P30 to P33

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7

VDD = 2.7 to 5.5 V

VDD = 1.8 to 5.5 V

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

0

0.3VDD

0.2VDD

0.1VDD

0.4

V

0

VIL4

X1, X2

0

0.2

VIL5

XT1, XT2

0

0.2VDD

0.1VDD

VDD

0

Output voltage,

high

VOH1

VOL1

VDD = 4.0 to 5.5 V, IOH = –1 mA

IOH = –100 µA

VDD – 1.0

VDD – 0.5

VDD

Output voltage,

low

P30 to P33

P50 to P57

VDD = 4.0 to 5.5 V, IOL = 15 mA

2.0

0.4

2.0

P00 to P03, P20 to P25,

P34 to P36, P40 to P47,

P64 to P67, P70 to P75

VDD = 4.0 to 5.5 V, IOL = 1.6 mA

0.4

VOL2

IOL = 400 µA

0.5

V

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

28

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

I^LIH1

Conditions

MIN.

TYP.

MAX.

3

Unit

Input leakage

current, high

VIN = VDD

P00 to P03, P10 to P17, P20 to P25,

P34 to P36, P40 to P47, P50 to P57,

P64 to P67, P70 to P75,

RESET

µA

ILIH2

ILIH3

I^LIL1

X1, X2, XT1, XT2

P30 to P33

20

3

µA

VIN = 5.5 V

VIN = 0 V

Input leakage

current, low

P00 to P03, P10 to P17, P20 to P25,

P34 to P36, P40 to P47, P50 to P57,

P64 to P67, P70 to P75,

RESET

–3

ILIL2

ILIL3

I^LOH

X1, X2, XT1, XT2

P30 to P33

–20

–3

3

µA

Output leakage

current, high

VOUT = VDD

VOUT = 0 V

VIN = 0 V,

Output leakage

current, low

ILOL

–3

µA

kΩ

Software pull-

up resistor

R

15

30

90

P00 to P03, P20 to P25, P34 to P36, P40 to P47,

P50 to P57, P64 to P67, P70 to P75

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14040EJ4V0DS

29

µPD78F0034A, 78F0034AY

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

Note 2

Supply

IDD1

8.38 MHz crystal

VDD = 5.0 V 10%

VDD = 3.0 V 10%

VDD = 2.0 V 10%

VDD = 5.0 V 10%

VDD = 3.0 V 10%

VDD = 2.0 V 10%

A/D converter stopped

10.5

11.5

4.5

5.5

1

21

23

9

mA

µA

Note 1

current

oscillation operating mode

A/D converter operating

A/D converter stopped

Note 2

Note 3

Note 2

Note 3

5.00 MHz crystal

oscillation operation mode

A/D converter operating

A/D converter stopped

11

2

A/D converter operating

Peripheral functions stopped

Peripheral functions operating

Peripheral functions stopped

Peripheral functions operating

Peripheral functions stopped

Peripheral functions operating

2

6

IDD2

8.38 MHz crystal

1.2

2.4

5

oscillation HALT mode

5.00 MHz crystal

0.4

0.2

0.8

1.7

0.4

1.1

230

190

150

60

18

10

30

10

oscillation HALT mode

Note 4

Note 2

IDD3

IDD4

IDD5

32.768 kHz crystal oscillation operating mode

VDD = 5.0 V 10%

115

95

Note 2

VDD = 3.0 V 10%

µA

Note 3

VDD = 2.0 V 10%

75

µA

Note 4

Note 2

32.768 kHz crystal oscillation HALT mode

VDD = 5.0 V 10%

30

µA

Note 2

VDD = 3.0 V 10%

6

µA

Note 3

VDD = 2.0 V 10%

2

µA

Note 2

XT1 = VDD, STOP mode

VDD = 5.0 V 10%

0.1

0.05

µA

When feed-back resistor not used

Note 2

VDD = 3.0 V 10%

µA

Note 3

VDD = 2.0 V 10%

µA

Notes 1. Refers to the total current flowing through the internal power supply (VDD0 and VDD1). Includes peripheral

operating current (however, current flowing through the pull-up resistors of ports and the AV^REFpin is

not included).

2. When the processor clock control register (PCC) is set to 00H.

3. When PCC is set to 02H.

4. When the main system clock is stopped.

30

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

AC Characteristics

(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter

Cycle time

Symbol

Conditions

MIN.

0.24

0.4

TYP.

122

MAX.

16

Unit

µs

TCY

Operating on main 4.0 ≤ VDD ≤ 5.5 V

(Min. instruction

execution time)

system clock

2.7 V ≤ VDD < 4.0 V

16

µs

1.8 V ≤ VDD < 2.7 V

Operating on subsystem clock

4.0 V ≤ VDD ≤ 5.5 V

1.6

16

µs

Note 1

103.9

125

µs

TI00, TI01 input

high-/low-level width

tTIH0, tTIL0

2/fsam + 0.1^{Note 2}

µs

2.7 V ≤ VDD < 4.0 V

2/fsam + 0.2^{Note 2}

µs

1.8 V ≤ VDD < 2.7 V

2/fsam + 0.5^{Note 2}

µs

TI50, TI51 input

frequency

fTI5

VDD = 2.7 to 5.5 V

0

4

MHz

kHz

ns

VDD = 1.8 to 5.5 V

275

TI50, TI51 input

high-/low-level

width

t^TIH5, tTIL5

VDD = 2.7 to 5.5 V

100

VDD = 1.8 to 5.5 V

1.8

1

µs

Interrupt request tINTH, tINTL INTP0 to INTP3, P40 to P47 VDD = 2.7 to 5.5 V

input high-/low-

VDD = 1.8 to 5.5 V

2

µs

level width

RESET

low-level width

tRSL

VDD = 2.7 to 5.5 V

VDD = 1.8 to 5.5 V

10

20

µs

Notes 1. Value when using an external clock. When using a crystal resonator, the value becomes 114 µs (MIN.).

2. Selection of f^sam= fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register

0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes f^sam=

fX/8.

Data Sheet U14040EJ4V0DS

31

µPD78F0034A, 78F0034AY

TCY vs. VDD (main system clock)

16.0

10.0

Operation

guaranteed

range

µ

5.0

2.0

1.6

1.0

0.8

0.4

0.24

0.1

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

1.8

2.7

Supply voltage V^DD[V]

32

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)

(1/3)

Parameter

ASTB high-level width

Address setup time

Symbol

tASTH

tADS

Conditions

MIN.

0.3tCY

20

MAX.

Unit

ns

Address hold time

tADH

6

Input time from address to data

tADD1

tADD2

tRDAD

tRDD1

tRDD2

tRDH

(2 + 2n)tCY – 54

(3 + 2n)tCY – 60

100

Output time from RD↓ to address

Input time from RD↓ to data

0

(2 + 2n)tCY – 87

(3 + 2n)tCY – 93

Read data hold time

RD low-level width

0

tRDL1

tRDL2

tRDWT1

tRDWT2

tWRWT

tWTL

(1.5 + 2n)tCY – 33

(2.5 + 2n)tCY – 33

Input time from RD↓ to WAIT↓

tCY – 43

Input time from WR↓ to WAIT↓

WAIT low-level width

tCY – 25

(0.5 + n)tCY + 10

(2 + 2n)tCY

Write data setup time

tWDS

60

Write data hold time

tWDH

6

(1.5 + 2n)tCY – 15

6

WR low-level width

tWRL1

tASTRD

tASTWR

tRDAST

Delay time from ASTB↓ to RD↓

Delay time from ASTB↓ to WR↓

2tCY – 15

0.8tCY – 15

Delay time from RD↑ to ASTB↑ in

1.2tCY

external fetch

Hold time from RD↑ to address in

t^RDADH

0.8tCY – 15

1.2tCY + 30

ns

external fetch

Write data output time from RD↑

Write data output time from WR↓

Hold time from WR↑ to address

Delay time from WAIT↑ to RD↑

Delay time from WAIT↑ to WR↑

tRDWD

tWRWD

tWRADH

tWTRD

40

10

ns

60

0.8tCY – 15

0.8tCY

1.2tCY + 30

2.5tCY + 25

tWTWR

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

3. C^L= 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB

pins.)

Data Sheet U14040EJ4V0DS

33

µPD78F0034A, 78F0034AY

(2) Read/write operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)

(2/3)

Parameter

ASTB high-level width

Address setup time

Symbol

tASTH

tADS

Conditions

MIN.

0.3tCY

30

MAX.

Unit

ns

Address hold time

tADH

10

Input time from address to data

tADD1

tADD2

tRDAD

tRDD1

tRDD2

tRDH

(2 + 2n)tCY – 108

(3 + 2n)tCY – 120

200

Output time from RD↓ to address

Input time from RD↓ to data

0

(2 + 2n)tCY – 148

(3 + 2n)tCY – 162

Read data hold time

RD low-level width

0

tRDL1

tRDL2

tRDWT1

tRDWT2

tWRWT

tWTL

(1.5 + 2n)tCY – 40

(2.5 + 2n)tCY – 40

Input time from RD↓ to WAIT↓

tCY – 75

tCY – 60

Input time from WR↓ to WAIT↓

WAIT low-level width

tCY – 50

(0.5 + 2n)tCY + 10

(2 + 2n)tCY

Write data setup time

tWDS

60

10

Write data hold time

tWDH

WR low-level width

tWRL1

tASTRD

tASTWR

tRDAST

(1.5 + 2n)tCY – 30

10

Delay time from ASTB↓ to RD↓

Delay time from ASTB↓ to WR↓

2tCY – 30

0.8tCY – 30

Delay time from RD↑ to ASTB↑ in

1.2tCY

external fetch

Hold time from RD↑ to address in

tRDADH

0.8tCY – 30

1.2tCY + 60

ns

external fetch

Write data output time from RD↑

Write data output time from WR↓

Hold time from WR↑ to address

Delay time from WAIT↑ to RD↑

Delay time from WAIT↑ to WR↑

tRDWD

tWRWD

tWRADH

tWTRD

40

20

ns

120

0.8tCY – 30

0.5tCY

1.2tCY + 60

2.5tCY + 50

tWTWR

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

3. C^L= 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB

pins.)

34

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

(2) Read/write operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)

(3/3)

Parameter

ASTB high-level width

Address setup time

Symbol

tASTH

tADS

Conditions

MIN.

0.3tCY

120

MAX.

Unit

ns

Address hold time

tADH

20

Input time from address to data

tADD1

tADD2

tRDAD

tRDD1

tRDD2

tRDH

(2 + 2n)tCY – 233

(3 + 2n)tCY – 240

400

Output time from RD↓ to address

Input time from RD↓ to data

0

(2 + 2n)tCY – 325

(3 + 2n)tCY – 332

Read data hold time

RD low-level width

0

tRDL1

tRDL2

tRDWT1

tRDWT2

tWRWT

tWTL

(1.5 + 2n)tCY – 92

(2.5 + 2n)tCY – 92

Input time from RD↓ to WAIT↓

tCY – 350

tCY – 132

tCY – 100

(2 + 2n)tCY

Input time from WR↓ to WAIT↓

WAIT low-level width

(0.5 + 2n)tCY + 10

Write data setup time

tWDS

60

20

Write data hold time

tWDH

WR low-level width

tWRL1

tASTRD

tASTWR

tRDAST

(1.5 + 2n)tCY – 60

20

Delay time from ASTB↓ to RD↓

Delay time from ASTB↓ to WR↓

2tCY – 60

0.8tCY – 60

Delay time from RD↑ to ASTB↑ in

1.2tCY

external fetch

Hold time from RD↑ to address in

t^RDADH

0.8tCY – 60

1.2tCY + 120

ns

external fetch

Write data output time from RD↑

Write data output time from WR↓

Hold time from WR↑ to address

Delay time from WAIT↑ to RD↑

Delay time from WAIT↑ to WR↑

tRDWD

tWRWD

tWRADH

tWTRD

40

ns

240

0.8tCY – 60

0.5tCY

1.2tCY + 120

2.5tCY + 100

tWTWR

Remarks 1. tCY = TCY/4

2. n indicates the number of waits.

3. C^L= 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB

pins.)

Data Sheet U14040EJ4V0DS

35

µPD78F0034A, 78F0034AY

(3) Serial interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

(a) 3-wire serial I/O mode (SCK3n... internal clock output)

Parameter

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

MIN.

954

TYP.

MAX.

Unit

ns

SCK3n cycle time

tKCY1

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

VDD = 4.0 to 5.5 V

VDD = 1.8 to 5.5 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

1,600

3,200

SCK3n high-/low-level

width

tKH1

tKL1

tKCY1/2 – 50

tKCY1/2 – 100

100

SI3n setup time

tSIK1

(to SCK3n↑)

150

300

SI3n hold time

t^KSI1

400

(from SCK3n↑)

Note

Output delay time from

t^KSO1

C = 100 pF

300

ns

SCK3n↓ to SO3n

Note C is the load capacitance of the SCK3n and SO3n output lines.

(b) 3-wire serial I/O mode (SCK3n... external clock input)

Parameter

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

MIN.

800

TYP.

MAX.

Unit

ns

SCK3n cycle time

tKCY2

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

1,600

3,200

400

SCK3n high-/low-level

width

tKH2

tKL2

800

1,600

100

SI3n setup time

tSIK2

t^KSI2

tKSO2

(to SCK3n↑)

SI3n hold time

400

ns

(from SCK3n↑)

Note

Output delay time from

C = 100 pF

300

SCK3n↓ to SO3n

Note C is the load capacitance of the SO3n output line.

Remark µPD78F0034A: n = 0, 1

µPD78F0034AY: n = 0

36

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

(c) UART mode (dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

MIN.

TYP.

MAX.

131,031

78,125

39,063

Unit

bps

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

(d) UART mode (external clock input)

Parameter

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

MIN.

800

TYP.

MAX.

Unit

ns

ASCK0 cycle time

tKCY3

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ VDD < 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

1.8 V ≤ V^DD< 2.7 V

1,600

3,200

400

ns

ASCK0 high-/low-level

width

tKH3,

tKL3

ns

800

ns

1,600

ns

Transfer rate

39,063

19,531

9,766

bps

(e) UART mode (infrared data transfer mode)

Parameter

Transfer rate

Symbol

Conditions

MIN.

MAX.

131,031

0.87

Unit

bps

%

VDD = 4.0 to 5.5 V

Bit rate allowable error

Output pulse width

Input pulse width

Note

1.2

0.24/fbr

µs

4/fX

µs

Note fbr: Specified baud rate

Data Sheet U14040EJ4V0DS

37

µPD78F0034A, 78F0034AY

(f) I²C bus Mode (µPD78F0034AY only)

Parameter

Symbol

Standard Mode

High-Speed Mode

Unit

MIN.

MAX.

100

–

MIN.

0

MAX.

SCL0 clock frequency

fCLK

0

400

kHz

Bus free time

t^BUF

4.7

1.3

–

µs

(between stop and start condition)

Hold time^{Note 1}

tHD:STA

tLOW

4.0

4.7

4.0

4.7

5.0

0^{Note 2}

250

–

0.6

–

µs

ns

µs

ns

pF

SCL0 clock low-level width

SCL0 clock high-level width

Start/restart condition setup time

Data hold time CBUS compatible master

I²C bus

–

1.3

–

tHIGH

–

0.6

–

tSU:STA

tHD:DAT

0.6

–

0^{Note 2}

0.9^{Note 3}

–

Data setup time

tSU:DAT

tR

–

100^{Note 4}

SDA0 and SCL0 signal rise time

SDA0 and SCL0 signal fall time

Stop condition setup time

Spike pulse width controlled by input filter

Capacitive load per each bus line

1,000

300

–

20 + 0.1Cb^{Note 5}

300

–

tF

–

20 + 0.1Cb^{Note 5}

tSU:STO

tSP

4.0

–

0.6

0

–

50

Cb

–

400

–

400

Notes 1. In the start condition, the first clock pulse is generated after this hold time.

2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide

at least 300 ns of hold time for the SDA0 signal (which is V^IHmin.of the SCL0 signal).

3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT

needs to be fulfilled.

4. The high-speed mode I²C bus is available in a standard mode I²C bus system. At this time, the

conditions described below must be satisfied.

• If the device does not extend the SCL0 signal low state hold time

t^SU:DAT≥ 250 ns

• If the device extends the SCL0 signal low state hold time

Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (t^Rmax.+ tSU:DAT

= 1,000 + 250 = 1,250 ns by standard mode I²C bus specification).

5. Cb: Total capacitance per one bus line (unit: pF)

38

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

AC Timing Measurement Point (Excluding X1, XT1 Input)

0.8VDD

0.2VDD

Point of measurement

0.2VDD

Clock Timing

1/fX

t

XL

t

XH

V

IH4 (MIN.)

IL4 (MAX.)

X1 input

V

1/fXT

t

XTL

t

XTH

V

IH5 (MIN.)

IL5 (MAX.)

XT1 input

V

TI Timing

tTIL0

t

TIH0

TI00, TI01

1/fTI5

t

TIL5

t

TIH5

TI50, TI51

Data Sheet U14040EJ4V0DS

39

µPD78F0034A, 78F0034AY

Interrupt Request Input Timing

tINTL

tINTH

INTP0 to INTP3

RESET Input Timing

t

RSL

RESET

40

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Read/Write Operation

External fetch (no wait):

A8 to A15

Higher 8-bit address

Hi-Z

tADD1

Lower 8-bit

address

AD0 to AD7

Instruction code

t

RDAD

t

ADS

t

RDD1

t

ADH

t

RDADH

RDAST

t

ASTH

t

ASTB

RD

t

ASTRD

t

RDL1

t

RDH

External fetch (wait insertion):

A8 to A15

Higher 8-bit address

Hi-Z

t

ADD1

Lower 8-bit

address

AD0 to AD7

Instruction code

t

RDAD

t

ADS

t

RDADH

RDAST

t

ADH

t

RDD1

t

ASTH

t

ASTB

RD

t

ASTRD

t

RDL1

t

RDH

WAIT

t

RDWT1

t

WTL

t

WTRD

Data Sheet U14040EJ4V0DS

41

µPD78F0034A, 78F0034AY

External data access (no wait):

A8 to A15

Higher 8-bit address

t

ADD2

Hi-Z

Lower 8-bit

address

AD0 to AD7

Read data

Write data

t

RDAD

t

ADS

t

RDD2

t

ADH

t

ASTH

t

RDH

ASTB

RD

t

RDWD

t

ASTRD

t

RDL2

t

WDS

t

WDH

WRADH

t

WRWD

WR

t

ASTWR

t

WRL1

External data access (wait insertion):

A8 to A15

Higher 8-bit address

Read data

t

ADD2

Hi-Z

Lower 8-bit

Write data

AD0 to AD7

address

t

RDAD

t

ADH

t

ADS

t

RDH

t

ASTH

t

RDD2

ASTB

RD

tASTRD

t

RDWD

t

RDL2

t

WDS

t

WDH

t

WRWD

WR

t

ASTWR

t

WRL1

t

WRADH

WAIT

t

WTL

t

WTRD

t

RDWT2

t

WTL

t

WRWT

t

WTWR

42

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Serial Transfer Timing

3-wire serial I/O mode:

t

KCYm

tKLm

tKHm

SCK3n

SI3n

t

SIKm

t

KSIm

Input data

tKSOm

SO3n

Output data

Remarks 1. m = 1, 2

2. µPD78F0034A: n = 0, 1

3. µPD78F0034AY: n = 0

UART mode (external clock input):

KCY3

t

KL3

t_KH3

ASCK0

I²C bus mode (µPD78F0034AY only):

t

LOW

t

R

SCL0

SDA0

t

F

t

HD:DAT

t

HIGH

SU:DAT

t

SU:STA

t

HD:STA

t

SP

tSU:STO

t

HD:STA

t

tBUF

Stop

Start

Restart

condition

Stop

condition

condition condition

Data Sheet U14040EJ4V0DS

43

µPD78F0034A, 78F0034AY

A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Note

Overall error

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

1.8 V ≤ AVREF < 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

1.8 V ≤ AVREF < 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

1.8 V ≤ AVREF < 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

1.8 V ≤ AVREF < 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

1.8 V ≤ AVREF < 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF ≤ 4.0 V

1.8 V ≤ AVREF < 2.7 V

0.2

0.3

0.6

0.4

0.6

1.2

96

%FSR

µs

Conversion time

tCONV

14

19

28

96

µs

96

µs

Notes 1, 2

Zero-scale error

0.4

0.6

1.2

0.4

0.6

1.2

2.5

4.5

8.5

1.5

2.0

3.5

AVREF

AVDD

%FSR

LSB

V

Notes 1, 2

Full-scale error

Note 1

Integral linearity error

Differential linearity error

Analog input voltage

Reference voltage

VIAN

0

AVREF

1.8

20

V

Resistance between AV^REFand AVSS RREF

During A/D conversion operation

40

kΩ

Notes 1. Excluding quantization error ( 1/2 LSB).

2. Indicated as a ratio to the full-scale value (%FSR).

Remark When the µPD78F0034A or 78F0034AY is used as an 8-bit resolution A/D converter, the specifications

are the same as for the µPD780024A or 78F0024AY Subseries A/D converter.

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= –40 to +85°C)

Parameter

Symbol

VDDDR

IDDDR

Conditions

MIN.

1.6

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Data retention supply current

Subsystem clock stop (XT1 = VDD)

and feed-back resistor disconnected

0.1

30

µA

Release signal set time

tSREL

tWAIT

0

µs

s

17

Oscillation stabilization wait time

Release by RESET

2 /fX

Release by interrupt request

Note

s

Note Selection of 2¹²/fX and 2¹⁴/fX to 2¹⁷/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time select register (OSTS).

44

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Data Retention Timing (STOP Mode Release by RESET)

Internal reset operation

HALT mode

Operating mode

STOP mode

Data retention mode

V

DD

V

DDDR

t

SREL

STOP instruction execution

RESET

t

WAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)

HALT mode

Operating mode

STOP mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction execution

Standby release signal

(Interrupt request)

tWAIT

Data Sheet U14040EJ4V0DS

45

µPD78F0034A, 78F0034AY

Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, VSS = 0 V, VPP = 9.7 to 10.3 V)

(1) Basic characteristics

Parameter

Symbol

Conditions

4.0 ≤ VDD ≤ 5.5 V

MIN.

1.0

2.7

0

TYP.

MAX.

8.38

Unit

MHz

V

Operating frequency

fX

2.7 ≤ VDD < 4.0 V

5.0

Supply voltage

VDD

Operation voltage when writing

Upon VPP low-level detection

Upon VPP high-level detection

Upon VPP high-voltage detection

5.5

VPPL

VPP

0.2VDD

1.2VDD

V

0.8VDD

VDD

V

Note 1

VPPH

IDD

9.7

10.0

10.3

V

VDD supply current

VPP supply current

Write time (per byte)

Number of rewrites

Erase time

10

mA

µs

IPP

VPP =10.0 V

75

100

TWRT

CWRT

TERASE

T^PRG

50

500

Note 2

20

Times

s

1

20

Programming temperature

+10

+40

°C

Notes 1. For the product grades “K, E, and P”, 10.2 V (MIN.), 10.3 V (TYP.), and 10.4 V (MAX.), are applied.

2. For the product specification “K and E”, the number is 1 (MAX.).

(2) Serial write operation characteristics

Parameter

Symbol

tPSRON

tDRPSR

tPSRRF

tRFCF

tCOUNT

tCH

Conditions

VPP high voltage

MIN.

1.0

TYP.

MAX.

Unit

µs

VPP set time

Set time from VDD↑ to VPP↑

Set time from VPP↑ to RESET↑

VPP count start time from RESET↑

Count execution time

VPP high voltage

1.0

µs

1.0

µs

1.0

µs

2.0

ms

µs

VPP counter high-level width

VPP counter low-level width

VPP counter noise elimination width

8.0

tCL

µs

tNFW

40

ns

Flash Memory Write Mode Set Timing

VDD

0 V

tDRPSR

t

RFCF

t

CH

V

PPH

VPP

VPPL

tCL

t

PSRON PSRRF

t

tCOUNT

V

DD

RESET (input)

0 V

46

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

8. PACKAGE DRAWINGS

64-PIN PLASTIC SDIP (19.05mm(750))

64

33

32

1

A

K

L

J

I

M

R

F

M

N

C

B

D

H

G

NOTES

ITEM MILLIMETERS

1. Each lead centerline is located within 0.17 mm of

its true position (T.P.) at maximum material condition.

+0.68

58.0

A

−0.20

B

C

D

F

1.78 MAX.

1.778 (T.P.)

0.50 0.10

0.9 MIN.

2. Item "K" to center of leads when formed parallel.

G

H

3.2 0.3

0.51 MIN.

+0.26

4.05

I

−0.20

J

K

L

5.08 MAX.

19.05 (T.P.)

17.0 0.2

+0.10

0.25

M

−0.05

N

R

0.17

0 ∼ 15°

P64C-70-750A,C-4

Remark The package and material of ES products are the same as mass produced products.

47

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

64-PIN PLASTIC LQFP (10x10)

A

B

detail of lead end

48

49

33

32

S

P

T

C

D

R

L

U

64

1

17

Q

16

F

G

J

M

H

I

ITEM MILLIMETERS

A

B

C

D

F

G

H

I

12.0 0.2

10.0 0.2

12.0 0.2

1.25

K

S

1.25

0.22 0.05

0.08

M

N

S

J

0.5 (T.P.)

1.0 0.2

0.5

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

K

L

+0.03

0.17

M

−0.07

N

P

Q

0.08

1.4

0.1 0.05

+4°

3°

R

−3°

S

T

1.5 0.10

0.25

U

0.6 0.15

S64GB-50-8EU-2

Remark The package and material of ES products are the same as mass produced products.

48

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

64-PIN PLASTIC LQFP (14x14)

A

B

48

49

33

32

detail of lead end

S

P

C

D

T

R

L

U

64

1

17

16

Q

F

G

J

M

H

I

ITEM MILLIMETERS

A

B

C

D

F

17.2 0.2

14.0 0.2

17.2 0.2

1.0

K

S

G

1.0

+0.08

0.37

H

−0.07

N

S

M

I

J

0.20

0.8 (T.P.)

1.6 0.2

0.8

K

L

NOTE

Each lead centerline is located within 0.20 mm of

its true position (T.P.) at maximum material condition.

+0.03

0.17

M

−0.06

N

P

Q

0.10

1.4 0.1

0.127 0.075

+4°

3°

R

−3°

S

T

1.7 MAX.

0.25

U

0.886 0.15

P64GC-80-8BS

Remark The package and material of ES products are the same as mass produced products.

49

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

64-PIN PLASTIC QFP (14x14)

A

B

48

49

33

32

detail of lead end

S

C D

Q

R

64

17

16

1

F

P

J

G

M

H

I

K

S

L

N

S

M

NOTE

Each lead centerline is located within 0.15 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

D

F

17.6 0.4

14.0 0.2

17.6 0.4

1.0

G

1.0

+0.08

0.37

H

−0.07

I

J

0.15

0.8 (T.P.)

1.8 0.2

0.8 0.2

K

L

+0.08

0.17

M

−0.07

N

P

Q

R

S

0.10

2.55 0.1

0.1 0.1

5° 5°

2.85 MAX.

P64GC-80-AB8-5

Remark The package and material of ES products are the same as mass produced products.

50

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

64-PIN PLASTIC TQFP (12x12)

A

B

detail of lead end

48

49

33

32

S

P

T

C

D

R

L

U

Q

64

1

17

16

F

G

J

M

H

I

ITEM MILLIMETERS

A

B

C

D

F

14.0 0.2

12.0 0.2

14.0 0.2

1.125

K

S

G

1.125

+0.06

0.32

H

−0.10

M

I

0.13

J

K

L

0.65 (T.P.)

1.0 0.2

0.5

N

S

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

+0.03

0.17

M

−0.07

N

P

Q

0.10

1.0

0.1 0.05

+4°

3°

R

−3°

1.1 0.1

0.25

S

T

U

0.6 0.15

P64GK-65-9ET-3

Remark The package and material of ES products are the same as mass produced products.

51

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

9. RECOMMENDED SOLDERING CONDITIONS

The µPD78F0034A, 78F0034AY should be soldered and mounted under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 9-1. Surface Mounting Type Soldering Conditions (1/2)

(1) µPD78F0034AGC-8BS: 64-pin plastic LQFP (14 × 14)

µPD78F0034AYGC-8BS: 64-pin plastic LQFP (14 × 14)

µPD78F0034AGC-AB8: 64-pin plastic QFP (14 × 14)

µPD78F0034AYGC-AB8: 64-pin plastic QFP (14 × 14)

Soldering Method

Infrared reflow

VPS

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

IR35-00-2

VP15-00-2

WS60-00-1

–

Count: Two times or less

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: Two times or less

Wave soldering

Partial heating

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature)

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

(2) µPD78F0034AGB-8EU: 64-pin plastic LQFP (10 × 10)

µPD78F0034AYGB-8EU: 64-pin plastic LQFP (10 × 10)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less,

IR35-107-2

VP15-107-2

–

Note

Exposure limit: 7 days

(after 7 days, prebake at 125°C for 10 hours)

VPS

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: Two times or less,

Note

Exposure limit: 7 days

(after 7 days, prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

52

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Table 9-1. Surface Mounting Type Soldering Conditions (2/2)

(3) µPD78F0034AGK-9ET: 64-pin plastic TQFP (12 × 12)

µPD78F0034AYGK-9ET: 64-pin plastic TQFP (12 × 12)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less,

IR35-107-2

VP15-107-2

WS60-107-1

–

Note

Exposure limit: 7 days

(after 7 days, prebake at 125°C for 10 hours)

VPS

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: Two times or less,

Note

Exposure limit: 7 days

(after 7 days, prebake at 125°C for 10 hours)

Wave soldering

Solder bath temperature: 260°C max., Time: 10 seconds max.,

Count: Once, Preheating temperature: 120°C max. (package surface temperature),

Note

Exposure limit: 7 days

(after 7 days, prebake at 125°C for 10 hours)

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Table 9-2. Insertion Type Soldering Conditions

µPD78F0034ACW: 64-pin plastic SDIP (19.05 mm (750))

µPD78F0034AYCW: 64-pin plastic SDIP (19.05 mm (750))

Soldering Method

Wave soldering (pin only)

Partial heating

Soldering Conditions

Solder bath temperature: 260°C max., Time: 10 seconds max.

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with

the package.

53

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD78F0034A, 78F0034AY

Subseries.

Also refer to (5) Cautions on Using Development Tools.

(1) Language Processing Software

RA78K0

Assembler package common to 78K/0 Series

C compiler package common to 78K/0 Series

Device file for µPD780034A, 78F0034AY Subseries

C compiler library source file common to 78K/0 Series

CC78K0

DF780034

CC78K0-L

(2) Flash Memory Writing Tools

Flashpro III

Flash programmer dedicated to microcontrollers with on-chip flash memory

(part No. FL-PR3, PG-FP3)

FA-64CW, FA-64GC,

FA-64GC-8BS,

FA-64GB-8EU,

FA-64GK-9ET

Adapter for flash memory writing

(3) Debugging Tools

• When IE-78K0-NS in-circuit emulator is used

IE-78K0-NS

IE-70000-MC-PS-B

In-circuit emulator common to 78K/0 Series

Power supply unit for IE-78K0-NS

IE-78K0-NS-PA

Performance board that enhances and expands the IE-78K0-NS functions

IE-70000-98-IF-C

Adapter required when using PC-9800 series PC (except notebook type) as host machine

(C bus supported)

IE-70000-CD-IF-A

PC card and interface cable when using PC-9800 series notebook PC as host machine (PCMCIA

socket supported)

TM

IE-70000-PC-IF-C

IE-70000-PCI-IF-A

IE-780034-NS-EM1

NP-64CW

Adapter required when using IBM PC/AT

or compatible as host machine (ISA bus supported)

Adapter necessary when using PC in which PCI bus is incorporated as host machine

Emulation board to emulate the µPD780034A, 78F0034AY Subseries

Emulation probe for 64-pin plastic SDIP (CW type)

NP-64GC, NP-64GC-TQ

NP-64GK

Emulation probe for 64-pin plastic QFP (CG-AB8, GC-8BS type)

Emulation probe for 64-pin plastic TQFP (GK-9ET type)

NP-H64GB-TQ

EV-9200GC-64

Emulation probe for 64-pin plastic LQFP (GB-8EU type)

Conversion socket to connect the NP-64GC and a target system board on which a 64-pin plastic

QFP (GC-AB8, GC-8BS type) can be mounted

TGC-064SAP

TGK-064SBP

TGB-064SDP

Conversion adapter to connect the NP-64GC-TQ and a target system board on which a 64-pin

plastic QFP (GC-AB8, GC-8BS type) can be mounted

Conversion adapter to connect the NP-64GK and a target system board on which a 64-pin plastic

TQFP (GK-9ET type) can be mounted

Conversion adapter to connect the NP-H64GB-TQ and a target system board on which a 64-pin

plastic LQFP (GB-8EU type) can be mounted

ID78K0-NS

SM78K0

Integrated debugger for IE-78K0-NS

System simulator common to 78K/0 Series

Device file for µPD780034A, 78F0034AY Subseries

DF780034

54

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

• When using in-circuit emulator IE-78001-R-A

IE-78001-R-A

In-circuit emulator common to 78K/0 Series

IE-70000-98-IF-C

Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus

supported)

IE-70000-PC-IF-C

IE-70000-PCI-IF-A

IE-780034-NS-EM1

IE-78K0-R-EX1

EP-78240CW-R

EP-78240GC-R

EP-78012GK-R

EV-9200GC-64

Adapter required when using IBM PC/AT or compatible as host machine (ISA bus supported)

Adapter required when using PC in which PCI bus is incorporated as host machine

Emulation board to emulate µPD780034A, 78F0034AY Subseries

Emulation probe conversion board to use IE-780034-NS-EM1 on IE-78001-R-A

Emulation probe for 64-pin plastic SDIP (CW type)

Emulation probe for 64-pin plastic QFP (GC-AB8, GC-8BS type)

Emulation probe for 64-pin plastic TQFP (GK-9ET type)

Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin

plastic QFP (GC-AB8, GC-8BS type) can be mounted

TGK-064SBP

Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin

plastic TQFP (GK-9ET type) can be mounted

ID78K0

Integrated debugger for IE-78001-R-A

SM78K0

DF780034

System simulator common to 78K/0 Series

Device file for µPD780034A, 78F0034AY Subseries

(4) Real-Time OS

RX78K0

Real-time OS for 78K/0 Series

55

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

(5) Cautions on Using Development Tools

•

The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.

The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780034.

The FL-PR3, FA-64CW, FA-64GC, FA-64GC-8BS, FA-64GB-8EU, FA-64GK-9ET, NP-64CW, NP-64GC, NP-

64GC-TQ, NP-64GK, and NP-H64GB-TQ are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-45-

475-4191).

•

The TGK-064SBW, TGC-064SAP, TGK-064-SBP, and TGB-064SDP are products made by TOKYO ELETECH

CORPORATION.

For further information contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (+81-3-3820-7112)

Osaka Electronic Division (+81-6-6244-6672)

•

For third party development tools, see the Single-Chip Microcontroller Selection Guide (U11069E).

The host machines and OSs supporting each software are as follows.

Host Machine

[OS]

PC

EWS

TM

PC-9800 series [Japanese Windows

IBM PC/AT or compatibles

]

HP9000 series 700

[HP-UX

TM

]

TM

SPARCstation

[SunOS , Solaris

]

Software

RA78K0

CC78K0

ID78K0-NS

ID78K0

[Japanese/English Windows]

Note

√

–

√

Note

√

SM78K0

RX78K0

Note

√

Note DOS-based software

56

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Conversion Socket Drawing (EV-9200GC-64) and Footprints

Figure A-1. EV-9200GC-64 Drawing (For Reference Only)

A

B

M

N

E

O

F

EV-9200GC-64

1

P

No.1 pin index

G

H

I

EV-9200GC-64-G0

ITEM

A

MILLIMETERS

18.8

14.1

18.8

4-C 3.0

0.8

INCHES

0.74

B

0.555

0.74

C

D

E

4-C 0.118

0.031

0.236

0.622

0.728

0.236

0.622

0.728

0.315

0.307

0.098

0.079

F

G

H

I

6.0

15.8

18.5

6.0

J

K

15.8

18.5

8.0

L

M

N

O

P

7.8

2.5

2.0

Q

R

S

1.35

0.35 0.1

2.3

0.053

+0.004

–0.005

0.014

0.091

0.059

T

1.5

57

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Figure A-2. EV-9200GC-64 Footprints (For Reference Only)

G

J

K

L

C

B

A

EV-9200GC-64-P1E

ITEM

MILLIMETERS

19.5

INCHES

A

B

C

D

E

F

G

H

I

0.768

0.583

14.8

+0.002

+0.003

–0.002

0.8 0.02 × 15=12.0 0.05 0.031

× 0.591=0.472

–0.001

+0.002

–0.001

+0.003

–0.002

0.8 0.02 × 15=12.0 0.05 0.031

14.8

0.583

0.768

0.236

0.197

19.5

+0.004

6.00 0.08

0.5 0.02

2.36 0.03

2.2 0.1

1.57 0.03

–0.003

+0.004

–0.003

+0.001

–0.002

+0.001

J

0.093

0.087

0.062

–0.002

+0.004

–0.005

K

L

+0.001

–0.002

DimensionsofmountpadforEV-9200andthatfortargetdevice

(QFP)maybedifferentinsomeparts.Fortherecommended

mountpaddimensionsforQFP,referto"SEMICONDUCTOR

DEVICE MOUNTING TECHNOLOGY MANUAL"

(C10535E).

Caution

58

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Conversion Adapter Drawing (TGC-064SAP)

Figure A-3. TGC-064SAP Drawing (For Reference Only)

A

B

I

J

K

C

S

Protrusion height

T

D

E F G H

Q R

M

N

L

O

P

V

W

d

U

j

i

X

Z

c

b

a

Y

ITEM MILLIMETERS

INCHES

0.556

ITEM MILLIMETERS

INCHES

0.073

A

B

C

D

E

F

14.12

0.8x15=12.0

0.8

a

b

c

d

e

f

1.85

3.5

0.031x0.591=0.472

0.031

0.138

0.079

2.0

e g

f

h

0.813

6.0

0.236

20.65

10.0

0.394

0.25

13.6

1.2

0.010

12.4

0.488

0.535

G

H

I

14.8

0.583

g

h

i

0.047

17.2

0.677

1.2

0.047

C 2.0

9.05

C 0.079

0.356

2.4

0.094

j

2.7

0.106

J

K

L

5.0

0.197

TGC-064SAP-G0E

13.35

1.325

16.0

0.526

M

N

O

P

Q

R

S

T

0.052

0.630

20.65

12.5

0.813

0.492

17.5

0.689

4-

φ

1.3

4-φ0.051

1.8

0.071

U

V

W

X

Y

Z

φ

3.55

0.9

φ

0.140

0.035

0.012

0.3

(19.65)

7.35

(0.667)

0.289

0.047

1.2

note: Product by TOKYO ELETECH CORPORATION.

59

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Conversion Adapter Drawing (TGK-064SBP)

Figure A-4. TGK-064SBP Drawing (For Reference Only) (Unit: mm)

A

B

L

K

Y

C

M

T

U

G F E D

H

I

J

R

V

_WX

Protrusion height

S

N

O

P

Q

a

b

i

Z

n

m

e

h

c

ITEM MILLIMETERS

INCHES

0.724

ITEM MILLIMETERS

INCHES

0.035

d

g

f

A

B

C

D

E

F

18.4

a

b

c

d

e

f

φ

0.9

0.3

φ

0.65x15=9.75

0.65

0.026x0.591=0.384

0.026

0.012

(16.95)

7.35

1.2

(0.667)

0.289

0.047

0.073

0.138

0.079

0.236

0.010

0.052

0.094

0.106

0.305

7.75

k

l

j

10.15

12.55

14.95

0.65x15=9.75

11.85

18.4

0.400

0.494

1.85

3.5

G

H

I

0.589

g

h

i

0.026x0.591=0.384

0.467

2.0

6.0

j

0.25

1.325

2.4

J

0.724

K

L

C 2.0

12.45

10.25

7.7

C 0.079

0.490

k

l

M

N

O

P

Q

R

S

T

0.404

m

n

0.303

2.7

10.02

14.92

18.4

0.394

TGK-064SBP-G0E

0.587

0.724

11.1

0.437

1.45

0.057

1.45

0.057

U

V

W

X

Y

Z

5.0

0.197

4-

1.8

5.3

4-C 1.0

3.55

φ

1.3

φ

0.051

0.071

φ

0.209

4-C 0.039

φ

φ0.140

Note: Product by TOKYO ELETECH CORPORATION.

60

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

APPENDIX B. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Documents Related to Devices

Document Name

Document No.

U14046E

µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual

µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet U14042E

µPD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),

U15131E

780024AY(A) Data Sheet

µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet U14044E

µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A),

780034AY(A) Data Sheet

U15132E

µPD78F0034A, 78F0034AY Data Sheet

This manual

U12326E

78K/0 Series User’s Manual Instruction

Documents Related to Development Software Tools (User’s Manuals)

Document Name

Document No.

U14445E

RA78K0 Assembler Package

CC78K0 C Compiler

Operation

Language

U14446E

Structured Assembly Language U11789E

Operation

U14297E

U14298E

U14611E

U15006E

Language

SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later

SM78K Series System Simulator Ver. 2.10 or Later

Operation (Windows Based)

External Part User Open

Interface Specifications

Operation (Windows Based)

Reference

ID78K0-NS Integrated Debugger Ver. 2.00 or Later

ID78K0 Integrated Debugger Windows Based

U14379E

U11539E

U11649E

U11537E

U11536E

U14610E

Guide

RX78K0 Real-Time OS

Fundamentals

Installation

Project Manager Ver. 3.12 or Later (Windows Based)

Documents Related to Development Hardware Tools (User’s Manuals)

Document Name

IE-78K0-NS In-Circuit Emulator

Document No.

U13731E

IE-78K0-NS-A In-Circuit Emulator

U14889E

IE-78001-R-A In-Circuit Emulator

U14142E

IE-78K0-R-EX1 In-Circuit Emulator

To be prepared

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

61

Data Sheet U14040EJ4V0DS

µPD78F0034A, 78F0034AY

Documents Related to Flash Memory Writing

Document Name

Document No.

U13502E

PG-FP3 Flash Memory Programmer User’s Manual


型号：	UPD780344
厂家：	NEC
描述：	8-BIT SINGLE-CHIP MICROCONTROLLER 8位单芯片微控制器微控制器
文件：	总66页 (文件大小：551K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD780344 [NEC]

相关型号：

UPD780344F1-XXX-DA3

UPD780344GC-XXX-8EU

UPD780344Y

UPD780344YGC-XXX-8EU-A

UPD780353

UPD780353F1-XXX-DA3

UPD780353GC-XXX-8EU-A

UPD780353Y

UPD780353YGC-XXX-8EU

UPD780353YGC-XXX-8EU-A

UPD780354

UPD780354GC-XXX-8EU