UPD78063GC-XXX-7EA [NEC]
Microcontroller, 8-Bit, MROM, 5MHz, MOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, QFP-100;
| 型号： | UPD78063GC-XXX-7EA |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, MOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总68页 (文件大小：540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78062(A), 78063(A), 78064(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78062(A), 78063(A), and 78064(A) are products to which a quality assurance program more stringent than that
used for the µPD78062, 78063, and 78064 (standard models) is applied (NEC classifies these products as “special” quality
grade models).
µPD78062(A), 78063(A), and 78064(A) are products in the µPD78064 subseries within the 78K/0 series, which
incorporate LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other
peripheral hardwares.
Various development tools are also provided.
For the details of functional description, refer to the following user's manual.Be sure to read this manual
before designing your system.
µPD78064 78064Y Subseries User's Manual : U10105E
78K/0 Series User's Manual (Instruction
: IEU-1372
FEATURES
•
Large on-chip ROM & RAM
Item
Program Memory
(ROM)
Data Memory
Internal High-Speed RAM
Package
Product Name
LCD Display RAM
µPD78062(A)
µPD78063(A)
µPD78064(A)
16K bytes
24K bytes
32K bytes
512 bytes
100-pin plastic QFP (fine pitch)
(14 × 14mm, 0.5 mm pitch)
100-pin plastic QFP
1024 bytes
40 × 4 bits
(14 × 20 mm, 0.65 mm pitch)
Note
100-pin plastic LQFP
(fine pitch)
(14 × 14 mm, 0.5 mm pitch)
Note Under planning
• Minimum instruction execution time can be varied from high speed (0.4 µs) to ultra-low speed (122 µs)
• I/O ports: 57 (including segment signal output dual-function pins)
• LCD controller/driver
Supply voltage
VDD = 2.0 to 6.0 V (Static display mode)
VDD = 2.5 to 6.0 V (1/3 bias)
VDD = 2.7 to 6.0 V (1/2 bias)
• 8-bit resolution A/D converter : 8 channels
• Serial interface : 2 channels
• Timer: 5 channels
• Supply voltage : VDD = 2.0 to 6.0 V
The information in this document is subject to change without notice.
Document No. U10335EJ2V0DS00 (2nd edition)
Date Published August 1997 N
Printed in Japan
The mark
shows major revised points.
1997
©
µPD78062(A), 78063(A), 78064(A)
APPLICATIONS
Controlunitsofautomobileelectronicsystems,gasdetectorsandcircuitbreakers,varioussafetysystems,hemadynamometers,
etc.
ORDERING INFORMATION
Part Number
Package
µPD78062GC(A)-×××-7EA
100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness: 1.45 mm)
µPD78062GC(A)-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness: 1.40 mm)
µPD78062GF(A)-×××-3BA
µPD78063GC(A)-×××-7EA
100-pin plastic QFP (14 ×20mm)
100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness: 1.45 mm)
µPD78063GC(A)-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness: 1.40 mm)
µPD78063GF(A)-×××-3BA
100-pin plastic QFP (14 ×20mm)
µPD78064GC(A)-×××-7EA
100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness: 1.45 mm)
µPD78064GC(A)-×××-8EUNote 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness: 1.40 mm)
µPD78064GF(A)-×××-3BA
100-pin plastic QFP (14 ×20mm)
Note Under planning
Caution The µPD78062GC(A), 78063GC(A), and 78064GC(A) are available in two types of packages (refer to 12.
PACKAGE DRAWINGS). For the available packages, consult NEC.
Remark
××× indicates a ROM code suffix.
QUALITY GRADE
Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
DIFFERENCES BETWEEN µPD78062(A), 78063(A) and 78064(A), and µPD78062, 78063 and 78064
Product name
µPD78062(A), 78063(A), 78064(A)
Special
µPD78062, 78063, 78064
Item
Quality grade
Standard
2
µPD78062(A), 78063(A), 78064(A)
78K/0 SERIES DEVELOPMENT
The following shows the 78 K/0 Series products development. Subseries names are shown inside frames.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
EMI noise reduction version of the µPD78078.
PD78075B
PD78078
µPD78075BY
µPD78078Y
µPD78070AY
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
A timer was added to the µPD78054, and the external interface function was enhanced.
µPD78070A
ROM-less versions of the PD78078.
µ
Serial I/O of the µPD78078Y was enhanced, and only selected functions are provided.
PD780018AY
µ
PD780058YNote
Serial I/O of the µPD78054 was enhanced, EMI noise reduction version.
PD780058
µ
µ
EMI noise reduction version of the PD78054.
µ
µPD78058F
PD78054
µPD78058FY
80-pin
µ
UART and D/A converter were added to the PD78014, and I/O was enhanced.
80-pin
PD78054Y
PD780034Y
PD780024Y
µ
µ
µ
µ
PD780034
µ
µ
An A/D converter of the PD780024 was enhanced.
64-pin
PD780024
64-pin
64-pin
µ
µ
Serial I/O of the PD78018F was enhanced, EMI noise reduction version.
µ
EMI noise reduction version of µPD78018F.
PD78014H
PD78018F
PD78014
Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available.
µ
64-pin
µ
µ
PD78018FY
PD78014Y
µ
µ
µ
µ
µ
An A/D converter and 16-bit timer were added to the PD78002.
µ
64-pin
An A/D converter was added to the PD78002.
µ
PD780001
64-pin
µPD78002Y
Basic subseries for control.
PD78002
PD78083
64-pin
On-chip UART, capable of operating at a low voltage (1.8 V).
42/44-pin
Inverter control
64-pin
64-pin
An A/D converter of the µPD780924 was enhanced.
PD780964
µ
On-chip inverter control circuit and UART, EMI noise reduction version.
PD780924
µ
FIPTM drive
The I/O and FIP C/D of theµPD78044F were enhanced, Display output total: 53
The I/O and FIP C/D of theµPD78044H were enhanced, Display output total: 48
100-pin
100-pin
80-pin
PD780208
PD780228
PD78044H
µ
µ
µ
78K/0
Series
µ
N-ch open drain input/output was added to the PD78044F, Display output total: 34
80-pin
PD78044F
µ
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
100-pin
100-pin
PD780308
PD78064B
µ
PD780308Y
PD78064Y
µ
µ
SIO of the µPD78064 was enhanced, and ROM and RAM were expanded.
EMI noise reduced version of the µPD78064.
µ
µ
PD78064
Basic subseries for driving LCDs, On-chip UART.
IEBusTM supported
µPD78098B
80-pin
80-pin
EMI noise reduction version of the µPD78098.
An IEBus controller was added to the µPD78054.
µPD78098
Meter control
80-pin
64-pin
µPD780973
On-chip automobile meter driving controller/driver.
LV
µPD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter.
Note Under planning
3
µPD78062(A), 78063(A), 78064(A)
The following table shows the differences among subseries functions.
Function
Timer
ROM
8-bit 10-bit 8-bit
A/D A/D D/A
VDD MIN.
Value
External
Serial Interface
I/O
88
Capacity
Expansion
Subseries Name
8-bit 16-bit Watch WDT
Control µPD78075B 32 K to 40 K 4ch 1ch 1ch 1ch 8ch
–
2ch 3ch (UART: 1ch)
1.8 V Available
µPD78078
48 K to 60 K
–
µPD78070A
61
2.7 V
1.8 V
2.7 V
2.0 V
1.8 V
µPD780058 24 K to 60 K 2ch
µPD78058F 48 K to 60 K
2ch 3ch (time division UART: 1ch) 68
3ch (UART: 1ch)
69
51
53
µPD78054
16 K to 60 K
µPD780034 8 K to 32 K
µPD780024
–
8ch
–
–
3ch (UART: 1ch,
time division 3-wire: 1ch)
8ch
µPD78014H
2ch
µPD78018F 8 K to 60 K
µPD78014
8 K to 32 K
2.7 V
µPD780001 8 K
–
–
1ch
–
1ch
39
53
33
47
–
µPD78002
µPD78083
8 K to 16 K
–
Available
8ch
–
1ch (UART: 1ch)
2ch (UART: 2ch)
1.8 V
–
Inverter µPD780964 8 K to 32 K 3ch Note
–
1ch
8ch
–
–
–
2.7 V Available
control
µPD780924
8ch
FIP
µPD780208 32 K to 60 K 2ch 1ch 1ch 1ch 8ch
µPD780228 48 K to 60 K 3ch
–
2ch
1ch
74
72
68
2.7 V
4.5 V
2.7 V
–
–
drive
–
–
µPD78044H 32 K to 48 K 2ch 1ch 1ch
µPD78044F 16 K to 40 K
2ch
LCD
drive
µPD780308 48 K to 60 K 2ch 1ch 1ch 1ch 8ch
µPD78064B 32 K
–
–
–
3ch (time division UART: 1ch) 57
2ch (UART: 1ch)
2.0 V
µPD78064
16 K to 32 K
IEBus
µPD78098B 40 K to 60 K 2ch 1ch 1ch 1ch 8ch
2ch 3ch (UART: 1ch)
69
2.7 V Available
supported
µPD78098
32 K to 60 K
Meter control µPD780973 24 K to 32 K 3ch 1ch 1ch 1ch 5ch
–
–
–
–
2ch (UART: 1ch)
2ch
56
54
4.5 V
–
LV
µPD78P0914 32 K
6ch
–
–
1ch 8ch
4.5 V Available
Note 10-bit timer: 1 channel
4
µPD78062(A), 78063(A), 78064(A)
FUNCTIONAL OUTLINE
Product Name
µPD78063(A)
µPD78064(A)
µPD78062(A)
Item
ROM
16K bytes
512 bytes
24K bytes
32K bytes
Internal
memory
High-speed RAM
LCD display RAM
1024 bytes
40 × 4 bits
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
General registers
Minimum instruction execution time
On-chip minimum instruction execution time cycle modification function
When main system clock
selected
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz operation)
When subsystem clock
selected
122 µs (at 32.768 kHz operation)
• 16-bit operation
• Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)
Instruction set
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
I/O ports
Total
:
:
:
57
02
55
(including segment signal output pins)
• CMOS input
• CMOS I/O
• 8-bit resolution × 8 channels
A/D converter
• Segment signal output : Maximum 40
• Common signal output : Maximum 4
LCD controller/driver
• Bias
: 1/2 or 1/3 switchable
• 3-wire serial I/O/SBI/2-wire serial I/O mode selectable
• 3-wire serial I/O/UART mode selectable
: 1 channel
: 1 channel
Serial interface
Timer
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watch timer
:
:
:
:
1 channel
2 channels
1 channel
1 channel
• Watchdog timer
Timer output
Clock output
Buzzer output
3 (14-bit PWM output capability : 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,
5.0 MHz (at main system clock 5.0 MHz operation)
32.768 kHz (at subsystem clock 32.768 kHz operation)
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 5.0 MHz operation)
Internal : 12, external :
6
Maskable
Vectored
Non-maskable
interrupt
sources
Internal :
1
1
Softwar
Test input
Internal: 1, external: 1
VDD = 2.0 to 6.0 V
Supply voltage
• 100-pin plastic QFP (Fine pitch) (14 × 14 mm, resin thickness: 1.45 mm)
• 100-pin plastic QFP (14 × 20 mm)
Package
•
100-pin plastic LQFP (Fine pitch) (14 × 14 mm, resin thickness: 1.40 mm, under planning)
5
µPD78062(A), 78063(A), 78064(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ........................................................................................................
7
2. BLOCK DIAGRAM ................................................................................................................................... 10
3. PIN FUNCTIONS ...................................................................................................................................... 11
3.1 Port Pins .......................................................................................................................................................... 11
3.2 Other Pins ........................................................................................................................................................ 13
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 14
4. MEMORY SPACE ..................................................................................................................................... 18
5. PERIPHERAL HARDWARE FUNCTION FEATURE ............................................................................... 19
5.1 Port ................................................................................................................................................................... 19
5.2 Clock Generator .............................................................................................................................................. 20
5.3 Timer/Event Counter ....................................................................................................................................... 20
5.4 Clock Output Control Circuit ......................................................................................................................... 23
5.5 Buzzer Output Control Circuit ....................................................................................................................... 23
5.6 A/D Converter .................................................................................................................................................. 24
5.7 Serial Interface ............................................................................................................................................... 24
5.8 LCD Controller/Driver ..................................................................................................................................... 26
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS............................................................................... 27
6.1 Interrupt Functions ......................................................................................................................................... 27
6.2 Test Functions ................................................................................................................................................. 31
7. STANDBY FUNCTION ............................................................................................................................. 32
8. RESET FUNCTION .................................................................................................................................. 32
9. INSTRUCTION SET ................................................................................................................................. 33
10. ELECTRICAL SPECIFICATIONS ............................................................................................................ 35
11. CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 56
12. PACKAGE DRAWINGS ........................................................................................................................... 58
13. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 61
APPENDIX A. DEVELOPMENT TOOLS ....................................................................................................... 62
APPENDIX B. RELATED DOCUMENTS ....................................................................................................... 64
6
µPD78062(A), 78063(A), 78064(A)
1. PIN CONFIGURATION (TOP VIEW)
• 100-pin plastic QFP (fine pitch)(14 × 14 mm, resin thickness: 1.45 mm)
µPD78062GC(A)-×××-7EA, 78063GC(A)-×××-7EA, 78064GC(A)-×××-7EA
• 100-pin plastic LQFP (fine pitch)(14 × 14 mm, resin thickness: 1.40 mm)
µPD78062GC(A)-×××-8EUNote, 78063GC(A)-×××-8EUNote, 78064GC(A)-×××-8EUNote
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P70/SI2/R
X
D
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
1
2
3
4
5
6
75
74
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P80/S39
73
72
71
70
69
68
67
66
65
64
63
62
61
P81/S38
P82/S37
P83/S36
7
8
P17/ANI7
AVDD
P84/S35
P85/S34
P86/S33
P87/S32
P90/S31
9
AVREF
P100
P101
10
11
12
13
14
15
16
17
18
VSS
P102
P103
P91/S30
P92/S29
P93/S28
P94/S27
P95/S26
P96/S25
P97/S24
S23
P30/TO0
P31/TO1
P32/TO2
60
59
58
P33/TI1
P34/TI2
57
56
55
19
20
P35/PCL
P36/BUZ
P37
21
S22
54
53
52
51
22
23
24
25
S21
COM0
COM1
S20
S19
COM2
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
26 27
Note Under planning
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS
2. Connect the AVDD pin to VDD
3. Connect the AVSS pin to VSS
.
.
.
7
µPD78062(A), 78063(A), 78064(A)
• 100-pin plastic QFP (14 × 20 mm)
µPD78062GF(A)-×××-3BA, 78063GF(A)-×××-3BA
µPD78064G(A)-×××-3BA
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
S20
P26/SO0/SB1
P27/SCK0
1
2
3
4
5
6
80
79
S19
S18
78
77
76
75
74
73
72
71
70
69
68
67
66
P70/SI2/RXD
P71/SO2/TXD
P72/SCK2/ASCK
IC
S17
S16
S15
S14
7
8
X2
X1
S13
S12
S11
S10
S9
9
V
DD
10
11
12
13
14
15
16
17
18
XT1/P07
XT2
RESET
S8
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
S7
S6
S5
P4
65
64
63
S3
S2
S1
S0
P05/INTP5
P110
62
61
60
19
20
P111
P112
P113
21
22
23
VSS
59
58
57
56
55
54
V
V
LC2
LC1
P114
P115
24
25
VLC0
P116
P117
BIAS
26
27
28
COM3
COM2
AVSS
53
52
51
P10/ANI0
29
30
COM1
COM0
P11/ANI1
P12/ANI2
31
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
32
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS
2. Connect the AVDD pin to VDD
3. Connect the AVSS pin to VSS
.
.
.
8
µPD78062(A), 78063(A), 78064(A)
ANI0-ANI7
ASCK
AVDD
: Analog Input
P110-P117 : Port11
: Asynchronous Serial Clock
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
PCL
: Programmable Clock
: Reset
RESET
RXD
AVREF
AVss
: Receive Data
: Segment Output
: Serial Bus
S0-S39
SB0-SB1
SI0, SI2
SO0, SO2
BIAS
: LCD Power Supply Bias Control
: Buzzer Clock
BUZ
: Serial Input
COM0-COM3 : Common Output
IC : Internally Connected
: Serial Output
SCK0, SCK2 : Serial Clock
INTP0-INTP5 : Interrupt from Peripherals
P00-P05, P07 : port0
TI00, TI01
TI1, TI2
TO0-TO2
TXD
: Timer Input
: Timer Input
P10-P17
P25-P27
P30-P37
P70-P72
P80-P87
P90-P97
P100-P103
: Port1
: Port2
: Port3
: Port7
: Port8
: Port9
: Port10
: Timer Output
: Transmit Data
VDD
: Power Supply
VLC0-VLC2
VSS
: LCD Power Supply
: Ground
X1, X2
XT1, XT2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
9
µPD78062(A), 78063(A), 78064(A)
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
P00
16-bit TIMER/
EVENT COUNTER
PORT0
P01-P05
P07
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
PORT1
PORT2
PORT3
PORT7
PORT8
PORT9
PORT10
PORT11
P10-P17
P25-P27
P30-P37
P70-P72
P80-P87
P90-P97
P100-P103
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
78K/0
CPU CORE
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
ROM
SERIAL
INTERFACE 0
SI2/RxD/P70
SO2/TxD/P71
SERIAL
INTERFACE 2
P110-P117
S0-S23
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
S24/P97-
S31/P90
RAM
AVDD
AVSS
A/D CONVERTER
S32/P87-
S39/P80
LCD
CONTROLLER/
DRIVER
AVREF
COM0-COM3
V
LC0-VLC2
INTP0/P00-
INTP5/P05
INTERRUPT
CONTROL
BIAS
f
LCD
BUZ/P36
PCL/P35
BUZZER OUTPUT
RESET
X1
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
X2
VDD
V
SS
IC
XT1/P07
XT2
Remark The internal ROM and RAM capacities differ depending on the product.
10
µPD78062(A), 78063(A), 78064(A)
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Dual-
Pin Name
I/O
Input
Function
Input only
After Reset
Input
Function Pin
INTP0/TI00
INTP1/TI01
INTP2
P00
P01
P02
Port 0
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up
resistor can be used in software.
Input/
7-bit I/O port.
Input
INTP3
P03
output
INTP4
P04
INTP5
P05
P07Note1
Input only
Input
Input
Input
XT1
Port 1
8-bit input/output port.
Input/
ANI0 to
ANI7
P10 to P17
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.Note2
output
Port 2
P25
P26
P27
SI0/SB0
SO0/SB1
SCK0
3-bit input/output port.
Input/
Input
Input
Input
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
output
P30
P31
P32
P33
P34
P35
P36
P37
P70
P71
TO0
TO1
Port 3
TO2
8-bit input/output port.
TI1
Input/
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
output
TI2
PCL
BUZ
——
Port 7
SI2/RxD
SO2/TxD
3-bit input/output port.
Input/
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
output
SCK2/
ASCK
P72
Notes 1. When using the P07/XT1 pins as an input port, set (1) bit 6 (FRC) of the processor clock control register (PCC)
(the on-chip feedback resistor of the subsystem clock oscillator should not be used).
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, port 1 is set to input mode.
However, on-chip pull-up resistor is not automatically used.
11
µPD78062(A), 78063(A), 78064(A)
3.1 Port Pins (2/2)
Dual-
Function
Pin Name
I/O
After Reset
Function Pin
Port 8
8-bit input/output port
Input/output can be specified bit-wise.
Input/
Input
S39 to S32
P80 to P87
When used as an input port , on-chip pull-up resistor can be used in
software.
output
Input/output port/segment signal output function can be specified in 2-bit
unit by the LCD control register (LCDC).
Port 9
8-bit input/output port
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
Input/
P90 to P97
Input
S31 to S24
output
Input/output port/segment signal output function can be specified in 2-bit
unit by the LCD control register (LCDC).
Port 10
4-bit input/output port
Input/
P100 to
P103
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
Input
output
LED direct drive capability.
Port 11
8-bit input/output port
Input/
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used in
software.
P110 to
P117
Input
output
Falling edge detection capability.
12
µPD78062(A), 78063(A), 78064(A)
3.2 Other Pins (1/2)
Dual-
Function
After Reset
Pin Name
I/O
Function Pin
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
SI0
P00/TI00
P01/TI01
External interrupt request input by which the effective edge (rising
edge, falling edge, or both rising edge and falling edge) can be
specified.
P02
P03
Input
Input
P04
P05
P25/SB0
P70/RxD
P26/SB1
P71/TxD
P25/SI0
P26/SO0
P27
Input
Serial interface serial data input.
Input
SI2
SO0
Output
Serial interface serial data output.
Serial interface serial data input/output.
Serial interface serial clock input/output.
Input
Input
Input
SO2
SB0
Input
/output
SB1
SCK0
SCK2
RxD
Input
/output
P72/ASCK
P70/SI2
P71/SO2
P72/SCK2
P00/INTP0
P01/INTP1
P33
Input
Input
Input
Asynchronous serial interface serial data input.
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input.
External count clock input to 16-bit timer (TM0).
Capture trigger signal input to capture register (CR00).
External count clock input to 8-bit timer (TM1).
External count clock input to 8-bit timer (TM2).
16-bit timer (TM0) output (shared with 14-bit PWM output).
8-bit timer (TM1) output.
Input
TxD
Output
Input
ASCK
TI00
TI01
Input
Input
Input
TI1
TI2
P34
TO0
P30
Output
TO1
P31
8-bit timer (TM2) output.
TO2
P32
Output
Output
Clock output (for main system clock, subsystem clock trimming).
Buzzer output.
Input
PCL
P35
BUZ
Input
P36
S0 to S23
S24 to S31
S32 to S39
COM0 to COM3
VLC0 to VLC2
BIAS
Output
Output
Output
LCD controller/driver segment signal output.
P97 to P90
P87 to P80
Input
LCD controller/driver common signal output.
LCD drive voltage. Split resistors can be incorporated by mask option.
LCD drive power supply.
Output
13
µPD78062(A), 78063(A), 78064(A)
3.2 Other Pins (2/2)
Dual-
Function Pin
After Reset
Pin Name
I/O
Input
Function
Input
——
——
——
——
——
——
Input
——
——
——
——
P10 to P17
——
ANI0 to ANI7
AVREF
AVDD
AVSS
RESET
X1
A/D converter analog input.
Input
A/D converter reference voltage input.
A/D converter analog power supply. Connect to VDD.
A/D converter ground potential. Connect to VSS.
System reset input.
——
——
——
Input
Input
——
Main system clock oscillation crystal connection.
Subsystem clock oscillation crystal connection.
——
X2
P07
XT1
Input
——
XT2
——
VDD
Positive power supply.
——
VSS
Ground potential.
——
IC
Internal connection. Connect directly to VSS pin.
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/output
Circuit Type
Pin Name
I/O
Recommended Connection when not Used
Connected to VSS .
2
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
Input
Input/output
Input
Independently connected to VSS through resistor.
8-A
P03/INTP3
P04/INTP4
P05/INTP5
16
11
Connected to VDD .
P07/XT1
P10/ANI0 to P17/ANI7
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
Input/output
Independently connected to VDD or VSS through resistor.
10-A
5-A
P31/TO1
P32/TO2
14
µPD78062(A), 78063(A), 78064(A)
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/output
Circuit Type
Pin Name
P33/TI1
I/O
Recommended Connection when not Used
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
8-A
5-A
8-A
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
Independently connected to VDD or VSS through resistor.
Input/output
P80/S39 to P87/S32
P90/S31 to P97/S24
P100 to P103
17-A
5-A
8-A
Independently connected to VDD through resistor.
P110 to P117
17
18
S0 to S23
COM0 to COM3
VLC0 to VLC2
BIAS
Output
Leave open.
——
——
Input
2
——
RESET
XT2
16
Leave open.
Connected to VSS .
AVREF
——
Connected to VDD .
AVDD
——
Connected to VSS .
AVSS
Connected directly to VSS .
IC
15
µPD78062(A), 78063(A), 78064(A)
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 10-A
Type 2
V
DD
pull-up
enable
P-ch
VDD
IN
data
P-ch
IN/OUT
open drain
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
Type 11
Type 5-A
VDD
VDD
pull-up
enable
pull-up
enable
P-ch
P-ch
VDD
data
P-ch
N-ch
V
DD
IN/OUT
data
P-ch
output
disable
IN/OUT
P-ch
output
disable
Comparator
N-ch
+
–
N-ch
REF (Threshold Voltage)
V
input
enable
input
enable
Type 16
Type 8-A
VDD
feedback cut-off
P-ch
pull-up
enable
P-ch
VDD
data
P-ch
IN/OUT
output
disable
N-ch
XT1
XT2
16
µPD78062(A), 78063(A), 78064(A)
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 17-A
Type 17
V
LC0
LC1
V
DD
P-ch
N-ch
V
pull-up
enable
P-ch
N-ch
P-ch
V
DD
SEG
data
OUT
data
P-ch
P-ch
N-ch
IN/OUT
V
LC2
output
disable
N-ch
input
enable
V
V
LC0
LC1
Type 18
P-ch
N-ch
V
V
LC0
LC1
P-ch
N-ch
P-ch
N-ch
SEG
data
N-ch
P-ch
P-ch
N-ch
P-ch
N-ch
OUT
V
LC2
COM
data
P-ch
N-ch
V
LC2
17
µPD78062(A), 78063(A), 78064(A)
4. MEMORY SPACE
The memory map of µPD78062(A)/78063(A)/78064(A) is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special Function Register (SFR)
256 × 8 Bits
FF00H
FEFFH
General Registers
32 8 Bits
×
FEE0H
Internal High-Speed RAMNote
mmmmH
nnnnH
mmmmH-1
Program Area
Data Memory
Space
Use Prohibited
1000H
0FFFH
FA80H
FA7FH
CALLF Entry Area
LCD Display RAM
40
× 4 Bits
0800H
07FFH
FA58H
FA57H
Program Area
0080H
007FH
Use Prohibited
nnnnH+1
nnnnH
CALLT Table Area
Vector Table Area
0040H
003FH
Program
Memory
Space
Internal ROMNote
0000H
0000H
Note The Internal ROM and Internal High-Speed RAM capacities differ depending on the product. (refer to the following
table.)
Last Address of Internal ROM
nnnnH
Start Address of Internal High-Speed RAM
mmmmH
Product Name
µPD78062(A)
µPD78063(A)
µPD78064(A)
3FFFH
5FFFH
7FFFH
FD00H
FB00H
18
µPD78062(A), 78063(A), 78064(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURE
5.1 Port
There are two kinds of I/O port.
• CMOS input (P00, P07)
: 2
• CMOS input/output (P01 to P05, Port 1 to 3, 7 to 11)
: 55
: 57
Total
Table 5-1. Functions of Ports
Name
Port 0
Pin Name
P00, P07
Function
Dedicated input port
4
Input/output port. Input/output specifiable bit-wise.
P01 to P05
When used as input port, on-chip pull-up resistor can be used in software .
Input/output port. Input/output specifialbe bit-wise.
P10 to P17
P25 to P27
P30 to P37
P70 to P72
Port 1
Port 2
Port 3
Port 7
When used as input port, on-chip pull-up resistor can be used in software .
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software .
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
P80 to P87
P90 to P97
Port 8
Port 9
Input/output port/segment signal output function specifiable in 2-bit units by LCD control
register (LCDC).
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
Input/output port/segment signal output function specifiable in 2-bit units by LCD control
register (LCDC).
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
Direct LED drive capability.
Port 10
Port 11
P100 to P103
P110 to P117
Input/output port. Input/output specifiable bit-wise.
When used as input port, on-chip pull-up resistor can be used in software.
Test flag (KRIF) is set to 1 by falling edge detection.
19
µPD78062(A), 78063(A), 78064(A)
5.2
Clock Generator
There are two kinds of clocks, main system clock and subsystem clock.
The minimum instruction execution time can also be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (main system clock: in 5.0 MHz operation)
• 122 µs (subsystem clock: in 32.768 kHz operation)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
Subsystem
Clock
Oscillator
fXT
Watch Timer
Clock Output Function
XT2
Prescaler
Main
System
Clock
X1
X2
fX
Selec-
tor
Prescaler
Clock to
Peripheral
Hardware
f
XX
Oscillator
1/2
Scaler
f
2
X
f
2
XX
f
XX
f
XX
f
XX
f
2
XT
22 23 24
STOP
CPU
Clock
Standby
Control
Circuit
Selec-
tor
(fCPU
)
To INTP0
Sampling Clock
5.3 Timer/Event Counter
Five timer/event counter channels are incorporated.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter
• Watch timer
: 2 channels
: 1 channel
: 1 channel
• Watchdog timer
Table 5-2. Timer/Event Counter Types and Functions
16-bit Timer/
Event Counter
8-bit Timer/
Event Counter
Watch Timer
Watchdog Timer
Interval timer
1 channel
1 channel
1 output
1 output
2 inputs
1 output
1 output
2 channels
1 channel
1 channel
Type
External event counter
2 channels
–
–
–
–
–
–
–
–
–
–
–
–
Timer output
PWM output
2 outputs
–
Pulse width measurement
Function
–
2 outputs
–
Square wave output
One-shot pulse output
Interrupt request
Test input
2
–
2
–
2
1
–
1 input
20
µPD78062(A), 78063(A), 78064(A)
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal Bus
INTP1
TI01/P01/INTP1
16-Bit
Capture/Compare
Register (CR00)
Selec-
tor
INTTM00
PWM
Pulse
Output
Control
Circuit
Output
Control Circuit
Match
TO0/P30
Watch Timer Output
2fXX
f
XX
XX/2
XX/22
TI00/P00/INTP0
16-Bit
Timer Register
(TM0)
Selec-
tor
f
4
f
Clear
Selector
Edge
Detector
Match
INTTM01
INTP0
16-Bit
Capture/Compare
Register
(CR01)
Internal Bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-Bit
Compare
Register (CR10)
8-Bit
Compare Register
(CR20)
Output
Control
Circuit
Selec-
tor
TO2/P32
INTTM2
Match
Match
f
XX/2-fXX/29
XX/211
8-Bit
Timer Register 1
(TM1)
Selec-
tor
f
8-Bit
Selec-
tor
Timer Register 2
(TM2)
TI1/P33
Clear
Clear
f
XX/2-fXX/29
Selector
Selec-
tor
f
XX/211
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
21
µPD78062(A), 78063(A), 78064(A)
Figure 5-4. Watch Timer Block Diagram
f
W
214
5-Bit Counter
Selector
f
XX/27
f
W
Selec-
tor
INTWT
Selector
Prescaler
f
XT
f
W
213
f
W
24
f
W
25
f
W
26
f
W
27
f
W
28
fW
29
INTTM3
Selector
To 16-Bit
Timer/Event Counter
To LCD
Controller/Driver
Figure 5-5. Watchdog Timer Block Diagram
f
XX
23
Prescaler
f
XX
24
f
XX
25
f
XX
26
f
XX
27
f
XX
28
f
XX
29
fXX
211
INTWDT
Maskable
Interrupt
Request
Control
Circuit
RESET
8-Bit Counter
Selector
INTWDT
Non-Maskable
Interrupt
Request
22
µPD78062(A), 78063(A), 78064(A)
5.4 Clock Output Control Circuit
Clocks of the following frequency can be output as clock outputs.
• 19.5 kHz/39.1kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: in 5.0
kHz operation)
• 32.768 kHz (subsystem clock: in 32.768 kHz operation)
Figure 5-6. Clock Output Circuit Block Diagram
f
XX
f
XX/2
f
f
f
XX/22
XX/23
XX/24
Synchronization
Circuit
Output Control Circuit
Selector
PCL/P35
f
XX/25
XX/26
XX/27
f
f
f
XT
4
5.5 Buzzer Output Control Circuit
Clocks of the following frequency can be output as buzzer outputs.
• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock : in 5.0 MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f
XX/29
XX/210
XX/211
BUZ/P36
Selector
Output Control Circuit
f
f
23
µPD78062(A), 78063(A), 78064(A)
5.6 A/D Converter
Eight 8-bit resolution A/D converter channels are incorporated.
The following two types of start-up method are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AVDD
ANI0/P10
AVREF
Sample & Hold Circuit
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Voltage Comparator
Tap
Selec-
tor
Selec-
tor
AVSS
Successive Approximation
Register (SAR)
Edge
Detector
Control
Circuit
INTP3/P03
INTAD
INTP3
A/D Conversion Result
Register (ADCR)
Internal Bus
5.7 Serial Interface
Two clocked serial interface channels are incorporated.
• Serial interface channel 0
• Serial interface channel 2
Table 5-3. Serial Interface Channel Block Diagram
Function
Serial Interface Channel 0
(MSB/LSB-first switchable)
(MSB-first)
Serial Interface Channel 2
3-wire serial I/O mode
SBI (serial bus interface) mode
2-wire serial I/O mode
(MSB/LSB-first switchable)
——
——
(MSB-first)
Asynchronous serial interface
(UART) mode
(Dedicated baud rate generator
incorpoorated)
——
24
µPD78062(A), 78063(A), 78064(A)
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
SO0/SB1/P26
Serial I/O
Shift Register 0 (SIO0)
Output
Latch
Selector
Selector
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detector
Interrupt Request
Signal Generator
INTCSI0
SCK0/P27
Serial Clock Counter
4
f
XX/2-fXX/28
Serial Clock Control Circuit
Selector
TO2
Figure 5-10. Serial Interface Channel 2 Block Diagram
Internal bus
Receive Buffer
Register (RXB/SIO2)
Direction
Control Circuit
Direction
Control Circuit
Transmit Shift
Register (TXS/SIO2)
Receive Shift
Register (RXS)
Transmit
Control Circuit
RX
D/SI2/P70
INTST
TXD/SO2/P71
INTSER
INTSR/INTCSI2
Receive
Control Circuit
SCK Output
Control Circuit
ASCK/SCK2/P72
Baud Rate
Generator
f
XX-fXX/210
25
µPD78062(A), 78063(A), 78064(A)
5.8
LCD Controller/Driver
An LCD controller/driver with the following functions is incorporated.
• Selection of 5 types of display mode
• 16 of the segment signal of outputs can be switched to input/output ports in units of 2.
(P80/S39 to P87/S32, P90/S31 to P97/S24)
Table 5-4. Display Mode Types and Maximum Number of Display Pixels
Bias Method
——
Time Multiplexing
Common Signal Used
Maximum Number of Display Pixels
Static
COM0 (COM1 to COM3)
COM0, COM1
40 (40 segments × 1 common)
80 (40 segments × 2 commons)
2
3
3
4
1/2
1/3
COM0 to COM2
COM0 to COM2
COM0 to COM3
120 (40 segments × 3 commons)
160 (40 segments × 4 commons)
Figure 5-11. LCD Controller/Driver Block Diagram
Internal Bus
f
W
26
Prescaler
Display
Data Memory
f
W
29
f
W
28
fW
27
LCDCL
Timing Controller
Selector
Segment
Data Selector
Port
Output Data
LCD Drive Voltage
Generator
Common Driver
Segment Driver
S0
S23 S24/P97
S39/P80
COM0 COM1 COM2 COM3
V
LC2
VLC1
VLC0 BIAS
26
µPD78062(A), 78063(A), 78064(A)
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
The following three types, 20 sources of interrupt functions are available:
• Non-maskable : 1
• Maskable
• Software
: 18
: 1
27
µPD78062(A), 78063(A), 78064(A)
Table 6-1. Interrupt Source List
Vector
Table
Address
Basic Con-
figuration
Type Note2
Interrupt Source
Trigger
Interrupt
Type
Default
Priority Note1
Internal/
External
Name
Watchdog timer overflow (with watchdog timer
mode 1 selected)
Non-
maskable
——
0
INTWDT
(A)
Internal
0004H
Watchdog timer overflow (with interval timer
mode selected)
INTWDT
(B)
(C)
1
2
3
4
5
6
7
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTCSI0
0006H
0008H
000AH
000CH
000EH
0010H
0014H
Pin input edge detection
External
(D)
Serial interface channel 0 transfer termination
Serial interface channel 2 UART reception
error generation
8
INTSER
INTSR
0018H
Serial interface channel 2 UART reception
termination
Maskable
9
001AH
Serial interface channel 2 3-wire transfer
termination
INTCSI2
INTST
Serial interface channel 2 UART transmission
termination
10
11
12
13
14
15
001CH
001EH
0020H
0022H
0024H
0026H
Reference time interval signal from watch
timer
INTTM3
INTTM00
INTTM01
INTTM1
INTTM2
(B)
Internal
16-bit timer register and capture/compare
register (CR00) match signal generation
16-bit timer register and capture/compare
register (CR01) match signal generation
8-bit timer/event counter 1 match signal
generation
8-bit timer/event counter 2 match signal
generation
16
A/D converter conversion termination
BRK instruction execution
0028H
003EH
INTAD
BRK
Software
——
(E)
——
Notes 1. Default priority is a priority order when more than one maskable interrupt request is generated simultaneously.
0 is the highest and 16 the lowest.
2. Basic configuration types (A) to (E) correspond to those shown in Figure 6-1.
28
µPD78062(A), 78063(A), 78064(A)
Figure 6-1. Basic Configuration of Interrupt Functions (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Priority
Control
Circuit
Vector Table
Interrupt
Request
Address
Generator
Standby Release
Signal
(B) Intrnal maskable interrupt
Internal Bus
IE
MK
PR
ISP
Priority
Control
Circuit
Vector Table
Address
Generator
Interrupt
Request
IF
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
MK
IE
PR
ISP
Priority
Control
Circuit
Vector Table
Address
Generator
Interrupt
Request
Sampling
Clock
Edge
Detector
IF
Standby
Release
Signal
29
µPD78062(A), 78063(A), 78064(A)
Figure 6-1. Basic Configuration of Interrupt Functions (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
MK
IE
PR
ISP
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
IF
Standby
Release
Signal
(E) Software interrupt
Internal Bus
Priority
Control
Circuit
Vector Table
Address
Generator
Interrupt
Request
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
30
µPD78062(A), 78063(A), 78064(A)
6.2 Test Functions
There are two sources of test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Trigger
Internal/External
Name
INTWT
INTPT11
Watch timer overflow
Internal
External
Port 11 falling edge detection
Figure 6-2. Basic Configuration of Test Function
Internal Bus
MK
Standby Release
Signal
Test Input
Signal
IF
IF : Test input flag
MK : Test mask flag
31
µPD78062(A), 78063(A), 78064(A)
7. STANDBY FUNCTION
The standby function is a function to reduce the consumption current and there are the following two kinds of standby
functions.
●
HALT mode : Halts CPU operating clock and can reduce average consumption current by the intermittent operation
along with the normal operation.
●
STOP mode : Halts main system clock oscillation. Halts all operations with the main system clock and sets ultra-low
consumption current state with subsystem clock only.
Figure 7-1. Standby Function
CSS=1
Main System Clock Operation
Subsystem Clock OperationNote
CSS=0
HALT Instruction
STOP
Instruction
HALT Instruction
HALT ModeNote
Interrupt
Request
Interrupt
Request
Interrupt
Request
STOP Mode
Main System Clock
Oscillation Halted
HALT Mode
Clock Supply to CPU Halted,
Clock Supply to CPU Halted,
(
)
(
)
(
)
Oscillation Maintained
Oscillation Maintained
Note Halting the main system clock enables the consumption current to be reduced.
When the CPU is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (MCC)
of the processor clock control register (PCC).
The STOP instruction is not available.
Caution When the main system clock is stopped and the system is operated by the subsystem clock, the main
system clock should be returned to after securing the oscillation stabilization time in software.
8. RESET FUNCTION
There are the following two kinds of resetting methods.
• External reset by RESET pin.
• Internal reset by watchdog timer hung-up time detection.
32
µPD78062(A), 78063(A), 78064(A)
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBS, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,
ROR4, ROL4, PUSH, POP, DBNZ
[HL+byte]
[HL+B]
[HL+C]
2nd operand
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
1st operand
A
MOV
MOV
MOV
XCH
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ROL
ADD
ADD
RORC
ROLC
ADDC
ADDC
ADDC ADDC
SUB
SUB
SUBC SUBC
SUB
SUB
SUBC
SUBC
AND
AND
AND
OR
AND
OR
XOR
CMP
OR
OR
XOR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
CMP
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
B, C
sfr
DBNZ
DBNZ
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
saddr
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
[HL+C]
X
MOV
MULU
C
DIVUW
Note Except r = A
33
µPD78062(A), 78063(A), 78064(A)
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd operand
#word
AX
rpNote
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
1st operand
A
ADDW
SUBW
CMPW
MOVW
MOVW
MOVW
XCHW
MOVW
rp
MOVWNote
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp=BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd operand
A.bit
sfr.bit
saddr.bit
PSW.bits
[HL].bit
CY
$addr16
None
1st operand
A.bit
BT
SET1
CLR1
MOV1
BF
BTCLR
BT
SET1
CLR1
sfr.bit
MOV1
MOV1
MOV1
MOV1
BF
BTCLR
BT
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
AND1
OR1
SET1
CLR1
NOT1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
(4) Call instruction/branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DNZB
2nd Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
BR
CALL
BR
BR, BC, BNC,
BZ, BNZ
Compound
Instruction
BT, BF,
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
34
µPD78062(A), 78063(A), 78064(A)
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Test Conditions
Rating
Unit
V
VDD
–0.3 to +7.0
AVDD
AVREF
AVSS
VI
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
V
V
V
V
Supply voltage
Input voltage
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF + 0.3
–10
VO
Output voltage
Analog input voltage
VAN
V
P10 to P17
1 pin
Analog input pin
mA
Total for P00 to P05, P07, P10 to P17, P100,
P101 & P110 to P117
mA
mA
–15
–15
Output current high
IOH
Total for P25 to P27, P30 to P37, P70 to P72, P80
to P87, P90 to P97, P102 & P103
30
15
mA
mA
mA
mA
mA
mA
mA
mA
Peak value
1 pin
rms value
100
70
Total for P00 to P05, P10 to
Peak value
P17, P100, P101 & P110 to
P117
rms value
Note
Output current low
IOL
100
70
Peak value
Total for P30 to P37, P102 &
P103
rms value
50
Peak value
rms value
Total for P25 to P27, P70 to
P72, P80 to P87 & P90 to P97
20
Operating ambient
temperature
TA
–40 to +85
°C
°C
Tstg
–65 to +150
Storage temperature
Note The rms value should be calculated as follows: [rms value] = [Peak value] × Duty
√
Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the
absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is, the
absolute maximum rating is a rating value which may cause a product to be damaged physically. The
absolute maximum rating values must therefore be observed in using the product.
Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins.
35
µµPD78062(A), 78063(A), 78064(A)
Permissible Inrush Current Characteristics of Pins on Application of Overvoltage (TA = –40 to +85 °C, VDD = 2.0
to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
5.00
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Positive inrush current
(VIN > VDD)
IIJH1
1 pin
Input ports other than
ANIn (n = 0 to 7)
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
Peak value
Mean value
0.50
Note 1
IIJH2
IIJH3
IIJH4
IIJL1
IIJL2
IIJL3
IIJL4
ANIn (n = 0 to 7)
1.50
0.15
Total of Input ports other than
all input ANIn (n = 0 to 7)
pins
40.0
4.00
Note 2
ANIn (n = 0 to 7)
1.50
0.15
Negative inrush current
(VIN < VSS)
1 pin
Input ports other than
ANIn (n = 0 to 7)
–0.50
–0.05
–0.50
–0.05
–4.00
–0.40
–1.50
–0.15
Note 1
ANIn (n = 0 to 7)
Total of Input ports other than
all input ANIn (n = 0 to 7)
pins
Note 2
ANIn (n = 0 to 7)
Notes 1. If an inrush current flows to one analog input pin (ANIn: n = 0 to 7), the A/D conversion result of the analog
input pin is the value when the inrush current does not flow ±2 LSB.
2. If an inrush current flows to two or more analog input pins (ANIn: n = 0 to 7), the A/D conversion result of
the analog input pin is the value when the inrush current does not flow ±4 LSB.
Remarks 1. The mean value (absolute value) of the inrush current of a pin can be calculated by the following
expression:
Mean value = ((1/T) ∫T0 | i (t) | 3/2dt)2/3
where i (t) is a pin inrush current, and the maximum value of |i (t)| is the peak value.
2. VIN is the input voltage applied to the pin.
Capacitance (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
Test Conditions
f = 1 MHz
MIN.
TYP.
MAX.
Unit
Input capacitance
Output capacitance
I/O capacitance
CIN
pF
pF
pF
15
15
15
COUT
CIO
unmeasured pins
returned to 0 V.
36
µPD78062(A), 78063(A), 78064(A)
Main System Clock Oscillator Characteristics (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Recommended
circuit
Test conditions
VDD = Oscillator
TYP.
Oscillator
Parameter
Oscillator
MIN.
1
MAX.
5
Unit
X1
IC
X2
MHz
frequency (fX) Note1
voltage range
Ceramic
oscillator
C1
C2
After VDD reaches oscil-
lator voltage range MIN.
Oscillation
stabilization time Note2
4
5
ms
X1
IC
X2
Oscillator
frequency (fX) Note1
1
MHz
ms
Crystal
C1
C2
resonator
10
30
VDD = 4.5 to 6.0 V
Oscillation
stabilization time Note2
X1 input
frequency (fX) Note1
MHz
ns
5.0
1.0
85
X2
X1
External clock
X1 input
µPD74HCU04
high/low level width
(tXH , tXL)
500
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2. If the main system clock oscillator is operated by the subsystem clock when the main system clock
is stopped, reswitching to the main system clock should be performed after the stable oscillation time
has been obtained by the program.
37
µµPD78062(A), 78063(A), 78064(A)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Recommended Circuit
Parameter
Test Conditions
MIN.
32
TYP. MAX. Unit
XT2
R2
IC
XT1
Oscillator frequency
(fXT) Note1
32.768 35
kHz
s
Crystal resonator
C4
C3
VDD = 4.5 to 6.0 V
1.2
2
Oscillation stabilization time
Note2
10
XT1 input frequency
(fXT) Note1
32
5
100
15
kHz
XT2
XT1
External clock
XT1 input high-/low-level
width (tXTH/tXTL)
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD has reached the minimum oscillation voltage range.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS.
• Do not ground it to the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
2. The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, causing misoperation by noise more frequently than the main system clock oscillation
circuit. Special care should therefore be taken to wiring method when the subsystem clock is used.
38
µPD78062(A), 78063(A), 78064(A)
Recommended Oscillator Constant
Main system clock: ceramic oscillator (TA = –40 to +85 °C)
Recommended
Circuit Constant
Oscillator
Voltage Range
Manufacturer
Frequency (MHz)
Remarks
Product Name
C1 (pF)
C2 (pF)
MIN. (V) MAX. (V)
CSA5.00MG
CST5.00MGW
EF0GC5004A4
EF0EC5004A4
EF0EN5004A4
EF0S5004B5
KBR-5.0MSA
PBRC5.00A
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
5.00
30
30
2.2
2.7
2.7
2.0
2.7
2.7
2.7
2.7
2.7
2.7
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
Murata Mfg.
Co., Ltd.
Built-in
Built-in
Built-in
33
Built-in
Built-in
Built-in
33
Lead type
Matsushita
Electronics
Components
Co., Ltd.
Round lead type
Lead type
Chip type
Built-in
33
Built-in
33
Lead type
Chip type
33
33
Kyocera
Corporation
KBR-5.0MKS
KBR-5.0MWS
Built-in
Built-in
Built-in
Built-in
Lead type
Chip type
Subsystem clock: crystal resonator (TA = –40 to +60 °C)
Recommended
Circuit Constant
Oscillator
Voltage Range
Manufacturer
Product Name
Frequency (kHz)
32.768
C3 (pF)
15
C4 (pF)
22
R2 (kΩ)
MIN. (V)
2.0
MAX. (V)
6.0
KF-38G-12P0200Note
Kyocera
220
Corporation
(Load capacitance 12 pF)
Note KF-38G-12P0200 is a maintenance product.
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation.
However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires
accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application
circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
39
µµPD78062(A), 78063(A), 78064(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
P10 to P17, P30 to P32,
MIN.
TYP.
MAX.
Unit
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0.7 VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIH1
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
P00 to P05, P25 to P27,
P33, P34, P70 to P72,
P110 to P117, RESET
0.8 VDD
0.8 VDD
VDD
VIH2
VIH3
0.85 VDD
VDD
Input voltage
high
VDD–0.5
VDD
X1, X2
VDD–0.2
VDD
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 VNote
VDD = 2.7 to 6.0 V
0.8 VDD
VDD
VIH4
0.9 VDD
VDD
XT1/P07, XT2
0.9 VDD
VDD
P10 to P17, P30 to P32,
P35 to P37, P80 to P87,
P90 to P97, P100 to P103
P00 to P05, P25 to P27,
P33, P34, P70 to P72,
P110 to P117, RESET
0
0.3 VDD
0.2 VDD
0.2 VDD
0.15 VDD
0.4
VIL1
VIL2
0
0
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0
Input voltage
low
0
VIL3
VIL4
VOH
X1, X2
0
0.2
4.5
2.7
V
V
≤ VDD ≤ 6.0 V
≤ VDD < 4.5 V
0
0.2 VDD
0.1 VDD
0.1 VDD
VDD
0
XT1/P07, XT2
2.0 V ≤ VDD < 2.7 VNote
0
VDD–1.0
VDD–0.5
VDD = 4.5 to 6.0 V, IOH = –1 mA
Output voltage
high
VDD
IOH = –100 µA
VDD = 4.5 to 6.0 V,
IOL = 15 mA
P100 to P103
0.4
2.0
0.4
V
VOL1
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P110 to P117
VDD = 4.5 to 6.0 V,
IOL = 1.6 mA
V
Output voltage
low
4.5
V ≤ VDD ≤ 6.0 V,
0.2 VDD
0.5
V
V
open-drain,
SB0, SB1, SCK0
VOL2
VOL3
pulled high (R = 1 kΩ)
IOL = 400 µA
Note When P07/XT1 is used as P07, the inverse phase of P07 should be input to XT2.
Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins.
40
µPD78062(A), 78063(A), 78064(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
P00 to P05, P10 to P17,
MIN.
TYP.
MAX.
3
Unit
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
ILIH1
µA
Input leakage
current high
VI = VDD
P110 to P117
ILIH2
X1, X2, XT1/P07, XT2
20
–3
µA
µA
P00 to P05, P10 to P17,
P25 to P27, P30 to P37,
P70 to P72, P80 to P87,
P90 to P97, P100 to P103,
ILIL1
Input leakage
current low
VI = 0 V
P110 to P117
ILIL2
X1, X2, XT1/P07, XT2
–20
3
µA
µA
Output leakage
current high
ILOH
VO = VDD
VO = 0 V
Output leakage
current low
ILOL
–3
90
µA
kΩ
VI = 0 V, P01 to P05,
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
15
20
40
P10 to P17, P25 to P27,
P30 to P37, P70 to P72,
P80 to P87, P90 to P97,
Software
R
pull-up resistor
500
kΩ
P100 to P103, P110 to P117
VDD = 5.0 V ± 10 %Note4
VDD = 3.0 V ± 10 %Note5
VDD = 2.2 V ± 10 %Note5
VDD = 5.0 V ± 10 %Note4
VDD = 3.0 V ± 10 %Note5
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
4
12
1.8
mA
mA
mA
mA
mA
mA
µA
5.00MHz, Crystaloscillation(fXX
= 2.5 MHz)Note2
operating mode
0.6
0.35
6.5
0.8
1.4
500
280
1.6
650
1.05
19.5
2.4
IDD1
5.00 MHz, Crystal oscillation
(fXX = 5.0 MHz)Note3
operating mode
Supply
currentNote1
4.2
5.00 MHz, Crystal oscillation
(fXX = 2.5 MHz)Note2
HALT mode
1500
840
4.8
IDD2
µA
5.00 MHz, Crystal oscillation
(fXX = 5.0 MHz)Note3
HALT mode
mA
µA
1950
Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
3. Main system clock fXX = fX operation (when OSMS is set to 01H)
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
5. Low-speed mode operation (when PCC is set to 04H)
Remark Unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins.
41
µµPD78062(A), 78063(A), 78064(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.2 V ± 10 %
60
32
120
64
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
32,768 kHz, Crystal oscillation
IDD3
operating modeNote2
24
48
25
55
32,768 kHz, Crystal oscillation
HALT modeNote2
IDD4
IDD5
IDD6
5
15
Supply
currentNote1
2.5
1
12.5
30
XT1 = VDD
STOP mode
When feedback resistor is connected
0.5
0.3
0.1
0.05
0.05
10
10
30
XT1 = VDD
STOP mode
When feedback resistor is disconnected
10
10
Notes 1. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.
2. When the main system clock is stopped.
42
µPD78062(A), 78063(A), 78064(A)
DC Characteristics (TA = –10 to +85 °C)
(1) Static display mode (VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
100
MAX.
Unit
LCD drive voltage
LCD split resistor
VLCD
2.0
60
VDD
V
RLCD
150
kΩ
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
2.0 V ≤ VLCD ≤ VDD
VLCD0 = VLCD
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(2) 1/3 bias method (VDD = 2.5 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
100
MAX.
Unit
LCD drive voltage
LCD split resistor
VLCD
RLCD
2.5
60
VDD
V
150
kΩ
2.5 V ≤ VLCD ≤ VDD
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
(3) 1/2 bias method (VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
100
MAX.
Unit
LCD drive voltage
LCD split resistor
VLCD
2.7
60
VDD
V
RLCD
150
kΩ
LCD output voltage
deviationNote (common)
LCD output voltage
deviationNote (segment)
2.7 V ≤ VLCD ≤ VDD
VODC
VODS
IO = ±5 µA
IO = ±1 µA
0
0
±0.2
±0.2
V
V
VLCD0 = VLCD
VLCD1 = VLCD × 1/2
VLCD2 = VLCD1
Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and
common outputs (VLCDn; n = 0, 1, 2).
43
µµPD78062(A), 78063(A), 78064(A)
AC Characteristics
(1) Basic operation (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Cycle time
(Minimum
instruction
Symbol
Test Conditions
Operating on main system clock
MIN.
TYP.
122
MAX.
Unit
VDD = 2.7 to 6.0 V
0.8
2.2
64
64
µs
µs
Note1
(fXX = 2.5 MHz)
TCY
fTI00
Operating on main system clock
4.5 ≤ VDD ≤ 6.0 V
2.7 ≤ VDD < 4.5 V
0.4
32
µs
Note2
execution time)
(fXX = 5.0 MHz)
0.8
40Note3
32
µs
Operating on subsystem clock
125
1/tTI00
µs
TI00 input
frequency
tTI00 = tTIH00 + tTIL00
0
MHz
2/fsam+0.1Note 4
2/fsam+0.2Note 4
2/fsam+0.5Note 4
µs
µs
µs
fTIH00,
tTIL00
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
TI00 input high/
low-level width
TI01 input high/
low-level width
fTIH01,
tTIL01
2.7 V ≤ VDD ≤ 6.0 V
10
20
0
µs
µs
VDD = 4.5 to 6.0 V
4
MHz
fTI1
TI1, TI2 input high/
low-level width
0
275
kHz
ns
VDD = 4.5 to 6.0 V
100
1.8
tTIH1,
tTIL1
TI1, TI2 input high/
low-level width
µs
µs
µs
µs
µs
µs
Note4
INTP0
8/fsam
Interrupt input
high/low-level
width
tINTH,
tINTL
INTP1 to INTP5,
P110 to P117
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
10
20
10
20
tRSL
RESET low level
width
Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. This is the value when the external clock is used. The value is 114 µs (min.) when the crystal resonator is used.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is
possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4).
44
µPD78062(A), 78063(A), 78064(A)
TCY vs VDD (At main system clock fXX = fX/2 operation)
TCY vs VDD (At main system clock fXX = fX operation)
60
60
32
10
10
µ
µ
Guaranteed Operation
Range
Guaranteed Operation
Range
2.0
2.0
1.0
0.8
1.0
0.8
0.4
0.4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
45
µµPD78062(A), 78063(A), 78064(A)
(2) Serial Interface (TA = –40 to +85 °C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
TYP.
MAX.
Unit
800
1600
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY1
2.7 V ≤ VDD < 4.5 V
3200
tKH1,
tKL1
VDD = 4.5 to 6.0 V
tKCY1/2–50
tKCY1/2–100
100
SCK0high/low-levelwidth
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
tSIK1
150
SI0setuptime(toSCK0↑)
SI0 hold time (from SCK0↑)
300
tKSI1
400
ns
ns
SO0 output delay time
tKSO1
C = 100 pFNote
300
from SCK0↓
Note C is the load capacitance of SCK0, SO0 output line.
(ii) 3-wire serial I/O mode (SCK0...External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
TYP.
MAX.
Unit
800
1600
3200
400
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY2
2.7 V ≤ VDD < 4.5 V
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
tKH2,
tKL2
800
SCK0high/low-levelwidth
1600
SI0setuptime(toSCK0↑)
SI0 hold time (from SCK0↑)
tSIK2
100
400
ns
ns
tKSI2
SO0 output delay time
tKSO2
C = 100 pFNote
300
ns
ns
from SCK0↓
tR2,
tF2
SCK0 rise, fall time
1000
Note C is the load capacitance of SO0 output line.
46
µPD78062(A), 78063(A), 78064(A)
(iii) SBI mode (SCK0...Internal clock output)
Parameter
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK0 cycle time
tKCY3
3200
ns
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
tKCY3/2–50
tKCY3/2–150
100
ns
SCK0 high/low-level
width
tKH3,
tKL3
ns
ns
SB0, SB1setuptime(to
tSIK3
tKSI3
tKSO3
SCK0↑)
300
ns
SB0, SB1 hold time
tKCY3/2
ns
(from SCK0↑)
SB0, SB1 output delay
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
250
ns
ns
ns
ns
time from SCK0↓
C = 100 pFNote
0
1000
tKCY3
tKCY3
SB0,SB1↓ fromSCK0↑
SCK0↓ fromSB0,SB1↓
tKSB
tSBK
SB0, SB1 high-level
width
tKCY3
tKCY3
ns
ns
tSBH
tSBL
SB0, SB1 low-level
width
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(iv) SBI mode (SCK0...External clock input)
Parameter
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK0 cycle time
tKCY4
3200
400
ns
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
ns
SCK0 high/low-level
width
tKH4,
tKL4
1600
100
ns
ns
SB0, SB1setuptime(to
tSIK4
tKSI4
SCK0↑)
300
ns
SB0, SB1 hold time
tKCY4/2
ns
(from SCK0↑)
SB0, SB1 output delay
R = 1 kΩ ,
VDD = 4.5 to 6.0 V
0
300
ns
ns
ns
ns
tKSO4
time from SCK0↓
C = 100 pFNote
0
1000
tKCY4
tKCY4
SB0,SB1↓ fromSCK0↑
SCK0↓ fromSB0,SB1↓
tKSB
tSBK
SB0, SB1 high-level
width
tKCY4
tKCY4
ns
tSBH
tSBL
SB0, SB1 low-level
width
ns
ns
tR4,
1000
SCK0 rise, fall time
tF4
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
47
µµPD78062(A), 78063(A), 78064(A)
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
3200
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY5
tKH5
tKL5
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
tKCY5/2–160
tKCY5/2–190
tKCY5/2–50
tKCY5/2–100
300
SCK0 high-level width
SCK0 low-level width
R = 1 kΩ,
C = 100 pFNote
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
SB0, SB1 setup time
(to SCK0↑)
tSIK5
350
400
SB0, SB1 hold time
(from SCK0↑)
tKSI5
600
ns
ns
SB0, SB1 output delay
time from SCK0↓
300
tKSO5
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 6.0 V
MIN.
TYP.
MAX.
Unit
1600
3200
650
ns
ns
ns
ns
ns
ns
tKCY6
tKH6
SCK0 cycle time
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
SCK0 high-level width
1300
800
tKL6
SCK0 low-level width
1600
SB0, SB1 setup time
(to SCK0↑)
tSIK6
100
ns
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI6
tKCY6/2
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 6.0 V
0
0
300
500
ns
ns
SB0, SB1 output delay
time from SCK0↓
tKSO6
tR6,
tF6
1000
ns
SCK0 rise, fall time
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
48
µPD78062(A), 78063(A), 78064(A)
(b) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
TYP.
MAX.
Unit
800
1600
ns
ns
ns
ns
ns
ns
ns
ns
tKCY7
2.7 V ≤ VDD < 4.5 V
SCK2 cycle time
3200
tKH7,
tKL7
VDD = 4.5 to 6.0 V
tKCY1/2–50
tKCY1/2–100
100
SCK2high/low-levelwidth
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
tSIK7
150
SI2setuptime(toSCK2↑)
SI2 hold time (from SCK2↑)
300
tKSI7
400
ns
ns
SO2 output delay time
tKSO7
C = 100 pFNote
300
from SCK2↓
Note C is the load capacitance of SCK2, SO2 output line.
(ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
TYP.
MAX.
Unit
800
1600
3200
400
ns
ns
ns
ns
ns
ns
SCK2 cycle time
tKCY8
2.7 V ≤ VDD < 4.5 V
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
tKH8,
tKL8
800
SCK2 high/low-levelwidth
1600
SI2setuptime(toSCK2↑)
SI2 hold time (from SCK2↑)
tSIK8
tKSI8
100
400
ns
ns
SO2 output delay time
tKSO8
C = 100 pFNote
300
ns
ns
from SCK2↓
tR8,
SCK2 rise, fall time
1000
tF8
Note C is the load capacitance of SO2 output line.
49
µµPD78062(A), 78063(A), 78064(A)
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
78125
39063
19531
bps
bps
bps
Transfer rate
(iv) UART mode (External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
TYP.
MAX.
Unit
800
1600
3200
400
ns
ns
ASCK cycle time
tKCY9
2.7 V ≤ VDD < 4.5 V
ns
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
ns
tKH9,
tKL9
ASCK high/low-level
width
800
ns
1600
ns
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
39063
19531
9766
bps
bps
bps
Transfer rate
tR9,
tF9
ASCK rise, fall time
1000
ns
50
µPD78062(A), 78063(A), 78064(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.8 VDD
0.2 VDD
Test Points
0.2 VDD
Clock Timing
1/f
X
t
XL
t
XH
V
IH3 (MIN.)
IL3 (MAX.)
X1 Input
V
1/fXT
t
XTL
t
XTH
V
IH4 (MIN.)
IL4 (MAX.)
XT1 Input
V
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI0–TI2
51
µµPD78062(A), 78063(A), 78064(A)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCY 1, 2, 7, 8
t
KL1, 2, 7, 8
R2, 8
t
KH1, 2, 7, 8
t
t
F2, 8
SCK0, SCK2
t
SIK1, 2, 7, 8
t
KSI1, 2, 7, 8
SI0, SI2
Input Data
t
KSO1, 2, 7, 8
SO0, SO2
Output Data
SBI mode (bus release signal transfer):
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
R4
t
F4
SCK0
t
KSB
t
SBL
t
SBK
t
SIK3, 4
t
KSI3, 4
t
SBH
SB0, SB1
t
KSO3, 4
SBI mode (command signal transfer):
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
R4
t
F4
SCK0
t
SBK
t
SIK3, 4
t
KSI3.4
t
KSB
SB0, SB1
t
KSO3, 4
52
µPD78062(A), 78063(A), 78064(A)
2-wire serial I/O mode:
t
KCY5.6
t
KL5, 6
t
KH5, 6
t
R6
t
F6
SCK0
t
SIK5, 6
t
KSI5, 6
t
KSO5, 6
SB0, SB1
UART mode:
tKCY9
t
KL9
t
KH9
t
R9
t
F9
ASCK
A/D Converter (TA = –40 to +85 °C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Test Conditions
MIN.
8
TYP.
8
MAX.
Unit
8
bit
%
2.7 V ≤ AVREF ≤ 6.0 V
±0.6
±1.4
200
Note
Overall error
%
tCONV
19.1
µs
Conversion time
Sampling time
tSAMP
VIAN
12/fXX
AVSS
2.0
µs
V
Analog input voltage
Reference voltage
AVREF-AVSS resistance
AVREF
AVDD
AVREF
RAIREF
V
4
14
kΩ
Note Quantization error (±1/2 LSB) is not included. This is expressed in proportion to the full-scale value.
53
µµPD78062(A), 78063(A), 78064(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Data retention
Symbol
Test Conditions
MIN.
1.8
TYP.
0.1
MAX.
6.0
Unit
V
VDDDR
supply voltage
VDDDR = 1.8 V
Data retention
supply current
IDDDR
tSREL
Subsystem clock stopped and
feed-back resistor disconnected
10
µA
Release signal set time
0
µs
Oscillation
stabilization
wait time
Release by RESET
Release by interrupt
217/fx
ms
tWAIT
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection
of 212/fXX and 214/fXX to 217/fXX is possible.
Data retention timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data retention timing (STOP mode release by standby release signal: Interrupt signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
t
SREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
t
WAIT
54
µPD78062(A), 78063(A), 78064(A)
Interrupt input timing
t
INTL
t
INTH
INTP0–INTP5
RESET input timing
t
RSL
RESET
55
µPD78062(A), 78063(A), 78064(A)
11. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock: 5.0 MHz)
(TA = 25 °C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
(X1 Oscillation,
XT1 Oscillation)
HALT
1.0
0.5
0.1
PCC=B0H
0.05
(X1 Stop, XT1 Oscillation)
STOP(X1 Stop, XT1 Oscillation)
HALT
0.01
f
f
XX
= 5.0 MHz
XT= 32.768 kHz
0.005
0.001
1
2
3
4
5
6
7
8
0
Supply Voltage VDD (V)
56
µPD78062(A), 78063(A), 78064(A)
IDD vs VDD (Main System Clock: 2.5 MHz)
(TA = 25 °C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
(X1 Oscillation,
HALT
XT1 Oscillation)
1.0
0.5
0.1
PCC=B0H
0.05
(X1 Stop, XT1 Oscillation)
STOP(X1 Stop, XT1 Oscillation)
HALT
0.01
f
f
XX
= 2.5 MHz
XT= 32.768 kHz
0.005
0.001
1
2
3
4
5
6
7
8
0
Supply Voltage VDD (V)
57
µPD78062(A), 78063(A), 78064(A)
12. PACKAGE DRAWINGS
100 PIN PLASTIC QFP (FINE PITCH) ( 14)
A
B
75
76
51
50
detail of lead end
100
1
26
25
G
M
I
H
J
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
A
B
16.0±0.2
14.0±0.2
0.630±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
16.0±0.2
1.0
0.630±0.008
0.039
G
1.0
0.039
+0.05
0.22
H
0.009±0.002
–0.04
Remark Dimensions and materials of ES products are same as those
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
of mass production product.
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
R
S
0.10
0.004
1.45
0.057
0.125±0.075
5°±5°
0.005±0.003
5°±5°
1.7 MAX.
0.067 MAX.
P100GC-50-7EA-2
58
µPD78062(A), 78063(A), 78064(A)
×
100 PIN PLASTIC QFP (14 20)
A
B
51
50
80
81
detail of lead end
31
30
100
1
G
M
I
H
J
K
N
L
P100GF-65-3BA1-2
NOTE
ITEM
A
B
MILLIMETERS
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
±
±
23.6 0.4
0.929 0.016
+0.009
–0.008
±
20.0 0.2
0.795
+0.009
–0.008
±
C
14.0 0.2
0.551
±
±
D
F
0.693 0.016
17.6 0.4
0.8
0.6
0.031
G
H
I
0.024
+0.004
–0.005
±
0.30 0.10
0.012
Remark Dimensions and materials of ES products are
0.15
0.006
same as mass production product.
J
0.65 (T.P.)
0.026 (T.P.)
+0.008
±
1.8 0.2
K
L
0.071
–0.009
+0.009
±
0.8 0.2
0.031
–0.008
+0.10
–0.05
+0.004
–0.003
0.15
M
N
P
0.006
0.10
2.7
0.004
0.106
±
Q
S
0.1 0.1
±
0.004 0.004
3.0 MAX.
0.119 MAX.
59
µPD78062(A), 78063(A), 78064(A)
100 PIN PLASTIC LQFP (FINE PITCH) (14×14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
H
I
J
G
K
L
P
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
A
B
16.00±0.20
14.00±0.20
0.630±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
16.00±0.20
–0.008
0.630±0.008
F
1.00
1.00
0.039
0.039
G
+0.05
0.22
H
0.009±0.002
–0.04
Remark Dimensions and materials of ES products are
I
0.08
0.003
same as mass production product.
J
0.50 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.00±0.20
0.50±0.20
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.08
0.003
1.40±0.05
0.10±0.05
0.055±0.002
0.004±0.002
+7°
3°
+7°
3°
R
S
–3°
–3°
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
60
µPD78062(A), 78063(A), 78064(A)
13. RECOMMENDED SOLDERING CONDITIONS
The µPD78062(A)/78063(A)/78064(A) should be soldered and mounted under the conditions recommended in the table
below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 13-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD78062GC(A)-×××-7EA : 100-pin plastic QFP (Fine pitch) (14 × 14mm, resin thickness: 1.45 mm)
µPD78063GC(A)-×××-7EA : 100-pin plastic QFP (Fine pitch) (14 × 14mm, resin thickness: 1.45 mm)
µPD78064GC(A)-×××-7EA : 100-pin plastic QFP (Fine pitch) (14 × 14mm, resin thickness: 1.45 mm)
Soldering
Method
Recommended
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
Infrared reflow
IR35-107-2
<precaution>
Baking cannot be applied to other than heat-resistant trays (magazine, taping, non-
heat-resistant trays) when the product is wrapped.
Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above),
Number of times: Twice max., Time limit: 7 daysNote (thereafter 10 hours prebaking
required at 125°C)
VPS
VP15-107-2
<precaution>
Baking cannot be applied to other than heat-resistant trays (magazine, taping, non-
heat-resistant trays) when the product is wrapped.
—
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.
(2) µPD78062GF(A)-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
µPD78063GF(A)-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
µPD78064GF(A)-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
Soldering
Method
Recommended
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
IR35-00-3
VP15-00-3
Infrared reflow
Number of times: Thrice max.
Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above),
VPS
Number of times: Thrice max.
Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120°C max. (Package surface temperature)
Wave soldering
WS60-00-1
—
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
Partial heating
Cautions 1. Use of more than one soldering method should be avoided (except in the case of partial heating).
2. The µPD78062GC(A)-×××-8EU, 78063GC(A)-×××-8EU, and 78064GC(A)-×××-8EU are under planning.
Therefore, soldering conditions for these products have not been specified.
61
µPD78062(A), 78063(A), 78064(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using µPD78062(A)/78063(A)/78064(A).
Language Processing Software
Note 1, 2, 3, 4
RA78K/0
CC78K/0
DF78064
78K/0 series common assembler package
78K/0 series common C compiler package
µPD78064 subseries device file
Note 1, 2, 3, 4
Note 1, 2, 3, 4
Note 1, 2, 3 ,4
CC78K/0-L
78K/0 series common C compiler library source file
PROM Writing Tools
PROM programmer
PG-1500
Programmer adapters connected to PG-1500
PA-78P0308GC
(or PA-78P064GC)
PA-78P0308GF
(or PA-78P064GF)
PA-78P0308KL-T
PG-1500 controller Notes 1, 2
PG-1500 control program
Debugging Tools
78K/0 series common in-circuit emulator
IE-78000-R
78K/0 series common in-circuit emulator (for integrated debugger)
78K/0 series common break board
IE-78000-R-A
IE-78000-R-BK
IE-78064-R-EM Note 8
IE-780308-R-EM
IE-78000-R-SV3
IE-70000-98-IF-B
µPD78064 subseries evaluation emulation board
µPD780308 subseries common emulation board
Interface adapter and cable when EWS is used as host machine (for IE-78000-R-A)
Interface adapter when PC-9800 series (except notebook type) is used as host machine (for IE-
78000-R-A)
Interface adapter and cable when notebook type PC-9800 series is used as host machine (for IE-
78000-R-A)
IE-70000-98N-IF
IE70000-PC-IF-B
Interface adapter when IBM PC/ATTM is used as host machine (IE-78000-R-A)
EP-78064GC-R
EP-78064GF-R
µPD78064 subseries common emulation probes
TGC-100SDW
Adapter to be mounted on a target system board made for 100-pin plastic QFP (GC-7EA, GC-8EU type)
TGC-100SDW is a product from Tokyo Eletech Corp. (TEL (03) 5295-1661)
When purchasing this product, please consult with our sales offices.
EV-9200GF-100
SM78K0 Note 5, 6, 7
ID78K0 Note 4, 5, 6, 7
SD78K/0 Note 1, 2
Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)
78K/0 series common system simulator
IE-78000-R-A integrated dubugger
IE-78000-R screen debugger
DF78064 Note 1, 2, 4, 5, 6, 7
µPD78064 subseries device file
62
µPD78062(A), 78063(A), 78064(A)
Real-Time OS
RX78K/0 Note 1, 2, 3, 4
MX78K0 Note 1, 2, 3, 4
78K/0 series real-time OS
78K/0 series OS
Fuzzy Inference Development Support System
FE9000 Note 1, FE9200 Note 6
FT9080 Note 1, FT9085 Note 2
FI78K/0 Note 1, 2
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fussy inference debugger
FD78K/0 Note 1, 2
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/AT and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based
5. PC-9800 series (MS-DOS + WindowsTM) based.
6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
8. IE-78064-R-EM is a maintenance product.
Remarks 1. For third party development tools, refer to the 78K/0 Series Selection Guide (U11126E).
2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78064.
63
µPD78062(A), 78063(A), 78064(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document No.
Document Name
Japanese
U10335J
English
µPD78062(A), 78063(A) 78064(A) Data Sheet
µPD78064, 78064Y Subseries User's Manual
78K/0 Series User's Manual - Instruction
78K/0 Series Instruction Table
This document
U10105J
U12326J
U10903J
U10904J
IEM-5568
IEA-767
IEA-718
U10105E
IEU-1372
—
78K/0 Series Instruction Set
—
µPD78018F Subseries Special Function Register Table
—
78K/0 Series Application Note
Fundamental (III)
Floating-Point Arithmetic Program
U10182E
IEA-1289
Development Tools Related Documents (User’s Manual) (1/2)
Document No.
Document Name
Japanese
EEU-809
English
RA78K Series Assembler Package
Operation
Language
EEU-1399
EEU-815
EEU-817
U11802J
U11801J
U11789J
EEU-656
EEU-655
U11517J
U11518J
EEA-618
U12322J
EEU-810
U10057J
EEU-867
EEU-905
U11362J
EEU-934
EEU-1404
EEU-1402
U11802E
U11801E
U11789E
EEU-1280
EEU-1284
U11517E
U11518E
EEA-1208
—
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
Operation
Assembly Language
Structured Assembly Language
Operation
CC78K Series C Compiler
CC78K/0 C Compiler
Language
Operation
Language
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
IE-78000-R
Programming Know-how
U11376E
U10057E
EEU-1427
EEU-1443
U11362E
EEU-1469
IE-78000-R-A
IE-78000-R-BK
IE-78064-R-EM
IE-780308-R-EM
EP-78064
Caution The contents of the above related documents are subject to change without notice. The latest
documents should be used for design, etc.
64
µPD78062(A), 78063(A), 78064(A)
Development Tools Documents (User's Manual) (2/2)
Document No.
Document Name
Japanese
U10092J
English
SM78K Series System Simulator
External Components User Open
U10092E
Interface
SM78K0 System Simulator Windows Based
ID78K0 Integrated Debugger EWS Based
ID78K0 Integrated Debugger PC Based
ID78K0 Integrated Debugger Windows Based
SD78K/0 Screen Debugger
Reference
Reference
Reference
Guide
U10181J
U11515J
U11539J
U11649J
EEU-852
U10952J
EEU-5024
U11279J
U10181E
—
U11539E
U11649E
U10539E
—
Introduction
Reference
Introduction
Reference
PC-9800 Series (MS-DOS) Based
SD78K/0 Screen Debugger
EEU-1414
U11279E
IBM PC/AT (PC DOS) Based
Embedded Software Documents (User's Manual)
Document No.
Document Name
Japanese
U11537J
English
—
78K/0 Series Real-Time OS
Fundamental
Installation
U11536J
U12257J
EEU-829
EEU-862
—
78K/0 Series OS MX78K0
Fundamental
—
Fuzzy Knowledge Data Creation Tool
EEU-1438
EEU-1444
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System
- Translator
78K/0 Series Fuzzy Inference Development Suport System
- Fuzzy Inference Module
EEU-858
EEU-921
EEU-1441
EEU-1458
78K/0 Series Fuzzy Inference Development Support System
- Fuzzy Inference Debugger
Other Documents
Document No.
Document Name
Japanese
C10943X
English
IC Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Device
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
C10535E
C11531E
C10983E
—
Guide to Quality Assurance for Semiconductor Device
Guide for Products Related to MicroComputer: Other Companies
C11893E
—
Caution The contents of the above related documents are subject to change without notice. The latest
documents should be used for design, etc.
65
µPD78062(A), 78063(A), 78064(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
66
µPD78062(A), 78063(A), 78064(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Fax: 02-66 75 42 99
Fax: 02-719-5951
Taeby, Sweden
Tel: 08-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 08-63 80 388
J96. 8
67
µPD78062(A), 78063(A), 78064(A)
FIP is a registered trademark of NEC Corporation.
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
Some of related document may be preliminary, but is not marked as such.
Please keep this in mind as you refer to this information.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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UPD78063GC-XXX-8EU
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NEC
UPD78063GFA-XXX-3BA
Microcontroller, 8-Bit, MROM, MOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
NEC
UPD78063YGC-XXX-8EU
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RENESAS
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