UPD78322L-XXX [NEC]
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| 型号： | UPD78322L-XXX |
| 厂家： | 
NEC |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78320,78322
16/8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78322 is a 16-/8-bit single-chip microcontroller that incorporates a high-performance 16-bit CPU. TheµPD78322
is one of 78K/III series.
A realtime pulse unit for realtime pulse control required in motor control, an A/D converter, a ROM, and a RAM have been
integrated into one chip.
The µPD78322 incorporates 16K-byte mask ROM and 640-byte RAM.
The µPD78320 is provided as a ROM-less product of the µPD78322. Also, the µPD78P322 is provided as an on-chip
PROM product.
Detailed information about product features and specifications can be found in the following document.
µPD78322 User’s Manual : IEU-1248
FEATURES
• Internal 16-bit architecture and external 8-bit data bus
• High-speed processing by pipeline control and instruction prefetch
• Minimum instruction execution time: 250 ns (with 16 MHz external clock in operation)
• Instruction set suitable for control operations (µPD78312 upward compatible)
• Multiplication/division instruction (16 bits × 16 bits, 32 bits ÷ 16 bits)
• Bit manipulation instruction
• String instruction, etc.
• On-chip high-function interrupt controller
• 3-level priority specifiable
• 3-type interrupt servicing mode selectable
(Vectored interrupt function, context switching function, and macro service function)
• Variety of peripheral hardware
• Realtime pulse unit
• 8-channel, 10-bit A/D converter
• Watchdog timer
• Powerful serial interface (with an on-chip dedicated baud rate generator)
• UART
····· 1 channel
• SBI (NEC Standard Serial Bus Interface)
• 3-wire serial I/O
····· 1 channel
APPLICATIONS
• Motor control devices
Unless there are any particular notices, the µPD78322 is described as the representative model in this document.
The information in this document is subject to change without notice.
Document No. U10455EJ7V0DS00 (7th edition)
(Previous No. IC-2354)
The mark
shows major revised points.
Date Published November 1995 P
Printed in Japan
1989
©
µPD78320, 78322
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD78320GF-3B9
µPD78320GJ-5BJ
µPD78320L
µPD78322GF-× × ×-3B9
µPD78322GJ-× × ×-5BJ
µPD78322L-× × ×
80-pin plastic QFP (14 × 20 mm)
74-pin plastic QFP (20 × 20 mm)
68-pin plastic QFJ ( 950 mil)
80-pin plastic QFP (14 × 20 mm)
74-pin plastic QFP (20 × 20 mm)
68-pin plastic QFJ ( 950 mil)
None
None
None
Mask ROM
Mask ROM
Mask ROM
Remark × × × indicates ROM code number.
2
µPD78320, 78322
PIN CONFIGURATION
•
68-pin plastic QFJ ( 950 mil)
µPD78320L
µPD78322L-×××
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
P71/AN1
P70/AN0
AVSS
P30/T
P31/R
X
X
D
D
10
11
12
13
14
59
58
57
56
55
54
53
52
51
P32/SO/SB0
P33/SI/SB1
P34/SCK
P80/TO00
P81/TO01
P82/TO02
P83/TO03
P84/TO10
P85/TO11
RESET
V
DD
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
15
16
17
18
19
20
50
49
48
P50/A8
21
22
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
X2
47
46
45
44
X1
23
24
25
V
SS
WDTO
RTP0/P00
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
3
µPD78320, 78322
•
74-pin plastic QFP (20 × 20 mm)
µPD78320GJ-5BJ
µPD78322GJ-×××-5BJ
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56
55
P00/RTP0
WDTO
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
V
SS
NC
X1
X2
RESET
P51/A9
P85/TO11
P84/TO10
P83/TO03
P82/TO02
P81/TO01
P80/TO00
NC
7
8
P52/A10
P53/A11
P54/A12
P55/A13
NC
9
10
45
44
43
11
12
P56/A14
P57/A15
13
14
42
41
40
P34/SCK
P33/SI/SB1
P32/SO/SB0
V
DD
15
16
17
AVSS
P70/AN0
P71/AN1
P31/R
P30/T
X
D
39
38
X
D
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Caution The NC pin should be connected to VSS for noise control (can also be left open).
4
µPD78320, 78322
•
80-pin plastic QFP (14 × 20 mm)
µPD78320GF-3B9
µPD78322GF-×××-3B9
80 7978 77 76 75 74 73 72 7170 69 68 67 66 65
P72/AN2
P27/INTP6/TI
NC
1
64
63
NC
2
NC
P30/TxD
P31/RxD
P32/SO/SB0
P33/SI/SB1
P34/SCK
P80/TO00
P81/TO01
P82/TO02
P83/TO03
P84/TO10
NC
NC
3
62
P71/AN1
P70/AN0
AVSS
4
5
6
7
61
60
59
58
V
DD
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
8
9
57
56
55
54
53
52
51
50
10
11
12
13
14
15
P85/TO11
RESET
P50/A8
16
17
18
19
20
49
48
47
46
45
P47/AD7
X2
X1
P46/AD6
P45/AD5
P44/AD4
P43/AD3
NC
V
SS
WDTO
RTP0/P00
NC
RTP1/P01
NC
21
22
23
24
44
43
42
41
NC
NC
P42/AD2
25 2627 28 29 30 31 32 33 3435 36 37 38 39 40
Caution The NC pin should be connected to VSS for noise control (can also be left open).
5
µPD78320, 78322
P00 to P07
P20 to P27
P30 to P34
P40 to P47
P50 to P57
P70 to P77
P80 to P85
P90 to P93
NMI
: Port0
: Port2
: Port3
: Port4
: Port5
: Port7
: Port8
: Port9
RESET
X1, X2
WDTO
EA
TMD
TAS
WR
RD
ASTB
AD0 to AD7
A8 to A15
AN0 to AN7
AVREF
AVSS
: Reset
: Crystal
: Watchdog Timer Output
: External Access
: Turbo Mode
: Turbo Access Strobe
: Write Strobe
: Read Strobe
: Nonmaskable Interrupt
: Address Strobe
: Address/Data Bus
: Address Bus
: Analog Input
: Analog Reference Voltage
: Analog VSS
INTP0 to INTP6 : Interrupt From Peripherals
RTP0 to RTP7 : Realtime Port
TI
TXD
RXD
: Timer Input
: Transmit Data
: Receive Data
SB0/SO
SB1/SI
SCK
TO00 to TO03
TO10, TO11
: Serial Bus/Serial Output
: Serial Bus/Serial Input
: Serial Clock
AVDD
: Analog VDD
: Power Supply
: Ground
VDD
VSS
NC
:
: Non-connection
Timer Output
:
6
µPD78320, 78322
GENERAL DESCRIPTION OF FUNCTIONS
Basic instructions
111
Minimum instruction
execution time
250 ns (with 16 MHz external clock in operation)
• ROM : 16384 × 8 bits (µPD78322)
Internal memory
None
(µPD78320)
• RAM : 640 × 8 bits
Memory space
64K bytes
General registers
8 bits × 16 × 8 banks (memory mapping)
• Input port
: 16 (dual-function as analog input: 8)
I/O line
• Input/output port
: 39 (µPD78322)
21 (µPD78320)
• 18-/16-bit free running timer × 1
• 16-bit timer/event counter × 1
• 16-bit compare register × 6
• 18-bit capture register × 4
Realtime pulse unit
• 18-bit capture/compare register × 2
• Realtime output port × 8
Serial interface with a dedicated baud rate generator
Serial communication
interface
• UART
: 1 channel
• SBI (NEC Serial Bus Interface) : 1 channel
A/D converter
Interrupt
10-bit resolution (8 analog inputs)
• External
• 3 servicing modes
(vectored interrupt function, context switching function, and macro service function)
:
8, internal
: 14 (dual-function as external : 2)
Test factor
Standby
Internal : 1
STOP mode/HALT mode
16-bit transfer/operation instruction, multiplication/division instruction (16 × 16, 32 ÷ 16), bit manipu-
Instruction set
Others
lation instruction, string instruction, etc.
On-chip watchdog timer
• 68-pin plastic QFJ ( 950 mil)
• 74-pin plastic QFP (20 × 20 mm)
• 80-pin plastic QFP (14 × 20 mm)
Package
7
µPD78320, 78322
DIFFERENCES BETWEEN µPD78322 AND 78320
Product Name
µPD78322
µPD78320
Item
Internal ROM
16K bytes
None
Input
16 (dual-function as analog input: 8)
I/O line
Input
39
21
/output
Specifiable as I/O as an 8-bit unit.
Functions as multiplexed address/data buses
(AD0 to AD7) in the external memory expansion
mode.
Functions always as multiplexed address/data
buses.
Port 4
(P40 to P47)
Specifiable as I/O bit-wise.
Port 5
Functions as address bus (A8 to A15) in the
external memory expansion mode.
Functions always as address bus.
(P50 to P57)
Specifiable as I/O bit-wise.
In the external memory expansion mode, P90
and P91 function as RD strobe signal output and
WR strobe signal output, respectively. In the
external memory high-speed fetch mode, P92
and P93 function as TAS output and TMD
output, respectively.
Always P90 and P91 function as RD strobe and
WR strobe signal output, respectively.
Port 9
(P90 to P93)
Memory expansion
mode register (MM)
In the µPD78322 emulation mode, turbo
Port 4 I/O mode is set as an 8-bit unit .
Port 5 I/O mode is set bit-wise.
Note
access manager (µPD71P301)
PA and PB pins
are controlled as port 4 and port 5 emulation
pins.
Port 5 mode register
(PM5)
Note Maintenance product
8
EXU
ROM/Peripheral RAM
BCU
Main RAM
GENERAL
REGISTERS
128 bytes
&
X1
(P20) NMI
X2
PROGRAMMABLE
INTERRUPT
CONTROLLER
RESET
ASTB
INTP0–INTP5
(P21–P26)
ALU
ROM Note
16K bytes/
Peripheral
RAM
DATA
MEMORY
128 bytes
SYSTEM
CONTROL
&
BUS
CONTROL
&
RD (P90)
WR (P91)
TAS (P92)
TMD (P93)
384 bytes
PREFETCH
CONTROL
(P80) TO00
(P81) TO01
(P82) TO02
(P83) TO03
(P84) TO10
(P85) TO11
(P27) TI/INTP6
MICRO SEQUENCE
CONTROL
EA
TIMER/COUNTER UNIT
(REALTIME PULSE UNIT)
A8–A15 (P50–P57)
MICRO ROM.
AD0–AD7 (P40–P47)
(P34) SCK
(P32) SO/SB0
(P33) SI/SB1
V
V
DD
SS
A/D CONVERTER
(10 BITS)
SERIAL INTERFACE
(SBI)
WDT
PORT
(UART)
(P30) T
X
D
D
(P31) R
X
µ
Note The µPD78320 does not incorporate ROM.
µPD78320, 78322
CONTENTS
1. LIST OF PIN FUNCTIONS ..................................................................................................................... 12
1.1 PORT PINS ...................................................................................................................................................... 12
1.2 NON-PORT PINS............................................................................................................................................. 13
1.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS................... 15
2. CPU ARCHITECTURE............................................................................................................................ 17
2.1 MEMORY SPACE ............................................................................................................................................ 17
2.2 PROCESSOR REGISTERS ............................................................................................................................ 20
2.2.1
2.2.2
2.2.3
Control Registers ........................................................................................................................... 21
General Registers........................................................................................................................... 23
Special Function Registers (SFR)................................................................................................ 25
2.3 DATA MEMORY ADDRESSING..................................................................................................................... 30
2.3.1
2.3.2
2.3.3
General Register Addressing ....................................................................................................... 30
Short Direct Addressing................................................................................................................ 30
Special Function Register (SFR) Addressing ............................................................................ 30
3. BLOCK FUNCTIONS .............................................................................................................................. 31
3.1 BUS CONTROL UNIT (BCU).......................................................................................................................... 31
3.2 EXECUTION UNIT (EXU)................................................................................................................................ 31
3.3 ROM/RAM ........................................................................................................................................................ 31
3.4 INTERRUPT CONTROLLER .......................................................................................................................... 31
3.5 PORT FUNCTIONS ......................................................................................................................................... 32
3.6 CLOCK GENERATOR .................................................................................................................................... 33
3.7 REALTIME PULSE UNIT (RPU)..................................................................................................................... 35
3.7.1
3.7.2
Configuration .................................................................................................................................. 35
Realtime Output Function ............................................................................................................. 37
3.8 A/D CONVERTER ........................................................................................................................................... 38
3.9 SERIAL INTERFACE ...................................................................................................................................... 38
3.10 WATCHDOG TIMER ....................................................................................................................................... 41
4. INTERRUPT FUNCTIONS ...................................................................................................................... 42
4.1 OVERVIEW ...................................................................................................................................................... 42
4.2 MACRO SERVICE ........................................................................................................................................... 44
4.3 CONTEXT SWITCHING FUNCTION .............................................................................................................. 45
4.3.1
4.3.2
Context Switching Function by Interrupt Request.................................................................... 45
Context Switching Function by BRKCS Instruction ................................................................. 46
5. STANDBY FUNCTIONS ......................................................................................................................... 47
6. EXTERNAL DEVICE EXPANSION FUNCTION .................................................................................... 48
7. OPERATION AFTER RESET ................................................................................................................. 49
8. INSTRUCTION SET ................................................................................................................................ 50
9. ELECTRICAL SPECIFICATIONS .......................................................................................................... 64
10
µPD78320, 78322
10. PACKAGE DRAWINGS.......................................................................................................................... 75
11. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 78
APPENDIX A. LIST OF 78K/ΙΙΙ SERIES PRODUCTS................................................................................ 79
APPENDIX B. TOOLS .................................................................................................................................. 81
B.1 DEVELOPMENT TOOL................................................................................................................................... 81
B.2 EVALUATION TOOL ....................................................................................................................................... 85
B.3 EMBEDDED SOFTWARE ............................................................................................................................... 85
11
µPD78320, 78322
1. LIST OF PIN FUNCTIONS
1.1 PORT PINS
Dual-
Pin Name
I/O
Function
Function Pin
Port 0
RTP0 to
RTP7
Input/
8-bit input/output port
P00 to P07
output
Input/output can be specified bit-wise
Also serves as a realtime output port.
P20
P21
NMI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6/TI
TXD
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
Port 2
Input
8-bit dedicated input port
Port 3
RXD
Input/
5-bit input/output port
Input/output can be specified bit-wise
SO/SB0
SI/SB1
SCK
output
Port 4
Input/
8-bit input/output port
AD0 to AD7
P40 to P47
output
Input/output can be specified in 8-bit unit.
Port 5
Input/
8-bit input/output port
Input/output can be specified bit-wise
P50 to P57
P70 to P77
A8 to A15
output
Port 7
AN0 to AN7
Input
8-bit dedicated input port
TO00
TO01
TO02
TO03
TO10
TO11
RD
P80
P81
P82
P83
P84
P85
P90
P91
P92
P93
Port 8
6-bit input/output port
Input/output can be specified bit-wise
Input/
output
Port 9
WR
Input/
4-bit input/output port
Input/output can be specified bit-wise
output
TAS
TMD
12
µPD78320, 78322
1.2 NON-PORT PINS (1/2)
Dual-
Pin Name
I/O
Function
Function Pin
Realtime output port which generates pulses in synchronization with the trigger signal
transmitted from the realtime pulse unit (RPU).
P00 to P07
P20
RTP0 to RTP7 Output
Nonmaskable interrupot request input capable of specifying the effective at the rising or
falling edge by a mode register.
Input
Input
NMI
P21
P22
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
TI
P23
External interrupt request input capable of specifying the effective edgy by a mode
register.
P24
P25
P26
P27/TI
P27/INTP6
Input
External count clock input to timer 1 (TM1)
Output
Serial data output of asynchronous serial interface (UART)
TXD
P30
P31
RXD
Input
Output
Input
Serial data input of asynchronous serial interface (UART)
Serial data output of clocked serial interface in 3-wire mode
Serial data input of clocked serial interface in 3-wire mode
P32/SB0
SO
SI
P33/SB1
P32/SO
SB0
SB1
Input
Serial data input/output of clocked serial interface in SBI mode
Serial clock input/output of clocked serial interface
/output
P33/SI
P34
Input
SCK
/output
Input
P40 to P47
Multiplexed address/data bus for external memory expansion
Address bus for external memory expansion
AD0 to AD7
/output
P50 to P57
P80
A8 to A15
TO00
Output
Output
P81
TO01
P82
TO02
Pulse output from the realtime pulse unit
P83
TO03
P84
TO10
P85
TO11
RD
P90
Strobe signal output generated for external memory read operation
Strobe signal output generated for external memory write operation
WR
TAS
P91
Output
P92
P93
Note
Control signal output generated for access to turbo access manager µPD71P301
TMD
WDTO
––
––
Signal output indicating that the watchdog timer has generated a nonmascable interrupt.
Output
Output
Timing signal output generated for externally latching the lower address information output
from pins AD0 to AD7 in order to access the external memory.
ASTB
Note Maintenance product
13
µPD78320, 78322
1.2 NON- PORT PINS (2/2)
Dual-
Pin Name
EA
I/O
Function
Function Pin
In the µPD78322, EA pin is normally connected to VDD. Connecting EA pin to VSS sets the
ROM-less mode and accesses the external memory. In the µPD78320, this pin should be
fixed to “0” (low level). The EA pin level cannot be changed during operation.
—
Input
—
—
—
—
—
—
—
—
—
—
AN0 to AN7
AVREF
AVDD
AVSS
RESET
X1
Input
Input
—
A/D converter analog input
A/D converter reference voltage input
A/D converter analog power supply
A/D converter GND
—
Input
Input
—
System reset input
Crystal connect pin for sysem clock oscillation. When an external clock is supplied,
the clock is input to X1 and the inverted clock is input to X2. (X2 can also be left open.)
X2
Positive power supply
VDD
––
GND pin
VSS
—
Not internally connected. Connected to VSS (GND) (can also be left open).
NC
—
14
µPD78320, 78322
1.3 PIN INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The pin input/output circuits, partly simplified, are shown in Table 1-1 and Figure 1-1.
Table 1-1. I/O Circuit Types of Pins and their Recommended
Connection Methods when Unused
Input/Output
Pin
Recommended Connection Method
Circuit Type
Input mode
:
Individually connected to VDD or VSS via
resistor
P00 to P07/RTP0 to RTP7
5
Output mode : Leave open
Connected to VSS
P20/NMI
P21 to P26/INTP0 to INTP5
P27/INTP6/TI
2
5
8
P30/TXD
P31/RXD
Input mode
:
Individually connected to VDD or VSS via
resistor
P32/SO/SB0
P33/SI/SB1
P34/SCK
Output mode : Leave open
P40 to P47/AD0 to AD7
P50 to P57/A8 to A15
5
9
5
Connected to VSS
P70 to P77/AN0 to AN7
P80 to P83/TO00 to TO05
P84, P85/TO10, TO11
Input mode
:
Individually connected to VDD or VSS via
resistor
P90/RD
P91/WR
P92/TAS
P93/TMD
Output mode : Leave open
5
WDTO
ASTB
EA
3
4
Leave open
1
––
––
RESET
AVREF, AVSS
AVDD
2
Connected to VSS
Connected to VDD
––
––
––
NC
Connected to VSS (can also be left open)
15
µPD78320, 78322
Figure 1-1. Pin Input/Output Circuits
Type 5
Type 1
VDD
VDD
data
P-ch
IN/OUT
P-ch
IN
output
disable
N-ch
N-ch
input
enable
Type 8
Type 2
VDD
data
P-ch
IN/OUT
IN
output
disable
N-ch
Schmitt-triggered input having hysteresis characteristics.
Type 3
Type 9
VDD
Comparator
P-ch
N-ch
+
–
IN
P-ch
N-ch
OUT
V
ref
(Threshold Voltage)
input
enable
Type 4
VDD
data
P-ch
N-ch
OUT
output
disable
Push-pull output which can become high-impedance
output (with both P-ch and N-ch set to off)
16
µPD78320, 78322
2. CPU ARCHITECTURE
2.1 MEMORY SPACE
In the µPD78322 a maximum of 64K bytes of memory can be addressed (see Figure 2-1).
Program fetches can be performed within the area from 0000H to FDFFH. However, when external memory expansion
is implemented in the area from FE00H to FFFFH (main RAM and special function register area), program fetches can also
be performed on this area. In this case, a program fetch is performed on the external memory, not on the main RAM or special
function registers.
(1) Vector table area
Interrupt request from the peripheral hardware, reset input, external interrupt request and interrupt branch address
by break instruction are stored in the 0000H to 003FH 64-byte area. Generation of an interrupt request sets the even
address content of each table in the lower 8 bits of the program counter (PC) and the odd address content in the higher
8 bits, and a branch is made.
Interrupt Source
Vector Table Address
RESET
NMI
(RESET pin input) ........................................... 0000H
(NMI pin input) ................................................ 0002H
WDT
(Watchdog timer) ............................................ 0004H
(Realtime pulse unit)....................................... 0006H
(INTP0 pin input)............................................. 0008H
(INTP1 pin input)............................................. 000AH
(INTP2 pin input)............................................. 000CH
(INTP3 pin input)............................................. 000EH
TMF0
EXF0
EXF1
EXF2
EXF3
EXF4/CCFX0 (INTP4 pin input/realtime pulse unit) ............. 0010H
EXF5/CCFX1 (INTP5 pin input/realtime pulse unit) ............. 0012H
EXF6/TI
CMF00
CMF01
CMF02
CMF03
CMF10
CMF11
SRF
(INTP6/TI pin input) ........................................ 0014H
(Realtime pulse unit)....................................... 0016H
(Realtime pulse unit)....................................... 0018H
(Realtime pulse unit)....................................... 001AH
(Realtime pulse unit)....................................... 001CH
(Realtime pulse unit)....................................... 001EH
(Realtime pulse unit)....................................... 0020H
(Serial receive complete)................................ 0024H
(Serial send complete).................................... 0026H
(Clocked serial interface)................................ 0028H
(A/D converter)................................................ 002AH
STF
CSIIF
ADF
Operation code trap ................................................................... 003CH
BRK (Break instruction)........................................... 003EH
If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8002H to 803FH external memory area is used as an interrupt
vector table in place of 0002H to 003FH.
17
µPD78320, 78322
(2) CALLT table area
32 tables of call addresses of 1-byte call instruction (CALLT) can be stored in the 0040H to 007FH 64-byte area.
If bit 1 (TPF) of CPU control word (CCW) is set to 1, the 8040H to 807FH external memory area is used as a CALLT
instruction table in place of 0040H to 007FH.
(3) CALLF entry area
The 0800H to 0FFFH area can be directly subroutine-called by 2-byte call instruction (CALLF).
(4) Internal RAM area
A 640-byte RAM is built in FC80H to FEFFH area.
This area is composed of the following 2 RAMs.
• Peripheral RAM : FC80H to FDFFH (384 bytes)
• Main RAM
: FE00H to FEFFH (256 bytes)
The main RAM can be accessed at high speed.
In the main RAM area, the macro service control word and general register group composed of 8 register banks are
mapped onto the 36 bytes from FE06H to FE2BH and the 128 bytes from FE80H to FEFFH, respectively.
(5) Special function register (SFR) area
Registers having specially assigned functions, such as on-chip peripheral hardware mode registers and control
registers, are mapped in the FF00H to FFFFH area. Addresses without mapped registers cannot be accessed.
(6) External memory area
The µPD78322 can add external memories (ROM, RAM) to the 48K-byte (4000H to FFFFH) area gradually.
The µPD78320 can connect external memories (ROM, RAM) to the 64K-byte (0000H to FFFFH) area.
Each external memory can be accessed using P40/AD0 to P47/AD7 (multiplexed address/data bus), P50/A8 to P57/
A15 (address bus) and RD, WR and ASTB signals.
The external access area is mapped in the FFD0H to FFDFH 16-byte area of the special function register (SFR). In
this way, the external memory can be accessed by SFR addressing.
Dedicated pins (TAS and TMD pins) are provided to connect turbo access manager (µPD71P301)Note
. If the
µPD71P301 is used, the program processing speed equal to that of the internal ROM can be obtained.
Note Maintenance product
18
Figure 2-1. Memory Map
EA = L
• µPD78320
EA = H
(µPD78322)
• µPD78322 ROM-Less Mode
FFFFH
Special Function Register
(SFR)
FEFFH
General Register
(256 × 8)
FF00H
FEFFH
(128 × 8)
FE80H
FE2BH
Main RAM
(256 × 8)
Macro Service Control
(36 × 8)
FE00H
FDFFH
FE06H
Data Memory
Peripheral RAM
Data Area
(384 × 8)
(640 × 8)
FC80H
3FFFH
FC80H
FC7FH
Memory Space
Program Area
(64K × 8)
Program Memory
Data Memory
External MemoryNote
1000H
0FFFH
(48256 × 8)
External Memory
(64640 × 8)
CALLF Instruction Entry Area
(2048 × 8)
0800H
07FFH
4000H
3FFFH
Program Area
0080H
007FH
0FFFH
CALLT Instruction Table Area
(64 × 8)
Program Memory
Data Memory
Internal ROM
(16384 × 8)
0040H
003FH
µ
Vector Table Area
(64 × 8)
0000H
0000H
0000H
Note Accessed in external memory expansion mode.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address
that specifies the operand must be an even value.
µPD78320, 78322
2.2 PROCESSOR REGISTERS
The processor registers consist mainly of three groups. They are general registers consisting of 8 banks of sixteen 8-
bit registers, control registers consisting of one 8-bit register and three 16-bit registers, and special function registers such
as peripheral hardware I/O mode registers.
Figure 2-2. Register Configuration
Control Registers
15
0
P
C
PSW
S
P
7
0
CCW
General Registers
7
0
7
0
R 1
R 3
R 0
R 2
R 5
R 4
R 7
R 6
R 9
R 8
R 11
R 13
R 15
R 10
R 12
R 14
Special Function Registers
7
0
7
0
SFR 255
SFR 254
SFR 252
SFR 250
SFR 248
SFR 253
SFR 251
SFR 249
SFR 1
SFR 0
Remark The CCWs of the control registers are mapped in the special function register (SFR) area.
20
µPD78320, 78322
2.2.1 Control Register
The control registers carry out dedicated functions such as control of the program sequence, status and stack memory,
and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register.
(1) Program counter (PC)
This is a 16-bit register which holds the address information of the next program to be executed. It is normally
incremented according to the number of bytes of the instruction to be fetched. If an instruction with data branch is
executed, immediate data and the register content are set. RESET input sets and branches the data of 0000H and 0001H
reset vector tables in the PC.
(2) Program status word (PSW)
This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/
write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be manipulated
using the bit manipulation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically
saved in the stack and is recovered by RETI or RETB instruction.
All bits are reset to 0 by RESET input.
Figure 2-3. PSW Format
7
6
5
4
3
0
2
0
1
0
0
0
PSWH
PSWL
UF
RBS2 RBS1 RBS0
7
6
Z
5
4
3
2
1
0
S
RSS
AC
IE
P/V
LT
CY
(a) Interrupt priority level transition flag (LT)
This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must not
be manipulated by a program.
(b) Carry flag (CY)
If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated
into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional
branch instruction.
When a bit manipulation instruction is executed, this flag functions as a bit accumulator.
(c) Zero flag (Z)
When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested
by the conditional branch instruction.
(d) Sign flag (S)
When MSB of the operation result is “1”, this flag is set to 1. When the MSB is “0”, this flag is reset to 0. This flag
can be tested by the conditional branch instruction.
(e) Parity/overflow flag (P/V)
Only when an overflow or underflow occurs as two’s complement during execution of an arithmetic operation
instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation).
If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag
is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation).
This flag can be tested by the conditional branch instruction.
21
µPD78320, 78322
(f) Auxiliary carry flag (AC)
If a carry is generated out of bit 3 as a result of operation or a borrow is generated into bit 3, this flag is set to 1. In
all other cases, this flag is reset to 0. This flag can be tested by the conditional branch instruction.
(g) Register set select flag (RSS)
This flag is used to specify general registers which function as X, A, C and B. As shown in Table 2-1, the RSS value
determines the relationship between the functional register and the absolute register.
Thus, another register set (X, A, C, B) can be used by switching the RSS flag.
(h) Interrupt request enable flag (IE)
This flag is used to indicate interrupt request enable/disable. This flag is set to 1 by execution of EI instruction and
is reset to 0 by execution of DI instruction or acceptance of an interrupt.
(i) Register bank select flag (RBS0 to RBS2)
This is a 3-bit flag to select one of eight register banks (RBANK0 to RBANK7).
(j) User flag (UF)
This flag is set or reset in the user program and can be used for program control.
(3) Stack pointer (SP)
This is a 16-bit register which holds the first address of the stack area (LIFO format) of the memory. It is manipulated
by a dedicated instruction.
SP is decremented before write (save) operation into the stack memory and is incremented after read (restore)
operation from the stack memory.
Since SP becomes indeterminate by RESET input, it must be set before subroutine call, etc..
22
µPD78320, 78322
(4) CPU control word (CCW)
This is an 8-bit register consisting of CPU control related flags. It is mapped in the special function register area and
can be controlled by the software. All bits are reset to 0 by RESET input.
Figure 2-4. CCW Format
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
TPF
CCW
• Table position flag (TPF)
This flag is used to specify the interrupt vector table area and the memory area used as CALLT instruction table area.
As TPF has been reset to 0 after application of RESET input, the 0000H to 007FH address is used as each table area.
The 8002H to 807FH address of the external memory area in place of 0002H to 007FH address can be used as each
table area by setting TPF to 1 using the software. The vector tables of the BRK instruction, operation code trap interrupt
and reset input are fixed to 003EH, 003CH and 0000H, respectively, and they are not affected by TPF.
2.2.2 General Registers
These are 128-byte registers mapped in the special area (FE80H to FEFFH) of the internal RAM space. They consist
of eight register banks. The general register in the bank consists of sixteen 8-bit registers.
Figure 2-5. General Register Memory Location
16-Bit Processing
8-Bit Processing
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
R15
R13
R11
R9
R14
R12
R10
R8
(FH)
RP7
(EH)
(CH)
(AH)
(8H)
(6H)
(4H)
(2H)
(0H)
FEFFH
(DH) RP6
(BH)
(9H)
(7H)
(5H)
(3H)
(1H)
RP5
RP4
RP3
RP2
RP1
RP0
R7
R6
R5
R4
R3
R2
R1
R0
FE80H
15
0
7
0 7
0
23
µPD78320, 78322
The sixteen 8-bit registers can function as eight 16-bit register pairs (RP0 to RP7) as well.
As shown in Table 2-1, the sixteen 8-bit registers are characterized by functional names. The X register functions as
the lower half of the 16-bit accumulator, the A register functions as the upper half of the 8-bit or 16-bit accumulator, the B
and C registers function as counters, and DE, HL, VP and UP function as address register pairs. In particular the VP register
functions as a base register and the UP register functions as a user stack pointer.
The unique function register changes as shown in Table 2-1 according to the value of the register set select flag (RSS)
in the PSW.
Thus, if the program is described by the functional name, another register set of X, A, C and B can be used by means
of the RSS flag.
The µPD78322 can carry out processed data addressing operations, implied addressing by functional names with
importance attached to the unique function of each register and register addressing by absolute names with a view to fast
processing with a small number of data transfers or creating highly descriptive programs.
Table 2-1. General Register Configuration
Absolute
Name
Functional Name
Absolute
Name
Functional Name
RSS = 0
RSS = 1
RSS = 0
RSS = 1
R0
R1
X
A
C
B
RP0
RP1
RP2
RP3
RP4
RP5
RP6
RP7
AX
BC
R2
AX
BC
VP
UP
DE
HL
R3
R4
X
A
VP
UP
DE
HL
R5
R6
C
R7
B
R8
VPL
VPH
UPL
UPH
E
VPL
VPH
UPL
UPH
E
R9
R10
R11
R12
R13
R14
R15
D
D
L
L
H
H
24
µPD78320, 78322
2.2.3 Special Function Registers (SFR)
These registers are provided with special functions. They include various peripheral hardware mode registers and control
registers (CCW).
The special function registers are assigned in the FF00H to FFFFH 256-byte space. Short direct memory addressing
is applied to the FF00H to FF1FH 32-byte area for processing with a short word length.
The bit manipulation, arithmetic and transfer instructions can be executed in all areas. The FFD0H to FFDFH 16-byte
area is externally accessible by SFR addressing. Thus, the external memory can be accessed and the external device bit
manipulation can be carried out by an instruction having a short word length.
Table 2-2 lists the special function registers (SFR). The items in the table have the following meanings.
• Symbol................. Indicates the address of the built-in special function register.
Can be described in the instruction operand column.
• R/W.......................Indicates if the corresponding special function register can read or write.
R/W : Read/write enable
R
: Read only enable (register bit test enable)
: Write only enable
W
• Manipulable bit unit
....................... Indicates the applicable manipulation bit unit for the corresponding special function
register.
16-bit manipulable SFR can be described in operand sfrp. When specified by an address,
an even address is described.
1-bit manipulable SFR can be described by the bit manipulation instruction.
• On reset ...............Indicates the state of each register when RESET is input.
Cautions 1. Addresses for which no special function registers have been assigned cannot be accessed in the
FF00H to FFFFH area.
2. Do not write to the read only register. If data is written, the internal circuit may malfunction.
25
µPD78320, 78322
Table 2-2. List of Special Function Registers (1/4)
Manipulable Bit Unit
Address
Symbol
R/W
On Reset
Special Function Register (SFR) Name
Port 0
16 bits
––
1 bit
8 bits
●
●
FF00H
FF02H
FF03H
FF04H
FF05H
FF07H
FF08H
FF09H
FF0AH
FF0BH
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF20H
FF23H
FF25H
FF28H
FF29H
FF2AH
FF2BH
FF2CH
FF2DH
FF30H
FF31H
FF32H
FF33H
FF34H
FF35H
P0
P2
P3
P4
P5
P7
P8
P9
R/W
R
––
●
●
●
––
●
●
●
●
●
●
●
●
●
Port 2
––
Port 3
Port 4
R/W
––
––
Undefined
Port 5
Port 7
R
Port 8
––
R/W
Port 9
Free running counter
TM0LW
CTX0LW
CT01LW
CT02LW
CT03LW
––
––
●
●
●
●
0000H
Note
(lower 16 bits)
Capture register X0
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
––
●
Note
(lower 16 bits)
Capture register 01
R
Note
(lower 16 bits)
Capture register 02
Note
(lower 16 bits)
Undefined
Capture register 03
●
●
●
Note
(lower 16 bits)
Capture/compoare register X0
CCX0LW
CC01LW
Note
(lower 16 bits)
R/W
Capture/compoare register 01
Note
(lower 16 bits)
Port 0 mode register
Port 3 mode register
Port 5 mode register
Port 8 mode register
Port 9 mode register
Free runnting counter
––
––
––
––
––
PM0
PM3
PM5
PM8
PM9
FFH
●
× × ×1 1111B
FFH
●
W
●
× × 11 1111B
× × × × 1111B
●
––
––
––
––
––
––
––
––
––
––
●
TM0UW
TM1
Note
(higher 16 bits)
0000H
Timer register 1
●
●
Capture register X0
CTX0UW
CT01UW
CT02UW
R
Note
(higher 16 bits)
Capture register 01
Undefined
●
●
Note
(higher 16 bits)
Capture register 02
Note
(higher 16 bits)
Note Upper or lower half of 18-bit register.
26
µPD78320, 78322
Table 2-2. List of Special Function Registers (2/4)
Manipulable Bit Unit
Address
Symbol
CT03UW
CCX0UW
CC01UW
R/W
R
On Reset
Undefined
00H
Special Function Register (SFR) Name
Capture register 03
16 bits
1 bit
––
8 bits
––
FF36H
FF37H
FF38H
FF39H
FF3AH
FF3BH
FF40H
FF41H
FF43H
FF48H
FF4CH
FF4DH
FF60H
FF61H
FF62H
FF68H
●
Note
––
––
––
––
––
––
●
––
––
––
––
●
●
●
●
––
––
––
––
––
●
●
●
●
––
––
●
●
●
●
(higher 16 bits)
Capture/compoare register X0
●
●
Note
(higher 16 bits)
R/W
Capture/compoare register 01
Note
(higher 16 bits)
––
––
––
––
Port 0 mode control register
Realtime output port set register
Port 3 mode control register
Port 8 mode control register
PMC0
RTPS
PMC3
PMC8
W
R/W
× × ×0 0000B
× ×00 0000B
W
●
Baud rate generator
BRG
Undefined
00H
––
––
––
––
Realtime output port register
Realtime output port reset register
Port read control register
A/D converter mode register
A/D conversion result register
(for 16-bit access)
RTP
RTPR
PRDC
ADM
R/W
●
ADCR
ADCRH
CM00
––
––
––
FF6AH
FF6BH
R
A/D conversion result register
(for upper 8-bit access)
●
––
––
––
––
––
––
––
FF70H
FF71H
FF72H
FF73H
FF74H
FF75H
FF76H
FF77H
FF7CH
FF7DH
FF7EH
FF7FH
FF80H
FF82H
FF86H
R/W
●
Compare register 00
CM01
Compare register 01
Compare register 02
Compare register 03
●
●
––
––
––
––
––
––
––
––
––
●
––
––
––
––
––
––
––
––
––
●
Undefined
CM02
CM03
●
●
Compare register 10
Compare register 11
CM10
CM11
R/W
●
Clocked serial interface mode register
Serial bus interface control register
Serial I/O shift register
CSIM
SBIC
SIO
––
––
––
00H
●
●
Undefined
●
●
Note Upper or lower half of 18-bit register.
27
µPD78320, 78322
Table 2-2. List of Special Function Registers (3/4)
Manipulable Bit Unit
Address
Symbol
ASIM
ASIS
R/W
R/W
On Reset
80H
Special Function Register (SFR) Name
16 bits
––
1 bit
8 bits
Asynchronous serial interface mode
●
●
FF88H
FF8AH
register
Asynchronous serial interface status
register
●
●
00H
––
R
––
––
––
––
––
––
––
––
––
––
––
––
––
––
FF8CH
FF8EH
FFB0H
FFB1H
FFB2H
FFB8H
FFB9H
FFBFH
FFC0H
FFC1H
FFC2H
FFC4H
FFC6H
FFC9H
Serial receive buffer
:UART
:UART
RXB
TXS
––
––
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Undefined
Serial send shift register
Timer control register
W
TMC
Baud rate generator mode register
Prescalar mode register
BRGM
PRM
TOC0
TOC1
RPUM
STBC
CCW
WDM
MM
00H
R/W
Timer output control register 0
Timer output control register 1
RPU mode register
Note
Standby control register
0000 × 000B
R/W
CPU control word
R/W
Note
Watchdog timer mode register
Memory expansion mode register
Programmable wait control register
Fetch cycle control register
R/W
00H
22H
00H
PWC
FCC
FFD0H to
FFDFH
FFE0H
FFE1H
FFE2H
FFE3H
FFE4H
FFE5H
FFE6H
FFE7H
FFE8H
FFE9H
FFEAH
FFEBH
FFECH
FFEDH
FFEEH
FFEFH
––
Undefined
●
●
External acces area
Interrupt request flag rgister 0L
Interrupt request flag rgister 0H
Interrupt request flag rgister 1L
––
IF0L
●
●
●
––
●
●
●
––
IF0
IF1
●
IF0H
IF1L
––
00H
●
––
Interrupt mask flag rgister 0L
Interrupt mask flag rgister 0H
Interrupt mask flag rgister 1L
MK0L
MK0H
MK1L
––
●
●
●
––
●
●
●
––
MK0
MK1
R/W
FFH
●
●
× × × × × 111B
––
––
Priority specify bufer register 0L
Priority specify bufer register 0H
Priority specify bufer register 1L
––
PB0L
PB0H
PB1L
––
●
●
●
––
●
●
●
––
●
●
●
––
●
●
●
––
PB0
PB1
●
●
00H
––
Interrupt servicing mode specify register 0L
Interrupt servicing mode specify register 0H
Interrupt servicing mode specify register 1L
––
ISM0L
ISM0H
ISM1L
––
●
●
ISM0
ISM1
00H
––
Note Write enable in case of special instructions.
28
µPD78320, 78322
Table 2-2. List of Special Function Registers (4/4)
Manipulable Bit Unit
Address
Symbol
R/W
On Reset
Special Function Register (SFR) Name
16 bits
1 bit
8 bits
●
●
FFF0H
FFF1H
FFF2H
FFF3H
FFF4H
FFF5H
FFF8H
FFF9H
Context switching enable register 0L
Context switching enable register 0H
Context switching enable register 1L
––
CSE0L
●
CSE0
CSE1
●
●
––
●
●
––
●
●
●
––
●
●
●
●
00H
––
CSE0H
CSE1L
––
●
R/W
External interupt mode register 0
External interupt mode register 1
In-service priority register
––
––
INTM0
INTM1
ISPR
00H
R
––
––
Priority specify register
PRSL
R/W
2.3 DATA MEMORY ADDRESSING
In the µPD78322, the internal RAM space (FC80H to FEFFH) and the special function register area (FF00H to FFFFH)
are mapped in the FC80H to FFFFH area. In the FE20H to FF1FH space of the data memory, short direct addressing enables
direct addressing by 1-byte data in an instruction word.
Figure 2-6. Data Memory Addressing
FFFFH
Special Function Register
(SFR)
SFR Addressing
FF1FH
FF00H
FEFFH
General Register
Register Addressing
Short Direct Addressing
FE80H
FE20H
Main RAM
FE00H
FDFFH
Peripheral RAM
Direct Addressing
Register Indirect Addressing
FC80H
Based Addressing
Based Indexed Addressing
Based Indexed Addressing
(Provided with Displacement)
External Memory
3FFFH
Internal ROMNote
0000H
Note When EA = L, or with the µPD78320, this is external memory.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the address that
specifies the operand must be an even value.
29
µPD78320, 78322
2.3.1 General Register Addressing
The general registers consist of eight register banks, each consisting of sixteen 8-bit registers or eight 16-bit registers.
General register addressing is carried out using the register specify field of 3 or 4 bits supplied from an instruction word,
the register bank select flag (RBS0 to RBS2) and the register set select flag (RSS) in the PSW.
2.3.2 Short Direct Addressing
Short direct addressing which enables direct address specification by 1-byte data in an instruction word is applied to the
FE20H to FF1FH space. The short direct memory is accessed as 8-bit or 16-bit data. When accessing the memory as 16-
bit data, specification of even data for 1-byte address specify data will cause 2-byte data specified by continuous addresses
of even and odd addresses to be accessed. (Do not specify odd number for address specify data.)
2.3.3 Special Function Register (SFR) Addressing
This addressing is applied to operations for the special function register (SFR) mapped in the SFR area of FF00H to
FFFFH. Addressing is performed by 1-byte data in the instruction word corresponding to the lower 8 bits of the special
function register address. For 16-bit access of 16-bit manipulable SFR, 2-byte data specified by continuous even and odd
addresses is accessed as is the case with short direct addressing.
30
µPD78320, 78322
3. BLOCK FUNCTIONS
3.1 BUS CONTROL UNIT (BCU)
In the BCU, the necessary bus cycle is started according to the physical address obtained by the execution unit (EXU).
If no bus cycle startup request is made from the EXU, a prefetch address is generated and instruction prefetch is carried
out. The prefetched operation code is fetched into the instruction queue.
3.2 EXECUTION UNIT (EXU)
In the EXU, address calculation, arithmetic logical operation and data transfer are controlled by microprograms. A 256-
byte RAM is built in the EXU.
The 256-byte main RAM in the EXU is accessible by the relevant instruction faster than peripheral RAM (384 bytes).
3.3 ROM/RAM
This block consists of a 16K-byte ROM and a 384-byte peripheral RAM. However, the µPD78320 does not incorporate
ROM.
ROM access can be disabled by EA pin.
3.4 INTERRUPT CONTROLLER
Various interrupt requests (NMI, INTP0 to INTP6) generated either externally or from the peripheral hardware are
serviced by the context switch, vectored interrupt or macro service function.
The 3-level interrupt priority is also specified.
31
µPD78320, 78322
3.5 PORT FUNCTIONS
Table 3-1 lists the digital input/output ports.
Each port can carry out many control operations including 8 and other bit data input/output manipulations.
Table 3-1. Port Functions and Features
Port Name
Port 0
Function
Feature
Remarks
Specifiable bit-wise for input/output.
Dual-function as pins
RTP0 to RTP7
8-bit input/outpput
Also specifiable for realtime output port..
Dual-function as pins NMI,
INTP0 to INTP5, INTP6/TI
Port 2
Port 3
8-bit input
Input port pin. Functions as an external interrupt input.
Specifiable bit-wise for port pins or control pins.
Dual-function as pins
TXD, RXD, SO/SB0, SI/SB1,
SCK
5-bit input/output
Specifiable in 8-bit units for input or output.
Port 4
Port 5
8-bit input/output
8-bit input/output
Functions as the multiplexed address/data bus (AD0 to
AD7) in the external memory expansion mode.
––––––––
––––––––
Specifiable bit-wise for input or output.
Functions as the address bus (A8 to A15) in the external
memory expansion mode.
Pins which are not used as the address bus can be used
as a port.
Input port pin. Also functions as analog input to the
A/D converter.
Dual-function as pins
AN0 to AN7
Port 7
Port 8
8-bit input
Dual-function as pins
TO00 to TO03, TO10 to
TO11
6-bit input/output
Specifiable bit-wise for the port pin or control pin.
Specifiable bit-wise for input/output.
P90 and P91 function as RD output and WR output,
respectively, in the external memory expansion mode.
P92 and P93 function as TAS output and TMD output,
respectively, in the external memory high-speed fetch
mode.
––––––––
Port 9
4-bit input/output
32
µPD78320, 78322
3.6 CLOCK GENERATOR
The clock generator generates and controls internal system clocks (CLK) supplied to the CPU.
It is configured as shown in Figure 3-1.
Figure 3-1. Clock Generator Block Diagram
X1
Divider
System
Clock
Generator
f
XX or f
X
f
CLK
Internal System
Clock (CLK)
1/2
X2
STOP Mode
Remarks 1. fXX : Crystal oscillator frequency
2. fX : External clock frequency
3. fCLK : Internal system clock frequency
The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set
to the standby mode (STOP).
External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input
the inverted clock signal to the X2 pin. The X2 pin can also be left open.
Caution When using external clocks, do not set the STBC STP bit.
The divider generates internal system clocks (fCLK) by dividing a system clock oscillator output (fxx for crystal oscillation
and fx for external clocks) into two parts.
33
µPD78320, 78322
Figure 3-2. Externally-Mounted System Clock Oscillator
(a) Crystal oscillator
µ PD78322
X2
X1
VSS
(b) External clock
(i) When the inverted phase of an external clock
to be input to the X1 pin is input to the X2 pin
(ii) When X2 pin is left open
µ PD78322
µ PD78322
External
Clock
X1
External
X1
Clock
Open X2
X2
Cautions 1. When the system clock oscillator is used, the following points should be noted concerning wiring
within broken lines shown in Figure 3-2, in order to prevent the effects of wiring capacitance, etc.
• Keep the wiring as short as possible.
• Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows.
• Ensure that oscillator capacitor connection points are always at the same potential as VSS.
Do not ground in a ground pattern in which a high current flows.
• Do not take a signal from the oscillator.
2. When an external clock is input to the X1 pin and the X2 pin is left open, ensure that no loads such
as wiring capacitance are connected to the X2 pin.
34
µPD78320, 78322
3.7 REALTIME PULSE UNIT (RPU)
This unit can measure pulse intervals and frequencies, and generate programmable pulse outputs.
It consists mainly of two timers. To flexibly cope with many applications, the configuration of registers connected to the
timers can be changed using programs. To meet various applications, toggle output (6 max.) or set/reset output (4 max.)
can be selected as timer output.
3.7.1 Configuration
The realtime pulse unit is configured mainly of timer 0 (TM0) which functions as a 16-bit or 18-bit free running timer and
timer 1 (TM1) which functions as a 16-bit timer/event counter shown in Figure 3-3.
35
Figure 3-3. Realtime Pulse Unit Configuration
TM0
TM1
INTOV
2
(CLEAR CONTROL)
INTP0
(OPPOSITE EDGE)
10 11
15
17
INTP6/TI
f
f
CLK/4
CLK/8
OVF
OVF
f
CLK/16
16-BIT TIMER/EVENT COUNTER
16/18-BIT FREE RUNNING TIMER
0
INTCM00
T
TO00
TO01
S
R
COMPARE REG. CM00
COMPARE REG. CM01
COMPARE REG. CM02
COMPARE REG. CM03
INTCM01
T
INTCM02
INTCM03
S
R
T
TO02
TO03
S
R
Match
INTCM10
COMPARE REG. CM10
COMPARE REG. CM11
INTCM11
Match
T
INTP0
CAPTURE REG. CT01
CAPTURE REG. CT02
CAPTURE REG. CT03
T
TO11
TO10
INTP1
INTP2
INTP3
R
S
INTCCX0
T
INTCC01
INTP5
CAPTURE/COMPARE REG. CC01
Match
MODE0
MODE1
µ
INTP0
INTP0
INTP4
CAPTURE REG. CTX0
INTCCX0
Match
CAPTURE/COMPARE REG. CCX0
µPD78320, 78322
3.7.2 Realtime Output Function
The realtime output port can set/reset port outputs bit-wise in synchronization with the trigger signal transmitted from
the RPU (Realtime Pulse Unit). It enables to generate multi-channel synchronous pulses easily.
Figure 3-4. Realtime Output Port
WRPORT
PMC0 = 0
n
P0n
Output Latch
INTCM03
WRRTPR
RTP
n
R
RTPR
n
WRPTP
PMC0 = 1
n
D
S
Q
P0n
WRRTPS
RTPS
n
PM0 = 0
n
INTCCX0
RD
PM0 = 1
n
37
µPD78320, 78322
3.8 A/D CONVERTER
The µPD78322 incorporates a high-speed, high-resolution 10-bit analog/digital (A/D) converter. This A/D converter is
equipped with eight analog inputs (AN0 to AN7) and A/D conversion result register (ADCR) which holds the conversion
results.
Upon termination of conversion, the interrupt which can start the macro service is generated.
Figure 3-5. A/D Converter Block Diagram
Sample & Hold Circuit
AVREF
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
D/A Converter
AVSS
Comparator
ADM (8)
8
SAR (10)
10
10
Internal Bus
ADCR (10)
10
Internal Bus
3.9 SERIAL INTERFACE
The µPD78322 is equipped with the following two independent channels for the serial interface function.
•
•
Asynchronous serial interface
Clocked serial interface
•
•
3-wire serial I/O mode
Serial bus interface mode (SBI mode)
Since the µPD78322 incorporates a baud rate generator, it can set any serial transfer rate irrespective of the operating
frequency. The baud rate generator functions for the 2-channel serial interface in common.
The serial transfer rate can be selected from 75 bps to 19.2 Kbps by setting the mode register.
38
Figure 3-6. Asynchronous Serial Interface Block Diagram
Internal Bus
ASIM
RXE PS1 PS0 CL SL SCK
RXB
Receive Buffer
Shift Register
BRG
BRGM
ASIS
Match
TXS
1
2
R
T
X
D
D
PE FE OVE
Shift Register
Clear
X
Receive
Control
Parity
fCLK/8
Send Control
Parity
Addition
INTSER
INTST
Check
INTSR
µ
1
1
16
16
Send/Receive Baud Rate Generator Output
Baud Rate Generator
f
CLK/4
Figure 3-7. Block Diagram of Clocked Serial Interface
Internal Bus
8
8
CSIM
SBIC
RELT CMDT RELD CMDD ACKT ACKE ACKD BSYE
MOD2 CTXE CRXE WUP MOD1 CLS1 CLS0 MOD0
SET
CLEAR
SO Latch
SI/SB1
Shift Register SIO
D
Q
SO/SB0
Busy/
Acknowledge
Detector
N-ch Open-Drain
Output Enable
Bus Release/
Command/Acknowledge
Detector
Interrupt
Signal
Generation
Controller
Serial Clock
Counter
SCK
INTCSI
Baud Rate Generator
Output
µ
f
CLK/8
Serial Clock
Controller
MPX
f
CLK/32
CLS1CLS0
µPD78320, 78322
3.10 WATCHDOG TIMER
The watchdog timer is used to prevent program overrun and deadlock. Normal operation of the program or system can
be confirmed by checking that no watchdog timer interrupt has been generated. Thus, an instruction to clear the watchdog
timer (timer start) is set into each program module.
If the watchdog timer clear instruction is not cleared within the time period set into the watchdog timer and the watchdog
timer overflows, a watchdog timer interrupt is generated, and a low level is generated to WDTO pin, thereby notifying of
an error in the program.
The watchdog timer can also be used to maintain the oscillation stabilization time of the oscillator after the stop mode
has been released.
Figure 3-8 shows the watchdog timer configuration.
Figure 3-8. Watchdog Timer Configuration
f
CLK/28
Overflow
f
f
CLK/210
CLK/212
Watchdog Timer (8 Bits)
WDTO
Timer (5 Bits)
INTWDT
Clear
WDT CLR
WDT STOP
Oscillation Stabilization
Time Controller
41
µPD78320, 78322
4. INTERRUPT FUNCTIONS
4.1 OVERVIEW
In the µPD78322, various interrupt requests generated externally or from the on-chip peripheral hardware are handled
in the following three servicing modes.
Interrupt Request
Handled by Vectored Interrupt Servicing
Handled by Context Switching
Handled by Macro Service
Interrupt requests are classified into the following three groups.
• Nonmaskable interrupt requests
• Maskable interrupt requests
• Interrupt requests by software
Figure 4-1 shows the maskable interrupt request servicing modes. Table 4-1 gives a listing of interrupt factors which can
be serviced.
Figure 4-1. Interrupt Request Servicing Modes
× × MK = 1 (Interrupt Masked)
Vectored Interrupt and Macro Service Reserved
× × MK = 0 (Interrupt Unmasked)
× × ISM = 0 (Vectored Interrupt Servicing Mode)
DI
EI
Vectored Interrupt Servicing Reserved
× × CSE = 0 Vectored Interrupt Servicing Executed
× × CSE = 1 Context Switching Executed
× × ISM = 1 (Macro Service Processing Mode)
Macro Service Processing Executed
42
µPD78320, 78322
Table 4-1. List of Interrupt Factors
Interrupt
Default
Interrupt Factor
Function
Generator
Unit
Macro
Vector Table
Address
Request Type Priority
Request Signal
Servicez
–––
–––
–––
BRK instruction
–––
–––
–––
–––
003EH
003CH
Software
–––
Operation code trap
(External
interrupt)
–––
0002H
–––
–––
NMI
NMI pin input
Non-
maskable
–––
INTWDT
INTOV
INTP0
INTP1
INTP2
INTP3
Watchdog timer
Timer 0 overflow
INTP0 pin input
INTP1 pin input
INTP2 pin input
INTP3 pin input
(WDT)
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0024H
0026H
0028H
002AH
0
1
2
3
4
5
6
7
(RPU)
(External)
(External)
(External)
(Exteranl)
(RPU/exteranl)
(RPU/exteranl)
(Exteranl)
(RPU)
INTP4/INTCCX0 INTP4 pin input/CCX0 match signal
INTP5/INTCC01 INTP5 pin input/CC01 match signal
INTP6/TI
INTCM00
INTCM01
INTCM02
INTCM03
INTCM10
INTCM11
INTSR
INTP6 pin input/TI input
CM00 match signal
8
Maskable
Available
9
CM01 match signal
(RPU)
10
11
12
13
14
15
16
17
CM02 match signal
(RPU)
CM03 match signal
(RPU)
CM10 match signal
(RPU)
CM11 match signal
(RPU)
Serial receive terminate interrupt
Serial send terminate interrupt
Serial send/receive interrupt
A/D conversion terminate interrupt
Serial receive error signal
Reset input
(UART)
(UART)
(CSI)
INTST
INTCSI
INTAD
(A/D)
Note
Note
–––
–––
–––
INTSER
RESET
(UART)
–––
–––
–––
–––
Reset
0000H
Note This is a test factor. A vectored interrupt is not generated.
43
µPD78320, 78322
4.2 MACRO SERVICE
The macro service function is executed at the interrupt request to carry out data operation and data transfer in hardware
terms between the special function register area and the memory space.
Upon startup of the macro service, the CPU stops program execution temporarily. 1-byte/2-byte data operation, transfer,
etc. are automatically carried out between the special function register (SFR) and the memory. Upon termination of the macro
service, the interrupt request flag is reset to 0 and the CPU restarts program execution. When the CPU carries out the macro
service operations as many as set into the macro service counter (MSC), a vectored interrupt request is generated after
completion.
Figure 4-2. Macro Service Processing Sequence Example
Macro Service Processing
Interrupt Request Generated
; Data Transfer, and Realtime
Macro service execution
Output Port Control
; Macro Service Counter (MSC)
Decrement (by –1)
MSC ← MSC–1
Yes
No
MSC = 0?
ISM×× ← 0
Interrupt request flag ← 0
Vectored Interrupt Request Occurred
Next Instruction Executed
44
µPD78320, 78322
4.3 CONTEXT SWITCHING FUNCTION
This is the function to first select the specified register bank in hardware terms by generating an interrupt request or
executing BRKCS instruction, to branch the selected register bank to the vector address prestored in the register bank, and
also to stack the current PC and PSW contents into the register bank.
4.3.1 Context Switching Function by Interrupt Request
The context switching function start is enabled by setting the × ×CSE bit preset at each interrupt request to 1.
If an unmasked interrupt request for which the context switching function has been enabled is generated in the EI state,
the register bank which is specified by the lower 3 bits of the low address (even address) of the corresponding interrupt
vector table address is selected. The vector address prestored in the selected register bank is transferred to the PC, the
PC and PSW contents are saved into the register bank, and the operation is branched to the interrupt service routine.
Return is by means of executing the RETCS instruction.
Figure 4-3. Context Switching by Interrupt Request Generation
Register
Banks
(0 – 7)
RBANK
n
A
X
C
B
PC
R5
R7
R4
R6
Exchange
Save
VP
UP
PSW
D
H
E
L
45
µPD78320, 78322
4.3.2 Context Switching Function by BRKCS Instruction
The context switching function can be started by executing BRKCS instruction.
The context switched register bank is specified by the lower 3-bit immediate data of the 2nd operation code of BRKCS
instruction. When BRKCS instruction is executed, the register bank specified by the 3-bit immediate data is selected, the
vector address prestored in the register bank is set and branched to the PC, and the PC and PSW contents are saved into
the register bank.
Return is by means of executing the RETCSB instruction.
Figure 4-4. Context Switching by Execution of BRKCS Instruction
OP CODE
(BRKCS)
OP CODE
N2 N1
N0
Register Bank Specification
RBANK0
000
111
RBANK7
Register
Banks
(0 – 7)
RBANK
n
(n = 0 – 7)
A
X
C
B
PC
R5
R7
R4
R6
Exchange
Save
VP
UP
PSW
D
H
E
L
46
µPD78320, 78322
5. STANDBY FUNCTIONS
The µPD78322 has the standby function to decrease the power consumption of the system. The following two modes
are available for execution of the standby function.
• HALT mode ........ Mode for halting the CPU operation clock. The total power consumption of the
system can be decreased by intermittent operation in combination with the normal
operating mode.
• STOP mode ....... Mode for stopping the whole system by stopping the oscillator. Considerably low
power consumption with leak current only can be set.
Each mode is set by the software. Figure 5-1 shows standby mode (STOP/HALT mode) transition.
Figure 5-1. Standby Status Transition
Normal
Status
STOP Set
Unmasked
Interrupt
Generated
NMI
HALT
STOP
47
µPD78320, 78322
6. EXTERNAL DEVICE EXPANSION FUNCTION
The µPD78322 can expand external devices (data memory, program memory or peripheral device) for areas (4000H
to FFFFH) except the internal ROM and RAM areas. Tables 6-1 through 6-3 shows the pin used for external device access
and the pin function setting procedure.
Table 6-1. Pin Function Setting (µPD78322)
Memory Expansion
Mode Register
Fetch Cycle
Control
Pin Function
EA Pin
Remarks
P40 to P47
P50 to P57
P90
P91
WR
P92
P93
Register
MM0 to MM2 MM7
0
General port
00H
Port mode
1
Setting prohibited
General-
External device
1
0
00H
purpose port connection mode
Set to A8 to
A15 in steps
Expansion
AD0 to AD7
RD
mode
1
µPD71P301
Except 00H
TAS TMD
connection mode
For P50 to P57 pins, the number of bits which serve as address buses can be changed according to the externally
expanded memory size. The memory can be expanded in steps from 256 bytes to about 48K bytes. The pins which are
not used as the address bus can be used as the general-purpose input/output port.
Table 6-2. Port and Address Setting for Port 5 (µPD78322)
P57
Port
Port
Port
A15
P56
Port
Port
Port
A14
P55
Port
Port
A13
A13
P54
Port
Port
A12
A12
P53
Port
A11
A11
A11
P52
P51
P50
Port
A8
External Address Space
256 bytes or less
Port Port
A10
A10
A10
A9
A9
A9
4K bytes or less
A8
16K bytes or less
A8
About 48K bytes or less
Table 6-3. Setting Pin Function (µPD78320)
Memory Expansion
Mode Register
Fetch Cycle
Pin Function
Control
EA Pin
ASTB
Remarks
AD0 to AD7
AD to AD7
A8 to A15
RD
RD
WR
WR
P92
P93
Register
MM7
µPD78322
TAS TMD
emulation mode
General-
External device
A8 to A15
0
1
00H
purpose port
connection mode
0
µPD71P301
Except 00H
TAS TMD
connection mode
48
µPD78320, 78322
7. OPERATION AFTER RESET
If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status
(reset status). If RESET input becomes high level, the reset state is released and program execution is started. Initialize
the contents of various registers in the program as required.
Change the number of cycles for the programmable wait control register and the fetch cycle control register as required
in particular.
The RESET input pin is equipped with an analog delay noise eliminator to prevent malfunctioning due to noise.
Cautions 1. While RESET is active (low level), all pins remain high impedance (except WDTO, AVREF, AVDD, AVSS,
VDD, VSS, X1 and X2).
2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is
possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM
contents corruption. In addition, signals may collide on the address/data bus, resulting in the
destruction of the input/output circuit.
Figure 7-1. Reset Signal Acknowledge
RESET Input
Analog
Delay
Analog
Delay
Analog
Delay
Eliminated
as Noise
Reset
Acknowl-
edged
Reset
Release
For reset operation upon power-up, secure the oscillation stabilization time of about 40 msec from power-up to reset
acknowledge as shown in Figure 7-2.
Figure 7-2. Reset Upon Power-Up
VDD
RESET
Oscillation
Stabilization
Time
Analog
Delay
Reset
Release
49
µPD78320, 78322
8. INSTRUCTION SET
This chapter covers instruction operations.
For the operation codes and the number of instruction execution clock cycles, seeµPD78322 User’s Manual (IEU-1248).
(1) Operand identifier and description method
In each instruction operand field, enter the operand using the description method for the instruction operand identifier
(refer to the assembler specification for details). If two or more factors are included in the description method field, select
one factor. The capital alphabetic letters and +, -, #, $, ! and [ ] symbols are keywords and should be described as they
are.
In case of immediate data, describe appropriate numeric values or labels. When describing labels, make sure to
describe #, $, ! and [ ] symbols.
Table 8-1. Operand Identifier and Description Method
Identifier
Description Method
r
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15
r1
r2
R0, R1, R2, R3, R4, R5, R6, R7
C, B
rp
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
DE, HL, VP, UP
rp1
rp2
sfr
Special function register code (see Table 2-2)
sfrp
Special function register code (16-bit manipulation enable register; see Table 2-2)
RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7
post
(Two or more instructions can be described. Only PUSH and POP instructions can be
described for RP5 and only PUSHU and POPU instructions can be described for PSW.)
[DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP] ; Register indirect mode
[DE+A], [HL+A], [DE+B], [HL+B], [VP+DE], [VP+HL]
; Based indexed mode
mem
[DE+byte], [HL+byte], [VP+byte], [UP+byte], [SP+byte] ; Based mode
word[A], word[B], word[DE], word[HL]
; Indexed mode
saddr
FE20H to FF1FH immediate data or label
saddrp
FE20H to FF1EH immediate data (bit0 = 0) or label (for 16-bit manipulation)
$addr16
!addr16
0000H to FDFFH immediate data or label; relative addressing
0000H to FDFFH immediate data or label; immediate addressing
(Up to FFFFH describable by MOV instruction)
addr11
addr5
800H to FFFH immediate data or label
Note
40H to 7EH immediate data (bit0 = 0)
or label
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data (0 to 7)
n
Note Do not make word access to bit0 = 1 (odd address).
Remarks 1. Although rp and rp1 have the same describable register names, they generate different codes.
2. r, r1, rp, rp1 and post can be described with absolute names (R0 to R15, RP0 to RP7) as well as functional
names (X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, UP (see Table 2-1 for details of the relationships between
the absolute and functional names).
3. Immediate addressing is enabled for all spaces. Relative addressing is only enabled from the first address
of the subsequent instruction to the range of -128 to +127.
50
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
r1, #byte
2
3
3
2
1
2
2
3
2
2
r1 ← byte
(saddr) ← byte
sfr ← byte
r ← r1
saddr, #byte
Note
sfr
, #byte
r, r1
A, r1
A ← r1
A, saddr
saddr, A
saddr, saddr
A, sfr
A ← (saddr)
(saddr) ← A
(saddr) ← (saddr)
A ← sfr
sfr, A
sfr ← A
A, mem
1-4 A ← (mem)
1-4 (mem) ← A
MOV
mem, A
A, [saddrp]
[saddrp], A
A, !addr16
!addr16, A
PSWL, #byte
PSWH, #byte
PSWL, A
PSWH, A
A, PSWL
A, PSWH
A, r1
2
2
4
4
3
3
2
2
2
2
1
2
A ← ((saddrp))
((saddrp)) ← A
A ← (addr16)
(addr16) ← A
PSWL ← byte
PSWH ← byte
PSWL ← A
PSWH ← A
A ← PSWL
A ← PSWH
A ↔ r1
×
×
×
×
×
×
×
×
×
×
r, r1
r ↔ r1
A, mem
2-4 A ↔ (mem)
XCH
A, saddr
A, sfr
2
3
2
3
A ↔ (saddr)
A ↔ sfr
A, [saddrp]
saddr, saddr
A ↔ ((saddrp))
(saddr) ↔ (saddr)
Note
If STBC and WDM are described for sft, a different dedicated instruction having a different number of bytes
is used.
Remark For the symbols in the Flags column, refer to the table below.
Symbol
Description
(Blank)
No change
Clear to 0.
Set to 1.
0
1
×
Set/clear according to the result.
P/V flag operates as a parity flag
P/V flag operates as an overflow flag.
The previously saved value is restored.
P
V
R
51
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
rp1, #word
3
4
4
2
2
2
3
2
2
4
4
rp1 ← word
saddrp, #word
sfrp, #word
rp, rp1
(saddrp) ← word
sfrp ← word
rp ← rp1
AX, saddrp
saddrp, AX
saddrp, saddrp
AX, sfrp
AX ← (saddrp)
(saddrp) ← AX
(saddrp) ← (saddrp)
AX ← sfrp
MOVW
sfrp, AX
sfrp ← AX
rp1, !addr16
!addr16, rp1
AX, mem
mem, AX
AX, saddrp
AX, sfrp
rp1 ← (addr16)
(addr16) ← rp1
2-4 AX ← (mem)
2-4 (mem) ← AX
2
3
3
2
AX ↔ (saddrp)
AX ↔ sfrp
XCHW
saddrp, saddrp
rp,rp1
(saddrp) ↔ (saddrp)
rp ↔ rp1
AX, mem
A, #byte
2-4 AX ↔ (mem)
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
2
3
4
2
2
3
3
A, CY ← A + byte
saddr, #byte
sfr, #byte
r, r1
(saddr), CY ← (saddr) + byte
sfr, CY ← sfr + byte
r, CY ← r + r1
A, saddr
ADD
A, CY ← A + (saddr)
A, CY ← A + sfr
A, sfr
saddr, saddr
A, mem
(saddr), CY ← (saddr) + (saddr)
2-4 A, CY ← A + (mem)
mem, A
2-4 (mem), CY ← (mem) + A
A, #byte
2
3
4
2
2
3
3
A, CY ← A + byte + CY
saddr, #byte
sfr, #byte
r, r1
(saddr), CY ← (saddr) + byte + CY
sfr, CY ← sfr + byte + CY
r, CY ← r + r1 + CY
ADDC
A, saddr
A, CY ← A + (saddr) + CY
A, CY ← A + sfr + CY
A, sfr
saddr, saddr
A, mem
(saddr), CY ← (saddr) + (saddr) + CY
2-4 A, CY ← A + (mem) + CY
mem, A
2-4 (mem), CY ← (mem) + A + CY
52
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
A, #byte
2
3
4
2
2
3
3
A, CY ← A – byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
P
P
P
P
P
P
P
P
P
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
sfr, #byte
r, r1
(saddr), CY ← (saddr) – byte
sfr, CY ← sfr – byte
r, CY ← r – r1
A, saddr
A, sfr
A, CY ← A – (saddr)
A, CY ← A – sfr
SUB
saddr, saddr
A, mem
mem, A
A, #byte
saddr, #byte
sfr, #byte
r, r1
(saddr), CY ← (saddr) – (saddr)
2-4 A, CY ← A – (mem)
2-4 (mem), CY ← (mem) – A
2
3
4
2
2
3
3
A, CY ← A – byte – CY
(saddr), CY ← (saddr) – byte – CY
sfr, CY ← sfr – byte – CY
r, CY ← r – r1 – CY
A, saddr
A, sfr
SUBC
A, CY ← A – (saddr) – CY
A, CY ← A – sfr – CY
saddr, saddr
A, mem
mem, A
A, #byte
saddr, #byte
sfr, #byte
r, r1
(saddr), CY ← (saddr) – (saddr) – CY
2-4 A, CY ← A – (mem) – CY
2-4 (mem), CY ← (mem) – A – CY
2
3
4
2
2
3
3
A ← A byte
(saddr) ← (saddr) byte
sfr ← sfr byte
r ← r r1
A, saddr
A, sfr
A ← A (saddr)
A ← A sfr
AND
saddr, saddr
A, mem
mem, A
(saddr) ← (saddr) (saddr)
2-4 A ← A (mem)
2-4 (mem) ← (mem)
A
53
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
A, #byte
2
3
4
2
2
3
3
A ← A byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
saddr, #byte
sfr, #byte
r, r1
(saddr) ← (saddr) byte
sfr ← sfr byte
r ← r r1
A, saddr
A, sfr
A ← A (saddr)
A ← A sfr
OR
saddr, saddr
A, mem
mem, A
A, #byte
saddr, #byte
sfr, #byte
r, r1
(saddr) ← (saddr) (saddr)
2-4 A ← A (mem)
2-4 (mem) ← (mem)
A
2
3
4
2
2
3
3
A ← A byte
(saddr) ← (saddr) byte
sfr ← sfr byte
r ← r r1
A, saddr
A, sfr
XOR
A ← A (saddr)
A ← A sfr
saddr, saddr
A, mem
mem, A
A, #byte
saddr, #byte
sfr, #byte
r, r1
(saddr) ← (saddr) (saddr)
2-4 A ← A (mem)
2-4 (mem) ← (mem)
A
2
3
4
2
2
3
3
A – byte
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
(saddr) – byte
sfr – byte
r – r1
A, saddr
A, sfr
A – (saddr)
A – sfr
CMP
saddr, saddr
A, mem
mem, A
(saddr) – (saddr)
2-4 A – (mem)
2-4 (mem) – A
54
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
AX, #word
3
4
5
2
2
3
3
3
4
5
2
2
3
3
3
4
5
2
2
3
3
2
2
AX, CY ← AX + word
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddrp, #word
sfrp, #word
rp, rp1
(saddrp), CY ← (saddrp) + word
sfrp, CY ← sfrp + word
rp, CY ← rp + rp1
ADDW
AX, saddrp
AX, sfrp
AX, CY ← AX + (saddrp)
AX, CY ← AX + sfrp
(saddrp), CY ← (saddrp) + (saddrp)
AX, CY ← AX – word
(saddrp), CY ← (saddrp) – word
sfrp, CY ← sfrp – word
rp, CY ← rp – rp1
saddrp, saddrp
AX, #word
saddrp, #word
sfrp, #word
rp, rp1
SUBW
AX, saddrp
AX, sfrp
AX, CY ← AX – (saddrp)
AX, CY ← AX – sfrp
(saddrp), CY ← (saddrp) – (saddrp)
AX – word
saddrp, saddrp
AX, #word
saddrp, #word
sfrp, #word
rp, rp1
(saddrp) – word
sfrp – word
rp – rp1
CMPW
AX, saddrp
AX, sfrp
AX – (saddrp)
AX – sfrp
saddrp, saddrp
r1
(saddrp) – (saddrp)
AX ← A × r1
MULU
r1
AX(quotient), r1(remainder) ← AX ÷ r1
AX(higher 16 bits), rp1(lower 16 bits)
← AX × rp1
DIVUW
rp1
rp1
2
2
MULUW
DIVUX
AXDE(quotient), rp1(remainder) ← AXDE
÷ rp1
AX(higher 16 bits), rp1(lower 16 bits)
rp1
MULW
2
← AX × rp1
55
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
r1 ← r1 + 1
r1
1
2
1
2
1
3
1
3
2
2
2
2
2
2
2
2
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
INC
(saddr) ← (saddr) + 1
saddr
r1
r1 ← r1 – 1
DEC
(saddr) ← (saddr) – 1
saddr
rp2
rp2 ← rp2 + 1
INCW
DECW
(saddrp) ← (saddrp) + 1
rp2 ← rp2 – 1
saddrp
rp2
(saddrp) ← (saddrp) – 1
(CY, r17 ← r10, r1m–1 ← r1m) × n times
(CY, r10 ← r17, r1m+1 ← r1m) × n times
(CY ← r10, r17 ← CY, r1m–1 ← r1m) × n times
(CY ← r17, r10 ← CY, r1m+1 ← r1m) × n times
(CY ← r10, r17 ← 0, r1m–1 ← r1m) × n times
(CY ← r17, r10 ← 0, r1m+1 ← r1m) × n times
(CY← rp10, rp115← 0, rp1m–1← rp1m) × n times
(CY← rp115, rp10← 0, rp1m+1← rp1m) × n times
A3–0 ← (rp1)3–0,
saddrp
r1, n
r1, n
r1, n
r1, n
r1, n
r1, n
rp1, n
rp1, n
ROR
P
P
P
P
P
P
P
P
×
×
×
×
×
×
×
×
ROL
RORC
ROLC
SHR
×
×
×
×
×
×
×
×
0
0
0
0
SHL
SHRW
SHLW
(rp1)7–4 ← A3–0,
[rp1]
[rp1]
ROR4
ROL4
2
2
(rp1)3–0 ← (rp1)7–4
A3–0 ← (rp1)7–4,
(rp1)3–0 ← A3–0,
(rp1)7–4 ← (rp1)3–0
ADJBA
ADJBS
Decimal Adjust Accumulator
2
1
×
×
×
P
×
When A7 = 0, X ← A, A ← 00H
When A7 = 1, X ← A, A ← FFH
CVTBW
56
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
CY, saddr. bit
CY, sfr. bit
3
3
2
2
2
2
3
3
2
2
2
2
3
3
3
3
2
2
2
2
2
2
2
2
3
3
3
3
2
2
2
2
2
2
2
2
CY ← (saddr.bit)
CY ← sfr.bit
×
×
×
×
×
×
CY, A. bit
CY ← A.bit
CY, X. bit
CY ← X.bit
CY, PSWH. bit
CY, PSWL. bit
saddr. bit, CY
sfr. bit, CY
CY ← PSWH.bit
CY ← PSWL.bit
(saddr.bit) ← CY
sfr.bit ← CY
MOV1
A. bit, CY
A.bit ← CY
X. bit, CY
X.bit ← CY
PSWH. bit, CY
PSWL. bit, CY
CY, saddr. bit
CY, /saddr. bit
CY, sfr. bit
PSWH.bit ← CY
PSWL.bit ← CY
CY ← CY (saddr.bit)
CY ← CY (saddr.bit)
CY ← CY sfr.bit
CY ← CY sfr.bit
CY ← CY A.bit
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CY, /sfr. bit
CY, A. bit
CY, /A. bit
CY ← CY A.bit
AND1
CY, X. bit
CY ← CY X.bit
CY, /X. bit
CY ← CY X.bit
CY, PSWH. bit
CY, /PSWH. bit
CY, PSWL. bit
CY, /PSWL. bit
CY, saddr. bit
CY, /saddr. bit
CY, sfr. bit
CY ← CY PSWH.bit
CY ← CY PSWH.bit
CY ← CY PSWL.bit
CY ← CY PSWL.bit
CY ← CY (saddr.bit)
CY ← CY (saddr.bit)
CY ← CY sfr.bit
CY ← CY sfr.bit
CY ← CY A.bit
CY, /sfr. bit
CY, A. bit
CY, /A. bit
CY ← CY A.bit
OR1
CY, X. bit
CY ← CY X.bit
CY, /X. bit
CY ← CY X.bit
CY, PSWH. bit
CY, /PSWH. bit
CY, PSWL. bit
CY, /PSWL. bit
CY ← CY PSWH.bit
CY ← CY PSWH.bit
CY ← CY PSWL.bit
CY ← CY PSWL.bit
57
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
CY, saddr. bit
CY, sfr. bit
CY, A. bit
CY, X. bit
CY, PSWH. bit
CY, PSWL. bit
saddr. bit
sfr. bit
3
3
2
2
2
2
2
3
2
2
2
2
2
3
2
2
2
2
3
3
2
2
2
2
1
1
1
CY ← CY (saddr.bit)
×
×
×
×
×
×
CY ← CY sfr.bit
CY ← CY A.bit
CY ← CY X.bit
CY ← CY PSWH.bit
CY ← CY PSWL.bit
(saddr.bit) ← 1
sfr.bit ← 1
XOR1
A. bit
A.bit ← 1
SET1
CLR1
NOT1
X. bit
X.bit ← 1
PSWH. bit
PSWL. bit
saddr. bit
sfr. bit
PSWH.bit ← 1
PSWL.bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
×
×
×
×
×
×
×
×
×
×
×
×
×
A. bit
A.bit ← 0
X. bit
X.bit ← 0
PSWH. bit
PSWL. bit
saddr. bit
sfr. bit
PSWH.bit ← 0
PSWL.bit ← 0
(saddr.bit) ← (saddr.bit)
sfr.bit ← sfr.bit
A.bit ← A.bit
X.bit ← X.bit
PSWH.bit ← PSWH.bit
PSWL.bit ← PSWL.bit
CY ← 1
×
A. bit
X. bit
PSWH. bit
PSWL. bit
CY
×
1
0
×
SET1
CLR1
NOT1
CY
CY ← 0
CY
CY ← CY
58
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
(SP–1) ← (PC+3)H, (SP–2) ← (PC+3)L,
PC ← addr16, SP ← SP–2
!addr16
CALL
3
2
1
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PC15–11←00001, PC10–0←addr11,SP←SP–2
!addr11
[addr5]
CALLF
(SP–1) ← (PC+1)H, (SP–2) ← (PC+1)L,
PCH←(TPF, 00000000, addr5+1),
PCL←(TPF, 00000000, addr5), SP←SP–2
CALLT
CALL
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PCH ← rp1H, PCL← rp1L, SP ← SP–2
2
2
rp1
(SP–1) ← (PC+2)H, (SP–2) ← (PC+2)L,
PCH ← (rp1+1), PCL← (rp1), SP ← SP–2
[rp1]
(SP–1) ← PSWH, (SP–2) ← PSWL
(SP–3) ← (PC+1)H, (SP–4) ← (PC+1)L,
PCL ← (003EH), PCH← (003FH), SP← SP–4
IE ← 0
BRK
1
1
1
PCL ← (SP), PCH← (SP+1), SP← SP+2
RET
PCL ← (SP), PCH← (SP+1)
PSWL ← (SP+2), PSWH ← (SP+3)
SP ← SP+4
RETB
R
R
R
R
R
R
R
R
R
R
PCL ← (SP), PCH← (SP+1)
PSWL ← (SP+2), PSWH ← (SP+3)
SP ← SP+4
1
3
RETI
(SP–1) ← sfrH
(SP–2) ← sfrL
SP ← SP–2
sfrp
PUSH
{(SP–1)←postH, (SP–2) ← postL,SP←SP–2}
2
1
2
post
PSW
post
Note
× n times
(SP–1)←PSWH, (SP–2)←PSWL, SP←SP–2
{(UP–1)←postH, (UP–2)←postL, UP←UP–2}
PUSHU
POP
Note
× n times
sfrL ← (SP)
sfrH ← (SP+1)
SP ← SP+2
sfrp
3
2
{postL← (SP), postH ← (SP+1), SP←SP+2}
post
Note
× n times
R
R
R
R
R
PSWL←(SP), PSWH←(SP+1), SP←SP+2
1
2
PSW
post
{postL← (UP), postH ← (UP+1), UP←UP+2}
POPU
Note
× n times
SP← word
SP← AX
4
2
SP, #word
MOVW
SP, AX
AX, SP
2
2
2
AX ←SP
SP
SP
SP ← SP+1
SP ← SP–1
INCW
DECW
(pin level) (signal level before output
buffer)
3
3
×
×
×
×
P
P
sfr
sfr
CHKL
A ← (pin level) (signal level before output
buffer)
CHKLA
Note n indicates the number of registers described as post.
59
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
!addr16
3
2
2
2
PC ← addr16
rp1
PCH ← rp1H, PCL ← rp1L
PCH ← (rp1+1), PCL ← (rp1)
PC ← PC+2+jdisp8
BR
[rp1]
$ addr16
BC
$ addr16
2
2
2
2
2
2
PC ← PC+2+jdisp8 if CY=1
PC ← PC+2+jdisp8 if CY=0
PC ← PC+2+jdisp8 if Z=1
PC ← PC+2+jdisp8 if Z=0
PC ← PC+2+jdisp8 if P/V=1
PC ← PC+2+jdisp8 if P/V=0
BL
BNC
BNL
BZ
$ addr16
$ addr16
$ addr16
$ addr16
$ addr16
BE
BNZ
BNE
BV
BPE
BNV
BPO
BN
2
2
3
3
3
3
3
3
3
4
3
3
3
3
4
4
3
3
3
3
PC ← PC+2+jdisp8 if S=1
$ addr16
BP
PC ← PC+2+jdisp8 if S=0
$ addr16
BGT
BGE
BLT
BLE
BH
PC ← PC+3+jdisp8 if (P/V S) Z=0
PC ← PC+3+jdisp8 if P/V S=0
PC ← PC+3+jdisp8 if P/V S=1
PC ← PC+3+jdisp8 if (P/V S) Z=1
PC ← PC+3+jdisp8 if Z CY=0
PC ← PC+3+jdisp8 if Z CY=1
PC ← PC+3+jdisp8 if (saddr.bit)=1
PC ← PC+4+jdisp8 if sfr.bit=1
PC ← PC+3+jdisp8 if A.bit=1
PC ← PC+3+jdisp8 if X.bit=1
PC ← PC+3+jdisp8 if PSWH.bit=1
PC ← PC+3+jdisp8 if PSWL.bit=1
PC ← PC+4+jdisp8 if (saddr.bit)=0
PC ← PC+4+jdisp8 if sfr.bit=0
PC ← PC+3+jdisp8 if A.bit=0
PC ← PC+3+jdisp8 if X.bit=0
PC ← PC+3+jdisp8 if PSWH.bit=0
PC ← PC+3+jdisp8 if PSWL.bit=0
$ addr16
$ addr16
$ addr16
$ addr16
$ addr16
BNH
$ addr16
saddr. bit, $ addr16
sfr. bit, $ addr16
A. bit, $ addr16
X. bit, $ addr16
PSWH. bit, $ addr16
PSWL. bit, $ addr16
saddr. bit, $ addr16
sfr. bit, $ addr16
A. bit, $ addr16
X. bit, $ addr16
PSWH. bit, $ addr16
PSWL. bit, $ addr16
BT
BF
60
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
PC ← PC+4+jdisp8 if (saddr.bit)=1
then reset (saddr.bit)
saddr.bit, $ addr16
sfr.bit, $ addr16
A.bit, $ addr16
4
4
3
3
3
3
4
4
3
3
3
3
2
3
2
3
4
PC ← PC+4+jdisp8 if sfr.bit=1
then reset sfr.bit
PC ← PC+3+jdisp8 if A.bit=1
then reset A.bit
BTCLR
PC ← PC+3+jdisp8 if X.bit=1
then reset X.bit
X.bit, $ addr16
PSWH.bit, $ addr16
PSWL.bit, $ addr16
saddr.bit, $ addr16
sfr.bit, $ addr16
A.bit, $ addr16
X.bit, $ addr16
PSWH.bit, $ addr16
PSWL.bit, $ addr16
r2, $ addr16
PC ← PC+3+jdisp8 if PSWH.bit=1
then reset PSWH.bit
PC ← PC+3+jdisp8 if PSWL.bit=1
then reset PSWL.bit
×
×
×
×
×
PC ← PC+4+jdisp8 if (saddr.bit)=0
then set (saddr.bit)
PC ← PC+4+jdisp8 if sfr.bit=0
then set sfr.bit
PC ← PC+3+jdisp8 if A.bit=0
then set A.bit
BFSET
PC ← PC+3+jdisp8 if X.bit=0
then set X.bit
PC ← PC+3+jdisp8 if PSWH.bit=0
then set PSWH.bit
PC ← PC+3+jdisp8 if PSWL.bit=0
then set PSWL.bit
×
×
×
×
×
r2 ← r2–1,
then PC ← PC+2+jdisp8 if r2≠0
(saddr) ← (saddr)–1,
DBNZ
saddr, $ addr16
RBn
then PC ← PC+3+jdisp8 if (saddr) ≠0
PCH ↔ R5, PCL ↔ R4, R7 ← PSWH,
R6←PSWL, RBS2–0← n, RSS←0, IE←0
PCH ← R5, PCL ← R4, R5, R4 ← addr16,
PSWH ← R7, PSWL ← R6
PCH ← R5, PCL ← R4, R5, R4 ← addr16,
PSWH ← R7, PSWL ← R6
BRKCS
RETCS
RETCSB
!addr16
R
R
R
R
R
R
R
R
R
R
!addr16
61
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
(DE + ) ← A, C ← C–1
[DE + ], A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
End if C=0
MOVM
(DE – ) ← A, C ← C–1
End if C=0
[DE – ], A
(DE + ) ← (HL + ), C ← C–1
End if C=0
[DE + ], [HL + ]
MOVBK
XCHM
(DE – ) ← (HL – ), C ← C–1
End if C=0
[DE – ], [HL – ]
[DE + ], A
(DE + ) ↔ A, C ← C–1
End if C=0
(DE – ) ↔ A, C ← C–1
End if C=0
[DE – ], A
(DE + ) ↔ (HL + ), C ← C–1
End if C=0
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
XCHBK
(DE – ) ↔ (HL – ), C ← C–1
End if C=0
(DE + ) – A, C ← C–1
End if C=0 or Z=0
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
CMPME
CMPBKE
CMPMNE
CMPBKNE
CMPMC
(DE – ) – A, C ← C–1
End if C=0 or Z=0
[DE – ], A
(DE + ) – (HL + ), C ← C–1
End if C=0 or Z=0
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
(DE – ) – (HL – ), C ← C–1
End if C=0 or Z=0
(DE + ) – A, C ← C–1
End if C=0 or Z=1
(DE – ) – A, C ← C–1
End if C=0 or Z=1
[DE – ], A
(DE + ) – (HL + ), C ← C–1
End if C=0 or Z=1
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
(DE – ) – (HL – ), C ← C–1
End if C=0 or Z=1
(DE + ) – A, C ← C–1
End if C=0 or CY=0
(DE – ) – A, C ← C–1
End if C=0 or CY=0
×
×
×
×
×
×
V
V
×
×
[DE – ], A
62
µPD78320, 78322
Flags
Mnemonic
Operand
Operation
S
Z
AC P/V CY
(DE + ) – (HL + ), C ← C–1
End if C=0 or CY=0
×
×
×
×
×
×
×
×
V
V
V
V
V
V
×
×
×
×
×
×
[DE + ], [HL + ]
[DE – ], [HL – ]
[DE + ], A
2
2
2
2
2
2
CMPBKC
(DE – ) – (HL – ), C ← C–1
End if C=0 or CY=0
×
×
×
×
×
×
×
×
×
×
(DE + ) – A, C ← C–1
End if C=0 or CY=1
CMPMNC
(DE – ) – A, C ← C–1
End if C=0 or CY=1
[DE – ], A
(DE + ) – (HL + ), C ← C–1
End if C=0 or CY=1
[DE + ], [HL + ]
[DE – ], [HL – ]
CMPBKNC
(DE – ) – (HL – ), C ← C–1
End if C=0 or CY=1
Note
STBC ← byte
STBC, #byte
WDM, #byte
4
4
1
2
2
1
1
1
MOV
Note
WDM ← byte
SWRS
RSS ← RSS
RBS2–0 ← n, RSS ← 0
RBS2–0 ← n, RSS ← 1
No Operation
RBn
SEL
RBn, ALT
NOP
EI
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
DI
Note
If the operation code of STBC register and WDM register manipulation instructions is abnormal, an operation
code trap interrupt is generated.
Operation in the event of trap:
(SP–1)← PSWH, (SP–2) ← PSWL,
(SP–3)← (PC–4)H, (SP–4) ← (PC–4)L,
PCL ← (003CH), PCH ← (003DH),
SP ← SP–4, IE ← 0
63
µPD78320, 78322
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
Test Conditions
Rating
Unit
VDD
AVDD
AVSS
VI
–0.5 to + 7.0
–0.5 to VDD + 0.5
–0.5 to + 0.5
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
4.0
V
V
Supply voltage
V
Note 1
Input voltage
V
Output voltage
VO
V
All output pins
mA
mA
mA
mA
Output current low
Output current high
Analog input voltage
IOL
All output pins total
All output pins
90
–1.0
IOH
All output pins total
–20
AVDD >VDD
–0.5 to VDD +0.5
–0.5 to AVDD +0.5
–0.5 to VDD +0.3
–0.5 to AVDD +0.3
–10 to + 70
–65 to + 150
Note 2
VIAN
V
V
VDD ≥ AVDD
AVDD >VDD
VDD ≥ AVDD
A/D converter reference
input voltage
AVREF
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
Notes 1. Except the pin described in Note 2.
2. P70/ANI0 to P77/ANI7 pins.
Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality
of the product may be degraded. In other words, the product may be physically damaged if any of the
absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings.
RECOMMENDED OPERATING CONDITION
Oscillation Frequency
TA
VDD
8 MHz ≤ fXX ≤ 16 MHz
–10 to +70 °C
+5.0 V ±10 %
CAPACITANCE (TA = 25 °C, VSS = VDD = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
pF
CI
Input capacitance
Output capacitance
I/O capacitance
10
20
20
f = 1 MHz
Unmeasured pins returned to 0 V.
pF
CO
pF
CIO
64
µPD78320, 78322
OSCILLATOR CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Resonator
Parameter
MIN.
MAX.
Unit
Recommended Circuit
X2
X1
VSS
Ceramic resonator
or
Oscillation frequency (fXX)
8
16
MHz
crystal resonator
C1
C2
X1
X2
MHz
ns
8
0
16
20
80
X1 input frequency (fX)
HCMOS
Invertor
External clock
X1 input rise/fall time (tXR, tXF)
or
X1
X2
Open
X1 input high/low level width
25
ns
HCMOS
Invertor
(tWXH , tWXL)
Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following
manner to avoid the influence of the wiring capacity, etc.
•
•
Make the wiring as short as possible.
Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating
currents run.
•
•
Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical
potential as VSS. Avoid grounding with a grand pattern in which very high currents run.
Do not fetch signals from the oscillation circuit.
65
µPD78320, 78322
RECOMMENDED OSCILLATOR CONSTANT
Ceramic Resonator
Frequency
[MHz]
Recommended Constant
Manufacturer
Product Name
C1 [pF]
30
C2 [pF]
30
CSA8.00MT
8.0
CSA12.0MT
12.0
CSA14.74MXZ040
CSA16.00MX040
14.74
16.0
15
15
Murata Mfg. Co., Ltd.
CST8.00MTW
8.0
12.0
14.74
16.0
CST12.0MTW
On-chip
On-chip
CST14.74MXW0C3
CST16.00MXW0C3
Crystal Resonator
Manufacturer
Frequency
[MHz]
Recommended Constant
Product Name
C1 [pF]
10
C2 [pF]
10
HC49/U-S
HC49/U
Kinseki Co., Ltd.
8 to 16
66
µPD78320, 78322
DC CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Symbol
VIL
Test Conditions
MIN.
0
TYP.
MAX.
0.8
Unit
V
Input voltage low
VIH1
VIH2
VOL
Note 1
Note 2
2.2
Input voltage high
V
0.8VDD
Output voltage low
IOL = 2.0 mA
0.45
V
V
Output voltage high
Input leakage current
Output leakage current
VOH
ILI
IOH = –400 µA
0 V ≤ VI ≤ VDD
0 V ≤ VO ≤ VDD
Operating mode
HALT mode
VDD – 1.0
±10
±10
65
µA
µA
mA
mA
V
ILO
IDD1
IDD2
VDDDR
40
20
VDD supply current
35
Data retention voltage
Data retention current
STOP mode
2.5
VDDDR = 2.5 V
2
10
50
µA
µA
IDDDR
STOP mode
VDDDR = 5.0 V ±10 %
10
Notes 1. Except the pin descried in Note 2.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5,
P27/INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.
67
µPD78320, 78322
AC CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Non-consecutive read/write operation (with general-purpose memory connected)
Parameter
System clock cycle time
Symbol
tCYK
Test Conditions
MIN.
125
32
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (vs. ASTB↓)
Address hold time (vs. ASTB↓)
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from RD↓
RD↓ delay time from ASTB↓
Data hold time (vs. RD↑)
Address active time from RD↑
RD low-level width
tSAST
tHSTA
tDAR
32
85
tFRA
0
tDAID
222
112
tDRID
tDSTR
tHRID
tDRA
42
0
50
157
37
85
tWRL
ASTB high-level width
tWSTH
tDAW
WR↓ delay time from address
Data output time from ASTB↓
Data output time from WR↓
WR↓ delay time from ASTB↓
Data setup time (vs. WR↑)
Data hold time (vs. WR↑)
ASTB↑ delay time from WR↑
WR low-level width
tDSTOD
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
102
40
42
147
32
42
157
68
µPD78320, 78322
tCYK DEPENDENT BUS TIMING DEFINITION
Parameter
tSAST
tHSTA
tDAR
Expression
MIN./MAX.
MIN.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5T – 30
0.5T – 30
MIN.
T – 40
MIN.
tDAID
(2.5 + n) T – 90
(1.5 + n) T – 75
0.5T – 20
MAX.
MAX.
MIN.
tDRID
tDSTR
tDRA
0.5T – 12
MIN.
tWRL
(1.5 + n) T – 30
0.5T – 25
MIN.
tWSTH
tDAW
MIN.
T – 40
MIN.
tDSTOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
0.5T + 40
MAX.
MIN.
0.5T – 20
1.5T – 40
MIN.
0.5T – 30
MIN.
0.5T – 20
MIN.
(1.5 + n) T – 30
MIN.
Remarks 1. T = tCYK = 1/fCLK (fCLK is an internal system clock frequency)
2. n indicates the number of wait cycles defined by user software.
3. Depends on tCYK for the bus timing shown in this table only.
69
µPD78320, 78322
SERIAL OPERATION (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Symbol
tCYSK
Test Conditions
Internal division by 8
MIN.
1
MAX.
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
SCK output
SCK input
SCK output
SCK input
SCK output
SCK input
Serial clock cycle time
External clock
1
Internal division by 8
External clock
420
420
420
420
80
Serial clock low-level width
Serial clock high-level width
tWSKL
tWSKH
Internal division by 8
External clock
SI setup time (vs. SCK↑)
SI hold time (vs. SCK↑)
SO delay time from SCK↓
tSRXSK
tHSKRX
tDSKTX
80
R = 1 kΩ, C = 100 pF
210
OTHER OPERATION (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
5
MAX.
Unit
µs
NMI high/low-level width
INTP0 high/low-level width
INTP1 high/low-level width
INTP2 high/low-evel width
NTP3 high/low-level width
NTP4 high/low-level width
INTP5 high/low-level width
INTP6 high/low-level width
RESET high/low-level width
TI high/low-level width
tWNIH, tWNIL
tWI0H, tWI0L
tWI1H, tWI1L
tWI2H, tWI2L
tWI3H, tWI3L
tWI4H, tWI4L
tWI5H, tWI5L
tWI6H, tWI6L
tWRSH, tWRSL
tWTIH, tWTIL
8T
8T
8T
8T
8T
8T
8T
5
tCYK
tCYK
tCYK
tCYK
tCYK
tCYK
tCYK
µs
In TM1 event counter mode
8T
tCYK
70
µPD78320, 78322
A/D CONVERTER CHARACTERISTICS (TA = –10 to +70 °C, VDD = +5 V ±10 %, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Symbol
Test Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Note 1
Total error
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
±0.4
±0.7
±1/2
%FSR
%FSR
LSB
tCYK
tCYK
LSB
LSB
LSB
LSB
LSB
LSB
V
Quantization error
Conversion time
Sampling time
tCONV
144
24
tSAMP
Note 1
Zero scale error
Full scale error
Non-linear error
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF ≤ AVDD
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±2.5
±4.5
±2.5
±4.5
±2.5
±4.5
AVDD
AVDD
3.0
Note 1
Note 1
Note 2
Analog input voltage
Reference voltage
AVREF current
VIAN
AVREF
AIREF
AIDD
–0.3
3.4
V
1.0
2.0
2.0
10
mA
AVDD supply current
6.0
mA
A/D converter data
retention current
AVDDR = 2.5 V
STOP mode
10
µA
AIDDR
AVDDR = 5 V ±10 %
50
µA
Notes 1. Quantization error excluded.
2. When –0.3 V ≤ VIAN ≤ 0 V, the conversion result becomes 000H.
When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits.
When AVREF ≤ VIAN ≤ AVDD, the conversion result is 3FFH.
71
µPD78320, 78322
Non-Consecutive Read Operation
t
CYK
(CLK)
P50-P57
(Output)
Higher Address
Hi-Z
Higher Address
t
DAID
t
SAST
Hi-Z
Hi-Z
Hi-Z
Lower Address
(Output)
Lower Address
(Output)
Data (Input)
P40-P47
(Input/
Output)
t
WSTH
t
HRID
ASTB
(Output)
t
HSTA
t
FRA
RD (Output)
t
DSTR
t
DRID
t
DRA
t
DAR
t
WRL
Non-Consecutive Write Operation
(CLK)
P50-P57
(Output)
Higher Address
Higher Address
t
SAST
P40-P47
(Input/
Lower Address
(Output)
Lower Address
(Output)
Data (Output)
Undefined
Output)
t
WSTH
t
HWOD
ASTB
(Output)
t
DWST
t
HSTA
t
DSTOD
WR (Output)
t
DSTW
t
SODW
t
DWOD
t
DAW
t
WWL
72
µPD78320, 78322
Serial Operation
t
CYSK
t
WSKH
t
WSKL
SCK
SO
SI
t
DSKTX
t
SRXSK
t
HSKRX
Interrupt Input Timing
t
WNIH
t
WNIL
0.8VDD
NMI
0.8V
t
WInH
t
WInL
INTPn
Remark n = 0 to 6
73
µPD78320, 78322
Reset Input Timing
t
WRSH
t
WRSL
0.8VDD
RESET
0.8V
TI Pin Input Timing
t
WTIH
t
WTIL
TI
74
µPD78320, 78322
10. PACKAGE DRAWINGS
68 PIN PLASTIC QFJ ( 950 mil)
A
B
68
1
F
E
T
Q
K
M
M
N
P
P68L-50A1-2
INCHES
NOTE
ITEM
A
MILLIMETERS
25.2 0.2
24.20
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.992 0.008
0.953
B
C
24.20
0.953
D
E
25.2 0.2
1.94 0.15
0.6
0.992 0.008
+0.007
0.076
–0.006
F
0.024
+0.009
G
H
I
4.4 0.2
2.8 0.2
0.9 MIN.
3.4
0.173
–0.008
+0.009
0.110
–0.008
0.035 MIN.
0.134
J
K
1.27 (T.P.)
0.40 1.0
0.12
0.050 (T.P.)
+0.004
M
N
P
0.016
–0.005
0.005
+0.009
23.12 0.20
0.15
0.910
–0.008
Q
T
0.006
R 0.8
R 0.031
+0.10
+0.004
U
0.20
0.008
–0.05
–0.002
75
µPD78320, 78322
74 PIN PLASTIC QFP ( 20)
A
B
56
57
38
37
detail of lead end
74
1
19
18
G2
G1
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
+0.017
A
B
C
D
23.2±0.4
20.0±0.2
20.0±0.2
23.2±0.4
0.913
0.787
0.787
0.913
–0.016
+0.009
–0.008
+0.009
–0.008
+0.017
–0.016
F
1
2
2.0
1.0
2.0
1.0
0.079
0.039
0.079
0.039
F
G
G
1
2
+0.004
–0.005
H
0.40±0.10
0.016
0.008
I
0.20
J
1.0 (T.P.)
1.6±0.2
0.039 (T.P.)
0.063±0.008
K
+0.009
0.031
L
0.8±0.2
–0.008
+0.004
0.006
+0.10
0.15
M
–0.003
–0.05
0.10
N
P
Q
R
S
0.004
3.7
0.146
0.1±0.1
5°±5°
0.004±0.004
5°±5°
4.0 MAX.
0.158 MAX.
S74GJ-100-5BJ-3
76
µPD78320, 78322
80 PIN PLASTIC QFP (14 20)
A
B
41
40
64
65
detail of lead end
S
C D
R
Q
25
24
80
1
F
G
J
M
H
I
K
P
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
A
23.6±0.4
0.929±0.016
+0.009
0.795
B
20.0±0.2
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.6±0.4
1.0
0.693±0.016
0.039
G
0.8
0.031
+0.004
0.014
H
0.35±0.10
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
+0.008
0.071
K
L
1.8±0.2
0.8±0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
5°±5°
3.0 MAX.
0.004±0.004
5°±5°
0.119 MAX.
P80GF-80-3B9-3
77
µPD78320, 78322
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78322 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting
Technology Manual” (IE-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 11-1. Soldering Conditions for Surface Mount Type
µPD78320GF-3B9
µPD78322GF-×××-3B9 : 80-pin plastic QFP (14 × 20 mm)
µPD78320GJ-5BJ : 74-pin plastic QFP (20 × 20 mm)
µPD78322GJ-×××-5BJ : 74-pin plastic QFP (20 × 20 mm)
: 80-pin plastic QFP (14 × 20 mm)
Recommended
Soldering Method
Soldering Conditions
Condition Symbol
Package peak temperature: 235 °C, Time: 30 sec. max. (at 210 °C or above),
Number of times: twice or less
<Caution>
Infrared reflow
(1) The second reflow should be started after the temperature of the device which
would have been changed by the first reflow has returned to normal.
(2) Please avoid flux water washing after the first reflow.
IR35-00-2
Package peak temperature: 215 °C, Time: 40 sec. max. (at 200 °C or above),
Number of times: twice or less
<Caution>
VPS
VP15-00-2
WS60-00-1
(1) The second reflow should be started after the temperature of the device which
would have been changed by the first reflow has returned to normal.
(2) Please avoid flux water washing after the first reflow.
Solder bath temperature: 260 °C max. Time: 10 sec. max., Number of times: Once
Preheating temperature: 120 °C max. (package surface temperature)
Wave soldering
Pin part heating
Pin temperature: 300 °C max. Time: 3 sec. max. (Per device side)
µPD78320L
: 68-pin plastic QFJ ( 950 mil)
µPD78322L-××× : 68-pin plastic QFJ ( 950 mil)
Recommended
Soldering Method
Soldering Conditions
Condition Symbol
Package peak temperature: 230 °C, Time: 30 sec. max. (at 210 °C or above),
Infrared reflow
IR30-00-1
VP15-00-1
Number of times: Once
Package peak temperature: 215 °C, Time: 40 sec. max. (at 200 °C or above),
VPS
Number of times: Once
Pin part heating
Pin part temperature: 300 °C max. Time: 3 sec. max. (Per device side)
Caution Use more than one soldering method should be avoided (except in the case of pin part heating).
78
APPENDIX A. LIST OF 78K/ΙΙΙ SERIES PRODUCTS (1/2)
Note
Note
µPD78322
µPD78320
µPD78312
µPD78310
µPD78312A
µPD78310A
Basic instruction
111
250 ns (at 16 MHz operation)
16384 × 8 bits ––
640 × 8 bits
96
500 ns (at 12 MHz operation)
–– 8192 × 8 bits
256 × 8 bits
Minimum instruction execution time
ROM
8192 × 8 bits
––
Internal memory
Memory space
RAM
64K bytes
16 (including 8 analog inputs)
––
12 (including 4 analog inputs)
1
Input
Output
I/O
I/O lines
39
21
40
24
40
24
Multi-function pulse I/O unit
• 16-bit presettable up/down-counter × 2
• 16-bit free running counter capture function × 2
• 16-bit interval time × 2
Real-time pulse unit
• 18-/16-bit free running timer × 1
• 16-bit timer/event counter × 1
• 16-bit compare register × 6
• 18-bit capture register × 4
• High-precision PWM output × 2
• Real-time output port : 4 bits × 2
Pulse unit
Count unit mode 4 (4-multiplication
mode) function not available
Count unit mode 4 (4-multiplication
mode) function available
• 18-bit capture/compare register × 2
• Real-time output port × 8
Count start function by interval time
external trigger not available
Count start function by interval timer
external trigger available
• Dedicated on-chip baud rate generator
• 8 bits (full-duplex transmission/reception)
• Dedicated on-chip baud rete generator
• UART
... 1 channel
Serial communication interface
A/D converter
• SBI
• 2 transfer modes (asynchronous mode, I/O interface mode)
... 1 channel
• 3-wire serial I/O
µ
Eight 10-bit resolution inputs
Four 8-bit resolution inputs
• 8 external, 14 internal (shared with
external : 2)
• 4 external, 13 internal
• 8-level programmable priority
Interrupt
• 3-level programmable priority
• 3 processing modes (vectored interrupt, context switching and macro service functions)
Note Maintenance product
LIST OF 78K/ΙΙΙ SERIES PRODUCTS (2/2)
Note
Note
µPD78322
Internal : 1
µPD78320
µPD78312
µPD78310
µPD78312A
µPD78310A
Test source
––
Following instructions added for
µPD78312 and 78310
Instructions for µPD78312 and 78310
–––
Instruction set
significantly added.
• MOVW rp1, !addr16 instruction
• MOVW !addr16, rp1 instruction
• On-chip watchdog timer
• Standby function (STOP/HALT)
Pulse unit
• 20-bit time base counter
—
• Pseudo static RAM refresh function
• 64-pin plastic shrink DIP (750 mil)
• 68-pin plastic QFJ ( 950 mil)
• 64-pin plastic QFP (14 × 20 mm)
• 64-pin plastic QUIP
Package
• 74-pin plastic QFP (20 × 20 mm)
• 80-pin plastic QFP (14 × 20 mm)
• 68-pin plastic QFJ ( 950 mil)
Note Maintenance product
µ
µPD78320, 78322
APPENDIX B. TOOLS
B.1 DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78322.
Language Processor
78K/III series relocatable assembler Refers to the relocatable assembler which can be used commonly for the 78K/III
(RA78K/III)
series. Equipped with the macro function, the relocatable assembler is aimed at
improved development efficiency.
The assembler is also accompanied by the structured assembler which can describe
the program control structure explicitly, thus making it possible to improve the
productivity and the maintainability of the program.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13RA78K3
µS5A10RA78K3
µS7B13RA78K3
µS7B10RA78K3
PC-9800 series
MS-DOSTM
IBM PC/ATTM and
its compatible
machine
3.5-inch 2HC
5-inch 2HC
PC DOSTM
HP-UXTM
HP9000 series
700TM
DAT
µS3P16RA78K3
SPARCstationTM
NEWSTM
SunOSTM
µS3K15RA78K3
µS3R15RA78K3
Cartridge tape
(QIC-24)
NEWS-OSTM
78K/III series C compiler (CC78K/III)
Refers to the C compiler which can be commonly used in the 78K/III series. This
compiler is a program converting the programs written in the C language to those
object codes which are executable by microcontrollers. When using this compiler, the
78K/III series relocatable assembler (RA78K/III) is required.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
DAT
µS5A13CC78K3
µS5A10CC78K3
µS7B13CC78K3
µS7B10CC78K3
µS3P16CC78K3
µS3K15CC78K3
µS3R15CC78K3
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
PC DOS
HP9000 series 700
SPARCstation
NEWS
HP-UX
SunOS
Cartridge tape
(QIC-24)
NEWS-OS
Remark
Relocatable assembler and C compiler operations are assured only on the host machine and the OS
above.
81
µPD78320, 78322
PROM Writing Tools
This PROM programmer allows programming, in stand-alone mode or via operation from
a host computer, of a single-chip microcontroller with on-chip PROM by connection of
the board provided and a separately available programmer adapter.
It can program typical 256K-bit to 4M-bit PROMs.
PG-1500
UNISITE
2900
PROM programmer made by Data I/O Japan Corporation.
Hardware
PROM programmer adapters for writing programs to the µPD78P322 with a general
PROM programmer such as the PG-1500.
PA-78P322GF ... For µPD78P322GF
PA-78P322GF
PA-78P322GJ
PA-78P322K
PA-78P322KC
PA-78P322KD
PA-78P322L
PA-78P322GJ ... For µPD78P322GJ
PA-78P322K ... For µPD78P322K
PA-78P322KC ... For µPD78P322KC
PA-78P322KD ... For µPD78P322KD
PA-78P322L ... For µPD78P322L
Connects PG-1500 and host machine via a serial and parallel interface, and controls the
PG-1500 on the host machine.
Host Machine
Part number
OS
Supply medium
Software
PG-1500 controller
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
µS5A13PG1500
µS5A10PG1500
µS7B13PG1500
µS7B10PG1500
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
PC DOS
Remark
Operation of the PG-1500 controller is guaranteed only on the host machines and operating systems quoted
above.
82
µPD78320, 78322
Debugging Tools
Hardware
IE-78327-R
These are the in-circuit emulators which can be used for the development and
Note
IE-78320-R
debugging of application systems. Debugging is performed by connecting them to a
host machine. The IE-78327-R can be used commonly for both the µPD78322
subseries and the µPD78328 subseries.
The IE-78320-R can be used for the µPD78322 subseries.
EP-78320GF-R
EP-78320GJ-R
EP-78320L-R
These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a
target system.
EP-78320GF-R: for 80-pin plastic QFP
EP-78320GJ-R: for 74-pin plastic QFP
EP-78320L-R : for 68-pin plastic QFJ
IE-78327-R
This program is for controlling the IE-78327-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.
control program
(IE controller)
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13IE78327
µS5A10IE78327
µS7B13IE78327
µS7B10IE78327
PC-9800 series
MS-DOS
3.5-inch 2HC
5-inch 2HC
IBM PC/AT and its
compatible machine
PC DOS
This program is for controlling the IE-78320-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.
Software
IE-78320-R
Note
control program
(IE controller)
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13IE78320
µS5A10IE78320
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
PC DOS
5-inch 2HC
µS7B10IE78320
Remarks 1. The operation of each software is assured only on the host machine and the OS above.
2. µPD78322 subseries: µPD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1),
78320(A2),78322(A),78322(A1),78322(A2),78323(A),78323(A1),78323(A2),
78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2)
µPD78328 subseries: µPD78327, 78328, 78P328, 78327(A), 78328(A)
Note
The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit
emulator, please use the alternative product IE-78327-R.
83
Host machine
PC-9800 series
IBM PC/AT or its compatible machine
RS-232-C
Emulation probes
IE-78327-R
in-circuit emulator
Software
RS-232-C
EP-78320GF-R
EP-78320GJ-R
EP-78320L-R
PROM programmer
Relocatable assembler PG-1500
(With structured assembler) controller
IE controller
Socket for connecting the emulation probe
Note
and the target system
PG-1500
PROM-incorporated products
EV-9200G-80
Socket for plastic QFJ
EV-9200G-74
µPD78P322K
µPD78P322GF
µPD78P322GJ
µPD78P322KC
µPD78P322KD
µPD78P322L
+
+
+
Programmer adapters
Target system
PA-78P322K
PA-78P322KC
PA-78P322KD
PA-78P322GF
PA-78P322GJ
PA-78P322L
µ
Note
The socket is supplied with the emulation probe.
Remark It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS-232C.
µPD78320, 78322
B.2 EVALUATION TOOLS
To evaluate the functions of the µPD78322, the following tools are made available.
Part Number
EB-78320-98
Host Machine
PC-9800 series
Function
By connecting to a host machine, it is possible
to evaluate the functions equipped by the
µPD78322 in a simple manner. The command
system of this product basically conforms to
that of IE-78327-R and IE-78320-R. Therefore,
it is easy to move to the development work of
application systems by IE-78327-R or IE-
78320-R. In addition a turbo access manager
(µPD71P301)Note can be mounted on the board.
EB-78320-PC
IBM PC/AT or its compatible
machine
Note
The turbo access manager (µPD71P301) is a maintenance product.
Cautions 1. This product is not a development tool of µPD78322 application systems.
2. This product is not equipped with the emulation function for executing the ROM incorporated
in the µPD78322.
B.3 EMBEDDED SOFTWARE
The following embedded software programs are available to perform program development and maintenance
more efficiently.
Eeal-time OS
Real-time OS (RX78K/III)
The RX78K/III is designed to provide a multi-task environment in the field of control
application where real-time operation is required. By using this real-time OS, the
performance of the whole system can be improved by allocating CPU’s idle time to
other processings.
The RX78K/III provides the system call based on the µITRON specifications.
The RX78K/III package provides tools (configurators) for creating RX78K/III’s nucleus
and multiple information table.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13RX78320
µS5A10RX78320
µS7B13RX78320
µS7B10RX78320
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
3.5-inch 2HC
5-inch 2HC
PC DOS
Caution
Remark
To purchase the operating system above, you need to fill in a purchase application form
beforehand and sign a contract allowing you to use the software.
When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well.
85
µPD78320, 78322
Fuzzy Inference Development Support System
Fuzzy knowledge data creation
tools (FE9000, FE9200)
This program supports inputting/editing/evaluating (through simulation) of the fuzzy
knowledge data (fuzzy rules and membership functions).
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
µS5A13FE9000
µS5A10FE9000
µS7B13FE9200
µS7B10FE9200
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine PC DOS WinsowsTM
Translator (FT78K3)Note
This program converts the fuzzy knowledge data obtained with fuzzy knowledge data
creation tools to an assembler source program for RA78K/III.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13FT78K3
µS5A10FT78K3
µS7B13FT78K3
µS7B10FT78K3
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
3.5-inch 2HC
5-inch 2HC
PC DOS
Fuzzy inference module
(FI78K/III)Note
This program executes fuzzy inference. Fuzzy inference is executed by being linked to
the fuzzy knowledge data converted by the translator.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13FI78K3
µS5A10FI78K3
µS7B13FI78K3
µS7B10FI78K3
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
3.5-inch 2HC
5-inch 2HC
PC DOS
Fuzzy inference debugger
(FD78K/III)
This is a support software program for evaluating and adjusting the fuzzy knowledge
data at a hardware level by using the in-circuit emulator.
Host machine
Part number
OS
Supply medium
3.5-inch 2HD
5-inch 2HD
µS5A13FD78K3
µS5A10FD78K3
µS7B13FD78K3
µS7B10FD78K3
PC-9800 series
MS-DOS
IBM PC/AT and its
compatible machine
3.5-inch 2HC
5-inch 2HC
PC DOS
Note
Under development
86
µPD78320, 78322
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
87
µPD78320, 78322
For this product, the following User’s Manual is available as a separate volume. Please refer to it in conjunction
with manual.
•
µPD78322 User’s Manual : IEU1248
The export of these products from Japan is regulated by the Japanese government. The export of some or all of
these products may be prohibited without governmental license. To export or re-export some or all of these
products from a country other than Japan may also be prohibited without a license from that country. Please call
an NEC sales representative.
License not needed
:
µPD78320
The customer must judge the need for license : µPD78322
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademark of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
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