UPD784037GC-XXX-8BT-A [NEC]
Microcontroller, 16-Bit, MROM, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80;
| 型号： | UPD784037GC-XXX-8BT-A |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 16-Bit, MROM, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80 时钟 微控制器 ISM频段 外围集成电路 |
| 文件： | 总489页 (文件大小：2138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
78K/IV Series
16-Bit Single-Chip Microcontroller
Instructions
For All 78K/IV Series
Document No. U10905EJ8V1UM00 (8th edition)
Date Published March 2001 N CP(K)
1997
©
Printed in Japan
[MEMO]
2
User’s Manual U10905EJ8V1UM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
IEBus and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
Ethernet is a trademark of Xerox Corporation.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U10905EJ8V1UM
3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Caution: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
•
The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
4
User’s Manual U10905EJ8V1UM
Major Revisions in This Edition
Pages
Contents
Throughout
• Addition of µPD784216A, 784216AY, 784218A, 784218AY, 784938A, 784956A, 784976A Subseries.
Deletion of µPD784216, 784216Y, 784218, 784218Y, 784937, 784955 Subseries.
Addition of µPD784928, 784928Y. Deletion of µPD784915, 784915A, 784916A
• The status of following products changed from under development to completed:
µPD784224, 784225, 78F4225, 784224Y, 784225Y, 78F4225Y
µPD784907, 784908, 78P4908
The mark
shows major revised points.
User’s Manual U10905EJ8V1UM
5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-3067-5899
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 250-3583
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
6
User’s Manual U10905EJ8V1UM
INTRODUCTION
Target Readers
: This manual is intended for users who wish to understand the functions of 78K/IV
Series products, and design and develop application systems using these products.
• 78K/IV Series products
• µPD784026 Subseries
• µPD784038 Subseries
: µPD784020, 784021, 784025, 784026, 78P4026
: µPD784031, 784035, 784036, 784037, 784038,
78P4038, 784031(A), 784035(A), 784036(A)
: µPD784031Y, 784035Y, 784036Y, 784037Y,
784038Y, 78P4038Y
• µPD784038Y Subseries
• µPD784046 Subseries
: µPD784044, 784046, 784054, 78F4046, 78444(A),
(A1), (A2), µPD784046(A), (A1), (A2), 784054(A),
(A1), (A2)
• µPD784216A Subseries
: µPD784214A, 784215A, 784216A, 78F4216A
• µPD784216AY Subseries : µPD784214AY,784215AY,784216AY,78F4216AY
•
•
µPD784218A SubseriesNote : µPD784217A, 784218A, 78F4218A
Note
µPD784218AY Subseries
: µPD784217AY, 784218AY, 78F4218AY
: µPD784224, 784225, 78F4225
: µPD784224Y, 784225Y, 78F4225Y
: µPD784907, 784908, 78P4908
: µPD784915B, 784916B, 78P4916
: µPD784927, 784928, 78F4928Note
: µPD784927Y, 784928Y, 78F4928YNote
: µPD784935A, 784936A, 784937A, 784938A,
78F4938ANote
• µPD784225 Subseries
µPD784225Y Subseries
•
• µPD784908 Subseries
• µPD784915 Subseries
• µPD784928 Subseries
• µPD784928Y Subseries
• µPD784938A Subseries
• µPD784956A SubseriesNote : µPD784953A, 784956A, 78F4956ANote
• µPD784976A SubseriesNote : µPD784975ANote, 78F4976ANote
Note Under development
Purpose
: This manual is intended for users to understand the instruction functions of the
78K/IV Series.
Organization
: This manual consists of the following chapters.
• Features of 78K/IV Series products
• CPU functions
• Instruction set
• Instruction descriptions
• Development tools
7
User’s Manual U10905EJ8V1UM
How to Read This Manual : It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To check the details of an instruction function when the mnemonic is known:
→ Use APPENDIX A and APPENDIX B INDEX OF INSTRUCTIONS.
• To check an instruction when you know the general function but do not know the
mnemonic:
→ Find the mnemonic in CHAPTER 6 INSTRUCTION SET, then check the function
in CHAPTER 7 DESCRIPTION OF INSTRUCTIONS.
• For a general understanding of the various instruction functions of the 78K/IV Series:
→ Read in accordance with the contents.
• For information on the hardware functions of the 78K/IV Series:
→ Read the separate User’s Manual.
– µPD784026 Subseries User’s Manual – Hardware (U10898E)
– µPD784038, 784038Y Subseries User’s Manual – Hardware (U11316E)
– µPD784046 Subseries User’s Manual – Hardware (U11515E)
– µPD784054 User’s Manual – Hardware (U11719E)
– µPD784216A, 784216AY, 784218A, 784218AY Subseries User’s Manual –
Hardware (U12015E)
– µPD784225, 784225Y Subseries User’s Manual – Hardware (U12679E)
– µPD784908 Subseries User’s Manual – Hardware (U11787E)
– µPD784915 Subseries User’s Manual – Hardware (U10444E)
– µPD784928, 784928Y Subseries User’s Manual – Hardware (U12648E)
– µPD784938A Subseries User’s Manual – Hardware (To be prepared)
– µPD784956A Subseries User’s Manual – Hardware (U14395E)
– µPD784976A Subseries User’s Manual – Hardware (U15017E)
Conventions
: Data significance
Active low representation
Note
: Higher digit on left and lower digit on right
: ××× (overscore over pin or signal name)
: Footnote for item marked with Note in the text
: Information requiring particular attention
: Supplementary information
Caution
Remark
Numerical notations
: Binary
××××B or ××××
××××
Decimal
Hexadecimal
××××H
8
User’s Manual U10905EJ8V1UM
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
• Documents common to the 78K/IV Series
Document Name
Document Number
This manual
U10095E
User’s Manual – Instructions
Application Note – Software Basics
• Individual documents
• µPD784026 Subseries
Document Name
Document Number
U11514E
µPD784020, 84021 Data Sheet
µPD784025, 784026 Data Sheet
µPD78P4026 Data Sheet
U11605E
U11609E
µPD784026 Subseries User’s Manual – Hardware
U10898E
µPD784026 Subseries Application Note – Hardware Basics
U10573E
• µPD784038, 784038Y Subseries
Document Name
µPD784031 Data Sheet
Document Number
U11507E
µPD784035, 784036, 784037, 784038 Data Sheet
µPD784031(A) Data Sheet
U10847E
U13009E
µPD784035(A), 784036(A) Data Sheet
µPD78P4038 Data Sheet
U13010E
U10848E
µPD784031Y Data Sheet
U11504E
µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet
µPD78P4038Y Data Sheet
U10741E
U10742E
µ
PD784038
,
784038Y Subseries User’s Manual – Hardware
U11316E
9
User’s Manual U10905EJ8V1UM
• µPD784046 Subseries
Document Name
Document Number
U10951E
µPD784044, 784046 Data Sheet
µPD784044(A), 784046(A) Data Sheet
µPD784054 Data Sheet
U13121E
U11154E
µPD784054(A) Data Sheet
U13122E
µPD78F4046 Preliminary Product Information
µPD784046 Subseries User’s Manual – Hardware
µPD784054 User’s Manual – Hardware
U11447E
U11515E
U11719E
• µPD784216A, 784216AY, 784218A, 784218AY Subseries
Document Name
Document Number
U14121E
µPD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY,
784217AY, 784218AY Data Sheet
µPD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet
µPD784216A, 784216AY Subseries User’s Manual – Hardware
U14125E
U12015E
• µPD784225, 784225Y Subseries
Document Name
µPD784224, 784225, 784224Y, 784225Y Data Sheet
µPD78F4225 Preliminary Product Information
Document Number
U12376E
U12499E
µPD78F4225Y Preliminary Product Information
U12377E
µPD784225, 784225Y Subseries User’s Manual – Hardware
U12679E
• µPD784908 Subseries
Document Name
µPD784907, 784908 Data Sheet
Document Number
U11680E
µPD78P4908 Data Sheet
U11681E
µPD784908 Subseries User’s Manual – Hardware
U11787E
• µPD784915 Subseries
Document Name
µPD784915B, 784916B Data Sheet
Document Number
U13118E
µPD78P4916 Data Sheet
U11045E
µPD784915 Subseries User’s Manual – Hardware
µPD784915, 784928, 784928Y Subseries Application Note – VCR Servo Basics
U10444E
U11361E
10
User’s Manual U10905EJ8V1UM
• µPD784928, 784928Y Subseries
Document Name
Document Number
U12255E
µPD784927, 784928, 784927Y, 784928Y Data Sheet
µPD78F4928 Preliminary Product Information
U12188E
µPD78F4928Y Preliminary Product Information
µPD784928, 784928Y Subseries User’s Manual – Hardware
U12271E
U12648E
• µPD784938A Subseries
Document Name
µPD784935A, 784936A, 784937A, 784938A Data Sheet
µPD78F4938A Data Sheet
Document Number
U13572E
To be prepared
To be prepared
µPD784938A Subseries User’s Manual – Hardware
• µPD784956A Subseries
Document Name
µPD784953A, 784956A Preliminary Product Information
µPD78F4956A Preliminary Product Information
Document Number
To be prepared
To be prepared
To be prepared
µPD784956A Subseries User’s Manual – Hardware
• µPD784976A Subseries
Document Name
µPD784975A Data Sheet
Document Number
On preparation
To be prepared
U15017E
µPD78F4976A Data Sheet
µPD784976A Subseries User’s Manual – Hardware
11
User’s Manual U10905EJ8V1UM
CONTENTS
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS ............................................................
1.1 78K/IV Series Product Lineup..........................................................................................
1.2 Product Outline of µPD784026 Subseries ......................................................................
19
21
22
22
22
23
24
25
26
26
27
27
29
30
31
31
32
32
34
35
36
36
36
37
38
40
42
42
42
43
44
46
47
47
47
48
49
51
52
52
53
53
54
56
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.3 Product Outline of µPD784038 Subseries ......................................................................
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.4 Product Outline of µPD784038Y Subseries ....................................................................
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.5 Product Outline of µPD784046 Subseries ......................................................................
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.6 Product Outline of µPD784216A Subseries ....................................................................
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.7 Product Outline of µPD784216AY Subseries..................................................................
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.8 Product Outline of µPD784218A Subseries ....................................................................
1.8.1
1.8.2
1.8.3
1.8.4
1.8.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
12
User’s Manual U10905EJ8V1UM
1.9 Product Outline of µPD784218AY Subseries..................................................................
57
57
58
58
59
61
62
62
63
63
64
66
67
67
68
68
69
71
72
72
73
73
74
76
77
77
77
78
79
80
81
81
81
82
83
84
85
85
85
86
87
88
89
89
89
90
91
93
1.9.1
1.9.2
1.9.3
1.9.4
1.9.5
Features...............................................................................................................................
Applications .........................................................................................................................
Ordering information and quality grade ...............................................................................
Outline of functions ..............................................................................................................
Block diagram ......................................................................................................................
1.10 Product Outline of µPD784225 Subseries ......................................................................
1.10.1 Features...............................................................................................................................
1.10.2 Applications .........................................................................................................................
1.10.3 Ordering information and quality grade ...............................................................................
1.10.4 Outline of functions ..............................................................................................................
1.10.5 Block diagram ......................................................................................................................
1.11 Product Outline of µPD784225Y Subseries ....................................................................
1.11.1 Features...............................................................................................................................
1.11.2 Applications .........................................................................................................................
1.11.3 Ordering information and quality grade ...............................................................................
1.11.4 Outline of functions ..............................................................................................................
1.11.5 Block diagram ......................................................................................................................
1.12 Product Outline of µPD784908 Subseries ......................................................................
1.12.1 Features...............................................................................................................................
1.12.2 Applications .........................................................................................................................
1.12.3 Ordering information and quality grade ...............................................................................
1.12.4 Outline of functions ..............................................................................................................
1.12.5 Block diagram ......................................................................................................................
1.13 Product Outline of µPD784915 Subseries ......................................................................
1.13.1 Features...............................................................................................................................
1.13.2 Applications .........................................................................................................................
1.13.3 Ordering information and quality grade ...............................................................................
1.13.4 Outline of functions ..............................................................................................................
1.13.5 Block diagram ......................................................................................................................
1.14 Product Outline of µPD784928 Subseries ......................................................................
1.14.1 Features...............................................................................................................................
1.14.2 Applications .........................................................................................................................
1.14.3 Ordering information ............................................................................................................
1.14.4 Outline of functions ..............................................................................................................
1.14.5 Block diagram ......................................................................................................................
1.15 Product Outline of µPD784928Y Subseries ....................................................................
1.15.1 Features...............................................................................................................................
1.15.2 Applications .........................................................................................................................
1.15.3 Ordering information ............................................................................................................
1.15.4 Outline of functions ..............................................................................................................
1.15.5 Block diagram ......................................................................................................................
1.16 Product Outline of µPD784938A Subseries ....................................................................
1.16.1 Features...............................................................................................................................
1.16.2 Applications .........................................................................................................................
1.16.3 Ordering information and quality grade ...............................................................................
1.16.4 Outline of functions ..............................................................................................................
1.16.5 Block diagram ......................................................................................................................
User’s Manual U10905EJ8V1UM
13
1.17 Product Outline of µPD784956A Subseries ....................................................................
1.17.1 Features...............................................................................................................................
1.17.2 Applications .........................................................................................................................
1.17.3 Ordering information and quality grade ...............................................................................
1.17.4 Outline of functions ..............................................................................................................
1.17.5 Block diagram ......................................................................................................................
1.18 Product Outline of µPD784976A Subseries ....................................................................
1.18.1 Features...............................................................................................................................
1.18.2 Applications .........................................................................................................................
1.18.3 Ordering information and quality grade ...............................................................................
1.18.4 Outline of functions ..............................................................................................................
1.18.5 Block diagram ......................................................................................................................
94
94
94
95
96
98
99
99
99
100
101
103
CHAPTER 2 MEMORY SPACE ....................................................................................................... 104
2.1 Memory Space................................................................................................................... 104
2.2 Internal ROM Area............................................................................................................. 106
2.3 Base Area .......................................................................................................................... 108
2.3.1
2.3.2
2.3.3
Vector table area .................................................................................................................
CALLT instruction table area ...............................................................................................
CALLF instruction entry area ...............................................................................................
109
109
109
110
110
115
115
115
2.4 Internal Data Area .............................................................................................................
2.4.1
2.4.2
2.4.3
Internal RAM area ...............................................................................................................
Special function register (SFR) area ...................................................................................
External SFR area ...............................................................................................................
2.5 External Memory Space ...................................................................................................
CHAPTER 3 REGISTERS................................................................................................................
3.1 Control Registers..............................................................................................................
116
116
116
116
120
124
3.1.1
3.1.2
3.1.3
3.1.4
Program counter (PC) .........................................................................................................
Program status word (PSW) ................................................................................................
Use of RSS bit .....................................................................................................................
Stack pointer (SP) ...............................................................................................................
3.2 General-Purpose Registers.............................................................................................. 128
3.2.1
3.2.2
Configuration .......................................................................................................................
Functions .............................................................................................................................
128
130
133
3.3 Special Function Registers (SFR) ...................................................................................
CHAPTER 4 INTERRUPT FUNCTIONS .......................................................................................... 134
4.1 Kinds of Interrupt Request...............................................................................................
135
135
135
135
4.1.1
4.1.2
4.1.3
Software interrupt requests .................................................................................................
Non-maskable interrupt requests ........................................................................................
Maskable interrupt requests ................................................................................................
4.2 Interrupt Service Modes ................................................................................................... 136
4.2.1
4.2.2
4.2.3
Vectored interrupts ..............................................................................................................
Context switching ................................................................................................................
Macro service function .........................................................................................................
136
136
137
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User’s Manual U10905EJ8V1UM
CHAPTER 5 ADDRESSING ............................................................................................................ 138
5.1 Instruction Address Addressing ..................................................................................... 138
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Relative addressing .............................................................................................................
Immediate addressing .........................................................................................................
Table indirect addressing .....................................................................................................
16-bit register addressing ....................................................................................................
20-bit register addressing ....................................................................................................
16-bit register indirect addressing .......................................................................................
20-bit register indirect addressing .......................................................................................
139
140
142
143
143
144
145
5.2 Operand Address Addressing ......................................................................................... 146
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Implied addressing ..............................................................................................................
Register addressing .............................................................................................................
Immediate addressing .........................................................................................................
8-bit direct addressing .........................................................................................................
16-bit direct addressing .......................................................................................................
24-bit direct addressing .......................................................................................................
Short direct addressing ........................................................................................................
Special function register (SFR) addressing function ...........................................................
Short direct 16-bit memory indirect addressing ...................................................................
147
148
149
150
151
152
153
155
156
157
158
159
161
162
163
164
5.2.10 Short direct 24-bit memory indirect addressing ...................................................................
5.2.11 Stack addressing .................................................................................................................
5.2.12 24-bit register indirect addressing .......................................................................................
5.2.13 16-bit register indirect addressing .......................................................................................
5.2.14 Based addressing ................................................................................................................
5.2.15 Indexed addressing .............................................................................................................
5.2.16 Based indexed addressing ..................................................................................................
CHAPTER 6 INSTRUCTION SET .................................................................................................... 166
6.1 Legend ............................................................................................................................... 166
6.2 List of Instruction Operations.......................................................................................... 170
6.3 Instructions Listed by Type of Addressing ....................................................................
196
6.4 Operation Codes ............................................................................................................... 201
6.4.1
6.4.2
Operation code symbols ......................................................................................................
List of operation codes ........................................................................................................
201
204
6.5 Number of Instruction Clocks.......................................................................................... 262
6.5.1
6.5.2
6.5.3
6.5.4
Execution time of instruction................................................................................................
Legend for “Clocks” column .................................................................................................
Explanation of “Clocks” column ...........................................................................................
List of number of clocks .......................................................................................................
262
262
263
264
CHAPTER 7 DESCRIPTION OF INSTRUCTIONS .......................................................................... 294
7.1 8-bit Data Transfer Instruction ......................................................................................... 296
7.2 16-bit Data Transfer Instruction ....................................................................................... 299
7.3 24-bit Data Transfer Instruction ....................................................................................... 302
7.4 8-bit Data Exchange Instruction ...................................................................................... 304
7.5 16-bit Data Exchange Instruction .................................................................................... 306
7.6 8-bit Operation Instructions ............................................................................................. 308
7.7 16-bit Operation Instructions........................................................................................... 318
User’s Manual U10905EJ8V1UM
15
7.8 24-bit Operation Instructions........................................................................................... 325
7.9 Multiplication/Division Instructions ................................................................................ 328
7.10 Special Operation Instructions ........................................................................................ 334
7.11 Increment/Decrement Instructions..................................................................................
344
7.12 Adjustment Instructions................................................................................................... 351
7.13 Shift/Rotate Instructions .................................................................................................. 355
7.14 Bit Manipulation Instructions .......................................................................................... 366
7.15 Stack Manipulation Instructions...................................................................................... 377
7.16 Call/Return Instructions ................................................................................................... 389
7.17 Unconditional Branch Instruction ...................................................................................
403
7.18 Conditional Branch Instructions ..................................................................................... 405
7.19 CPU Control Instructions ................................................................................................. 425
7.20 Special Instructions .......................................................................................................... 435
7.21 String Instructions ............................................................................................................ 438
CHAPTER 8 DEVELOPMENT TOOLS............................................................................................ 475
8.1 Development Tools ........................................................................................................... 476
8.2 PROM Programming Tools .............................................................................................. 479
8.3 Flash Memory Programming Tools ................................................................................. 479
CHAPTER 9 EMBEDDED SOFTWARE .......................................................................................... 480
9.1 Real-time OS...................................................................................................................... 480
APPENDIX A INDEX OF INSTRUCTIONS (MNEMONICS: BY FUNCTION) ..................................
APPENDIX B INDEX OF INSTRUCTIONS (MNEMONICS: ALPHABETICAL ORDER) ................
481
484
APPENDIX C REVISION HISTORY .................................................................................................. 486
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User’s Manual U10905EJ8V1UM
LIST OF FIGURES
Figure No.
1-1
Title
Page
20
78K Series and 78K/IV Series Composition .....................................................................................
2-1
2-2
Memory Map .....................................................................................................................................
Internal RAM Memory Mapping ........................................................................................................
105
113
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Program Counter (PC) Configuration ...............................................................................................
Program Status Word (PSW) Configuration .....................................................................................
Stack Pointer (SP) Configuration ......................................................................................................
Data Saved to Stack Area.................................................................................................................
Data Restored from Stack Area ........................................................................................................
General-Purpose Register Configuration..........................................................................................
General-Purpose Register Addresses ..............................................................................................
116
117
124
125
126
128
129
4-1
8-1
Context Switching Operation by Interrupt Request Generation ........................................................
Development Tools Structure............................................................................................................
136
478
User’s Manual U10905EJ8V1UM
17
LIST OF TABLES
Table No.
Title
Page
106
2-1
2-2
2-3
List of Internal ROM Space for 78K/IV Series Products ...................................................................
Vector Table ......................................................................................................................................
Internal RAM Area in 78K/IV Series Products ..................................................................................
109
111
3-1
3-2
Register Bank Selection ...................................................................................................................
Function Names and Absolute Names .............................................................................................
119
132
4-1
Interrupt Request Servicing ..............................................................................................................
134
6-1
6-2
6-3
6-4
6-5
List of Instructions by 8-Bit Addressing .............................................................................................
List of Instructions by 16-Bit Addressing ...........................................................................................
List of Instructions by 24-Bit Addressing ...........................................................................................
List of Instructions by Bit Manipulation Instruction Addressing .........................................................
List of Instructions by Call/Return Instruction/Branch Instruction Addressing...................................
196
197
198
199
200
8-1
Types and Functions of Development Tools .....................................................................................
476
18
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
The 78K Series consists of 6 series as shown in Figure 1-1.
The 78K/IV Series is one of these 6 series, comprising products with an on-chip 16-bit CPU.
These products have an instruction set suitable for control applications, a high-performance interrupt controller,
and incorporate a high-performance CPU equipped with a maximum 1 MB program memory space and maximum
16 MB data memory space.
The 78K/IV Series offers a variety of subseries, enabling the most suitable subseries to be selected for a particular
application.
All the subseries have the same CPU, and differ only in their peripheral hardware. Consequently, the entire
instruction set is common to all subseries. Moreover, individual products within a subseries differ only in the size
of on-chip memory.
19
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
Figure 1-1. 78K Series and 78K/IV Series Composition
78K Series
78K/0S Series
78K/0 Series
8-bit single-chip
microcontrollers
78K/I Series
78K/II Series
78K/III Series
78K/IV Series
µµPD784026 Subseries
µPD784038 Subseries
µPD784038Y Subseries
µPD784046 Subseries
µPD784216A Subseries
µPD784216AY Subseries
µPD784218A Subseries
µPD784218AY Subseries
µPD784225 Subseries
µPD784225Y Subseries
µPD784908 Subseries
µPD784915 Subseries
µPD784928 Subseries
µPD784928Y Subseries
16-bit single-chip
microcontrollers
µPD784938A Subseries
µPD784956A Subseries
µPD784976A Subseries
20
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.1 78K/IV Series Product Lineup
: Under mass production
: Under development
I2C bus supported
Multimaster I2C bus supported
µ
µ
PD784038Y
PD784225Y
µPD784225
80 pins,
Standard models
µPD784038
Enhanced internal memory
capacity, pin compatible with the
µPD784026
added ROM correction
µ
PD784026
Enhanced A/D,
16-bit timer,
and power
Multimaster I2C bus supported
PD784216AY
PD784216A
Multimaster I2C bus supported
µ
µPD784218AY
management
µ
µPD784218A
100 pins,
enhanced I/O and
internal memory capacity
Enhanced internal memory capacity,
added ROM correction
µ
PD784046
On-chip 10-bit A/D
ASSP models
µPD784956A
For DC inverter control
µ
PD784938A
Enhanced function of the
enhanced internal memory capacity,
added ROM correction
µ
PD784908,
µ
PD784908
On-chip IEBusTM
controller
Multimaster I2C bus supported
µ
PD784928Y
PD784928
Enhanced function of the
µ
µ
PD784915
µPD784915
Equipped with analog circuit for
software servo control VCR,
enhanced timer
µ
PD784976A
On-chip VFD
controller/driver
21
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.2 Product Outline of µPD784026 Subseries
(µPD784020, 784021, 784025, 784026, 78P4026)
1.2.1 Features
• Pins are compatible with µPD78234 Subseries
• Minimum instruction execution time: 160 ns/320 ns/640 ns/1,280 ns (at 25 MHz operation)
• On-chip memory
• ROM
Mask ROM : 48 KB (µPD784025)
64 KB (µPD784026)
None (µPD784020, 784021)
PROM
• RAM
: 64 KB (µPD78P4026)
: 2,048 bytes (µPD784021, 784025, 784026)
512 bytes (µPD784020)
• I/O pins: 64
46 (µPD784020, 784021 only)
• Timer/counter: 16-bit timer/counter × 3 units
16-bit timer × 1 unit
• Watchdog timer: 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
CSI (3-wire serial I/O, SBI): 1 channel
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Standby function: HALT/STOP/IDLE mode
• Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (except µPD784020, 784021)
• Power supply voltage: VDD = 2.7 to 5.5 V
1.2.2 Applications
Laser beam printers, autofocus cameras, plain paper copiers, printers, electronic typewriters, air conditioners,
electronic musical instruments, cellular phones, etc.
22
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.2.3 Ordering information and quality grade
(1) Ordering information
Part Number
µPD784020GC-3B9
µPD784021GC-3B9
µPD784021GK-BE9
µPD784025GC-×××-3B9
µPD784026GC-×××-3B9
µPD78P4026GC-3B9
Package
Internal ROM
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin ceramic WQFN (14 × 14 mm)
None
None
None
Mask ROM
Mask ROM
One-time PROM
Preprogramming one-time PROM
EPROM
Note
µ
PD78P4026GC-×××-3B9
µPD78P4026KK-T
Note QTOPTM microcontroller. “QTOP microcontroller” is a general term for a single-chip microcontroller
with on-chip one-time PROM, for which total support is provided by NEC programming service, from
programming to marking, screening, and verification.
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
Standard
µPD784020GC-3B9
µPD784021GC-3B9
µPD784021GK-BE9
µPD784025GC-×××-3B9
µPD784026GC-×××-3B9
µPD78P4026GC-3B9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin ceramic WQFN (14 × 14 mm)
Standard
Standard
Standard
Standard
Standard
Standard
Note
µ
PD78P4026GC-×××-3B9
µPD78P4026KK-T
Not applicable
(for function evaluation)
Note QTOP microcontroller. “QTOP microcontroller” is a general term for a single-chip microcontroller with
on-chip one-time PROM, for which total support is provided by NEC programming service from
programming to marking, screening, and verification.
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Caution The EPROM version of the µPD78P4026 does not have a level of reliability intended for volume
productionofcustomers’equipment,andshouldonlybeusedforexperimentalorpreproduction
function evaluation.
Remark ××× indicates ROM code suffix.
23
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.2.4 Outline of functions
Product Name
µPD784020
µPD784021 µPD784025
µPD784026 µPD78P4026
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
160 ns/320 ns/640 ns/1,280 ns (at 25 MHz operation)
ROM
RAM
On-chip memory capacity
None
48 KB
64 KB
64 KB
(Mask ROM) (Mask ROM) (PROM)
512 bytes
2,048 bytes
Memory space
1 MB total both program and data
I/O ports
Total
46
64
8
Input
8
Input/output
Output
34
56
0
4
Pins with
additional
Pins with pull-up resistors
LED direct drive output
Transistor direct drive
32
54
24
8
Note
functions
8
Real-time output port
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter 0:
(16 bits)
Timer register × 1
Compare register × 2 • Toggle output
Pulse output capability
Capture register × 1
• PWM/PPG output
• One-shot pulse output
Timer/counter 1:
(8/16 bits)
Timer register × 1
Compare register × 1 • Real-time output: 4 bits × 2
Capture register × 1
Pulse output capability
Capture/compare register
×
1
Timer/counter 2:
(8/16 bits)
Timer register × 1
Compare register × 1 • Toggle output
Pulse output capability
Capture/compare register
× 1 • PWM/PPG output
Capture register × 1
Timer 3:
Timer register × 1
(8/16 bits)
Compare register × 1
Watchdog timer
1 channel
PWM output function
Serial interfaces
12-bit resolution × 2 channels
•
•
UART/IOE (3-wire serial I/O)
CSI (3-wire serial I/O, SBI)
:
:
2 channels (on-chip baud rate generator)
1 channel
A/D converter
D/A converter
Standby function
Interrupts
8-bit resolution × 8 channels
8-bit resolution × 2 channels
HALT/STOP/IDLE mode
Hardware sources
Software sources
Non-maskable
Maskable
23 (internal: 16, external: 7 (sampling clock variable input: 1) )
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 15, external: 6
•
•
4-level programmable priority
3 kinds of process mode (vectored interrupt/macro service/context switching)
Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8,
fCLK/16 (also usable as 1-bit output port)
—
Power supply voltage
Package
VDD = 2.7 to 5.5 V
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch, 12 × 12 mm: µPD784021 only)
• 80-pin ceramic WQFN (14 × 14 mm: µPD78P4026 only)
Note The pins with additional functions are included in the I/O pins.
24
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.2.5 Block diagram
R
X
D/SI1
UART/IOE2
NMI
PROGRAMMABLE
INTERRUPT
CONTROLLER
T
XD/SO1
BAUD-RATE
GENERATOR
ASCK/SCK1
INTP0 to INTP5
R
D2/SI2
TX
X
D2/SO2
UART/IOE1
INTP3
TO0
TO1
TIMER/
COUNTER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
SCK0
SO0/SB0
SI0
CLOCKED
SERIAL
INTERFACE
TIMER/
COUNTER1
(16 BITS)
INTP0
ASTB/CLKOUT
AD0 to AD7
A8 to A15
A16 to A19
RD
CLOCK OUTPUT
INTP1
INTP2/CI
TO2
TIMER/
COUNTER2
(16 BITS)
78K/IV
CPU CORE
ROM
TO3
WR
TIMER3
WAIT/HLDRQ
REFRQ/HLDAK
D0 to D7
(A0 to A16)
(CE)
BUS I/F
(16 BITS)
P00 to P03
P04 to P07
PWM0
REAL-TIME
OUTPUT
PORT
(OE)
(PGM)
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
RAM
PWM
PWM1
ANO0
ANO1
D/A
CONVERTER
AVREF2
AVREF3
ANI0 to ANI7
AVDD
A/D
CONVERTER
AVREF1
AVSS
RESET
TEST
X1
WATCHDOG
TIMER
INTP5
SYSTEM
CONTROL
X2
V
VPP
VSDSD
Remarks 1. Internal ROM and RAM capacities vary depending on the products.
2. VPP applies to the µPD78P4026 only.
3. The pins in parentheses are used in the PROM programming mode.
25
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.3 Product Outline of µPD784038 Subseries
(µPD784031, 784035, 784036, 784037, 784038, 78P4038, 784031(A), 784035(A), 784036(A))
1.3.1 Features
• Pins are compatible with µPD78234 Subseries, µPD784026 Subseries, and µPD784038Y Subseries
• On-chip memory capacity of µPD78234 Subseries and µPD784026 Subseries is expanded.
• Minimum instruction execution time 125 ns/250 ns/500 ns/1,000 ns (at 32 MHz operation)
• On-chip memory
• ROM
Mask ROM : None (µPD784031, 784031(A))
48 KB (µPD784035, 784035(A))
64 KB (µPD784036, 784036(A))
96 KB (µPD784037)
128 KB (µPD784038)
PROM
• RAM
: 128 KB (µPD78P4038)
: 2,048 bytes (µPD784031, 784035, 784036, 784031(A), 784035(A), 784036(A))
3,584 bytes (µPD784037)
4,352 bytes (µPD784038)
• I/O port: 64
• Timer/counter: 16-bit timer/counter × 3 units
16-bit timer × 1 unit
• Watchdog timer: 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• 12-bit PWM output: 2 channels
• Serial interface
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Standby function
HALT/STOP/IDLE mode
• Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, and fCLK/16 (except µPD784031)
• Power supply voltage: VDD = 2.7 to 5.5 V
26
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.3.2 Applications
• Standard-grade devices: Laser beam printers, autofocus cameras, plain paper copiers, printers, electronic
typewriters, air conditioners, electronic musical instruments, cellular phones, etc.
• Special-grade devices:
Controlequipmentinautomobileelectricalsystem, gasdetectorandcutoffequipment,
and various safety equipment.
1.3.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784031GC-3B9
µPD784031GC-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) None
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) None
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) None
µPD784031GC(A)-×××-3E9
µPD784031GK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
None
µPD784035GC-×××-3B9
µPD784035GC-×××-8BT
µPD784035GC(A)-×××-3B9
µPD784035GK-×××-BE9
µPD784036GC-×××-3B9
µPD784036GC-×××-8BT
µPD784036GC(A)-×××-3B9
µPD784036GK-×××-BE9
µPD784037GC-×××-3B9
µPD784037GC-×××-8BT
µPD784037GK-×××-BE9
µPD784038GC-×××-3B9
µPD784038GC-×××-8BT
µPD784038GK-×××-BE9
µPD78P4038GC-3B9
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) One-time PROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) One-time PROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Preprogrammingone-timePROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Preprogrammingone-timePROM
µPD78P4038GC-8BT
Note
µPD78P4038GC-×××-3B9
µPD78P4038GC-×××-8BT
µPD78P4038GK-BE9
µPD78P4038GK-×××-BE9
µPD78P4038KK-T
Note
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin ceramic WQFN (14 × 14 mm)
One-time PROM
Preprogrammingone-timePROM
EPROM
Note
Note QTOP microcontrollers. “QTOP microcontroller” is a general term for a single-chip microcontroller with on-
chip one-time ROM, for which total support is provided by NEC programming service, from programming
to marking, screening, and verification.
Remark ××× indicates ROM code suffix.
27
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2) Quality grades
Part Number
Package
Quality Grade
µPD784031GC-3B9
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD784031GC-8BT
µPD784031GC-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
µPD784035GC-×××-3B9
µPD784035GC-×××-8BT
µPD784035GK-×××-BE9
µPD784036GC-×××-3B9
µPD784036GC-×××-8BT
µPD784036GK-×××-BE9
µPD784037GC-×××-3B9
µPD784037GC-×××-8BT
µPD784037GK-×××-BE9
µPD784038GC-×××-3B9
µPD784038GC-×××-8BT
µPD784038GK-×××-BE9
µPD78P4038GC-3B9
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
µPD78P4038GC-×××-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD78P4038GC-×××-3B9 Note 80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
µPD78P4038GC-×××-8BT Note 80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD78P4038GK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
Standard
Note
µPD78P4038GK-×××-BE9
µPD784031GC(A)-×××-3B9
µPD784035GC(A)-×××-3B9
µPD784036GC(A)-×××-3B9
µPD78P4038KK-T
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Special
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Special
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Special
80-pin ceramic WQFN (14 × 14 mm)
Not applicable
(forfunctionevaluation)
Note QTOP microcontrollers. “QTOP microcontroller” is a general term for a single-chip microcontroller with on-
chip one-time ROM, for which total support is provided by NEC programming service, from programming
to marking, screening, and verification.
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
Caution The EPROM version of the µPD78P4028 does not have a level of reliability intended for volume
production of customer’s equipment, and should only be used for experimental or preproduction
function evaluation.
28
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.3.4 Outline of functions
Product Name µPD784031, µPD784035, µPD784036, µPD784037 µPD784038 µPD78P4038
784031(A) 784035(A) 784036(A)
Number of basic instructions (mnemonics) 113
Item
General-purpose registers
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
125 ns/250 ns/500 ns/1,000 ns (at 32 MHz operation)
On-chip memory capacity
ROM
None
48 KB
64 KB
96 KB
128 KB
128 KB
(Mask ROM) (Mask ROM) (Mask ROM) (Mask ROM) (One-time PROM
or EPROM)
RAM
2,048 bytes
3,584 bytes 4,352 bytes
Memory space
1 MB total both programs and data
I/O ports
Total
64
8
Input
Input/Output
56
Pins with
Pins with pull-up resistors 54
additional
functionsNote
LED direct drive output
24
Transistor direct drive
8
Real-time output port
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter 0: Timer register × 1
Pulse output capability
• Toggle output
• PWM/PPG output
• One-shot pulse output
(16 bits)
Capture register × 1
Compare register × 2
Timer/counter 1: Timer register × 1
Pulse output capability
(8/16 bits)
Capture register × 1
• Real-time output (4 bits × 2)
Capture/compare register × 1
Compare register × 1
Timer/counter 2: Timer register × 1
Pulse output capability
(8/16 bits)
Capture register × 1
• Toggle output
Capture/compare register × 1 • PWM/PPG output
Compare register × 1
Timer 3:
Timer register × 1
(8/16 bits)
Compare register × 1
PWM output
12-bit resolution × 2 channels
• UART/IOE (3-wire serial I/O)
Serial interfaces
: 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
A/D converter
D/A converter
Clock output
8-bit resolution × 8 channels
8-bit resolution × 2 channels
—
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, and fCLK/16 (also usable as 1-bit output port)
Watchdog timer
Standby function
1 channel
HALT/STOP/IDLE mode
Interrupts
Hardware sources
23 (internal: 16, external: 7 (sampling clock variable input: 1) )
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Software sources
Non-maskable
Maskable
Internal: 15, external: 6
• 4-level programmable priority
• 3 processing modes (vectored interrupt, macro service, context switching)
Power supply voltage
Package
VDD = 2.7 to 5.5 V
• 80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm)
• 80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
• 80-pin ceramic WQFN (14 × 14 mm): µPD78P4038 only
Note The pins with additional functions are included in the I/O pins.
29
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.3.5 Block diagram
R
X
D/SI1
UART/IOE2
NMI
PROGRAMMABLE
INTERRUPT
CONTROLLER
T
XD/SO1
BAUD-RATE
GENERATOR
ASCK/SCK1
INTP0 to INTP5
R
X
D2/SI2
UART/IOE1
INTP3
TO0
TO1
TXD2/SO2
TIMER/
COUNTER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
SCK0/SCL
SO0/SDA
SI0
CLOCKED
SERIAL
INTERFACE
TIMER/
COUNTER1
(16 BITS)
INTP0
ASTB/CLKOUT
AD0 to AD7
A8 to A15
A16 to A19
RD
CLOCK OUTPUT
INTP1
INTP2/CI
TO2
TIMER/
COUNTER2
(16 BITS)
78K/IV
CPU CORE
ROM
TO3
WR
TIMER3
WAIT/HLDRQ
REFRQ/HLDAK
D0 to D7
(A0 to A16)
(CE)
BUS I/F
(16 BITS)
P00 to P03
P04 to P07
PWM0
REAL-TIME
OUTPUT PORT
(OE)
(PGM)
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
RAM
PWM
PWM1
ANO0
ANO1
D/A
CONVERTER
AVREF2
AVREF3
ANI0 to ANI7
AV
A/D
CONVERTER
AVREF1
AVSS
RESET
TEST
X1
WATCHDOG
TIMER
INTP5
SYSTEM
CONTROL
X2
VPP
V
VSDSD
Remarks 1. Internal ROM and RAM capacities vary depending on the products.
2. VPP applies to the µPD78P4038 only.
3. The pins in parentheses are used in the PROM programming mode
30
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.4 Product Outline of µPD784038Y Subseries
(µPD784031Y, 784035Y, 784036Y, 784037Y, 784038Y, 78P4038Y)
1.4.1 Features
• I2C bus control function is added to µPD784038.
• Pins are compatible with µPD78234 Subseries, µPD784026 Subseries, and µPD784038.
• On-chip memory capacity of µPD78234 Subseries and µPD784026 Subseries is expanded.
• Minimum instruction execution time: 125 ns/250 ns/500 ns/1,000 ns (at 32 MHz operation)
• On-chip memory
• ROM
Mask ROM : None (µPD784031Y)
48 KB (µPD784035Y)
64 KB (µPD784036Y)
96 KB (µPD784037Y)
128 KB (µPD784038Y)
PROM
• RAM
: 128 KB (µPD78P4038Y)
: 2,048 bytes (µPD784031Y, 784035Y, 784036Y)
3,584 bytes (µPD784037Y)
4,352 bytes (µPD784038Y)
• I/O port: 64
• Timer/counter: 16-bit timer/counter × 3 units
16-bit timer × 1 unit
• Watchdog timer: 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• 12-bit PWM output: 2 channels
• Serial interface
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus): 1 channel
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Standby function
HALT/STOP/IDLE modes
• Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8,and fCLK/16 (except µPD784031Y)
• Power supply voltage: VDD = 2.7 to 5.5 V
31
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.4.2 Applications
Cellular phones, cordless phones, audiovisual equipment, etc.
1.4.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784031YGC-3B9
µPD784031YGC-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) None
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) None
µPD784031YGK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
None
µPD784035YGC-×××-3B9
µPD784035YGC-×××-8BT
µPD784035YGK-×××-BE9
µPD784036YGC-×××-3B9
µPD784036YGC-×××-8BT
µPD784036YGK-×××-BE9
µPD784037YGC-×××-3B9
µPD784037YGC-×××-8BT
µPD784037YGK-×××-BE9
µPD784038YGC-×××-3B9
µPD784038YGC-×××-8BT
µPD784038YGK-×××-BE9
µPD78P4038YGC-3B9
µPD78P4038YGC-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Mask ROM
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Mask ROM
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) One-time PROM
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) One-time PROM
µPD78P4038YGC-×××-3B9 Note 80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Preprogrammingone-timePROM
µPD78P4038YGC-×××-8BT Note 80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Preprogrammingone-timePROM
µPD78P4038YGK-BE9
µPD78P4038YGK-×××-BE9 Note 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78P4038YKK-T 80-pin ceramic WQFN (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
One-time PROM
Preprogrammingone-timePROM
EPROM
Note QTOP microcontrollers. “QTOP microcontroller” is a general term for a single-chip microcontroller with on-
chip one-time ROM, for which total support is provided by NEC programming service, from programming
to marking, screening, and verification.
Remark ××× indicates ROM code suffix.
Caution µPD784035YGK-×××-BE9 and µPD784036YGK-×××-BE9 are under development.
32
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2) Quality grades
Part Number
Package
Quality Grade
µPD784031YGC-3B9
µPD784031YGC-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD784031YGK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
µPD784035YGC-×××-3B9
µPD784035YGC-×××-8BT
µPD784035YGK-×××-BE9
µPD784036YGC-×××-3B9
µPD784036YGC-×××-8BT
µPD784036YGK-×××-BE9
µPD784037YGC-×××-3B9
µPD784037YGC-×××-8BT
µPD784037YGK-×××-BE9
µPD784038YGC-×××-3B9
µPD784038YGC-×××-8BT
µPD784038YGK-×××-BE9
µPD78P4038YGC-3B9
µPD78P4038YGC-8BT
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD78P4038YGC-×××-3B9 Note 80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm) Standard
µPD78P4038YGC-×××-8BT Note 80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm) Standard
µPD78P4038YGK-BE9
µPD78P4038YGK-×××-BE9 Note 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD78P4038YKK-T 80-pin ceramic WQFN (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Standard
Standard
Not applicable
(for function evaluation)
Note QTOP microcontrollers. “QTOP microcontroller” is a general term for a single-chip microcontroller with on-
chip one-time ROM, for which total support is provided by NEC programming service, from programming
to marking, screening, and verification.
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
Cautions 1. The EPROM version of the µPD78P4028 dose not have a level of reliability intended for volume
productionofcustomer’sequipment,andshouldonlybeusedforexperimentalorpreproduction
function evaluation.
2. µPD784035YGK-×××-BE9 and µPD784036YGK-×××-BE9 are under development.
33
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.4.4 Outline of functions
Product Name µPD784031Y µPD784035Y µPD784036Y µPD784037Y µPD784038Y µPD78P4038Y
Item
Number of basic instructions (mnemonics) 113
General-purpose registers
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
125 ns/250 ns/500 ns/1,000 ns (at 32 MHz operation)
Minimum instruction execution time
On-chip memory capacity
ROM
None
48 KB
64 KB
96 KB
128 KB
128 KB
(Mask ROM) (Mask ROM) (Mask ROM) (Mask ROM) (One-time PROM
or EPROM)
RAM
2,048 bytes
3,584 bytes 4,352 bytes
Memory space
1 MB total both programs and data
I/O ports
Total
64
8
Input
Input/Output
56
Pins with pull-up resistors 54
LED direct drive output 24
Pins with
additional
functionsNote
Transistor direct drive
8
Real-time output port
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter 0: Timer register × 1
Capture register × 1
Pulse output capability
• Toggle output
Compare register × 2
• PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register × 1
Capture register × 1
Pulse output capability
• Real-time output (4 bits × 2)
Capture/compare register × 1
Compare register × 1
Timer/counter 2: Timer register × 1
Capture register × 1
Pulse output capability
• Toggle output
Capture/compare register × 1 • PWM/PPG output
Compare register × 1
Timer 3:
Timer register × 1
Compare register × 1
PWM output
12-bit resolution × 2 channels
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, 2-wire serial I/O, I C bus) : 1 channel
2
A/D converter
D/A converter
Clock output
8-bit resolution × 8 channels
8-bit resolution × 2 channels
—
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8,and fCLK/16 (also usable as 1-bit output port)
Watchdog timer
Standby function
1 channel
HALT/STOP/IDLE mode
Interrupts
Hardware sources
24 (internal: 17, external: 7 (sampling clock variable input: 1) )
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Software sources
Non-maskable
Maskable
Internal: 16, external: 6
• 4-level programmable priority
• 3 processing modes (vectored interrupt, macro service, context switching)
Power supply voltage
Package
VDD = 2.7 to 5.5 V
• 80-pin plastic QFP (14 × 14 mm, thickness: 1.4 mm)
• 80-pin plastic QFP (14 × 14 mm, thickness: 2.7 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
• 80-pin ceramic WQFN (14 × 14 mm): µPD78P4038Y only
Note The pins with additional functions are included in the I/O pins.
34
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.4.5 Block diagram
R
X
D/SI1
UART/IOE2
NMI
PROGRAMMABLE
T
XD/SO1
INTERRUPT
BAUD-RATE
GENERATOR
ASCK/SCK1
CONTROLLER
INTP0 to INTP5
R
X
D2/SI2
UART/IOE1
INTP3
TO0
TO1
TXD2/SO2
TIMER/
COUNTER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
SCK0/SCL
SO0/SDA
SI0
CLOCKED
SERIAL
INTERFACE
TIMER/
COUNTER1
(16 BITS)
INTP0
ASTB/CLKOUT
AD0 to AD7
A8 to A15
A16 to A19
RD
CLOCK OUTPUT
INTP1
INTP2/CI
TO2
TIMER/
COUNTER2
(16 BITS)
78K/IV
CPU CORE
ROM
TO3
WR
TIMER3
WAIT/HLDRQ
REFRQ/HLDAK
D0 to D7
(A0 to A16)
(CE)
BUS I/F
(16 BITS)
P00 to P03
P04 to P07
PWM0
REAL-TIME
OUTPUT PORT
(OE)
(PGM)
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
RAM
PWM
PWM1
ANO0
ANO1
D/A
CONVERTER
AVREF2
AVREF3
ANI0 to ANI7
AVDD
A/D
CONVERTER
AVREF1
AVSS
RESET
TEST
X1
WATCHDOG
TIMER
INTP5
SYSTEM
CONTROL
X2
VPP
V
VSDSD
Remarks 1. Internal ROM and RAM capacities vary depending on the products.
2. VPP applies to the µPD78P4038Y only.
3. The pins in parenthesis are used in the PROM programming mode.
35
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.5 Product Outline of µPD784046 Subseries
(µPD784044,784054,784046,78F4046,784044(A),784044(A1),784044(A2),784046(A),784046(A1),
784046(A2), 784054(A), 784054(A1), 784054(A2))
1.5.1 Features
• Minimum instruction execution time:
125 ns (at internal 16 MHz operation).......... µPD784044, 784046, 784054, 78F4046
160 ns (at internal 12.5 MHz operation)....... µPD784044(A), 784046(A), 784054(A)
200 ns (at internal 10 MHz operation).......... µPD784044(A1), (A2), 784046(A1), (A2), 784054(A1), (A2)
• On-chip memory
• ROM
Mask ROM
: 64 KB (µPD784046, 784046(A), (A1), (A2))
: 32 KB (µPD784044, 784044(A), (A1), (A2), 784054, 784054(A), (A1), (A2))
Flash memory : 64 KB (µPD78F4046)
• RAM : 2,048 bytes (µPD784046, 784046(A), (A1), (A2), 78F4046)
1,024 bytes (µPD784044, 784044(A), (A1), (A2), 784054, 784054(A), (A1), (A2))
• I/O port: 65 (64 for only µPD784054 and 784054(A), (A1), (A2))
• Timer/counter: 16-bit timer/counter × 2 units
16-bit timer × 3 units
(only 16-bit timer × 3 units for µPD784054 and 784054(A), (A1), (A2))
• Watchdog timer: 1 channel
• A/D converter: 10-bit resolution × 16 channels (VDD = 4.5 to 5.5 V)
• Serial interface
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Standby function
HALT/STOP/IDLE mode (/standby invalid function mode … µPD784054 and 784054(A), (A1), (A2) only)
• Power supply voltage: VDD = 4.0 to 5.5 V
1.5.2 Applications
• Standard: Water heaters, vending machines, office automation equipment such as PPCs or printers, and factory
automation equipment such as robots or automation machine tools
• Special:
Automobile electrical systems, etc.
36
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.5.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784044GC-×××-3B9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
µPD784044GC(A)-×××-3B9
µPD784044GC(A1)-×××-3B9
µPD784044GC(A2)-×××-3B9
µPD784046GC-×××-3B9 Note
µPD784046GC(A)-×××-3B9 Note
µPD784046GC(A1)-×××-3B9 Note
µPD784046GC(A2)-×××-3B9 Note
µPD784054GC-×××-3B9
µPD784054GC(A)-×××-3B9
µPD784054GC(A1)-×××-3B9
µPD784054GC(A2)-×××-3B9
µPD78F4046GC-3B9 Note
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
µPD784044GC-×××-3B9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic QFP (14 × 14 mm)
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Special
Special
Special
µPD784046GC-×××-3B9 Note
µPD784054GC-×××-3B9
µPD78F4046GC-3B9 Note
µPD784044GC(A)-×××-3B9
µPD784044GC(A1)-×××-3B9
µPD784044GC(A2)-×××-3B9
µPD784046GC(A)-×××-3B9 Note
µPD784046GC(A1)-×××-3B9 Note
µPD784046GC(A2)-×××-3B9 Note
µPD784054GC(A)-×××-3B9
µPD784054GC(A1)-×××-3B9
µPD784054GC(A2)-×××-3B9
Please refer to “Quality grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Note Under development
Remark ××× indicates ROM code suffix.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.5.4 Outline of functions
(1) µPD784044, 784044(A), (A1), (A2), 784046, 784046(A), (A1), (A2), 78F4046
Product Name
µPD784044,
µPD784046,
µPD78F4046
Item
784044(A), (A1), (A2)
784046(A), (A1), (A2)
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
125 ns (at internal clock 16 MHz operation) ..... µPD784044, 78F4046
160 ns (at internal clock 12.5 MHz operation) .. µPD784044(A), 784046(A)
200 ns (at internal clock 10 MHz operation) ..... µPD784044(A1), (A2),
784046(A1), (A2)
On-chip memory capacity
Memory space
ROM
RAM
32 KB
64 KB
64 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
1,024 bytes
2,048 bytes
1 MB total both programs and data
I/O ports
Total
65
17
48
29
Input
Input/Output
Pins with
Pins with pull-up resistors
additional
functionsNote
Real-time output port
Timer/counters
4 bits × 1
Timer 0:
Timer register × 1
Pulse output capability
Capture/compare register × 4 • Toggle output
• Set/Reset output
Timer 1:
Timer register × 1
Compare register × 2
Pulse output capability
• Toggle output
• Set/Reset output
Timer/counter 2:
Timer/counter 3:
Timer 4:
Timer register × 1
Compare register × 2
Pulse output capability
• Toggle output
• PWM/PPG output
Timer register × 1
Compare register × 2
Pulse output capability
• Toggle output
• PWM/PPG output
Timer register × 1
Pulse output capability
Compare register × 2
• Real-time output (4 bits × 1)
A/D converter
Serial interface
Watchdog timer
Interrupts
10-bit resolution × 16 channels (AVDD = 4.5 to 5.5 V)
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
1 channel
Hardware sources
Software sources
Non-maskable
Maskable
27 (internal: 23, external: 8 (compatible with internal: 4))
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 22, external: 7 (compatible with internal: 4)
• 4-level programmable priority
•
3 processing modes (vectored interrupt, macro service, context switching)
Bus sizing function
Standby function
8-bit/16-bit external data bus selectable
HALT/STOP/IDLE mode
Power supply voltage
Package
VDD = 4.0 to 5.5 V
80-pin plastic QFP (14 × 14 mm)
Note The pins with additional functions are included in the I/O pins.
38
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2) µPD784054, 784054(A), (A1), (A2)
Product Name
µPD784054, 784054(A), (A1), (A2)
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
125 ns (at internal clock 16 MHz operation) ...... µPD784054
160 ns (at internal clock 12.5 MHz operation) ... µPD784054(A)
200 ns (at internal clock 10 MHz operation) ...... µPD784054(A1), (A2)
ROM
RAM
On-chip memory capacity
Memory space
32 KB (Mask ROM)
1,024 bytes
1 MB total both programs and data
I/O ports
Total
64
17
47
29
Input
Input/Output
Pins with
Pins with pull-up resistors
additional
functionsNote
Timers
Timer 0:
(16 bits)
Timer register × 1
Capture/compare register × 4 • Toggle output
• Set/Reset output
Pulse output capability
Timer 1:
(16 bits)
Timer register × 1
Compare register × 2
Pulse output capability
• Toggle output
• Set/Reset output
Timer 4:
(16 bits)
Timer register × 1
Compare register × 2
A/D converter
Serial interface
Watchdog timer
Interrupts
10-bit resolution × 16 channels (AVDD = 4.5 to 5.5 V)
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
1 channel
Hardware sources
Software sources
Non-maskable
Maskable
23 (internal: 19, external: 8 (compatible with internal: 4))
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 18, external: 7 (compatible with internal: 4)
• 4-level programmable priority
•
3 processing modes (vectored interrupt, macro service, context switching)
Bus sizing function
Standby function
8-bit/16-bit external data bus selectable
HALT/STOP/IDLE mode/standby invalid function mode
VDD = 4.0 to 5.5 V
Power supply voltage
Package
80-pin plastic QFP (14 × 14 mm)
Note The pins with additional functions are included in the I/O pins.
39
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.5.5 Block diagram
(1) µPD784044, 784044(A), (A1), (A2), 784046, 784046(A), (A1), (A2), 78F4046
RxD/SI1
PROGRAMMABLE
INTERRUPT
CONTROLLER
UART/IOE1
NMI
TxD/SO1
INTP0 to INTP6
BAUD-RATE
GENERATOR
ASCK/SCK1
RxD2/SI2
TxD2/SO2
UART/IOE2
INTP0 to INTP3
TO00 to TO03
TIMER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
BWD
TIMER1
(16 BITS)
AD0 to AD15
A16 to A19
RD
TO10, TO11
BUS I/F
LWR, HWR
ASTB
INTP5/TI2
WAIT
TIMER/COUNTER2
78K/IV
CPU CORE
ROM
(16 BITS)
TO20, TO21
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
P00 to P03
P10 to P13
INTP6/TI3
TIMER/COUNTER3
P20
P21 to P27
(16 BITS)
TO30, TO31
P30 to P37
P40 to P47
P50 to P57
P60 to P63
P70 to P77
P80 to P87
P90 to P94
TIMER4
(16 BITS)
RAM
REAL-TIME
OUTPUT PORT
RTP0 to RTP3
ANI0 to ANI15
AVDD
A/D
CONVERTER
AVSS
AVREF
RESET
CLKOUT
MODE
X1
INTP4
SYSTEM
CONTROL
WATCHDOG
TIMER
X2
Note
VPP
V
DD
SS
V
Note VPP applies to the µPD78F4046 only.
Remark Internal ROM and RAM capacities vary depending on the products.
40
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2) µPD784054, 784054(A), (A1), (A2)
BWD
PROGRAMMABLE
INTERRUPT
CONTROLLER
NMI
AD0 to AD15
A16 to A19
RD
INTP0 to INTP6
BUS I/F
LWR, HWR
ASTB
WAIT
INTP0 to INTP3
TO00 to TO03
TIMER0
(16 BITS)
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
P00 to P03
P10 to P13
TIMER1
(16 BITS)
TO10, TO11
P20
P21 to P27
TIMER4
(16 BITS)
78K/IV
CPU CORE
ROM
P30 to P37
P40 to P47
P50 to P57
P60 to P63
P70 to P77
P80 to P87
ANI0 to ANI15
AVDD
A/D
CONVERTER
AVSS
AVREF
INTP4
WATCHDOG
TIMER
RAM
RxD/SI1
TxD/SO1
UART/IOE1
P90 to P94
CLKOUT
BAUD-RATE
GENERATOR
ASCK/SCK1
RESET
MODE
MODE1
X1
RxD2/SI2
TxD2/SO2
SYSTEM
CONTROL
UART/IOE2
BAUD-RATE
GENERATOR
ASCK2/SCK2
X2
V
DD
VSS
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User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.6 Product Outline of µPD784216A Subseries
(µPD784214A, 784215A, 784216A, 78F4216A)
1.6.1 Features
• Peripheral functions of µPD78078 are inherited
• Minimum instruction execution time: 160 ns (at 12.5 MHz main system clock operation)
61 µs (at 32.768 kHz subsystem clock operation)
• On-chip memory
• ROM
Mask ROM
: 96 KB (µPD784214A)
128 KB (µPD784215A, 784216A)
Flash memory : 128 KB (µPD78F4216A)
• RAM
: 3,584 bytes (µPD784214A)
: 5,120 bytes (µPD784215A)
4,352 bytes (µPD784216A, 78F4216A)
• I/O port : 86
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 6 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
CSI (3-wire serial I/O): 1 channel
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Clock output function
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function
Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• Standby function
HALT/STOP/IDLE mode
Low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784214A, 784215A, 784216A)
VDD = 1.9 to 5.5 V (µPD78F4216A)
1.6.2 Applications
Cellular phones, PHS, cordless phones, CD-ROMs, audiovisual equipment, etc.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.6.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784214AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
µPD784214AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784215AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Mask ROM
Mask ROM
µPD784215AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784216AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Mask ROM
Mask ROM
µPD784216AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD78F4216AGC-8EU
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Flash memory
µPD78F4216AGF-3BA
100-pin plastic QFP (14 × 20 mm)
Flash memory
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
Standard
µPD784214AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
µPD784214AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784215AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Standard
Standard
µPD784215AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784216AGC-×××-8EU 100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Standard
Standard
µPD784216AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
Standard
Standard
µPD78F4216AGC-8EU
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
µPD78F4216AGF-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
43
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.6.4 Outline of functions
(1/2)
Product Name
µPD784214A
113
µPD784215A
µPD784216A
µPD78F4216A
Item
Number of basic instructions (mnemonics)
General-purpose registers
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction
execution time
When main system
clock is selected
160 n/320 ns/640 ns/1,280 ns/2,560 ns (at 12.5 MHz operation)
When subsystem
clock is selected
61 µs (at 32.768 kHz operation)
On-chip memory capacity
96 KB
128 KB
128 KB
ROM
RAM
(Mask ROM)
(Mask ROM)
(Flash memory)
3,584 bytes
5,120 bytes
8,192 bytes
Memory space
I/O ports
1 MB total both programs and data
Total
86
2
CMOS input
CMOS I/O
72
6
N-ch open-drain
I/O
Pins with
additional
Pins with pull-up
resistors
70
Note
functions
LED direct drive output 22
Medium voltage
resistance pins
6
Real-time output port
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter:
(16 bits)
Timer register × 1
Capture/compare register × 2 • PWM/PPG output
Pulse output capability
• Square wave output
• One-shot pulse output
Timer/counter 1:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 2:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 5:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 6:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 7:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 8:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Note The pins with additional functions are included in the I/O pins.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784214A
µPD784215A
µPD784216A
µPD78F4216A
Item
A/D converter
D/A converter
Serial interfaces
8-bit resolution × 8 channels
8-bit resolution × 2 channels
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
2
3
4
5
6
7
Clock output
Buzzer output
Watch timer
Watchdog timer
Interrupts
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Hardware sources 29 (internal: 20, external: 9)
Software sources
Non-maskable
Maskable
BRK instruction, BRKCS instructions, operand error
Internal: 1, external: 1
Internal: 19, external: 8
• 4-level programmable priority
• 3 processing modes: vectored interrupt, macro service, context switching
Standby functions
• HALT/STOP/IDLE mode
• Low power consumption mode (CPU can operate on subsystem clock):
HALT/IDLE mode
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.6.5 Block diagram
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP6
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
TIMER/COUNTER
(16 BITS)
SI0
SO0
SCK0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
AD0 to AD7
A0 to A7
TIMER/COUNTER2
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER5
BUS I/F
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
(8 BITS)
RD
WR
WAIT
ASTB
TIMER/COUNTER6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT12
PORT13
P00 to P06
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127
P130,P131
TIMER/COUNTER 7
(8 BITS)
TIMER/COUNTER 8
(8 BITS)
WATCH TIMER
RAM
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVREF0
AVDD
AVSS
RESET
X1
SYSTEM CONTROL
CLOCK OUTPUT
CONTROL
X2
PCL
BUZ
XT1
XT2
BUZZER
OUTPUT
V
V
DD
SS
Note
TEST/VPP
Note VPP applies to the µPD78F4216A only.
Remark Internal ROM and RAM capacities vary depending on the products.
46
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.7 Product Outline of µPD784216AY Subseries
(µPD784214AY, 784215AY, 784216AY, 78F4216AY)
1.7.1 Features
• I2C bus interface is added to µPD784216A Subseries
• Minimum instruction execution time: 160 ns (main system clock: at 12.5 MHz operation)
61 µs (subsystem clock: at 32.768 kHz operation)
• On-chip memory
• ROM
Mask ROM
: 96 KB (µPD784214AY)
128 KB (µPD784215AY, 784216AY)
: 128 KB (µPD78F4216AY)
Flash Memory
• RAM
: 3,584 bytes (µPD784214AY)
5,120 bytes (µPD784215AY)
8,192 bytes (µPD784216AY, 78F4216AY)
• I/O port: 86
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 6 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
CSI (3-wire serial I/O, multimaster supported I2C bus): 1 channel
• Interrupt controller (4-level priority)
Vectored interrupt/macro service/context switching
• Clock output functions
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output functions
Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• Standby function
HALT/STOP/IDLE mode
Low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784214AY, 784215AY, 784216AY)
VDD = 1.9 to 5.5 V (µPD78F4216AY)
1.7.2 Applications
Cellular phones, PHS, cordless phones, CD-ROMs, audiovisual equipment, etc.
47
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.7.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784214AYGC-×××-8EU
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
µPD784214AYGF-×××-3BA
µPD784215AYGC-×××-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Mask ROM
Mask ROM
µPD784215AYGF-×××-3BA
µPD784216AYGC-×××-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Mask ROM
Mask ROM
µPD784216AYGF-×××-3BA
µPD78F4216AYGC-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Mask ROM
Flash memory
µPD78F4216AYGF-3BA
100-pin plastic QFP (14 × 20 mm)
Flash memory
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
Standard
µPD784214AYGC-×××-8EU
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
µPD784214AYGF-×××-3BA
µPD784215AYGC-×××-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Standard
Standard
µPD784215AYGF-×××-3BA
µPD784216AYGC-×××-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Standard
Standard
µPD784216AYGF-×××-3BA
µPD78F4216AYGC-8EU
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch)
(14 × 14 mm)
Standard
Standard
µPD78F4216AYGF-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
48
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.7.4 Outline of functions
(1/2)
Product Name
µPD784214AY
µPD784215AY
µPD784216AY
µPD78F4216AY
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction
execution time
When main system 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (12.5 MHz operation)
clock is selected
When subsystem
clock is selected
61 µs (32.768 kHz)
On-chip memory capacity ROM
96 KB
128 KB
128 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
RAM
3,584 bytes
5,120 bytes
8,192 bytes
Memory space
1 MB total both programs and data
I/O ports
Total
86
2
CMOS input
CMOS I/O
72
6
N-ch open-drain
I/O
Pins with
additional
Pins with pull-up
resistors
70
Note
functions
LED direct drive output 22
Medium voltage
resistance pins
6
Real-time output port
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter:
(16 bits)
Timer register × 1
Capture/compare register × 2 • PWM/PPG output
Pulse output capability
• Square wave output
• One-shot pulse output
Timer/counter 1:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 2:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 5:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 6:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 7:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
Timer/counter 8:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
• Square wave output
A/D converter
D/A converter
8-bit resolution × 8 channels
8-bit resolution × 2 channels
Note The pins with additional functions are included in the I/O pins.
49
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784214AY
µPD784215AY
µPD784216AY
µPD78F4216AY
Item
Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
2
• CSI (3-wire serial I/O, multimaster supported I C bus): 1 channel
2
3
4
5
6
7
Clock output
Buzzer output
Watch timer
Watchdog timer
Interrupts
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Hardware sources 29 (internal: 20, external: 9)
Software sources
Non-maskable
Maskable
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 19, external: 8
• 4-level programmable priority
• 3 processing modes: vectored interrupt, macro service, context switching
Standby functions
•
•
HALT/STOP/IDLE mode
Low power consumption mode (CPU can operate on subsystem clock):
HALT/IDLE mode
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
50
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.7.5 Block diagram
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP6
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
TIMER/COUNTER
(16 BITS)
SI0/SDA0
SO0
SCK0/SCL0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
AD0 to AD7
A0 to A7
TIMER/COUNTER2
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER5
BUS I/F
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
(8 BITS)
RD
WR
WAIT
ASTB
TIMER/COUNTER6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT12
PORT13
P00 to P06
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127
P130,P131
TIMER/COUNTER 7
(8 BITS)
TIMER/COUNTER 8
(8 BITS)
WATCH TIMER
RAM
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVREF0
AVDD
AVSS
RESET
X1
SYSTEM CONTROL
CLOCK OUTPUT
CONTROL
X2
PCL
BUZ
XT1
XT2
BUZZER
OUTPUT
V
V
DD
SS
Note
TEST/VPP
Note VPP applies to the µPD78F4216AY only.
Remark Internal ROM and RAM capacities vary depending on the products.
51
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.8 Product Outline of µPD784218A Subseries
(µPD784217A, 784218A, 78F4218A)
1.8.1 Features
• Internal ROM correction
• Inherits the peripheral functions of the µPD78078 Subseries
• Minimum instruction execution time
• 160 ns (main system clock: fXX = 12.5 MHz operation)
• 61 µs (subsystem clock: fXT = 32.768 kHz operation)
• Instruction set suited for control applications
• Interrupt controller (4-level priority)
• Vectored interrupt servicing/macro service/context switching
• Standby function
• HALT/STOP/IDLE mode
• In the low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• On-chip memory: Mask ROM
256 KB (µPD784218A)
192 KB (µPD784217A)
Flash memory 256 KB (µPD78F4218A)
RAM 12,800 bytes
• I/O pins: 86
• Software programmable pull-up resistors: 70 inputs
• LED direct drive possible: 22 outputs
• Transistor direct drive possible: 6 outputs
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 6 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently
controlled.)
• Clock frequency dividing function
• Clock output function: Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function: Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• External access status function
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784217A, 784218A)
VDD = 1.9 to 5.5 V (µPD78F4218A)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.8.2 Applications
Cellular phones, PHS, cordless phones, CD-ROM, audiovisual equipment, etc.
1.8.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784217AGC-×××-7EA
µPD784217AGF-×××-3BA
µPD784218AGC-×××-7EA
µPD784218AGF-×××-3BA
µPD78F4218AGC-7EA
µPD78F4218AGF-3BA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
Mask ROM
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Flash memory
Flash memory
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
µPD784217AGC-×××-7EA
µPD784217AGF-×××-3BA
µPD784218AGC-×××-7EA
µPD784218AGF-×××-3BA
µPD78F4218AGC-7EA
µPD78F4218AGF-3BA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
User’s Manual U10905EJ8V1UM
53
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.8.4 Outline of functions
(1/2)
Product Name
µPD784217A
µPD784218A
µPD78F4218A
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns
(main system clock: at 12.5 MHz operation)
• 61 µs (subsystem clock: at 32.768 kHz operation)
On-chip memory
capacity
ROM
RAM
192 KB
256 KB
256 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
12,800 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
86
8
CMOS inputs
CMOS I/O
72
6
N-ch open-drain I/O
Pins with additional Pins with pull-up
70
Note
functions
resistors
LED direct drive output 22
Medium voltage pins
6
Real-time output ports
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter:
(16 bits)
Timer register × 1
Pulse output possible
Capture/compare register × 2 • PWM/PPG output
• Square wave output
• One-shot pulse output
Timer/counter 1: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 2: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 5: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
`
• Square wave output
Timer/counter 6: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 7: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 8: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Note The pins with additional functions are included in the I/O pins.
54
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784217A
µPD784218A
µPD78F4218A
Item
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
A/D converter
D/A converter
Clock output
8-bit resolution × 8 channels
8-bit resolution × 2 channels
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Buzzer output
Watch timer
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Watchdog timer
Standby functions
• HALT/STOP/IDLE mode
• In the low power consumption mode
(CPU operation by subsystem clock): HALT/IDLE mode
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
29 (internal: 20, external: 9)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 19, external: 8
• 4-level programmable priority
•
Three processing formats: Vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
User’s Manual U10905EJ8V1UM
55
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.8.5 Block diagram
RxD1/SI1
TxD1/SO1
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP6
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
TIMER/COUNTER
(16 BITS)
SI0
SO0
SCK0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
AD0 to AD7
A0 to A7
TIMER/COUNTER2
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER5
BUS I/F
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
(8 BITS)
RD
WR
WAIT
ASTB
TIMER/COUNTER6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT12
PORT13
P00 to P06
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127
P130,P131
TIMER/COUNTER 7
(8 BITS)
TIMER/COUNTER 8
(8 BITS)
WATCH TIMER
RAM
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVREF0
AVDD
AVSS
RESET
X1
SYSTEM CONTROL
CLOCK OUTPUT
CONTROL
X2
PCL
BUZ
XT1
XT2
BUZZER
OUTPUT
V
V
DD
SS
Note
TEST/VPP
Note The VPP pin applies to the µPD78F4218A only.
Remark Internal ROM capacity varies depending on the products.
56
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.9 Product Outline of µPD784218AY Subseries
(µPD784217AY, 784218AY, 78F4218AY)
1.9.1 Features
• Adds the I2C bus interface to the µPD784218A Subseries.
• Internal ROM correction
• Inherits the peripheral functions of the µPD78078Y Subseries
• Minimum instruction execution time
• 160 ns (main system clock: fXX = 12.5 MHz operation)
• 61 µs (subsystem clock: fXT = 32.768 kHz operation)
• Instruction set suited for control applications
• Interrupt controller (4-level priority)
• Vectored interrupt servicing/macro service/context switching
• Standby function
• HALT/STOP/IDLE mode
• In the low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• On-chip memory: Mask ROM
256 KB (µPD784218AY)
192 KB (µPD784217AY)
Flash memory 256 KB (µPD78F4218AY)
RAM 12,800 bytes
• I/O pins: 86
• Software programmable pull-up resistors: 70 inputs
• LED direct drive possible: 22 outputs
• Transistor direct drive possible: 6 outputs
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 6 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, multimaster supported I2C bus): 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently
controlled.)
• Clock frequency dividing function
• Clock output function: Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function: Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• External access status function
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784217AY, 784218AY)
VDD = 1.9 to 5.5 V (µPD78F4218AY)
User’s Manual U10905EJ8V1UM
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.9.2 Applications
Cellular phones, PHS, cordless phones, CD-ROM, audiovisual equipment, etc.
1.9.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784217AYGC-×××-7EA
µPD784217AYGF-×××-3BA
µPD784218AYGC-×××-7EA
µPD784218AYGF-×××-3BA
µPD78F4218AYGC-7EA
µPD78F4218AYGF-3BA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
Mask ROM
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Flash memory
Flash memory
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
µPD784217AYGC-×××-7EA
µPD784217AYGF-×××-3BA
µPD784218AYGC-×××-7EA
µPD784218AYGF-×××-3BA
µPD78F4218AYGC-7EA
µPD78F4218AYGF-3BA
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
58
User’s Manual U10905EJ8V1UM
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.9.4 Outline of functions
(1/2)
Product Name
µPD784217AY
µPD784218AY
µPD78F4218AY
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns
(main system clock: at 12.5 MHz operation)
• 61 µs (subsystem clock: at 32.768 kHz operation)
On-chip memory
capacity
ROM
RAM
192 KB
250 KB
256 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
12,800 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
86
8
CMOS inputs
CMOS I/O
72
6
N-ch open-drain I/O
Pins with additional Pins with pull-up
70
Note
functions
resistors
LED direct drive output 22
Medium voltage pins
6
Real-time output ports
Timer/counters
4 bits × 2, or 8 bits × 1
Timer/counter:
(16 bits)
Timer register × 1
Pulse output possible
Capture/compare register × 2 • PWM/PPG output
• Square wave output
• One-shot pulse output
Timer/counter 1: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 2: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 5: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
`
• Square wave output
Timer/counter 6: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 7: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 8: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Note The pins with additional functions are included in the I/O pins.
User’s Manual U10905EJ8V1UM
59
CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784217AY
µPD784218AY
µPD78F4218AY
Item
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
2
• CSI (3-wire serial I/O, multimaster supported I C bus): 1 channel
A/D converter
D/A converter
Clock output
8-bit resolution × 8 channels
8-bit resolution × 2 channels
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Buzzer output
Watch timer
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Watchdog timer
Standby functions
• HALT/STOP/IDLE mode
• In the low power consumption mode
(CPU operation by subsystem clock): HALT/IDLE mode
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
29 (internal: 20, external: 9)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 19, external: 8
• 4-level programmable priority
•
Three processing formats: Vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 100-pin plastic QFP (fine pitch) (14 × 14 mm)
• 100-pin plastic QFP (14 × 20 mm)
60
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.9.5 Block diagram
RxD1/SI1
TxD1/SO1
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP6
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
TIMER/COUNTER
(16 BITS)
SI0/SDA0
SO0
SCK0/SCL0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
AD0 to AD7
A0 to A7
TIMER/COUNTER2
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER5
BUS I/F
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
(8 BITS)
RD
WR
WAIT
ASTB
TIMER/COUNTER6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT12
PORT13
P00 to P06
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127
P130,P131
TIMER/COUNTER 7
(8 BITS)
TIMER/COUNTER 8
(8 BITS)
WATCH TIMER
RAM
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVREF0
AVDD
AVSS
RESET
X1
SYSTEM CONTROL
CLOCK OUTPUT
CONTROL
X2
PCL
BUZ
XT1
XT2
BUZZER
OUTPUT
V
V
DD
SS
Note
TEST/VPP
Note The VPP pin applies to the µPD78F4218AY only.
Remark Internal ROM capacity varies depending on the products.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.10 Product Outline of µPD784225 Subseries
(µPD784224, 784225, 78F4225)
1.10.1 Features
• Inherits the peripheral functions of the µPD780058 Subseries
• Minimum instruction execution time
• 160 ns (main system clock: fXX = 12.5 MHz operation)
• 61 µs (subsystem clock: fXT = 32.768 kHz operation)
• Instruction set suited for control applications
• Interrupt controller (4-level priority)
• Vectored interrupt servicing/macro service/context switching
• Standby function
• HALT/STOP/IDLE mode
• In the low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• On-chip memory: Mask ROM
128 KB (µPD784225)
96 KB (µPD784224)
Flash memory 128 KB (µPD78F4225)
RAM 4,352 bytes (µPD784225, 78F4225)
3,584 bytes (µPD784224)
• I/O pins: 67
• Software programmable pull-up resistors: 50 inputs
• LED direct drive possible: 16 outputs
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 4 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently
controlled.)
• Clock frequency division function
• Clock output function: Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function: Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784224, 784225)
VDD = 1.9 to 5.5 V (µPD78F4225)
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1.10.2 Applications
Car audio, portable audio, air conditioner, telephone, etc.
1.10.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784224GC-×××-8BT
µPD784224GK-×××-BE9
µPD784225GC-×××-8BT
µPD784225GK-×××-BE9
µPD78F4225GC-8BT
µPD78F4225GK-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
µPD784224GC-×××-8BT
µPD784224GK-×××-BE9
µPD784225GC-×××-8BT
µPD784225GK-×××-BE9
µPD78F4225GC-8BT
µPD78F4225GK-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.10.4 Outline of functions
(1/2)
Product Name
µPD784224
µPD784225
µPD78F4225
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns
(main system clock: at 12.5 MHz operation)
• 61 µs (subsystem clock: at 32.768 kHz operation)
On-chip memory
capacity
ROM
RAM
96 KB
128 KB
128 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
3,584 bytes
4,352 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
67
8
CMOS inputs
CMOS I/O
59
57
Pins with additional Pins with pull-up
Note
functions
resistors
LED direct drive outputs 16
4 bits × 2, or 8 bits × 1
Real-time output ports
Timer/counters
Timer/counter:
(16 bits)
Timer register × 1
Capture/compare register × 2 • PWM/PPG output
• Square wave output
Pulse output possible
• One-shot pulse output
Timer/counter 1: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 2: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 5: Timer register × 1
(8 bits) Compare register × 1
`
Timer/counter 6: Timer register × 1
(8 bits) Compare register × 1
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
A/D converter
D/A converter
Clock output
Buzzer output
Watch timer
8-bit resolution × 8 channels
8-bit resolution × 2 channels
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Watchdog timer
Note The pins with additional functions are included in the I/O pins.
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(2/2)
Product Name
µPD784224
µPD784225
µPD78F4225
Item
Standby functions
• HALT/STOP/IDLE mode
• In the low power consumption mode
(CPU operation by subsystem clock): HALT/IDLE mode
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
25 (internal: 18, external: 7)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 17, external: 6
• 4-level programmable priority
•
Three processing formats: Vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
• 80-pin plastic QFP (14 × 14 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.10.5 Block diagram
RxD1/SI1
TxD1/SO1
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP5
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
TIMER/COUNTER
(16 BITS)
SI0
SO0
SCK0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
TIMER/COUNTER2
A0 to A7
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER 5
BUS I/F
RD
WR
(8 BITS)
WAIT
ASTB
EXA
TIMER/COUNTER 6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT12
PORT13
P00 to P05
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P120 to P127
P130,P131
WATCH TIMER
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
RAM
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVDD
AVSS
RESET
X1
CLOCK OUTPUT
CONTROL
PCL
BUZ
SYSTEM CONTROL
X2
XT1
XT2
BUZZER
OUTPUT
V
V
DD0, VDD1
SS0, VSS1
Note
TEST/VPP
Note The VPP pin applies to the µPD78F4225 only.
Remark Internal ROM and RAM capacities vary depending on the products.
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1.11 Product Outline of µPD784225Y Subseries
(µPD784224Y, 784225Y, 78F4225Y)
1.11.1 Features
• Adds the I2C bus interface to the µPD784225 Subseries.
• Inherits the peripheral functions of the µPD780058Y Subseries
• Minimum instruction execution time
• 160 ns (main system clock: fXX = 12.5 MHz operation)
• 61 µs (subsystem clock: fXT = 32.768 kHz operation)
• Instruction set suited for control applications
• Interrupt controller (4-level priority)
• Vectored interrupt servicing/macro service/context switching
• Standby function
• HALT/STOP/IDLE mode
• In the low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• On-chip memory: Mask ROM
128 KB (µPD784225Y)
96 KB (µPD784224Y)
Flash memory 128 KB (µPD78F4225Y)
RAM 4,352 bytes (µPD784225Y, 78F4225Y)
3,584 bytes (µPD784224Y)
• I/O pins: 67
• Software programmable pull-up resistors: 50 inputs
• LED direct drive possible: 16 outputs
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit timer/counter × 4 units
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, multimaster supported I2C bus): 1 channel
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
• Real-time output port (by combining with the timer/counter, two stepping motors can be independently
controlled.)
• Clock frequency dividing function
• Clock output function: Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
• Buzzer output function: Selectable from fXX/210, fXX/211, fXX/212, fXX/213
• External access status function
• Power supply voltage: VDD = 1.8 to 5.5 V (µPD784224Y, 784225Y)
VDD = 1.9 to 5.5 V (µPD78F4225Y)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.11.2 Applications
Car audios, portable audios, air conditioners, telephones, etc.
1.11.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784224YGC-×××-8BT
µPD784224YGK-×××-BE9
µPD784225YGC-×××-8BT
µPD784225YGK-×××-BE9
µPD78F4225YGC-8BT
µPD78F4225YGK-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
Mask ROM
Mask ROM
Mask ROM
Flash memory
Flash memory
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
Standard
Standard
Standard
Standard
Standard
µPD784224YGC-×××-8BT
µPD784224YGK-×××-BE9
µPD784225YGC-×××-8BT
µPD784225YGK-×××-BE9
µPD78F4225YGC-8BT
µPD78F4225YGK-BE9
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
Caution The µPD784225Y Subseries is under development.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.11.4 Outline of functions
(1/2)
Product Name
µPD784224Y
µPD784225Y
µPD78F4225Y
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns
(main system clock: at 12.5 MHz operation)
• 61 µs (subsystem clock: at 32.768 kHz operation)
On-chip memory
capacity
ROM
RAM
96 KB
128 KB
128 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
3,584 bytes
4,352 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
67
8
CMOS inputs
CMOS I/O
59
57
Pins with additional Pins with pull-up
Note
functions
resistors
LED direct drive output 16
4 bits × 2, or 8 bits × 1
Real-time output ports
Timer/counters
Timer/counter:
(16 bits)
Timer register × 1
Capture/compare register × 2 • PWM/PPG output
• Square wave output
Pulse output possible
• One-shot pulse output
Timer/counter 1: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 2: Timer register × 1
(8 bits) Compare register × 1
Pulse output possible
• PWM output
• Square wave output
Timer/counter 5: Timer register × 1
(8 bits) Compare register × 1
`
Timer/counter 6: Timer register × 1
(8 bits) Compare register × 1
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
2
• CSI (3-wire serial I/O, multimaster supported I C bus): 1 channel
A/D converter
D/A converter
Clock output
Buzzer output
Watch timer
8-bit resolution × 8 channels
8-bit resolution × 2 channels
2
3
4
5
6
7
Selectable from fXX, fXX/2, fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXX/2 , fXT
10
11
12
13
Selectable from fXX/2 , fXX/2 , fXX/2 , fXX/2
1 channel
1 channel
Watchdog timer
Note The pins with additional functions are included in the I/O pins.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784224Y
µPD784225Y
µPD78F4225Y
Item
Standby functions
• HALT/STOP/IDLE mode
• In the low power consumption mode
(CPU operation by subsystem clock): HALT/IDLE mode
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
25 (internal: 18, external: 7)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 17, external: 6
• 4-level programmable priority
•
Three processing formats: Vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 1.8 to 5.5 V
VDD = 1.9 to 5.5 V
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
• 80-pin plastic QFP (14 × 14 mm)
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1.11.5 Block diagram
RxD1/SI1
TxD1/SO1
INTP2/NMI
UART/IOE1
BAUD-RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
INTP0,INTP1,
INTP3 to INTP5
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
UART/IOE2
BAUD-RATE
GENERATOR
TI00
TI01
TO0
TIMER/COUNTER
(16 BITS)
SI0/SDA0
SO0
SCK0/SCL0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
TI1
TO1
(8 BITS)
TIMER/COUNTER2
A0 to A7
TI2
TO2
(8 BITS)
A8 to A15
A16 to A19
TIMER/COUNTER 5
BUS I/F
RD
WR
(8 BITS)
WAIT
ASTB
EXA
TIMER/COUNTER 6
78K/IV
CPU CORE
(8 BITS)
ROM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT12
PORT13
P00 to P05
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P120 to P127
P130,P131
WATCH TIMER
WATCHDOG TIMER
REAL-TIME
OUTPUT PORT
RTP0 to RTP7
RAM
ANO0
ANO1
AVREF1
AVSS
D/A
CONVERTER
ANI0 to ANI7
A/D
CONVERTER
AVDD
AVSS
RESET
X1
CLOCK OUTPUT
CONTROL
PCL
BUZ
SYSTEM CONTROL
X2
XT1
XT2
BUZZER
OUTPUT
V
V
DD0, VDD1
SS0, VSS1
Note
TEST/VPP
Note The VPP pin applies to the µPD78F4225Y only.
Remark Internal ROM and RAM capacities vary depending on the products.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.12 Product Outline of µPD784908 Subseries
(µPD784907, 784908, 78P4908)
1.12.1 Features
• Minimum instruction execution time: 160 ns (at 12.58 MHz operation)
• On-chip memory
• Mask ROM : 96 KB (µPD784907)
128 KB (µPD784908)
PROM
• RAM
: 128 KB (µPD78P4908)
: 3,584 bytes (µPD784907)
4,352 bytes (µPD784908, 78P4908)
• I/O port: 80
• Timer/counter: 16-bit timer/counter × 3 units
16-bit timer × 1 unit
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Serial interfaces: 4 channels
• UART/IOE (3-wire serial I/O): 2 channels
• CSI (3-wire serial I/O): 2 channels
• Standby function
• HALT/STOP/IDLE mode
• Clock frequency dividing function
• Clock output function: Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16
• A/D converter: 8-bit resolution × 8 channels
• Internal IEBus controller
• Low power consumption
• Power supply voltage: VDD = 3.5 to 5.5 V (Mask ROM version)
VDD = 4.0 to 5.5 V (PROM version)
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1.12.2 Applications
Car audios, etc.
1.12.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784907GF-×××-3BA
µPD784908GF-×××-3BA
µPD78P4908GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
One-time PROM
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
µPD784907GF-×××-3BA
µPD784908GF-×××-3BA
µPD78P4908GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.12.4 Outline of functions
(1/2)
Product Name
µPD784907
µPD784908
µPD78P4908
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
160 ns/320 ns/636 ns/1.27 µs (at 12.58kHz operation)
Minimum instruction execution time
On-chip memory
capacity
ROM
96 KB
128 KB
128 KB
(Mask ROM)
(Mask ROM)
(PROM)
RAM
3,584 bytes
4,352 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
Inputs
I/O
80
8
72
24
Pins with additional LED direct drive
Note
functions
outputs
Transistor direct drive
N-ch open-drain
8
4
Real-time output ports
IEBus controller
4 bits × 2, or 8 bits × 1
Internal (simplify)
Timer/counters
Timer/counter 0: Timer register × 1
Pulse output capability
• Toggle output
(16 bits)
Capture register × 1
Compare register × 2
• PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register × 1
Real-time output port
(16 bits)
Capture register × 1
Capture/compare register × 1
Compare register × 1
Timer/counter 2: Timer register × 1
Capture register × 1
Pulse output capability
• Toggle output
Capture/compare register × 1 • PWM/PPG output
Compare register × 1
Timer 3:
Timer register × 1
Compare register × 1
Watch timer
Interrupt occurs at an interval of 0.5 sec. (Has an internal clock oscillator.)
The input clock can be selected from among the main clock
(12.58 MHz) or clock (32.7 kHz).
Clock output
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16, (also usable as output port)
PWM output
12-bit resolution × 2 channels
Serial interfaces
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 2 channels
A/D converter
8-bit resolution × 8 channels
1 channel
Watchdog timer
Standby function
HALT/STOP/IDLE mode
Note The pins with additional functions are included in the I/O pins.
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(2/2)
Product Name
µPD784907
µPD784908
µPD78F4908
Item
Interrupts
Hardware sources
Software sources
Non-maskable
Maskable
27 (internal: 20, external: 7 (sampling clock variable input: 1))
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 19, external: 6
• 4-level programmable priority
• Three processing formats: Vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 3.5 to 5.5 V
VDD = 4.0 to 5.5 V
100-pin plastic QFP (14 × 20 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.12.5 Block diagram
RxD/SI1
NMI
UART/IOE2
BAUD-RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
TxD/SO1
ASCK/SCK1
INTP0 to INTP5
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
INTP3
TO0
TO1
UART/IOE1
BAUD-RATE
GENERATOR
TIMER/COUNTER0
(16 BITS)
SCK0
SO0
SI0
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER1
INTP0
(16 BITS)
INTP1
SCK3
SO3
SI3
CLOCKED
SERIAL
INTERFACE3
TIMER/COUNTER2
INTP2/CI
(8 BITS)
TO2
TO3
78K/IV
CPU CORE
ROM
CLOCK OUTPUT
TIMER 3
(16 BITS)
ASTB/CLKOUT
AD0 to AD7
A8 to A15
P00 to P03
P04 to P07
REAL-TIME
OUTPUT PORT
A16 to A19
BUS I/F
RD
WR
PWM0
PWM1
RAM
WAIT/HLDRQ
REFRQ/HLDAK
PWM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT9
PORT10
ANI0 to ANI7
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P90 to P97
P100 to P107
AVDD
AVREF1
AVSS
A/D
CONVERTER
INTP5
TX
IEBUS
CONTROLLER
RX
RESET
TEST
X1
X2
REGC
SYSTEM
CONTROL
(REGULATOR)
WATCHDOG
TIMER
REGOFF
V
V
DD
SS
XT1
XT2
WATCH TIMER
Remark Internal ROM and RAM capacities vary depending on the products.
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1.13 Product Outline of µPD784915 Subseries
(µPD784915B, 784916B, 78P4916)
1.13.1 Features
• 78K/IV Series (16-bit CPU core employed): Minimum instruction execution time: 250 ns (at 8 MHz internal clock)
• Internal timer unit for VCR servo control (super timer unit)
• Internal analog circuit for VHS type VCR
• CTL amplifier
• RECCTL driver (supports rewriting)
• DPFG separation circuit (ternary separation circuit)
• DFG amplifier, DPG comparator, CFG amplifier
• Reel FG comparator (2 channels), CSYNC comparator
• I/O port: 54
• Serial interface: 2 channels (3-wire serial I/O)
• A/D converter: 12 channels (conversion time: 10 µs)
• PWM output: 16-bit resolution × 3 channels, 8-bit resolution × 3 channels
• Interrupt function
• Vectored interrupt function
• Macro service function
• Context switching function
• Low-frequency oscillation mode supported: Main system clock frequency = internal clock frequency
• Low-power consumption mode: CPU can operate on subsystem clock.
• Hardware watch function: Watch operation on low voltage (VDD = 2.7 V (MIN.)) and with low current consumption
• Package for high-density mounting: 100-pin plastic QFP (0.65 mm pitch, 14 × 20 mm)
1.13.2 Applications
For controlling system/servo/timer of VCR (stationary type and camcorder type)
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1.13.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
Mask ROM
µPD784915BGF-×××-3BA
µPD784916BGF-×××-3BA
µPD78P4916GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
One-time PROM
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
Standard
µPD784915BGF-×××-3BA
µPD784916BGF-×××-3BA
µPD78P4916GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
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1.13.4 Outline of functions
Product Name
µPD784915B
µPD784916B
µPD78P4916
Item
Number of instructions
113
250 ns (8 MHz internal clock operation)
Minimum instruction execution time
On-chip memory capacity
48 KB
62 KB
62 KB
(One-time
PROM)
ROM
RAM
(Mask ROM)
(Mask ROM)
1,280 bytes
2,048 bytes
Interrupts
4 levels (programmable), vector interrupt, macro service, context
switching
External source
Internal source
9 (including NMI)
19
25
Number of interrupts that can use macro
service
Types of macro services
4 types, 10 macro services
Input: 8, I/O: 46
I/O port
Time base counter
•
•
22-bit FRC
Resolution: 125 ns, Maximum count time: 524 ms
Capture registers
Input signal Number of bits
Measurement cycle Operating edge
CFG
DFG
HSW
VSYNC
CTL
22
22
16
22
16
22
22
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
TREEL
SREEL
General-purpose timer
16-bit timer × 3
PBCTL duty identification
•
•
Duty of playback control signal
VISS detection, wide aspect detection
Linear time counter
Real-time output port
Serial interface
A/D converter
5-bit UDC for counting CTL signal
11
Clocked (3-wire): 2 channels
8-bit resolution × 12 channels, conversion time: 10 µs
PWM output
•
•
16-bit resolution × 3 channels, 8-bit resolution × 3 channels
Carrier frequency: 62.5 kHz
Watch function
Standby function
Analog circuits
0.5-sec measurement, low-voltage operation
HALT mode/STOP mode
•
•
•
•
•
•
CTL amplifier
RECCTL driver (supports rewriting)
DPFG separation circuit (ternary separation circuit)
DFG amplifier, DPG comparator, CFG amplifier
Reel FG comparator
CSYNC comparator
Power supply voltage
Package
VDD = 2.7 to 5.5 V
100-pin plastic QFP (14 × 20 mm)
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1.13.5 Block diagram
NMI
V
V
DD
INTERRUPT
CONTROL
SS
INTP0 to INTP3
X1
X2
XT1
XT2
RESET
PWM0 to PWM5
SYSTEM
CONTROL
SUPER TIMER
UNIT
PTO00 to PTO02
PTO10, PTO11
(D0 to D7)
(A0 to A16)
(CE)
(OE)
(PGM)
VREFC
REEEL0IN
REEEL1IN
CSYNCIN
DFGIN
(VPP
)
CLO
BUZ
CLOCK OUTPUT
BUZZER OUTPUT
DPGIN
CFGIN
CFGAMPO
CFGCPIN
CTLOUT1
CTLOUT2
CTLIN
78K/IV
16-bit CPU CORE
KEY INPUT
KEY0 to KEY4
RECCTL+
RECCTL–
CTLDLY
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
P00 to P07
ANALOG UNIT
&
REAL- TIME
OUTPUT PORT
A/D CONVERTER
P80, P82, P83
P00 to P07
ANI0 to ANI11
PORT0
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
RAM
ROM
SI1
SO1
SERIAL
INTERFACE 1
P40 to P47
P50 to P57
SCK1
SI2/BUSY
SO2
SERIAL
INTERFACE 2
P60 to P67
SCK2
STRB
P70 to P77
P80, P82 to P87
P90 to P96
Remarks 1. Internal ROM and RAM capacities vary depending on the products.
2. VPP applies to the µPD78P4916 only.
3. The pins in parentheses are used in the PROM programming mode.
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1.14 Product Outline of µPD784928 Subseries
(µPD784927, 784928, 78F4928)
1.14.1 Features
• 16-bit CPU core: Minimum instruction execution time: 250 ns (with 8 MHz internal clock)
• Internal timer unit (super timer unit) for VCR servo control
• I/O ports: 74
• Internal analog circuits for VHS type VCR
• CTL amplifier
• RECCTL driver (supporting rewrite)
• CFG amplifier
• DFG amplifier
• DPG amplifier
• DPFG separation circuit (ternary separation circuit)
• Reel FG comparator (2 channels)
• CSYNC comparator
• Serial interface: 2 channels
• 3-wire serial I/O: 2 channels
• A/D converter: 12 channels (conversion time: 10 µs)
• PWM output: 16-bit resolution × 3 channels, 8-bit resolution × 3 channels
• Interrupt function
• Vector interrupt function
• Macro service function
• Context switching function
• Low frequency oscillation mode: Main system clock frequency = internal clock frequency
• Low power consumption mode: CPU can operate on subsystem clock.
• Power supply voltage: VDD = 2.7 to 5.5 V
• Hardware watch function: Low-voltage (VDD = 2.7 V MIN.), low-current consumption operation
1.14.2 Applications
For stationary type and camcorder type VCRs.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.14.3 Ordering information
(1) Ordering information
Part Number
Package
Internal ROM
µPD784927GF-×××-3BA
µPD784928GF-×××-3BA
µPD78F4928GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
Mask ROM
Flash memory
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
µPD784927GF-×××-3BA
µPD784928GF-×××-3BA
µPD78F4928GF-3BA
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
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1.14.4 Outline of functions
Product Name
µPD784927
µPD784928
µPD78F4928
Item
Number of instructions
Minimum instruction execution time
On-chip memory capacity ROM
RAM
113
250 ns (internal clock: 8 MHz operation)
96 KB (Mask ROM)
2,048 bytes
128 KB (Mask ROM)
3,584 bytes
128 KB (Flash memory)
3,584 bytes
Interrupt sources
External 9 (including NMI)
Internal 22 (including software interrupt)
•
•
4 levels programmable priority
3 types of processing methods
Vectored interrupt, macro service, context switching
I/O ports
Input
I/O
20
54 (including LED direct drive ports: 8)
Time base counter
•
•
22-bit FRC
Resolution: 125 ns, maximum count time: 524 ms
Capture registers
Input signal
Number of bits
Measuring cycle
Operating edge
CFG
DFG
HSW
VSYNC
CTL
22
22
16
22
16
22
22
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
TREEL
SREEL
General-purpose timer
16-bit timer × 3
PBCTL duty identification
•
•
Identifies duty of recording control signal
VISS detection, wide aspect detection
Linear time counter
Real-time output port
Serial interface
5-bit UDC counts CTL signal
11
3-wire serial I/O: 2 channels (including BUSY/STRB control possible: 1 channel)
Buzzer output function
1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (internal: 8 MHz operation)
2.048 kHz, 4.096 kHz, 32.768 kHz (subsystem clock: 32.768 kHz operation)
A/D converter
PWM output
8-bit resolution × 12 channels, conversion time: 10 µs
•
•
16-bit resolution × 3 channels, 8-bit resolution × 3 channels
Carrier frequency: 62.5 kHz
Watch function
0.5-second measurement, low-voltage operation (VDD = 2.7 V) possible
Standby function
HALT mode/STOP mode/low power consumption mode/low power consumption
HALT mode
Analog circuits
•
•
•
•
CTL amplifier
•
•
DPG amplifier
RECCTL driver (rewriting supported)
CFG amplifier
DPFG separation circuit
(ternary separation circuit)
Reel FG comparator
CSYNC comparator
DFG amplifier
•
•
Power supply voltage
Package
VDD = +2.7 to 5.5 V
100-pin plastic QFP (14 × 20 mm)
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1.14.5 Block diagram
NMI
V
V
X1
DD
SS
INTERRUPT
CONTROL
INTP0 to INTP3
X2
XT1
XT2
SYSTEM
CONTROL
PWM0 to PWM5
PTO00 to PTO02
PTO10, PTO11
RESET
V
Note
PP
SUPER TIMER
UNIT
CLO
BUZ
CLOCK OUTPUT
BUZZER OUTPUT
VREFC
REEL0IN
REEL1IN
CSYNCIN
DFGIN
KEY INPUT
KEY0 to KEY4
DPGIN
CFGIN
CFGAMPO
CFGCPIN
CTLOUT1
CTLOUT2
CTLIN
P00 to P07
78K/IV
16-bit CPU CORE
(RAM: 512 bytes)
REAL- TIME
OUTPUT PORT
P80, P82, P83
RECCTL+
RECCTL–
CTLDLY
DFGMON
DPGMON
CFGMON
CTLMON
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
PORT0
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT11
P00 to P07
P20 to P23
P30 to P37
ANALOG UNIT
&
A/D CONVERTER
RAM
ROM
ANI0 to ANI11
P40 to P47
P50 to P57
P60 to P67
SI1
SO1
SERIAL
INTERFACE 1
SCK1
SI2/BUSY
SO2
P70 to P77
SERIAL
INTERFACE 2
SCK2
STRB
P80, P82 to P87
P90 to P96
P100 to P103
P110 to P113
Note The VPP pin applies to the µPD78F4928 only.
Remark Internal ROM and RAM capacities vary depending on the products.
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1.15 Product Outline of µPD784928Y Subseries
(µPD784927Y, 784928Y, 78F4928Y)
1.15.1 Features
• Add the I2C bus interface to the µPD784928 Subseries.
• 16-bit CPU core: Minimum instruction execution time: 250 ns (at 8 MHz internal clock)
• Internal timer unit (super timer unit) for VCR servo control
• I/O ports: 74
• Internal analog circuits for VHS type VCR
• CTL amplifier
• RECCTL driver (supporting rewrite)
• CFG amplifier
• DFG amplifier
• DPG amplifier
• DPFG separation circuit (ternary separation circuit)
• Reel FG comparator (2 channels)
• CSYNC comparator
• Serial interface: 2 channels
• 3-wire serial I/O: 2 channels
• I2C bus interface: 1 channel
• A/D converter: 12 channels (conversion time: 10 µs)
• PWM output: 16-bit resolution × 3 channels, 8-bit resolution × 3 channels
• Interrupt function
• Vector interrupt function
• Macro service function
• Context switching function
• Low frequency oscillation mode: main system clock frequency = internal clock frequency
• Low power consumption mode: CPU can operate on subsystem clock.
• Power supply voltage: VDD = 2.7 to 5.5 V
• Hardware watch function: Low-voltage (VDD = 2.7 V MIN.), low-current consumption operation
1.15.2 Applications
For stationary type and camcorder type VCRs.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.15.3 Ordering information
(1) Ordering information
Part Number
Package
Internal ROM
µPD784927YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784928YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
Mask ROM
Mask ROM
Flash memory
µPD78F4928YGF-3BA
100-pin plastic QFP (14 × 20 mm)
Remark ××× indicates ROM code suffix.
(2) Quality grade
Part Number
Package
Quality Grade
Standard
µPD784927YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD784928YGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
Standard
µPD78F4928YGF-3BA
100-pin plastic QFP (14 × 20 mm)
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
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1.15.4 Outline of functions
Product Name
µPD784927Y
µPD784928Y
µPD78F4928Y
Item
Number of instructions
Minimum instruction execution time
On-chip memory capacity ROM
RAM
113
250 ns (internal clock: 8 MHz operation)
96 KB (Mask ROM)
2,048 bytes
128 KB (Mask ROM)
3,584 bytes
128 KB (Flash memory)
Interrupt sources
External 9 (including NMI)
Internal 23 (including software interrupt)
•
•
4 levels programmable priority
3 types of processing methods
Vectored interrupt, macro service, context switching
I/O ports
Input
I/O
20
54 (including LED direct drive ports: 8)
Time base counter
•
•
22-bit FRC
Resolution: 125 ns, maximum count time: 524 ms
Capture registers
Input signal
Number of bits
Measuring cycle
Operating edge
CFG
DFG
HSW
VSYNC
CTL
22
22
16
22
16
22
22
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
TREEL
SREEL
General-purpose timer
16-bit timer × 3
PBCTL duty identification
•
•
Identifies duty of recording control signal
VISS detection, wide aspect detection
Linear time counter
Real-time output port
Serial interface
5-bit UDC counts CTL signal
11
•
•
3-wire serial I/O: 2 channels (including BUSY/STRB control possible: 1 channel)
2
I C bus interface (multimaster supported): 1 channel
Buzzer output function
1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (internal: 8 MHz operation)
2.048 kHz, 4.096 kHz, 32.768 kHz (subsystem clock: 32.768 kHz operation)
A/D converter
PWM output
8-bit resolution × 12 channels, conversion time: 10 µs
•
•
16-bit resolution × 3 channels, 8-bit resolution × 3 channels
Carrier frequency: 62.5 kHz
Watch function
0.5-second measurement, low-voltage operation (VDD = 2.7 V) possible
Standby function
HALT mode/STOP mode/low power consumption mode/low power consumption
HALT mode
Analog circuits
•
•
•
•
CTL amplifier
•
•
DPG amplifier
RECCTL driver (rewriting supported)
CFG amplifier
DPFG separation circuit
(ternary separation circuit)
Reel FG comparator
CSYNC comparator
DFG amplifier
•
•
Power supply voltage
Package
VDD = +2.7 to 5.5 V
100-pin plastic QFP (14 × 20 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.15.5 Block diagram
NMI
V
V
X1
DD
SS
INTERRUPT
CONTROL
INTP0 to INTP3
X2
XT1
XT2
SYSTEM
CONTROL
PWM0 to PWM5
RESET
V
Note 1
PP
SUPER TIMER
UNIT
PTO00 to PTO02
PTO10, PTO11
CLO
BUZ
CLOCK OUTPUT
BUZZER OUTPUT
VREFC
REEL0IN
REEL1IN
CSYNCIN
DFGIN
KEY INPUT
KEY0 to KEY4
DPGIN
CFGIN
CFGAMPO
CFGCPIN
CTLOUT1
CTLOUT2
CTLIN
78K/IV
16-bit CPU CORE
(RAM: 512 bytes)
P00 to P07
REAL- TIME
OUTPUT PORT
P80, P82, P83
RECCTL+
RECCTL–
CTLDLY
DFGMON
DPGMON
CFGMON
CTLMON
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
PORT0
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT11
P00 to P07
P20 to P23
P30 to P37
ANALOG UNIT
&
A/D CONVERTER
RAM
ROM
ANI0 to ANI11
P40 to P47
P50 to P57
P60 to P67
SI1
SO1
SERIAL
INTERFACE 1
SCK1
SI2/BUSY
SO2
P70 to P77
SERIAL
INTERFACE 2
SCK2
STRB
P80, P82 to P87
SDA
SCL
SERIAL Note 2
INTERFACE 3
P90 to P96
P100 to P103
P110 to P113
Notes 1. The VPP pin applies to the µPD78F4928Y only.
2. I2C bus interface supported.
Remark Internal ROM and RAM capacities vary depending on the products.
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1.16 Product Outline of µPD784938A Subseries
(µPD784935A, 784936A, 784937A, 784938A, 78F4938A)
1.16.1 Features
• Inherits the peripheral functions of the µPD784908 Subseries
• Minimum instruction execution time: 320 ns (at fXX = 6.29 MHz operation)
160 ns (at fXX = 12.5 MHz operation)
• On-chip memory
• Mask ROM
: 96 KB (µPD784935A)
128 KB (µPD784936A)
192 KB (µPD784937A)
256 KB (µPD784938A)
• Flash memory : 256 KB (µPD78F4938A)
• RAM
: 5,120 bytes (µPD784935A)
: 6,656 bytes (µPD784936A)
: 8,192 bytes (µPD784937A)
: 10,496 bytes (µPD784938A, 78F4938A)
• I/O port: 80
• Timer/counter: 16-bit timer/counter × 1 unit
16-bit timer/counter × 2 units
16-bit timer × 1 unit
• Serial interface: 4 channels
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 2 channels
• PWM output: 2 outputs
• Standby function
HALT/STOP/IDLE mode
• Clock frequency dividing function
• Clock output function: Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25
• External expansion function
• Internal ROM correction function
• A/D converter: 8-bit resolution × 8 channels
• Internal IEBus controller
• Watchdog timer: 1 channel
• Low power consumption
• Power supply voltage: VDD = 4.0 to 5.5 V (at 12.58 MHz operation)
VDD = 3.0 to 5.5 V (at 6.29 MHz operation)
1.16.2 Applications
Car audios, etc.
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1.16.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784935AGF-×××-3BA
µPD784936AGF-×××-3BA
µPD784937AGF-×××-3BA
µPD784938AGF-×××-3BA
µPD78F4938AGF-3BANote
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
Note Under development
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
µPD784935AGF-×××-3BA
µPD784936AGF-×××-3BA
µPD784937AGF-×××-3BA
µPD784938AGF-×××-3BA
µPD78F4938AGF-3BANote
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Standard
Standard
Standard
Standard
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Note
Under development
Remark ××× indicates ROM code suffix.
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1.16.4 Outline of functions
(1/2)
Product Name µPD784935A µPD784936A
µPD784937A µPD784938A µPD78F4938A
Item
Number of basic instructions (mnemonics) 113
General-purpose registers
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time
• 320 ns/636 ns/1.27 µs/2.54 µs (at 6.29 kHz operation)
• 160 ns/320 ns/636 ns/1.27 µs (at 12.58 kHz operation)
On-chip memory
capacity
ROM
RAM
92 KB
128 KB
192 KB
256 KB
256 KB
(Mask ROM)
(Mask ROM)
(Mask ROM)
(Mask ROM)
(Flash memory)
5,120 bytes
6,656 bytes
8,192 bytes
10,496 bytes
Memory space
I/O ports
1 MB in total of program and data
Total
Inputs
I/O
80
8
72
24
Pins with
additional
LED direct drive
outputs
Note
functions
Transistor direct drive
N-ch open-drain
8
4
Real-time output ports
IEBus controller
4 bits × 2, or 8 bits × 1
Internal (simplify)
Timer/counters
Timer/counter 0: Timer register × 1
Pulse output capability
• Toggle output
(16 bits)
Capture register × 1
Compare register × 2
• PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register × 1
Real-time output port
(16 bits)
Capture register × 1
Capture/compare register × 1
Compare register × 1
Timer/counter 2: Timer register × 1
Pulse output capability
• Toggle output
(16 bits)
Capture register × 1
Capture/compare register × 1
Compare register × 1
• PWM/PPG output
Timer 3:
(16 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• Toggle output
• PWM/PPG output
Watch timer
Interrupt occurs at an interval of 0.5 sec. (Has an internal clock oscillator.)
The input clock can be selected from among the main clock (12.58 MHz) or
clock (32.7 kHz).
PWM output
12-bit resolution × 2 channels
Serial interfaces
• UART/IOE (3-wire serial I/O) : 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O): 2 channels
A/D converter
8-bit resolution × 8 channels
Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16
(can be used as 1-bit output port)
Watchdog timer
1 channel
Note The pins with additional functions are included in the I/O pins.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
µPD784937A µPD784938A µPD78F4938A
Product Name µPD784935A µPD784936A
Item
ROM correction function
External expansion function
Standby function
Internal (can be set for 4 points of correction address)
Available (can be set up to 1 MB)
HALT/STOP/IDLE mode
Interrupts
Hardware sources
27 (internal: 20, external: 7 (sampling clock variable input: 1))
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Software sources
Non-maskable
Maskable
Internal: 19, external: 6
4-level programmable priority
Three processing formats: Macro service/vectored interrupt/context switching
Power supply voltage
Package
• VDD = 4.0 to 5.5 V (at 12.58 MHz operation)
• VDD = 3.0 to 5.5 V (at 6.29 MHz operation)
100-pin plastic QFP (14 × 20 mm)
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1.16.5 Block diagram
RxD/SI1
UART/IOE2
PROGRAMMABLE
INTERRUPT
CONTROLLER
NMI
TxD/SO1
BAUD-RATE
GENERATOR
INTP0 to INTP5
ASCK/SCK1
RxD2/SI2
TxD2/SO2
UART/IOE1
INTP3
TO0
TO1
TIMER/COUNTER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
TIMER/COUNTER1
(16 BITS)
SCK0
SO0
SI0
CLOCKED
SERIAL
INTERFACE
INTP0
INTP1
INTP2/CI
TO2
78K/IV
CPU CORE
ROM
TIMER/COUNTER2
(16 BITS)
SCK3
SO3
SI3
CLOCKED
SERIAL
INTERFACE3
TO3
TIMER3
(16 BITS)
ASTB/CLKOUT
AD0 to AD7
CLOCK OUTPUT
BUS I/F
A8 to A15
A16 to A19
RD
WR
P00 to P03
P04 to P07
REAL-TIME
OUTPUT PORT
WAIT/HLDRQ
REFRQ/HLDAK
RAM
PWM0
PWM1
PWM
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT9
PORT10
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P90 to P97
P100 to P107
ANI0 to ANI7
AVDD
A/D
AVREF1
AVSS
CONVERTER
INTP5
TX
RX
IEBUS
CONTROLLER
RESET
Note
IC/VPP
X1
X2
REGC
REGOFF
SYSTEM
CONTROL
(REGULATOR)
WATCHDOG
TIMER
V
DD
VSS
XT1
XT2
WATCH
TIMER
Note In the flash memory programming mode of the µPD78F4938A.
Remark Internal ROM and RAM capacities vary depending on the products.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.17 Product Outline of µPD784956A Subseries
(µPD784953A, 784956A, 78F4956A)
1.17.1 Features
• Minimum instruction execution time: 160 ns (at fCLK = 12.5 MHz operation)
• On-chip memory
• ROM
Mask ROM
: 24 KB (µPD784953A)
48 KB (µPD784956A)
Flash memory : 64 KB (µPD78F4956A)
• RAM
: 768 bytes (µPD784953A)
: 2,048 bytes (µPD784956A, 78F4956A)
• I/O port : 67
• Timer/counter: 16-bit timer/counter × 6 units
8-bit timer/counter × 2 units
• Serial interface: 2 channels
UART: 1 channel (on-chip baud rate generator)
CSI (3-wire serial I/O): 1 channel
• A/D converter: 8-bit resolution × 8 channels
• Real-time output function: 6-bit resolution × 2 channels
• Watchdog timer: 1 channel
• Standby function
HALT/STOP/IDLE mode
Low power consumption mode: HALT/IDLE mode (subsystem clock operation)
• Interrupt controller (4-level priority)
Vector interrupt/macro service/context switching
• Power supply voltage: VDD = 4.5 to 5.5 V
1.17.2 Applications
Motor control for inverter air conditioners, etc.
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1.17.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784953AGC-×××-8BT 80-pin plastic QFP (14 × 14 mm)
µPD784956AGC-×××-8BT 80-pin plastic QFP (14 × 14 mm)
Mask ROM
Mask ROM
Flash Memory
µPD78F4956AGC-8BT
80-pin plastic QFP (14 × 14 mm)
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
µPD784953AGC-×××-8BT 80-pin plastic QFP (14 × 14 mm)
µPD784956AGC-×××-8BT 80-pin plastic QFP (14 × 14 mm)
Standard
Standard
Standard
µPD78F4956AGC-8BT
80-pin plastic QFP (14 × 14 mm)
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
Caution The µPD784956A Subseries is under development.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.17.4 Outline of functions
(1/2)
Product Name
µPD784953A
µPD784956A
µPD78F4956A
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
On-chip memory capacity ROM
160 ns (at fCLK = 12.5 MHz operation)
24 KB
64 KB
64 KB
(Mask ROM)
(Mask ROM)
(Flash memory)
RAM
768 bytes
2,048 bytes
I/O ports
Total
67
8
CMOS input
CMOS I/O
59
59
Pins with
additional
Pin with pull-up
resistor
Note
functions
Real-time output port
Timer/counters
LED direct drive output 32
6 bits × 2
16-bit timer/counter: Timer register × 1
Pulse output capability
Capture/compare register × 2 • PWM output
16-bit timer/counter 1: Timer register × 1
Compare register × 2
Pulse output capability
• PWM output
16-bit timer/counter 2: Timer register × 1
Compare register × 2
Pulse output capability
• PWM output
16-bit timer/counter 3: Timer register × 1
Compare register × 2
16-bit timer/counter 4: Timer register × 1
Capture/compare register × 3
16-bit timer/counter 5: Timer register × 1
Compare register × 1
Capture/compare register × 2
8-bit timer/counter 6: Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
8-bit timer/counter 7: Timer register × 1
Compare register × 1
Serial interfaces
• UART: 1 channel (on-chip baud rate generator)
• CSI (3-wire serial I/O): 1 channel
A/D converter
8-bit resolution × 8 channels
1 channel
Watchdog timer
Standby function
HALT/STOP/IDLE mode
Note The pins with additional functions are included in the I/O pins.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784953A
µPD784956A
µPD78F4956A
Item
Interrupts
Hardware sources 28 (internal: 22, external: 8 (shared with internal: 2))
Software sources
Non-maskable
Maskable
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 20, external: 7
• 4-level programmable priority
• 3 processing modes: vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 4.5 to 5.5 V
80-pin plastic QFP (14 × 14 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.17.5 Block diagram
PROGRAMMABLE
INTERRUPT
CONTROLLER
UART
BAUD-RATE
GENERATOR
RxD
TxD
INTP0 to INTP6
INTP0
INTP1
TO0
SI
SO
SCK
CLOCKED
SERIAL
INTERFACE
TIMER/COUNTER
(16BITS)
TIMER/COUNTER1
(16BITS)
TO1
TO2
RD
BUS I/F
TIMER/COUNTER2
(16BITS)
WR
78K/IV
CPU CORE
ROM
P00 to P07
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT9
TIMER/COUNTER3
(16BITS)
P10 to P17
INTP2
INTP3
INTP4
TIMER/COUNTER4
(16BITS)
P20, P21,
P25 to P27
INTP5
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P90 to P95
TIMER/COUNTER5
(16BITS)
INTP6
RAM
TIMER/COUNTER6
(8BITS)
TO6
TIMER/COUNTER7
(8BITS)
WATCHDOGTIMER
INTP3
RTP02 to RTP07
INTP5
REAL-TIME
OUTPUTPORT0
RESET
X1
REAL-TIME
OUTPUTPORT1
X2
SYSTEM
CONTROL
RTP12 to RTP17
VDD
V
SS
Note
IC/VPP
ANI0 to ANI7
INTP0
AVDD
AVSS
A/D
CONVERTER
AVREF
Note In the flash memory programming mode of the µPD78F4956A.
Remark Internal ROM and RAM capacities vary depending on the products.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.18 Product Outline of µPD784976A Subseries
(µPD784975A, 78F4976A)
1.18.1 Features
• Minimum instruction execution time: 160 ns (at fXX =12.58 MHz operation)
• On-chip memory
• Mask ROM
: 96 KB (µPD784975A)
• Flash memory : 128 KB (µPD78F4976A)
• RAM
: 3,072 bytes (µPD784975A)
: 4,608 bytes (µPD78F4976A)
• I/O port : 72
• VFD controller/driver: Total display output pins: 48 (universal grid compatible)
• Display current 10 mA: 16 pins
• Display current 3 mA: 32 pins
• Timer/counter: 16-bit timer/counter × 1 unit
8-bit PWM timer × 1 unit
• Serial interface: 3 channels
• CSI (3-wire serial I/O): 2 channels
• UART/IOE (3-wire serial I/O): 1 channel
• A/D converter: 8-bit resolution × 12 channels
• Watchdog timer: 1 channel
• Standby function: HALT/STOP/IDLE mode
• Power supply voltage: VDD = 4.5 to 5.5 V
1.18.2 Applications
Combined mini-component audio systems, separate mini-component audio systems, tuners, cassette decks, CD
players, and audio amplifiers.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.18.3 Ordering information and quality grade
(1) Ordering information
Part Number
Package
Internal ROM
µPD784975AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD78F4976AGF-3BA 100-pin plastic QFP (14 × 20 mm)
Mask ROM
One-time PROM
Remark ××× indicates ROM code suffix.
(2) Quality grades
Part Number
Package
Quality Grade
µPD784975AGF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µPD78F4976AGF-3BA 100-pin plastic QFP (14 × 20 mm)
Standard
Standard
Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Remark ××× indicates ROM code suffix.
Caution µPD784976A Subseries are under development.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.18.4 Outline of functions
(1/2)
Product Name
µPD784975A
µPD78F4976A
Item
Number of basic instructions (mnemonics)
General-purpose registers
113
8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapped)
Minimum instruction execution time
On-chip memory capacity ROM
160 n/320 ns/640 ns/1,280 ns/2,560 ns (at fXX = 12.5 MHz operation)
96 KB
128 KB
(Mask ROM)
(Flash memory)
RAM
3,072 bytes
4,608 bytes
VFD display RAM 96 bytes
Memory space
1 MB total both programs and data
I/O ports
(including VFD-
multiplexed pin)
Total
72
12
20
8
CMOS input
CMOS I/O
N-ch open-drain
I/O
P-ch open-drain
I/O
24
8
P-ch open-drain
input
Pins with
functions
additional
Pins with pull-up
resistors
20
Note
LED direct drive output 16
High voltage
32
resistance pin
Medium voltage
resistance pins
8
VFD controller/driver
Timer/counters
• Total display output: 48
• Display current 10 mA: 16
• Display current 3 mA: 32
Timer/counter:
(16 bits)
Timer register × 1
Capture/compare register × 2
PWM timer 50:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
PWM timer 51:
(8 bits)
Timer register × 1
Compare register × 1
Pulse output capability
• PWM output
Serial interfaces
• UART/IOE (3-wire serial I/O): 1 channel (on-chip baud rate generator)
• CSI (3-wire serial I/O): 2 channels
A/D converter
Watch timer
8-bit resolution × 12 channels
1 channel
Watchdog timer
Standby functions
1 channel
HALT/STOP/IDLE mode
Note The pins with additional functions are included in the I/O pins.
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
(2/2)
Product Name
µPD784975A
µPD78F4976A
Item
Interrupts
Hardware sources 12 (internal: 7, external: 3, internal/external altarnative: 2)
Software sources
Non-maskable
Maskable
BRK instruction, BRKCS instructions, operand error
Internal: 1, external: 1
Internal: 14, external: 3, internal/external altarnative: 2
• 4-level programmable priority
• 3 processing modes: vectored interrupt, macro service, context switching
Power supply voltage
Package
VDD = 4.5 to 5.5 V
100-pin plastic QFP (14 × 20 mm)
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CHAPTER 1 FEATURES OF 78K/IV SERIES PRODUCTS
1.18.5 Block diagram
PORT0
PORT1
PORT2
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
P00 to P03
P10 to P17
P20, P25 to P27
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
P100 to P107
8-bit PWM TIMER
TIO50/P63
TIO51/P66
(TM50)
8-bit PWM TIMER
(TM51)
78K/IV
CPU CORE
ROM
16-bit TIMER/COUNTER
TI00/P20
(TM50)
WATCHDOG TIMER
SCK0/ASCK0/P27
SERIAL INTERFACE
(SIO0/UART)
SO0/T
SI0/R
X
D0/P26
D0/P25
X
RAM
SCK1/P62
SO1/P61
SI1/P60
SERIAL INTERFACE
(SIO1)
VFD
CONTROLLER/
DRIVER
FIP0 to FIP47
SERIAL
INTERFACE
(SIO2)
SCK2
SO2
SI2
VLOAD
RESET
X1
X2
ANI0/P10-
ANI7/P17,
ANI8/P00-
ANI11/P03
SYSTEM
CONTROL
A/D CONVERTER
AVDD
AVSS
WATCH TIMER
INTP0/P64
INTP1/P65
INTP2/P67
INTERRUPT
CONTROL
(INT)
V
DD0
,
,
V
V
SS0
,
IC
(VPP
VDD1
SS1
)
VDD2
Remarks 1. Internal ROM capacity varies depending on the products.
2. VPP applies to the µPD78F4976A only.
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CHAPTER 2 MEMORY SPACE
2.1 Memory Space
The 78K/IV Series can access a maximum memory space of 16 MB. However, memory mapping varies from
product to product according to the on-chip memory capacity and pin status. Therefore, the User’s Manual —
Hardware for the individual products should be consulted for details of the memory map address areas.
The 78K/IV Series can access a 16 MB memory space. The mapping of the internal data area (special function
registers and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after
reset release, and can only be used once.
The program after reset release must be as follows.
RSTVCT CSEG AT
0
DW RSTSTRT
INITSEG CSEG BASE
RSTSTRT:LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
(1) When LOCATION 0H instruction is executed
The internal data area is mapped with the maximum address as FFFFH.
An area in the internal ROM that overlaps an internal data area cannot be used as internal ROM when the
LOCATION 0H instruction is executed.
External memory is accessed in external memory extension mode.
(2) When LOCATION 0FH instruction is executed
The internal data area is mapped with the maximum address as FFFFFH.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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Figure 2-1. Memory Map
When LOCATION 0H
instruction is executed
When LOCATION 0FH
instruction is executed
FFFFFFH
Special function
FFFFFFH
00FFFFH
00FFDFH
00FFD0H
00FF00H
0FFFFFH
registers (SFR)
0FFFDFH
0FFFD0H
Note
(256 bytes)
0FFF00H
0FFEFFH
00FEFFH
00FE80H
00FE3BH
General register area
(128 bytes)
100000H
0FFFFFH
100000H
0FFFFFH
0FFE80H
0FFE3BH
Internal
data area
Macro service
control word area
00FE06H
0FFE06H
Internal RAM area
Internal
high-speed RAM
(512 bytes) data area
Internal
ROM area
0FFD00H
010000H
00FFFFH
00FD00H
Internal
peripheral RAM
program/data area
010000H
00FFFFH
Internal
data area
Internal
ROM area
Internal
ROM area
000FFFH
000800H
000FFFH
000800H
CALLF
entry area
CALLF
entry area
00007FH
000040H
00003FH
000000H
00007FH
000040H
00003FH
CALLT
CALLT table area
Vector table area
table area
Vector
table area
000000H
Note External SFR area
Caution The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
CHAPTER 2 MEMORY SPACE
2.2 Internal ROM Area
The 78K/IV Series products shown below incorporate ROM which is used to store programs, table data, etc.
If the internal ROM area and internal data area overlap when the LOCATION 0H instruction is executed, the internal
data area is accessed, and the overlapping part of the internal ROM area cannot be accessed.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
Table 2-1. List of Internal ROM Space for 78K/IV Series Products (1/2)
Subseries Name
Product
Address Space
None
Internal ROM
µPD784026 Subseries
µPD784020
µPD784021
µPD784025
00000H to 0BFFFH
00000H to 0FFFFH
48 K × 8 bits
64 K × 8 bits
µPD784026
µPD78P4026
µPD784038 Subseries
µPD784038Y Subseries
µPD784031
µPD784031Y
None
µPD784035
µPD784035Y
00000H to 0BFFFH
00000H to 0FFFFH
00000H to 17FFFH
00000H to 1FFFFH
48 K × 8 bits
64 K × 8 bits
96 K × 8 bits
128 K × 8 bits
µPD784036
µPD784036Y
µPD784037
µPD784037Y
µPD784038
µPD78P4038
µPD784038Y
µPD78P4038Y
µPD784046 Subseries
µPD784216A Subseries
µPD784044
µPD784054
00000H to 07FFFH
00000H to 0FFFFH
00000H to 17FFFH
00000H to 1FFFFH
32 K × 8 bits
64 K × 8 bits
96 K × 8 bits
128 K × 8 bits
µPD784046
µPD78F4046
µPD784214A
µPD784216AY Subseries µPD784214AY
µPD784215A
µPD784215AY
µPD784216A
µPD784216AY
µPD78F4216A
µPD78F4216AY
µPD784218A Subseries
µPD784218AY Subseries µPD784217AY
µPD784217A
00000H to 2FFFFH
00000H to 3FFFFH
192 K × 8 bits
256 K × 8 bits
µPD784218A
µPD784218AY
µPD78F4218A
µPD78F4218AY
Remark In case of a ROM-less product, this address space is an external memory.
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CHAPTER 2 MEMORY SPACE
Table 2-1. List of Internal ROM Space for 78K/IV Series Products (2/2)
Subseries Name
Product
Address Space
Internal ROM
µPD784225 Subseries
µPD784225Y Subseries
µPD784224
µPD784224Y
µPD784225
00000H to 17FFFH
96 K × 8 bits
00000H to 1FFFFH
128 K × 8 bits
µPD784225Y
µPD78F4225
µPD78F4225Y
µPD784908 Subseries
µPD784915 Subseries
µPD784907
00000H to 17FFFH
00000H to 1FFFFH
96 K × 8 bits
128 K × 8 bits
µPD784908
µPD78P4908
µPD784915B
µPD784916B
µPD78P4916
00000H to 0BFFFH
00000H to 0F6FFH
48 K × 8 bits
62 K × 8 bits
µPD784928 Subseries
µPD784928Y Subseries
µPD784927
µPD784927Y
00000H to 17FFFH
00000H to 1FFFFH
96 K × 8 bits
128 K × 8 bits
µPD784928
µPD784928Y
µPD78F4928
µPD78F4928Y
µPD784938A Subseries
µPD784935A
µPD784936A
00000H to 17FFFH
00000H to 1FFFFH
96 K × 8 bits
128 K × 8 bits
µPD784937A
µPD784938A
00000H to 2FFFFH
00000H to 3FFFFH
192 K × 8 bits
256 K × 8 bits
µPD78F4938A
µPD784953A
µPD784956A
µPD78F4956A
µPD784975A
µPD78F4976A
µPD784956A Subseries
µPD784976A Subseries
00000H to 05FFFH
00000H to 0F6FFH
00000H to 0F6FFH
00000H to 17FFFH
00000H to 1FFFFH
24 K × 8 bits
64 K × 8 bits
64 K × 8 bits
96 K × 8 bits
128 K × 8 bits
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CHAPTER 2 MEMORY SPACE
2.3 Base Area
The space from 00000H to FFFFFH comprises the base area. The base area is the object for the following uses.
• Reset entry address
• Interrupt entry address
• CALLT instruction entry address
• 16-bit immediate addressing mode (with instruction address addressing)
• 16-bit direct addressing mode
• 16-bit register addressing mode (with instruction address addressing)
• 16-bit register indirect addressing mode
• Short direct 16-bit memory indirect addressing mode
The vector table area, CALLT instruction table area and CALLF instruction entry area are allocated to the base
area.
When the LOCATION 0H instruction is executed, the internal data area is located in the base area. Note that,
in the internal data area, program fetches cannot be performed from the internal high-speed RAM area and special
function register (SFR) area. Also, internal RAM area data should only be used after initialization has been performed.
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CHAPTER 2 MEMORY SPACE
2.3.1 Vector table area
The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The vector table area holds the
program start addresses used when a jump is performed as the result of RESET input or generation of an interrupt
request. When context switching is used by an interrupt, the number of the register bank to be switched to is stored
here.
Any portion not used by the vector table can be used as program memory or data memory.
16-bit values can be written to the vector table. Therefore, branches can only be made within the base area.
Table 2-2. Vector Table
Vector Table Address
00000H
Interrupts
Reset (RESET input)
Note
00002H
NMI
Note
00004H
WDT
00006H
to
Differs for each product
0003AH
0003CH
0003EH
Operand error interrupt
BRK
Note Not used by some products.
2.3.2 CALLT instruction table area
The 1-byte call instruction (CALLT) subroutine entry addresses can be stored in the 64-byte area from 00040H
to 0007FH.
The CALLT instruction references this table, and branches to a base area address written in the table as a
subroutine. As the CALLT instruction is one byte in length, use of the CALLT instruction for subroutine calls written
frequently throughout the program enables the program object size to be reduced. The table can contain up to 32
subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency.
If this area is not used as the CALLT instruction table, it can be used as ordinary program memory or data memory.
Values that can be written to the CALLT instruction table are 16-bit values. Therefore, a branch can only be made
within the base area.
2.3.3 CALLF instruction entry area
A subroutine call can be made directly to the area from 00800H to 00FFFH with the 2-byte call instruction (CALLF).
As the CALLF instruction is a two-byte call instruction, it enables the object size to be reduced compared with use
of the direct subroutine call CALL instruction (3 bytes).
Writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device.
If you wish to reduce the object size, writing an unconditional branch (BR) instruction in this area and locating the
subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more
points. In this case, only the 4 bytes of the BR instruction are occupied in the CALLF entry area, enabling the object
size to be reduced with a large number of subroutines.
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2.4 Internal Data Area
The internal data area comprises the internal RAM area and special function register area. In some products,
memories dependent on other hardware are also allocated to this areas (see the User’s Manual — Hardware of each
product).
The final address of the internal data area can be specified by means of the LOCATION instruction as either FFFFH
(when a LOCATION 0H instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed).
Selection of the addresses of the internal data area by means of the LOCATION instruction must be executed once
immediately after reset release, and once the selection is made, it cannot be changed. The program after reset release
must be as shown in the example below. If the internal data area and another area are allocated to the same
addresses, the internal data area is accessed and the other area cannot be accessed.
Example RSTVCT CSEG AT 0
DW
RSTSTRT
INITSEG CSEG BASE
RSTSTRT:LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
Cautions 1. When the LOCATION 0H instruction is executed, it is necessary to ensure that the program
after reset release does not overlap the internal data area. It is also necessary to make sure
that the entry addresses of the service routines for non-maskable interrupts such as NMI do
not overlap the internal data area. Also, initialization must be performed for maskable
interrupt entry areas, etc., before the internal data area is referenced.
2. The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
2.4.1 Internal RAM area
78K/IV Series products incorporate general-purpose static RAM.
This area is configured as follows:
Peripheral RAM (PRAM)
• Internal RAM area
Internal high-speed RAM (IRAM)
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Table 2-3. Internal RAM Area in 78K/IV Series Products (1/2)
Subseries Name
Product
Internal RAM area
Peripheral RAM: PRAM
0 Byte
Internal high-speed RAM: IRAM
µPD784026 Subseries
µPD784020
512 Bytes
512 Bytes
(0FD00H to 0FEFFH)
(0FD00H to 0FEFFH)
µPD784021
µPD784025
µPD784026
µPD78P4026
2,048 Bytes
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784038 Subseries
µPD784038Y Subseries
µPD784031
µPD784031Y
µPD784035
µPD784036
µPD784035Y
µPD784036Y
2,048 Bytes
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784037
3,584 Bytes
3,072 Bytes
µPD784037Y
(0F100H to 0FEFFH)
(0F100H to 0FCFFH)
µPD784038
4,352 Bytes
3,840 Bytes
µPD78P4038
µPD784038Y
µPD78P4038Y
(0EE00H to 0FEFFH)
(0FE00H to 0FCFFH)
µPD784046 Subseries
µPD784216A Subseries
µPD784044
µPD784054
1,024 Bytes
512 Bytes
(0FB00H to 0FEFFH)
(0FB00H to 0FCFFH)
µPD784046
µPD78F4046
2,048 Bytes
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784214A
3,584 Bytes
3,072 Bytes
µPD784216AY Subseries µPD784214AY
(0F100H to 0FEFFH)
(0F100H to 0FCFFH)
µPD784215A
5,120 Bytes
4,608 Bytes
µPD784215AY
(0EB00H to 0FEFFH)
(0FB00H to 0FCFFH)
µPD784216A
8,192 Bytes
7,680 Bytes
µPD784216AY
µPD78F4216A
µPD78F4216AY
(0DF00H to 0FEFFH)
(0DF00H to 0FCFFH)
µPD784218A Subseries
µPD784217A
12,800 Bytes
12,288 Bytes
µPD784218AY Subseries µPD784217AY
(0CD00H to 0FEFFH)
(0CD00H to 0FCFFH)
µPD784218A
µPD784218AY
µPD78F4218A
µPD78F4218AY
µPD784225 Subseries
µPD784225Y Subseries
µPD784224
µPD784224Y
3,584 Bytes
3,072 Bytes
(0F100H to 0FEFFH)
(0CF10H to 0FCFFH)
µPD784225
4,352 Bytes
3,840 Bytes
µPD784225Y
µPD78F4225
µPD78F4225Y
(0EE00H to 0FEFFH)
(0EE00H to 0FCFFH)
Remark The addresses in the table are the values that apply when the LOCATION 0H instruction is executed.
When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
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Table 2-3. Internal RAM Area in 78K/IV Series Products (2/2)
Subseries Name
Product
Internal RAM area
Peripheral RAM: PRAM
Internal high-speed RAM: IRAM
µPD784908 Subseries
µPD784907
3,584 Bytes
3,072 Byte
512 Bytes
(0F100H to 0FEFFH)
(0F100H to 0FEFFH)
(0FD00H to 0FEFFH)
µPD784908
4,352 Bytes
3,840 Bytes
µPD78P4908
(0EE00H to 0FEFFH)
(0EE00H to 0FCFFH)
µPD784915 Subseries
µPD784915B
µPD784916B
µPD78P4916
1,280 Bytes
768 Bytes
(0FA00H to 0FEFFH)
2,048 Bytes
(0FA00H to 0FCFFH)
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784928 Subseries
µPD784928Y Subseries
µPD784927
µPD784927Y
2,048 Bytes
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784928
3,584 Bytes
µPD784928Y
(0F100H to 0FEFFH)
µPD78F4928
µPD78F4928Y
µPD784938A Subseries
µPD784935A
µPD784936A
µPD784937A
5,120 Bytes
4,608 Bytes
(0EB00H to 0FEFFH)
(0EB00H to 0FCFFH)
6,656 Bytes
6,144 Bytes
(0E500H to 0FEFFH)
(0E500H to 0FCFFH)
8,192 Bytes
7,680 Bytes
(0DF00H to 0FEFFH)
(0DF00H to 0FCFFH)
µPD784938A
µPD78F4938A
µPD784953A
10,496 Bytes
9,984 Bytes
(0D600H to 0FEFFH)
(0D600H to 0FCFFH)
µPD784956A Subseries
µPD784976A Subseries
768 Bytes
256 Bytes
(0FC00H to 0FEFFH)
(0FC00H to 0FCFFH)
µPD784956A
µPD78F4956A
2,048 Bytes
1,536 Bytes
(0F700H to 0FEFFH)
(0F700H to 0FCFFH)
µPD784975A
3,584 Bytes
3,072 Bytes
(0F100H to 0FEFFH)
(0F100H to 0FCFFH)
µPD78F4976A
5,120 Bytes
4,608 Bytes
(0EB00H to 0FEFFH)
(0EB00H to 0FCFFH)
Remark The addresses in the table are the values that apply when the LOCATION 0H instruction is executed.
When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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Internal RAM mapping is shown in Figure 2-2.
Figure 2-2. Internal RAM Memory Mapping
00FEFFH
00FE80H
General-purpose
register area
Short direct addressing
1 permissible range
00FE3BH
00FE04H
Macro service
control word area
Internal high-speed RAM
00FE00H
00FDFFH
Short direct addressing
2 permissible range
00FD20H
00FD1FH
00FD00H
00FCFFH
Peripheral RAM
Differs
according
to product
Remark The addresses in the figure are the values that apply when the LOCATION 0H instruction is executed.
When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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(1) Internal high-speed RAM (IRAM)
The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing
mode for high-speed accesses can be used on 0FD20H to 0FEFFH in this area. There are two kinds of short
direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target
address. The function is the same in both of these addressing modes. With some instructions, the word length
is shorter with short direct addressing 2 than with short direct addressing 1. See CHAPTER 6 INSTRUCTION
SET for details.
A program fetch cannot be performed from IRAM. If a program fetch is performed from an address onto which
IRAM is mapped, CPU runaway will result.
The following areas are reserved in IRAM.
• General register area
: 0FE80H to 0FEFFH
• Macro service control word area : 0FE06H to 0FE3BH (theaddressesactuallyreserveddifferfromproduct
to product)
• Macro service channel area
: 0FE00H to 0FEFFH (the address is specified by the macro service
control word)
If the reserved function is not used in these areas, they can be used as ordinary data memory.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed.
When the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
(2) Peripheral RAM (PRAM)
The peripheral RAM (PRAM) is used as ordinary program memory or data memory. When used as program
memory, he program must be written to the peripheral RAM beforehand by a program.
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2.4.2 Special function register (SFR) area
The on-chip peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to
0FFFFH (see the User’s Manual — Hardware for the individual products).
In some products, the area from 0FFD0H to 0FFDFH is mapped as an external SFR area, and allows externally
connected peripheral I/Os, etc., to be accessed in external memory extension mode (specified by the memory
extension mode register (MM)) by ROM-less products or on-chip ROM products.
Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an address
is accessed by mistake, the CPU may become deadlocked. A deadlock can only be released by reset
input.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed. When
the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
2.4.3 External SFR area
In some 78K/IV Series products, the 16-byte area from 0FFD0H to 0FFDFH in the SFR area (when the LOCATION
0H instruction is executed; 0FFFD0H to 0FFFDFH when the LOCATION 0FH instruction is executed) is mapped as
an external SFR area. When the external memory extension mode is set in a ROMless product or on-chip ROM
product, externally connected peripheral I/Os, etc., can be accessed using the address bus or address/data bus, etc.
As the external SFR area can be accessed by SFR addressing, peripheral I/O and similar operations can be
performed easily, the object size can be reduced, and macro service can be used.
Bus operations for accesses to the external SFR area are performed in the same way as for ordinary memory
accesses.
2.5 External Memory Space
The external memory space is a memory space that can be accessed in accordance with the setting of the memory
extension mode register (MM). It can hold programs, table data, etc., and can have peripheral I/O devices allocated
to it.
A program cannot be allocated to the area from 100000H to 0FFFFFFH in the external memory space.
Note also that some products do not have an external memory space.
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3.1 Control Registers
Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP).
3.1.1 Program counter (PC)
This is a 20-bit binary counter that holds information on the next program address to be executed (see Figure 3-
1).
Normally, the PC is incremented automatically by the number of bytes in the fetched instruction. When an
instruction associated with a branch is executed, the immediate data or register contents are set in the PC.
Upon RESET input, the 16-bit data in address 0 and address 1 is set in the lower 16 bits of the PC, and 0000 in
the higher 4 bits.
Figure 3-1. Program Counter (PC) Configuration
19
0
PC
3.1.2 Program status word (PSW)
The program status word (PSW) is a 16-bit register comprising various flags that are set or reset according to the
result of instruction execution.
Read accesses and write accesses are performed in higher 8 bits (PSWH) and lower 8 bits (PSWL) units. Individual
flags can be accessed by bit-manipulation instructions.
The contents of the PSW are automatically saved to the stack when a vectored interrupt request is acknowledged
or a BRK instruction is executed, and automatically restored when an RETI or RETB instruction is executed. When
context switching is used, the contents are automatically saved in RP3, and automatically restored when an RETCS
or RETCSB instruction is executed.
RESET input resets (0) all bits.
“0” must always be written to the bits written as “0” in Figure 3-2. The contents of bits written as “–” are undefined
when read.
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Figure 3-2. Program Status Word (PSW) Configuration
7
6
5
4
3
2
1
0
PSWH
PSWL
UF
RBS2
RBS1
RBS0
—
—
—
—
7
6
Z
5
4
3
2
1
0
0
S
RSS
AC
IE
P/V
CY
The flags are described below.
(1) Carry flag (CY)
The carry flag stores a carry or borrow resulting from an operation.
This flag also stores the shifted-out value when a shift/rotate instruction is executed, and functions as a bit
accumulator when a bit-manipulation instruction is executed.
The status of the CY flag can be tested with a conditional branch instruction.
(2) Parity/overflow flag (P/V)
The P/V flag performs the following two kinds of operation associated with execution of an operation instruction.
The status of the P/V flag can be tested with a conditional branch instruction.
• Parity flag operation
Set (1) when the number of bits set (1) as the result of execution of a logical operation instruction, shift/
rotate instruction, or a CHKL or CHKLA instruction is even, and reset (0) if odd. When a 16-bit shift instruction
is executed, however, only the lower 8 bits of the operation result are valid for the parity flag.
• Overflow flag operation
Set (1) when the numeric range expressed as a two’s complement is exceeded as the result of execution
of a logical operation instruction, and reset (0) otherwise. More specifically, the value of this flag is the
exclusive OR of the carry into the MSB and the carry out of the MSB. For example, the two’s complement
range in an 8-bit arithmetic operation is 80H (–128) to 7FH (+127), and the flag is set (1) if the operation
result is outside this range, and reset (0) if within this range.
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Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below.
When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225),
and the two’s complement limit is exceeded, with the result that the P/V flag is set (1). Expressed
as a two’s complement, E1H is –31.
78H (+120)
=
=
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 1
+) 69H (+105)
+) 0 1 1 0
0
↑
1 1 1 0
=
–31
P/V = 1
CY
When the following two negative numbers are added together, the operation result is within the
two’s complement range, and therefore the P/V flag is reset.
FBH (–5)
=
=
1 1 1 1
1 0 1 1
0 0 0 0
1 0 1 1
+) F0H (–16)
+) 1 1 1 1
1
↑
1 1 1 0
=
–21
P/V = 0
CY
(3) Interrupt request enable flag (IE)
This flag controls CPU interrupt request acknowledgment operations.
When “0”, interrupts are disabled, and only non-maskable interrupts and unmasked macro service requests
can be acknowledged. All other interrupts are disabled.
When “1”, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled
by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual
interrupts.
The IE flag is set (1) by execution of an EI instruction, and reset (0) by execution of a DI instruction or
acknowledgment of an interrupt.
(4) Auxiliary carry flag (AC)
The AC flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation,
and reset (0) otherwise.
This flag is used when the ADJBA or ADJBS instruction is executed.
(5) Register set selection flag (RSS)
The RSS flag specifies the general registers that function as X, A, C, and B, and the general register pairs
(16-bit) that function as AX and BC.
This flag is provided to maintain compatibility with the 78K/III Series, and must be set to 0 except when using
a 78K/III Series program.
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(6) Zero flag (Z)
The Z flag records that the result of an operation is “0”.
It is set (1) when the result of an operation is “0”, and reset (0) otherwise. The status of the Z flag can be
tested with a conditional branch instruction.
(7) Sign flag (S)
The S flag records that the MSB is “1” as the result of an operation.
It is set (1) when the MSB is “1” as the result of an operation, and reset (0) otherwise. The status of the S
flag can be tested with a conditional branch instruction.
(8) Register bank selection flag (RBS0 to RBS2)
This is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (see Table
3-1).
It holds 3-bit information which indicates the register bank selected by execution of a SEL RBn instruction,
etc.
Table 3-1. Register Bank Selection
RBS2
RBS1
RBS0
Specified Register Bank
Register bank 0
Register bank 1
Register bank 2
Register bank 3
Register bank 4
Register bank 5
Register bank 6
Register bank 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(9) User flag (UF)
This flag can be set and reset in the user program, and used for program control.
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3.1.3 Use of RSS bit
Basically, the RSS bit should be fixed at 0 at all times.
The following explanation refers to the case where a 78K/III Series program is used, and the program used sets
the RSS bit to 1. This explanation can be skipped if the RSS bit is fixed at 0.
The RSS bit is provided to allow the functions of A (R1), X (R0), B (R3), C (R2), AX (RP0), and BC (RP1) to be
used by registers R4 to R7 (RP2, RP3) as well. Effective use of this bit enables efficient programs to be written in
terms of program size and program execution.
However, careless use can result in unforeseen problems. Therefore, the RSS bit should always be set to 0. The
RSS bit should only be set to 1 when a 78K/III Series program is used.
Use of the RSS bit set to 0 in all programs will improve programming and debugging efficiency.
Even when using a program in which the RSS bit is used set to 1, it is recommended that the program be amended
if possible so that it does not set the RSS bit to 1.
(1) RSS bit functions
• Registers used by instructions for which the A, X, B, C, and AX registers are directly entered in the operand
column of the instruction operation list (see 6.2.)
• Registers specified as implied by instructions that use the A, AX, B, and C registers by means of implied
addressing
• Registers used in addressing by instructions that use the A, B, and C registers in indexed addressing and
based indexed addressing
The registers used in these cases are switched as follows according to the RSS bit.
– When RSS = 0
A → R1, X → R0, B → R3, C → R2, AX → RP0, BC → RP1
– When RSS = 1
A → R5, X → R4, B → R7, C → R6, AX → RP2, BC → RP3
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Registers used other than those mentioned above are always the same irrespective of the value of the RSS
bit. With the NEC assembler (RA78K4), the register operation code generated when the A, X, B, C, AX, and
BC registers are described by those names is determined by the assembler RSS pseudo-instruction.
When the RSS bit is set or reset, an RSS pseudo-instruction must be written immediately before (or
immediately after) the relevant instruction (see example below).
<Program example>
• When RSS is set to 0
RSS 0
; RSS pseudo-instruction
CLR1 PSWL.5
MOV B, A
; This description is equivalent to “MOV R3, R1”.
• When RSS is set to 1
RSS 1
; RSS pseudo-instruction
SET1 PSWL.5
MOV B, A
; This description is equivalent to “MOV R7, R5”.
(2) Operation code generation method with RA78K4
• With RA78K4, if there is an instruction with the same function as an instruction for which A or AX is directly
entered in the operand column of the instruction operation list, the operation code for which A or AX is directly
entered in the operand column is generated first.
Example The function is the same when B is used for r in a MOV A, r instruction and when A is used as
r and B is used as r’ in a MOV r, r’ instruction, and the same description (MOVA, B) is used in
the assembler source program. In this case, RA78K4 generates code equivalent to the MOV
A, r instruction.
Remark The register that is actually used with this instruction is determined when the program is run
according to the contents of the RSS bit in the PSW. When RSS = 0, R1 or RP0 is used, and
when RSS = 1, R5 or RP2 is used.
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• If A, X, B, C, AX, or BC is written in an instruction for which r, r’, rp and rp’ are specified in the operand column,
the A, X, B, C, AX, and BC instructions generate an operation code that specifies the following registers
according to the operand of the RA78K4 pseudo-instruction.
Register
RSS 0
R1
RSS 1
R5
A
X
R0
R4
B
R3
R7
C
R2
R6
AX
BC
RP0
RP1
RP2
RP3
• If R0 to R7 or RP0 to RP4 is written as r, r’, rp or rp’ in the operand column, an operation code in accordance
with that specification is output (an operation code for which A or AX is directly entered in the operand column
is not output.)
• Descriptions R1, R3, R2 or R5, R7, R6 cannot be used for registers A, B, and C used in indexed addressing
and based indexed addressing.
(3) Operating precautions
Switching the RSS bit has the same effect as having two register sets. However, the following point must
be noted. If use with RSS = 1 is essential, these defects must be given full consideration when writing the
program.
(a) When writing a program, care must be taken to ensure that the static program description and dynamic
RSS bit changes at the time of program execution always coincide.
For example, when an MOV A, B instruction is assembled by RA78K4, MOV A, r code is generated. In
this case, the registers actually used are as shown below according to the RSS pseudo-instruction written
directly before the MOV A, B instruction in the source program and the RSS bit in the PSW when the
program is run.
RSS Pseudo-Instruction Operand
0
1
RSS bit in PSW
0
1
MOV R1, R3
MOV R5, R3
MOV R1, R7
MOV R5, R7
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(b) As a program that sets RSS to 1 cannot be used by a program that uses the context switching function,
program applicability is poor.
(c) If interrupts are used by a program with more than one section in which the RSS bit in the PSW is set
to “1”, it is necessary to set the RSS bit in the PSW to “0” or “1” at the beginning of the interrupt service
program, and write an RSS pseudo-instruction corresponding to this in the source program. If this is not
done, the execution results may sometimes be incorrect. For example, consider the following interrupt
service program.
INT:
PUSH AX
MOV A, #byte
ADD !!addr24, A
POP AX
RETI
In this program, the register determined at assembly time by the RSS pseudo-instruction written
immediately before is used as the AX or A register in the “PUSH AX”, “MOV A, #byte”, and “POP AX”
instructions. However, in the “ADD !!addr24, A” instruction, the register used as the A register is
determined by the value to which the interrupted program set the RSS bit in the PSW. Therefore, either
the expected value or an unexpected value may be stored in the memory specified by !!addr24.
In this example, only the interrupt service program execution result is in error, but if, for example, the ADD
instruction operands are reversed (ADD A, !!addr24), the contents of the register used by the interrupt
program might be corrupted.
Since the phenomenon occurs in an irregular fashion with this kind of bug, it is extremely difficult to find
the cause during debugging.
(d) As different registers are used under the same name, program legibility is poor and debugging is difficult.
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3.1.4 Stack pointer (SP)
The stack pointer is a 24-bit register that holds the start address of the stack area (LIFO type: 000000H to FFFFFFH)
(see Figure 3-3). It is used to address the stack area when subroutine processing or interrupt servicing is performed.
The contents of the SP are decremented before a write to the stack area and incremented after a read from the
stack area (see Figures 3-4 and 3-5).
The SP is accessed by special instructions.
The SP contents are undefined after RESET input, and therefore the SP must always be initialized by an
initialization program directly after reset release (before a subroutine call or interrupt acknowledgment).
In some products a number of bits at the high-order end of the SP are fixed at 0. Please refer to the User’s Manual
— Hardware for the individual products for details.
Example SP initialization
MOVG SP, #0FEE0H;SP ← 0FEE0H (when used from FEDFH)
Figure 3-3. Stack Pointer (SP) Configuration
23
0
SP
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CHAPTER 3 REGISTERS
Figure 3-4. Data Saved to Stack Area
PUSH sfr
instruction
stack
PUSH sfrp
instruction
stack
SP
SP
↓
Higher byte
Lower byte
SP–1
↓
SP–1
↓
SP–2
SP←SP–1
SP←SP–2
PUSH PSW
instruction
stack
PUSH rg
instruction
stack
SP
↓
SP
↓
PSWH7-
PSWH4
Undefined
Higher byte
Middle byte
Lower byte
SP–1
SP–1
↓
↓
SP–2
SP–2
PSWL
↓
SP←SP–2
SP–3
SP←SP–3
PUSH post, PUSHU post instruction
(In case of PUSH AX, RP2, RP3)
stack
CALL, CALLF, CALLT
instruction stack
Vectored
interrupt stack
SP
SP
SP
↓
↓
↓
PSWH7-
Undefined PC19-PC16
PC15-PC8
SP–1
SP–1
SP–1
R7
R6
R5
R4
A
PC19-PC16
PSWH4
PSWL
↓
↓
↓
RP3
RP2
AX
SP–2
SP–2
SP–2
↓
↓
↓
SP–3
SP–3
↓
SP–4
SP–3
↓
SP–4
PC7-PC0
PC15-PC8
PC7-PC0
SP←SP–3
↓
SP←SP–4
SP–5
↓
X
SP–6
SP←SP–6
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CHAPTER 3 REGISTERS
Figure 3-5. Data Restored from Stack Area
POP sfr
instruction
stack
POP sfrp
instruction
stack
SP←SP+2
SP←SP+1
Higher byte
Lower byte
SP+1
↑
SP
SP
POP PSW
instruction
stack
POP rg
instruction
stack
SP←SP+2
SP←SP+3
↑
PSWH7-
PSWH4
Note
–
Higher byte
Middle byte
Lower byte
SP+1
SP+2
↑
SP
↑
SP+1
PSWL
↑
SP
POP post, POPU post instruction
(In case of POP AX, RP2, RP3)
stack
RET
instruction stack
RETI, RETB
instruction stack
SP←SP+6
SP←SP+3
SP←SP+4
PSWH7-
Note
–
PC19-PC16
SP+2
SP+3
SP+5
R7
R6
R5
R4
A
PC19-PC16
PSWH4
PSWL
↑
↑
↑
RP3
RP2
AX
SP+1
SP+2
SP+4
PC15-PC8
PC7-PC0
↑
SP
↑
SP+1
↑
↑
SP+3
↑
SP+2
PC15-PC8
PC7-PC0
SP
↑
SP+1
↑
SP
X
Note This 4-bit data is ignored.
Cautions 1. With stack addressing, the entire 16 MB space can be accessed but a stack area cannot be
reserved in the SFR area or internal ROM area.
2. The SP is undefined after RESET input. Moreover, non-maskable interrupts can still be
acknowledged when the SP is in an undefined state. An unanticipated operation may
therefore be performed if a non-maskable interrupt request is generated when the SP is in
the undefined state directly after reset release. To avoid this risk, the program after reset
release must be written as follows.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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CHAPTER 3 REGISTERS
RSTVCT
INITSEG
CSEG AT 0
DW RSTSTRT
CSEG BASE
RSTSTRT: LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
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CHAPTER 3 REGISTERS
3.2 General-Purpose Registers
3.2.1 Configuration
There are sixteen 8-bit general-purpose registers. Also, two general-purpose registers can be used together as
a 16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an
8-bit register for address extension and used as 24-bit address specification registers.
General-purpose registers other than the V, U, T, and W registers for address extension are mapped onto internal
RAM.
These register sets are provided in 8 banks, and can be switched by means of software or the context switching
function.
Upon RESET input, register bank 0 is selected. The register bank used during program execution can be checked
by reading the register bank selection flag (RBS0, RBS1, RBS2) in the PSW.
Figure 3-6. General-Purpose Register Configuration
7
0 7
0
A (R1)
B (R3)
R5
X (R0)
C (R2)
R4
AX (RP0)
BC (RP1)
RP2
R7
R9
R6
R8
RP3
V
U
T
VP (RP4)
VVP (RG4)
UUP (RG5)
TDE (RG6)
R11
R10
UP (RP5)
DE (RP6)
D (R13)
E (R12)
W
H (R15)
L (R14)
HL (RP7)
8 banks
WHL (RG7)
15
23
0
Remark Absolute names are shown in parentheses.
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Figure 3-7. General-Purpose Register Addresses
8-bit processing
16-bit processing
HL (RP7) (EH)
DE (RP6) (CH)
UP (RP5) (AH)
VP (RP4) (8H)
RP3 (6H)
FEFFHNote
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
H (R15) (FH) L (R14) (EH)
D (R13) (DH) E (R12) (CH)
R11
R10 (AH)
R8 (8H)
(BH)
R9 (9H)
R7 (7H)
R6 (6H)
R5 (5H)
R4 (4H)
RP2 (4H)
B (R3) (3H)
C (R2) (2H)
X (R0) (0H)
BC (RP1) (2H)
AX (RP0) (0H)
A (R1)
(1H)
FE80HNote
7
0 7
0
15
0
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed,
0F0000H should be added to the address values shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
Caution R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers respectively
by setting the RSS bit of the PSW to 1, but this function should only be used when using a 78K/
III Series program.
Remark When the register bank is switched, and it is necessary to return to the original register bank, an SEL
RBn instruction should be executed after first saving the PSW to the stack with a PUSH PSW instruction.
When returning to the original register bank, if the stack location does not change the POP PSW
instruction should be used.
When the register bank is changed by a vectored interrupt service program, etc., the PSW is automatically
saved to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so
that, if only one register bank is used in the interrupt service program, only an SEL RBn instruction need
be executed, and execution of a PUSH PSW and POP W instruction is not necessary.
.
.
.
Example 1. When register bank 2 is specified
.
PUSH PSW
.
.
.
SEL RB2
.
Operations in register bank 2
.
.
.
POP PSW
.
Operations in original register bank
2. When the register bank is specified by a vectored interrupt service program.
INT:
.
.
.
SEL RB5
.
Operation in register bank 5
RETI
Automatic return to original register bank
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CHAPTER 3 REGISTERS
3.2.2 Functions
In addition to being manipulated as 8-bit units, the general-purpose registers can also be manipulated as 16-bit
units by pairing two 8-bit registers. Also, four of the 16-bit general registers can be combined with an 8-bit register
for address extension and manipulated as 24-bit units.
Each register can be used in a general way for temporary storage of an operation result and as the operand of
an inter-register operation instruction.
The area from 0FE80H to 0FEFFH (when the LOCATION 0H is executed; 0FFE80H to 0FFEFFH when the
LOCATION 0FH instruction is executed) can be given an address specification and accessed as ordinary data memory
irrespective of whether or not it is used as the general-purpose register area.
As 8 register banks are provided in the 78K/IV Series, efficient programs can be written by using different register
banks for normal processing and processing in the event of an interrupt.
The registers have the following specific functions.
A (R1):
• Register mainly used for 8-bit data transfers and operation processing. Can be used in combination with all
addressing modes for 8-bit data.
• Can also be used for bit data storage.
• Can be used as the register that holds the offset value in indexed addressing and based indexed addressing.
X (R0):
• Can be used for bit data storage.
AX (RP0):
• Register mainly used for 16-bit data transfers and operation processing. Can be used in combination with all
addressing modes for 16-bit data.
AXDE:
• Used for 32-bit data storage when a DIVUX, MACW, or MACSW instruction is executed.
B (R3):
• Has a loop counter function, and can be used by the DBNZ instruction.
• Can be used as the register that holds the offset value in indexed addressing and based indexed addressing.
• Used as the MACW and MACSW instruction data pointer.
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C (R2):
• Has a loop counter function, and can be used by the DBNZ instruction.
• Can be used as the register that holds the offset value in based indexed addressing.
• Used as the counter in a string instruction and the SACW instruction.
• Used as the MACW and MACSW instruction data pointer.
RP2:
• Used to save the lower 16 bits of the program counter (PC) when context switching is used.
RP3:
• Used to save the higher 4 bits of the program counter (PC) and the program status word (PSW) (excluding bits
0 to 3 of PSWH) when context switching is used.
VVP (RG4):
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing,
based addressing and based indexed addressing.
UUP (RG5):
• Has a user stack pointer function, and enables a stack separate from the system stack to be implemented by
means of the PUSHU and POPU instructions.
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
DE (RP6), HL (RP7):
• Operate as the registers that specify the offset value in indexed addressing and based indexed addressing.
TDE (RG6):
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
• Used as the pointer in a string instruction and the SACW instruction.
WHL (RG7):
• Register used mainly for 24-bit data transfers and operation processing.
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
• Used as the pointer in a string instruction and the SACW instruction.
In addition to the function name that emphasizes the specific function of the register (X, A, C, B, E, D, L, H, AX,
BC, VP, UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be described by its absolute name (R0 to R15,
RP0 to RP7, RG4 to RG7). The correspondence between these names is shown in Table 3-2.
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Table 3-2. Function Names and Absolute Names
(a) 8-bit register
(b) 16-bit register
Function Name
Function Name
Absolute Name
Absolute Name
Note
Note
RSS = 0
RSS = 1
RSS = 0
AX
RSS = 1
R0
R1
X
A
C
B
RP0
RP1
RP2
RP3
RP4
RP5
RP6
RP7
BC
R2
AX
BC
VP
UP
DE
HL
R3
VP
UP
DE
HL
R4
X
A
C
B
R5
R6
R7
R8
R9
(c) 24-bit register
R10
R11
R12
R13
R14
R15
Absolute Name
RG4
Function Name
E
D
L
E
D
L
VVP
UUP
TDE
WHL
RG5
RG6
H
H
RG7
Note RSS should only be set to 1 when a 78K/III Series program is used.
Remark R8 to R11 have no function name.
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3.3 Special Function Registers (SFR)
These are registers to which a specific function is assigned, such as on-chip peripheral hardware mode registers,
control registers, etc., and they are mapped onto the 256-byte space from 0FF00H to 0FFFFH Note. Please refer
to the individual product documentation for details of the special function registers.
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed, the
area is 0FFF00H to 0FFFFFH.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an
address is accessed by mistake, the CPU may become deadlocked. A deadlock can only be
released by reset input.
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CHAPTER 4 INTERRUPT FUNCTIONS
The three kinds of processing shown in Table 4-1 can be programmed as servicing for interrupt requests.
Multiprocessing control using a 4-level priority system can easily be performed for maskable vectored interrupts.
Table 4-1. Interrupt Request Servicing
Service Mode
Service Performed by
Service
PC/PSW Contents
Vectored interrupts Software
Executed by branching to service routine Associated saving to & restoration
(any service contents)
from stack
Context switching
Executed by automatic switching of
register bank and branching to service
routine (any service contents)
Associated saving to & restoration
from fixed area in register bank
Macro service
Firmware
Execution of memory-I/O data transfers, No change
etc. (fixed service contents)
Remark Please refer to the User’s Manual — Hardware for the individual products for details.
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CHAPTER 4 INTERRUPT FUNCTIONS
4.1 Kinds of Interrupt Request
There are three kinds of interrupt request, as follows:
• Software interrupt requests
• Non-maskable interrupt requests
• Maskable interrupt requests
4.1.1 Software interrupt requests
An interrupt request by software is generated when a BRK instruction or BRKCS RBn instruction is executed, or
if here is an error in an operand of an MOV WDM, #byte instruction or MOV STBC, #byte instruction, LOCATION
instruction (operand error interrupt). Interrupt requests by software are acknowledged even in the interrupt disabled
(DI) state, and are not subject to interrupt priority control. Therefore, when an interrupt request is generated by
software, a branch is made to the interrupt service routine unconditionally.
To return from a BRK instruction, an RETB instruction is executed.
To return from a BRKCS RBn instruction service routine, a RETCSB !addr16 instruction is executed.
As an operand error interrupt is an interrupt generated if there is an error in an operand, processing is required
for branching to the initialization program by a reset release after the necessary processing has been performed, etc.
4.1.2 Non-maskable interrupt requests
A non-maskable interrupt request is generated when a valid edge is input to the NMI pin or when the watchdog
timer overflows. The provision of the NMI pin and watchdog timer functions varies from product to product. Please
refer to the User’s Manual — Hardware for the individual products for details.
Non-maskable interrupt requests are acknowledged unconditionally, even in the interrupt disabled (DI) state. Also,
they are not subject to interrupt priority control, and are of higher priority that any other interrupt.
4.1.3 Maskable interrupt requests
A maskable interrupt request is one subject to masking control according to the setting of the interrupt control
register. In addition, acknowledgment enabling/disabling can be set for all maskable interrupts by means of the IE
flag in the PSW.
The priority order for maskable interrupt requests when interrupt requests of the same priority are generated
simultaneously is predetermined (default priority). Also, multiprocessing can be performed with interrupt priorities
divided into 4 levels in accordance with the specification of the interrupt control register. However, macro service
requests are acknowledged without regard to priority control or the IE flag.
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CHAPTER 4 INTERRUPT FUNCTIONS
4.2 Interrupt Service Modes
4.2.1 Vectored interrupts
A branch is made to the service routine using the memory contents of the vector table address corresponding to
the interrupt source as the branch destination address.
The following operations are executed to enable the CPU to perform interrupt servicing.
• When branching: The CPU state (PC & PSW contents) is saved to the stack.
• When returning : CPU statuses (PC & PSW contents) are restored from the stack.
The return from the service routine to the main routine is performed by an RETI instruction (or an RETB instruction
in the case of a BRK instruction or operand error interrupt).
The branch destination address is restricted to the base area from 0000H to FFFFH.
Please refer to the User’s Manual — Hardware for the individual products for details of the vector table.
4.2.2 Context switching
The prescribed register bank is selected by hardware by generation of an interrupt request or execution of a BRKCS
RBn instruction. With this function, a branch is made to the vector address stored beforehand in the register bank,
and at the same time the contents of the program counter (PC) and program status word (PSW) are stacked in the
register bank.
The return from the service routine is performed by a RETCS !addr16 instruction (or an RETCSB !addr16 instruction
in the case of a BRKCS RBn instruction).
The branch destination address is restricted to the base area from 0000H to FFFFH.
Figure 4-1. Context Switching Operation by Interrupt Request Generation
Register bank
0000B
(0 to 7)
7 Transfer
Register bank n (n = 0 to 7)
PC19-PC16
PC15-PC0
A
B
X
C
6 Exchange
R5
R7
R4
R6
1 Save
(temporary
register
5 Save
bit 8 to 11)
V
U
T
VP
UP
3 Register bank
switching
(RBS0-RBS2←n)
Temporary register
D
H
E
L
4
RSS←0
IE←0
1 Save
PSW
W
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CHAPTER 4 INTERRUPT FUNCTIONS
4.2.3 Macro service function
In macro service, CPU execution is temporarily suspended when an interrupt is acknowledged, and the service
set by firmware is executed. Since macro service is performed without the intermediation of the CPU, it is not
necessary to save CPU statuses such as the PC and PSW contents. This is therefore very effective in improving
the CPU service time.
Please refer to the User’s Manual — Hardware for the individual products for details of macro service.
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CHAPTER 5 ADDRESSING
5.1 Instruction Address Addressing
The instruction address is determined by the contents of the program counter (PC), and is normally incremented
(by 1 for one byte) automatically in accordance with the number of bytes in the fetched instruction each time an
instruction is executed. However, when an instruction associated with a branch is executed, branch address
information is set in the PC and a branch performed by means of the addressing modes shown below.
The following kinds of instruction address addressing are provided:
• (8-bit/16-bit) relative addressing
• (11-bit/16-bit/20-bit) immediate addressing
• Table indirect addressing
• 16-bit register addressing
• 20-bit register addressing
• 16-bit register indirect addressing
• 20-bit register indirect addressing
Details of each kind of addressing are given in the following sections.
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CHAPTER 5 ADDRESSING
5.1.1 Relative addressing
[Function]
The value obtained by adding the 8-bit or 16-bit immediate data in the operation code (displacement value: jdisp8,
jdisp16) to the start address of the next instruction is transferred to the program counter (PC), and a branch is
made. The displacement value is treated as signed two’s complement data (–128 to +127, –32,768 to +32,767),
with the MSB as the sign bit.
This is performed when a CALL $!addr20, BR $!addr20, BR $addr20, or conditional branch instruction is executed
(only 8-bit immediate data can be used in a conditional branch instruction).
[Explanatory Diagrams]
8-bit relative addressing
19
0
0
. . . b = number of
instruction bytes
PC+b
+
19
8 7 6
S
X
jdisp8
↓
19
0
PC
When S = 0, all bits of x are 0
When S = 1, all bits of x are 1
16-bit relative addressing
19
0
0
. . . b = number of
instruction bytes
PC+b
+
19
S
jdisp16
↓
19
0
PC
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CHAPTER 5 ADDRESSING
5.1.2 Immediate addressing
[Function]
The immediate data in the instruction word is transferred to the program counter (PC), and a branch is made.
This is performed when a CALL !!addr20, BR !!addr20, CALL !addr16, BR !addr16, or CALLF !addr11 instruction
is executed.
In the case of a CALL !addr16 or BR !addr16 instruction (16-bit immediate addressing), the higher 4-bit address
is fixed at 0, and a branch is made to the base area. In the case of the CALLF !addr11 instruction, the higher 9-
bit address is fixed at 000000001.
[Explanatory Diagrams]
20-bit immediate addressing
7
0
CALL or BR
High addr.
Low addr.
Middle addr.
19
16 15
8 7
0
PC
16-bit immediate addressing
7
0
CALL or BR
Low addr.
Middle addr.
19
16 15
8 7
0
PC 0 0 0 0
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CHAPTER 5 ADDRESSING
11-bit immediate addressing
7
0
CALLF
faH
faL
19
11 10
8 7
0
PC
0 0 0 0 0 0 0 0 1
[Caution]
As the branch destination of the BR !addr16 instruction is restricted, it should only be used when using a
78K/0, 78K/I, 78K/II, or 78K/III Series program.
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CHAPTER 5 ADDRESSING
5.1.3 Table indirect addressing
[Function]
The specific location table contents (branch destination address) addressed by the immediate data in the lower
5 bits of the operation code are transferred to the lower 16 bits of the program counter (PC), 0000 is transferred
to the higher 4 bits, and a branch is made (the branch destination address is restricted to the base area).
This is performed when a CALLT [addr5] instruction is executed.
[Explanatory Diagram]
7
5 4
0
1 1 1
ta
0
Operation code
23
8 7 6 5
0
Effective
address =
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ta
0
Memory (Table)
Low addr.
Effective address
Effective address + 1
High addr.
19
0
16 15
8 7
0
PC
0 0 0
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CHAPTER 5 ADDRESSING
5.1.4 16-bit register addressing
[Function]
The contents of register rp (RP0 to RP7) specified by the instruction word are transferred to the lower 16 bits of
the program counter (PC), 0000 is transferred to the higher 4 bits, and a branch is made (the branch destination
address is restricted to the base area).
This is performed when a BR rp or CALL rp instruction is executed.
[Explanatory Diagrams]
7
0 7
0
0
rp
↓
19
0
16 15
0
8 7
PC
0 0
[Caution]
As the branch destination of the BR rp instruction is restricted, it should only be used when using a 78K/0,
78K/I, 78K/II, or 78K/III Series program.
If AX or BC is written for rp, with the NEC RA78K4 assembler the object code generated depends on the RSS
pseudo-instruction written immediately before. “1” should be specified by the RSS pseudo-instruction only when
a 78K/III Series program is used (see 3.1.3 Use of RSS bit).
5.1.5 20-bit register addressing
[Function]
The contents of register rg (RG4 to RG7) specified by the instruction word are transferred to the program counter
(PC), and a branch is made. The higher 4 bits of rg should be set to 0000.
This is performed when a BR rg or CALL rg instruction is executed.
[Explanatory Diagram]
7
4
0 7
0 7
0
0
0
0 0 0
↓
19
16 15
8 7
PC
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CHAPTER 5 ADDRESSING
5.1.6 16-bit register indirect addressing
[Function]
The 2 consecutive bytes of data in the memory addressed by the contents of register rp (RP0 to RP7) specified
by the instruction word are transferred to the lower 16 bits of the program counter (PC), 0000 is transferred to the
higher 4 bits, and a branch is made (the branch destination address is restricted to the base area).
This is performed when a BR [rp] or CALL [rp] instruction is executed.
[Explanatory Diagram]
7
0 7
0
0
rp
↓
23
0
16 15
0
8 7
Effective
address =
0
0 0 0 0 0
Memory
Low addr.
High addr.
Effective address
Effective address + 1
19
0
16 15
8 7
0
0
0 0
[Caution]
As the address that holds the branch destination address and the branch destination of the BR [rp] instruction are
restricted, it should only be used when using a 78K/III Series program.
If AX or BC is written for rp, with the NEC RA78K4 assembler the object code generated depends on the RSS
pseudo-instruction written immediately before. “1” should be specified by the RSS pseudo-instruction only when
a 78K/III Series program is used (see 3.1.3 Use of RSS bit).
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5.1.7 20-bit register indirect addressing
[Function]
The 3 consecutive bytes of data in the memory addressed by the contents of register rg (RP0 to RP7) specified
by the instruction word are transferred to the program counter (PC), and a branch is made. The higher 4 bits of
the 3-byte data stored in the memory should be set to 0000.
This is performed when a BR [rg] or CALL [rg] instruction is executed.
[Explanatory Diagram]
7
0 7
0 7
8 7
0
0
rg
↓
23
16 15
Effective
address =
Memory
Effective address
Low addr.
Effective address + 1
Effective address + 2
Middle addr.
0
0 0 0
High addr.
19
16 15
8 7
0
PC
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5.2 Operand Address Addressing
The following methods are available for specifying the register, memory, etc., to be manipulated when an instruction
is executed.
• Implied addressing
• Register addressing
• Immediate addressing
• 8-bit direct addressing
• 16-bit direct addressing
• 24-bit direct addressing
• Short direct addressing
• Special function register (SFR) addressing
• Short direct 16-bit memory indirect addressing
• Short direct 24-bit memory indirect addressing
• Stack addressing
• 24-bit register indirect addressing (including 24-bit register indirect addressing with auto-increment/auto-
decrement)
• 16-bit register indirect addressing
• Based addressing
• Indexed addressing
• Based indexed addressing
Details of each kind of addressing are given in the following sections.
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5.2.1 Implied addressing
[Function]
This type of addressing automatically addresses registers in the register bank specified by the register bank
selection flags (RBS2, RBS1, and RBS0).
Instructions that use implied addressing in the 78K/IV Series instruction word are shown below.
The A, AX, C, and B registers used by these instructions are affected by the RSS bit in the PSW. When RSS =
0, R1, RP0, R2, and R2, respectively are accessed for the A, AX, C, and B registers, and when RSS = 1, R5, RP2,
R6, and R7 are accessed. RSS should only be set to 1 when a 78K/III Series program is used (see 3.1.3 Use
of RSS bit).
Instruction
Registers Specified by Implied Addressing
A register as multiplicand, AX register as that holds product
AX register as multiplicand and register that holds higher 16 bits of product
AX register as register that holds dividend and quotient
MULU
MULUW, MULW
DIVUW
DIVUX
AXDE register as register that holds dividend and quotient
MACW, MACSW
AXDE register as register that holds result of sum of products operation, B and C registers as
pointer registers that specify data
ADJBA, ADJBS
CVTBW
A register as register that holds numeric value subject to decimal adjustment
A register as register that holds data before sign extension is performed, and AX register as
register that holds result of sign extension
CHKLA
A register as register that holds result of comparison between pin level and port output latch
A register as register that holds digit data subject to digit rotation (only lower 4 bits are used)
C register as data counter string instruction
ROR4, ROL4
SACW, string instruction
[Operand Format]
As this is used automatically according to the instruction, there is no specific operand format.
[Description Example]
MULU r; In an 8-bit x 8-bit multiplication instruction, the product of the A register and r register are stored in the
AX register. Here, the A and AX registers are specified by implied addressing.
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5.2.2 Register addressing
[Function]
This type of addressing accesses as an operand the general-purpose register specified by the register specification
code in the instruction word in the register bank specified by the register bank selection flag (RBS2, RBS1, RBS0).
Register addressing is performed when an instruction with one of the operand formats shown below is executed.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
Description Format
A
A
C
X
B
C
X
B
r
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
r1
r2
r3
AX
rp
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7
R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
V, U, T, W
AX
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)
AX(RP0), BC(RP1), RP2, RP3
rp1
rp2
WHL
rg
VP(RP4), UP(RP5), DE(RP6), HL(RP7)
WHL
VVP(RG4), UUP(RG5), TDE(RG6), WHL(RP7)
Remarks 1. Absolute names are shown in parentheses.
2. With an instruction (such as ADDW AX, #word) in which A, X, AX, B, or C is specified directly as
the register addressing operand, the register used as A, X, AX, B, or C is determined by the RSS
bit in the PSW when the instruction is executed. The RSS bit in the PSW should be set to “1” only
when a 78K/III Series program is used (see 3.1.3 Use of RSS bit).
3. If A, X, B, C, AX, or BC is written as an operand in an instruction in which r, r1, rp, or rp1 is specified
as the register addressing operand, with the NEC RA78K4 assembler the object code generated
depends on the RSS pseudo-instruction written immediately before. “1” should be specified in the
RSS pseudo-instruction operand only when a 78K/III Series program is used (see 3.1.3 Use of RSS
bit).
[Description Example 1]
• General example
MOV A, r
• Specific example
MOV A, C ; When the C register is selected as r
[Description Example 2]
• General example
INCW rp
• Specific example
INCW DE ; When the DE register pair is selected as rp
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5.2.3 Immediate addressing
[Function]
This type of addressing has 8-bit data, 16-bit data and 24-bit data subject to manipulation in the operation code.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
byte
Description Format
Label or 8-bit immediate data
Label or 16-bit immediate data
Label or 24-bit immediate data
word
imm24
[Description Example]
• General example
ADD A, #byte
• Specific example
ADD A, #77H ; When 77H is used as byte
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5.2.4 8-bit direct addressing
[Function]
With this kind of addressing, the immediate data in the instruction word is the operand address and the memory
to be manipulated is addressed. It is used with the MOVTBLW instruction. Memory from 0FE00H to 0FEFFH is
addressed when a LOCATION 0H instruction is executed, and memory from 0FFE00H to 0FFEFFH when a
LOCATION 0FH instruction is executed.
[Operand Format]
Performed when an instruction with the operands shown below is executed.
Identifier
!addr8
Description Format
Note
Label, or immediate data 0FE00H to 0FEFFH
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed, the
range is 0FFE00H to 0FFEFFH.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
[Description Examples]
• General example
MOVTBLW !addr8, n
• Specific example
MOVTBLW !0FE24H, n; When FE24H is used as addr8
[Explanatory Diagram]
7
0
OP code
Low addr.
Memory
23
0
16 15
8 7
0
Effective
address
→
0
0
0
L
1 1 1 1 1 1 1 0
Remark L depends on the LOCATION instruction.
• When LOCATION 0H instruction is executed : 0000
• When LOCATION 0FH instruction is executed : 1111
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5.2.5 16-bit direct addressing
[Function]
This type of addressing addresses memory subject to manipulation with the immediate data in the instruction word
as the operand address. The base area can be addressed.
[Operand Format]
Performed when an instruction with the operand format shown below is executed.
Identifier
addr16
Description Format
Label or 16-bit immediate data
[Description Example]
• General example
MOV A, !addr16
• Specific example
MOV A, !0FE00H ; When FE00H is used as addr16
[Explanatory Diagram]
7
0
OP code
Low addr.
Middle addr.
Base area memory
23
16 15
0
8 7
0
Effective
address
→
0
0 0 0 0 0 0
[Remarks]
This kind of addressing should only be used when it is absolutely essential to reduce the execution time or object
size, or when 78K/0, 78K/I, 78K/II, or 78K/III Series software is used and program amendment is difficult.
Amendments may be necessary in order to make further use of a program that uses this kind of addressing.
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5.2.6 24-bit direct addressing
[Function]
This type of addressing addresses memory subject to manipulation with the immediate data in the instruction word
as the operand address. The entire memory space can be addressed.
[Operand Format]
Performed when an instruction with the operand format shown below is executed.
Identifier
addr24
Description Format
Label or 24-bit immediate data
[Description Example]
• General example
MOV A, !!addr24
• Specific example
MOV A, !!54FE00H ; When 54FE00H is used as addr24
[Explanatory Diagram]
7
0
OP code
High addr.
Low addr.
Middle addr.
Memory
23
16 15
8 7
0
Effective
address
→
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5.2.7 Short direct addressing
[Function]
This type of addressing directly addresses memory subject to manipulation in a fixed space with the 8-bit immediate
data in the instruction word. This kind of addressing can be used with most instructions, and allows various kinds
of data to be manipulated using a small number of bytes and small number of clocks.
With short direct addressing, the applicable address range varies according to the LOCATION instruction in the
same way as the internal data area location addresses. When a LOCATION 0H instruction is executed, internal
RAM from 0FD20H to 0FEFFH and special function registers (SFRs) from 0FF00H to 0FF1FH can be accessed.
When a LOCATION 0FH instruction is executed, internal RAM from 0FFD20H to 0FFEFFH and SFRs from
0FFF00H to 0FFF1FH can be accessed.
Ports frequently accessed in the program, timer/counter unit compare registers and capture registers are mapped
onto the SFR area on which short direct addressing is used. These special function registers can be manipulated
using a small number of bytes and small number of clocks.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
saddr
Description Format
Label or immediate data 0FD20H to 0FF1FH
saddr1
saddr2
saddrp
saddrp1
saddrp2
Label or immediate data 0FE00H to 0FEFFH
Label or immediate data 0FD20H to 0FDFFH and 0FF00H to 0FF1FH
Label or immediate data 0FD20H to 0FF1EH
Label or immediate data 0FE00H to 0FEFEH
Label or immediate data 0FD20H to 0FDFFH and 0FF00H to 0FF1EH
(If 0FDFFH is specified, the higher byte is 0FE00H)
saddrg
Label or immediate data 0FD20H to 0FEFDH
saddrg1
saddrg2
Label or immediate data 0FE00H to 0FEFDH (during 24-bit manipulation)
Label or immediate data 0FD20H to 0FDFFH (during 24-bit manipulation)
Remark The addresses in this table are those that apply when the LOCATION 0H instruction is executed.
When the LOCATION 0FH instruction is executed, F0000H should be added to the values shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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[Description Example]
• General example
MOV saddr, saddr
•
Specific example
MOV 0FE30H, 0FE50H
[Explanatory Diagram]
7
0
OP code
Saddr–offset
Short direct memory
23
2019 16 15
10 9 8 7
0
Effective
address
→
0 0 0 0 1 1 1 1 1 1
L
X
Remark L depends on the LOCATION instruction.
• When LOCATION 0H instruction is executed : 0000
• When LOCATION 0FH instruction is executed : 1111
X is determined by the op code information and the value of Saddr-offset.
• When saddr1 is specified by op code: 10
• When saddr2 is specified by op code and Saddr-offset is 20H to FFH: 01
• When saddr2 is specified by op code and Saddr-offset is 00H to 1FH: 11
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5.2.8 Special function register (SFR) addressing function
[Function]
This type of addressing addresses memory-mapped special function registers (SFRs) with the 8-bit immediate data
in the instruction word.
The space used by this kind of addressing varies according to the LOCATION instruction in the same way as the
internal data area location addresses. When a LOCATION 0H instruction is executed, it is the 256-byte space
from 0FF00H to 0FFFFH, and when a LOCATION 0FH instruction is executed, it is the 256-byte space from
0FFF00H to 0FFFFFH. However, SFRs mapped onto 0FF00H to 0FF1FH (when the LOCATION 0H instruction
is executed; 0FFF00H to 0FFF1FH accessed by short direct addressing.
Remarks 1. With the NEC assembler package (RA78K4), short direct addressing is automatically (forcibly) used
for instructions on SFRs in addresses that can be accessed by short direct addressing.
2. The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
Description Format
sfr
Special function register name
Name of special function register for which 16-bit operation is possible
sfrp
[Description Example]
• General example
MOV sfr, A
• Specific example
MOV PM0, A ; When PM0 is specified as sfr
[Explanatory Diagram]
7
0
OP code
Sfr–offset
SFR
23
16 15
8 7
0
Effective
address
0 0 0 0
L
1 1 1 1 1 1 1 1
Remark L depends on the LOCATION instruction.
• When LOCATION 0H instruction is executed : 0000
• When LOCATION 0FH instruction is executed : 1111
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5.2.9 Short direct 16-bit memory indirect addressing
[Function]
This type of addressing addresses base area memory subject to manipulation with the contents of the two
consecutive bytes of short direct memory addressed by the lower 16 bits of the operand address and the higher
8 bits of the operand address set to 00000000.
This addressing is used when an instruction with [saddrp] in an operand is executed.
[Operand Format]
Performed when an instruction with the operand format shown below is executed.
Identifier
[saddrp]
Description Format
Note
[Label, immediate data FD20H to FEFEH
]
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, the
range is FFD20H to FFEFEH.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
[Description Example]
• General example
XCH A, [saddrp]
• Specific example
XCH A, [0FEA0H] ; When memory indicated by 2-byte data in addresses 0FEA0H and 0FEA1H is specified
[Explanatory Diagram]
7
0
OP code
Saddr–offset
Short direct addressing
Short direct memory
7
0
Low addr.
High addr.
Memory
23
1615
0
8 7
0
Effective
address
0
0 0 0 0 0 0
[Remarks]
This kind of addressing should only be used when it is absolutely essential to reduce the execution time or object
size, or when 78K/0, 78K/I, 78K/II, or 78K/III Series software is used and program amendment is difficult.
Amendments may be necessary in order to make further use of a program that uses this kind of addressing.
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5.2.10 Short direct 24-bit memory indirect addressing
[Function]
This type of addressing addresses memory subject to manipulation with the contents of the 3 consecutive bytes
of short direct memory addressed by the 8-bit immediate data in the instruction word as the operand address.
This addressing is used when an instruction with [%saddrg] in an operand is executed.
[Operand Format]
Performed when an instruction with the operand format shown below is executed.
Identifier
[%saddrg]
Description Format
Note
[%label, immediate data FD20H to FEFDH
]
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed, the
range is 0FFD20H to 0FFEFDH.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
[Description Example]
• General example
XCH A, [%saddrg]
• Specific example
XCH A, [%0FEA0H] ; When memory indicated by 3-byte data in addresses 0FEA0H, 0FEA1H and 0FEA2H is
specified
[Explanatory Diagram]
7
0
OP code
Saddr–offset
Short direct addressing
Short direct memory
7
0
Low addr.
Middle addr.
High addr.
Memory
23
1615
8 7
0
Effective
address
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CHAPTER 5 ADDRESSING
5.2.11 Stack addressing
[Function]
This type of addressing indirectly addresses the stack area in accordance with the contents of the stack pointer
(SP) and user stack pointer (UUP).
The SP is used automatically when a PUSH or POP instruction is executed, when register saving/restoration is
performed as the result of interrupt request generation, and when a subroutine call or return instruction is executed.
The UUP is used automatically when a PUSHU or POPU instruction is executed.
[Description Example]
PUSH DE ; When the contents of the DE register are saved to the stack using a PUSH instruction When this
instruction is executed, the SP is automatically decremented (by 2) and the contents of the DE register
are saved to the stack.
[Explanatory Diagram]
Stack area
SP
↓
D register contents
E register contents
SP–1
↓
SP–2
SP←SP–2
Caution With stack addressing, the entire 16 MB space can be accessed but a stack area cannot be
reserved in the SFR area or internal ROM area.
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5.2.12 24-bit register indirect addressing
[Function]
This type of addressing addresses the memory to be manipulated with the contents of register rg (RG4 to RG7)
specified by the register pair specification code in the instruction word in the register bank specified by the register
bank selection flag (RBS2, RBS1, RBS0) as the operand address. The entire memory space can be addressed.
In addition, register indirect addressing with auto-increment that increments (+1/+2/+3) the register for which an
address specification was made after instruction execution and register indirect addressing with auto-decrement
that decrements (–1/–2/–3) the register after instruction execution are provided. The increment and decrement
values are determined by the size of data manipulated.
This type of addressing is ideal for consecutive processing of multiple items of data.
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
mem
Description Format
[TDE], [WHL], [TDE+], [WHL+], [TDE–], [WHL–], [VVP], [UUP]
[TDE], [WHL], [TDE+], [TDE–]
mem1
mem2
mem3
[TDE], [WHL]
[TDE], [WHL], [VVP], [UUP]
Remark “+” after register name: With auto-increment
“–” after register name: With auto-decrement
[Description Example]
• General example
MOV A, mem
• Specific example
ADD A, [TDE] ; When [TDE] is specified as mem
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[Explanatory Diagram]
24-bit register indirect addressing
23
rg
0
0
Memory
↓
23
Effective
address
Register indirect addressing with auto-increment/decrement
23
rg
0
+/–
1/2/3
Memory
23
0
Effective
address
Remark +/–
+ : With auto-increment
– : With auto-decrement
1/2/3
1 : When data size is 1 byte
2 : When data size is 2 bytes (1 word)
3 : When data size is 3 bytes
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5.2.13 16-bit register indirect addressing
[Function]
This type of addressing addresses the memory to be manipulated with the contents of register rp (RP0 to RP3)
specified by the register specification code in the instruction word in the register bank specified by the register
bank selection flag (RBS2, RBS1, RBS0) as the operand address. The base area memory space can be addressed.
This type of addressing is only used with the ROR4 and ROL4 instructions, and is used when processing multiple
consecutive bytes of BCD data.
This addressing is provided to maintain compatibility with the 78K/III Series, and should only be used when using
a 78K/III Series program.
[Operand Format]
Performed when an instruction with the operand format shown below is executed.
Identifier
mem3
Description Format
[AX], [BC], [RP2], [RP3]
[Description Example]
• General example
ROR4 mem3
• Specific example
ROR4 [BC] ; When [BC] is written as mem3
[Explanatory Diagram]
15
rp
0
0
Memory
↓
23
1615
0
Effective
address
0
0 0 0 0 0 0
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5.2.14 Based addressing
[Function]
With this type of addressing, register rg (RG4 to RG7) specified by the register specification code in the instruction
word or the stack pointer (SP) in the register bank specified by the register bank selection flag (RBS2, RBS1, RBS0)
addressed with the result of adding 8-bit immediate data to addition is performed with the offset data extended
to 24 bits as a positive number. A carry from the 24th bit is ignored.
The entire memory space can be addressed.
This type of addressing is used when specific data is specified in an array in which one record consists of a number
of bytes of data.
MOV A, [WHL+2H]
Record start address→
WHL + 2 manipulated with WHL
as record start address
WHL+2→
WHL→
One record of array
Record start address→
: Specific data in each record
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
mem
mem1
Description Format
[TDE + byte], [WHL + byte], [SP + byte], [VVP + byte], [UUP + byte]
[TDE + byte], [WHL + byte], [SP + byte], [VVP + byte], [UUP + byte]
[Description Example]
• General example
AND A, mem
• Specific example
AND A, [TDE+10H] ; When based addressing using the sum of register TDE as mem and 10H is selected
[Explanatory Diagram]
23
0
0
0
rg
+
7
8-bit offset data
Memory
↓
23
Effective
address
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5.2.15 Indexed addressing
[Function]
With this type of addressing, the 24-bit address data written as the operand in the instruction word is used as the
index, and memory is addressed with the result of adding the contents of the register specified in the instruction
word in the register bank specified by the register bank selection flag (RBS2, RBS1, RBS0) to this value. The
addition is performed with the register carry from the 24th bit is ignored.
The entire memory space can be addressed.
This type of addressing is used for table data reads, etc.
The A and B registers used in this addressing vary according to the value of the RSS bit in the PSW. When RSS
= 0, these registers are R1 and R3 respectively, and when RSS = 1 they are R5 and R7. RSS should only be
set to 1 when using a 78K/III Series program.
TABLE+4→
←TABLE [A], when A = 3H :
Manipulation of A'th data
item in table by TABLE [A]
TABLE+3→
TABLE+2→
TABLE+1→
TABLE
→
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
mem
mem1
Description Format
imm24[A], imm24[B], imm24[DE], imm24[HL]
imm24[A], imm24[B], imm24[DE], imm24[HL]
[Description Example]
• General example
ADDC A, mem
• Specific example
ADDC A, 4010H[DE] ; When indexed addressing using the sum of register DE as mem and 04010H is selected
[Explanatory Diagram]
23
0
0
0
Index address
Register
+
15/7Note
Memory
↓
23
Effective
address
Note 15 : When register is DE or HL
7 : When register is A or B
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5.2.16 Based indexed addressing
[Function]
With this type of addressing, the register specified by the register specification code in the instruction word in the
register bank specified by the register bank selection flag (RBS2, RBS1, RBS0) is used as the base register, and
memory is addressed with the result of adding the value of a register specified in the same way to the contents
of this base register as offset data. The addition is performed with the offset data extended to 24 bits as a positive
number. A carry from the 24th bit is ignored.
The entire memory space can be addressed.
This type of addressing is used to specify in order data in an array in which one record consists of a number of
bytes of data.
The A, B, and C registers used in this addressing vary according to the value of the RSS bit in the PSW. When
RSS = 0, these registers are R1, R3, and R2 respectively, and when RSS = 1 they are R5, R7, and R6. RSS should
only be set to 1 when using a 78K/III Series program.
MOV A, [WHL+C]
Record start address→
WHL+C→
WHL→
WHL + C manipulated with WHL
as record start address (When C = 2)
One record of array
Record start address→
: Specific data in each record
[Operand Format]
Performed when an instruction with one of the operand formats shown below is executed.
Identifier
mem
mem1
Description Format
[TDE + A], [TDE + B], [TDE + C], [WHL + A], [WHL + B], [WHL + C], [VVP + DE], [VVP + HL]
[TDE + A], [TDE + B], [TDE + C], [WHL + A], [WHL + B], [WHL + C], [VVP + DE], [VVP + HL]
[Description Example]
• General example
AND A, mem
• Specific example
AND A, [TDE+B] ; When based addressing using the sum of register TDE as mem and register B is selected
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[Explanatory Diagram]
23
0
Base register
+
15/7Note
0
0
Offset register
Memory
↓
23
Effective
address
Note 15 : When register is DE or HL
7 : When register is A, B or C
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CHAPTER 6 INSTRUCTION SET
This chapter shows the 78K/IV Series instruction set.
6.1 Legend
(1) Operand identifiers and descriptions (1/2)
Identifier
Description Format
Note 1
r, r’
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7
Note 1
r1
r2
R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
V, U, T, W
r3
Note 2
rp, rp’
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)
AX(RP0), BC(RP1), RP2, RP3
Note 2
rp1
rp2
VP(RP4), UP(RP5), DE(RP6), HL(RP7)
rg, rg’
sfr
VVP(RG4), UUP(RG5), TDE(RG6), WHL(RG7)
Special function register symbol (see Special Function Register Application Table)
Special function register symbol (register for which 16-bit operation is possible: see Special Function
Register Application Table)
sfrp
Note 2
post
Multiple descriptions of AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5)/PSW, DE(RP6) and HL(RP7)
are permissible. However, UP is only used with PUSH/POP instructions, and PSW with PUSHU/POPU
instructions.
mem
[TDE], [WHL], [TDE +], [WHL +], [TDE –], [WHL –], [VVP], [UUP]: Register indirect addressing
[TDE + byte], [WHL + byte], [SP + byte], [UUP + byte], [VVP + byte]: Based addressing
imm24[A], imm24[B], imm24[DE], imm24[HL]: Indexed addressing
[TDE + A], [TDE + B], [TDE + C], [WHL + A], [WHL + B], [WHL + C], [VVP + DE], [VVP + HL]: Based
indexed addressing
mem1
mem2
All with [WHL +], [WHL –] excluded from mem
[TDE], [WHL]
mem3
[AX], [BC], [RP2], [RP3], [VVP], [UUP], [TDE], [WHL]
Notes 1. Setting the RSS bit to 1 enables R4 to R7 to be used as X, A, C, and B, but this function should only
be used when using a 78K/III Series program.
2. Setting the RSS bit to 1 enables RP2 and RP3 to be used as AX and BC, but this function should only
be used when using a 78K/III Series program.
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(1) Operand identifiers and descriptions (2/2)
Identifier
Description Format
Note
saddr, saddr’
saddr1, saddr1’
saddr2, saddr2’
saddrp
FD20H to FF1FH immediate data or label
FE00H to FEFFH immediate data or label
FD20H to FDFFH, FF00H to FF1FH immediate data or label
FD20H to FF1EH immediate data or label (16-bit operation)
FE00H to FEFEH immediate data or label (16-bit operation)
FD20H to FDFFH, FF00H to FF1EH immediate data or label (16-bit operation)
FD20H to FEFDH immediate data or label (24-bit operation)
FE00H to FEFDH immediate data or label (24-bit operation)
FD20H to FDFFH immediate data or label (24-bit operation)
saddrp1
saddrp2
saddrg
saddrg1
saddrg2
addr24
addr20
addr16
addr11
addr8
0H to FFFFFFH immediate data or label
0H to FFFFFH immediate data or label
0H to FFFFH immediate data or label
800H to FFFH immediate data or label
Note
0FE00H to 0FEFFH
immediate data or label
addr5
40H to 7EH immediate data or label
imm24
word
byte
bit
24-bit immediate data or label
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data
n
locaddr
00H or 0FH
Note The addresses shown here apply when 00H is specified by the LOCATION instruction.
When 0FH is specified by the LOCATION instruction, F0000H should be added to the address values shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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(2) Operand column symbols
Symbol
Description
+
–
Auto-increment
Auto-decrement
Immediate data
#
!
16-bit absolute address
24-bit/20-bit absolute address
8-bit relative address
16-bit relative address
Bit inversion
!!
$
$!
/
[ ]
Indirect addressing
[% ]
24-bit indirect addressing
(3) Flag column symbols
Symbol
Description
(Blank)
No change
0
1
x
Cleared to 0
Set to 1
Set or cleared depending on result
P/V flag operates as parity flag
P/V flag operates as overflow flag
P
V
R
Previously saved value is restored
(4) Operation field symbols
Symbol
Description
jdisp8
Signed two’s complement data (8 bits) indicating relative address distance between start address of next
instruction and branch address
jdisp16
Signed two’s complement data (16 bits) indicating relative address distance between start address of next
instruction and branch address
PC bits 16 to 19
PCHW
PCLW
PC bits 0 to 15
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(5) Number of bytes of instruction that includes mem in operands
mem Mode
Register Indirect Addressing
Based
Indexed
Based Indexed
Addressing
Addressing
Addressing
Note
Number of bytes
1
2
3
5
2
Note One-byte instruction only when [TDE], [WHL], [TDE +], [TDE –], [WHL +], or [WHL –] is written as mem in
a MOV instruction
.
(6) Number of bytes of instruction that includes saddr, saddrp, r or rp in operands
In some instructions which include saddr, saddrp, r, rp as operands, the number of bytes is written divided
into two with “/”. Which number of bytes is to be used depends on the table below.
Identifier
saddr
saddrp
r
Number of Bytes: Left Side
Number of Bytes: Right Side
saddr2
saddrp2
r1
saddr1
saddrp1
r2
rp
rp1
rp2
(7) Description of instructions that include mem in operands and string instructions
Operands TDE, WHL, VVP, and UUP (24-bit registers) can also be written as DE, HL, VP, and UP respectively.
However, they are still treated as TDE, WHL, VVP, and UUP (24-bit registers) when written as DE, HL, VP,
and UP.
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6.2 List of Instruction Operations
(1) 8-bit data transfer instruction: MOV
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MOV
r, #byte
2/3
3/4
3
r ← byte
saddr, #byte
sfr, #byte
!addr16, #byte
!!addr24, #byte
r, r’
(saddr) ← byte
sfr ← byte
5
(addr16) ← byte
(addr24) ← byte
r ← r’
6
2/3
1/2
2
A, r
A ← r
A, saddr2
r, saddr
A ← (saddr2)
r ← (saddr)
(saddr2) ← A
(saddr) ← r
A ← sfr
3
saddr2, A
saddr, r
2
3
A, sfr
2
r, sfr
3
r ← sfr
sfr, A
2
sfr ← A
sfr, r
3
sfr ← r
saddr, saddr’
r, !addr16
!addr16, r
r, !!addr24
!!addr24, r
A, [saddrp]
A, [%saddrg]
A, mem
4
(saddr) ← (saddr’)
r ← (addr16)
(addr16) ← r
r ← (addr24)
(addr24) ← r
A ← ((saddrp))
A ← ((saddrg))
A ← (mem)
((saddrp)) ← A
((saddrg)) ← A
(mem) ← A
PSWL ← byte
PSWH ← byte
PSWL ← A
PSWH ← A
A ← PSWL
A ← PSWH
r3 ← byte
4
4
5
5
2/3
3/4
1-5
2/3
3/4
1-5
3
[saddrp], A
[%saddrg], A
mem, A
PSWL, #byte
PSWH, #byte
PSWL, A
PSWH, A
A, PSWL
A, PSWH
r3, #byte
A, r3
×
×
×
×
×
×
×
×
×
×
3
2
2
2
2
3
2
A ← r3
r3, A
2
r3 ← A
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(2) 16-bit data transfer instruction: MOVW
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MOVW
rp, #word
3
rp ← word
saddrp, #word
sfrp, #word
!addr16, #word
!!addr24, #word
rp, rp’
4/5
4
(saddrp) ← word
sfrp ← word
6
(addr16) ← word
(addr24) ← word
rp ← rp’
7
2
AX, saddrp2
rp, saddrp
2
AX ← (saddrp2)
rp ← (saddrp)
(saddrp2) ← AX
(saddrp) ← rp
AX ← sfrp
3
saddrp2, AX
saddrp, rp
2
3
AX, sfrp
2
rp, sfrp
3
rp ← sfrp
sfrp, AX
2
sfrp ← AX
sfrp, rp
3
sfrp ← rp
saddrp, saddrp’
rp, !addr16
!addr16, rp
rp, !!addr24
!!addr24, rp
AX, [saddrp]
AX, [%saddrg]
AX, mem
4
(saddrp) ← (saddrp’)
rp ← (addr16)
(addr16) ← rp
rp ← (addr24)
(addr24) ← rp
AX ← ((saddrp))
AX ← ((saddrg))
AX ← (mem)
((saddrp)) ← AX
((saddrg)) ← AX
(mem) ← AX
4
4
5
5
3/4
3/4
2-5
3/4
3/4
2-5
[saddrp], AX
[%saddrg], AX
mem, AX
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(3) 24-bit data transfer instruction: MOVG
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MOVG
rg, #imm24
5
rg ← imm24
rg, rg’
2
5
rg ← rg’
rg, !!addr24
!!addr24, rg
rg, saddrg
rg ← (addr24)
(addr24) ← rg
rg ← (saddrg)
(saddrg) ← rg
WHL ← ((saddrg))
((saddrg)) ← WHL
WHL ← (mem1)
(mem1) ← WHL
5
3
saddrg, rg
3
WHL, [%saddrg]
[%saddrg], WHL
WHL, mem1
mem1, WHL
3/4
3/4
2-5
2-5
(4) 8-bit data exchange instruction: XCH
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
XCH
r, r’
A, r
2/3
1/2
2
r ↔ r’
A ↔ r
A, saddr2
r, saddr
A ↔ (saddr2)
r ↔ (saddr)
r ↔ sfr
3
r, sfr
3
saddr, saddr’
r, !addr16
r, !!addr24
A, [saddrp]
A, [%saddrg]
A, mem
4
(saddr) ↔ (saddr’)
r ↔ (addr16)
r ↔ (addr24)
A ↔ ((saddrp))
A ↔ ((saddrg))
A ↔ (mem)
4
5
2/3
3/4
2-5
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(5) 16-bit data exchange instruction: XCHW
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
XCHW
rp, rp’
2
rp ↔ rp’
AX, saddrp2
rp, saddrp
2
3
AX ↔ (saddrp2)
rp ↔ (saddrp)
rp ↔ sfrp
rp, sfrp
3
AX, [saddrp]
AX, [%saddrg]
AX, !addr16
AX, !!addr24
saddrp, saddrp’
3/4
3/4
4
AX ↔ ((saddrp))
AX ↔ ((saddrg))
AX ↔ (addr16)
AX ↔ (addr24)
(saddrp) ↔ (saddrp’)
5
4
AX, mem
2-5
AX ↔ (mem)
(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, CMP, AND, OR, XOR
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
ADD
A, #byte
2
3
A, CY ← A + byte
r, CY ← r + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr), CY ← (saddr) + byte
sfr, CY ← sfr + byte
2/3
2
r, CY ← r + r’
A, saddr2
r, saddr
A, CY ← A + (saddr2)
r, CY ← r + (saddr)
3
saddr, r
3
(saddr), CY ← (saddr) + r
r, CY ← r + sfr
r, sfr
3
sfr, r
3
sfr, CY ← sfr + r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) + (saddr’)
A, CY ← A + ((saddrp))
A, CY ← A + ((saddrg))
((saddrp)), CY ← ((saddrp)) + A
((saddrg)), CY ← ((saddrg)) + A
A, CY ← A + (addr16)
A, CY ← A + (addr24)
(addr16), CY ← (addr16) + A
(addr24), CY ← (addr24) + A
A, CY ← A + (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) + A
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Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
ADDC
A, #byte
2
A, CY ← A + byte + CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
3
3/4
4
r, CY ← r + byte + CY
saddr, #byte
sfr, #byte
r, r’
(saddr), CY ← (saddr) + byte + CY
sfr, CY ← sfr + byte + CY
2/3
2
r, CY ← r + r’ + CY
A, saddr2
r, saddr
A, CY ← A + (saddr2) + CY
r, CY ← r + (saddr) + CY
3
saddr, r
3
(saddr), CY ← (saddr) + r + CY
r, CY ← r + sfr + CY
r, sfr
3
sfr, r
3
sfr, CY ← sfr + r + CY
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) + (saddr’) + CY
A, CY ← A + ((saddrp)) + CY
A, CY ← A + ((saddrg)) + CY
((saddrp)), CY ← ((saddrp)) + A + CY
((saddrg)), CY ← ((saddrg)) + A + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (addr24) + CY
(addr16), CY ← (addr16) + A + CY
(addr24), CY ← (addr24) + A + CY
A, CY ← A + (mem) + CY
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) + A + CY
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Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
SUB
A, #byte
2
A, CY ← A – byte
r, CY ← r – byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
3
3/4
4
saddr, #byte
sfr, #byte
r, r’
(saddr), CY ← (saddr) – byte
sfr, CY ← sfr – byte
2/3
2
r, CY ← r – r’
A, saddr2
r, saddr
A, CY ← A – (saddr2)
r, CY ← r – (saddr)
3
saddr, r
3
(saddr), CY ← (saddr) – r
r, CY ← r – sfr
r, sfr
3
sfr, r
3
sfr, CY ← sfr – r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) – (saddr’)
A, CY ← A – ((saddrp))
A, CY ← A – ((saddrg))
((saddrp)), CY ← ((saddrp)) – A
((saddrg)), CY ← ((saddrg)) – A
A, CY ← A – (addr16)
A, CY ← A – (addr24)
(addr16), CY ← (addr16) – A
(addr24), CY ← (addr24) – A
A, CY ← A – (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) – A
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Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
SUBC
A, #byte
2
A, CY ← A – byte – CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
3
3/4
4
r, CY ← r – byte – CY
saddr, #byte
sfr, #byte
r, r’
(saddr), CY ← (saddr) – byte – CY
sfr, CY ← sfr – byte – CY
2/3
2
r, CY ← r – r’ – CY
A, saddr2
r, saddr
A, CY ← A – (saddr2) – CY
r, CY ← r – (saddr) – CY
3
saddr, r
3
(saddr), CY ← (saddr) – r – CY
r, CY ← r – sfr – CY
r, sfr
3
sfr, r
3
sfr, CY ← sfr – r – CY
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) – (saddr’) – CY
A, CY ← A – ((saddrp)) – CY
A, CY ← A – ((saddrg)) – CY
((saddrp)), CY ← ((saddrp)) – A – CY
((saddrg)), CY ← ((saddrg)) – A – CY
A, CY ← A – (addr16) – CY
A, CY ← A – (addr24) – CY
(addr16), CY ← (addr16) – A – CY
(addr24), CY ← (addr24) – A – CY
A, CY ← A – (mem) – CY
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) – A – CY
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Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
CMP
A, #byte
2
A – byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
3
3/4
4
r – byte
saddr, #byte
sfr, #byte
r, r’
(saddr) – byte
sfr – byte
2/3
2
r – r’
A, saddr2
r, saddr
A – (saddr2)
r – (saddr)
(saddr) – r
r – sfr
3
saddr, r
3
r, sfr
3
sfr, r
3
sfr – r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) – (saddr’)
A – ((saddrp))
A – ((saddrg))
((saddrp)) – A
((saddrg)) – A
A – (addr16)
A – (addr24)
(addr16) – A
(addr24) – A
A – (mem)
(mem) – A
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
User’s Manual U10905EJ8V1UM
177
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
AND
A, #byte
2
A ← A
r ← r
byte
byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
3
3/4
4
saddr, #byte
sfr, #byte
r, r’
(saddr) ← (saddr)
byte
sfr ← sfr
r ← r
byte
2/3
2
r’
A, saddr2
r, saddr
A ← A
r ← r
(saddr2)
3
(saddr)
saddr, r
3
(saddr) ← (saddr)
r
r, sfr
3
r ← r
sfr
sfr, r
3
sfr ← sfr
r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr)
(saddr’)
3/4
3/4
3/4
3/4
4
A ← A
A ← A
((saddrp))
((saddrg))
((saddrp)) ← ((saddrp))
((saddrg)) ← ((saddrg))
A
A
A ← A
A ← A
(addr16)
(addr24)
5
4
(addr16) ← (addr16)
(addr24) ← (addr24)
A
A
5
2-5
2-5
A ← A
(mem)
mem, A
(mem) ← (mem)
A
178
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
OR
A, #byte
2
A ← A
r ← r
byte
byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
3
3/4
4
saddr, #byte
sfr, #byte
r, r’
(saddr) ← (saddr)
byte
sfr ← sfr
byte
2/3
2
r ← r
A ← A
r ← r
r’
A, saddr2
r, saddr
(saddr2)
(saddr)
3
saddr, r
3
(saddr) ← (saddr)
r
r, sfr
3
r ← r
sfr
sfr, r
3
sfr ← sfr
r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr)
(saddr’)
3/4
3/4
3/4
3/4
4
A ← A
A ← A
((saddrp))
((saddrg))
((saddrp)) ← ((saddrp))
((saddrg)) ← ((saddrg))
A
A
A ← A
A ← A
(saddr16)
(saddr24)
5
4
(addr16) ← (addr16)
(addr24) ← (addr24)
A
A
5
2-5
2-5
A ← A
(mem)
mem, A
(mem) ← (mem)
A
User’s Manual U10905EJ8V1UM
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CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
XOR
A, #byte
2
A ← A
r ← r
byte
byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
3
3/4
4
saddr, #byte
sfr, #byte
r, r’
(saddr) ← (saddr)
byte
sfr ← sfr
r ← r
byte
2/3
2
r’
A, saddr2
r, saddr
A ← A
r ← r
(saddr2)
3
(saddr)
saddr, r
3
(saddr) ← (saddr)
r
r, sfr
3
r ← r
sfr
sfr, r
3
sfr ← sfr
r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr)
(saddr’)
3/4
3/4
3/4
3/4
4
A ← A
A ← A
((saddrp))
((saddrg))
((saddrp)) ← ((saddrp))
((saddrg)) ← ((saddrg))
A
A
A ← A
A ← A
(addr16)
(addr24)
5
4
(addr16) ← (addr16)
(addr24) ← (addr24)
A
A
5
2-5
2-5
A ← A
(mem)
mem, A
(mem) ← (mem)
A
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User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(7) 16-bit operation instructions: ADDW, SUBW, CMPW
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
ADDW
AX, #word
3
AX, CY ← AX + word
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
rp, #word
rp, rp’
4
2
rp, CY ← rp + word
rp, CY ← rp + rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX, CY ← AX + (saddrp2)
rp, CY ← rp + (saddrp)
(saddrp), CY ← (saddrp) + rp
rp, CY ← rp + sfrp
sfrp, CY ← sfrp + rp
(saddrp), CY ← (saddrp) + word
sfrp, CY ← sfrp + word
(saddrp), CY ← (saddrp) + (saddrp’)
AX, CY ← AX – word
rp, CY ← rp – word
rp, CY ← rp – rp’
3
3
3
sfrp, rp
3
saddrp, #word
sfrp, #word
saddrp, saddrp’
AX, #word
rp, #word
rp, rp’
4/5
5
4
SUBW
3
4
2
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX, CY ← AX – (saddrp2)
rp, CY ← rp – (saddrp)
(saddrp), CY ← (saddrp) – rp
rp, CY ← rp – sfrp
sfrp, CY ← sfrp – rp
(saddrp), CY ← (saddrp) – word
sfrp, CY ← sfrp – word
(saddrp), CY ← (saddrp) – (saddrp’)
AX – word
3
3
3
sfrp, rp
3
saddrp, #word
sfrp, #word
saddrp, saddrp’
AX, #word
rp, #word
rp, rp’
4/5
5
4
CMPW
3
4
rp – word
2
rp – rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX – (saddrp2)
3
rp – (saddrp)
3
(saddrp) – rp
3
rp – sfrp
sfrp, rp
3
sfrp – rp
saddrp, #word
sfrp, #word
saddrp, saddrp’
4/5
5
(saddrp) – word
sfrp – word
4
(saddrp) – (saddrp’)
User’s Manual U10905EJ8V1UM
181
CHAPTER 6 INSTRUCTION SET
(8) 24-bit operation instructions: ADDG, SUBG
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
×
×
×
×
Z
×
×
×
×
×
×
AC P/V CY
ADDG
rg, rg’
2
rg, CY ← rg + rg’
×
×
×
×
×
×
V
V
V
V
V
V
×
×
×
×
×
×
rg, #imm24
WHL, saddrg
rg, rg’
5
3
2
5
3
rg, CY ← rg + imm24
WHL, CY ← WHL + (saddrg)
rg, CY ← rg – rg’
SUBG
rg, #imm24
WHL, saddrg
rg, CY ← rg – imm24
WHL, CY ← WHL – (saddrg)
(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MULU
r
2/3
2
AX ← A × r
MULUW
MULW
DIVUW
DIVUX
rp
rp
r
AX (higher half), rp (lower half) ← AX × rp
AX (higher half), rp (lower half) ← AX × rp
2
Note 1
2/3
2
AX (quotient), r (remainder) ← AX ÷ r
Note 2
rp
AXDE (quotient), rp (remainder) ← AXDE ÷ rp
Notes 1. When r = 0, r ← X, AX ← FFFFH
2. When rp = 0, rp ← DE, AXDE ← FFFFFFFFH
(10) Special operation instructions: MACW, MACSW, SACW
Mnemonic
Operands
Bytes
3
Operation
Flags
S
Z
AC P/V CY
MACW
byte
byte
AXDE ← (B) × (C) + AXDE, B ← B + 2,
C ← C + 2, byte ← byte – 1
End if (byte = 0 or P/V = 1)
×
×
×
V
×
MACSW
SACW
3
4
AXDE ← (B) × (C) + AXDE, B ← B + 2,
C ← C + 2, byte ← byte – 1
if byte = 0 then End
×
×
×
×
×
V
×
if P/V = 1 then if overflow AXDE ← 7FFFFFFFH, End
if underflow AXDE ← 80000000H, End
[TDE +], [WHL +]
AX ← | (TDE) – (WHL) | + AX,
×
V
×
TDE ← TDE + 2, WHL ← WHL + 2
C ← C – 1 End if (C = 0 or CY = 1)
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CHAPTER 6 INSTRUCTION SET
(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG
Mnemonic
INC
Operands
Bytes
Operation
Flags
S
×
×
×
×
Z
×
×
×
×
AC P/V CY
r
1/2
2/3
1/2
2/3
2/1
3/4
2/1
3/4
2
r ← r + 1
×
×
×
×
V
V
V
V
saddr
r
(saddr) ← (saddr) + 1
r ← r – 1
DEC
saddr
rp
(saddr) ← (saddr) – 1
rp ← rp + 1
INCW
DECW
saddrp
rp
(saddrp) ← (saddrp) + 1
rp ← rp – 1
saddrp
rg
(saddrp) ← (saddrp) – 1
rg ← rg + 1
INCG
DECG
rg
2
rg ← rg – 1
(12) Adjustment instructions: ADJBA, ADJBS, CVTBW
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
Z
×
×
AC P/V CY
ADJBA
ADJBS
CVTBW
2
2
1
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
×
×
P
P
×
×
X ← A, A ← 00H if A7 = 0
X ← A, A ← FFH if A7 = 1
User’s Manual U10905EJ8V1UM
183
CHAPTER 6 INSTRUCTION SET
(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
ROR
r, n
r, n
r, n
r, n
r, n
r, n
rp, n
2/3
2/3
2/3
2/3
2/3
2/3
2
(CY, r7 ← r0, rm – 1 ← rm) x n
(CY, r0 ← r7, rm + 1 ← rm) x n
n = 0 – 7
n = 0 – 7
P
P
P
P
P
P
P
×
×
×
×
×
×
×
ROL
RORC
ROLC
SHR
(CY ← r0, r7 ← CY, rm – 1 ← rm) x n
(CY ← r7, r0 ← CY, rm + 1 ← rm) x n
(CY ← r0, r7 ← 0, rm – 1 ← rm) x n
(CY ← r7, r0 ← 0, rm + 1 ← rm) x n
n = 0 – 7
n = 0 – 7
n = 0 – 7
n = 0 – 7
×
×
×
×
×
×
0
0
0
SHL
SHRW
(CY ← rp0, rp15 ← 0, rpm – 1 ← rpm) x n
n = 0 – 7
SHLW
ROR4
ROL4
rp, n
2
2
2
(CY ← rp15, rp0 ← 0, rpm + 1 ← rpm) x n
n = 0 – 7
×
×
0
P
×
mem3
mem3
A3 – 0 ← (mem3)3 – 0, (mem3)7 – 4 ← A3 – 0,
(mem3)3 – 0 ← (mem3)7 – 4
A3 – 0 ← (mem3)7 – 4, (mem3)3 – 0 ← A3 – 0,
(mem3)7 – 4 ← (mem3)3 – 0
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CHAPTER 6 INSTRUCTION SET
(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MOV1
CY, saddr.bit
3/4
3
CY ← (saddr.bit)
CY ← sfr.bit
×
×
×
×
×
×
×
×
×
CY, sfr.bit
CY, X.bit
2
CY ← X.bit
CY, A.bit
2
CY ← A.bit
CY, PSWL.bit
CY, PSWH.bit
CY, !addr16.bit
CY, !!addr24.bit
CY, mem2.bit
saddr.bit, CY
sfr.bit, CY
2
CY ← PSWL.bit
CY ← PSWH.bit
CY ← !addr16.bit
CY ← !!addr24.bit
CY ← mem2.bit
(saddr.bit) ← CY
sfr.bit ← CY
2
5
6
2
3/4
3
X.bit, CY
2
X.bit ← CY
A.bit, CY
2
A.bit, ← CY
PSWL.bit, CY
PSWH.bit, CY
!addr16.bit, CY
!!addr24.bit, CY
mem2.bit, CY
CY, saddr.bit
CY, /saddr.bit
CY, sfr.bit
2
PSWL.bit ← CY
PSWH.bit ← CY
!addr16.bit ← CY
!!addr24.bit ← CY
mem2.bit ← CY
×
×
×
×
×
2
5
6
2
AND1
3/4
3/4
3
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
(saddr.bit)
(saddr.bit)
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
sfr.bit
CY, /sfr.bit
3
sfr.bit
CY, X.bit
2
X.bit
CY, /X.bit
2
X.bit
CY, A.bit
2
A.bit
CY, /A.bit
2
A.bit
CY, PSWL.bit
CY, /PSWL.bit
CY, PSWH.bit
CY, /PSWH.bit
CY, !addr16.bit
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
CY, mem2.bit
CY, /mem2.bit
2
PSWL.bit
PSWL.bit
PSWH.bit
PSWH.bit
!addr16.bit
!addr16.bit
!!addr24.bit
!!addr24.bit
mem2.bit
mem2.bit
2
2
2
5
5
6
6
2
2
User’s Manual U10905EJ8V1UM
185
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
OR1
CY, saddr.bit
3/4
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
CY ← CY
(saddr.bit)
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CY, /saddr.bit
CY, sfr.bit
3/4
3
(saddr.bit)
sfr.bit
CY, /sfr.bit
CY, X.bit
3
sfr.bit
2
X.bit
CY, /X.bit
2
X.bit
CY, A.bit
2
A.bit
CY, /A.bit
2
A.bit
CY, PSWL.bit
CY, /PSWL.bit
CY, PSWH.bit
CY, /PSWH.bit
CY, !addr16.bit
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
CY, mem2.bit
CY, /mem2.bit
CY, saddr.bit
CY, sfr.bit
2
PSWL.bit
PSWL.bit
PSWH.bit
PSWH.bit
!addr16.bit
!addr16.bit
!!addr24.bit
!!addr24.bit
mem2.bit
mem2.bit
(saddr.bit)
sfr.bit
2
2
2
5
5
6
6
2
2
XOR1
3/4
3
CY, X.bit
2
X.bit
CY, A.bit
2
A.bit
CY, PSWL.bit
CY, PSWH.bit
CY, !addr16.bit
CY, !!addr24.bit
CY, mem2.bit
saddr.bit
2
PSWL.bit
PSWH.bit
!addr16.bit
!!addr24.bit
mem2.bit
2
5
6
2
NOT1
3/4
3
(saddr.bit) ← (saddr.bit)
sfr.bit ← sfr.bit
sfr.bit
X.bit
2
X.bit ← X.bit
A.bit
2
A.bit ← A.bit
PSWL.bit
2
PSWL.bit ← PSWL.bit
PSWH.bit ← PSWH.bit
!addr16.bit ← !addr16.bit
!!addr24.bit ← !!addr24.bit
mem2.bit ← mem2.bit
CY ← CY
×
×
×
×
×
×
PSWH.bit
2
!addr16.bit
!!addr24.bit
mem2.bit
5
6
2
CY
1
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User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
SET1
saddr.bit
2/3
(saddr.bit) ← 1
sfr.bit ← 1
sfr.bit
3
2
X.bit
X.bit ← 1
A.bit
2
A.bit ← 1
PSWL.bit
PSWH.bit
!addr16.bit
!!addr24.bit
mem2.bit
CY
2
PSWL.bit ← 1
PSWH.bit ← 1
!addr16.bit ← 1
!!addr24.bit ← 1
mem2.bit ← 1
CY ← 1
×
×
×
×
×
1
×
0
2
5
6
2
1
CLR1
saddr.bit
sfr.bit
2/3
3
(saddr.bit) ← 0
sfr.bit ← 0
X.bit
2
X.bit ← 0
A.bit
2
A.bit ← 0
PSWL.bit
PSWH.bit
!addr16.bit
!!addr24.bit
mem2.bit
CY
2
PSWL.bit ← 0
PSWH.bit ← 0
!addr16.bit ← 0
!!addr24.bit ← 0
mem2.bit ← 0
CY ← 0
×
×
×
×
2
5
6
2
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(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
Note 1
PUSH
PSW
sfrp
sfr
1
3
3
2
2
2
1
3
3
2
2
2
5
2
2
4
4
2
2
(SP – 2) ← PSW, SP ← SP – 2
(SP – 2) ← sfrp, SP ← SP – 2
(SP – 1) ← sfr, SP ← SP – 1
{(SP – 2) ← post, SP ← SP – 2} × m
(SP – 3) ← rg, SP ← SP – 3
Note 2
post
rg
Note 1
Note 1
Note 2
PUSHU
post
PSW
sfrp
sfr
{(UUP – 2) ← post, UUP ← UUP – 2} × m
PSW ← (SP), SP ← SP + 2
sfrp ← (SP), SP ← SP + 2
POP
R
R
R
R
R
sfr ← (SP), SP ← SP + 1
Note 2
post
rg
{post ← (SP), SP ← SP + 2} × m
rg ← (SP), SP ← SP + 3
Note 1
Note 2
POPU
MOVG
post
{post ← (UUP), UUP ← UUP + 2} × m
SP ← imm24
SP, #imm24
SP, WHL
WHL, SP
SP, #word
SP, #word
SP
SP ← WHL
WHL ← SP
ADDWG
SUBWG
INCG
SP ← SP + word
SP ← SP – word
SP ← SP + 1
DECG
SP
SP ← SP – 1
Notes 1. For details about operation, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure
3-5 Data Restored from Stack Area.
2. m = number of registers specified by post
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(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
Note
CALL
!addr16
3
4
2
2
2
2
3
2
1
1
(SP – 3) ← (PC + 3), SP ← SP – 3,
PCHW ← 0, PCLW ← addr16
!!addr20
rp
(SP – 3) ← (PC + 4), SP ← SP – 3,
PC ← addr20
(SP – 3) ← (PC + 2), SP ← SP – 3,
PCHW ← 0, PCLW ← rp
rg
(SP – 3) ← (PC + 2), SP ← SP – 3,
PC ← rg
[rp]
(SP – 3) ← (PC + 2), SP ← SP – 3,
PCHW ← 0, PCLW ← (rp)
[rg]
(SP – 3) ← (PC + 2), SP ← SP – 3,
PC ← (rg)
$!addr20
!addr11
[addr5]
(SP – 3) ← (PC + 3), SP ← SP – 3,
PC ← PC + 3 + jdisp16
Note
CALLF
CALLT
BRK
(SP – 3) ← (PC + 2), SP ← SP – 3
PC19 – 12 ← 0, PC11 ← 1, PC10 – 0 ← addr11
Note
(SP – 3) ← (PC + 1), SP ← SP – 3,
PCHW ← 0, PCLW ← (addr5)
(SP – 2) ← PSW, (SP – 1)0 – 3 ← (PC + 1)HW,
(SP – 4) ← PC + 1,
SP ← SP – 4
PCHW ← 0, PCLW ← (003EH)
BRKCS
RBn
2
PCLW ↔ RP2, RP3 ← PSW, RBS2 – 0 ← n,
RSS ← 0, IE ← 0, RP38 – 11 ← PCHW, PCHW ← 0
Note
RET
1
1
1
3
PC ← (SP), SP ← SP + 3
Note
RETI
PC ← (SP), PSW ← (SP + 2), SP ← SP + 4
PC ← (SP), PSW ← (SP + 2), SP ← SP + 4
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note
RETB
RETCS
!addr16
!addr16
PSW ← RP3, PCLW ← RP2, RP2 ← addr16,
PCHW ← RP38 – 11
RETCSB
4
PSW ← RP3, PCLW ← RP2, RP2 ← addr16,
PCHW ← RP38 – 11
R
R
R
R
R
Note For details about operation, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-
5 Data Restored from Stack Area.
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(17) Unconditional branch instruction: BR
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
BR
!addr16
3
PCHW ← 0, PCLW ← addr16
!!addr20
rp
4
2
2
2
2
2
3
PC ← addr20
PCHW ← 0, PCLW ← rp
PC ← rg
rg
[rp]
PCHW ← 0, PCLW ← (rp)
PC ← (rg)
[rg]
$addr20
$!addr20
PC ← PC + 2 + jdisp8
PC ← PC + 3 + jdisp16
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(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP,
BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Mnemonic
Operands
Bytes
Operation
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if P/V = 0
PC ← PC + 2 + jdisp8 if P/V = 1
Flags
S
Z
AC P/V CY
BNZ
BNE
BZ
$addr20
2
2
2
2
2
2
$addr20
$addr20
$addr20
$addr20
$addr20
BE
BNC
BNL
BC
BL
BNV
BPO
BV
BPE
BP
$addr20
2
2
PC ← PC + 2 + jdisp8 if S = 0
PC ← PC + 2 + jdisp8 if S = 1
PC ← PC + 3 + jdisp8 if P/V
PC ← PC + 3 + jdisp8 if P/V
PC ← PC + 3 + jdisp8 if (P/V
PC ← PC + 3 + jdisp8 if (P/V
BN
$addr20
BLT
BGE
BLE
BGT
BNH
BH
$addr20
3
S = 1
S = 0
S)
$addr20
3
$addr20
3
Z = 1
Z = 0
$addr20
3
S)
$addr20
3
PC ← PC + 3 + jdisp8 if Z
CY = 1
CY = 0
$addr20
3
PC ← PC + 3 + jdisp8 if Z
Note
BF
saddr.bit, $addr20
sfr.bit, $addr20
X.bit, $addr20
A.bit, $addr20
PSWL.bit, $addr20
PSWH.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
mem2.bit, $addr20
4/5
4
PC ← PC + 4
+ jdisp8 if(saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if X.bit = 0
3
3
PC ← PC + 3 + jdisp8 if A.bit = 0
3
PC ← PC + 3 + jdisp8 if PSWL.bit = 0
PC ← PC + 3 + jdisp8 if PSWH.bit = 0
PC ← PC + 3 + jdisp8 if !addr16.bit = 0
PC ← PC + 3 + jdisp8 if !!addr24.bit = 0
PC ← PC + 3 + jdisp8 if mem2.bit = 0
3
6
7
3
Note When the number of bytes is 4; when 5, the operation is: PC ← PC + 5 + jdisp8.
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Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
Note 1
BT
saddr.bit, $addr20
sfr.bit, $addr20
3/4
4
PC ← PC + 3
+ jdisp8 if(saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if X.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSWL.bit = 1
PC ← PC + 3 + jdisp8 if PSWH.bit = 1
PC ← PC + 3 + jdisp8 if !addr16.bit = 1
PC ← PC + 3 + jdisp8 if !!addr24.bit = 1
X.bit, $addr20
3
A.bit, $addr20
3
PSWL.bit, $addr20
PSWH.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
mem2.bit, $addr20
saddr.bit, $addr20
3
3
6
7
3
PC ← PC + 3 + jdisp8 if mem2.bit = 1
Note 2
BTCLR
4/5
{PC ← PC + 4
+ jdisp8, (saddr.bit) ← 0}
if(saddr.bit) = 1
sfr.bit, $addr20
4
{PC ← PC + 4 + jdisp8, sfr.bit ← 0}
if sfr.bit = 1
X.bit, $addr20
3
3
3
{PC ← PC + 3 + jdisp8, X.bit ← 0} if X.bit = 1
{PC ← PC + 3 + jdisp8, A.bit ← 0} if A.bit = 1
A.bit, $addr20
PSWL.bit, $addr20
{PC ← PC + 3 + jdisp8, PSWL.bit ← 0}
×
×
×
×
×
if PSWL.bit = 1
PSWH.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
mem2.bit, $addr20
3
6
7
3
{PC ← PC + 3 + jdisp8, PSWH.bit ← 0}
if PSWH.bit = 1
{PC ← PC + 3 + jdisp8, !addr16.bit ← 0}
if !addr16 = 1
{PC ← PC + 3 + jdisp8, !!addr24.bit ← 0}
if !!addr24 = 1
{PC ← PC + 3 + jdisp8, mem2.bit ← 0}
if mem2. bit = 1
Notes 1. When the number of bytes is 3; when 4, the operation is: PC ← PC + 4 + jdisp8.
2. When the number of bytes is 4; when 5, the operation is: PC ← PC + 5 + jdisp8.
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Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
Note 1
BFSET
saddr.bit, $addr20
sfr.bit, $addr20
4/5
4
{PC ← PC + 4
if(saddr.bit) = 0
+ jdisp8, (saddr.bit) ← 1}
{PC ← PC + 4 + jdisp8, sfr.bit ← 1}
if sfr.bit = 0
X.bit, $addr20
3
3
3
{PC ← PC + 3 + jdisp8, X.bit ← 1} if X.bit = 0
{PC ← PC + 3 + jdisp8, A.bit ← 1} if A.bit = 0
A.bit, $addr20
PSWL.bit, $addr20
{PC ← PC + 3 + jdisp8, PSWL.bit ← 1}
×
×
×
×
×
if PSWL.bit = 0
PSWH.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
mem2.bit, $addr20
3
6
7
3
{PC ← PC + 3 + jdisp8, PSWH.bit ← 1}
if PSWH.bit = 0
{PC ← PC + 3 + jdisp8, !addr16.bit ← 1}
if !addr16 = 0
{PC ← PC + 3 + jdisp8, !!addr24.bit ← 1}
if !!addr24 = 0
{PC ← PC + 3 + jdisp8, mem2.bit ← 1}
if mem2.bit = 0
DBNZ
B, $addr20
2
2
B ← B – 1, PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C – 1, PC ← PC + 2 + jdisp8 if C ≠ 0
C, $addr20
saddr, $addr20
3/4
(saddr) ← (saddr) – 1,
Note 2
PC ← PC + 3
+ jdisp8 if (saddr) ≠ 0
Notes 1. When the number of bytes is 4; when 5, the operation is: PC ← PC + 5 + jdisp8.
2. When the number of bytes is 3; when 4, the operation is: PC ← PC + 4 + jdisp8.
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(19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI
Mnemonic
Operands
Bytes
Operation
Flags
S
Z
AC P/V CY
MOV
STBC, #byte
WDM, #byte
LOCATION locaddr
4
4
4
STBC ← byte
WDM ← byte
SFR, internal data area location address high-order
word specification
SEL
RBn
2
2
2
1
1
1
RSS ← 0, RBS2 – 0 ← n
RSS ← 1, RBS2 – 0 ← n
RSS ← RSS
RBn, ALT
SWRS
NOP
EI
No Operation
IE ← 1(Enable interrupt)
IE ← 0(Disable interrupt)
DI
(20) Special instructions: CHKL, CHKLA
Mnemonic
Operands
Bytes
Operation
Flags
S
×
×
Z
×
×
AC P/V CY
CHKL
sfr
sfr
3
3
(pin level)
(output latch)
(output latch)
P
P
CHKLA
A ← (pin level)
Caution The CHKL and CHKLA instructions are not available in the µPD784216, 784216Y, 784218, 784218Y,
784225, 784225Y, 784937 Subseries. Do not execute these instructions. If these instructions are
executed, the following operations will result.
• CHKL instruction ....... After the pin levels of the output pins are read two times, they are
exclusive-ORed. As a result, if the pins checked with this instruction are
used in the port output mode, the exclusive-OR result is always 0 for all
bits, and the Z flag is set to (1).
• CHKLA instruction .... After the pin levels of output pins are read two times, they are exclusive-
ORed. As a result, if the pins checked with this instruction are used in
the port output mode, the exclusive-OR result is always 0 for all bits, and
the Z flag is set to (1) along with that the result is stored in the A register.
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(21) String instructions: MOVTBLW,MOVM,XCHM,MOVBK,XCHBK,CMPME,CMPMNE,CMPMC,CMPMNC,
CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
Mnemonic
Operands
Bytes
4
Operation
Flags
S
Z
AC P/V CY
MOVTBLW !addr8, byte
(addr8 + 2) ← (addr8), byte ← byte – 1,
addr8 ← addr8 – 2 End if byte = 0
MOVM
XCHM
[TDE +], A
2
2
2
2
2
(TDE) ← A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ← A, TDE ← TDE – 1, C ← C – 1 End if C = 0
(TDE) ↔ A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ↔ A, TDE ← TDE – 1, C ← C – 1 End if C = 0
[TDE –], A
[TDE +], A
[TDE –], A
MOVBK
[TDE +], [WHL +]
(TDE) ← (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
2
2
2
(TDE) ← (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0
XCHBK
(TDE) ↔ (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0
(TDE) ↔ (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0
CMPME
[TDE +], A
[TDE –], A
[TDE +], A
[TDE –], A
[TDE +], A
[TDE –], A
[TDE +], A
[TDE –], A
[TDE +], [WHL +]
2
2
2
2
2
2
2
2
2
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 0
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
CMPMNE
CMPMC
CMPMNC
CMPBKE
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or Z = 0
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
2
2
2
2
2
2
2
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or Z = 0
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
×
×
×
×
×
×
×
CMPBKNE
CMPBKC
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or CY = 0
CMPBKNC
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or CY = 1
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or CY = 1
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6.3 Instructions Listed by Type of Addressing
(1) 8-bit instructions (combinations expressed by writing A for r are shown in parentheses)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,
CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
Table 6-1. List of Instructions by 8-Bit Addressing
Note 2
2nd Operand #byte
1st Operand
A
r
saddr
saddr’
sfr
!addr16
mem
r3
[WHL +]
n
No
r’
!!addr24 [saddrp] PSWL [WHL –]
[%saddrg] PSWH
A
(MOV) (MOV)
MOV
XCH
(MOV) Note 6 MOV
(XCH) Note 6 (XCH)
(MOV) MOV
(XCH) XCH
MOV
(MOV)
Note 1
ADD
(XCH)
(XCH)
Note 1
Note 1
(ADD) Note 1 (ADD) Note 1 (ADD) Notes 1, 6 (ADD) Note 1 ADD
ADD
(ADD) Note 1
r
MOV
(MOV)
(XCH)
(ADD) Note 1 ADD
MOV
XCH
MOV
XCH
MOV
XCH
MOV
XCH
ROR Note 3 MULU
DIVUW
INC
Note 1
ADD
Note 1
Note 1
Note 1
ADD
ADD
DEC
saddr
sfr
MOV
(MOV) Note 6 MOV
MOV
XCH
INC
Note 1
Note 1
ADD
(ADD) Note 1 ADD
DEC
DBNZ
Note 1
ADD
MOV
MOV
MOV
PUSH
POP
Note 1
Note 1
ADD
(ADD) Note 1 ADD
CHKL
CHKLA
!addr16
!!addr24
MOV
(MOV)
MOV
Note 1
ADD
mem
MOV
Note 1
[saddrp]
[%saddrg]
ADD
mem3
ROR4
ROL4
r3
MOV
MOV
MOV
PSWL
PSWH
B, C
DBNZ
STBC, WDM
[TDE +]
[TDE –]
(MOV)
(ADD) Note 1
MOVBK Note 5
Note 4
MOVM
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are equivalent to ADD.
2. There is no 2nd operand, or the 2nd operand is not an operand address.
3. ROL, RORC, ROLC, SHR, and SHL are equivalent to ROR.
4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are equivalent to MOVM.
5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are equvalent to MOVBK.
6. When saddr is saddr2 in this combination, a short code length instruction can be used.
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(2) 16-bit instructions (combinations expressed by writing AX for rp are shown in parentheses)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,
POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 6-2. List of Instructions by 16-Bit Addressing
Note 2
2nd Operand #word
1st Operand
AX
rp
saddrp
saddrp’
sfrp
!addr16
mem [WHL +]
byte
n
No
rp’
!!addr24 [saddrp]
[%saddrg]
AX
(MOVW) (MOVW) (MOVW) (MOVW) Note 3 MOVW (MOVW) MOVW (MOVW)
ADDW Note 1 (XCHW) (XCHW) (XCHW) Note 3 (XCHW) XCHW XCHW (XCHW)
(ADD) Note 1
(ADDW) Note 1 (ADDW) Notes 1, 3 (ADDW)Note 1
rp
MOVW (MOVW) MOVW MOVW
ADDW Note 1 (XCHW) XCHW XCHW
MOVW MOVW
XCHW
SHRW
SHLW
MULW Note 4
INCW
(ADDW) Note 1
ADDW Note 1 ADDW Note 1
ADDW Note 1
DECW
saddrp
sfrp
MOVW (MOVW) Note 3 MOVW MOVW
INCW
ADDW Note 1 (ADDW) Note 1
ADDW Note 1 XCHW
DECW
Note 1
ADDW
MOVW MOVW
MOVW
PUSH
POP
ADDW Note 1 (ADDW) Note 1
ADDW Note 1
!addr16
!!addr24
MOVW (MOVW) MOVW
MOVW
MOVTBLW
mem
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE +]
byte
(MOVW)
SACW
MACW
MACSW
Notes 1. SUBW and CMPW are equivalent to ADDW.
2. There is no 2nd operand, or the 2nd operand is not an operand address.
3. When saddrp is saddrp2 in this combination, a short code length instruction can be used.
4. MULUW and DIVUX are equivalent to MULW.
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CHAPTER 6 INSTRUCTION SET
(3) 24-bit instructions (combinations expressed by writing WHL for rg are shown in parentheses)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
Table 6-3. List of Instructions by 24-Bit Addressing
Note
2nd
#imm24 WHL
rg
saddrg !!addr24 mem1 [%saddrg]
SP
No
Operand
rg’
1st
Operand
WHL
(MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG
(ADDG) (ADDG) (ADDG) ADDG
MOVG MOVG
(SUBG) (SUBG) (SUBG) SUBG
rg
MOVG (MOVG) MOVG
MOVG MOVG
INCG
DECG
PUSH
POP
ADDG
SUBG
(ADDG) ADDG
(SUBG) SUBG
saddrg
!!addr24
mem1
(MOVG) MOVG
(MOVG) MOVG
MOVG
[%saddrg]
SP
MOVG
MOVG MOVG
INCG
DECG
Note There is no 2nd operand, or the 2nd operand is not an operand address.
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(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
Table 6-4. List of Instructions by Bit Manipulation Instruction Addressing
Note
2nd Operand
CY
saddr.bit sfr.bit
A.bit X.bit
/saddr.bit /sfr.bit
/A.bit /X.bit
No
PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit
mem2.bit
/mem2.bit
!addr16.bit
!!addr24.bit
/!addr16.bit
/!!addr24.bit
1st Operand
CY
MOV1
AND1
OR1
AND1
OR1
NOT1
SET1
CLR1
XOR1
saddr.bit
sfr.bit
MOV1
NOT1
SET1
CLR1
BF
A.bit
X.bit
PSWL.bit
PSWH. bit
mem2.bit
!addr16.bit
!!addr24.bit
BT
BTCLR
BFSET
Note There is no 2nd operand, or the 2nd operand is not an operand
address.
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CHAPTER 6 INSTRUCTION SET
(5) Call/return instructions/branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL,
BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Table 6-5. List of Instructions by Call/Return Instruction/Branch Instruction Addressing
Instruction
$addr20 $!addr20 !addr16 !!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
No
Address Operand
Note
Basic instructions BC
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALLF CALLT BRKCS BRK
RET
RETCS
RETCSB
RETI
RETB
Compound
instructions
BF
BT
BTCLR
BFSET
DBNZ
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are
equivalent to BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
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6.4 Operation Codes
6.4.1 Operation code symbols
(1) r1
(2) r2
R2 R1 R0
r1
R2 R1 R0
r2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
R0
R1
R2
R3
R4
R5
R6
R7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
R8
R9
R10
R11
R12
R13
R14
R15
(3) r, r’
(4) rp
R3 R2 R1 R0
R7 R6 R5 R4
r
P7 P6 P5
rp
r’
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RP0
RP1
RP2
RP3
RP4
RP5
RP6
RP7
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
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CHAPTER 6 INSTRUCTION SET
(6) rg, rg’
(5) rp, rp’
P2 P1 P0
rp
G6 G5
G2 G1
rg
rp’
rg’
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RP0
RP4
RP1
RP5
RP2
RP6
RP3
RP7
0
0
1
1
0
1
0
1
RG4
RG5
RG6
RG7
(7) mem3
P2 P1 P0
mem3
[RP0]
[RG4]
[RP1]
[RG5]
[RP2]
[RG6]
[RP3]
[RG7]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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(8) post byte
Corresponding
Register Pair
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
AX
BC
RP2
RP3
VP
UP/PSWNote
DE
HL
0
1
Save/restore operation not performed on stack memory
Save/restore operation performed on stack memory
Note UP in the case of a PUSH/POP instruction, PSW in the case of a PUSHU/POPU instruction.
(9) locaddr
locaddr
locaddrl
FEH
locaddrh
01H
0
0FH
FFH
00H
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CHAPTER 6 INSTRUCTION SET
6.4.2 List of operation codes
(1) 8-bit data transfer instruction: MOV
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV
r1, #byte
1 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
1 R2 R1 R0
1 1 0 0
1 0 1 0
1 1 0 0
←
#byte
→
r2, #byte
1 0 1 1
Saddr2-offset
0 0 1 1 1 0 1 0
1 R2 R1 R0
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
0 0 1 0 1 0 1 1
0 0 0 0 1 0 0 1
→
sfr, #byte
←
Sfr-offset
→
←
←
#byte
→
→
!addr16, #byte
0 1 0 0 0 0 0 0
Low Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
←
#byte
→
!!addr24, #byte
0 0 0 0 1 0 0 1
0 1 0 1 0 0 0 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Low Address
→
←
High Address
→
0 R2 R1 R0
0 1 0 0
←
#byte
→
r, r1
0 0 1 0 0 1 0 0
R7 R6 R5 R4
0 0 1 0
r, r2
0 0 1 1
1 1 0 1
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 1
0 0 0 1
0 0 1 1
0 0 0 1
0 0 1 1
0 0 1 0
1 1 0 0
0 R2 R1 R0
1 1 0 0
0 0 0 0
1 0 0 0
1 0 0 0
0 0 1 0
1 0 0 0
1 0 0 0
0 0 0 0
1 0 0 0
0 0 1 0
1 0 0 0
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, r1
A, r2
1 1 0 1
←
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, A
saddr2, r
saddr1, r
A, sfr
Saddr2-offset
→
R3 R2 R1 R0
R3 R2 R1 R0
0 0 0 0
0 0 0 1
←
Saddr2-offset
Saddr1-offset
→
→
←
←
Saddr2-offset
→
R3 R2 R1 R0
R3 R2 R1 R0
0 1 0 0
0 1 0 1
←
←
Saddr2-offset
Saddr1-offset
→
→
←
Sfr-offset
→
r, sfr
R3 R2 R1 R0
0 0 1 0
←
Sfr-offset
→
sfr, A
←
Sfr-offset
→
sfr, r
R3 R2 R1 R0
0 1 1 0
←
←
Sfr-offset
→
→
saddr2, saddr2’
0 0 0 0
0 0 0 0
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
0 0 1 0 1 0 1 0
0 0 0 1
0 0 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
0 0 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
(Continued on next page)
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CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV
saddr1, saddr1’
r, !addr16
0 0 1 0
1 0 1 0
0 0 1 1
0 0 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
0 0 1 1 1 1 1 0
R3 R2 R1 R0
0 0 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
!addr16, r
0 0 1 1
1 1 1 0
R3 R2 R1 R0
0 0 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
r, !!addr24
!!addr24, r
0 0 1 1
1 1 1 0
R3 R2 R1 R0
0 0 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 1 1 1 1 1 0 0 0 1 1
R3 R2 R1 R0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Low Address
→
←
←
High Address
Saddr2-offset
→
→
A, [saddrp2]
A, [saddrp1]
A, [%saddrg2]
A, [%saddrg1]
0 0 0 1 1 0 0 0
0 0 1 1
0 0 0 0
0 0 1 1
1 1 0 0
0 1 1 1
1 1 0 0
0 0 0 1
1 0 0 0
←
←
Saddr1-offset
Saddr2-offset
→
→
0 0 1 1
0 0 0 0
0 0 0 0
0 1 1 1
0 0 1 1
0 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
A, [TDE +]
0 1 0 1 1 0 0 0
A, [WHL +]
A, [TDE –]
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [HL]
0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
(Continued on next page)
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CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV
A, imm24 [B]
0 0 0 0
1 0 1 0
0 0 1 1
0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Offset
→
←
High-w Offset
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[saddrp2], A
[saddrp1], A
[%saddrg2], A
[%saddrg1], A
0 0 0 1 0 1 1 1
0 0 0 0 0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 1
0 0 0 0
0 0 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 1 0 0
0 1 1 1
1 1 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
←
Saddr2-offset
→
0 0 0 1
1 0 1 1
0 0 0 0
1 0 0 1
0 0 0 0
0 1 1 1
←
←
Saddr1-offset
Saddr2-offset
→
→
1 0 1 1
0 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[TDE +], A
0 1 0 1 0 0 0 0
[WHL +], A
[TDE –], A
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [HL], A
0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
(Continued on next page)
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CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV
imm24 [B], A
0 0 0 0
1 0 1 0
1 0 1 1
0 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Offset
→
←
High-w Offset
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
PSWL, #byte
PSWH, #byte
PSWL, A
PSWH, A
A, PSWL
A, PSWH
V, #byte
0 0 0 1 0 1 1 1
1 0 0 0 0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 1 1
1 0 1 1
0 0 1 0
0 0 1 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 0
1 1 1 1
1 1 1 0
1 1 1 1
1 1 1 0
1 1 1 1
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
←
←
#byte
#byte
→
→
←
←
←
←
#byte
#byte
#byte
#byte
→
→
→
→
U, #byte
T, #byte
W, #byte
A, V
A, U
A, T
A, W
V, A
U, A
T, A
W, A
User’s Manual U10905EJ8V1UM
207
CHAPTER 6 INSTRUCTION SET
(2) 16-bit data transfer instruction: MOVW
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVW
rp, #word
0 1 1 0
0 0 0 0
0 P2 P1 P0
1 1 0 0
←
←
Low Byte
→
→
←
←
High Byte
Low Byte
→
→
saddrp2, #word
saddrp1, #word
sfrp, #word
Saddr2-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
0 0 1 1 1 1 0 0
0 0 0 0
1 1 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Low Byte
→
←
←
High Byte
Sfr-offset
→
→
0 0 0 0 1 0 1 1
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
!addr16, #word
!!addr24, #word
0 0 0 0 1 0 0 1
0 1 0 0
0 0 0 1
Low Byte
0 1 0 1 0 0 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
←
→
←
←
High Byte
→
→
0 0 0 0 1 0 0 1
High-w Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Low Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Byte
→
←
High Address
→
←
Low Byte
→
←
→
rp, rp’
0 0 1 0 0 1 0 0
P7 P6 P5 0
1 P2 P1 P0
AX, saddrp2
rp, saddrp2
rp, saddrp1
saddrp2, AX
saddrp2, rp
saddrp1, rp
AX, sfrp
0 0 0 1
0 0 1 1
0 0 1 1
0 0 0 1
0 0 1 1
0 0 1 1
0 0 0 1
0 0 1 1
0 0 0 1
0 0 1 1
0 0 1 0
1 1 0 0
1 0 0 0
1 0 0 0
1 0 1 0
1 0 0 0
1 0 0 0
0 0 0 1
1 0 0 0
0 0 1 1
1 0 0 0
1 0 1 0
←
Saddr2-offset →
P7 P6 P5 0
P7 P6 P5 0
←
1 0 0 0
1 0 0 1
←
←
Saddr2-offset
Saddr1-offset
→
→
Saddr2-offset
→
P7 P6 P5 0
P7 P6 P5 0
1 1 0 0
1 1 0 1
←
←
Saddr2-offset
Saddr1-offset
→
→
←
Sfr-offset
→
rp, sfrp
P7 P6 P5 0
1 0 1 0
←
Sfr-offset
→
sfrp, AX
←
Sfr-offset
→
sfrp, rp
P7 P6 P5 0
1 1 1 0
←
←
Sfr-offset
→
→
saddrp2, saddrp2’
1 0 0 0
0 0 0 0
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddrp2, saddrp1
saddrp1, saddrp2
saddrp1, saddrp1’
rp, !addr16
0 0 1 0 1 0 1 0
1 0 0 1
0 0 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 0
0 0 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 1
0 0 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 1
1 1 1 0
P7 P6 P5 0
1 0 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
(Continued on next page)
208
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVW
!addr16, rp
0 0 1 1
1 1 1 0
P7 P6 P5 0
1 0 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
rp, !!addr24
!!addr24, rp
0 0 1 1 1 1 1 0
P7 P6 P5 0
1 0 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 1 1 1 1 1 0 1 0 1 1
P7 P6 P5 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
AX, [saddrp2]
AX, [saddrp1]
0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1
0 0 1 0 0 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
AX, [%saddrg2]
AX, [%saddrg1]
0 0 0 0 0 1 1 1
0 0 1 1
0 0 0 0
0 0 0 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 1 1 0 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
AX, [TDE +]
0 0 0 1 0 1 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
AX, [WHL +]
AX, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
AX, [WHL –]
AX, [TDE]
AX, [WHL]
AX, [VVP]
AX, [UUP]
AX, [TDE + byte]
AX, [SP + byte]
AX, [WHL + byte]
AX, [UUP + byte]
AX, [VVP + byte]
AX, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
AX, imm24 [A]
AX, imm24 [HL]
AX, imm24 [B]
AX, [TDE + A]
0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
(Continued on next page)
User’s Manual U10905EJ8V1UM
209
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVW
AX, [WHL + A]
AX, [TDE + B]
AX, [WHL + B]
AX, [VVP + DE]
AX, [VVP + HL]
AX, [TDE + C]
AX, [WHL + C]
[saddrp2], AX
[saddrp1], AX
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 1 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 1 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
←
Saddr2-offset
→
1 0 1 0
0 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
[%saddrg2], AX
[%saddrg1], AX
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
1 0 1 1
0 0 0 1
←
Saddr2-offset
→
0 0 0 0
0 1 1 1
1 0 1 1 0 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[TDE +], AX
0 0 0 1 0 1 1 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
[WHL +], AX
[TDE –], AX
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
[WHL–], AX
[TDE], AX
[WHL], AX
[VVP], AX
[UUP], AX
[TDE + byte], AX
[SP + byte], AX
[WHL + byte], AX
[UUP + byte], AX
[VVP + byte], AX
imm24 [DE], AX
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], AX
imm24 [HL], AX
imm24 [B], AX
0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
(Continued on next page)
210
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVW
[TDE + A], AX
[WHL + A], AX
[TDE + B], AX
[WHL + B], AX
[VVP + DE], AX
[VVP + HL], AX
[TDE + C], AX
[WHL + C], AX
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
User’s Manual U10905EJ8V1UM
211
CHAPTER 6 INSTRUCTION SET
(3) 24-bit data transfer instruction: MOVG
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVG
rg, #imm24
0 0 1 1
1 0 0 0
1 G6 G5 1
1 0 1 1
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
0 0 1 0 0 1 0 0
0 0 1 1 1 1 1 0
→
←
High-w Byte
1 G6 G5 1
1 G6 G5 1
→
rg, rg’
1 G2 G1 1
rg, !!addr24
1 0 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
!!addr24, rg
0 0 1 1 1 1 1 0 1 G6 G5 1 1 0 1 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
rg, saddrg2
0 0 1 1 1 0 0 0 1 G6 G5 1 1 0 0 0
←
←
←
←
←
Saddr2-offset
Saddr1-offset
Saddr2-offset
Saddr1-offset
Saddr2-offset
→
→
→
→
→
rg, saddrg1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
1 0 0 0
1 0 0 0
1 0 0 0
0 1 1 1
1 1 0 0
1 G6 G5 1
1 G6 G5 1
1 G6 G5 1
0 0 1 1
0 0 0 0
1 0 0 1
1 1 0 0
1 1 0 1
0 0 1 0
0 1 1 1
saddrg2, rg
saddrg1, rg
WHL, [%saddrg2]
WHL, [%saddrg1]
0 0 1 1
0 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
[%saddrg2], WHL
[%saddrg1], WHL
0 0 0 0 0 1 1 1
1 0 1 1
0 0 0 0
0 0 1 0
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
1 0 1 1 0 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
WHL, [TDE +]
0 0 0 1 0 1 1 0
0 0 0 0
0 0 1 0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
WHL, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
WHL, [TDE]
WHL, [WHL]
WHL, [VVP]
WHL, [UUP]
WHL, [TDE + byte]
WHL, [SP + byte]
WHL, [WHL + byte]
WHL, [UUP + byte]
WHL, [VVP + byte]
WHL, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
WHL, imm24 [A]
0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
(Continued on next page)
212
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVG
WHL, imm24 [HL]
WHL, imm24 [B]
0 0 0 0
1 0 1 0
0 0 1 0
0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Offset
→
←
High-w Offset
→
0 0 0 0 1 0 1 0
0 0 1 1 0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
WHL, [TDE + A]
WHL, [WHL + A]
WHL, [TDE + B]
WHl, [WHL + B]
WHL, [VVP + DE]
WHL, [VVP + HL]
WHL, [TDE + C]
WHL, [WHL + C]
[TDE +], WHL
0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
[TDE –], WHL
[TDE], WHL
[WHL], WHL
[VVP], WHL
[UUP], WHL
[TDE + byte], WHL
[SP + byte], WHL
[WHL + byte], WHL
[UUP + byte], WHL
[VVP + byte], WHL
imm24 [DE], WHL
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], WHL
imm24 [HL], WHL
imm24 [B], WHL
0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], WHL
[WHL + A], WHL
[TDE + B], WHL
0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 0
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
0 0 1 0
0 0 1 0
(Continued on next page)
User’s Manual U10905EJ8V1UM
213
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVG
[WHL + B], WHL
[VVP + DE], WHL
[VVP + HL], WHL
[TDE + C], WHL
[WHL + C], WHL
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
214
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(4) 8-bit data exchange instruction: XCH
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XCH
r, r1
r, r2
A, r1
A, r2
0 0 1 0
0 0 1 1
1 1 0 1
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 0
0 1 0 1
1 1 0 0
1 R2 R1 0
1 1 0 0
0 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 1 0
R7 R6 R5 R4
0 0 1 0
0 R2 R1 R0
0 1 0 1
R7 R6 R5 R4
0 R2 R1 R0
1 1 0 1
1 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
r, sfr
←
Saddr2-offset
→
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
←
←
←
←
Saddr2-offset
Saddr1-offset
Sfr-offset
→
→
→
→
0 0 0 1
0 0 1 0
0 1 0 0
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
r, !addr16
0 0 1 0 1 0 1 0
0 0 0 1
0 1 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
0 1 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
0 1 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 1
1 1 1 0
R7 R6 R5 R4
0 1 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
r, !!addr24
0 0 1 1 1 1 1 0
R7 R6 R5 R4
0 1 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Low Address
→
←
←
High Address
Saddr2-offset
→
→
A, [saddrp2]
A, [saddrp1]
A, [%saddrg2]
A, [%saddrg1]
0 0 1 0 0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
1 1 0 0
0 1 1 1
1 1 0 0
0 0 1 0
0 0 1 1
←
←
Saddr1-offset
Saddr2-offset
→
→
0 0 1 1
0 0 0 0
0 1 0 0
0 1 1 1
0 0 1 1
0 1 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
A, [TDE +]
A, [WHL +]
A, [TDE –]
A, [WHL –]
A, [TDE]
0 0 0 1 0 1 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
A, [WHL]
A, [VVP]
A, [UUP]
(Continued on next page)
User’s Manual U10905EJ8V1UM
215
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XCH
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
216
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(5) 16-bit data exchange instruction: XCHW
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XCHW
rp, rp’
0 0 1 0
0 0 0 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 1 0 1
1 0 1 1
1 0 0 1
1 0 0 1
1 0 0 1
0 1 1 1
1 1 0 0
P7 P6 P5 0
1 P2 P1 P0
AX, saddrp2
rp, saddrp2
rp, saddrp1
rp, sfrp
←
Saddr2-offset
→
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
0 0 1 0
0 0 0 0
1 0 0 0
←
←
←
←
Saddr2-offset
Saddr1-offset
Sfr-offset
→
→
→
→
1 0 0 1
1 0 1 0
0 1 0 1
0 1 1 1
AX, [saddrp2]
AX, [saddrp1]
Saddr2-offset
0 0 1 0
0 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
AX, [%saddrg2]
AX, [%saddrg1]
0 0 0 0 0 1 1 1
0 0 1 1
0 0 0 0
0 1 0 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 1 1 0 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
AX, !addr16
0 0 0 0 1 0 1 0
0 1 0 0
0 1 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
AX, !!addr24
0 0 0 0
1 0 1 0
0 1 0 1
0 1 0 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
saddrp2, saddrp2’
saddrp2, saddrp1
saddrp1, saddrp2
saddrp1, saddrp1’
0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0
←
Saddr2’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 0 1
0 1 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 0
0 1 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 1
0 1 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
AX, [TDE + byte]
AX, [SP + byte]
AX, [WHL + byte]
AX, [UUP + byte]
AX, [VVP + byte]
AX, imm24 [DE]
0 0 0 0 0 1 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
AX, imm24 [A]
0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
217
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XCHW
AX, imm24 [HL]
AX, imm24 [B]
0 0 0 0
1 0 1 0
0 0 1 0
0 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Offset
→
←
High-w Offset
→
0 0 0 0 1 0 1 0
0 0 1 1 0 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
AX, [TDE +]
AX, [WHL +]
AX, [TDE –]
AX, [WHL –]
AX, [TDE]
0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
AX, [WHL]
AX, [VVP]
AX, [UUP]
AX, [TDE + A]
AX, [WHL + A]
AX, [TDE + B]
AX, [WHL + B]
AX, [VVP + DE]
AX, [VVP + HL]
AX, [TDE + C]
AX, [WHL + C]
218
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, CMP, AND, OR, XOR
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADD
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 0 0 0
1 0 0 0
1 0 0 0
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 0 0 0
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 0 0 0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 0 0 0
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 0 0 0
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 0 0 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 0 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 0 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 0 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
0 0 1 0
1 0 0 0
←
Saddr2-offset
→
0 0 0 0
0 1 1 1
0 0 1 0 1 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 0 0 0
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 0 0 0
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
219
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADD
[%saddrg2], A
[%saddrg1], A
0 0 0 0
0 0 1 1
0 1 1 1
1 1 0 0
1 0 1 1
0 0 0 0
1 0 0 0
0 1 1 1
←
Saddr2-offset
→
1 0 1 1
1 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1 Offset
→
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 0 0 1 0 1 0
0 1 0 0
1 0 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 0 0 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 0 0 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 0
0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0
(Continued on next page)
220
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADD
A, [TDE + B]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
User’s Manual U10905EJ8V1UM
221
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADDC
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 0 0 1
1 0 0 1
1 0 0 1
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 0 0 1
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 0 0 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 0 0 1
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 0 0 1
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 0 0 1
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 0 0 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 0 0 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 0 0 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 0 0 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 0 0 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 0 0 1
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 0 0 1
←
Saddr2-offset
→
(Continued on next page)
222
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADDC
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 0 0 1
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 0 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 0 0 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 0 0 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 0 0 1
1 0 0 1
(Continued on next page)
User’s Manual U10905EJ8V1UM
223
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADDC
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
224
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUB
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 0 1 0
1 0 1 0
1 0 1 0
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2 Offset
0 1 1 0 1 0 1 0
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-Offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 0 1 0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 0 1 0
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 0 1 0
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 0 1 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 0 1 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 0 1 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 0 1 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 0 1 0
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 0 1 0
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 0 1 0
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 0 1 0
←
Saddr2-offset
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
225
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUB
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 0 1 0
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 0 1 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 0 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 0 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 0 1 0
1 0 1 0
(Continued on next page)
226
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUB
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
User’s Manual U10905EJ8V1UM
227
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUBC
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 0 1 1
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 0 1 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 0 1 1
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 0 1 1
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 0 1 1
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 0 1 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 0 1 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 0 1 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 0 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 0 1 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 0 1 1
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 0 1 1
←
Saddr2-offset
→
(Continued on next page)
228
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUBC
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 0 1 1
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 0 1 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 0 1 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 0 1 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 0 1 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 0 1 1
1 0 1 1
(Continued on next page)
User’s Manual U10905EJ8V1UM
229
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUBC
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
230
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CMP
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 1 1 1
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 1 1 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 1 1 1
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 1 1 1
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 1 1 1
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 1 1 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 1 1 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 1 1 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 1 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 1 1 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 1 1 1
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 1 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 1 1 1
←
Saddr2-offset
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
231
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CMP
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 1 1 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 1 1 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 1 1 1
1 1 1 1
(Continued on next page)
232
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CMP
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
User’s Manual U10905EJ8V1UM
233
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
AND
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 1 0 0
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 1 0 0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 1 0 0
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 1 0 0
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 1 0 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 1 0 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 1 0 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 1 0 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 1 0 0
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 1 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 1 0 0
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 1 0 0
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 1 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 1 0 0
←
Saddr2-offset
→
(Continued on next page)
234
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
AND
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 1 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 1 0 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 1 0 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 1 0 0
1 1 0 0
(Continued on next page)
User’s Manual U10905EJ8V1UM
235
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
AND
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
236
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
OR
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 1 1 0
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 1 1 0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 1 1 0
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 1 1 0
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 1 1 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 1 1 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 1 1 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 1 1 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 1 1 0
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 1 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 1 1 0
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 1 1 0
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 1 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 1 1 0
←
Saddr2-offset
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
237
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
OR
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 0
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 1 1 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 1 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 1 1 0
1 1 1 0
(Continued on next page)
238
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
OR
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
User’s Manual U10905EJ8V1UM
239
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XOR
A, #byte
1 0 1 0
0 1 1 1
0 1 1 0
0 0 1 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 0
←
#byte
→
r, #byte
R7 R6 R5 R4
0 0 1 1
Saddr2-offset
0 1 1 0 1 1 0 1
←
←
←
#byte
#byte
→
→
→
saddr2, #byte
saddr1, #byte
←
→
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
sfr, #byte
0 0 0 0 0 0 0 1
0 1 1 0
1 1 0 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
r, r1
1 0 0 0 1 1 0 1
R7 R6 R5 R4
1 0 0 0
0 R2 R1 R0
1 1 0 1
→
r, r2
0 0 1 1
1 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 1 0
1 1 0 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 0 1 0
R7 R6 R5 R4
0 R2 R1 R0
A, saddr2
r, saddr2
r, saddr1
saddr2, r
saddr1, r
r, sfr
←
Saddr2-offset
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
R7 R6 R5 R4
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0
0 1 1 0
1 1 0 1
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
→
→
→
→
→
→
→
Saddr2-offset
Saddr1-offset
Sfr-offset
sfr, r
Sfr-offset
saddr2, saddr2’
Saddr2’-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
saddr2, saddr1
saddr1, saddr2
saddr1, saddr1’
0 0 1 0 1 0 1 0
0 0 0 1
1 1 0 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 0
1 1 0 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
0 0 1 1
1 1 0 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
A, [saddrp2]
A, [saddrp1]
0 0 0 0 0 1 1 1
0 0 1 0
1 1 0 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 0
0 0 0 0
0 1 1 1
0 0 1 0 1 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
A, [%saddrg2]
A, [%saddrg1]
0 0 1 1
0 0 0 0
1 1 0 1
0 1 1 1
←
Saddr2-offset
→
0 0 1 1 1 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0
→
[saddrp2], A
[saddrp1], A
1 0 1 0
0 0 0 0
1 1 0 1
0 1 1 1
←
Saddr2-offset
→
1 0 1 0 1 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
[%saddrg2], A
0 0 0 0 0 1 1 1
1 0 1 1
1 1 0 1
←
Saddr2-offset
→
(Continued on next page)
240
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XOR
[%saddrg1], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 1
←
→
0 0 0 0
1 0 1 0
0 1 0 0
1 1 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
0 1 0 1
1 1 0 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Address
←
→
0 0 0 0
1 0 1 0
1 1 0 1
1 1 0 1
←
High-w Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
A, [TDE +]
0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 1
A, [WHL +]
A, [TDE –]
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
A, [WHL –]
A, [TDE]
A, [WHL]
A, [VVP]
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24 [DE]
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, imm24 [A]
A, imm24 [HL]
A, imm24 [B]
0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 0 0 1
0 0 1 0
1 1 0 1
1 1 0 1
(Continued on next page)
User’s Manual U10905EJ8V1UM
241
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
XOR
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 0 0 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24 [DE], A
←
←
←
←
←
←
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
Low Offset
→
→
→
→
→
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
imm24 [A], A
imm24 [HL], A
imm24 [B], A
0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 1
←
Low Offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Offset High-w Offset
←
→
←
→
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
242
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(7) 16-bit operation instructions: ADDW, SUBW, CMPW
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADDW
AX, #word
0 0 1 0
0 1 1 1
1 1 0 1
1 0 0 0
←
Low Byte
→
←
←
High Byte
Low Byte
→
→
rp, #word
P7 P6 P5 0
1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
rp, rp’
1 0 0 0 1 0 0 0
P7 P6 P5 0
1 P2 P1 P0
AX, saddrp2
rp, saddrp2
rp, saddrp1
saddrp2, rp
saddrp1, rp
rp, sfrp
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 0 0
1 1 0 1
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 1 0 1
←
Saddr2-offset →
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
←
1 0 0 0
1 0 0 1
1 1 0 0
1 1 0 1
1 0 1 0
1 1 1 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
Saddr2-offset
Saddr1-offset
Sfr-offset
→
→
→
→
→
→
→
sfrp, rp
Sfr-offset
saddrp2, #word
Saddr2-offset
→
Low Byte
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
saddrp1, #word
sfrp, #word
0 0 1 1 1 1 0 0
0 0 0 0
1 1 0 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
saddrp2, saddrp2’
saddrp2, saddrp1
saddrp1, saddrp2
saddrp1, saddrp1’
0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1
←
Saddr2’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 0 1
1 1 0 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 0
1 1 0 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 1
1 1 0 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
SUBW
AX, #word
rp, #word
0 0 1 0 1 1 1 0
←
Low Byte
→
←
←
High Byte
Low Byte
→
→
0 1 1 1 1 0 1 0
P7 P6 P5 0
1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
rp, rp’
1 0 0 0 1 0 1 0
P7 P6 P5 0
1 P2 P1 P0
AX, saddrp2
rp, saddrp2
rp, saddrp1
saddrp2, rp
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
1 1 1 0
1 0 1 0
1 0 1 0
1 0 1 0
←
Saddr2-offset →
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
1 0 0 0
1 0 0 1
1 1 0 0
←
←
←
Saddr2-offset
Saddr1-offset
Saddr2-offset
→
→
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
243
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
SUBW
saddrp1, rp
0 1 1 1
0 1 1 1
0 1 1 1
0 0 0 0
1 0 1 0
1 0 1 0
1 0 1 0
1 1 1 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
1 1 0 1
1 0 1 0
1 1 1 0
←
←
←
←
Saddr1-offset
Sfr-offset
→
→
→
→
rp, sfrp
sfrp, rp
Sfr-offset
saddrp2, #word
←
Saddr2-offset
→
Low Byte
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
saddrp1, #word
sfrp, #word
0 0 1 1 1 1 0 0
0 0 0 0
1 1 1 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
saddrp2, saddrp2’
saddrp2, saddrp1
saddrp1, saddrp2
saddrp1, saddrp1’
0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0
←
Saddr2’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 0 1
1 1 1 0
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 0
1 1 1 0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 1
1 1 1 0
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
CMPW
AX, #word
rp, #word
0 0 1 0 1 1 1 1
0 1 1 1 1 1 1 1
←
Low Byte
→
←
←
High Byte
Low Byte
→
→
P7 P6 P5 0
1 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
rp, rp’
1 0 0 0 1 1 1 1
P7 P6 P5 0
1 P2 P1 P0
AX, saddrp2
rp, saddrp2
rp, saddrp1
saddrp2, rp
saddrp1, rp
rp, sfrp
0 0 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
←
Saddr2-offset →
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
P7 P6 P5 0
←
1 0 0 0
1 0 0 1
1 1 0 0
1 1 0 1
1 0 1 0
1 1 1 0
←
←
←
←
←
←
←
Saddr2-offset
Saddr1-offset
Saddr2-offset
Saddr1-offset
Sfr-offset
→
→
→
→
→
→
→
sfrp, rp
Sfr-offset
saddrp2, #word
Saddr2-offset
→
Low Byte
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
saddrp1, #word
sfrp, #word
0 0 1 1 1 1 0 0
0 0 0 0
1 1 1 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Byte High Byte
←
→
←
→
(Continued on next page)
244
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CMPW
saddrp2, saddrp2’
saddrp2, saddrp1
saddrp1, saddrp2
saddrp1, saddrp1’
0 0 1 0
1 0 1 0
1 0 0 0
1 1 1 1
←
Saddr2’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr2-offset
→
0 0 1 0 1 0 1 0
1 0 0 1
1 1 1 1
←
Saddr1-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr2-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 0
1 1 1 1
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
0 0 1 0
1 0 1 0
1 0 1 1
1 1 1 1
←
Saddr1’-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
←
→
(8) 24-bit operation instructions: ADDG, SUBG
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADDG
rg, rg’
1 0 0 0
0 1 1 1
1 0 0 0
1 0 0 0
1 G6 G5 1
1 G6 G5 1
1 G2 G1 1
1 0 1 1
rg, #imm24
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
←
High-w Byte
→
WHL, saddrg2
WHL, saddrg1
rg, rg’
0 1 1 1 1 0 0 0
1 1 1 1 1 0 0 0
←
←
Saddr2-offset
Saddr1-offset
→
→
0 1 1 1
1 0 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 0 1 0
1 1 1 1
1 G6 G5 1
1 G6 G5 1
1 0 0 1
1 G2 G1 1
1 0 1 1
SUBG
rg, #imm24
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
0 1 1 1 1 0 1 0
0 1 1 1 1 0 1 0
→
←
High-w Byte
1 1 1 1 1 0 0 0
1 1 1 1 1 0 0 1
→
WHL, saddrg2
WHL, saddrg1
←
←
Saddr2-offset
Saddr1-offset
→
→
User’s Manual U10905EJ8V1UM
245
CHAPTER 6 INSTRUCTION SET
(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MULU
r1
r2
rp
rp
r1
r2
rp
0 0 0 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 0 0
0 1 0 1
1 1 0 0
0 1 0 1
0 1 0 1
0 1 0 1
1 1 0 0
0 1 0 1
0 0 0 0
1 R2 R1 R0
0 1 0 1
1 P2 P1 P0
1 P2 P1 P0
1 R2 R1 R0
0 1 0 1
1 P2 P1 P0
0 0 0 0
0 0 1 0
0 0 1 1
0 0 0 1
0 0 0 0
1 1 1 0
0 0 0 0
1 R2 R1 R0
MULUW
MULW
DIVUW
0 0 0 1
1 R2 R1 R0
DIVUX
(10) Special operation instructions: MACW, MACSW, SACW
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MACW
MACSW
SACW
byte
byte
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
1 0 0 1
1 0 0 0
1 0 0 1
0 1 1 0
0 1 0 1
0 1 0 1
0 1 0 0
←
byte
byte
→
→
←
[TDE + ], [WHL + ]
0 1 0 0
0 0 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 1 0 0
0 1 1 0
246
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
INC
r1
r2
1 1 0 0
0 0 1 1
0 0 1 0
0 0 1 1
1 1 0 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 0 0 0
0 0 1 1
0 R2 R1 R0
1 1 0 0
0 1 1 0
1 1 0 0
1 R2 R1 R0
1 1 0 0
0 1 1 1
1 1 0 0
1 1 1 0
1 1 1 0
1 1 1 0
1 1 1 0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 1 1 1
1 1 0 0
1 1 0 0
Saddr2-offset
0 0 1 0 0 1 1 0
0 R2 R1 R0
saddr2
saddr1
r1
←
→
←
←
Saddr1-offset
Saddr1-offset
→
→
DEC
r2
1 1 0 0
1 R2 R1 R0
saddr2
saddr1
RP0
←
Saddr2-offset
→
0 0 1 0
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
0 1 1 1
INCW
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
RP1
RP2
RP3
VP (RP4)
UP (RP5)
DE (RP6)
HL (RP7)
saddrp2
saddrp1
1 1 1 0
0 0 0 0
1 0 0 0
0 1 1 1
←
Saddr2-offset
→
1 1 1 0
1 0 0 0
←
Saddr1-offset
→
DECW
RP0
0 0 1 1 1 1 1 0
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
RP1
0 0 1 1
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 0 0 0
0 0 1 1
1 1 1 0
1 1 1 0
1 1 1 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
0 1 1 1
1 1 0 0
RP2
RP3
VP (RP4)
UP (RP5)
DE (RP6)
HL (RP7)
saddrp2
saddrp1
1 1 1 0
0 0 0 0
1 0 0 1
0 1 1 1
←
Saddr2-offset
→
1 1 1 0
1 0 0 1
←
Saddr1-offset
→
INCG
rg
rg
0 0 1 1
0 0 1 1
1 1 1 0
1 1 1 0
1 G6 G5 1
1 G6 G5 1
1 1 0 1
1 1 1 1
DECG
User’s Manual U10905EJ8V1UM
247
CHAPTER 6 INSTRUCTION SET
(12) Adjustment instructions: ADJBA, ADJBS, CVTBW
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ADJBA
ADJBS
CVTBW
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 1
0 1 0 1
0 1 0 0
1 1 1 1
1 1 1 1
1 1 1 0
1 1 1 1
(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
ROR
ROL
r1, n
r2, n
r1, n
r2, n
r1, n
r2, n
r1, n
r2, n
r1, n
r2, n
r1, n
r2, n
rp, n
rp, n
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
1 1 0 0
0 0 0 1
1 1 0 0
0 0 0 0
1 1 0 0
0 0 0 1
1 1 0 0
0 0 0 0
1 1 0 0
0 0 0 1
1 1 0 0
0 0 0 0
0 0 0 1
0 1 0 1
0 1 0 1
0 1 N2 N1
N0 R2 R1 R0
0 0 0 0
N0 R2 R1 R0
0 0 0 1
N0 R2 R1 R0
0 0 0 0
N0 R2 R1 R0
0 0 0 1
N0 R2 R1 R0
0 0 0 0
N0 R2 R1 R0
0 0 0 1
N0 P2 P1 P0
N0 P2 P1 P0
1 P2 P1 P0
1 P2 P1 P0
0 0 1 1
0 1 N2 N1
0 0 1 1
0 0 N2 N1
0 0 1 1
0 0 N2 N1
0 0 1 1
1 0 N2 N1
0 0 1 1
1 0 N2 N1
0 0 1 1
1 1 N2 N1
1 1 N2 N1
1 0 0 0
1 0 0 1
0 1 N2 N1
0 1 N2 N1
0 0 N2 N1
0 0 N2 N1
1 0 N2 N1
1 0 N2 N1
N0 R2 R1 R0
N0 R2 R1 R0
N0 R2 R1 R0
N0 R2 R1 R0
N0 R2 R1 R0
N0 R2 R1 R0
RORC
ROLC
SHR
SHL
SHRW
SHLW
ROR4
ROL4
mem3
mem3
248
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV1
CY, saddr2. bit
CY, saddr1. bit
0 0 0 0
0 0 1 1
1 0 0 0
1 1 0 0
0 0 0 0
0 0 0 0
0 B2 B1 B0
1 0 0 0
←
Saddr2-offset
→
0 0 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
CY, sfr. bit
0 0 0 0 1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 0 1
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
Sfr-offset
→
CY, X. bit
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
CY, A. bit
CY, PSWL. bit
CY, PSWH. bit
CY, [TDE]. bit
CY, [WHL]. bit
CY, !addr16.bit
0 0 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
CY, !!addr24.bit
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 0 0 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High-w Address
0 0 0 0 1 0 0 0
0 0 1 1 1 1 0 0
→
←
Low Address
→
←
←
High Address
Saddr2-offset
→
→
saddr2. bit, CY
saddr1. bit, CY
0 0 0 1
0 B2 B1 B0
0 0 0 0
1 0 0 0
0 0 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
sfr. bit, CY
0 0 0 0 1 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
1 1 0 1
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
Sfr-offset
→
X. bit, CY
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
A. bit, CY
PSWL. bit, CY
PSWH. bit, CY
[TDE]. bit, CY
[WHL]. bit, CY
!addr16. bit, CY
0 0 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
!addr24. bit, CY
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 0 0 1
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High-w Address
0 0 0 0 1 0 0 0
0 0 1 1 1 1 0 0
→
←
Low Address
→
←
←
High Address
Saddr2-offset
→
→
AND1
CY, saddr2. bit
CY, saddr1. bit
0 0 1 0
0 B2 B1 B0
0 0 0 0
1 0 0 0
0 0 1 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
CY,/saddr2. bit
0 0 0 0 1 0 0 0
0 0 1 1
0 B2 B1 B0
←
Saddr2-offset
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
249
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
AND1
CY,/saddr1. bit
0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset
1 1 0 0
0 0 0 0
1 0 0 0
0 0 1 1
0 B2 B1 B0
←
→
CY, sfr. bit
0 0 0 0 1 0 0 0
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
0 0 1 0
0 0 1 1
1 1 0 1
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
←
Sfr-offset
Sfr-offset
→
→
CY,/sfr. bit
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
1 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 0 0 1
CY, X. bit
CY,/X. bit
CY, A. bit
CY,/A. bit
CY, PSWL. bit
CY,/PSWL. bit
CY, PSWH. bit
CY,/PSWH. bit
CY, [TDE]. bit
CY,/ [TDE]. bit
CY, [WHL]. bit
CY,/ [WHL]. bit
CY, !addr16.bit
0 0 1 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
0 B2 B1 B0
←
→
←
→
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 0 1 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 0 1 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
←
→
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 B2 B1 B0
←
High-w Address
0 0 0 0 1 0 0 0
0 0 1 1 1 1 0 0
→
←
Low Address
→
←
High Address
→
OR1
CY, saddr2. bit
CY, saddr1. bit
0 1 0 0
0 B2 B1 B0
←
Saddr2-offset
→
0 0 0 0
1 0 0 0
0 1 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
0 0 0 0 1 0 0 0
0 0 1 1 1 1 0 0
→
CY, /saddr2. bit
CY, /saddr1. bit
0 1 0 1
0 0 0 0
0 B2 B1 B0
1 0 0 0
←
Saddr2-offset
→
0 1 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
CY, sfr. bit
CY,/sfr. bit
CY, X. bit
CY,/X. bit
0 0 0 0 1 0 0 0
0 1 0 0
0 1 0 1
0 1 0 0
0 1 0 1
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
←
←
Sfr-offset
Sfr-offset
→
→
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
0 0 1 1
0 0 1 1
(Continued on next page)
250
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
OR1
CY, A. bit
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 0 0 1
0 1 0 0
0 1 0 1
0 1 0 0
0 1 0 1
0 1 0 0
0 1 0 1
0 1 0 0
0 1 0 1
0 1 0 0
0 1 0 1
1 1 0 1
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
1 B2 B1 B0
0 0 0 0
CY,/A. bit
CY, PSWL. bit
CY,/PSWL. bit
CY, PSWH. bit
CY,/PSWH. bit
CY, [TDE]. bit
CY,/ [TDE]. bit
CY, [WHL]. bit
CY,/ [WHL]. bit
CY, !addr16.bit
0 1 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
CY,/!addr16.bit
CY, !!addr24.bit
CY,/!!addr24.bit
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 1 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 1 0 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
←
→
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1 B2 B1 B0
←
High-w Address
0 0 0 0 1 0 0 0
0 0 1 1 1 1 0 0
→
←
Low Address
→
←
High Address
→
XOR1
CY, saddr2. bit
CY, saddr1. bit
0 1 1 0
0 B2 B1 B0
←
Saddr2-offset
→
0 0 0 0
1 0 0 0
0 1 1 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
CY, sfr. bit
0 0 0 0 1 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
1 1 0 1
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
Sfr-offset
→
CY, X. bit
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
CY, A. bit
CY, PSWL. bit
CY, PSWH. bit
CY, [TDE]. bit
CY, [WHL]. bit
CY, !addr16.bit
0 1 1 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
CY, !!addr24.bit
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 1 1 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
←
→
←
→
←
→
(Continued on next page)
User’s Manual U10905EJ8V1UM
251
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
NOT1
saddr2. bit
0 0 0 0
0 0 1 1
1 0 0 0
1 1 0 0
0 1 1 1
0 0 0 0
0 B2 B1 B0
1 0 0 0
←
Saddr2-offset
→
saddr1. bit
0 1 1 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
Saddr1-offset
→
sfr. bit
0 0 0 0 1 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 1 0 1
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
Sfr-offset
→
X. bit
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
A. bit
PSWL. bit
PSWH. bit
[TDE]. bit
[WHL]. bit
!addr16.bit
0 1 1 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
!!addr24.bit
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
0 1 1 1
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High-w Address
→
←
←
Low Address
Saddr2-offset
→
←
High Address
→
CY
0 1 0 0 0 0 1 0
SET1
saddr2. bit
saddr1. bit
sfr. bit
1 0 1 1
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 B2 B1 B0
1 1 0 0
1 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
→
1 0 1 1
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
←
Saddr1-offset
Sfr-offset
→
→
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 1 0 1
X. bit
A. bit
PSWL. bit
PSWH. bit
[TDE]. bit
[WHL]. bit
!addr16. bit
1 0 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
!!addr24. bit
CY
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
1 0 0 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
←
→
←
→
←
→
0 1 0 0 0 0 0 1
(Continued on next page)
252
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CLR1
saddr2. bit
1 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 B2 B1 B0
1 1 0 0
1 0 0 0
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
←
Saddr2-offset
→
saddr1. bit
sfr. bit
1 0 1 0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
←
Saddr1-offset
Sfr-offset
→
→
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1 1 0 1
X. bit
A. bit
PSWL. bit
PSWH. bit
[TDE]. bit
[WHL]. bit
!addr16.bit
1 0 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address
←
→
←
→
!!addr24.bit
CY
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0
1 0 0 1
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High-w address
→
←
Low Address
→
←
High Address
→
0 1 0 0 0 0 0 0
User’s Manual U10905EJ8V1UM
253
CHAPTER 6 INSTRUCTION SET
(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
PUSH
PSW
sfrp
sfr
0 1 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 0 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 0 0
0 0 1 1
0 0 0 0
1 0 0 1
0 1 1 1
0 1 1 1
0 1 0 1
1 0 0 1
0 1 1 1
1 0 0 0
0 1 1 1
0 1 1 1
0 1 0 0
1 0 0 1
0 1 1 0
1 0 0 1
1 1 0 1
1 1 0 1
1 0 0 1
1 0 1 1
←
←
sfr-offset
sfr-offset
→
→
post
rg
←
post
post
→
1 0 0 0
1 G2 G1 1
PUSHU
POP
post
PSW
sfrp
sfr
←
→
1 1 0 1
1 1 0 1
1 0 0 0
1 0 1 0
←
←
Sfr-offset
Sfr-offset
→
→
post
rg
←
post
post
→
1 0 0 1
1 G2 G1 1
POPU
MOVG
post
←
→
SP, #imm24
0 0 1 0
0 0 0 0
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
←
High-w Byte
→
SP, WHL
WHL, SP
SP, #word
0 0 0 0 0 1 0 1
1 1 1 1 1 0 1 1
0 0 0 0
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 1
0 0 1 0
1 0 1 0
1 0 0 0
ADDWG
SUBWG
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Byte
→
SP, #word
0 0 0 0 1 0 0 1
0 0 1 0
1 0 1 0
←
Low Byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High Byte
←
→
INCG
SP
SP
0 0 0 0 0 1 0 1
0 0 0 0 0 1 0 1
1 1 1 1
1 1 1 1
1 0 0 0
1 0 0 1
DECG
254
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CALL
!addr16
0 0 1 0
0 0 0 0
1 0 0 0
1 0 0 1
←
Low Address
→
←
←
High Address
Low Address
→
→
!!addr20
1 1 1 1
Hi-w Add
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
rp
0 0 0 0 0 1 0 1
0 1 0 1
0 1 0 1
0 1 1 1
0 1 1 1
1 P2 P1 P0
0 G2 G1 1
1 P2 P1 P0
0 G2 G1 1
rg
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
1 0 0 1
1 1 1 T4
0 1 0 1
0 0 0 0
0 1 0 1
0 1 0 1
0 1 0 1
0 0 1 0
0 0 0 0
0 1 0 1
0 1 0 1
0 1 0 1
1 1 1 1
0
[rp]
[rg]
$!addr20
!addr11
[addr5]
←
$addr Low
fa
→
→
←
$addr High
→
CALLF
CALLT
BRK
←
T3 T2 T1 T0
1 1 1 0
0 1 0 1
0 1 1 0
0 1 1 1
1 1 1 1
1 0 0 1
1 0 0 1
BRKCS
RET
RBn
1 1 0 1
1 E2 E1 E0
RETI
RETB
RETCS
RETCSB
!addr16
!addr16
←
Low Address
→
←
←
High Address
Low Address
→
→
1 0 1 1 0 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
User’s Manual U10905EJ8V1UM
255
CHAPTER 6 INSTRUCTION SET
(17) Unconditional branch instruction: BR
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
BR
!addr16
0 0 1 0
0 0 0 0
1 1 0 0
1 0 0 1
←
Low Address
→
←
←
High Address
Low Address
→
→
!!addr20
1 1 1 0
Hi-w Add
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
High Address
→
rp
0 0 0 0 0 1 0 1
0 1 0 0
0 1 0 0
0 1 1 0
0 1 1 0
1 P2 P1 P0
0 G2 G1 1
1 P2 P1 P0
0 G2 G1 1
rg
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 0
0 0 1 1
[rp]
[rg]
$addr20
$!addr20
←
$addr20
$addr Low
→
→
←
←
$addr High
→
(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN,
BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
BNZ
BNE
BZ
$addr20
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
←
←
←
←
←
←
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
→
→
→
→
→
→
$addr20
$addr20
$addr20
$addr20
$addr20
BE
BNC
BNL
BC
BL
BNV
BPO
BV
BPE
BP
$addr20
$addr20
$addr20
1 0 0 0
1 0 0 0
0 0 0 0
0 1 1 0
0 1 1 1
0 1 1 1
←
←
$addr20
$addr20
→
→
BN
BLT
1 1 1 1
1 0 0 0
←
$addr20
→
(Continued on next page)
256
User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
BGE
BLE
BGT
BNH
BH
$addr20
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
1 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 0 1 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
0 B2 B1 B0
←
←
←
←
←
←
$addr20
$addr20
→
→
→
→
→
→
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
BF
saddr2. bit, $addr20
Saddr2-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
$addr20
→
saddr1. bit, $addr20
sfr. bit, $addr20
0 0 1 1 1 1 0 0
0 0 0 0
1 0 0 0
1 0 1 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset $addr20
←
→
←
→
0 0 0 0 1 0 0 0 1 0 1 0
1 B2 B1 B0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
X. bit, $addr20
0 0 0 0 0 0 1 1
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 0 1 0
1 1 0 1
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
←
←
←
←
←
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
→
→
→
→
→
→
A. bit, $addr20
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
PSWL. bit, $addr20
PSWH. bit, $addr20
[TDE]. bit, $addr20
[WHL]. bit, $addr20
!addr16.bit, $addr20
1 0 1 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address $addr20
←
→
←
→
←
→
!!addr24.bit, $addr20
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
←
→
←
→
←
→
BT
saddr2. bit, $addr20
saddr1. bit, $addr20
0 1 1 1
0 0 1 1
0 B2 B1 B0
1 1 0 0
←
Saddr2-offset
→
←
←
$addr20
→
→
0 1 1 1
0 B2 B1 B0
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
$addr20
→
sfr. bit, $addr20
0 0 0 0 1 0 0 0
1 0 1 1
1 B2 B1 B0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
X. bit, $addr20
0 0 0 0 0 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
←
←
←
←
←
←
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
→
→
→
→
→
→
A. bit, $addr20
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
PSWL. bit, $addr20
PSWH. bit, $addr20
[TDE]. bit, $addr20
[WHL]. bit, $addr20
(Continued on next page)
User’s Manual U10905EJ8V1UM
257
CHAPTER 6 INSTRUCTION SET
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
BT
!addr16.bit, $addr20
!!addr24.bit, $addr20
0 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address $addr20
1 0 0 1
1 1 0 1
0 0 0 0
1 0 1 1
0 B2 B1 B0
←
→
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
←
→
←
→
←
→
BTCLR
saddr2, bit, $addr20
saddr1. bit, $addr20
sfr. bit, $addr20
0 0 0 0
1 0 0 0
1 1 0 1
0 B2 B1 B0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
0 0 1 1
1 1 0 0
0 0 0 0
1 0 0 0
1 1 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset $addr20
←
→
←
→
0 0 0 0 1 0 0 0 1 1 0 1
1 B2 B1 B0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
X. bit, $addr20
0 0 0 0 0 0 1 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
1 1 0 1
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 0 0 0
←
←
←
←
←
←
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
→
→
→
→
→
→
A. bit, $addr20
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 0 0
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
1 0 0 1
PSWL. bit, $addr20
PSWH. bit, $addr20
[TDE]. bit, $addr20
[WHL]. bit, $addr20
!addr16.bit, $addr20
1 1 0 1
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address $addr20
←
→
←
→
←
→
!!addr24.bit, $addr20
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
←
→
←
→
←
→
BFSET
saddr2. bit, $addr20
saddr1. bit, $addr20
sfr. bit, $addr20
0 0 0 0
1 0 0 0
1 1 0 0
0 B2 B1 B0
←
Saddr2-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
0 0 1 1
1 1 0 0
0 0 0 0
1 0 0 0
1 1 0 0
0 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Saddr1-offset $addr20
←
→
←
→
0 0 0 0 1 0 0 0 1 1 0 0
1 B2 B1 B0
←
Sfr-offset
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
X. bit, $addr20
0 0 0 0 0 0 1 1
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
1 1 0 0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
0 B2 B1 B0
1 B2 B1 B0
←
←
←
←
←
←
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
→
→
→
→
→
→
A. bit, $addr20
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 0
0 0 1 0
1 1 0 1
1 1 0 1
PSWL. bit, $addr20
PSWH. bit, $addr20
[TDE]. bit, $addr20
[WHL]. bit, $addr20
(Continued on next page)
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Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
BFSET
!addr16.bit, $addr20
!!addr24.bit, $addr20
0 0 0 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Low Address High Address $addr20
1 0 0 1
1 1 0 1
0 0 0 0
1 1 0 0
0 B2 B1 B0
←
→
←
→
←
→
0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 0
1 B2 B1 B0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
High-w Address Low Address High Address
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
$addr20
←
→
←
→
←
→
←
→
DBNZ
B, $addr20
0 0 1 1 0 0 1 1
←
←
←
$addr20
$addr20
→
→
→
C, $addr20
0 0 1 1
0 0 1 1
0 0 1 1
0 0 1 0
1 0 1 1
1 1 0 0
saddr2, $addr20
saddr1, $addr20
Saddr2-offset
←
←
$addr20
→
→
0 0 1 1
1 0 1 1
Saddr1-offset
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
$addr20
→
(19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOV
STBC, #byte
0 0 0 0
1 0 0 1
1 1 0 0
0 0 0 0
←
#byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
#byte
→
WDM, #byte
0 0 0 0 1 0 0 1
1 1 0 0
0 0 1 0
←
#byte
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#byte
←
→
LOCATION locaddr
0 0 0 0
1 0 0 1
1 1 0 0
0 0 0 1
←
locaddr1
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
locaddrh
←
→
SEL
RBn
0 0 0 0 0 1 0 1
1 0 1 0
1 0 1 1
1 1 1 1
1 E2 E1 E0
1 E2 E1 E0
1 1 0 0
RBn. ALT
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 0 0 0
1 0 1 1
1 0 1 0
SWRS
NOP
EI
DI
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CHAPTER 6 INSTRUCTION SET
(20) Special instructions: CHKL, CHKLA
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CHKL
sfr
sfr
0 0 0 0
0 0 0 0
0 1 1 1
0 1 1 1
1 1 0 0
1 1 0 0
1 0 0 0
1 0 0 1
←
←
Sfr address
Sfr address
→
→
CHKLA
Caution The CHKL and CHKLA instructions are not available in the µPD784216, 784216Y, 784218, 784218Y,
784225, 784225Y, 784937 Subseries. Do not execute these instructions. If these instructions are
executed, the following operations will result.
• CHKL instruction ....... After the pin levels of the output pins are read two times, they are
exclusive-ORed. As a result, if the pins checked with this instruction are
used in the port output mode, the exclusive-OR result is always 0 for all
bits, and the Z flag is set to (1).
• CHKLA instruction .... After the pin levels of output pins are read two times, they are exclusive-
ORed. As a result, if the pins checked with this instruction are used in
the port output mode, the exclusive-OR result is always 0 for all bits, and
the Z flag is set to (1) along with that the result is stored in the A register.
(21) String instructions: MOVTBLW, MOVM, MOVBK, XCHM, XCHBK, CMPME, CMPBKE, CMPMNE,
CMPBKNE, CMPMC, CMPBKC, CMPMNC, CMPBKNC
Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
MOVTBLW !addr8, byte
0 0 0 0
1 0 0 1
1 0 1 0
0 0 0 0
←
Low Address
→
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
←
byte
→
MOVM
[TDE +], A
0 0 0 1
0 1 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
[TDE –], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
MOVBK
XCHM
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
[TDE –], A
XCHBK
CMPME
CMPBKE
CMPMNE
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
[TDE –], A
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
[TDE –], A
(Continued on next page)
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Mnemonic
Operands
Operation Code
B1
B4
B7
B2
B5
B3
B6
CMPBKNE
CMPMC
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 0 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 1 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 1
0 1 0 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 1
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
[TDE –], A
CMPBKC
CMPMNC
CMPBKNC
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
[TDE –], A
[TDE +], [WHL +]
[TDE –], [WHL –]
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CHAPTER 6 INSTRUCTION SET
6.5 Number of Instruction Clocks
6.5.1 Execution time of instruction
The execution time for instructions is shown as the number of clocks of fCLK.
The CPU in the 78K/IV Series has an instruction queue, so that another instruction can be prefetched in parallel
while one instruction is executed. Consequently, the actual execution time of an instruction is dependent on the
preceding instruction.
The execution time of an instruction also changes with the number of wait states used for memory access.
Therefore, the accurate execution time of the program cannot be calculated by merely adding the number of execution
clocks of instructions.
The minimum number of execution clocks is shown for instructions except those used for branch operation, such
as BR, CALL, and RET instructions. For the branch instructions, the number of clocks slightly more than the minimum
value is shown.
6.5.2 Definitions for “Clocks” column
(1) Internal ROM
The number of clocks set to 1 if the data to be accessed by an instruction is stored in the internal ROM and
if the IFCH bit, which is bit 7 of the memory mapping mode register (MM), is shown. If the IFCH bit is cleared
to 0, refer to the column of PRAM, EMEM, or SFR.
(2) IRAM
The number of clocks if the data to be accessed by an instruction is stored in the internal high-speed RAM
(the area of addresses FD00H through FEFFH when LOCATION 0H instruction is executed, and the area of
FFD00H through FFEFFH when LOCATION 0FH instruction is executed) is shown.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
(3) PRAM/EMEM/SFR
The number of clocks if the data to be accessed by an instruction is stored in an area of the internal RAM
which is not IRAM, in the external memory (including the external SFR), or in the SFR area is shown.
(4) Others
The number of clocks if no data is accessed by an instruction is shown.
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6.5.3 Explanation of “Clocks” column
(1) Number of clocks for accessing word data
• The number of clocks shown in the PRAM, EMEM, and SFR columns is when the bus width is 16 bits and
when data is located at an even address. If the bus width is 8 bits, or if data is located at an odd address
even though the bus width is 16 bits, add 4 to the number of clocks shown in the table. Note that the width
of the internal RAM is 16 bits. Also, if word data of the internal ROM is located at an odd address, add 4
to the number of clocks.
• If word data is saved to or restored from an odd address by a stack manipulation instruction marked “n”,
add 4 to the coefficient of “n”.
(2) Number of clocks for accessing 3-byte data
The number of clocks shown in the PRAM, EMEM, or SFR column is used when the bus width is 16 bits. If
the bus width is 8 bits, and if data is located at an odd address even though the bus width is 16 bits, add 4
to the number of clocks shown in the table. Note that the bus width of the internal RAM is 16 bits.
(3) If two types of numbers of clocks are shown with each delimited by “/” from the other
If two types of numbers of clocks are shown with each delimited by “/” from the other, two types of numbers
of bytes are shown for that instruction with each delimited by “/” from the other. The execution time of this
kind of instruction is the number of clocks shown at the same side as the number of bytes.
(4) When “n” is shown in “Clocks” column
• When the MACW, MACSW, and MOVTBLW instructions are used, the number specified by operand byte
substitutes for “n”.
• In the case of the SACW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC,
CMPBKE, CMPBKNE, CMPBKC, and CMPBKNC instructions, the value set to the C register on starting
execution of the instruction substitutes for “n”. This number of clocks is the value when the instruction
execution is not stopped by an interrupt or macro service.
• When the shift or rotate instruction is used, the number of bits to be shifted or rotated substitutes for “n”.
• When the stack manipulation instruction is used, the number of registers to be saved to the stack or restored
from the stack substitutes for “n”.
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6.5.4 List of number of clocks
(1) 8-bit data transfer instruction: MOV
(1/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
MOV
r, #byte
2/3
3/4
3
2/3
3/4
–
–
7
saddr, #byte
sfr, #byte
!addr16, #byte
!!addr24, #byte
r, r’
7
5
–
–
–
7
9
6
8
10
–
2/3
1/2
2
2/3
A, r
A, saddr2
r, saddr
3
4
2
4
–
7
3
8
saddr2, A
saddr, r
2
6
3
8
7
A, sfr
2
r, sfr
3
8
sfr, A
2
6
sfr, r
3
8
saddr, saddr’
r, !addr16
!addr16, r
r, !!addr24
!!addr24, r
A, [saddrp]
A, [%saddrg]
A, [TDE +]
A, [WHL +]
A, [TDE –]
A, [WHL –]
A, [TDE]
4
6
14
9
4
9
–
7
6
4
8
5
10
8
10
9
5
–
7
2/3
3/4
1
9/10
14/15
9
7/8
12/13
7
9/10
14/15
9
1
1
1
1
8
9
6
7
8
9
A, [WHL]
A, [VVP]
1
2
A, [UUP]
A, [TDE + byte]
A, [SP + byte]
2
3
10
11
8
9
10
11
3
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(2/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
10
PRAM/EMEM/SFR
10
Others
–
MOV
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24[DE]
A, imm24[A]
A, imm24[HL]
A, imm24[B]
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[saddrp], A
3
3
8
3
5
12
10
10
12
10
5
5
5
2
8
2
2
2
2
2
2
2
2/3
3/4
1
–
6/7
12/13
8
8/9
14/15
10
[%saddrg], A
[TDE +], A
[WHL +], A
1
[TDE –], A
1
[WHL –], A
1
[TDE], A
1
5
7
7
9
[WHL], A
1
[VVP], A
2
[UUP], A
2
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24[DE], A
imm24[A], A
imm24[HL], A
imm24[B], A
3
8
9
8
10
11
10
3
3
3
3
5
10
12
5
5
5
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(3/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
8
Internal ROM
–
PRAM/EMEM/SFR
10
Others
–
MOV
[TDE + A], A
2
2
2
2
2
2
2
2
3
3
2
2
2
2
3
2
2
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
PSWL, #byte
PSWH, #byte
PSWL, A
–
–
7
6
7
PSWH, A
A, PSWL
A, PSWH
r3, #byte
3
4
3
A, r3
r3, A
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(2) 16-bit data transfer instruction: MOVW
(1/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
MOVW
rp, #word
3
4/5
4
3
4
–
8
9
2
3
4
2
3
–
–
8
saddrp, #word
sfrp, #word
!addr16, #word
!!addr24, #word
rp, rp’
6
10
7
11
2
–
AX, saddrp2
rp, saddrp
2
7
3
8
saddrp2, AX
saddrp, rp
2
6
3
7
AX, sfrp
2
7
8
rp, sfrp
3
sfrp, AX
2
6
sfrp, rp
3
7
saddrp, saddrp’
rp, !addr16
4
6
14
9
4
9
–
7
6
!addr16, rp
4
8
rp, !!addr24
!!addr24, rp
AX, [saddrp]
AX, [%saddrg]
AX, [TDE +]
AX, [WHL +]
AX, [TDE –]
AX, [WHL –]
AX, [TDE]
5
10
8
10
9
5
–
7
3/4
3/4
2
10/11
14/15
11
8/9
12/13
9
10/11
14/15
11
2
2
2
2
9
7
9
AX, [WHL]
2
AX, [VVP]
2
AX, [UUP]
2
AX, [TDE + byte]
AX, [SP + byte]
AX, [WHL + byte]
AX, [UUP + byte]
AX, [VVP + byte]
3
10
11
10
8
9
8
10
11
10
3
3
3
3
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CHAPTER 6 INSTRUCTION SET
(2/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
10
Internal ROM
12
PRAM/EMEM/SFR
12
Others
–
MOVW
AX, imm24[DE]
AX, imm24[A]
AX, imm24[HL]
AX, imm24[B]
AX, [TDE + A]
AX, [WHL + A]
AX, [TDE + B]
AX, [WHL + B]
AX, [VVP + DE]
AX, [VVP + HL]
AX, [TDE + C]
AX, [WHL + C]
[saddrp], AX
5
5
5
5
2
10
8
10
2
2
2
2
2
2
2
3/4
3/4
2
–
8/9
12/13
9
10/11
14/15
11
[%saddrg], AX
[TDE +], AX
[WHL +], AX
2
[TDE –], AX
2
[WHL –], AX
2
[TDE], AX
2
7
9
[WHL], AX
2
[VVP], AX
2
[UUP], AX
2
[TDE + byte], AX
[SP + byte], AX
[WHL + byte], AX
[UUP + byte], AX
[VVP + byte], AX
imm24[DE], AX
imm24[A], AX
imm24[HL], AX
imm24[B], AX
3
8
9
8
10
11
10
3
3
3
3
5
10
12
5
5
5
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(3/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
10
Others
–
MOVW
[TDE + A], AX
2
2
2
2
2
2
2
2
8
[WHL + A], AX
[TDE + B], AX
[WHL + B], AX
[VVP + DE], AX
[VVP + HL], AX
[TDE + C], AX
[WHL + C], AX
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(3) 24-bit data transfer instruction: MOVG
(1/2)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
MOVG
rg, #imm24
5
2
5
4
rg, rg’
rg, !!addr24
5
17
–
13
12
9
17
16
!!addr24, rg
5
rg, saddrg
3
17
saddrg, rg
3
7
15
WHL, [%saddrg]
[%saddrg], WHL
WHL, [TDE +]
WHL, [TDE –]
WHL, [TDE]
3/4
3/4
2
21/22
–
17/18
21/22
19
15
12
19
16
2
2
16
WHL, [WHL]
2
WHL, [VVP]
2
WHL, [UUP]
2
WHL, [TDE + byte]
WHL, [SP + byte]
WHL, [WHL + byte]
WHL, [UUP + byte]
WHL, [VVP + byte]
WHL, imm24[DE]
WHL, imm24[A]
WHL, imm24[HL]
WHL, imm24[B]
WHL, [TDE + A]
WHL, [WHL + A]
WHL, [TDE + B]
WHL, [WHL + B]
WHL, [VVP + DE]
WHL, [VVP + HL]
WHL, [TDE + C]
WHL, [WHL + C]
3
17
18
17
13
14
13
17
18
17
3
3
3
3
5
19
17
15
13
19
17
5
5
5
2
2
2
2
2
2
2
2
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CHAPTER 6 INSTRUCTION SET
(2/2)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
19
Others
–
MOVG
[TDE +], WHL
2
2
2
2
2
2
3
3
3
3
3
5
5
5
5
2
2
2
2
2
2
2
2
15
[TDE –], WHL
[TDE], WHL
12
16
[WHL], WHL
[VVP], WHL
[UUP], WHL
[TDE + byte], WHL
[SP + byte], WHL
[WHL + byte], WHL
[UUP + byte], WHL
[VVP + byte], WHL
imm24[DE], WHL
imm24[A], WHL
imm24[HL], WHL
imm24[B], WHL
[TDE + A], WHL
[WHL + A], WHL
[TDE + B], WHL
[WHL + B], WHL
[VVP + DE], WHL
[VVP + HL], WHL
[TDE + C], WHL
[WHL + C], WHL
13
14
13
17
18
17
15
13
19
17
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CHAPTER 6 INSTRUCTION SET
(4) 8-bit data exchange instruction: XCH
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
XCH
r, r’
A, r
2/3
1/2
2
4
4/5
5
A, saddr2
13
14
14
24
15
r, saddr
3
6
r, sfr
3
–
saddr, saddr’
r, !addr16
4
8
4
11
r, !!addr24
5
A, [saddrp]
A, [%saddrg]
A, [TDE +]
2/3
3/4
2
8/9
17/18
14
10/11
21/22
18
A, [WHL +]
A, [TDE –]
2
2
A, [WHL –]
A, [TDE]
2
2
12
16
A, [WHL]
2
A, [VVP]
2
A, [UUP]
2
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24[DE]
A, imm24[A]
A, imm24[HL]
A, imm24[B]
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
3
13
14
13
17
18
17
3
3
3
3
5
15
13
19
17
5
5
5
2
2
2
2
2
2
2
2
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CHAPTER 6 INSTRUCTION SET
(5) 16-bit data exchange instruction: XCHW
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
XCHW
rp, rp’
2
2
4
–
13
AX, saddrp2
rp, saddrp
5
3
6
14
rp, sfrp
3
–
13/14
17/18
3
14
AX, [saddrp]
AX, [%saddrg]
AX, !addr16
3/4
3/4
4
17/18
21/22
3
AX, !!addr24
saddrp, saddrp’
AX, [TDE +]
5
4
4
4
8
24
2
14
18
AX, [WHL +]
AX, [TDE –]
2
2
AX, [WHL –]
AX, [TDE]
2
2
12
16
AX, [WHL]
2
AX, [VVP]
2
AX, [UUP]
2
AX, [TDE + byte]
AX, [SP + byte]
AX, [WHL + byte]
AX, [UUP + byte]
AX, [VVP + byte]
AX, imm24[DE]
AX, imm24[A]
AX, imm24[HL]
AX, imm24[B]
AX, [TDE + A]
AX, [WHL + A]
AX, [TDE + B]
AX, [WHL + B]
AX, [VVP + DE]
AX, [VVP + HL]
AX, [TDE + C]
AX, [WHL + C]
3
13
14
13
17
18
17
3
3
3
3
5
15
13
19
17
5
5
5
2
2
2
2
2
2
2
2
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CHAPTER 6 INSTRUCTION SET
(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP
(1/5)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
ADD
ADDC
SUB
SUBC
AND
OR
A, #byte
2
3
2
r, #byte
4
6/7
–
saddr, #byte
sfr, #byte
3/4
4
12/13
13
r, r’
2/3
4
3/4
3
–
A, saddr2
r, saddr
7
XOR
3
4
8
saddr, r
3
8
14
r, sfr
3
–
8
sfr, r
3
–
14
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, [TDE +]
A, [WHL +]
A, [TDE –]
A, [WHL –]
A, [TDE]
4
8
18
3/4
3/4
3/4
3/4
4
11/12
15/16
–
9/10
13/14
11/12
15/16
8
11/12
15/16
15/16
19/20
10
10
11
–
5
9
11
4
10
11
9
14
5
15
1
11
10
12
11
1
1
1
1
8
10
12
A, [WHL]
1
A, [VVP]
2
A, [UUP]
2
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
3
10
3
3
3
3
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CHAPTER 6 INSTRUCTION SET
(2/5)
Mnemonic
Operands
Bytes
Clocks
IRAM
11
Internal ROM
13
PRAM/EMEM/SFR
13
Others
–
ADD
ADDC
SUB
SUBC
AND
OR
A, imm24[DE]
5
5
5
5
2
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
3
3
3
3
3
5
5
5
5
A, imm24[A]
A, imm24[HL]
A, imm24[B]
A, [TDE + A]
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
11
9
11
XOR
–
10
14
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24[DE], A
imm24[A], A
imm24[HL], A
imm24[B], A
13
14
17
18
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CHAPTER 6 INSTRUCTION SET
(3/5)
Mnemonic
Operands
Bytes
Clocks
IRAM
12
Internal ROM
–
PRAM/EMEM/SFR
16
Others
–
ADD
ADDC
SUB
SUBC
AND
OR
[TDE + A], A
2
2
2
2
2
2
2
2
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
XOR
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(4/5)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
CMP
A, #byte
2
3
2
4
r, #byte
saddr, #byte
sfr, #byte
3/4
4
4/5
–
8/9
9
r, r’
2/3
4
3/4
3
–
A, saddr2
7
r, saddr
3
4
8
saddr, r
3
6
10
r, sfr
3
–
9
sfr, r
3
10
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, [TDE +]
A, [WHL +]
A, [TDE –]
A, [WHL –]
A, [TDE]
4
6
9/10
13/14
9/10
13/14
8
14
3/4
3/4
3/4
3/4
4
11/12
15/16
11/12
15/16
10
11/12
15/16
11/12
15/16
10
5
11
9
11
4
10
8
10
5
11
9
11
1
11
9
11
1
1
1
1
10
12
8
10
12
A, [WHL]
1
A, [VVP]
2
A, [UUP]
2
A, [TDE + byte]
A, [SP + byte]
A, [WHL + byte]
A, [UUP + byte]
A, [VVP + byte]
A, imm24[DE]
A, imm24[A]
A, imm24[HL]
A, imm24[B]
3
10
3
3
3
3
5
13
11
13
5
5
5
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CHAPTER 6 INSTRUCTION SET
(5/5)
Mnemonic
Operands
Bytes
Clocks
IRAM
9
Internal ROM
11
PRAM/EMEM/SFR
11
Others
–
CMP
A, [TDE + A]
2
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
3
3
3
3
3
5
5
5
5
2
2
2
2
2
2
2
2
A, [WHL + A]
A, [TDE + B]
A, [WHL + B]
A, [VVP + DE]
A, [VVP + HL]
A, [TDE + C]
A, [WHL + C]
[TDE +], A
10
8
10
[WHL +], A
[TDE –], A
[WHL –], A
[TDE], A
[WHL], A
[VVP], A
[UUP], A
[TDE + byte], A
[SP + byte], A
[WHL + byte], A
[UUP + byte], A
[VVP + byte], A
imm24[DE], A
imm24[A], A
imm24[HL], A
imm24[B], A
[TDE + A], A
[WHL + A], A
[TDE + B], A
[WHL + B], A
[VVP + DE], A
[VVP + HL], A
[TDE + C], A
[WHL + C], A
13
11
13
14
12
12
10
14
12
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CHAPTER 6 INSTRUCTION SET
(7) 16-bit operation instructions: ADDW, SUBW, CMPW
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
ADDW
SUBW
AX, #word
3
4
3
5
3
rp, #word
rp, rp’
2
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
7
9
3
5
8
3
14
9
3
–
sfrp, rp
3
–
13
saddrp, #word
sfrp, #word
saddrp, saddrp’
AX, #word
rp, #word
rp, rp’
4/5
5
7/8
–
14
20
–
4
8
CMPW
3
–
3
–
4
5
2
3
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
7
9
3
5
–
3
3
sfrp, rp
3
saddrp, #word
sfrp, #word
saddrp, saddrp’
4/5
5
5/6
–
9
10
4
6
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CHAPTER 6 INSTRUCTION SET
(8) 24-bit operation instructions: ADDG, SUBG
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
ADDG
SUBG
rg, rg’
2
5
3
6
8
rg, #imm24
WHL, saddrg
13
19
(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
MULU
r
2/3
2
–
–
–
–
–
11/12
15
–
–
–
–
–
–
–
–
–
–
MULUW
MULW
DIVUW
DIVUX
rp
rp
r
2
14
2/3
2
23/24
43
rp
(10) Special operation instructions: MACW, MACSW, SACW
Mnemonic
Operands
Bytes
Clocks
Internal ROM
IRAM
PRAM/EMEM/SFR
Others
MACW
MACSW
SACW
byte
byte
3
3
4
–
–
–
5 + 21n
5 + 21n
4 + 19n
–
–
–
–
–
[TDE +], [WHL +]
4 + 23n
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CHAPTER 6 INSTRUCTION SET
(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
INC
r
1/2
2/3
2/1
3/4
2
2/3
5/6
3/2
6/7
4
–
11/12
–
DEC
saddr
rp
INCW
DECW
INCG
DECG
–
–
–
–
saddrp
rg
12/13
–
(12) Adjustment instructions: ADJBA, ADJBS, CVTBW
Mnemonic
Operands
Bytes
Clocks
Internal ROM
IRAM
PRAM/EMEM/SFR
Others
ADJBA
ADJBS
CVTBW
2
2
1
–
–
–
5
5
3
–
–
–
–
–
–
(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4
Mnemonic
Operands
Bytes
2/3
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
–
ROR
r, n
5 + n/6 + n
ROL
RORC
ROLC
SHR
SHL
SHRW
SHLW
ROR4
ROL4
rp, n
2
2
–
–
5 + n
11
–
–
–
mem3
15
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CHAPTER 6 INSTRUCTION SET
(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1
(1/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
MOV1
CY, saddr.bit
3/4
3
6/7
–
10/11
10
CY, sfr.bit
CY, X.bit
2
5
–
CY, A.bit
2
CY, PSWL.bit
CY, PSWH.bit
CY, [TDE].bit
CY, [WHL].bit
CY, !addr16.bit
CY, !!addr24.bit
saddr.bit, CY
sfr.bit, CY
2
–
9
5
2
2
11
16
–
11
16
2
5
14
6
3/4
3
5/6
–
13/14
13
X.bit, CY
2
6
–
A.bit, CY
2
PSWL.bit, CY
PSWH.bit, CY
[TDE].bit, CY
[WHL].bit, CY
!addr16.bit, CY
!!addr24.bit, CY
2
–
8
7
2
2
10
13
14
2
5
15
6
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User’s Manual U10905EJ8V1UM
CHAPTER 6 INSTRUCTION SET
(2/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
10/11
Others
–
AND1
OR1
CY, saddr.bit
3/4
3/4
3
6/7
CY, /saddr.bit
CY, sfr.bit
–
10
–
CY, /sfr.bit
3
CY, X.bit
2
5
CY, /X.bit
2
CY, A.bit
2
CY, /A.bit
2
CY, PSWL.bit
CY, /PSWL.bit
CY, PSWH.bit
CY, /PSWH.bit
CY, [TDE].bit
CY, /[TDE].bit
CY, [WHL].bit
CY, /[WHL].bit
CY, !addr16.bit
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
CY, saddr.bit
CY, /sfr.bit
2
2
2
2
2
11
16
–
9
11
16
2
2
2
5
14
5
6
6
XOR1
3/4
3
6/7
–
10/11
10
CY, X.bit
2
5
–
CY, A.bit
2
CY, PSWL.bit
CY, PSWH.bit
CY, [TDE].bit
CY, [WHL].bit
CY, !addr16.bit
CY, !!addr24.bit
2
–
9
5
2
2
11
16
11
16
2
5
14
6
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CHAPTER 6 INSTRUCTION SET
(3/3)
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
NOT1
saddr.bit
3/4
3
5/6
–
13/14
13
sfr.bit
X.bit
2
5
–
A.bit
2
PSWL.bit
PSWH.bit
[TDE].bit
[WHL].bit
!addr16.bit
!!addr24.bit
CY
2
–
7
6
2
2
10
13
14
2
5
15
6
1
–
4/5
–
2
12/13
13
SET1
CLR1
saddr.bit
sfr.bit
2/3
3
X.bit
2
5
–
A.bit
2
PSWL.bit
PSWH.bit
[TDE].bit
[WHL].bit
!addr16.bit
!!addr24.bit
CY
2
–
10
13
–
7
6
2
2
14
2
5
15
2
6
1
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CHAPTER 6 INSTRUCTION SET
(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
Others
–
PUSH
PSW
sfrp
sfr
1
3
3
2
2
2
1
3
3
2
2
2
5
2
2
4
5
7
10
14
post
rg
4 + 5n
12
4 + 7n
16
PUSHU
POP
post
PSW
sfrp
sfr
–
8
6 + 5n
7
6 + 7n
9
–
–
15
14
16
post
rg
4 + 8n
17
4 + 6n
13
4 + 8n
17
POPU
MOVG
post
7 + 8n
–
7 + 6n
–
7 + 8n
–
–
5
SP, #imm24
SP, WHL
WHL, SP
ADDWG
SUBWG
INCG
SP, #word
–
–
–
–
–
–
5
5
SP
2
DECG
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CHAPTER 6 INSTRUCTION SET
(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
–
CALL
!addr16
3
4
2
2
2
2
3
2
1
1
2
1
1
1
3
4
–
–
–
–
19
22
20
22
24
29
19
19
22
23
–
23
26
24
26
30
37
23
23
28
29
–
!!addr20
rp
rg
Note
[rp]
30
Note
[rg]
37
$!addr20
!addr11
[addr5]
–
–
CALLF
CALLT
BRK
–
–
Note
28
–
–
–
BRKCS
RET
RBn
13
–
21
22
21
–
17
18
17
–
21
22
21
–
RETI
–
RETB
RETCS
RETCSB
–
!addr16
!addr16
14
14
–
–
–
Note When the stack is PRAM or EMEM
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CHAPTER 6 INSTRUCTION SET
(17) Unconditional branch instruction: BR
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
11
12
11
12
–
BR
!addr16
3
4
2
2
2
2
2
3
–
–
–
–
–
–
!!addr20
rp
–
–
–
rg
–
–
–
[rp]
16
22
–
14
18
–
16
22
–
[rg]
–
$addr20
$!addr20
10
11
–
–
–
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CHAPTER 6 INSTRUCTION SET
(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN,
BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
(1/4)
Mnemonic
Operands
Bytes
Clocks
Branches
Not
Branch
Internal ROM
–
IRAM
–
PRAM/EMEM/SFR Others
BNZ
BNE
BZ
$addr20
2
2
2
2
2
2
2
3
3
3
3
3
3
3
–
–
–
–
–
–
–
10
10
10
10
10
10
10
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
–
–
–
–
–
–
–
–
–
–
–
–
BE
BNC
BNL
BC
BL
BNV
BPO
BV
BPE
BP
BN
BLT
BGE
BLE
BGT
BNH
BH
$addr20
$addr20
$addr20
$addr20
$addr20
$addr20
3
3
3
3
3
3
4
4
4
4
4
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
11
11
11
11
11
11
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CHAPTER 6 INSTRUCTION SET
(2/4)
Mnemonic
Operands
saddr.bit, $addr20
sfr.bit, $addr20
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
BF
4/5
4
–
–
14/15
7/8
–
18
11
18
11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X.bit, $addr20
3
–
13
6
–
–
A.bit, $addr20
3
–
13
6
–
–
–
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
–
–
13
6
–
–
3
–
–
13
6
–
–
3
19
12
–
17
10
22
15
22
15
19
12
24
17
24
17
6
–
7
–
–
Remark The number of clocks differs depending on the following cases. Therefore, two types of numbers of clocks
are shown for each operand with one type shown at the top and the other at the bottom.
Top
: Branches (internal ROM high-speed fetch, etc.)
Bottom : Does not branch
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CHAPTER 6 INSTRUCTION SET
(3/4)
Mnemonic
Operands
saddr.bit, $addr20
sfr.bit, $addr20
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
BT
3/4
4
–
–
13/14
6/7
–
17
10
18
11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X.bit, $addr20
3
–
13
6
–
–
A.bit, $addr20
3
–
13
6
–
–
–
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
–
–
13
6
–
–
3
–
–
13
6
–
–
3
19
12
–
17
10
22
15
22
15
19
12
24
17
24
17
6
–
7
–
–
Remark The number of clocks differs depending on the following cases. Therefore, two types of numbers of clocks
are shown for each operand with one type shown at the top and the other at the bottom.
Top
: Branches (internal ROM high-speed fetch, etc.)
Bottom : Does not branch
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CHAPTER 6 INSTRUCTION SET
(4/4)
Mnemonic
Operands
saddr.bit, $addr20
sfr.bit, $addr20
X.bit, $addr20
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
BTCLR
BFSET
4/5
4
–
–
16/17
7/8
–
24
15
24
15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
–
15
6
–
–
A.bit, $addr20
3
–
15
6
–
–
–
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
B, $addr20
3
–
–
15
6
–
–
3
–
–
16
6
–
–
3
–
21
12
24
15
24
15
–
25
16
26
17
26
17
–
–
6
–
–
7
–
–
DBNZ
2
12
4
–
–
C, $addr20
2
12
4
–
–
–
–
saddr, $addr20
3
21
5
17
5
21
5
4
22
6
18
6
22
6
Remark The number of clocks differs depending on the following cases. Therefore, two types of numbers of clocks
are shown for each operand with one type shown at the top and the other at the bottom.
Top
: Branches (internal ROM high-speed fetch, etc.)
Bottom : Does not branch
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CHAPTER 6 INSTRUCTION SET
(19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
–
PRAM/EMEM/SFR
–
Others
13
MOV
STBC, #byte
WDM, #byte
LOCATION locaddr
4
4
4
2
2
2
1
1
1
–
–
–
–
–
–
–
13
3
SEL
RBn
RBn, ALT
SWRS
NOP
EI
–
–
–
–
–
–
–
–
–
–
–
–
4
2
2
2
DI
(20) Special instructions: CHKL, CHKLA
Mnemonic
Operands
Bytes
Clocks
Internal ROM
IRAM
PRAM/EMEM/SFR
Others
CHKL
sfr
sfr
3
3
–
–
–
–
14
14
–
–
CHKLA
Caution The CHKL and CHKLA instructions are not available in the µPD784216A, 784216AY, 784218A,
784218AY, 784225, 784225Y, 784938A Subseries. Do not execute these instructions. If these
instructions are executed, the following operations will result.
• CHKL instruction ....... After the pin levels of the output pins are read two times, they are
exclusive-ORed. As a result, if the pins checked with this instruction are
used in the port output mode, the exclusive-OR result is always 0 for all
bits, and the Z flag is set to (1).
• CHKLA instruction .... After the pin levels of output pins are read two times, they are exclusive-
ORed. As a result, if the pins checked with this instruction are used in
the port output mode, the exclusive-OR result is always 0 for all bits, and
the Z flag is set to (1) along with that the result is stored in the A register.
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CHAPTER 6 INSTRUCTION SET
(21) String instructions: MOVTBLW,MOVM,XCHM,MOVBK,XCHBK,CMPME,CMPMNE,CMPMC,CMPMNC,
CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
Mnemonic
Operands
Bytes
Clocks
IRAM
Internal ROM
PRAM/EMEM/SFR
Others
MOVTBLW !addr16, byte
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
–
–
7 + 5n
3 + 8n
–
–
–
MOVM
[TDE +], A
3 + 10n
[TDE –], A
XCHM
[TDE +], A
–
3 + 14n
3 + 20n
–
–
–
–
–
–
–
–
–
–
–
[TDE –], A
Note 1
Note 2
Note 3
MOVBK
XCHBK
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], A
3 + 17n
3 + 13n
3 + 21n
3 + 17n
Note 2
Note 3
–
3 + 29n
CMPME
CMPMNE
CMPMC
CMPMNC
CMPBKE
CMPBKNE
CMPBKC
CMPBKNC
3 + 12n
3 + 12n
3 + 12n
3 + 12n
3 + 10n
3 + 12n
3 + 12n
3 + 12n
3 + 12n
[TDE –], A
[TDE +], A
3 + 10n
3 + 10n
3 + 10n
[TDE –], A
[TDE +], A
[TDE –], A
[TDE +], A
[TDE –], A
Note 1
Note 2
Note 3
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
[TDE +], [WHL +]
[TDE –], [WHL –]
3 + 19n
3 + 15n
3 + 15n
3 + 15n
3 + 15n
3 + 19n
Note 1
Note 2
Note 2
Note 2
Note 3
3 + 19n
3 + 19n
Note 1
Note 3
3 + 19n
3 + 19n
Note 1
Note 3
3 + 19n
3 + 19n
Notes 1. When the memory specified by the WHL register is the internal ROM and the memory specified by the
TDE register is PRAM or EMEM
2. If both the transfer source and destination memories are IRAM
3. If both the transfer source and destination memories are PRAM or EMEM
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
This chapter describes the instructions of 78K/IV Series products. Each instruction is described on a mnemonic
basis, with a number of operands covered together.
The basic organization of the instruction descriptions is shown on the following page.
Refer to CHAPTER 6 INSTRUCTION SET for the number of bytes in the instructions, and the operation codes.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Description Example
Mnemonic
Full name
Move
Byte Data Transfer
MOV
Meaning of Instruction
MOV dst, src : Shows the basic description format of the instruction.
dst ← src : Shows the operation of the instruction using symbols.
[Instruction format]
[Operation]
[Operands]
: Shows the operands that can be specified in this instruction. See CHAPTER 6
INSTRUCTION SET for an explanation of the operand symbols.
Mnemonic
Operands
Mnemonic
Operands
[saddrp], A
MOV
r, #byte
MOV
~
~
~
~
saddr, #byte
A, saddr2
saddr2, A
A, mem
[%saddrg], A
mem, A
A, r3
~
~
~
~
~
~
~
~
~
~
~
~
r3, A
[Flags]
: Shows the operation of flags changed by execution of the instruction.
The operation symbols for each flag are shown in the legend below.
S
Z
AC
P/V
CY
Legend
Symbol
Meaning
Blank
No change
0
1
Cleared to 0
Set to 1
×
Set or cleared depending on result
P/V flag operates as parity flag
P/V flag operates as overflow flag
Previously saved value is restored
P
V
R
[Description]
: Explains the detailed operation of the instruction.
• Transfers the contents of the source operand (src) specified by the 2nd operand to the destination operand (dst)
specified by the 1st operand.
[Coding example]
MOV A, #4DH ; Transfers 4DH to A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.1 8-bit Data Transfer Instruction
There is one 8-bit data transfer instruction, a follows:
MOV ... 297
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move
MOV
Byte Data Transfer
[Instruction format]
[Operation]
MOV dst, src
dst ← src
[Operands]
Mnemonic
Operands (dst, src)
Mnemonic
Operands (dst, src)
MOV
r, #byte
MOV
r, !!addr24
!!addr24, r
A, [saddrp]
A, [%saddrg]
A, mem
saddr, #byte
sfr, #byte
!addr16, #byte
!!addr24, #byte
r, r’
[saddrp], A
[%saddrg], A
mem, A
A, r
A, saddr2
r, saddr
PSWL, #byte
PSWH, #byte
PSWL, A
PSWH, A
A, PSWL
A, PSWH
r3, #byte
saddr2, A
saddr, r
A, sfr
r, sfr
sfr, A
sfr, r
saddr, saddr’
r, !addr16
!addr16, r
A, r3
r3, A
[Flags]
In case of PSWL, #byte
and PSWL, A operands
In other cases
S
Z
AC
P/V
CY
S
Z
AC
P/V
CY
×
×
×
×
×
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Description]
• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand
(dst) specified by the 1st operand.
• No interrupts or macro service requests are acknowledged between a MOV PSWL, #byte instruction or MOV
PSWL, A instruction and the following instruction.
• Instructions with r3 (T, U, V, or W register) as an operand should only be used when the higher 8 bits of the
address are set when a 78K/0, 78K/I, 78K/II, or 78K/III Series program is used. Also, if possible, the program
should be amended so that r3 need not be specified directly.
[Coding example]
MOV A, #4DH ; Transfers 4DH to A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.2 16-bit Data Transfer Instruction
There is one 16-bit data transfer instruction, as follows:
MOVW ... 300
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move Word
MOVW
Word Data Transfer
[Instruction format]
[Operation]
MOVW dst, src
dst ← src
[Operands]
Mnemonic
Operands (dst, src)
Mnemonic
Operands (dst, src)
sfrp, rp
MOVW
rp, #word
MOVW
saddrp, #word
sfrp, #word
!addr16, #word
!!addr24, #word
rp, rp’
saddrp, saddrp’
rp, !addr16
!addr16, rp
rp, !!addr24
!!addr24, rp
AX, [saddrp]
AX, [%saddrg]
AX, mem
AX, saddrp2
rp, saddrp
saddr2, AX
saddrp, rp
AX, sfrp
[saddrp], AX
[%saddrg], AX
mem, AX
rp, sfrp
sfrp, AX
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand
(dst) specified by the 1st operand.
• The following caution should be noted if all the following conditions apply when a 78K/0, 78K/I, 78K/II, or
78K/III Series program is used.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Conditions]
• An instruction in which rp is specified as an operand is used .
• DE, HL, VP, or UP is actually written for rp .
• DE, HL, VP, or UP is used as an address pointer
[Caution]
Ensure that the contents of the T, W, V, or U register that indicates the higher 8 bits of the address pointer are
coordinated with DE, HL, VP, or UP that indicates the lower 16 bits, and if program amendment is possible,
change the program so that a 24-bit manipulation instruction is used.
[Coding example]
MOVW AX, [WHL] ; Transfers the contents of memory indicated by the WHL register to the AX register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.3 24-bit Data Transfer Instruction
There is one 24-bit data transfer instruction, as follows:
MOVG ... 303
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Note
Move G
24-Bit Data Transfer
MOVG
[Instruction format]
MOVG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
[Operation]
[Operands]
dst ← src
Mnemonic
Operands (dst, src)
rp, #imm24
MOVG
rg, rg’
rg, !!addr24
!!addr24, rg
rg, saddrg
saddrg, rg
WHL, [%saddrg]
[%saddrg], WHL
WHL, mem1
mem1, WHL
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand
(dst) specified by the 1st operand.
[Coding example]
MOVG VVP, SADG ; Transfers the 24-bit data in address SADG that can be accessed by short direct addressing
to the VVP register.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.4 8-bit Data Exchange Instruction
There is one 8-bit data exchange instruction, as follows:
XCH ... 305
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Exchange
XCH
Byte Data Exchange
[Instruction format]
[Operation]
XCH dst, src
dst ↔ src
[Operands]
Mnemonic
Operands (dst, src)
XCH
r, r’
A, r
A, saddr2
r, saddr
r, sfr
saddr, saddr’
r, !addr16
r, !!addr24
A, [saddrp]
A, [%saddrg]
A, mem
[Flags]
S
Z
AC
P/V
CY
[Description]
• Exchanges the contents of the 1st operand and 2nd operand.
[Coding example]
XCH B, D ; Exchanges the contents of the B register with the contents of the D register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.5 16-bit Data Exchange Instruction
There is one 16-bit data exchange instruction, as follows:
XCHW ... 307
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Exchange
XCHW
Word Data Exchange
[Instruction format]
[Operation]
XCHW dst, src
dst ↔ src
[Operands]
Mnemonic
Operands (dst, src)
XCHW
rp, rp’
AX, saddrp2
rp, saddrp
rp, sfrp
AX, [saddrp]
AX, [%saddrg]
AX, !addr16
AX, !!addr24
saddrp, saddrp’
AX, mem
[Flags]
S
Z
AC
P/V
CY
[Description]
• Exchanges the contents of the 1st operand and 2nd operand.
• The following caution should be noted if all the following conditions apply when a 78K/0, 78K/I, 78K/II, or
78K/III Series program is used.
[Conditions]
• An instruction in which rp is specified as an operand is used
• DE, HL, VP, or UP is actually written for rp
• DE, HL, VP, or UP is used as an address pointer
[Caution]
Ensure that the contents of the T, W, V, or U register that indicates the higher 8 bits of the address pointer are
coordinated with DE, HL, VP, or UP that indicates the lower 16 bits, and if program amendment is possible,
change the program so that a 24-bit manipulation instruction is used.
[Coding example]
XCHW AX, mem ; Exchanges the contents of the AX register with the memory contents addressed by memory
addressing
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7.6 8-bit Operation Instructions
8-bit operation instructions are as follows:
ADD ... 309
ADDC ... 310
SUB ... 311
SUBC ... 312
CMP ... 313
AND ... 315
OR ... 316
XOR ... 317
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Add
ADD
Byte Data Addition
[Instruction format]
[Operation]
ADD dst, src
dst, CY ← dst + src
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
ADD
ADD
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
saddr, r
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by
the 1st operand, and the result is stored in the CY flag and destination operand (dst).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the addition, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise.
• The AC flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the addition, and cleared (0)
otherwise.
• The P/V flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as
a result of the addition (when overflow is generated by a two’s complement type operation), or if a carry is not
generated out of bit 6 into bit 7 and a carry is generated out of bit 7 (when underflow is generated by a two’s
complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a carry is generated out of bit 7 as a result of the addition, and cleared (0) otherwise.
[Coding example]
ADD CR11, #56H ; Adds 56H to the value in register CR11, and stores the result in register CR11
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Add with Carry
ADDC
Byte Data Addition including Carry
[Instruction format]
[Operation]
ADDC dst, src
dst, CY ← dst + src + CY
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
ADDC
ADDC
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
A, !!addr24
!addr16, A
saddr, r
!!addr24, A
A, mem
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand and the CY flag are added to the destination operand
(dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the CY flag. This
instruction is mainly used when performing multiple byte addition.
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the addition, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise.
• The AC flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the addition, and cleared (0)
otherwise.
• The P/V flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as
a result of the addition (when overflow is generated by a two’s complement type operation), or if a carry is not
generated out of bit 6 into bit 7 and a carry is generated out of bit 7 (when underflow is generated by a two’s
complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a carry is generated out of bit 7 as a result of the addition, and cleared (0) otherwise.
[Coding example]
ADDC A, 12345H [B] ; Adds the contents of address (12345H + (B register)) and the CY flag to the A register,
and stores the result in the A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Subtract
SUB
Byte Data Subtraction
[Instruction format]
[Operation]
SUB dst, src
dst, CY ← dst – src
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
SUB
SUB
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
saddr, r
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified
by the 1st operand, and the result is stored in the destination operand (dst) and the CY flag.
• The destination operand (dst) can be cleared to 0 by making the source operand (src) and destination operand
(dst) the same.
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as
a result of the subtraction (when underflow is generated by a two’s complement type operation), or if a borrow
is not generated out of bit 6 into bit 7 and a borrow is generated in bit 7 (when overflow is generated by a two’s
complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
[Coding example]
SUB D, L ; Subtracts the L register from the D register and stores the result in the D register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Subtract with Carry
Byte Data Subtraction including Carry
SUBC
[Instruction format]
[Operation]
SUBC dst, src
dst, CY ← dst – src – CY
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
SUBC
Operands (dst, src)
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
SUBC
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
A, !!addr24
!addr16, A
saddr, r
!!addr24, A
A, mem
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand and the CY flag are subtracted from the destination
operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the CY
flag. The CY flag is subtracted from the LSB. This instruction is mainly used when performing multiple byte
subtraction.
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as
a result of the subtraction (when underflow is generated by a two’s complement type operation), or if a borrow
is not generated out of bit 6 into bit 7 and a borrow is generated in bit 7 (when overflow is generated by a two’s
complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
[Coding example]
SUBC A, [TDE+] ; Subtracts the contents of the TDE register address and the CY flag from the A register, and
stores the result in the A register (the TDE register is incremented after the subtraction)
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare
CMP
Byte Data Comparison
[Instruction format]
[Operation]
CMP dst, src
dst – src
[Operands]
Mnemonic
Operands (dst, src)
Mnemonic
Operands (dst, src)
CMP
A, #byte
r, #byte
saddr, #byte
sfr, #byte
r, r’
CMP
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
A, saddr2
r, saddr
saddr, r
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
CY
×
×
×
V
×
[Description]
• The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified
by the 1st operand.
The result of the subtraction is not stored anywhere, and only the S, Z, AC, P/V, and CY flags are changed.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 7 and a borrow is not generated in bit 6 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 7 and a borrow is generated in bit 6 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Coding example]
CMP SADG1, SADG2 ; Subtracts the contents of address SADG2 that can be accessed by short direct addressing
from the contents of address SADG1 that can be accessed by short direct addressing,
and changes the flags only (comparison of the contents of address SADG1 and the
contents of address SADG2)
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
And
AND
Byte Data Logical Product
[Instruction format]
[Operation]
AND dst, src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
AND
AND
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
A, !!addr24
!addr16, A
saddr, r
!!addr24, A
A, mem
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
P
CY
×
×
[Description]
• The bit-wise logical sum of the destination operand (dst) specified by the 1st operand and the source operand
(src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the logical product operation, and cleared (0) otherwise.
• The Z flag is set (1) if all bits are 0 as a result of the logical product operation, and cleared (0) otherwise.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the logical product operation is even, and
cleared (0) otherwise.
[Coding example]
AND SADG, #11011100B ; Finds the bit-wise logical product of the contents of address SADG that can be
accessed by short direct addressing and 11011100B, and stores the result in SADG
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Or
OR
Byte Data Logical Sum
[Instruction format]
[Operation]
OR dst, src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
OR
OR
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
saddr, r
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
P
CY
×
×
[Description]
• The bit-wise logical sum of the destination operand (dst) specified by the 1st operand and the source operand
(src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the logical sum operation, and cleared (0) otherwise.
• The Z flag is set (1) if all bits are 0 as a result of the logical sum operation, and cleared (0) otherwise.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the logical sum operation is even, and
cleared (0) otherwise.
[Coding example]
OR A, !!12345H ; Finds the bit-wise logical sum of the contents of the A register and address 12345H, and stores
the result in the A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Exclusive Or
XOR
Byte Data Exclusive Logical Sum
[Instruction format]
[Operation]
XOR dst, src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
A, #byte
Mnemonic
Operands (dst, src)
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
XOR
XOR
r, #byte
saddr, #byte
sfr, #byte
r, r’
A, saddr2
r, saddr
A, !!addr24
!addr16, A
saddr, r
!!addr24, A
A, mem
r, sfr
sfr, r
mem, A
saddr, saddr’
[Flags]
S
Z
AC
P/V
P
CY
×
×
[Description]
• The bit-wise exclusive logical sum of the destination operand (dst) specified by the 1st operand and the source
operand (src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• Selecting #0FFH as the source operand (src) in this instruction results in logical negation of all the bits of the
destination operand (dst).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the exclusive logical sum operation, and cleared (0)
otherwise.
• The Z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and cleared (0) otherwise.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the exclusive logical sum operation is
even, and cleared (0) otherwise.
[Coding example]
XOR C, P2 ; Finds the bit-wise exclusive logical sum of the C register and P2 register, and stores the result in
the C register
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7.7 16-bit Operation Instructions
16-bit operation instructions are as follows:
ADDW ... 319
SUBW ... 321
CMPW ... 323
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Add Word
ADDW
Word Data Addition
[Instruction format]
[Operation]
ADDW dst, src
dst, CY ← dst + src
[Operands]
Mnemonic
Operands (dst, src)
AX, #word
rp, #word
ADDW
rp, rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
sfrp, rp
saddrp, #word
sfrp, #word
saddrp, saddrp’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by
the 1st operand, and the result is stored in the destination operand (dst).
• The S flag is set (1) if bit 15 of dst is set (1) as a result of the addition, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise.
• The AC flag is undefined as a result of the addition.
• The P/V flag is set (1) if a carry is generated out of bit 14 into bit 15 and a carry is not generated out of bit 15
as a result of the addition (when overflow is generated by a two’s complement type operation), or if a carry is
not generated out of bit 14 into bit 15 and a carry is generated out of bit 15 (when underflow is generated by
a two’s complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a carry is generated out of bit 15 as a result of the addition, and cleared (0) otherwise.
• The following caution should be noted if all the following conditions apply when a 78K/0, 78K/I, 78K/II, or
78K/III Series program is used.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Conditions]
• An instruction in which rp is specified as an operand is used
• DE, HL, VP, or UP is actually written for rp
• DE, HL, VP, or UP is used as an address pointer
[Caution]
Ensure that the contents of the T, W, V, or U register that indicates the higher 8 bits of the address pointer are
coordinated with DE, HL, VP, or UP that indicates the lower 16 bits, and if program amendment is possible,
change the program so that a 24-bit manipulation instruction is used.
[Coding example]
ADDW BC, #0ABCDH ; Adds 0ABCDH to the BC register, and stores the result in the BC register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Subtract Word
SUBW
Word Data Subtraction
[Instruction format]
[Operation]
SUBW dst, src
dst, CY ← dst – src
[Operands]
Mnemonic
Operands (dst, src)
AX, #word
rp, #word
SUBW
rp, rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
sfrp, rp
saddrp, #word
sfrp, #word
saddrp, saddrp’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified
by the 1st operand, and the result is stored in the destination operand (dst) and the CY flag.
• The destination operand (dst) can be cleared to 0 by making the source operand (src) and destination operand
(dst) the same.
• The S flag is set (1) if bit 15 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise.
• The AC flag is undefined as a result of the subtraction.
• The P/V flag is set (1) if a borrow is generated out of bit 14 into bit 15 and a borrow is not generated in bit 15
as a result of the subtraction (when underflow is generated by a two’s complement type operation), or if a borrow
is not generated out of bit 14 into bit 15 and a borrow is generated in bit 15 (when overflow is generated by a
two’s complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 15 as a result of the subtraction, and cleared (0) otherwise.
• The following caution should be noted if all the following conditions apply when a 78K/0, 78K/I, 78K/II, or
78K/III Series program is used.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Conditions]
• An instruction in which rp is specified as an operand is used
• DE, HL, VP, or UP is actually written for rp
• DE, HL, VP, or UP is used as an address pointer
[Caution]
Ensure that the contents of the T, W, V, or U register that indicates the higher 8 bits of the address pointer are
coordinated with DE, HL, VP, or UP that indicates the lower 16 bits, and if program amendment is possible,
change the program so that a 24-bit manipulation instruction is used.
[Coding example]
SUBW CR01, AX ; Subtracts the contents of the AX register from the contents of the CR01 register and stores
the result in the CR01 register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Word
CMPW
Word Data Comparison
[Instruction format]
[Operation]
CMPW dst, src
dst – src
[Operands]
Mnemonic
Operands (dst, src)
CMPW
AX, #word
rp, #word
rp, rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
sfrp, rp
saddrp, #word
sfrp, #word
saddrp, saddrp’
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified
by the 1st operand. The result of the subtraction is not stored anywhere, and only the Z, AC, and CY flags are
changed.
• The S flag is set (1) if bit 15 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise.
• The AC flag is undefined as a result of the subtraction.
• The P/V flag is set (1) if a borrow is generated out of bit 14 into bit 15 and a borrow is not generated in bit 15
as a result of the subtraction (when underflow is generated by a two’s complement type operation), or if a borrow
is not generated out of bit 14 into bit 15 and a borrow is generated in bit 15 (when overflow is generated by a
two’s complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 15 as a result of the subtraction, and cleared (0) otherwise.
• The following caution should be noted if all the following conditions apply when a 78K/0, 78K/I, 78K/II, or
78K/III Series program is used.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Conditions]
• An instruction in which rp is specified as an operand is used
• DE, HL, VP, or UP is actually written for rp
• DE, HL, VP, or UP is used as an address pointer
[Caution]
Ensure that the contents of the T, W, V, or U register that indicates the higher 8 bits of the address pointer are
coordinated with DE, HL, VP, or UP that indicates the lower 16 bits, and if program amendment is possible,
change the program so that a 24-bit manipulation instruction is used.
[Coding example]
CMPW AX, SADG ; Subtracts the word data in address SADG that can be accessed by short direct addressing
from the AX register, and changes the flags only (comparison of AX register and address
SADG word data)
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.8 24-bit Operation Instructions
24-bit operation instructions are as follows:
ADDG ... 326
SUBG ... 327
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Note
Add G
24-Bit Data Addition
ADDG
[Instruction format]
[Operation]
ADDG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
dst ← dst + src
[Operands]
Mnemonic
Operands (dst, src)
rg, rg’
ADDG
rg, #imm24
WHL, saddrg
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by
the 1st operand. The result of the addition is stored in dst, and the S, Z, AC, P/V, and CY flags are changed.
• The S flag is set (1) if bit 23 of dst is set (1) as a result of the addition, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the addition is 0, and cleared (0) otherwise.
• The AC flag is undefined as a result of the addition.
• The P/V flag is set (1) if a carry is generated out of bit 22 into bit 23 and a carry is not generated out of bit 23
as a result of the addition (when overflow is generated by a two’s complement type operation), or if a carry is
not generated out of bit 22 into bit 23 and a carry is generated out of bit 23 (when underflow is generated by
a two’s complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a carry is generated out of bit 23 as a result of the addition, and cleared (0) otherwise.
[Coding example]
ADDG TDE, VVP ; Adds the VVP register to the TDE register, and stores the result in the TDE register
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Note
Subtract G
24-Bit Data Subtraction
SUBG
[Instruction format]
[Operation]
SUBG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
dst ← dst – src
[Operands]
Mnemonic
Operands (dst, src)
rg, rg’
SUBG
rg, #imm24
WHL, saddrg
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified
by the 1st operand. The result of the subtraction is stored in dst, and the S, Z, AC, P/V, and CY flags are changed.
• The S flag is set (1) if bit 23 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and cleared (0) otherwise.
• The AC flag is undefined as a result of the subtraction.
• The P/V flag is set (1) if a borrow is generated out of bit 23 into bit 22 and a borrow is not generated in bit 23
as a result of the subtraction (when underflow is generated by a two’s complement type operation), or if a borrow
is not generated out of bit 23 into bit 22 and a borrow is generated in bit 23 (when overflow is generated by a
two’s complement type operation), and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 23 as a result of the subtraction, and cleared (0) otherwise.
[Coding example]
SUBG UUP, #543210H ; Subtracts 543210H from the contents of the UUP register and stores the result in the
UUP register
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7.9 Multiplication/Division Instructions
Multiplication/division instructions are as follows:
MULU ... 329
MULUW ... 330
MULW ... 331
DIVUW ... 332
DIVUX ... 333
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Multiply Unsigned
MULU
Unsigned Data Multiplication
[Instruction format]
[Operation]
MULU src
AX ← A × src
[Operands]
Mnemonic
Operands (src)
MULU
r
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the A register and the source operand (src) data are multiplied as unsigned data, and the result
is stored in the AX register.
[Coding example]
MULU H ; Multiplies the contents of the A register by the contents of the H register, and stores the result in the
AX register
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Multiply Unsigned Word
Unsigned Word Data Multiplication
MULUW
[Instruction format]
[Operation]
MULUW src
AX (upper half), src (lower half) ← AX × src
[Operands]
Mnemonic
Operands (src)
rp
MULUW
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the AX register and the source operand (src) data are multiplied as unsigned data, and the higher
16 bits of the result are stored in the AX register, and the lower 16 bits in the source operand.
• When the AX register is specified as the source operand (src), the higher 16 bits of the multiplied result are stored
in the AX register, and the lower 16 bits are not stored anywhere.
[Coding example]
MULUW HL ; Multiplies the contents of the AX register by the contents of the HL register, and stores the result
in the AX register and HL register
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Multiply Signed Word
Signed Word Data Multiplication
MULW
[Instruction format]
[Operation]
MULW src
AX (upper half), src (lower half) ← AX × src
[Operands]
Mnemonic
Operands (src)
rp
MULW
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the AX register and the source operand (src) data are multiplied as signed data, and the higher
16 bits of the result are stored in the AX register, and the lower 16 bits in the source operand.
• When the AX register is specified as the source operand (src), the higher 16 bits of the multiplied result are stored
in the AX register, and the lower 16 bits are not stored anywhere.
[Coding example]
MULW HL ; Multiplies the contents of the AX register by the contents of the HL register, and stores the result
in the AX register and HL register
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Divide Unsigned Word
DIVUW
Unsigned Word Data Division
[Instruction format]
[Operation]
DIVUW dst
AX (quotient), dst (remainder) ← AX ÷ dst
[Operands]
Mnemonic
Operands (dst)
r
DIVUW
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the AX register are divided by the contents of the destination operand (dst), and the quotient
is stored in the AX register, and the remainder in the destination operand (dst).
The division is performed with the AX register and destination operand (dst) contents as unsigned data.
• If division by 0 is performed, the following will result:
– AX (quotient) = FFFFH
– dst (remainder) = Original X register value
• When the A register is specified as the destination operand (dst), the remainder is stored in the A register, and
the lower 8 bits of the quotient are stored in the X register.
• When the X register is specified as the destination operand (dst), the higher 8 bits of the quotient are stored
in the A register, and the remainder is stored in the X register.
[Coding example]
DIVUW E ; Divides the contents of the AX register by the contents of the E register, and stores the quotient in
the AX register and the remainder in the E register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Divide Unsigned Word Expansion Word
Unsigned Doubleword Data Division
DIVUX
[Instruction format]
[Operation]
DIVUX dst
AXDE (quotient), dst (remainder) ← AXDE ÷ dst
[Operands]
Mnemonic
Operands (dst)
rp
DIVUX
[Flags]
S
Z
AC
P/V
CY
[Description]
• 32-bit data with the contents of the AX register as the higher 16 bits and the contents of the DE register as the
lower 16 bits is divided by the contents of the destination operand (dst), the higher 16 bits of the quotient are
stored in the AX register, the lower 16 bits in the DE register, and the remainder in the destination operand (dst).
The division is performed with the contents of the 32-bit data indicated by the AX register and DE register and
the contents of the destination operand (dst) as unsigned data.
• If division by 0 is performed, the following will result:
– AXDE (quotient) = FFFFFFFFH
– dst (remainder) = Original DE register value
• When the AX register is specified as the destination operand (dst), the remainder is stored in the AX register,
and the lower 16 bits of the quotient are stored in the DE register.
• When the DE register is specified as the destination operand (dst), the higher 8 bits of the quotient is stored
in the AX register, and the remainder is stored in the DE register.
[Coding example]
DIVUX BC ; Divides the contents of the AXDE register by the contents of the BC register, and stores the higher
16 bits of the quotient in the AX register, the lower 16 bits in the DE register, and the remainder in
the BC register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.10 Special Operation Instructions
Special operation instructions are as follows:
MACW ... 335
MACSW ... 338
SACW ... 341
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Multiply and Accumulate Word
Word Data Sum of Products Operation
MACW
[Instruction format]
[Operation]
MACW dst
AXDE ← (B) × (C) + AXDE, B ← B + 2, C ← C + 2, byte ← byte – 1
End if (byte = 0 or P/V = 1)
[Operands]
Mnemonic
Operands (dst, src)
byte
MACW
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• Signed multiplication is performed of the contents of the 2-byte area addressed by the B register and the contents
of the 2-byte area addressed by the C register, and binary addition is performed of the result and the contents
of the AXDE register.
• After the result of the addition is stored in the AXDE register, the contents of the B register and C register are
incremented by 2.
• The above operations are repeated the number of times equal to the 8-bit immediate data written in the operand.
• If overflow or underflow is generated as a result of the addition, the value of the AXDE register is undefined.
Also, the B register and C register keep their values prior to overflow.
• The area addressed by the MACW instruction is limited to addresses 0FE00H to 0FEFFH when the LOCATION
0H instruction is executed, or addresses 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is
executed. The lower byte of the address is specified by the B register and C register. Addresses FE80H to
FEFFH (FFE80H to FFEFFH when the LOCATION 0FH instruction is executed) are also used as general
registers.
• Interrupts and macro service requests are not acknowledged during execution of the MACW instruction.
• The MACW instruction does not clear the value of the AXDE register pair automatically, and therefore this should
be cleared by the program if necessary.
• The S, Z, AC, and CY flags are undefined as a result of the operation.
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• The P/V flag is set (1) if overflow or underflow occurs, and cleared (0) otherwise.
15
0
×
31
0
byte word
+
AXDE
P/V
×
0FE00HNote
+ (C register)
×
Set (1) in case of
overflow or underflow.
Calculation is suspended
when P/V is set to 1.
byte word
0FE00HNote
+ (B register)
Note When a LOCATION 0H instruction is executed. 0FFE00H when a LOCATION 0FH instruction is
executed.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
MACW
AXDE ← AXDE +
(Data addressed by B register) ×
(Data addressed by C register)
Overflow
Yes
or underflow
generated?
No
B ← B + 2
C ← C + 2
byte ← byte – 1
No
byte = 0?
Yes
END
[Coding example]
MACW 5 ; Executes sum of products operation 5 times
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Multiply and Accumulate with Saturation Word
Sum of Products Operation with Saturation Function
MACSW
[Instruction format]
[Operation]
MACSW byte
AXDE ← (B) × (C) + AXDE, B ← B + 2, C ← C + 2, byte ← byte – 1 if byte = 0 then End,
if P/V = 1, then if overflow AXDE ← 7FFFFFFFH, end, if underflow AXDE ← 80000000H,
end
[Operands]
Mnemonic
Operands ($addr16)
byte
MACSW
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• Signed multiplication is performed of the contents of the 2-byte area addressed by the B register and the contents
of the 2-byte area addressed by the C register, and binary addition is performed of the result and the contents
of the AXDE register.
• After the result of the addition is stored in the AXDE register, the contents of the B register and C register are
incremented by 2.
• The above operations are repeated the number of times equal to the 8-bit immediate data written in the operand.
• If overflow is generated as a result of the addition, the P/V flag is set (1) and the value of the AXDE register
is 7FFFFFFFH. If underflow is generated, the P/V flag is set (1) and the AXDE register value is 80000000H.
The B register and C register keep their values prior to overflow or underflow.
• The area addressed by the MACSW instruction is limited to addresses 0FE00H to 0FEFFH when the LOCATION
0H instruction is executed, or addresses 0FFE00H to 0FFEFFH when the LOCATION 0FH instruction is
executed. The lower byte of the address is specified by the B register and C register. Addresses FE80H to
FEFFH (FFE80H to FFEFFH when the LOCATION 0FH instruction is executed) are also used as general
registers.
• Interrupts and macro service requests are not acknowledged during execution of the MACSW instruction.
• The MACSW instruction does not clear the value of the AXDE register pair automatically, and therefore this
should be cleared by the program if necessary.
• The S, Z, AC, and CY flags are undefined as a result of the operation.
• The P/V flag is set (1) if overflow or underflow occurs, and cleared (0) otherwise.
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15
0
×
31
0
byte word
+
AXDE
P/V
×
0FE00HNote
+ (C register)
×
Set (1) in case of
overflow or underflow.
When P/V is set to 1.
calculation is suspended,
byte word
and 7FFFFFFFH (in case of overflow)
or 80000000H (in case of underflow) is
loaded into AXDE.
0FE00HNote
+ (B register)
Note When a LOCATION 0H instruction is executed. 0FFE00H when a LOCATION 0FH instruction is
executed.
The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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MACSW
AXDE ← AXDE +
(Data addressed by B register) ×
(Data addressed by C register)
Overflow
Yes
or underflow
generated?
No
B ← B + 2
C ← C + 2
byte ← byte – 1
No
byte = 0?
No
Overflow?
Yes
Yes
AXDE ← 7FFFFFFFH
AXDE ← 80000000H
END
[Coding example]
MACSW 6 ; Executes sum of products operation 6 times
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Subtract, Absolute and Accumulate Word
Correlation Instruction
SACW
[Instruction format]
[Operation]
SACW [TDE +], [WHL +]
AX ← | (TDE) – (WHL) | + AX, TDE ← TDE + 2, WHL ← WHL + 2, C ← C – 1, end if
(C = 0 or CY = 1)
[Operands]
Mnemonic
Operands ($addr16)
[TDE +], [WHL +]
SACW
[Flags]
S
Z
AC
P/V
CY
×
×
×
×
×
[Description]
• Subtraction is performed on the 16-bit data items addressed by the TDE register and WHL register, the absolute
value of the result is added to the contents of the AX register, and the result is stored in the AX register.
• Each time the above operation is performed, the contents of the TDE and WHL registers are incremented by
2, and the contents of the C register are decremented by 1.
• The above operations are repeated until the C register value is 0 or a carry is generated out of bit 15 as a result
of the addition.
• If a carry occurs from bit 15 as a result of addition, therefore stopping repetition, the TDE and WHL registers
retain the values immediately before the carry has occurred plus 2. The C register retains the value immediately
before the carry has occurred.
• If an interrupt or macro service request that can be acknowledged during execution of the SACW instruction
is generated, the interrupt or macro service processing is performed before the series of operation processing.
When an interrupt is acknowledged, the program counter (PC) value saved to the stack is the SACW instruction
start address.
Therefore, after returning from the interrupt, continuation of the interrupted SACW instruction is executed.
• The CY flag is set (1) if a carry is generated out of bit 15 as a result of the final addition, and cleared (0) otherwise.
• The contents of the S, Z, AC, and P/V flags are undefined.
• The SACW instruction does not clear the contents of the AX register pair automatically, and therefore this should
be done by the program if necessary.
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Conversion to
absolute value
15
0
–
Conversion to
absolute value
15
0
(C register word)
WHL
+
AX
CY
–
–
Conversion to
absolute value
Calculation is suspended
when CY is set to 1.
(C register word)
TDE
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SACW
AX ← AX + (TDE) – (WHL)
TDE ← TDE + 2
WHL ← WHL + 2
Yes
CY = 1
No
C ← C – 1
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
[Coding example]
SACW [TDE+], [WHL+] ; Executes a correlation instruction
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.11 Increment/Decrement Instructions
Increment/decrement instructions are as follows:
INC ... 345
DEC ... 346
INCW ... 347
DECW ... 348
INCG ... 349
DECG ... 350
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Increment
INC
Byte Data Increment
[Instruction format]
[Operation]
INC dst
dst ← dst + 1
[Operands]
Mnemonic
Operands (dst)
INC
r
saddr
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
[Description]
• The contents of the destination operand (dst) are incremented by 1.
• The Z flag is set (1) if the result of the increment is 0, and cleared (0) otherwise.
• The AC flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the increment, and cleared (0)
otherwise.
• The CY flag value does not change since this is often used for repeat processing counter or indexed address
offset register incrementing (as the CY flag value is retained in a multiple-byte operation).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the increment, and cleared (0) otherwise.
• The P/V flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as
a result of the increment (when overflow is generated by a two’s complement type operation), and is cleared
(0) otherwise.
[Coding example]
INC B ; Increments the B register
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Decrement
DEC
Byte Data Decrement
[Instruction format]
[Operation]
DEC dst
dst ← dst – 1
[Operands]
Mnemonic
Operands (dst)
DEC
r
saddr
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
[Description]
• The contents of the destination operand (dst) are decremented by 1.
• The Z flag is set (1) if the result of the decrement is 0, and cleared (0) otherwise.
• The AC flag is set (1) if a carry is generated out of bit 4 into bit 3 as a result of the decrement, and cleared (0)
otherwise.
• The CY flag value does not change since this is often used for repeat processing counter or indexed address
offset register decrementing (as the CY flag value is retained in a multiple-byte operation).
• The S flag is set (1) if bit 7 of dst is set (1) as a result of the decrement, and cleared (0) otherwise.
• The P/V flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as
a result of the decrement (when underflow is generated by a two’s complement type operation), and is cleared
(0) otherwise.
• If dst is the B register, C register or saddr, and you do not want to change the S, Z, AC, or P/V flag, the DBNZ
instruction can be used.
[Coding example]
DEC SAD1 ; Decrements the contents of address SAD1 that can be accessed by short direct addressing
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Increment Word
INCW
Word Data Increment
[Instruction format]
[Operation]
INCW dst
dst ← dst + 1
[Operands]
Mnemonic
Operands (dst)
INCW
rp
saddrp
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the destination operand (dst) are incremented by 1.
• The S, Z, AC, P/V, and CY flags are not changed since this is often used for incrementing the register used in
addressing that uses a register.
• If the HL, DE, VP, or UP register (VP and UP: 78K/III Series only) is used as the base register in register indirect
addressing, base addressing or based index addressing (78K/0 and 78K/III Series only) when rp is specified
as the operand and a 78K/0, 78K/I, 78K/II, or 78K/III Series program is used, ensure that the contents of the
T, W, V, or U register that indicates the higher 8 bits of the address are coordinated with the DE, HL, VP, or
UP register that indicates the lower 16 bits. Also, if program amendment is possible, the program should be
changed so that a 24-bit manipulation instruction (INCG instruction) is used.
[Coding example]
INCW HL ; Increments the HL register
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Decrement Word
DECW
Word Data Decrement
[Instruction format]
[Operation]
DECW dst
dst ← dst – 1
[Operands]
Mnemonic
Operands (dst)
DECW
rp
saddrp
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the destination operand (dst) are decremented by 1.
• The S, Z, AC, P/V, and CY flags are not changed since this is often used for decrementing the register used
in addressing that uses a register.
• If the HL, DE, VP, or UP register (VP and UP: 78K/III Series only) is used as the base register in register indirect
addressing, base addressing or based index addressing (78K/0 and 78K/III Series only) when rp is specified
as the operand and a 78K/0, 78K/I, 78K/II, or 78K/III Series program is used, ensure that the contents of the
T, W, V, or U register that indicates the higher 8 bits of the address are coordinated with the DE, HL, VP, or
UP register that indicates the lower 16 bits. Also, if program amendment is possible, the program should be
changed so that a 24-bit manipulation instruction (INCG instruction) is used.
[Coding example]
DECW DE ; Decrements the DE register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Note
Increment G
24-Bit Data Increment
INCG
[Instruction format]
[Operation]
INCG dst
Note G is a character that indicates that 24-bit
data is to be manipulated.
dst ← dst + 1
[Operands]
Mnemonic
Operands (dst)
INCG
rg
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the destination operand (dst) are incremented by 1.
• The S, Z, AC, P/V, and CY flags are not changed since this is often used to decrement the register (pointer)
used in addressing that uses a register.
[Coding example]
INCG UUP ; Increments the UUP register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Note
Decrement G
24-Bit Data Decrement
DECG
[Instruction format]
[Operation]
DECG dst
Note G is a character that indicates that 24-bit
data is to be manipulated.
dst ← dst – 1
[Operands]
Mnemonic
Operands (dst)
DECG
rg
SP
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the destination operand (dst) are decremented by 1.
• The S, Z, AC, P/V, and CY flags are not changed since this is often used to decrement the register (pointer)
used in addressing that uses a register.
[Coding example]
DECG VVP ; Decrements the VVP register
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7.12 Adjustment Instructions
Adjustment instructions are as follows.
ADJBA ... 352
ADJBS ... 353
CVTBW ... 354
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Decimal Adjust Register for Addition
Decimal Adjustment of Addition Result
ADJBA
[Instruction format]
[Operation]
ADJBA
Decimal Adjust Accumulator for Addition
[Operands]
None
[Flags]
S
Z
AC
P/V
P
CY
×
×
×
×
[Description]
• Decimal adjustment of the A register, CY flag and AC flag is performed from the A register, CY flag and AC flag
contents. This instruction only performs a meaningful operation when the addition result is stored in the A register
after BCD (binary-code decimal) data has been added (in other cases, a meaningless operation is performed).
The adjustment method is shown in the table below.
Condition
Operation
A3–0 ≤ 9
AC = 0
A7–4 ≤ 9 and CY = 0
A7–4 ≥ 10 or CY = 1
A7–4 < 9 and CY = 0
A7–4 ≥ 9 or CY = 1
A7–4 ≤ 9 and CY = 0
A7–4 ≥ 10 or CY = 1
A ← A, CY ← 0, AC ← 0
A ← A + 01100000B, CY ← 1, AC ← 0
A ← A + 00000110B, CY ← 0, AC ← 1
A ← A + 01100110B, CY ← 1, AC ← 1
A ← A + 00000110B, CY ← 0, AC ← 1
A ← A + 01100110B, CY ← 1, AC ← 1
A3–0 ≥ 10
AC = 0
AC = 1
• The Z flag is set (1) if the contents of the A register are 0 as a result of the adjustment, and cleared (0) otherwise.
• The S flag is set (1) if bit 7 of the A register is 1 as a result of the adjustment, and cleared (0) otherwise.
• The P/V flag is set (1) if the number of bits set (1) in the A register as a result of the adjustment is even, and
cleared (0) otherwise.
[Coding example]
ADJBA ; Performs decimal adjustment of the contents of the A register
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Decimal Adjust Register for Subtraction
Decimal Adjustment of Subtraction Result
ADJBS
[Instruction format]
[Operation]
ADJBS
Decimal Adjust Accumulator for Subtraction
[Operands]
None
[Flags]
S
Z
AC
P/V
P
CY
×
×
×
×
[Description]
• Decimal adjustment of the A register, CY flag and AC flag is performed from the A register, CY flag and AC flag
contents. This instruction only performs a meaningful operation when the subtraction result is stored in the A
register after BCD (binary-code decimal) data has been subtracted (in other cases, a meaningless operation
is performed). The adjustment method is shown in the table below.
Condition
CY = 0
CY = 1
CY = 0
CY = 1
Operation
AC = 0
AC = 1
A ← A, CY ← 0, AC ← 0
A ← A – 01100000B, CY ← 1, AC ← 0
A ← A – 00000110B, CY ← 0, AC ← 1
A ← A – 01100110B, CY ← 1, AC ← 1
• The Z flag is set (1) if the contents of the A register are 0 as a result of the adjustment, and cleared (0) otherwise.
• The S flag is set (1) if bit 7 of the A register is 1 as a result of the adjustment, and cleared (0) otherwise.
• The P/V flag is set (1) if the number of bits set (1) in the A register as a result of the adjustment is even, and
cleared (0) otherwise.
[Coding example]
ADJBS ; Performs decimal adjustment of the contents of the A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Convert Byte to Word
Conversion from Byte Data to Word Data
CVTBW
[Instruction format]
[Operation]
CVTBW
When A7 = 0, X ← A, A ← 00H
When A7 = 1, X ← A, A ← FFH
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
•
•
The signed 8-bit data in the A register is extended to signed 16-bit data in the AX register.
The S, Z, AC, P/V, and CY flags are not changed by this instruction.
[Coding example]
CVTBW ; Extends the signed 8-bit data in the A register to signed 16-bit data and stores it in the AX register
354
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.13 Shift/Rotate Instructions
Shift/rotate instructions are as follows:
ROR ... 356
ROL ... 357
RORC ... 358
ROLC ... 359
SHR ... 360
SHL ... 361
SHRW ... 362
SHLW ... 363
ROR4 ... 364
ROL4 ... 365
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Right
ROR
Right Rotation of Byte Data
[Instruction format]
[Operation]
ROR dst, cnt
(CY, dst7 ← dst0, dstm–1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
ROR
[Flags]
S
Z
AC
P/V
P
CY
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are rotated to the right cnt times
specified by the 2nd operand.
• The contents of the LSB (bit 0) are rotated into the MSB (bit 7) and are also transferred to the CY flag.
• If the 2nd operand (cnt) is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the right rotation is even, and cleared
(0) otherwise.
• The S, Z, and AC flags do not change irrespective of the result of the rotate operation.
CY
7
0
[Coding example]
ROR R5, 4 ; Rotates the contents of the R5 register 4 bits to the right
356
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Left
ROL
Left Rotation of Byte Data
[Instruction format]
[Operation]
ROL dst, cnt
(CY, dst0 ← dst7, dstm+1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
ROL
[Flags]
S
Z
AC
P/V
P
CY
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are rotated to the left cnt times
specified by the 2nd operand.
• The contents of the MSB (bit 7) are rotated into the LSB (bit 0) and are also transferred to the CY flag.
• If the 2nd operand (cnt) is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the left rotation is even, and cleared (0)
otherwise.
• The S, Z, and AC flags do not change irrespective of the result of the rotate operation.
CY
7
0
[Coding example]
ROL L, 2 ; Rotates the contents of the L register 2 bits to the left
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Right with Carry
Right Rotation of Byte Data including Carry
RORC
[Instruction format]
[Operation]
RORC dst, cnt
(CY ← dst0, dst7 ← CY, dstm–1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
RORC
[Flags]
S
Z
AC
P/V
P
CY
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand, and the CY flag, are rotated to the
right cnt times specified by the 2nd operand.
• If the 2nd operand (cnt) is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the right rotation is even, and cleared
(0) otherwise.
• The S, Z, and AC flags do not change irrespective of the result of the rotate operation.
CY
7
0
[Coding example]
RORC B, 1 ; Rotates the contents of the B register and the CY flag 1 bit to the right
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Left with Carry
Left Rotation of Byte Data including Carry
ROLC
[Instruction format]
[Operation]
ROLC dst, cnt
(CY ← dst7, dst0 ← CY, dstm+1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
ROLC
[Flags]
S
Z
AC
P/V
P
CY
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand, and the CY flag, are rotated to the
left cnt times specified by the 2nd operand.
• If the 2nd operand (cnt) is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• If you wish to perform a left rotation of 1 bit only, the execution time can be reduced by using ADDC r, r.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the left rotation is even, and cleared (0)
otherwise.
• The S, Z, and AC flags do not change irrespective of the result of the rotate operation.
CY
7
0
[Coding example]
ROLC R7, 3 ; Rotates the contents of the R7 register and the CY flag 3 bits to the left
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Shift Right (Logical)
Logical Right Shift of Byte Data
SHR
[Instruction format]
[Operation]
SHR dst, cnt
(CY ← dst0, dst7 ← 0, dstm–1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
SHR
[Flags]
S
Z
AC
0
P/V
P
CY
×
×
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times
specified by the 2nd operand.
0 is shifted into the MSB (bit 7) each time a 1-bit shift is performed.
• The S flag is cleared (0) if cnt is 1 or more.
• The Z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise.
• The AC flag is always 0 irrespective of the result of the shift operation.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the shift operation is even, and cleared
(0) otherwise.
• The last data shifted out of the LSB (bit 0) as a result of the shift operation is set in the CY flag.
• If cnt is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• This instruction gives the same result as division of the destination operand (dst) as unsigned data by 2cnt
.
CY
7
0
0
[Coding example]
SHR H, 2 ; Shifts the contents of the H register 2 bits to the right
360
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Shift Left (Logical)
SHL
Logical Left Shift of Byte Data
[Instruction format]
[Operation]
SHL dst, cnt
(CY ← dst7, dst0 ← 0, dstm+1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
r, n
SHL
[Flags]
S
Z
AC
0
P/V
P
CY
×
×
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are shifted to the left cnt times specified
by the 2nd operand.
• 0 is shifted into the LSB (bit 0) each time a 1-bit shift is performed.
• The S flag is set (1) if bit 7 of dst is 1 as a result of the shift operation, and cleared (0) if 0.
• The Z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise.
• The AC flag is always 0 irrespective of the result of the shift operation.
• The P/V flag is set (1) if the number of bits set (1) in dst as a result of the shift operation is even, and cleared
(0) otherwise.
• The last data shifted out of the LSB (bit 0) as a result of the shift operation is set in the CY flag.
• If cnt is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• If you wish to perform a left shift of 1 bit only, the execution time can be reduced by using ADD r, r.
• This instruction gives the same result as multiplication of the destination operand (dst) by 2cnt (if the multiplication
result is 8 bits or less).
CY
7
0
0
[Coding example]
SHL E, 1 ; Shifts the contents of the E register 1 bit to the left
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Shift Right (Logical) Word
Logical Right Shift of Word Data
SHRW
[Instruction format]
[Operation]
SHRW dst, cnt
(CY ← dst0, dst15 ← 0, dstm–1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
rp, n
SHRW
[Flags]
S
Z
AC
0
P/V
P
CY
×
×
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times
specified by the 2nd operand.
0 is shifted into the MSB (bit 15) each time a 1-bit shift is performed.
• The S flag is cleared (0) if cnt is 1 or more.
• The Z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise.
• The AC flag is always 0 irrespective of the result of the shift operation.
• The P/V flag is set (1) if the number of bits set (1) in the lower 8 bits of dst as a result of the shift operation is
even, and cleared (0) otherwise.
• The last data shifted out of the LSB (bit 0) as a result of the shift operation is set in the CY flag.
• If cnt is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
• This instruction gives the same result as division of the destination operand (dst) as unsigned data by 2cnt
.
CY
15
0
0
[Coding example]
SHRW AX, 3 ; Shifts the contents of the AX register 3 bits to the right (divides the contents of the AX register by
8)
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Shift Left (Logical) Word
SHLW
Logical Left Shift of Word Data
[Instruction format]
[Operation]
SHLW dst, cnt
(CY ← dst15, dst0 ← 0, dstm+1 ← dstm) × cnt times cnt = 0 to 7
[Operands]
Mnemonic
Operands (dst, cnt)
rp, n
SHLW
[Flags]
S
Z
AC
0
P/V
P
CY
×
×
×
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times
specified by the 2nd operand.
• 0 is shifted into the LSB (bit 0) each time a 1-bit shift is performed.
• The S flag is set (1) if bit 15 of dst is 1 as a result of the shift operation, and cleared (0) if 0.
• The Z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise.
• The AC flag is always 0 irrespective of the result of the shift operation.
• The P/V flag is set (1) if the number of bits set (1) in the lower 8 bits of dst as a result of the shift operation is
even, and cleared (0) otherwise.
• The last data shifted out of the LSB (bit 0) as a result of the shift operation is set in the CY flag.
• If cnt is 0, no processing is performed (and the S, Z, AC, P/V, and CY flags do not change).
CY
15
0
0
[Coding example]
SHLW E, 1 ; Shifts the contents of the E register 1 bit to the left
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Right Digit
ROR4
Right Digit Rotation
[Instruction format]
[Operation]
ROR4 dst
A3–0 ← (dst)3–0, (dst)7–4 ← A3–0, (dst)3–0 ← dst7–4
[Operands]
Mnemonic
Operands (dst)
mem3
ROR4
[Flags]
S
Z
AC
P/V
CY
[Description]
• The lower 4 bits of the A register and the two items of digit data (4-bit data) of the destination operand (dst) are
rotated to the right.
The higher 4 bits of the A register are not changed.
7
4 3
0
7
4 3
0
A
dst
[Coding example]
ROR4 [WHL] ; Performs digit rotation to the right of the A register and memory contents specified by the WHL
register.
A
(WHL)
4 3
7
4 3
0
7
0
Before Execution
After Execution
1 0 1 0 0 0 1 1
1 1 0 0 0 1 0 1
1 0 1 0 0 1 0 1
0 0 1 1 1 1 0 0
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Rotate Left Digit
ROL4
Left Digit Rotation
[Instruction format]
[Operation]
ROL4 dst
A3–0 ← (dst)7–4, (dst)3–0 ← A3–0, (dst)7–4 ← dst3–0
[Operands]
Mnemonic
Operands (dst)
mem3
ROL4
[Flags]
S
Z
AC
P/V
CY
[Description]
• The lower 4 bits of the A register and the two items of digit data (4-bit data) of the destination operand (dst) are
rotated to the left.
The higher 4 bits of the A register are not changed.
7
4 3
0
7
4 3
0
A
dst
[Coding example]
ROL4 [TDE] ; Performs digit rotation to the left of the A register and memory contents specified by the TDE register.
A
(TDE)
4 3
7
4 3
0
7
0
Before Execution
After Execution
0 0 0 1 0 0 1 0
0 1 0 0 1 0 0 0
0 0 0 1 0 1 0 0
1 0 0 0 0 0 1 0
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.14 Bit Manipulation Instructions
Bit manipulation instructions are as follows:
MOV1 ... 367
AND1 ... 369
OR1 ... 371
XOR1 ... 373
NOT1 ... 374
SET1 ... 375
CLR1 ... 376
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move Single Bit
MOV1
1-Bit Data Transfer
[Instruction format]
[Operation]
MOV1 dst, src
dst ← src
[Operands]
Mnemonic
Operands (dst, src)
MOV1
CY, saddr.bit
CY, sfr.bit
CY, X.bit
CY, A.bit
CY, PSWL.bit
CY, PSWH.bit
CY, mem2.bit
CY, !addr16.bit
CY, !!addr24.bit
saddr.bit, CY
sfr.bit, CY
X.bit, CY
A.bit, CY
PSWL.bit, CY
PSWH.bit, CY
mem2.bit, CY
!addr16.bit, CY
!!addr24.bit, CY
[Flags]
dst is PSWL.bit
dst is CY
S
S
Z
AC
P/V
CY
Z
AC
P/V
CY
×
×
×
×
×
×
Other cases
S
Z
AC
P/V
CY
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Description]
• The source operand (src) bit data specified by the 2nd operand is transferred to the destination operand (dst)
specified by the 1st operand.
• If the destination operand (dst) is CY or PSW.bit, only the relevant flag changes.
[Coding example]
MOV1 P3.4, CY ; Transfers the contents of the CY flag to bit 4 of port 3
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
And Single Bit
AND1
1-Bit Data Logical Product
[Instruction format]
[Operation]
AND1 dst, src
AND1 dst, /src
dst ← dst src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
CY, saddr.bit
CY, /saddr.bit
CY, sfr.bit
AND1
CY, /sfr.bit
CY, X.bit
CY, /X.bit
CY, A.bit
CY, /A.bit
CY, PSWL.bit
CY, /PSWL.bit
CY, PSWH.bit
CY, /PSWH.bit
CY, mem2.bit
CY, /mem2.bit
CY, !addr16.bit
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
[Flags]
S
Z
AC
P/V
CY
×
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Description]
• The logical product of the destination operand (dst) specified by the 1st operand and the source operand (src)
bit data specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• If the 2nd operand is immediately preceded by “/”, the logical product operation is performed on the logical NOT
of the source operand (src).
• The CY flag stores the operation result (as it is the destination operand (dst)).
[Coding examples]
AND1 CY, SADR.3 ; Finds the logical product of bit 3 of address SADR which can be accessed by short direct
addressing and the CY flag, and stores the result in the CY flag
AND1 CY, /PSW.6 ; Finds the logical product of the logical NOT of bit 6 of the PSW (Z flag) and the CY flag, and
stores the result in the CY flag
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Or Single Bit
OR1
1-Bit Data Logical Sum
[Instruction format]
[Operation]
OR1 dst, src
OR1 dst, /src
dst ← dst src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
CY, saddr.bit
CY, /saddr.bit
CY, sfr.bit
OR1
CY, /sfr.bit
CY, X.bit
CY, /X.bit
CY, A.bit
CY, /A.bit
CY, PSWL.bit
CY, /PSWL.bit
CY, PSWH.bit
CY, /PSWH.bit
CY, mem2.bit
CY, /mem2.bit
CY, !addr16.bit
CY, /!addr16.bit
CY, !!addr24.bit
CY, /!!addr24.bit
[Flags]
S
Z
AC
P/V
CY
×
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Description]
• The logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) bit
data specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• If the 2nd operand is immediately preceded by “/”, the logical sum operation is performed on the logical NOT
of the source operand (src).
• The CY flag stores the operation result (as it is the destination operand (dst)).
[Coding examples]
OR1 CY, P2.5; Finds the logical sum of bit 5 of port 2 and the CY flag, and stores the result in the CY flag
OR1 CY, /X.0 ; Finds the logical sum of the logical NOT of bit 0 of the X register and the CY flag, and stores the
result in the CY flag
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Exclusive Or Single Bit
1-Bit Data Exclusive Logical Sum
XOR1
[Instruction format]
[Operation]
XOR1 dst, src
dst ← dst src
[Operands]
Mnemonic
Operands (dst, src)
CY, saddr.bit
CY, sfr.bit
XOR1
CY, X.bit
CY, A.bit
CY, PSWL.bit
CY, PSWH.bit
CY, mem2.bit
CY, !addr16.bit
CY, !!addr24.bit
[Flags]
S
Z
AC
P/V
CY
×
[Description]
• The exclusive logical sum of the destination operand (dst) specified by the 1st operand and the source operand
(src) bit data specified by the 2nd operand is found, and the result is stored in the destination operand (dst).
• The CY flag stores the operation result (as it is the destination operand (dst)).
[Coding example]
XOR1 CY, A.7 ; Finds the exclusive logical sum of bit 7 of the A register and the CY flag, and stores the result
in the CY flag
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Not Single Bit (Carry Flag)
1-Bit Data Logical NOT
NOT1
[Instruction format]
[Operation]
NOT1 dst
dst ← dst
[Operands]
Mnemonic
Operands (dst)
NOT1
saddr.bit
sfr.bit
X.bit
A.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
CY
[Flags]
dst is PSWL.bit
dst is CY
S
S
Z
AC
P/V
CY
Z
AC
P/V
CY
×
×
×
×
×
×
Other cases
S
Z
AC
P/V
CY
[Description]
• The logical NOT of the bit specified by the destination operand (dst) is found, and the result is stored in the
destination operand (dst).
• If the destination operand (dst) is CY or PSW.bit, only the relevant flag changes.
[Coding examples]
NOT1 A.2 ; Inverts bit 2 of the A register
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Set Single Bit (Carry Flag)
1-Bit Data Setting
SET1
[Instruction format]
[Operation]
SET1 dst
dst ← 1
[Operands]
Mnemonic
Operands (dst)
SET1
saddr.bit
sfr.bit
X.bit
A.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
CY
[Flags]
dst is PSWL.bit
dst is CY
S
S
Z
AC
P/V
CY
Z
AC
P/V
CY
1
×
×
×
×
×
Other cases
S
Z
AC
P/V
CY
[Description]
•
•
The destination operand (dst) is set (1).
If the destination operand (dst) is CY or PSW.bit, only the relevant flag is set (1).
[Coding example]
SET1 BITSYM ; Sets (1) the contents of a bit located in an area that can be accessed by short direct addressing
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Clear Single Bit (Carry Flag)
1-Bit Data Clear
CLR1
[Instruction format]
[Operation]
CLR1 dst
dst ← 0
[Operands]
Mnemonic
Operands (dst)
CLR1
saddr.bit
sfr.bit
X.bit
A.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
CY
[Flags]
dst is PSWL.bit
dst is CY
S
S
Z
AC
P/V
CY
Z
AC
P/V
CY
0
×
×
×
×
×
Other cases
S
Z
AC
P/V
CY
[Description]
• The destination operand (dst) is cleared (0).
• If the destination operand (dst) is CY or PSW.bit, only the relevant flag is cleared (0).
[Coding example]
CLR1 P3.7 ; Clears (0) bit 7 of port 3
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.15 Stack Manipulation Instructions
Stack manipulation instructions are as follows:
PUSH ... 378
PUSHU ... 380
POP ... 381
POPU ... 383
MOVG ... 384
ADDWG ... 385
SUBWG ... 386
INCG SP ... 387
DECG SP ... 388
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Push
Push
PUSH
[Instruction format]
PUSH src
Note
[Operation]
(1) When src is PSW, sfrp
(SP – 2) ← src,
SP ← SP – 2
(2) When src is sfr
(SP – 1) ← src,
SP ← SP – 1
(3) When src is rg
(SP – 3) ← src,
SP ← SP – 3
(4) When src is post
{(SP – 2) ← post, SP ← SP – 2} × n times
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands (src)
PUSH
PSW
sfrp
sfr
post
rg
[Flags]
S
Z
AC
P/V
CY
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Description]
• The data in the registers specified by the source operand (src) is saved to the stack.
• If post is specified as the source operand, any combination of the following registers can be saved to the stack
by the instruction.
AX (RP0), BC (RP1), RP2, RP3, UP, VP, DE, HL
The save order at this time is from the rightmost of the above registers.
• The VP, UP, DE, and HL registers should only be used when a 78K/0, 78K/I, 78K/II, or 78K/III Series program
is used. In other cases, saving to the stack should be specified individually as the UUP, VVP, TDE, and WHL
registers.
Moreover, saving to the stack should also be specified individually as the UUP, VVP, TDE, and WHL registers
when a 78K/0, 78K/I, 78K/II, or 78K/III Series program is used.
• After the source operand (src) save, the stack pointer (SP) is decremented by the number of bytes of data saved.
[Coding example]
PUSH AX, BC, RP2, RP3 ; Saves the contents of the AX, BC, RP2, and RP3 registers to the stack
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Push to User Stack
PUSHU
Register Push to User Stack
[Instruction format]
PUSHU src
Note
[Operation]
{(UUP – 1) ← post, UUP ← UUP – 2} × n times
(n = number of register pairs written as post)
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands (src)
PUSHU
post
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the 16-bit register pair specified by the source operand (src) are saved to the memory addressed
by the user stack pointer (UUP), and then the UUP is decremented.
• Any combination of the following registers can be written in post as the source operand (src).
AX (RP0), BC (RP1), RP2, RP3, VP, PSW, DE, HL
The save order at this time is from the rightmost of the above registers.
[Coding example]
PUSHU BC, PSW ; Saves the contents of the BC register and PSW to the stack
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Pop
Pop
POP
[Instruction format]
POP dst
Note
[Operation]
(1) When dst is PSW, sfrp
dst ← (SP)
SP ← SP + 2
(2) When dst is sfr
dst ← (SP),
SP ← SP + 1
(3) When dst is rg
dst ← (SP),
SP ← SP + 3
(4) When dst is post
{post ← (SP), SP ← SP+2} × n times
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
POP
Operands (dst)
PSW
sfrp
sfr
post
rg
[Flags]
dst is PSW
In other cases
S
R
Z
AC
R
P/V
R
CY
R
S
Z
AC
P/V
CY
R
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[Description]
• Data is restored from the stack to the registers specified by the destination operand (dst).
• If the destination operand (dst) is the PSW, each flag is replaced with stack data.
• If post is specified as the destination operand (dst), data can be restored to any combination of the following
registers by one instruction.
AX (RP0), BC (RP1), RP2, RP3, VP (RP4), UP (RP5), DE (RP6), HL (RP7)
The restoration order at this time is from the leftmost of the above registers.
• The UP, VP, DE, and HL registers should only be used when a 78K/0, 78K/I, 78K/II, or 78K/III Series program
is used. In other cases, restoration from the stack should be specified individually as the UUP, VVP, TDE, and
WHL registers.
Moreover, saving to the stack should also be specified individually as the UUP, VVP, TDE, and WHL registers
when a 78K/0, 78K/I, 78K/II, or 78K/III Series program is used.
• After data has been restored from the stack, the stack pointer (SP) is incremented by the number of bytes of
data restored.
[Coding example]
POP IMK0L ; Restores stack data to the IMK0L register
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Pop from User Stack
POPU
Register Pop from User Stack
[Instruction format]
POPU dst
Note
[Operation]
{post ← (UUP), UUP ← UUP + 2} × n times
(n = number of register pairs written as post)
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands (dst)
POPU
post
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the memory (stack) addressed by the user stack pointer (UUP) are restored to the registers
specified by the destination operand (dst), and then the UUP is incremented.
• Any combination of the following registers can be written in post as the destination operand (dst).
AX (RP0), BC (RP1), RP2, RP3, VP (RP4), PSW, DE (RP6), HL (RP7)
The restoration order at this time is from the leftmost of the above registers.
[Coding example]
POPU AX, BC ; Restores stack data to the AX and BC registers
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Note
Move G
24-Bit Data Transfer
MOVG
[Instruction format]
[Operation]
MOVG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
When dst is SP
When dst is WHL
SP ← src
WHL ← SP
[Operands]
Mnemonic
Operands (dst, src)
SP, #imm24
SP, WHL
MOVG
WHL, SP
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand
(dst) specified by the 1st operand.
• After reset release, SP initialization must always be performed with an MOVG SP, #imm24 instruction after
executing the LOCATION instruction.
[Coding example]
MOVG SP, #0FFD20H ; Sets 0FFD20H in the SP
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Note
Add Word to G
24-Bit Word Data Addition
ADDWG
[Instruction format]
[Operation]
ADDWG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
SP ← SP + word
[Operands]
Mnemonic
Operands (dst, src)
SP, #word
ADDWG
[Flags]
S
Z
AC
P/V
CY
[Description]
• Unsigned 16-bit immediate data is added to the contents of the stack pointer (SP), and the result is stored in
the stack pointer (SP).
• This instruction is used to release a memory area reserved as a temporary variable storage location in a high-
level language, etc.
[Coding example]
ADDWG SP, #30H ; Adds 30H to the SP and stores the result in the SP
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Note
Subtract Word from G
24-Bit Word Data Subtraction
SUBWG
[Instruction format]
[Operation]
SUBWG dst, src
Note G is a character that indicates that 24-bit
data is to be manipulated.
SUBWG SP ← SP – 1
[Operands]
Mnemonic
Operands (dst, src)
SP, #word
SUBWG
[Flags]
S
Z
AC
P/V
CY
[Description]
• Unsigned 16-bit immediate data is subtracted from the contents of the stack pointer (SP), and the result is stored
in the SP.
• This instruction is used to reserve a temporary variable area in a high-level language, etc.
[Coding example]
SUBWG SP, #50H ;Subtracts 50H from the SP and stores the result in the SP. This reserves a 50H-byte temporary
variable area.
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Note
Increment G
INCG SP
Stack Pointer 24-Bit Data Increment
[Instruction format]
[Operation]
INCG SP
Note G is a character that indicates that 24-bit
data is to be manipulated.
SP ← SP + 1
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• Increments the SP (stack pointer) contents by 1.
[Coding example]
INCG SP
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Note
Decrement G
DECG SP
Stack Pointer 24-Bit Data Decrement
[Instruction format]
[Operation]
DECG SP
Note G is a character that indicates that 24-bit
data is to be manipulated.
SP ← SP – 1
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• Decrements the SP (stack pointer) contents by 1.
[Coding example]
DECG SP
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7.16 Call/Return Instructions
Call/return instructions are as follows:
CALL ... 390
CALLF ... 391
CALLT ... 392
BRK ... 393
BRKCS ... 394
RET ... 396
RETI ... 397
RETB ... 398
RETCS ... 399
RETCSB ... 401
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Call
CALL
Subroutine Call
[Instruction format]
CALL target
Note
[Operation]
(SP – 3) ← (PC + n),
SP ← SP – 3
PC ← target
n: Number of instruction bytes
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands (target)
!addr16
CALL
!!addr20
rp
rg
[rp]
[rg]
$!addr20
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is a subroutine call using a 16-bit or 20-bit absolute address, 16-bit relative address, register direct address,
or register indirect address.
• The start address of the next instruction (PC + n) is saved to the stack, and the program branches to the address
specified by the target operand (target).
• If !addr16, rp or [rp] is specified as the operand, the branch destination address is limited to the base area (0
to FFFFH) (in the case of [rp], the branch destination table is also limited to the base area). This should only
be used when it is absolutely essential to reduce the execution time or object size, and when 78K/0, 78K/I, 78K/
II, or 78K/III Series software is used and program amendment is difficult.
Amendments may be necessary in order to make further use of a program that uses these instructions.
• With the NEC assembler (RA78K4), if CALL addr is written, the object code that can be assumed to be most
appropriate can be selected and generated automatically from CALL !addr16, CALL !!addr20, and CALL
$!addr20.
[Coding example]
CALL !!13059H ; Subroutine call to 013059H
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Call Flag
Subroutine Call (11-Bit Direct Specification)
CALLF
[Instruction format]
CALLF target
Note
[Operation]
(SP – 3) ← (PC + 2),
SP ← SP – 3
PC ← target
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands (target)
!addr11
CALLF
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is a subroutine call that can branch to addresses 00800H to 00FFFH.
• The start address of the next instruction (PC + 2) is saved to the stack, and the program branches to an address
in the range 00800H to 00FFFH.
• Only the lower 11 bits of the address are specified (the higher 5 bits are fixed at 00001B).
• Locating the subroutine in the area from 00800H to 00FFFH and using this instruction enables the program size
to be reduced.
[Coding example]
CALLF !0C2AH ; Subroutine call to 00C2AH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Call Table
Subroutine Call (Call Table Reference)
CALLT
[Instruction format]
CALLT [addr5]
Note
[Operation]
(SP – 3) ← (PC + 1),
SP ← SP – 3,
PCHW ← 0
PCH ← (addr5 + 1)
PCL ← (addr5)
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
Mnemonic
Operands ([addr5])
[addr5]
CALLT
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is a call table reference subroutine call.
• The start address of the next instruction (PC + 1) is saved to the stack, and the program branches to the address
indicated by call table (higher bits of the address fixed at 0000000001B, next 5 bit specified by addr5, LSB fixed
at 0) word data.
• Subroutine start addresses that can be branched to by this instruction are limited to the base area (0 to FFFFH).
[Coding Example]
CALLT [60H] ; Uses the word data in addresses 00060H and 00061H as the address, and makes a subroutine
call to that address
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Break
BRK
Software Vectored Interrupt
[Instruction format]
[Operation]
BRK
(SP – 2) ← PSW,
(SP – 4) ← PC + 1,
IE ← 0
SP ← SP – 4,
PCHW ← 0,
PCLW ← (003EH)
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is a software interrupt instruction.
• The PSW and the address of the next instruction (PC + 1) are saved to the stack, then the IE flag is cleared
(0), and a branch is made to the address specified by the vector address (0003EH) word data (the branch
destination address is limited to the base area (0 to FFFFH)).
• The RETB instruction is used to return from a software vectored interrupt generated by this instruction.
[Coding Example]
BRK
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Break Context Switch
BRKCS
Software Context Switch
[Instruction format]
[Operation]
BRKCS RBn
PCLW ↔ RP2,
RP3 ← PSW, PC15–19
PC15–19 ← 0
RBS2 – 0 ← n,
RSS ← 0,
IE ← 0
(n = 0 to 7)
[Operands]
Mnemonic
Operands
BRKCS
RBn
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is a software interrupt instruction.
• Register bank n written in the operand is selected, the contents of RP2 in that register bank and the contents
of the lower 16 bits of the program counter (PC) are exchanged, the contents of the program status word (PSW)
and the higher 4 bits of the PC are saved to the stack, the higher 4 bits of the PC are set to 0, and a branch
is made to that address. The RSS flag and IE flag are then cleared to 0.
• Only addresses in the base area (0 to FFFFH) can be branched to by this instruction.
• The RETCSB instruction is used to return from a software interrupt generated by this instruction.
• The contents of RP2 and RP3 must not be changed in the software interrupt program initiated by this instruction.
If RP2 and RP3 are used, they must be saved to the stack, etc., and returned to their original value before the
RETCSB instruction is executed.
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Register bank
(0 to 7)
00008
Transfer
7
Register bank (n = 0 to 7)
A
B
X
C
PC19–16
PC15–0
6
Exchange
Save
RP2
RP3
VP
2
Save (Bits 8 to
11 of temporary
register)
5
3
4
Register
V
U
T
bank switchover
(RBS0-RBS2 ← n)
RSS ← 0
UP
Temporary register
D
H
E
L
IE ← 0
W
1
Save
PSW
[Coding Example]
BRKCS RB3 ; Selects register bank 3, and executes instructions from the address indicated by RP2 in register
bank 3
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Return
RET
Return from Subroutine
[Instruction format]
RET
Note
[Operation]
PC ← (SP),
SP ← SP + 3
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• This is the instruction for returning from a subroutine call made by a CALL, CALLF, or CALLT instruction.
• The data saved to the stack is restored to the PC, and a return is made from the subroutine.
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Return from Interrupt
Return from Hardware Vectored Interrupt
RETI
[Instruction format]
RETI
Note
[Operation]
PC ← (SP),
PSW ← (SP + 2),
PC ← SP + 4
The bit set (1) in ISPR with the highest priority is cleared (0).
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
None
[Flags]
S
R
Z
AC
R
P/V
R
CY
R
R
[Description]
• This is the instruction for returning from a vectored interrupt.
• The data saved in the stack is restored in PC and PSW, and of the flags set (1) in the ISPR register, the flag
with the highest priority is cleared (0), and operation then returns from the interrupt processing routine.
• This instruction cannot be used to return from a software interrupt generated by a BRK instruction, BRKCS
instruction or operand error, or from an interrupt that uses context switching.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Return from Break
Return from Software Vectored Interrupt
RETB
[Instruction format]
RETB
Note
[Operation]
PC ← (SP),
PSW ← (SP + 2),
PC ← SP + 4
Note For details, refer to CHAPTER 3, Figure 3-4 Data Saved to Stack Area, and Figure 3-5 Data Restored
from Stack Area.
[Operands]
None
[Flags]
S
R
Z
AC
R
P/V
R
CY
R
R
[Description]
• This is the instruction for returning from a software interrupt generated by an BRK instructions operand error.
• The PC and PSW saved to the stack are restored, and a return is made from the interrupt service routine.
• This instruction cannot be used to return from a hardware interrupt caused by a BRKCS instruction or hardware
interrupt
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Return from Context Switch
Return from Hardware Context Switch
RETCS
[Instruction format]
[Operation]
RETCS targer
PCLW ← RP2,
PC15–19 ← RP28–11
RP2 ← addr16,
PSW ← RP3
The bit set (1) in ISPR with the highest priority is cleared (0).
[Operands]
Mnemonic
Operands
!addr16
RETCS
[Flags]
S
R
Z
AC
R
P/V
R
CY
R
R
[Description]
• The contents of register banks RP2 and RP3 that are specified when this instruction is executed are transferred
to the program counter (PC) and program status word (PSW), and of the flags set (1) in the ISPR register, the
flag with the highest priority is cleared (0), and operation then returns from the interrupt processing routine.
The data specified by the operand is then transferred to RP2.
• The RETCS instruction is valid for context switching associated with generation of an interrupt request, and is
used to return from branch processing due to context switching. addr16 written in the operand is the branch
address used if the same register bank is specified again by the context switching function (only an address
in the base area can be specified as the branch destination address).
• This instruction cannot be used to return from a software interrupt generated by a BRK instruction, BRKCS
instruction or operand error, or from a vectored interrupt.
• Before this instruction is executed, the contents of RP2 and RP3 must be the same as immediately after interrupt
acknowledgment.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Register bank (n = 0 to 7)
A
B
X
C
PC19–16
PC15–0
1
Restore
RETCS instruction operand
Transfer
RP2
RP3
VP
2
Restore
3
V
U
T
4
Restore
UP
(To original
register bank)
D
H
E
L
W
PSW
[Coding example]
RETCS !03456H ; Returns from a context switching interrupt, and sets the address for acknowledgment of the
next interrupt to 03456H
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Return from Context Switch Break
Return from Software Context Switch
RETCSB
[Instruction format]
[Operation]
RETCSB target
PCLW ← RP2,
PC15–19 ← RP38–11
RP2 ← addr16,
PSW ← RP3
[Operands]
Mnemonic
Operands
!addr16
RETCSB
[Flags]
S
R
Z
AC
R
P/V
R
CY
R
R
[Description]
• The contents of RP2 and RP3 in the register bank specified when this instruction is executed are transferred
to the program counter (PC) and program status word (PSW), and a return is made from the interrupt service
routine.
The data specified by the operand is then transferred to RP2.
• The RETCSB instruction is valid for context switching by means of the BRKCS instruction, and is used to return
from branch processing due to context switching. addr16 written in the operand is the branch address used
if the same register bank is specified again by the context switching function (only an address in the base area
can be specified as the branch destination address).
• This instruction cannot be used to return from a software interrupt generated by a BRK instruction or operand
error, or from a hardware interrupt.
• Before this instruction is executed, the contents of RP2 and RP3 must be the same as immediately after interrupt
acknowledgment.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Register bank (n = 0 to 7)
A
B
X
C
PC19–16
PC15–0
1
Restore
RETCSB instruction operand
Transfer
RP2
RP3
VP
2
Restore
3
V
U
T
4
Restore
UP
(To original
register bank)
D
H
E
L
W
PSW
[Coding example]
RETCSB !0ABCDH ; Returns from an interrupt generated by a BRKCS instruction
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7.17 Unconditional Branch Instruction
There is one unconditional branch instruction, as follows.
BR ... 404
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Branch
BR
Unconditional Branch
[Instruction format]
[Operation]
BR target
PC ← target
[Operands]
Mnemonic
Operands (target)
BR
!addr16
!!addr20
rp
rg
[rp]
[rg]
$addr20
$!addr20
[Flags]
S
Z
AC
P/V
CY
[Description]
• Instruction that performs an unconditional branch.
• The target address operand (target) data is transferred to the PC, and a branch is made.
• If !addr16, rp or [rp] is specified as the operand, the branch destination address is limited to the base area (0
to FFFFH) (in the case of [rp], the branch destination table is also limited to the base area). This should only
be used when it is absolutely essential to reduce the execution time or object size, and when a 78K/0, 78K/I,
78K/II, or 78K/III Series software is used and program amendment is difficult. Amendments may be necessary
in order to make further use of a program that uses these instructions.
• With the NEC assembler RA78K4, if BR addr is written, the object code that can be assumed to be most
appropriate can be selected and generated automatically from BR $addr20, BR $!addr20, BR !addr16, and
BR!!addr20.
[Coding example]
BR TDE ; Branches using the contents of the TDE register as the address
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7.18 Conditional Branch Instructions
Conditional branch instructions are as follows:
BNZ ... 406
BNE ... 406
BZ ... 407
BE ... 407
BNC ... 408
BNL ... 408
BC ... 409
BL ... 409
BNV ... 410
BPO ... 410
BV ... 411
BPE ... 411
BP ... 412
BN ... 413
BLT ... 414
BGE ... 415
BLE ... 416
BGT ... 417
BNH ... 418
BH ... 419
BF ... 420
BT ... 421
BTCLR ... 422
BFSET ... 423
DBNZ ... 424
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Not Zero/Not Equal
Conditional Branch upon Zero Flag (Z = 0)
BNZ
BNE
[Instruction format]
BNZ $addr20
BNE $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if Z = 0
Mnemonic
BNZ
Operands ($addr20)
$addr20
BNE
[Flags]
S
Z
AC
P/V
CY
[Description]
• If Z = 0, the program branches to the address specified by the operand.
If Z = 1, no processing is performed and the next instruction is executed.
• The operation of the BNZ instruction and the BNE instruction is the same. They are used as follows:
– BNZ instruction: To check whether the result of an addition, subtraction or increment/decrement instruction,
or an 8-bit logical operation or shift/rotate instruction is 0.
– BNE instruction: Checks for a match after a compare instruction.
• If two –80H values are added together in the case of 8 bits when two’s complement type data addition is
performed, or two –8000H values in the case of 16 bits, Z is set to 1. When determining whether or not the result
of a two’s complement type data addition is 0, check for overflow beforehand using the overflow flag (V).
[Coding example]
CMP A, #55H
BNE $0A39H ; Branches to 00A39H if the A register is not 0055H
The start address of the BNE instruction must be in the range 009B8H to 00AB7H
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Branch if Zero/Equal than
Conditional Branch upon Zero Flag (Z = 1)
BZ
BE
[Instruction format]
BZ $addr20
BE $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if Z = 1
Mnemonic
Operands ($addr20)
$addr20
BZ
BE
[Flags]
S
Z
AC
P/V
CY
[Description]
• If Z = 1, the program branches to the address specified by the operand.
If Z = 0, no processing is performed and the next instruction is executed.
• The operation of the BZ instruction and the BE instruction is the same. They are used as follows:
– BZ instruction: To check whether the result of an addition, subtraction or increment/decrement instruction,
or an 8-bit logical operation or shift/rotate instruction is 0.
– BE instruction: Checks for a match after a compare instruction.
• If two –80H values are added together in the case of 8 bits when two’s complement type data addition is
performed, or two –8000H values in the case of 16 bits, Z is set to 1. When determining whether or not the result
of a two’s complement type data addition is 0, check for overflow beforehand using the overflow flag (V).
[Coding example]
DEC B
BZ $3C5H ; Branches to 003C5H if the B register is 0
The start address of the BZ instruction must be in the range 00344H to 00443H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Not Carry/Less than
Conditional Branch upon Carry Flag (CY = 0)
BNC
BNL
[Instruction format]
BNC $addr20
BNL $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if CY = 0
Mnemonic
BNC
Operands ($addr20)
$addr20
BNL
[Flags]
S
Z
AC
P/V
CY
[Description]
• If CY = 0, the program branches to the address specified by the operand.
If CY = 1, no processing is performed and the next instruction is executed.
• The operation of the BNC instruction and the BNL instruction is the same. Differences in their use are as follows:
– BNC instruction: Checks whether a carry has been generated after an addition or shift/rotate instruction.
Determines the result of bit manipulation.
– BNL instruction: Checks whether a borrow has been generated after a subtraction instruction.
After a compare instruction on unsigned data, checks whether or not the 1st operand of the
compare instruction is smaller.
[Coding example]
CMP A, B
; Compares the size of the A register contents and B register contents
BNL $1500H ; Branches to 01500H if the A register contents are smaller than the B register contents
The start address of the BNL instruction must be in the range 0147FH to 0157EH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Carry/Less than
Conditional Branch upon Carry Flag (CY = 1)
BC
BL
[Instruction format]
BC $addr20
BL $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if CY = 1
Mnemonic
Operands ($addr20)
$addr20
BC
BL
[Flags]
S
Z
AC
P/V
CY
[Description]
• If CY = 1, the program branches to the address specified by the operand.
If CY = 0, no processing is performed and the next instruction is executed.
• The operation of the BC instruction and the BL instruction is the same. They are used as follows:
– BC instruction : Checks whether a carry has been generated after an addition or shift/rotate instruction.
Determines the result of bit manipulation.
– BL instruction : Checks whether a borrow has been generated after a subtraction instruction.
After a compare instruction on unsigned data, checks whether or not the 1st operand of the
compare instruction is smaller.
[Coding example]
BC $300H ; Branches to 00300H if CY = 1
The start address of the BC instruction must be in the range 0027FH to 0037EH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if No Overflow/Branch if Parity Odd
Conditional Branch upon Parity/Overflow Flag (P/V = 0)
BNV
BPO
[Instruction format]
BNV $addr20
BPO $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if P/V = 0
Mnemonic
BNV
Operands ($addr20)
$addr20
BPO
[Flags]
S
Z
AC
P/V
CY
[Description]
• If P/V = 0, the program branches to the address specified by the operand.
If P/V = 1, no processing is performed and the next instruction is executed.
• The operation of the BNV instruction and the BPO instruction is the same. They are used as follows:
– BNV instruction : Checks that the result has neither overflowed nor underflowed after an operation of two’s
complement format data, etc.
– BPO instruction : Checks that the parity of the logical operation instruction or shift rotate instruction execution
result is odd.
[Coding example]
ADD B, C ; Adds together the contents of the B register and C register (two’s complement type data)
BNV $560H ; Branches to 560H if there is no overflow in the result of the addition
The start address of the BNV instruction must be in the range 004DFH to 05DEH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Overflow/Branch if Parity Even
Conditional Branch upon Parity/Overflow Flag (P/V = 1)
BV
BPE
[Instruction format]
BV $addr20
BPE $addr20
[Operation]
[Operands]
PC ← PC + 2 + jdisp8 if P/V = 1
Mnemonic
BV
Operands ($addr20)
$addr20
BPE
[Flags]
S
Z
AC
P/V
CY
[Description]
• If P/V = 1, the program branches to the address specified by the operand.
If P/V = 0, no processing is performed and the next instruction is executed.
• The operation of the BV instruction and the BPE instruction is the same. They are used as follows:
– BV instruction : Checks that the result has overflowed or underflowed after an operation of two’s complement
format data, etc.
– BPE instruction: Checks that the parity of the logical operation instruction or shift rotate instruction execution
result is even.
[Coding example]
OR D, #055H ; Finds the bit-wise logical sum of the D register contents and 055H
BPE $841EH ; Branches to 841EH if the parity is even as a result of finding the logical sum
The start address of this instruction must be in the range 839DH to 849CH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Positive
Conditional Branch upon Sign Flag (S = 0)
BP
[Instruction format]
[Operation]
BP $addr20
PC ← PC + 2 + jdisp8 if S = 0
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BP
[Flags]
S
Z
AC
P/V
CY
[Description]
• If S = 0, the program branches to the address specified by the operand.
If S = 1, no processing is performed and the next instruction is executed.
• This instruction is used to check whether the result is positive (including 0) after a two’s complement type data
operation. However, a correct judgment cannot be made if the operation result overflows or underflows;
therefore, a BV instruction or BNV instruction should be used beforehand to check that there is no overflow or
underflow, or the BGE instruction should be used.
[Coding example]
BV $OVER ; Branches to address OVER, if the operation result overflows or underflows
BP $TARGET ; Branches to address TARGET if the operation result is positive (including 0)
Address TARGET must be within –126 to +129 of the start address of the BP instruction
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Negative
Conditional Branch upon Sign Flag (S = 1)
BN
[Instruction format]
[Operation]
BN $addr20
PC ← PC + 2 + jdisp8 if S = 1
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BN
[Flags]
S
Z
AC
P/V
CY
[Description]
• If S = 1, the program branches to the address specified by the operand.
If S = 0, no processing is performed and the next instruction is executed.
• This instruction is used to check whether the result is negative after a two’s complement type data operation.
However, a correct judgment cannot be made if the operation result overflows or underflows; therefore, a BV
instruction or BNV instruction should be used beforehand to check that there is no overflow or underflow, or the
BLT instruction should be used.
[Coding example]
BN #TARGET ; Branches to address TARGET if the operation result is negative
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if less than
Conditional Branch upon Size of Number (Less than ... )
BLT
[Instruction format]
[Operation]
BLT $addr20
PC ← PC + 3 + jdisp8 if P/V S = 1
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BLT
[Flags]
S
Z
AC
P/V
CY
[Description]
• If P/V S = 1, the program branches to the address specified by the operand.
If P/V S = 0, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of two’s complement type data, or to check whether the
result of an operation is negative. In relative size determination, the instruction checks whether the 1st operand
of the CMP instruction executed immediately before is smaller than the 2nd operand. This instruction is also
used to check whether the operation result is negative, including the case where underflow has occurred.
[Coding example]
CMPW AX, #3456H
BLT $8123H
; Branches to address 8123H if the contents of the AX register are less than 3456H
The start address of the BLT instruction must be in the range 80A1H to 81A0H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Greater than/Equal
Conditional Branch upon Size of Number (Greater than or Equal to ... )
BGE
[Instruction format]
[Operation]
BGE $addr20
PC ← PC + 3 + jdisp8 if P/V S = 0
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BGE
[Flags]
S
Z
AC
P/V
CY
[Description]
• If P/V S = 0, the program branches to the address specified by the operand.
If P/V S = 1, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of two’s complement type data, or to check whether the
result of an operation is 0 or positive. In relative size determination, the instruction checks whether the 1st
operand of the CMP instruction executed immediately before is greater than the 2nd operand. This instruction
is also used to check whether the operation result is 0 or greater, including the case where overflow has occurred.
[Coding example]
ADDW AX, BC
BGE $23456H; Branches to address 23456H if the result of the immediately preceding addition instruction is 0
or greater
The start address of the BGE instruction must be in the range 233D4H to 234D3H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if less than/Equal
Conditional Branch upon Size of Number (Less than or Equal to ... )
BLE
[Instruction format]
[Operation]
BLE $addr20
PC ← PC + 3 + jdisp8 if (P/V S) Z = 1
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BLE
[Flags]
S
Z
AC
P/V
CY
[Description]
• If (P/V S) Z = 1, the program branches to the address specified by the operand.
If (P/V S) Z = 0, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of two’s complement type data, or to check whether the
result of an operation is negative, including 0. In relative size determination, the instruction checks whether the
1st operand of the CMP instruction executed immediately before is smaller than the 2nd operand. This instruction
is also used to check whether the operation result is negative, including the case where underflow has occurred.
[Coding example]
SUB H, L
BLE $789ABH ; Branches to 789ABH if the result of the immediately preceding subtraction instruction is 0 or less,
including the case where underflow has occurred
The start address of the BL instruction must be in the range 78929H to 789ABH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Greater than
Conditional Branch upon Size of Number (Greater than ... )
BGT
[Instruction format]
[Operation]
BGT $addr20
PC ← PC + 3 + jdisp8 if (P/V S) Z = 0
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BGT
[Flags]
S
Z
AC
P/V
CY
[Description]
• If (P/V S) Z = 0, the program branches to the address specified by the operand.
If (P/V S) Z = 1, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of two’s complement type data, or to check whether the
result of an operation is greater than 0. In relative size determination, the instruction checks whether the 1st
operand of the CMP instruction executed immediately before is greater than the 2nd operand. This instruction
is also used to check whether the operation result is greater than 0, including the case where overflow has
occurred.
[Coding example]
CMP A, E
BGT $0CFFEDH ;Branches to address 0CFFEDH if the contents of the A register are greater than the contents
of the B register
The start address of the BGT instruction must be in the range 0CFF6BH to 0D006DH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Not Higher than
Conditional Branch upon Size of Number (Not Higher than ... )
BNH
[Instruction format]
[Operation]
BNH $addr20
PC ← PC + 3 + jdisp8 if Z CY = 1
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BNH
[Flags]
S
Z
AC
P/V
CY
[Description]
• If Z CY = 1, the program branches to the address specified by the operand.
If Z CY = 0, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of unsigned data. The instruction checks whether the 1st
operand of the CMP instruction executed immediately before is not greater than the 2nd operand (i.e. the 1st
operand is the same as or smaller than the 2nd operand).
[Coding example]
CMPW RP2, #8921H
BNH $TARGET
; Branches to address TARGET if the contents of the RP2 register are not greater than
8921H (equal to or less than 8912H)
The start address of the BNH instruction must be an address from which a branch can be
made to address TARGET
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if Higher than
Conditional Branch upon Size of Number (Higher than ... )
BH
[Instruction format]
[Operation]
BH $addr20
PC ← PC + 3 + jdisp8 if Z CY = 0
[Operands]
Mnemonic
Operands ($addr20)
$addr20
BH
[Flags]
S
Z
AC
P/V
CY
[Description]
• If Z CY = 0, the program branches to the address specified by the operand.
If Z CY = 1, no processing is performed and the next instruction is executed.
• This instruction is used to determine the relative size of unsigned data. The instruction checks whether the 1st
operand of the CMP instruction executed immediately before is greater than the 2nd operand.
[Coding example]
CMP B, C
BH $356H ; Branches to 356H if the contents of the B register are greater than the contents of the C register
The start address of the BH instruction must be in the range 2D4H to 3D3H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if False
Conditional Branch depending on Bit Test (Byte Data Bit = 0)
BF
[Instruction format]
[Operation]
BF bit, $addr20
PC ← PC + b + jdisp8 if bit = 0
[Operands]
Mnemonic
Operands (bit, $addr20)
saddr.bit, $addr20
sfr.bit, $addr20
b (Number of Bytes)
BF
4/5
4
X.bit, $addr20
3
A.bit, $addr20
3
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
3
3
6
7
[Flags]
S
Z
AC
P/V
CY
[Description]
• If the contents of the 1st operand (bit) are cleared (0), the program branches to the address specified by the
2nd operand ($addr20).
If the contents of the 1st operand (bit) are not cleared (0), no processing is performed and the next instruction
is executed.
[Coding example]
BF P2.2, $1549H ; Branches to address 01549H if bit 2 of port 2 is 0
The start address of the BF instruction must be in the range 014C6H to 015C5H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if True
Conditional Branch depending on Bit Test (Byte Data Bit = 1)
BT
[Instruction format]
[Operation]
BT bit, $addr20
PC ← PC + b + jdisp8 if bit = 1
[Operands]
Mnemonic
Operands (bit, $addr20)
saddr.bit, $addr20
sfr.bit, $addr20
b (Number of Bytes)
BF
3/4
4
X.bit, $addr20
3
A.bit, $addr20
3
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
3
3
6
7
[Flags]
S
Z
AC
P/V
CY
[Description]
• If the contents of the 1st operand (bit) are set (1), the program branches to the address specified by the 2nd
operand ($addr16).
If the contents of the 1st operand (bit) are not set (1), no processing is performed and the next instruction is
executed.
[Coding example]
BT 0FE47H.3, $55CH ; Branches to 0055CH if bit 3 of address 0FE47H
The start address of the BT instruction must be in the range 004D9H to 005D8H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if True and Clear
Conditional Branch and Clear depending on Bit Test (Byte Data Bit = 1)
BTCLR
[Instruction format]
[Operation]
BTCLR bit, $addr20
PC ← PC + b + jdisp8 if bit = 1, then bit ← 0
[Operands]
Mnemonic
Operands (bit, $addr20)
saddr.bit, $addr20
sfr.bit, $addr20
b (Number of Bytes)
BTCLR
4/5
4
X.bit, $addr20
3
A.bit, $addr20
3
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
3
3
6
7
[Flags]
bit is PSWL.bit
In other cases
S
Z
AC
P/V
CY
S
Z
AC
P/V
CY
×
×
×
×
×
[Description]
• If the contents of the 1st operand (bit) are set (1), the contents of the 1st operand (bit) are cleared (0), and the
program branches to the address specified by the 2nd operand.
If the contents of the 1st operand (bit) are not set (1), no processing is performed and the next instruction is
executed.
• If the 1st operand (bit) is PSW.bit, the contents of the relevant flag are cleared (0).
[Coding example]
BTCLR PSW.0, $356H ;If bit 0 of the PSW (CY flag) is 1, clears (0) the CY flag and branches to address 00356H
The start address of the BTCLR instruction must be in the range 002D4H to 003D3H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Branch if False and Set
Conditional Branch and Set depending on Bit Test (Byte Data Bit = 0)
BFSET
[Instruction format]
[Operation]
BFSET bit, $addr20
PC ← PC + b + jdisp8 if bit = 0, then bit ← 1
[Operands]
Mnemonic
Operands (bit, $addr20)
saddr.bit, $addr20
sfr.bit, $addr20
b (Number of Bytes)
BFSET
4/5
4
X.bit, $addr20
3
A.bit, $addr20
3
PSWL.bit, $addr20
PSWH.bit, $addr20
mem2.bit, $addr20
!addr16.bit, $addr20
!!addr24.bit, $addr20
3
3
3
6
7
[Flags]
bit is PSWL.bit
In other cases
S
Z
AC
P/V
CY
S
Z
AC
P/V
CY
×
×
×
×
×
[Description]
• If the contents of the 1st operand (bit) are cleared (0), the contents of the 1st operand (bit) are set (1), and the
program branches to the address specified by the 2nd operand.
If the contents of the 1st operand (bit) are set (1), no processing is performed and the next instruction is executed.
• If the 1st operand (bit) is PSW.bit, the contents of the relevant flag are set (1).
[Coding example]
BFSET A.6, $3FFE1H ;If bit 6 of the A register is 0, sets (1) bit 6 of the A register and branches to address 3FFE1H
The start address of the BFSET instruction must be in the range 3FF5FH to 4005EH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Decrement and Branch if Not Zero
Conditional Loop (dst ≠ 0)
DBNZ
[Instruction format]
[Operation]
DBNZ dst, $addr20
dst ← dst – 1,
then PC ← PC + b + jdisp8 if dst ≠ 0
[Operands]
Mnemonic
Operands (bit, $addr20)
B, $addr20
b (Number of Bytes)
DBNZ
2
2
C, $addr20
saddr, $addr20
3/4
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the destination operand (dst) specified by the 1st operand are decremented by 1, and the program
branches to the destination operand (dst).
• If the result of decrementing the destination operand (dst) by 1 is not 0, the program branches to the address
indicated by the 2nd operand ($addr20). If the result of decrementing the destination operand (dst) by 1 is 0,
no processing is performed and the next instruction is executed.
• Flags are not changed.
[Coding example]
DBNZ B, $1215H ; Decrements the contents of the B register, and if 0, branches to 001215H
The start address of the DBNZ instruction must be in the range 001194H to 001293H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.19 CPU Control Instructions
CPU control instructions are as follows:
MOV STBC, #byte ... 426
MOV WDM, #byte ... 427
LOCATION ... 428
SEL RBn ... 429
SEL RBn, ALT ... 430
SWRS ... 431
NOP ... 432
EI ... 433
DI ... 434
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move
MOV STBC, #byte
Standby Mode Setting
[Instruction format]
[Operation]
MOV STBC #byte
STBC ← byte
[Operands]
Mnemonic
Operands
MOV
STBC, #byte
[Flags]
S
Z
AC
P/V
CY
[Description]
• This a special instruction for writing to the standby control register (STBC). The immediate data specified by
the 2nd operand is written to STBC. The STBC register can only be written to by means of this instruction.
• This instruction has a special format, and in addition to the immediate data used to perform the write, the logical
NOT of that value must also be provided in the operation code (see figure below). (This is generated automatically
by the NEC assembler (RA78K4).)
– Operation code format
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
→
→
←
←
byte
byte
• The CPU checks the immediate data to be used for the write and the logical NOT data, and only performs the
write if they are correct. If they are not correct, the write is not performed and an operand error interrupt is
generated.
[Coding example]
MOV STBC, #2 ; Writes 2 to STBC (sets the STOP mode)
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move
MOV WDM, #byte
Watchdog Timer Setting
[Instruction format]
[Operation]
MOV WDM #byte
WDM ← byte
[Operands]
Mnemonic
Operands
MOV
WDM, #byte
[Flags]
S
Z
AC
P/V
CY
[Description]
• This a special instruction for writing to the watchdog timer mode register (WDM). The immediate data specified
by the 2nd operand is written to WDM. The WDM register can only be written to by means of this instruction.
• This instruction can only be used with a product that incorporates a watchdog timer. Please refer to the User’s
Manual — Hardware for the relevant product to see whether a watchdog timer is incorporated.
• This instruction has a special format, and in addition to the immediate data used to perform the write, the logical
NOT of that value must also be provided in the operation code (see figure below). (This is generated automatically
by the NEC assembler (RA78K4).)
– Operation code format
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
0
→
→
←
←
byte
byte
• The CPU checks the immediate data to be used for the write and the logical NOT data, and only performs the
write if they are correct. If they are not correct, the write is not performed and an operand error interrupt is
generated.
[Coding example]
MOV WDM, #0C0H ; Writes 0C0H to WDM
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Location
Location
LOCATION
[Instruction format]
[Operation]
LOCATION locaddr
SFR & internal data area location address upper word specification
[Operands]
Mnemonic
Operands
locaddr
LOCATION
[Flags]
S
Z
AC
P/V
CY
[Description]
• This instruction is used to specify the address of the internal data area (internal RAM and special function
registers (SFRs)). If 0 is specified, the maximum address of the internal data area is 0FFFFH, and if 0FH is
specified, the maximum address of the internal data area is 0FFFFFH.
• An interrupt or macro service request is not acknowledged between this instruction and the next instruction.
• This instruction must always be executed immediately after reset release. That is, this instruction must be located
in the address specified by the reset vector. This instruction cannot be used more than once. If executed more
than once, an address in the internal data area cannot be changed in the second or subsequent executions.
• The operand for this instruction is coded as shown below.
locaddr
0H
Operand Code
01FEH
0FH
00FFH
Execution of this instruction is ignored if a different value is specified. Also, an operand error interrupt is
generated if the exclusive logical sum of the upper byte and lower byte of the operand is not 0FFH.
[Coding example]
LOCATION 0FH ; Sets the maximum address of the internal data area to 0FFFFFH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Select Register Bank
SEL RBn
Register Bank Selection
[Instruction format]
[Operation]
SEL RBn
RSS ← 0, RBS2 – 0 ← n ; (n = 0 – 3)
[Operands]
Mnemonic
Operands (RBn)
RBn
SEL
[Flags]
S
Z
AC
P/V
CY
[Description]
• Selects the register bank specified by the operand (RBn) as the register bank to be used from the next instruction
onward.
• The range for RBn is RB0 to RB7.
[Coding example]
SEL RB2 ; Selects register bank 2 as the register bank to be used from the next instruction onward.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Select Register Bank
SEL RBn, ALT
Register Bank Selection
[Instruction format]
[Operation]
SEL RBn, ALT
RSS1 ← 1, RBS2 – 0 ← n ; (n = 0 – 3)
[Operands]
Mnemonic
Operands
RBn, ALT
S EL
[Flags]
S
Z
AC
P/V
CY
[Description]
• Selects the register bank specified by the 1st operand (RBn) as the register bank to be used from the next
instruction onward, and also sets (1) the register selection flag (RSS).
• The range for RBn is RB0 to RB7.
• This instruction is provided to maintain compatibility with the 78K/III Series, and can only be used when a 78K/
III Series program is used. It should not be used when using a program for a 78K Series other than the 78K/
III Series or when using a newly written program.
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Switch Register Set
SWRS
Register Bit Switching
[Instruction format]
[Operation]
SWRS
RSS ← RSS
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• Inverts the contents of the register set selection flag (RSS).
• This instruction is provided to maintain compatibility with the 78K/III Series, and can only be used when a 78K/
III Series program is used. It should not be used when using a program for a 78K Series other than the 78K/
III Series or when using a newly written program.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
No Operation
No Operation
NOP
[Instruction format]
[Operation]
NOP
No Operation
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• This instruction simply consumes time without performing any processing.
432
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Enable interrupt
EI
Interrupt Enabling
[Instruction format]
[Operation]
EI
IE ← 1 (Enable interrupt)
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• Sets the state in which maskable interrupts can be acknowledged (sets (1) the interrupt enable flag (IE)).
• No interrupts or macro service requests are acknowledged for a certain period after execution of this instruction.
Please refer to the User’s Manual — Hardware for the relevant product for details.
• It is possible to arrange for acknowledgment of vectored interrupts from other sources not to be performed even
though this instruction is executed. Please refer to the User’s Manual — Hardware for the individual products
for details.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Disable interrupt
DI
Interrupt Disabling
[Instruction format]
[Operation]
DI
IE ← 0 (Disable interrupt)
[Operands]
None
[Flags]
S
Z
AC
P/V
CY
[Description]
• Disables acknowledgment by vectored interrupts among maskable interrupts (clears (0) the interrupt enable flag
(IE)).
• No interrupts or macro service requests are acknowledged for a certain period after execution of this instruction.
Please refer to the User’s Manual — Hardware for the relevant product for details.
• Please refer to the User’s Manual — Hardware for the individual products for details of interrupt servicing.
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7.20 Special Instructions
Special instructions are as follows.
CHKL ... 436
CHKLA ... 437
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Check Level
CHKL
Pin Output Level Check
[Instruction format]
[Operation]
CHKL sfr
(Pin level) (output latch)
[Operands]
Mnemonic
Operands
sfr
CHKL
[Flags]
S
Z
AC
P/V
P
CY
×
×
[Description]
• The exclusive logical sum of the output pin level and output buffer prestage signal level is found.
• The S flag is set (1) if bit 7 is set (1) as a result of the exclusive logical sum operation, and S flag is cleared
(0) if bit 7 is cleared (0).
• The Z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and Z flag is cleared (0)
if there are non-zero bits.
• The P/V flag is set (1) if the number of bits in the data set (1) as a result of the exclusive logical sum operation
is even, and cleared (0) if the number is odd.
• This instruction is used to detect an abnormal state which has arisen for some reason or other in which the output
pin level and the output buffer prestage signal level are different. In normal operation, the Z flag is always set
(1).
• When this instruction is executed, with a product that has a port read control register (PRDC), the PRDC0 bit
of the PRDC register must be cleared (0). An abnormal state cannot be detected if the PRDC0 bit is set (1).
• When this instruction is executed on a port that includes a pin used as a control output, the input/output mode
for the port with a pin used as a control output must be set to input mode. If the input/output mode for a port
with a pin used as a control output is set to output mode, operation may be judged to be abnormal even though
it is normal.
• A pin for which the input/output mode as a port is specified as the input mode will always be judged to be normal
by this instruction.
[Coding example]
CHKL P0
BNZ $ERROR ; Checks whether the port 0 pin level and output buffer prestage signal level match, and if they do
not, branches to address ERROR
Caution The CHKL instruction is not available in the µPD784216A, 784216AY, 784218A, 784218AY, 784225,
784225Y, 784938A Subseries. Do not execute this instruction. If this instruction is executed, the
following condition will result.
• After the pin levels of output pins are read two times, they are exclusive-ORed. As a result,
if the pins checked with this instruction are used in the port output mode, the exclusive-OR
result is always 0 for all bits, and the Z flag is set to (1).
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Check Level and Transfer to Register
Pin Output Level Check and Transfer to Register
CHKLA
[Instruction format]
[Operation]
CHKLA sfr
A ← (Pin level) (output latch)
[Operands]
Mnemonic
Operands
sfr
CHKLA
[Flags]
S
Z
AC
P/V
P
CY
×
×
[Description]
• The exclusive logical sum of the output pin level and output buffer prestage signal level is found, and the result
is stored in the A register.
• The S flag is set (1) if bit 7 is set (1) as a result of the exclusive logical sum operation, and S flag is cleared
(0) if bit 7 is cleared (0).
• The Z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and Z flag is cleared (0)
if there are non-zero bits.
• The P/V flag is set (1) if the number of bits in the data set (1) as a result of the exclusive logical sum operation
is even, and cleared (0) if the number is odd.
• This instruction is used to detect an abnormal state which has arisen for some reason or other in which the output
pin level and the output buffer prestage signal level are different. In normal operation, the Z flag is always set
(1).
• When this instruction is executed, with a product that has a port read control register (PRDC), the PRDC0 bit
of the PRDC register must be cleared (0). An abnormal state cannot be detected if the PRDC0 bit is set (1).
• When this instruction is executed on a port that includes a pin used as a control output, the input/output mode
for the port with a pin used as a control output must be set to input mode. If the input/output mode for a port
with a pin used as a control output is set to output mode, operation may be judged to be abnormal even though
it is normal.
• A pin for which the input/output mode as a port is specified as the input mode will always be judged to be normal
by this instruction.
[Coding example]
CHKLA P3 ; Checks whether the port 3 pin level and output buffer prestage signal level match, and stores the
result in the A register
Caution The CHKLA instruction is not available in the µPD784216A, 784216AY, 784218A, 784218AY,
784225, 784225Y, 784938A Subseries. Do not execute this instruction. If this instruction is
executed, the following condition will result.
• After the pin levels of output pins are read two times, they are Exclusive-ORed. As a result,
if the pins checked with this instruction are used in the port output mode, the exclusive-OR
result is always 0 for all bits, and the Z flag is set to (1) along with that the result is saved in
the A register.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7.21 String Instructions
String instructions are as follows.
MOVTBLW ... 439
MOVM ... 441
XCHM ... 443
MOVBK ... 445
XCHBK ... 448
CMPME ... 451
CMPMNE ... 454
CMPMC ... 457
CMPMNC ... 460
CMPBKE ... 463
CMPBKNE ... 466
CMPBKC ... 469
CMPBKNC ... 472
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Move Table Word
MOVTBLW
Table Word Transfer
[Instruction format]
[Operation]
MOVTBLW !addr8, byte
(addr8 + 2) ← (addr8),
byte ← byte – 1,
addr8 ← addr8 – 2,
End if byte = 0
[Operands]
Mnemonic
Operands
MOVTBLW
!addr16, byte
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the memory addressed by the 16 bits immediate data specified by the 1st operand are transferred
to the address incremented by 2. addr8 is then decremented by 2. The above operations are repeated the
number of times indicated by the 8 bits immediate data written as the 2nd operand.
• This instruction is used to shift the data table used by the MACW and MACSW instructions.
• The address of the most significant data of the data on which the transfer is to be performed is written directly
in the 1st operand !addr8 as a label or number.
• The address written as the 1st operand must be in the range 00FE00H to 00FEFFH when a LOCATION 0H
instruction is executed, or in the range 0FFE00H to 0FFEFFH when a LOCATION 0FH instruction is executed.
Remark The µPD784915 Subseries is fixed to the LOCATION 0H instruction.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
MOVTBLW
(addr8 + 2) ← (addr8)
addr8 ← addr8 – 2
byte ← byte – 1
No
byte = 0?
Yes
END
[Coding example]
MOVTBLW !0FFE60H, 5 ; Transfers the data in 0FFE58H through 0FFE60H to 0FFE5AH through 0FFE62H
Before execution
After execution
15
0
15
0
0BA98H
0123H
0FE62H
0FE60H
0123H
4567H
0FE60H
5 words
4567H
89ABH
89ABH
0CDEFH
0FEDCH
0FEDCH
0CDEFH
0FEDCH
0FE58H
0FE58H
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Move Multiple Byte
Block Transfer of Fixed Byte Data
MOVM
[Instruction format]
[Operation]
MOVM [TDE +], A
MOVM [TDE –], A
(TDE) ← A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ← A, TDE ← TDE – 1, C ← C – 1 End if C = 0
[Operands]
Mnemonic
Operands
[TDE + ], A
MOVM
[TDE – ], A
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the A register are transferred to the memory addressed by the TDE register, and the contents
of the TDE register are incremented/decremented. The contents of the C register are then decremented, and
the above operations are repeated until the contents of the C register are 0.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• This instruction is mainly used to initialize a certain area of memory with a specific value. The MOVBK instruction
is used to perform initialization with multi-byte data.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
MOVM
(TDE) ← A
TDE ← TDE ±1Note
C ← C – 1
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
7
0
A register
C byte
TDE
[Coding example]
MOV C, #00H
; C ← 00H
; A ← 00H
MOV A, #00H
MOVG TDE, #0FE00H ; TDE ← FE00H
MOVM [TDE +], A ; Clears RAM FE00H to FEFFH
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Exchange Multiple Byte
Block Exchange of Fixed Byte Data
XCHM
[Instruction format]
[Operation]
XCHM [TDE + ], A
XCHM [TDE – ], A
(TDE) ↔ A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ↔ A, TDE ← TDE – 1, C ← C – 1 End if C = 0
[Operands]
Mnemonic
Operands
[TDE + ], A
XCHM
[TDE – ], A
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the A register are exchanged with the contents of the memory addressed by the TDE register,
and the contents of the TDE register are incremented/decremented. The contents of the C register are then
decremented, and the above operations are repeated until the contents of the C register are 0.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• This instruction is mainly used to perform a one-byte move of data in memory. XCHM [TDE + ], A is used for
a move in the upper address direction, and XCHM [TDE – ], A for a move in the low-order address direction.
The MOVBK instruction is used to move two or more bytes.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
XCHM
(TDE) ↔ A
TDE ← TDE ±1Note
C ← C – 1
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
7
0
A register
C byte
TDE
[Coding example]
MOV C, #10H
; C ← 10H
; A ← 00H
MOV A, #00H
MOVG TDE, #3050H ; TDE ← 3050H
XCHM [TDE +], A
; Shifts the contents of memory 3050H through 305FH one address at a time into the
addresses behind (the contents of address 3050H become 0)
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Move Block Byte
MOVBK
Byte Data Block Transfer
[Instruction format]
[Operation]
MOVBK [TDE +], [WHL + ]
MOVBK [TDE – ], [WHL – ]
(TDE) ← (WHL), TDE ← TDE + 1, WHL ← WHL + 1 C ← C – 1
End if C = 0
(TDE) ← (WHL), TDE ← TDE – 1, WHL ← WHL – 1 C ← C – 1
End if C = 0
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
MOVBK
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the memory addressed by the WHL register are transferred to the memory addressed by the
TDE register, and the contents of the TDE and WHL registers are incremented/decremented. The contents of
the C register are then decremented, and the above operations are repeated until the contents of the C register
are 0.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
• If the transfer source data area and transfer destination data area overlap, the operation is as follows.
– If the minimum address of the transfer source is smaller than the maximum address of the transfer destination,
the respective minimum addresses are used as the initial values for both the TDE and the WHL register, and
MOVBK [TDE + ], [WHL + ] is used.
– If the maximum address of the transfer source is greater than the minimum address of the transfer destination,
the respective maximum addresses are used as the initial values for both the TDE and the WHL register, and
MOVBK [TDE – ], [WHL – ] is used.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
MOVBK
(TDE) ← (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C – 1
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
7
0
C byte
WHL
TDE
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[Coding example]
MOV C, #10H
; C ← 10H
MOVG TDE, #3000H
MOVG WHL, #5000H
; TDE ← 3000H
; WHL ← 5000H
MOVBK [TDE + ], [WHL + ] ; Transfers the contents of memory 5000H through 500FH to memory 3000H through
300FH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Exchange Block Byte
XCHBK
Byte Data Block Exchange
[Instruction format]
[Operation]
XCHBK [TDE +], [WHL + ]
XCHBK [TDE – ], [WHL – ]
(TDE) ↔ (WHL), TDE ← TDE + 1,
WHL ← WHL + 1 C ← C – 1 End if C = 0
(TDE) ↔ (WHL), TDE ← TDE – 1,
WHL ← WHL – 1 C ← C – 1 End if C = 0
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
XCHBK
[Flags]
S
Z
AC
P/V
CY
[Description]
• The contents of the memory addressed by the WHL register are exchanged with the contents of the memory
addressed by the TDE register, and the contents of the WHL and TDE registers are incremented/decremented.
The contents of the C register are then decremented, and the above operations are repeated until the contents
of the C register are 0.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
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XCHBK
(TDE) ← (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C – 1
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
7
0
C byte
WHL
TDE
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
[Coding example]
MOV C, #80H
MOVG TDE, #3456H
MOVG WHL, #1FF96H
XCHBK [TDE + ], [WHL + ] ; Exchanges the 80H-byte data from address 3456H with the data from address 1FF96H
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Compare Multiple Equal Byte
Block Comparison with Fixed Byte Data (Match Detection)
CMPME
[Instruction format]
[Operation]
CMPME [TDE + ], A
CMPME [TDE – ], A
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 0
[Operands]
Mnemonic
Operands
[TDE + ], A
CMPME
[TDE – ], A
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the A register are compared with the contents of the memory addressed by the TDE register,
the contents of the TDE register are incremented/decremented, and the contents of the C register are
decremented. The above operations are repeated until the result of the comparison is a mismatch, or the contents
of the C register are 0.
• Execution of this instruction does not change the contents of the A register or of the memory addressed by the
TDE register.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPME
S, Z, AC, P/V, CY
← (TDE) – A
TDE ← TDE ±1Note
C ← C – 1
Yes
Z = 0?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
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End of execution
7
0
Yes
=?
No
Yes
A register
C byte
TDE
Yes
Yes
=?
No
=?
No
End of execution
[Coding example]
MOV C, #20H
MOVG TDE, #56283H
MOV A, #00H
CMPME [TDE +], A ; Indicates whether the 20H-byte data from address 56283H is all 00H
BNZ $JMP
; Branches to address JMP if there is data that is not 00H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Multiple Not Equal Byte
Block Comparison with Fixed Byte Data (Mismatch Detection)
CMPMNE
[Instruction format]
[Operation]
CMPMNE [TDE + ], A
CMPMNE [TDE – ], A
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 1
[Operands]
Mnemonic
Operands
[TDE + ], A
CMPMNE
[TDE – ], A
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the A register are compared with the contents of the memory addressed by the TDE register,
the contents of the TDE register are incremented/decremented, and the contents of the C register are
decremented. The above operations are repeated until the result of the comparison is a match or the contents
of the C register are 0.
• Execution of this instruction does not change the contents of the A register or of the memory addressed by the
TDE register.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPMNE
S, Z, AC, P/V, CY
← (TDE) – A
TDE ← TDE ±1Note
C ← C – 1
Yes
Z = 1?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
End of execution
7
0
Yes
≠?
No
Yes
A register
C byte
TDE
Yes
Yes
≠?
No
≠?
No
End of execution
[Coding example]
MOV C, #00H
; C ← 00H
MOVG TDE, #3000H ; TDE ← 3000H
CMPMNE [TDE +], A
BZ $IMP
; Branches to the address indicated by label IMP if the same value as that of the A register
is in 3000H to 30FFH
456
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Multiple Carry Byte
Block Comparison with Fixed Byte Data (Size Comparison)
CMPMC
[Instruction format]
[Operation]
CMPMC [TDE + ], A
CMPMC [TDE – ], A
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 0
[Operands]
Mnemonic
Operands
[TDE + ], A
CMPMC
[TDE – ], A
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the A register are compared with the contents of the memory addressed by the TDE register,
the contents of the TDE register are incremented/decremented, and the contents of the C register are
decremented. The above operations are repeated until the result of the comparison is that the contents of the
memory addressed by the TDE register are equal to or greater than the contents of the A register, or the contents
of the C register are 0.
• Execution of this instruction does not change the contents of the A register or of the memory addressed by the
TDE register.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPMC
S, Z, AC, P/V, CY
← (TDE) – A
TDE ← TDE ±1Note
C ← C – 1
Yes
CY = 0?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
458
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
End of execution
7
0
Yes
<?
No
Yes
A register
C byte
TDE
Yes
Yes
<?
No
<?
No
End of execution
[Coding example]
MOV C, #10H
MOV A, #80H
MOVG TDE, #567800H
CMPMC [TDE +], A
BNC $BIG
; Branches to address BIG if data of 80H or above is present in the 10H-byte data from
address 567800H
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Multiple Not Carry Byte
Block Comparison with Fixed Byte Data (Size Comparison)
CMPMNC
[Instruction format]
[Operation]
CMPMNC [TDE + ], A
CMPMNC [TDE – ], A
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 1
[Operands]
Mnemonic
Operands
[TDE + ], A
CMPMNC
[TDE – ], A
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the A register are compared with the contents of the memory addressed by the TDE register,
the contents of the TDE register are incremented/decremented, and the contents of the C register are
decremented. The above operations are repeated until the result of the comparison is that the contents of the
A register are greater, or the contents of the C register are 0.
• Execution of this instruction does not change the contents of the A register or of the memory addressed by the
TDE register.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE and C registers used by this
instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the interrupted
instruction is resumed upon returning from the interrupt. When a macro service request is acknowledged,
execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
•
The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPMNC
S, Z, AC, P/V, CY
← (TDE) – A
TDE ← TDE ±1Note
C ← C – 1
Yes
CY = 1?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
User’s Manual U10905EJ8V1UM
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
End of execution
7
0
Yes
≥?
No
Yes
A register
C byte
TDE
Yes
Yes
≥?
No
≥?
No
End of execution
[Coding example]
MOV C, #00H
; C ← 00H
MOVG TDE, #8000H ; TDE ← 8000H
CMPMNC [TDE +], A
BC $JMP
; Branches to the address indicated by label JMP if there is a value greater than the contents
of the A register in 8000H to 80FFH
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Block Equal Byte
Block Comparison with Byte Data (Match Detection)
CMPBKE
[Instruction format]
[Operation]
CMPBKE [TDE + ], [WHL + ]
CMPBKE [TDE – ], [WHL – ]
(TDE) – (WHL), TDE ← TDE + 1, WHL ← WHL + 1, C ← C – 1
End if C = 0 or Z = 0
(TDE) – (WHL), TDE ← TDE – 1, WHL ← WHL – 1, C ← C – 1
End if C = 0 or Z = 0
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
CMPBKE
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the memory addressed by the WHL register are compared with the contents of the memory
addressed by the TDE register, the contents of the TDE and WHL registers are incremented/decremented, and
the contents of the C register are decremented. The above operations are repeated until the result of the
comparison is a mismatch, or the contents of the C register are 0.
• Execution of this instruction does not change the contents of the memory addressed by the TDE and WHL
registers.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
•
The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPBKE
S, Z, AC, P/V, CY
← (TDE) – (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C–1
Yes
Z = 0?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
464
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7
0
C byte
WHL
End of execution
Yes
=?
No
Yes
Yes
=?
No
Yes
TDE
=?
No
End of execution
[Coding example]
MOV C, #40H
MOVG TDE, #342156H
MOVG WHL, #3421AAH
CMPBKE [TDE +], [WHL +]
BNE $DIFF
; Compares the 40H-byte data from address 342156H with the data from address
3421AAH, and branches to address DIFF if there is different data
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Block Not Equal Byte
Block Comparison with Byte Data (Mismatch Detection)
CMPBKNE
[Instruction format]
[Operation]
CMPBKNE [TDE + ], [WHL + ]
CMPBKNE [TDE – ], [WHL – ]
(TDE) – (WHL), TDE ← TDE + 1, WHL ← WHL + 1, C ← C – 1
End if C = 0 or Z = 1
(TDE) – (WHL), TDE ← TDE – 1, WHL ← WHL – 1, C ← C – 1
End if C = 0 or Z = 1
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
CMPBKNE
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the memory addressed by the WHL register are compared with the contents of the memory
addressed by the TDE register, the contents of the TDE and WHL registers are incremented/decremented, and
the contents of the C register are decremented. The above operations are repeated until the result of the
comparison is a match, or the contents of the C register are 0.
• Execution of this instruction does not change the contents of the memory addressed by the TDE and WHL
registers.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
• The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPBKNE
S, Z, AC, P/V, CY
← (TDE) – (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C – 1
Yes
Z = 1?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7
0
C byte
WHL
End of execution
Yes
≠?
No
Yes
Yes
≠?
No
Yes
TDE
≠?
No
End of execution
[Coding example]
MOV C, #5H
MOVG TDE, #0FFC50H
MOVG WHL, #0FC50H
CMPBKNE [TDE +], [WHL +]
BE $FIND
; Compares the 5-byte data from address 0FFC50H with the data from address
0FC50H, and branches to address FIND if there is matching data
468
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Block Carry Byte
Block Comparison with Byte Data (Size Detection)
CMPBKC
[Instruction format]
[Operation]
CMPBKC [TDE + ], [WHL + ]
CMPBKC [TDE – ], [WHL – ]
(TDE) – (WHL), TDE ← TDE + 1, WHL ← WHL + 1, C ← C – 1
End if C = 0 or CY = 0
(TDE) – (WHL), TDE ← TDE – 1, WHL ← WHL – 1, C ← C – 1
End if C = 0 or CY = 0
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
CMPBKC
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the memory addressed by the WHL register are compared with the contents of the memory
addressed by the TDE register, the contents of the TDE and WHL registers are incremented/decremented, and
the contents of the C register are decremented. The above operations are repeated until the result of the
comparison is that the contents of the memory addressed by the TDE register are equal to or greater than the
contents of the memory addressed by the WHL register, or the contents of the C register are 0.
• Execution of this instruction does not change the contents of the memory addressed by the TDE and WHL
registers.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
•
The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPBKC
S, Z, AC, P/V, CY
← (TDE) – (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C – 1
Yes
CY = 0?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
470
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7
0
C byte
WHL
End of execution
Yes
<?
No
Yes
Yes
<?
No
Yes
TDE
<?
No
End of execution
[Coding example]
MOV C, #3H
MOVG TDE, #0E8762H
MOVG WHL, #03502H
CMPBKC [TDE – ], [WHL – ]
BNC $BIG
; Compares the 3-byte data from address 0E8760H with the 3-byte data from
address 03500H, and branches to address BIG if the result of the comparison is
that the values are the same or the 3-byte data from address 0E8760H is greater
User’s Manual U10905EJ8V1UM
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
Compare Block Not Carry Byte
Fixed Byte Data Block Comparison (Size Comparison)
CMPBKNC
[Instruction format]
[Operation]
CMPBKNC [TDE + ], [WHL + ]
CMPBKNC [TDE – ], [WHL – ]
(TDE) – (WHL), TDE ← TDE + 1, WHL ← WHL + 1, C ← C – 1
End if C = 0 or CY = 1
(TDE) – (WHL), TDE ← TDE – 1, WHL ← WHL – 1, C ← C – 1
End if C = 0 or CY = 1
[Operands]
Mnemonic
Operands
[TDE + ], [WHL + ]
[TDE – ], [WHL – ]
CMPBKNC
[Flags]
S
Z
AC
P/V
V
CY
×
×
×
×
[Description]
• The contents of the memory addressed by the WHL register are compared with the contents of the memory
addressed by the TDE register, the contents of the TDE and WHL registers are incremented/decremented, and
the contents of the C register are decremented. The above operations are repeated until the result of the
comparison is that the contents of the memory addressed by the WHL register are greater, or the contents of
the C register are 0.
• Execution of this instruction does not change the contents of the memory addressed by the TDE and WHL
registers.
• If an acknowledgeable interrupt or macro service request is generated during execution of this instruction,
execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. When
an interrupt is acknowledged, if the return address and the contents of the TDE, WHL, and C registers used
by this instruction which have been saved to the stack or to RP2 and R7 are not changed, execution of the
interrupted instruction is resumed upon returning from the interrupt. When a macro service request is
acknowledged, execution of this instruction is resumed after completion of the macro service.
• The S, Z, AC, P/V, and CY flags are changed in accordance with the last compare operation (subtraction)
executed by this instruction.
• The S flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise.
• The Z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise.
• The AC flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared
(0) otherwise.
• The P/V flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the
subtraction (when underflow is generated by a two’s complement type operation), or if a borrow is not generated
in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a two’s complement type operation),
and is cleared (0) otherwise.
•
The CY flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise.
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CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
CMPBKNC
S, Z, AC, P/V, CY
← (TDE) – (WHL)
TDE ← TDE ±1Note
WHL ← WHL ±1Note
C ← C – 1
Yes
CY = 1?
No
No
C = 0?
Yes
Acknowledgeable
interrupt or macro
service request?
No
END
Yes
Note +1 if the operand specifies "+",
and –1 if it specifies "–"
Adjust PC
value to enable
instruction restart
To interrupt or macro
service processing
User’s Manual U10905EJ8V1UM
473
CHAPTER 7 DESCRIPTION OF INSTRUCTIONS
7
0
C byte
WHL
End of execution
Yes
≥?
No
Yes
Yes
≥?
No
Yes
TDE
≥?
No
End of execution
[Coding example]
MOV C, #4H
MOVG TDE, #05503H
MOVG WHL, #0FFC03H
CMPBKNC [TDE – ], [WHL – ]
BC $LITTLE
;Compares the 4-byte data from address 05500H with the data from address
0FFC00H, and branches to address LITTLE if the data from address 05500H is
smaller
474
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CHAPTER 8 DEVELOPMENT TOOLS
Tools required for 78K/IV Series product development are shown in this chapter.
For details, refer to the User’s Manual — Hardware of each device and the Single-Chip Microcontroller
Development Tools Selection Guide (U11069E).
User’s Manual U10905EJ8V1UM
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CHAPTER 8 DEVELOPMENT TOOLS
8.1 Development Tools
The following development tools are provided to develop programs for application systems
Table 8-1. Types and Functions of Development Tools (1/2)
Development tools
Functions
Hardware
In-circuit emulator
(IE-784000-R)
(IE-78K4-NS)
This is a hardware tool used for program debugging for system development
of 78K/IV Series.
TM
When a personal computer (PC-9800 Series or IBM PC/(IE-78K4-NS) AT
is used as a host machine of this emulator, it is possible to perform more
efficient debugging by means of functions such as the symbolic debugging
and the object file and symbol file transfer.
)
An on-chip serial interface RS-232-C enables connection to a PROM
programmer (PG-1500).
Emulation board
(IE-78×××-R-EM)
(IE-78×××-R-EM-A)
(IE-78××××-R-EM)
This is a board to emulate peripheral hardware that is specific to the target
device.
I/O emulation board
(IE-78×××-R-EM1)
(IE-78××××-R-EM1)
(IE-78××××-NS-EM1)
This is a board to emulate peripheral hardware that is specific to the target
device. It is used in combination with an emulation board. The I/O emulation
board required for the target device depends on the products.
Emulation probe
(EP-78×××......)
(NP-×××......)
This probe connects the in-circuit emulator to the target device. It is provided
each target device package.
Conversion socket
This is a socket used to connect the emulation probe for QFP to the
application system. It is a standard accessory for an emulation probe for
QPF. Mount it on the circuit board for an application system.
(EV-9200××-××)
Programmer adapter
This is an adapter for the PROM programmer (PG-1500) that is used for
programming on-chip PROM products.
(PA-78P×××......)
Jig (EV-9900)
Jig for removing WQFP-package product from the EV-9200××-××.
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CHAPTER 8 DEVELOPMENT TOOLS
Table 8-1. Types and Functions of Development Tools (2/2)
Development tools
Functions
Software
Integrated debugger
(ID78K4)
This is a control program for in-circuit emulators for the 78K/IV Series. This
debugger is used in combination with the device files. This debugger
enables more effective debugging than previous IE controllers by offering the
following features: source program level debugging written in C language,
structured assembly language, or assembly language and display for a
variety of simultaneous a variety of information by dividing the screen of the
host machine.
Device file
Used in combination with an integrated debugger. This file is required when
debugging the 78K/IV Series.
In-circuit emulator control
program (IE controller)
This is software to perform efficient debugging by connecting the IE to the
host machine.
This software makes full use of the capabilities of the IE by means of file
(object or symbol) transfer, on-line assembly, disassembly, break condition
(event) setup, etc.
Note 1
Relocatable assembler
This is a program to convert a program written in mnemonic to an object
code that can be executed by microcontrollers.
In addition, an automatic function to perform a symbol table creation and
branch instruction optimization processing is provided.
Structured assembler
preprocessor
This software introduces a structured programming method into the
assembler.
It enables writing functions with a C language-like control structure without
sacrificing the size and speed of the assembler.
Note 1
C compiler
This is a program that translates a program written in the high-level C
language into object code, which can be executed by a microcontroller.
C library source
This source program is attached to the C compiler. This program is required
when modifying a library (To better match user specifications).
System simulator
This is a software development support tool. C source level or assembler
level debugging is possible while simulating the operation of the target
system in the host machine. The SM78K4 enables the verification of the
logic and performance of applications independently from the hardware
development. Consequently, development efficiency and software quality
can be improved.
Note 2
(SM78K4)
Notes 1. Used in combination with the device files for 78K/IV Series.
2. Used in combination with the device files.
Remark All the software listed above runs under MS-DOSTM and PC DOSTM
.
User’s Manual U10905EJ8V1UM
477
CHAPTER 8 DEVELOPMENT TOOLS
Figure 8-1. Development Tools Structure
(On-chip PROM)
In-circuit emulator
IE-784000-R
Emulation probe
IE-78K4-NS
Host machine
PC-9800 Series
or IBM PC/AT
EP-78×××..........
NP-×××..........
Note 1
Real-time OS
Break
board
Emulation
board
Target
system
Note 2
PROM programmer
PG-1500
On-chip PROM product
PD78P×××
Relocatable assembler,
Structured assembler,
C compiler
PA-78P×××..........
µ
Programmer adapter
(On-chip Flash Memory)
In-circuit emulator
Emulation probe
IE-784000-R
IE-78K4-NS
Host machine
PC-9800 Series
EP-78×××..........
NP-×××..........
Note 1
Real-time OS
or IBM PC/AT
Emulation board
Target
system
Note 2
Flash memory writing tool
Flashpro III (FL-PR3)
On-chip flash memory product
Relocatable assembler,
Structured assembler,
C compiler
FA-×××
PD78F×××
µ
Notes 1. Integrated debugger and device file
2. Conversion socket to connect emulation probe to the target system (Products whose prefix is EV-9200)
Remark The meaning of part number prefix are as follows.
IE
: In-circuit emulator
EP
NP
PA
FA
: Emulation probe
: Emulation probe (Made by Naito Densei Machida Mfg. Co., Ltd.)
: PROM programmer adapter
: Adapter for flash memory writing
×××...... : Varies depending on the target device or package.
478
User’s Manual U10905EJ8V1UM
CHAPTER 8 DEVELOPMENT TOOLS
8.2 PROM Programming Tools
(1) Hardware
PG-1500
PROM programmer which allows programming, in standalone mode or via operation from a host
machine, of a single-chip microcontroller with on-chip PROM by connection of the board provided
and a separately available PROM programmer adapter. It can also program typical 256 Kb to
4 Mb PROM.
PROM programmer adapter Adapter which provided for each product with on-chip PROM. This adapter is used in combination
with PROM programmer. For actual product names, refer to the User’s Manual — Hardware for
the relevant device.
(2) Software
PG-1500 controller
Controls the PG-1500 on the host machine by connecting PG-1500 to the host machine with
parallel and serial interface.
8.3 Flash Memory Programming Tools
Flashpro III (FL-PR3)
This is flash programmer for a microcontroller in the flash memory.
Adapter for flash memory This must be wired to match the objective product.
programming
For details about part names, refer to the hardware version of the user’s manual for each device.
Remark This is a product of Naito Densei Machida Mfg. Co., Ltd. Consult with an NEC representative before
buying this part.
User’s Manual U10905EJ8V1UM
479
CHAPTER 9 EMBEDDED SOFTWARE
9.1 Real-time OS
Note
RX78K/IV
The aim of the RX78K/IV is to realize multi-task environments for real-time required control fields.
The CPU idle time can be allotted to other processes to improve the overall performance of the
system. The RX78K/IV provides system calls (31 kinds) conforming to the µITRON specification,
and the tools (configurator) for creating the RX78K/IV nucleus and several information tables.
The RX78K/IV should be used in combination with separately available assembler package
(RA78K4) and device files.
Real-time OS
<Precaution when used under PC environment>
Real-time OS is a DOS-based application. When using this application on Windows, use the
DOS prompt.
MX78K4
OS
µITRON specification subset OS. Nucleus of MX78K4 is attached. Task, event, and time
management are performed. Task execution sequence is controlled in task management and with
subsequent switch to the next execution task.
<Precaution when used under PC environment>
MX78K4 is a DOS-based application. When using this application on Windows, use the DOS
prompt.
Note When purchasing the RX78K/IV, the purchasing application must be filled in advance and a using conditions
agreement signed.
480
User’s Manual U10905EJ8V1UM
APPENDIX A INDEX OF INSTRUCTIONS (MNEMONICS: BY FUNCTION)
[Multiplication/Division Instructions]
[8-Bit Data Transfer Instruction]
MULU ................................................................. 329
MULUW.............................................................. 330
MULW ................................................................ 331
DIVUW ............................................................... 332
DIVUX ................................................................ 333
MOV ................................................................... 297
[16-Bit Data Transfer Instruction]
MOVW................................................................ 300
[24-Bit Data Transfer Instruction]
[Special Operation Instructions]
MACW ................................................................ 335
MACSW ............................................................. 338
SACW ................................................................ 341
MOVG ................................................................ 303
[8-Bit Data Exchange Instruction]
[Increment/Decrement Instructions]
XCH.................................................................... 305
[16-Bit Data Exchange Instruction]
INC ..................................................................... 345
DEC.................................................................... 346
INCW.................................................................. 347
DECW ................................................................ 348
INCG .................................................................. 349
DECG ................................................................. 350
XCHW ................................................................ 307
[8-Bit Operation Instructions]
ADD.................................................................... 309
ADDC ................................................................. 310
SUB .................................................................... 311
SUBC ................................................................. 312
CMP ................................................................... 313
AND.................................................................... 315
OR ...................................................................... 316
XOR ................................................................... 317
[Adjustment Instructions]
ADJBA................................................................ 352
ADJBS................................................................ 353
CVTBW .............................................................. 354
[Shift/Rotate Instructions]
ROR ................................................................... 356
ROL .................................................................... 357
RORC................................................................. 358
ROLC ................................................................. 359
SHR.................................................................... 360
SHL .................................................................... 361
SHRW ................................................................ 362
SHLW ................................................................. 363
ROR4 ................................................................. 364
ROL4 .................................................................. 365
[16-Bit Operation Instructions]
ADDW ................................................................ 319
SUBW ................................................................ 321
CMPW ................................................................ 323
[24-Bit Operation Instructions]
ADDG ................................................................. 326
SUBG ................................................................. 327
User’s Manual U10905EJ8V1UM
481
APPENDIX A INDEX OF INSTRUCTIONS (MNEMONICS: BY FUNCTION)
[Bit Manipulation Instructions]
[Conditional Branch Instructions]
MOV1 ................................................................. 367
AND1.................................................................. 369
OR1 .................................................................... 371
XOR1 ................................................................. 373
NOT1.................................................................. 374
SET1 .................................................................. 375
CLR1 .................................................................. 376
BNZ .................................................................... 406
BNE .................................................................... 406
BZ....................................................................... 407
BE ...................................................................... 407
BNC.................................................................... 408
BNL .................................................................... 408
BC ...................................................................... 409
BL ....................................................................... 409
BNV .................................................................... 410
BPO.................................................................... 410
BV ...................................................................... 411
BPE .................................................................... 411
BP ...................................................................... 412
BN ...................................................................... 413
BLT..................................................................... 414
BGE.................................................................... 415
BLE .................................................................... 416
BGT .................................................................... 417
BNH.................................................................... 418
BH ...................................................................... 419
BF....................................................................... 420
BT....................................................................... 421
BTCLR ............................................................... 422
BFSET................................................................ 423
DBNZ ................................................................. 424
[Stack Manipulation Instructions]
PUSH ................................................................. 378
PUSHU............................................................... 380
POP.................................................................... 381
POPU ................................................................. 383
MOVG ................................................................ 384
ADDWG ............................................................. 385
SUBWG.............................................................. 386
INCG SP ............................................................ 387
DECG SP........................................................... 388
[Call/Return Instructions]
CALL .................................................................. 390
CALLF ................................................................ 391
CALLT ................................................................ 392
BRK .................................................................... 393
BRKCS ............................................................... 394
RET .................................................................... 396
RETI ................................................................... 397
RETB.................................................................. 398
RETCS ............................................................... 399
RETCSB ............................................................ 401
[CPU Control Instructions]
MOV STBC, #byte............................................. 426
MOV WDM, #byte ............................................. 427
LOCATION......................................................... 428
SEL RBn ............................................................ 429
SEL RBn, ALT ................................................... 430
SWRS ................................................................ 431
NOP ................................................................... 432
EI ........................................................................ 433
DI........................................................................ 434
[Unconditional Branch Instruction]
BR ...................................................................... 404
[Special Instructions]
CHKL.................................................................. 436
CHKLA ............................................................... 437
482
User’s Manual U10905EJ8V1UM
APPENDIX A INDEX OF INSTRUCTIONS (MNEMONICS: BY FUNCTION)
[String Instructions]
MOVTBLW ......................................................... 439
MOVM ................................................................ 441
XCHM................................................................. 443
MOVBK .............................................................. 445
XCHBK ............................................................... 448
CMPME .............................................................. 451
CMPMNE ........................................................... 454
CMPMC.............................................................. 457
CMPMNC ........................................................... 460
CMPBKE ............................................................ 463
CMPBKNE ......................................................... 466
CMPBKC............................................................ 469
CMPBKNC ......................................................... 472
User’s Manual U10905EJ8V1UM
483
APPENDIX B INDEX OF INSTRUCTIONS (MNEMONICS: ALPHABETICAL ORDER)
[A]
[C]
ADD ................................................................... 309
ADDC ................................................................ 310
ADDG ................................................................ 326
ADDW ............................................................... 319
ADDWG ............................................................ 385
ADJBA............................................................... 352
ADJBS............................................................... 353
AND ................................................................... 315
AND1................................................................. 369
CALL ................................................................. 390
CALLF ............................................................... 391
CALLT ............................................................... 392
CHKL................................................................. 436
CHKLA .............................................................. 437
CLR1 ................................................................. 376
CMP .................................................................. 313
CMPBKC ........................................................... 469
CMPBKE ........................................................... 463
CMPBKNC ........................................................ 472
CMPBKNE ........................................................ 465
CMPMC............................................................. 457
CMPME ............................................................. 451
CMPMNC .......................................................... 460
CMPMNE .......................................................... 454
CMPW ............................................................... 323
CVTBW ............................................................. 354
[B]
BC ..................................................................... 409
BE...................................................................... 407
BF ...................................................................... 420
BFSET............................................................... 423
BGE ................................................................... 415
BGT ................................................................... 417
BH ..................................................................... 419
BL ...................................................................... 409
BLE.................................................................... 416
BLT .................................................................... 414
BN ..................................................................... 413
BNC ................................................................... 408
BNE ................................................................... 406
BNH ................................................................... 418
BNL ................................................................... 408
BNV ................................................................... 410
BNZ ................................................................... 406
BP...................................................................... 412
BPE ................................................................... 411
BPO ................................................................... 410
BR ..................................................................... 404
BRK ................................................................... 393
BRKCS .............................................................. 394
BT ...................................................................... 421
BTCLR .............................................................. 422
BV...................................................................... 421
BZ ...................................................................... 407
[D]
DBNZ................................................................. 424
DEC ................................................................... 346
DECG ................................................................ 350
DECG SP .......................................................... 388
DECW ............................................................... 348
DI ....................................................................... 434
DIVUW .............................................................. 332
DIVUX ............................................................... 333
[E]
[I]
EI ....................................................................... 433
INC .................................................................... 345
INCG ................................................................. 349
INCG SP ........................................................... 387
INCW................................................................. 347
484
User’s Manual U10905EJ8V1UM
APPENDIX B INDEX OF INSTRUCTIONS (MNEMONICS: ALPHABETICAL ORDER)
[L]
[R]
LOCATION........................................................ 428
ROL ................................................................... 357
ROLC ................................................................ 359
ROL4 ................................................................. 365
ROR .................................................................. 356
RORC................................................................ 358
ROR4 ................................................................ 364
RET ................................................................... 396
RETB................................................................. 398
RETCS .............................................................. 399
RETCSB............................................................ 401
RETI .................................................................. 397
[M]
MACSW ............................................................ 338
MACW ............................................................... 335
MOV .................................................................. 297
MOVBK ............................................................. 445
MOVG ....................................................... 303, 384
MOVM ............................................................... 300
MOV STBC, #byte ............................................ 426
MOVTBLW ........................................................ 439
MOVW............................................................... 441
MOV WDM, #byte ............................................ 427
MOV1 ................................................................ 367
MULU ................................................................ 329
MULUW............................................................. 330
MULW ............................................................... 331
[S]
SACW ............................................................... 341
SEL RBn ........................................................... 429
SEL RBn, ALT .................................................. 330
SET1 ................................................................. 375
SHL ................................................................... 361
SHLW ................................................................ 363
SHR ................................................................... 360
SHRW ............................................................... 362
SUB ................................................................... 311
SUBC ................................................................ 312
SUBG ................................................................ 327
SUBW ............................................................... 321
SUBWG............................................................. 386
SWRS ............................................................... 431
[N]
[O]
[P]
NOP................................................................... 332
NOT1................................................................. 374
OR ..................................................................... 316
OR1 ................................................................... 371
[X]
POP ................................................................... 381
POPU ................................................................ 383
PUSH ................................................................ 378
PUSHU.............................................................. 380
XCH ................................................................... 305
XCHBK .............................................................. 448
XCHM................................................................ 443
XCHW ............................................................... 307
XOR................................................................... 317
XOR1 ................................................................ 373
User’s Manual U10905EJ8V1UM
485
APPENDIX C REVISION HISTORY
Revisions through this document are listed in the following table. The column "Applicable Chapters" indicates
the chapters in each edition.
(1/3)
Edition
Major Revisions from Previous Edition
Applicable Chapters
2nd edition
• The following instructions are added to bit manipulation instructions.
CHAPTER 6
MOV1
CY, !addr16.bit
CY, !!addr24, bit
!addr16.bit, CY
!!addr24.bit, CY
INSTRUCTION SET
AND1, OR1
CY, !addr16.bit
CY, !!addr24.bit
CY,/!addr16.bit
CY,/!!addr24.bit
CY, !addr16.bit
CY,!!addr24.bit
XOR1
NOT1, SET1, CLR1
!addr16.bit
!!addr24.bit
• The following instructions are added to conditional branch instructions.
BF, BT, BFSET, BTCLR
!addr16.bit, $addr20
!!addr24.bit, $addr20
3rd edition
• Descriptions regarding µPD784915 Subseries are added.
Throughout
•
µPD784020 is added to µPD784026 Subseries.
Notation used in section 5.2.10 Short direct 24-bit memory indirect
addressing changed as follows: [%saddrp] → [%saddrg]
CHAPTER 5 ADDRESSING
• saddrg1 and saddrg2 are added to section 6.1 Legend, (1) Operand
Identifiers and Description (2/2).
CHAPTER 6
INSTRUCTION SET
• MOVG operand corrected as follows:
[TDE+HL], WHL → [TDE+C], WHL
• Section 6.5 Number of Instruction Clocks is added
• 3.5-inch 2HC or 3.5-inch 2HD is added as supply medium for IBM PC/AT
• Part numbers for ordering integrated debuggers are changed as follows:
µS5A10ID78K4 → µSAA10ID78K4
CHAPTER 8
DEVELOPMENT TOOLS
µS5A13ID78K4 → µSAA13ID78K4
µS7B10ID78K4 → µSBB10ID78K4
486
User’s Manual U10905EJ8V1UM
APPENDIX C REVISION HISTORY
(2/3)
Edition
Major Revisions from Previous Edition
Applicable Chapters
4th edition
• GK Package (80-pin plastic TQFP, fine pitch, 12 mm × 12 mm) is added
to µPD784021.
Throughout
• Descriptions regarding µPD784038/784038Y Subseries are added.
• Descriptions regarding µPD784046 Subseries are added.
• Descriptions regarding µPD784208/784208Y Subseries are added.
• A “Note” mark is appended to the RETCS instruction, which indicates that
the µPD784208 and 784208Y Subseries do not have the RETCS instruction.
• Descriptions regarding flash memory are added.
CHAPTER 8
DEVELOPMENT TOOLS
• Descriptions regarding the MX78K4 are added.
CHAPTER 9
SOFTWARE FOR
EMBEDDING
5th edition
• New products (µPD784031/Y) and new package (80-pin plastic QFP
(14 mm square, 1.4 mm thick)) have been added to the µPD784038/Y
Subseries.
Throughout
• Entries related to the new product (µPD784054) of the µPD784046
Subseries have been added.
• Entries related to the µPD784208 Subseries have been deleted.
• Entries related to the µPD784216/Y Subseries have been added.
• Entries related to the new products (µPD784915A, 784916A) of the
µPD784915 Subseries have been added.
• Entries related to the µPD784908 Subseries have been added.
• Entries related to the µPD78F4943 Subseries have been added.
• Note that there is no RETCS instruction in the µPD764208 and
µPD784208Y Subseries has been deleted.
CHAPTER 6
INSTRUCTION SET
• The entry, ‘Highest-order/On Highest-order side’ for RETI instructions
has been changed to ‘Highest Priority.’
CHAPTER 7
DESCRIPTION OF
INSTRUCTIONS
• Note that there is no RETCS instruction in the µPD764208 and
µPD784208Y Subseries has been deleted, ‘target’ has been added
to the instruction format, and the entry, ‘Highest-order/On Highest-order
side’ has been changed to ‘Highest Priority.’
• ‘target’ has been added to the instruction format for RETCSB instructions.
• Entries related to flash memory have been corrected.
CHAPTER 8
DEVELOPMENT TOOLS
6th edition
• Adds the µPD784218, 784218Y, 784225, 784225Y, 784928, and
784928Y Subseries and µPD784943.
Throughout
• The following products are in the development to completion stage:
µPD784037, 784038, 78P4038
µPD784031Y, 784035Y, 784036Y, 784037Y, 784038Y, 78P4038Y
µPD784215, 784216
µPD784215Y, 784216Y
µPD784915A, 784916A
• Changes the GC-7EA package to the GC-8EU package in the µPD784214,
784215, 784216, 784214Y, 784215Y, and 784216Y.
• Describes that the µPD784915 Subseries provide the fixed LOCATION 0
instruction instead of the LOCATION 0FH instruction.
• Adds Note describing that the special instructions (CHKL and CHKLA) are
not available for the µPD784216, 784216Y, 784218, 784218Y, 784225,
and 784215Y,
• Changes the µPD78F4943 Subseries to the µPD784943 Subseries.
User’s Manual U10905EJ8V1UM
487
APPENDIX C REVISION HISTORY
(3/3)
Edition
Major Revisions from Previous Edition
Applicable Chapters
7th edition
• Addition of µPD784937 and 784955 Subseries. Deletion of µPD784943.
• The following products changed from under development stage to
completed.
Throughout
µPD784031(A), 784035(A), 784036(A),
µPD784044(A), 784044(A1), 784044(A2), 784046(A), 784046(A1),
784046(A2),
µPD784054(A), 784054(A1), 784054(A2), µPD784214, 784214Y,
µPD784915B, 784916B,
µPD784927, 78F4928, 784927Y, 78F4928Y
• Modification of GC-7EA package to GC-8EU package for the µPD78F4216,
78F4216Y
• Modification of power supply voltage in the µPD784908 Subseries.
Mask ROM version (µPD784907, 784908) ... changed from (VDD = 4.5 to
5.5 V) to (VDD = 3.5 to 5.5 V)
PROM version (µPD78P4908) ... changed from (VDD = 4.5 to 5.5 V) to
(VDD = 4.0 to 5.5 V)
Modification of the Notes in the special instructions (CHKL, CHKLA).
CHAPTER 6
INSTRUCTION SET
Modification of the operation sequence of the POP instruction.
Addition of the Note in CHKL instruction.
CHAPTER 7
DESCRIPTION OF
INSTRUCTIONS
Addition of Note in CHKLA instruction.
Modification of the format.
CHAPTER 8
DEVELOPMENT TOOLS
Addition of the description on the PC environment.
CHAPTER 9 EMBEDDED
SOFTWARE
8th edition
• Addition of µPD784216A, 784216AY, 784218A, 784218AY, 784938A,
784956A, 784976A Subseries. Deletion of µPD784216, 784216Y, 784218,
784218Y, 784937, 784955 Subseries.
Throughout
Addition of µPD784928, 784928Y. Deletion of µPD784915, 784915A,
784916A
• The status of following products changed from under development to
completed:
µPD784224, 784225, 78F4225, 784224Y, 784225Y, 78F4225Y, µPD784907
784908, 78P4908
488
User’s Manual U10905EJ8V1UM
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