UPD784054GC(A)-XXX3B9 [NEC]
Microcontroller, 16-Bit, MROM, 12.5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80;
| 型号： | UPD784054GC(A)-XXX3B9 |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 16-Bit, MROM, 12.5MHz, CMOS, PQFP80, 14 X 14 MM, PLASTIC, QFP-80 微控制器 |
| 文件： | 总472页 (文件大小：3178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
µPD784054
16-Bit Single-Chip Microcontrollers
Hardware
µPD784054
µPD784054(A)
µPD784054(A1)
µPD784054(A2)
Document No. U11719EJ3V1UD00 (3rd edition)
Date Published August 2005 N CP(K)
c
Printed in Japan
[MEMO]
User’s Manual U11719EJ3V1UD
2
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
User’s Manual U11719EJ3V1UD
FIP and IEBus are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft
Corporation in the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
Ethernet is a trademark of Zerox Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U11719EJ3V1UD
4
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
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each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
5
User’s Manual U11719EJ3V1UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
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Santa Clara, California
Tel: 408-588-6000
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Tel: 0211-65030
800-366-9782
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J05.6
User’s Manual U11719EJ3V1UD
6
Major Revisions in This Edition
Contents
Page
U11719EJ2V0UD00 → U11719EJ3V0UD00
CHAPTER 1 GENERAL
• Completion of development of the following product
µPD78F4046
p. 29
p. 47
• Update of 78K/IV Series Product Lineup
CHAPTER 2 PIN FUNCTIONS
Addition of description on BWD pin in Table 2-4 I/O Circuit Type of Each Pin and Recommended Processing
of Unused Pins
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
p. 268
Addition of cautions on start bit during UART transmission to 12.5 Cautions
CHAPTER 16 STANDBY FUNCTION
p. 365
p. 378
• Modification of Figure 16-1 Diagram of Standby Mode Transition
• Modification of description in 16.6 (5) A/D converter
CHAPTER 18 µPD78F4046
p. 385
p. 387
• Addition of description on Flashpro III
• Addition of cautions in 18.3 Cautions
p. 423
p. 429
p. 435
p. 441
p. 447
p. 452
p. 453
Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS (µPD784054)
Addition of CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
Addition of CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
Addition of CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
Addition of CHAPTER 24 TIMING CHARTS
Addition of CHAPTER 25 PACKAGE DRAWING
Addition of CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT TOOLS
p. 455
• Addition of description on host machines and OSs
pp. 458, 459
p. 459
• Addition of SP78K4 to A.1 Language Processing Software, modification of description in Remark
• Addition of description on Flashpro III in Remark in A.2 Flash Memory Writing Tools
• Addition and modification of description in A.3.1 Hardware
• Modification of description in Remark in A.3.2 Software
pp. 460, 461
p. 462
p. 463
• Addition of A.4 Cautions on Designing Target System
p. 467
Modification of description in APPENDIX B EMBEDDED SOFTWARE
U11719EJ3V0UD00 → U11719EJ3V1UD00
p. 30
p. 30
p. 453
Modification of 1.2 Ordering Information
Modification of 1.3 Quality Grades
Addition of Table 26-1. Surface Mounting Type Soldering Conditions (2)
The mark shows major revised points.
7
User’s Manual U11719EJ3V1UD
INTRODUCTION
Intended Reader
This manual is intended for user engineers who understand the functions of the µPD784054 and wish to design application
systems using this subseries.
The relevant products are as follows:
• Standard products: µPD784054
• Special products : µPD784054(A), (A1), (A2)
Purpose
The purpose of this manual is to give users an understanding of the various hardware functions of the µPD784054.
Organization
The µPD784054 manual is divided into two volumes – the hardware volume (this manual) and the instruction volume.
Hardware volume
Instruction volume
Pin functions
CPU functions
Internal block functions
Interrupts
Addressing
Instruction set
Other on-chip peripheral functions
Electrical specifications
Certain operating precautions apply to these products.
These precautions are stated at the relevant points in the text of each chapter, and are
also summarized at the end of each chapter. Be sure to read them.
How to Read This Manual
Readers are required a general knowledge of electrical and logic circuits and microcomputers.
♦ To readers using this manual as a µPD784054(A), 784054(A1), 784054(A2) manual:
→
The µPD784054 is treated as the representative model. Therefore, when using this manual for the µPD784054(A),
784054(A1), 784054(A2) manual, µPD784054 should be read as each product name as appropriate. For the
differences between products, refer to 1.8 Differences between µPD784054 and µPD784046 Subseries, 1.9
DifferencesbetweenµPD784054andµPD784054(A),and1.10DifferencesbetweenµPD784054(A),784054(A1),
and 784054(A2).
The application examples presented in this manual are for the “standard” quality
models in general-purpose electronic systems. If you wish to use the applications
presentedinthismanualforelectronicsystemsthatrequire“special”qualitymodels,
thoroughly study the parts and circuits to be actually used, and their quality grade.
♦ To check the details of a register when the register name is known:
Use APPENDIX C REGISTER INDEX.
→
User’s Manual U11719EJ3V1UD
8
♦ If the device operates strangely after debugging:
Cautions are summarized at the end of each chapter, so refer to the Cautions for the relevant function.
→
♦ For a general understanding of the functions
Read in accordance with the CONTENTS.
→
♦ For the details of the instruction functions:
Refer to the separate 78K/IV Series User’s Manual - Instruction (U10905E).
→
♦ To find out about electrical specifications
Refer to the each chapter of electrical specifications.
→
♦ To find out about application examples of each function,
Refer to the Application Note separately available.
→
Legend
Significance in data notation : High-order digit on left, low-order digit on right
Active-low notation
Note
: × × × (Line above pin or signal name)
: Explanation of item marked with Note in the text
: Item to be especially noted
Caution
Remark
: Supplementary information
Numeric notations
: Binary ................. × × × × B or × × × ×
Decimal .............. × × × ×
Hexadecimal....... × × × × H
Register Notation
7
6
1
5
0
4
3
2
1
0
0
Where the bit number is marked with a circle, the
bit name is reserved for NEC Electronics
assembler and is defined as a sfr variable by the
#pragma sfr directive for C compiler.
EDC
B
×
A
1
×
Write Operation
Read Operation
0 or 1 is read.
0 or 1 is written. The
operation is not affected
by either value.
0 is read.
1 is read.
0 must be written
1 must be written
A value is written
according to the
function to be used.
A value is read
according to the
operating status.
Code combinations marked “Setting prohibited” in the register notations in the text must not be written.
Easily confused characters : 0 (Zero), O (Letter O)
: 1 (One), l (Lower-case letter L), I (Upper-case letter I)
9
User’s Manual U11719EJ3V1UD
Related Documents Therelateddocumentsinthispublicationmayincludepreliminaryversions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
µPD784054 Subseries User’s Manual - Hardware
Document No.
This manual
U10095E
78K/IV Series Application Note - Software Fundamentals
78K/IV Series User's Manual - Instructions
U10905E
Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
U15254E
U15255E
U11743E
U15557E
U15556E
U15373E
U15802E
U15185E
U10603E
U10604E
U14610E
RA78K4 Assembler Package
Operation
Language
Structured Assembler Preprocessor
Operation
CC78K4 C Compiler
Language
SM78K Series Ver. 2.30 or Later System Simulator
Operation (WindowsTM Based)
External Part User Open Interface Specification
Operation (Windows Based)
Fundamentals
ID78K Series Integrated Debugger Ver. 2.30 or Later
RX78K4 Real-time OS
Installation
Project Manager Ver 3.12 or Later (Windows Based)
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
IE-78K4-NS In-Circuit Emulator
Document No.
U13356E
IE-784046-NS-EM1 Emulation Board
IE-784000-R In-Circuit Emulator
U13744E
U12903E
IE-784046-R-EM1 Emulation Board
U11677E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U11719EJ3V1UD
10
Documents Related to Flash Memory Writing (User’s Manuals)
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User’s Manual
Other Related Documents
Document Name
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Document No.
X13769X
Note
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note
See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
11
User’s Manual U11719EJ3V1UD
CONTENTS
CHAPTER 1 GENERAL ............................................................................................................................... 28
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Features ...................................................................................................................................... 30
Ordering Information................................................................................................................. 30
Quality Grades ........................................................................................................................... 30
Pin Configuration (Top View) ................................................................................................... 31
System Configuration Example (PPC) .................................................................................... 33
Block Diagram ............................................................................................................................ 34
List of Functions........................................................................................................................ 35
Differences between µPD784054 and µPD784046 Subseries .............................................. 36
Differences between µPD784054 and µPD784054(A)............................................................ 37
1.10 Differences between µPD784054(A), 784054(A1), and 784054(A2) ..................................... 37
CHAPTER 2 PIN FUNCTIONS ..................................................................................................................... 38
2.1
2.2
2.3
List of Pin Functions ................................................................................................................. 38
Description of Pin Functions ................................................................................................... 41
I/O Circuits of Pins and Processing of Unused Pins ........................................................... 47
CHAPTER 3 CPU ARCHITECTURE .......................................................................................................... 49
3.1
3.2
3.3
Memory Space............................................................................................................................ 49
Internal ROM Area ..................................................................................................................... 51
Base Area.................................................................................................................................... 51
3.3.1
3.3.2
3.3.3
Vector table area ............................................................................................................................ 52
CALLT instruction table area ......................................................................................................... 53
CALLF instruction entry area......................................................................................................... 53
3.4
Internal Data Area.................................................................................................................... 54
3.4.1
3.4.2
3.4.3
Internal RAM area .......................................................................................................................... 54
Special function register (SFR) area ............................................................................................. 57
External SFR area.......................................................................................................................... 57
3.5
3.6
External Memory Space ............................................................................................................ 57
Control Registers....................................................................................................................... 58
3.6.1
3.6.2
3.6.3
3.6.4
Program counter (PC) .................................................................................................................... 58
Program status word (PSW) .......................................................................................................... 58
Use of RSS bit................................................................................................................................ 61
Stack pointer (SP) .......................................................................................................................... 63
3.7
General-Purpose Registers ...................................................................................................... 67
3.7.1
3.7.2
Configuration .................................................................................................................................. 67
Functions ........................................................................................................................................ 69
3.8
3.9
Special Function Registers (SFRs) ......................................................................................... 72
Cautions ...................................................................................................................................... 77
CHAPTER 4 CLOCK GENERATOR .......................................................................................................... 78
4.1
4.2
Configuration and Function ..................................................................................................... 78
Control Registers....................................................................................................................... 80
User’s Manual U11719EJ3V1UD
12
4.2.1
4.2.2
Standby control register (STBC) ................................................................................................... 80
Oscillation stabilization time specification register (OSTS) ......................................................... 81
4.3
4.4
Clock Generator Operation ...................................................................................................... 82
4.3.1
4.3.2
Clock oscillator ............................................................................................................................... 82
Frequency divider........................................................................................................................... 82
Cautions ...................................................................................................................................... 83
4.4.1
4.4.2
When an external clock is input .................................................................................................... 83
When crystal/ceramic oscillation is used ...................................................................................... 84
CHAPTER 5 PORT FUNCTIONS.............................................................................................................. 87
5.1
5.2
Digital Input/Output Port........................................................................................................... 87
Port 0 ........................................................................................................................................... 89
5.2.1
5.2.2
5.2.3
5.2.4
Hardware configuration .................................................................................................................. 89
Input/output mode/control mode setting........................................................................................ 90
Operating status ............................................................................................................................. 90
Internal pull-up resistors ................................................................................................................ 92
5.3
5.4
Port 1 ........................................................................................................................................... 94
5.3.1
5.3.2
5.3.3
Hardware configuration .................................................................................................................. 94
Setting I/O mode/control mode...................................................................................................... 95
Operating status ............................................................................................................................. 95
Port 2 ........................................................................................................................................... 97
5.4.1
5.4.2
5.4.3
Hardware configuration .................................................................................................................. 98
Setting I/O mode/control mode...................................................................................................... 100
Operating status ............................................................................................................................. 101
5.5 Port 3 ............................................................................................................................................. 103
5.5.1
5.5.2
5.5.3
Hardware configuration .................................................................................................................. 104
Input/output mode/control mode setting........................................................................................ 105
Operating status ............................................................................................................................. 107
5.6
5.7
5.8
5.9
Port 4 .......................................................................................................................................... 109
5.6.1
5.6.2
5.6.3
5.6.4
Hardware configuration .................................................................................................................. 109
Input/output mode/control mode setting........................................................................................ 110
Operating status ............................................................................................................................. 111
Internal pull-up resistors ................................................................................................................ 113
Port 5 .......................................................................................................................................... 115
5.7.1
5.7.2
5.7.3
5.7.4
Hardware configuration .................................................................................................................. 115
Input/output mode/control mode setting........................................................................................ 116
Operating status ............................................................................................................................. 117
Internal pull-up resistors ................................................................................................................ 119
Port 6 .......................................................................................................................................... 121
5.8.1
5.8.2
5.8.3
5.8.4
Hardware configuration .................................................................................................................. 121
Setting of I/O mode/control mode ................................................................................................. 122
Operating status ............................................................................................................................. 123
Internal pull-up resistors ................................................................................................................ 125
Port 7 ........................................................................................................................................... 127
5.9.1
5.9.2
Hardware configuration .................................................................................................................. 127
Notes............................................................................................................................................... 127
5.10 Port 8 ........................................................................................................................................... 128
5.10.1 Hardware configuration .................................................................................................................. 128
User’s Manual U11719EJ3V1UD
13
5.10.2 Cautions.......................................................................................................................................... 128
5.11 Port 9............................................................................................................................................. 129
5.11.1 Hardware configuration .................................................................................................................. 130
5.11.2 Setting of I/O mode/control mode ................................................................................................. 132
5.11.3 Operating status ............................................................................................................................. 133
5.11.4 Internal pull-up resistor .................................................................................................................. 135
5.12 Port Output Data Check Function ........................................................................................... 137
5.13 Cautions ...................................................................................................................................... 140
CHAPTER 6 OUTLINE OF TIMER............................................................................................................. 142
CHAPTER 7 TIMER 0 ................................................................................................................................... 144
7.1
7.2
7.3
7.4
Function ...................................................................................................................................... 144
Configuration.............................................................................................................................. 145
Timer 0 Control Register .......................................................................................................... 148
Operation of Timer Register 0 (TM0) ...................................................................................... 150
7.4.1
7.4.2
Basic operation............................................................................................................................... 150
Clear operation ............................................................................................................................... 152
7.5
7.6
Operation of Capture/Compare Register................................................................................ 153
7.5.1
7.5.2
Compare operation ........................................................................................................................ 153
Capture operation .......................................................................................................................... 155
Basic Operation of Output Control Circuit ............................................................................ 157
7.6.1
7.6.2
7.6.3
Basic operation............................................................................................................................... 159
Toggle output .................................................................................................................................. 159
Set/reset output .............................................................................................................................. 160
7.7
7.8
Examples of Use ........................................................................................................................ 161
7.7.1
7.7.2
Operation as interval timer ............................................................................................................ 161
Pulse width measurement operation ............................................................................................. 164
Cautions ...................................................................................................................................... 167
CHAPTER 8 TIMER 1 ................................................................................................................................... 169
8.1
8.2
8.3
8.4
Function ...................................................................................................................................... 169
Configuration.............................................................................................................................. 169
Timer 1 Control Register .......................................................................................................... 172
Operation of Timer Register 1 (TM1) ...................................................................................... 174
8.4.1
8.4.2
Basic operation............................................................................................................................... 174
Clear operation ............................................................................................................................... 176
8.5
8.6
Operation of Compare Register............................................................................................... 178
Basic Operation of Output Control Circuit ............................................................................ 181
8.6.1
8.6.2
8.6.3
Basic operation............................................................................................................................... 182
Toggle output .................................................................................................................................. 182
Set/reset output .............................................................................................................................. 183
8.7
8.8
Examples of Use ........................................................................................................................ 184
8.7.1
8.7.2
Operation as interval timer (1)....................................................................................................... 184
Operation as interval timer (2)....................................................................................................... 187
Cautions ...................................................................................................................................... 189
User’s Manual U11719EJ3V1UD
14
CHAPTER 9 TIMER 4 ................................................................................................................................... 192
9.1
9.2
9.3
9.4
Function ...................................................................................................................................... 192
Configuration.............................................................................................................................. 192
Timer 4 Control Register .......................................................................................................... 195
Operation of Timer Register 4 (TM4) ...................................................................................... 196
9.4.1
9.4.2
Basic operation............................................................................................................................... 196
Clear operation ............................................................................................................................... 198
9.5
9.6
Operation of Compare Register............................................................................................... 200
Example of Use .......................................................................................................................... 202
9.6.1
9.6.2
Operation as interval timer (1)....................................................................................................... 202
Operation as interval timer (2)....................................................................................................... 205
9.7 Cautions ........................................................................................................................................ 207
CHAPTER 10 WATCHDOG TIMER FUNCTION.......................................................................................... 209
10.1 Configuration.............................................................................................................................. 209
10.2 Watchdog Timer Mode Register (WDM) ................................................................................. 210
10.3 Operation .................................................................................................................................... 212
10.3.1 Count operation .............................................................................................................................. 212
10.3.2 Interrupt priorities ........................................................................................................................... 212
10.4 Cautions ...................................................................................................................................... 213
10.4.1 General cautions on use of watchdog timer ................................................................................. 213
10.4.2 Cautions on µPD784054 watchdog timer ..................................................................................... 213
CHAPTER 11 A/D CONVERTER.................................................................................................................. 214
11.1 Configuration.............................................................................................................................. 214
11.2 A/D Converter Mode Register (ADM) ...................................................................................... 217
11.3 A/D Conversion Result Registers (ADCR0 to ADCR7) ......................................................... 220
11.4 Operation .................................................................................................................................... 222
11.4.1 Basic A/D converter operation ....................................................................................................... 222
11.4.2 Select mode.................................................................................................................................... 225
11.4.3 Scan mode ..................................................................................................................................... 227
11.4.4 A/D conversion operation start by software .................................................................................. 229
11.4.5 A/D conversion operation start by hardware ................................................................................ 231
11.5 External Circuit of A/D Converter............................................................................................ 234
11.6 Cautions ...................................................................................................................................... 234
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O ......................................... 236
12.1 Switching between Asynchronous Serial Interface Mode and 3-wire Serial I/O Mode ... 237
12.2 Asynchronous Serial Interface Mode ..................................................................................... 238
12.2.1 Configuration in asynchronous serial interface mode .................................................................. 238
12.2.2 Asynchronous serial interface control registers............................................................................ 240
12.2.3 Data format ..................................................................................................................................... 244
12.2.4 Parity types and operations ........................................................................................................... 245
12.2.5 Transmission .................................................................................................................................. 246
12.2.6 Reception........................................................................................................................................ 247
12.2.7 Receive errors ................................................................................................................................ 248
12.2.8 Transmitting/receiving data with macro service............................................................................ 249
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12.3 3-Wire Serial I/O Mode .............................................................................................................. 251
12.3.1 Configuration in 3-wire serial I/O mode ........................................................................................ 251
12.3.2 Clocked serial interface mode registers (CSIM1, CSIM2) ........................................................... 254
12.3.3 Basic operation timing ................................................................................................................... 255
12.3.4 Operation when transmission only is enabled .............................................................................. 257
12.3.5 Operation when reception only is enabled ................................................................................... 257
12.3.6 Operation when transmission/reception is enabled...................................................................... 258
12.3.7 Corrective action in case of slippage of serial clock and shift operations .................................. 258
12.4 Baud Rate Generator................................................................................................................. 259
12.4.1 Baud rate generator configuration................................................................................................. 259
12.4.2 Baud rate generator control register ............................................................................................... 261
12.4.3 Baud rate generator operation ........................................................................................................ 263
12.4.4 Baud rate setting in asynchronous serial interface mode.............................................................. 264
12.5 Cautions ...................................................................................................................................... 267
CHAPTER 13 EDGE DETECTION FUNCTION ........................................................................................... 273
13.1 Edge Detection Function Control Registers.......................................................................... 273
13.1.1 External interrupt mode registers (INTM0, INTM1) ...................................................................... 273
13.1.2 Interrupt valid edge flag registers (IEF1, IEF2) ............................................................................ 276
13.1.3 Noise protection control register (NPC) ........................................................................................ 277
13.2 Edge Detection for Pin P20 ...................................................................................................... 278
13.3 Pin Edge Detection for Pins P21 to P27................................................................................. 279
13.4 Cautions ...................................................................................................................................... 280
CHAPTER 14 INTERRUPT FUNCTIONS .................................................................................................... 281
14.1 Interrupt Request Sources ....................................................................................................... 281
14.1.1 Software interrupts ......................................................................................................................... 283
14.1.2 Operand error interrupts ................................................................................................................ 283
14.1.3 Non-maskable interrupts ................................................................................................................ 283
14.1.4 Maskable interrupts ........................................................................................................................ 283
14.2 Interrupt Processing Modes..................................................................................................... 284
14.2.1 Vectored interrupt processing........................................................................................................ 284
14.2.2 Macro service ................................................................................................................................. 284
14.2.3 Context switching ........................................................................................................................... 284
14.3 Interrupt Processing Control Registers ................................................................................. 285
14.3.1 Interrupt control registers............................................................................................................... 287
14.3.2 Interrupt mask registers (MK0, MK1) ............................................................................................ 291
14.3.3 In-service priority register (ISPR) .................................................................................................. 293
14.3.4 Interrupt mode control register (IMC) ............................................................................................ 294
14.3.5 Watchdog timer mode register (WDM).......................................................................................... 295
14.3.6 Program status word (PSW) .......................................................................................................... 296
14.4 Software Interrupt Acknowledgment Operations.................................................................. 297
14.4.1 BRK instruction software interrupt acknowledgment operation ................................................... 297
14.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation 297
14.5 Operand Error Interrupt Acknowledgment Operation .......................................................... 298
14.6 Non-Maskable Interrupt Acknowledgment Operation .......................................................... 299
14.7 Maskable Interrupt Acknowledgment Operation................................................................... 302
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14.7.1 Vectored interrupt ........................................................................................................................... 304
14.7.2 Context switching ........................................................................................................................... 304
14.7.3 Maskable interrupt priority levels................................................................................................... 306
14.8 Macro Service Function ............................................................................................................ 312
14.8.1 Outline of macro service function.................................................................................................. 312
14.8.2 Types of macro service .................................................................................................................. 312
14.8.3 Basic operation of macro service (except CPU monitor modes 0 and 1) ................................... 316
14.8.4 Operation on completion of macro servicing (except CPU monitor modes 0 and 1) ................. 317
14.8.5 Macro service control register ....................................................................................................... 318
14.8.6 Macro service mode....................................................................................................................... 320
14.8.7 Operation of macro service ........................................................................................................... 320
14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending.................... 332
14.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro
Service......................................................................................................................................... 334
14.11 Interrupt and Macro Service Operation Timing..................................................................... 334
14.11.1 Interrupt acceptance processing time ........................................................................................... 335
14.11.2 Processing time of macro service ................................................................................................. 336
14.12 Restoring Interrupt Function To Initial State ......................................................................... 337
14.13 Cautions ...................................................................................................................................... 338
CHAPTER 15 LOCAL BUS INTERFACE FUNCTION ................................................................................ 340
15.1 Memory Extension Function ..................................................................................................... 340
15.1.1 Memory extension mode register (MM) ........................................................................................ 340
15.1.2 Memory map with external memory extension ............................................................................. 342
15.1.3 Basic operation of local bus interface ........................................................................................... 344
15.2 Wait Function ............................................................................................................................. 347
15.2.1 Wait function control registers ....................................................................................................... 347
15.2.2 Address waits ................................................................................................................................. 351
15.2.3 Access waits................................................................................................................................... 354
15.3 Bus Sizing Function .................................................................................................................. 361
15.3.1 Bus width specification register (BW) ........................................................................................... 361
15.4 Cautions ...................................................................................................................................... 363
CHAPTER 16 STANDBY FUNCTION .......................................................................................................... 364
16.1 Configuration and Function ..................................................................................................... 364
16.2 Control Registers....................................................................................................................... 367
16.2.1 Standby control register (STBC) ................................................................................................... 367
16.2.2 Oscillation stabilization time specification register (OSTS) ......................................................... 368
16.3 HALT Mode ................................................................................................................................. 370
16.3.1 HALT mode setting and operating states...................................................................................... 370
16.3.2 HALT mode release ....................................................................................................................... 370
16.4 STOP Mode ................................................................................................................................. 373
16.4.1 STOP mode setting and operating states ..................................................................................... 373
16.4.2 STOP mode release....................................................................................................................... 374
16.5 IDLE Mode................................................................................................................................... 375
16.5.1 IDLE mode setting and operating states....................................................................................... 375
16.5.2 IDLE mode release ........................................................................................................................ 376
16.6 Check Items When STOP Mode/IDLE Mode Is Used ............................................................ 377
16.7 Cautions ...................................................................................................................................... 379
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CHAPTER 17 RESET FUNCTION ............................................................................................................... 380
17.1 Reset Function ........................................................................................................................... 380
17.2 Caution ........................................................................................................................................ 383
CHAPTER 18 µPD78F4046 .......................................................................................................................... 384
18.1 Memory Mapping of µPD78F4046 ............................................................................................ 384
18.2 Programming µPD78F4046 ....................................................................................................... 385
18.2.1 Selecting communication mode..................................................................................................... 386
18.2.2 Function of flash memory programming ....................................................................................... 386
18.2.3 Connecting Flashpro II/Flashpro III ............................................................................................... 387
18.3 Cautions ...................................................................................................................................... 387
CHAPTER 19 INSTRUCTION OPERATIONS.............................................................................................. 389
19.1 Legend......................................................................................................................................... 389
19.2 List of Operations ...................................................................................................................... 392
19.3 Instructions Listed by Type of Addressing............................................................................ 417
CHAPTER 20 ELECTRICAL SPECIFICATIONS (µPD784054)................................................................. 423
CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A)) ........................................................... 429
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))........................................................... 435
CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2)) ......................................................... 441
CHAPTER 24 TIMING CHARTS................................................................................................................... 447
CHAPTER 25 PACKAGE DRAWING ........................................................................................................... 452
CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS ................................................................... 453
CHAPTER 27 CAUTIONS ON USING DEVELOPMENT TOOLS .............................................................. 454
APPENDIX A DEVELOPMENT TOOLS...................................................................................................... 455
A.1 Language Processing Software............................................................................................... 458
A.2 Flash Memory Writing Tools .................................................................................................... 459
A.3 Debugging Tools ........................................................................................................................ 460
A.3.1
A.3.2
Hardware ........................................................................................................................................ 460
Software.......................................................................................................................................... 462
A.4 Cautions on Designing Target System ................................................................................... 463
A.5 Dimensions of Conversion Socket (EV-9200GC-80) and Recommended Board
Mounting Pattern ....................................................................................................................... 465
APPENDIX B EMBEDDED SOFTWARE ...................................................................................................... 467
APPENDIX C REGISTER INDEX ................................................................................................................. 468
APPENDIX D REVISION HISTORY ............................................................................................................. 471
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LIST OF FIGURES (1/6)
Figure No.
2-1
Title
Page
I/O Circuits of Pins ....................................................................................................................................... 48
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
Memory Map ................................................................................................................................................. 50
Internal RAM Memory Map .......................................................................................................................... 55
Format of Program Counter (PC) ................................................................................................................ 58
Format of Program Status Word (PSW) ...................................................................................................... 58
Format of Stack Pointer (SP) ....................................................................................................................... 63
Data Saved to Stack Area ............................................................................................................................ 64
Data Restored from Stack Area ................................................................................................................... 65
Format of General-Purpose Register .......................................................................................................... 67
General-Purpose Register Addresses ......................................................................................................... 68
4-1
4-2
4-3
4-4
4-5
4-6
4-7
Block Diagram of Clock Generator .............................................................................................................. 78
Clock Oscillator External Circuitry ............................................................................................................... 79
Standby Control Register (STBC) Format................................................................................................... 80
Format of Oscillation Stabilization Time Specification Register (OSTS) ................................................... 81
Signal Extraction with External Clock Input ................................................................................................ 83
Cautions on Resonator Connection............................................................................................................. 84
Incorrect Example of Resonator Connection .............................................................................................. 85
5-1
Port Configuration......................................................................................................................................... 87
Block Diagram of Port 0 ............................................................................................................................... 89
Format of Port 0 Mode Register (PM0) ....................................................................................................... 90
Port Specified as Output Port ...................................................................................................................... 90
Port Specified as Input Port ......................................................................................................................... 91
Pull-Up Resistor Option Register L (PUOL) Format ................................................................................... 92
Pull-Up Resistor Specification (Port 0) ........................................................................................................ 93
Block Diagram of Port 1 ............................................................................................................................... 94
Format of Port 1 Mode Register (PM1) ....................................................................................................... 95
Port Specified as Output Port ...................................................................................................................... 95
Port Specified as Input Port ......................................................................................................................... 96
Block Diagram of P20 (Port 2) ..................................................................................................................... 98
Block Diagram of P21 to P24 (Port 2) ......................................................................................................... 99
Block Diagram of P25 to P27 (Port 2) ......................................................................................................... 99
Format of Port 2 Mode Register (PM2) ....................................................................................................... 100
Format of Port 2 Mode Control Register (PMC2) ....................................................................................... 100
Port in Output Port Mode ............................................................................................................................. 101
Port in Input Port Mode ................................................................................................................................ 101
Port in Control Mode .................................................................................................................................... 102
Block Diagram of P30, P31, P33 and P36 (Port 3) .................................................................................... 104
Block Diagram of P32 and P35 (Port 3) ...................................................................................................... 104
Block Diagram of P34 and P37 (Port 3) ...................................................................................................... 105
Format of Port 3 Mode Register (PM3) ....................................................................................................... 105
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
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LIST OF FIGURES (2/6)
Figure No.
Title
Page
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
Format of Port 3 Mode Control Register (PMC3) ....................................................................................... 106
Port Specified as Output Port ...................................................................................................................... 107
Port Specified as Input Port ......................................................................................................................... 107
Control Specification .................................................................................................................................... 108
Block Diagram of Port 4 ............................................................................................................................... 109
Format of Port 4 Mode Register (PM4) ....................................................................................................... 110
Port Specified as Output Port ...................................................................................................................... 111
Port Specified as Input Port ......................................................................................................................... 112
Format of Pull-up Resistor Option Register L (PUOL) ............................................................................... 113
Pull-Up Resistor Specification (Port 4) ........................................................................................................ 114
Block Diagram of Port 5 ............................................................................................................................... 115
Format of Port 5 Mode Register (PM5) ....................................................................................................... 116
Port Specified as Output Port ...................................................................................................................... 117
Port Specified as Input Port ......................................................................................................................... 118
Format of Pull-Up Resistor Option Register L (PUOL) ............................................................................... 119
Pull-Up Resistor Specification (Port 5) ........................................................................................................ 120
Block Diagram of Port 6 ............................................................................................................................... 121
Format of Port 6 Mode Register (PM6) ....................................................................................................... 122
Port Specified as Output Port ...................................................................................................................... 123
Port Specified as Input Port ......................................................................................................................... 124
Format of Pull-Up Resistor Option Register L (PUOL) ............................................................................... 125
Pull-Up Resistor Specification (Port 6) ........................................................................................................ 126
Block Diagram of Port 7 ............................................................................................................................... 127
Block Diagram of Port 8 ............................................................................................................................... 128
Block Diagram of P90 to P93 (Port 9) ......................................................................................................... 130
Block Diagram of P94 (Port 9) ..................................................................................................................... 131
Format of Port 9 Mode Register (PM9) ....................................................................................................... 132
Format of Port 9 Mode Control Register (PMC9) ....................................................................................... 132
Port in Output Port Mode ............................................................................................................................. 133
Port in Input Port Mode ................................................................................................................................ 134
Format of Pull-up Resistor Option register H (PUOH)................................................................................ 135
Specifying Pull-up Resistor (port 9) ............................................................................................................. 136
Format of Port Read Control Register (PRDC)........................................................................................... 137
Concept of Control (in output port mode).................................................................................................... 138
6-1
Block Diagram of Timer ................................................................................................................................ 143
7-1
7-2
7-3
7-4
7-5
7-6
Block Diagram of Timer 0............................................................................................................................. 146
Format of Timer Unit Mode Register 0 (TUM0) .......................................................................................... 148
Format of Timer Mode Control Register (TMC) .......................................................................................... 149
Format of Timer Output Control Register 0 (TOC0) ................................................................................... 149
Format of Prescaler Mode Register (PRM) ................................................................................................. 150
Basic Operation of Timer Register 0 (TM0) ................................................................................................ 151
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LIST OF FIGURES (3/6)
Figure No.
Title
Page
7-7
Clear Operation of Timer Register 0 (TM0)................................................................................................. 152
Compare Operation (timer 0) ....................................................................................................................... 154
Capture Operation (timer 0) ......................................................................................................................... 156
Block Diagram of Timer Output Operation of Timer 0 ................................................................................ 158
Operation of Toggle Output .......................................................................................................................... 159
Operation of Set/Reset Output (timer 0) ..................................................................................................... 160
Timing of Interval Timer Operation .............................................................................................................. 161
Set Contents of Control Register for Interval Timer Operation .................................................................. 162
Setting Procedure of Interval Timer Operation ........................................................................................... 163
Interrupt Request Processing of Interval Timer Operation ......................................................................... 163
Timing of Pulse Width Measurement........................................................................................................... 164
Control Register Settings for Pulse Width Measurement ........................................................................... 165
Pulse Width Measurement Setting Procedure ............................................................................................ 166
Interrupt Request Processing that Calculates Pulse Width........................................................................ 166
Operation When Counting Is Started .......................................................................................................... 167
Operation When Compare Register (CC00 to CC03) Is Set to 0000H ..................................................... 168
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
8-1
Block Diagram of Timer 1............................................................................................................................. 170
Format of Timer Unit Mode Register 0 (TUM0) .......................................................................................... 172
Format of Timer Mode Control Register (TMC) .......................................................................................... 173
Format of Timer Output Control Register 1 (TOC1) ................................................................................... 173
Format of Prescaler Mode Register (PRM)................................................................................................. 174
Basic Operation of Timer Register 1 (TM1) ................................................................................................ 175
TM1 Clear Operation by Match with Compare Register (CM10) ............................................................... 176
TM1 Clear Operation When CE1 Bit is Cleared (0).................................................................................... 177
Compare Operation (timer 1) ....................................................................................................................... 179
Clearing TM1 after Detection of Match ....................................................................................................... 180
Block Diagram of Timer Output Operation of Timer 1 ................................................................................ 181
Operation of Toggle Output .......................................................................................................................... 182
Operation of Set/Reset Output (timer 1) ..................................................................................................... 183
Timing of Interval Timer Operation (1) ........................................................................................................ 184
Control Register Settings for Interval Timer Operation (1) ......................................................................... 185
Setting Procedure of Interval Timer Operation (1)...................................................................................... 186
Interrupt Request Processing of Interval Timer Operation (1) ................................................................... 186
Timing of Interval Timer Operation (2) ........................................................................................................ 187
Control Register Settings for Interval Timer Operation (2) ......................................................................... 188
Setting Procedure of Interval Timer Operation (2)...................................................................................... 188
Operation When Counting Is Started .......................................................................................................... 189
Operation When Compare Register (CM10, CM11) Is Set to 0000H ........................................................ 191
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
9-1
9-2
9-3
Block Diagram of Timer 4............................................................................................................................. 193
Format of Timer Mode Control Register 4 (TMC4) ..................................................................................... 195
Format of Prescaler Mode Register 4 (PRM4) ........................................................................................... 196
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LIST OF FIGURES (4/6)
Figure No.
Title
Page
9-4
Basic Operation of Timer Register 4 (TM4) ................................................................................................ 197
TM4 Clear Operation by Match with Compare Register (CM40, CM41) ................................................... 198
Clear Operation of TM4 When CE4 Bit is Cleared (0) ............................................................................... 199
Compare Operation (timer 4) ....................................................................................................................... 201
TM4 Clearance after Match Detection......................................................................................................... 201
Timing of Interval Timer Operation (1) ........................................................................................................ 202
Set Contents of Control Registers for Interval Timer Operation (1)........................................................... 203
Setting Procedure of Interval Timer Operation (1)...................................................................................... 204
Interrupt Request Processing of Interval Timer Operation (1) ................................................................... 204
Timing of Interval Timer Operation (2) ........................................................................................................ 205
Set Contents of Control Register for Interval Timer Operation (2) ............................................................ 206
Setting Procedure of Interval Timer Operation (2)...................................................................................... 206
Operation When Count Starts ...................................................................................................................... 207
Operation When Compare Register (CM40, CM41) Is Set to 0000H ........................................................ 208
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
10-1
10-2
Block Diagram of Watchdog Timer .............................................................................................................. 209
Format of Watchdog Timer Mode Register (WDM)..................................................................................... 211
11-1
Block Diagram of A/D Converter.................................................................................................................. 215
Example of Capacitor Connection on A/D Converter Pins ......................................................................... 216
Format of A/D Converter Mode Register (ADM) ......................................................................................... 218
Word Access to A/D Conversion Result Register ....................................................................................... 220
Byte Access to A/D Conversion Result Register ........................................................................................ 221
Basic Operation of A/D Converter ............................................................................................................... 223
Relationship Between Analog Input Voltage and A/D Conversion Result ................................................. 224
Operating Timing in Select Mode (1-buffer mode)...................................................................................... 225
Operation Timing in Select Mode (4-buffer mode)...................................................................................... 227
Operation Timing in Scan Mode .................................................................................................................. 228
A/D Conversion in Select Mode (1-buffer mode) Started by Software ...................................................... 229
A/D Conversion in Select Mode (4-buffer mode) Started by Software ...................................................... 230
A/D Conversion in Scan Mode Started by Software................................................................................... 230
A/D Conversion in Select Mode (1-buffer mode) Started by Hardware..................................................... 231
A/D Conversion in Select Mode (4-buffer mode) Started by Hardware..................................................... 232
A/D Conversion in Scan Mode Started by Hardware ................................................................................. 233
Example of Capacitor Connection on A/D Converter Pins ......................................................................... 234
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
12-1
12-2
12-3
Switching Between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ............................ 237
Block Diagram of Asynchronous Serial Interface........................................................................................ 239
Formats of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial
Interface Mode Register 2 (ASIM2) ............................................................................................................. 241
Formats of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial
12-4
12-5
Interface Status Register 2 (ASIS2) ............................................................................................................ 243
Data Format of Asynchronous Serial Interface Transmit/Receive ............................................................. 244
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LIST OF FIGURES (5/6)
Figure No.
Title
Page
12-6
Interrupt Timing of Asynchronous Serial Interface Transmission Completion ........................................... 246
Interrupt Timing of Asynchronous Serial Interface Reception Completion ................................................ 247
Timing of Receive Error ............................................................................................................................... 248
Transmission/Reception with Macro Service .............................................................................................. 250
Example of 3-Wire Serial I/O System Configuration................................................................................... 251
Block Diagram of 3-Wire Serial I/O Mode ................................................................................................... 252
Formats of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface Mode
Register 2 (CSIM2)....................................................................................................................................... 254
Timing of 3-Wire Serial I/O Mode ................................................................................................................ 255
Example of Connection to 2-Wire Serial I/O ............................................................................................... 256
Block Diagram of Baud Rate Generator...................................................................................................... 260
Formats of Baud Rate Generator Control Register (BRGC) and Baud Rate Generator Control
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
Register 2 (BRGC2) ..................................................................................................................................... 262
13-1
13-2
13-3
13-4
13-5
13-6
13-7
Format of External Interrupt Mode Register 0 (INTM0).............................................................................. 274
Format of External Interrupt Mode Register 1 (INTM1).............................................................................. 275
Format of Interrupt Valid Edge Flag Register 1 (IEF1) ............................................................................... 276
Format of Interrupt Valid Edge Flag Register 2 (IEF2) ............................................................................... 277
Format of Noise Protection Control Register (NPC)................................................................................... 277
Edge Detection for Pin P20 ......................................................................................................................... 278
Edge Detection for Pins P21 to P27............................................................................................................ 279
14-1
Interrupt Control Registers (××ICn) ............................................................................................................. 288
Format of Interrupt Mask Registers (MK0, MK1) ........................................................................................ 292
Format of In-Service Priority Register (ISPR) ............................................................................................. 293
Format of Interrupt Mode Control Register (IMC) ....................................................................................... 294
Format of Watchdog Timer Mode Register (WDM)..................................................................................... 295
Format of Program Status Word (PSWL) .................................................................................................... 296
Context Switching Operation by Execution of a BRKCS Instruction ......................................................... 297
Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) .............................. 298
Operations of Non-Maskable Interrupt Request Acknowledgment ............................................................ 300
Algorithm of Interrupt Acknowledgment Processing ................................................................................... 303
Context Switching Operation by Generation of an Interrupt Request........................................................ 304
Return from Interrupt that Uses Context Switching by Means of RETCS Instruction............................... 305
Examples of Processing When Another Interrupt Request Is Generated During Interrupt Processing ... 307
Examples of Processing of Simultaneously Generated Interrupts............................................................. 310
Differences in Level 3 Interrupt Acknowledgment According to Setting of Interrupt Mode Control
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
Register (IMC) .............................................................................................................................................. 311
Differences between Vectored Interrupt and Macro Service Processing .................................................. 312
Example of Macro Service Processing Sequence ...................................................................................... 316
Operation on Completion of Macro Service ................................................................................................ 317
Basic Configuration of Macro Service Control Word .................................................................................. 318
Format of Macro Service Control Word ....................................................................................................... 319
Interrupt Request Generation and Acknowledgment (Unit: Clocks) .......................................................... 339
14-16
14-17
14-18
14-19
14-20
14-21
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LIST OF FIGURES (6/6)
Figure No.
Title
Page
15-1
Format of Memory Expansion Mode Register (MM) ................................................................................... 341
Memory Map ................................................................................................................................................. 342
Read Timing (8 Bits)..................................................................................................................................... 344
Write Timing (8 Bits) ..................................................................................................................................... 344
Read Timing (16 Bits, Even Address Access)............................................................................................. 345
Write Timing (16 Bits, Even Address Access) ............................................................................................. 345
Read Timing (16 Bits, Odd Address Access) .............................................................................................. 346
Write Timing (16 Bits, Odd Address Access) .............................................................................................. 346
Format of Memory Extension Mode Register (MM).................................................................................... 347
Format of Programmable Wait Control Register 1 (PWC1) ....................................................................... 348
Format of Programmable Wait Control Register 2 (PWC2) ....................................................................... 350
Read/Write Timing of Address Wait Function.............................................................................................. 351
Format of Port 9 Mode Control Register (PMC9) ....................................................................................... 354
Wait Control Spaces ..................................................................................................................................... 355
Read Timing of Access Wait Function ......................................................................................................... 356
Write Timing of Access Wait Function ......................................................................................................... 358
Timing with External Wait Signal ................................................................................................................. 360
Format of Bus Width Specification Register (BW) ...................................................................................... 362
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
16-1
16-2
16-3
16-4
16-5
16-6
Diagram of Standby Mode Transition .......................................................................................................... 365
Block Diagram of Standby Function ............................................................................................................ 366
Standby Control Register (STBC) Format................................................................................................... 367
Format of Oscillation Stabilization Time Specification Register (OSTS) ................................................... 369
STOP Mode Release by NMI Input ............................................................................................................. 374
Example of Address/Data Bus Processing.................................................................................................. 378
17-1
17-2
17-3
Acknowledgment of Reset Signal ................................................................................................................ 380
Power-On Reset Operation .......................................................................................................................... 380
Timing on Reset Input .................................................................................................................................. 381
18-1
18-2
18-3
18-4
Format of Internal Memory Size Select Register (IMS).............................................................................. 385
Selecting Format of Communication Mode ................................................................................................. 386
Connecting Flashpro II/Flashpro III in 3-Wire Serial I/O Mode .................................................................. 387
Connecting Flashpro II/Flashpro III in UART Mode .................................................................................... 387
A-1
A-2
A-3
A-4
A-5
Development Tool Configuration.................................................................................................................. 456
Distance Between In-Circuit Emulator and Conversion Socket ................................................................. 463
Target System Connection Conditions ........................................................................................................ 464
Dimensions of EV-9200GC-80 (reference).................................................................................................. 465
Recommended Board Mounting Pattern of EV-9200GC-80 (reference) ................................................... 466
User’s Manual U11719EJ3V1UD
24
LIST OF TABLES (1/3)
Table No.
Title
Page
1-1
1-2
1-3
Differences between µPD784054 and µPD784046 Subseries................................................................... 36
Differences between µPD784054 and µPD784054(A) ............................................................................... 37
Differences between µPD784054(A), 784054(A1), and 784054(A2) ......................................................... 37
2-1
2-2
2-3
2-4
Operation Mode of Port 2............................................................................................................................. 41
Operation Mode of Port 3............................................................................................................................. 42
Operation Mode of Port 9............................................................................................................................. 43
I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins ......................................... 47
3-1
3-2
3-3
3-4
3-5
3-6
Internal ROM Area ........................................................................................................................................ 51
Vector Table .................................................................................................................................................. 52
Internal RAM Area ........................................................................................................................................ 54
Register Bank Selection ............................................................................................................................... 60
Correspondence between Function Names and Absolute Names............................................................. 71
Special Function Registers (SFRs) List ...................................................................................................... 73
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Port Function ................................................................................................................................................ 88
Operation Mode of Port 2............................................................................................................................. 97
Port 3 Operating Modes ............................................................................................................................... 103
Operation Mode of Port 4............................................................................................................................. 110
Operation Mode of Port 5............................................................................................................................. 116
Operation Mode of Port 6............................................................................................................................. 120
Operation Mode of Port 9............................................................................................................................. 129
Operation Mode of P90 to P93 .................................................................................................................... 130
6-1
Operations of Timer ...................................................................................................................................... 140
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Interval Time of Timer 0 ............................................................................................................................... 144
Pulse Width Measurement Range of Timer 0 ............................................................................................. 145
Interrupt Request Signal from Compare Register (timer 0) ....................................................................... 153
Operation Mode of Timer Output Pin (timer 0) ........................................................................................... 153
Capture Trigger Signal to Capture Register (timer 0)................................................................................. 155
Toggle Signal of Timer Output Pin (timer 0) ................................................................................................ 157
Set/Reset Signal of Timer Output Pin (timer 0) .......................................................................................... 157
Toggle Output of TO00 to TO03 (fCLK = 16 MHz) ........................................................................................ 160
8-1
8-2
8-3
8-4
8-5
8-6
Interval Time of Timer 1 ............................................................................................................................... 169
Interrupt Request Signal from Compare Register (timer 1) ....................................................................... 178
Operation Mode of Timer Output Pin (timer 1) ........................................................................................... 178
Toggle Signal of Timer Output Pin (timer 1) ................................................................................................ 181
Set/Reset Signal of Timer Output Pin (timer 1) .......................................................................................... 181
Toggle Output of TO10 and TO11 (fCLK = 16 MHz) ..................................................................................... 182
User’s Manual U11719EJ3V1UD
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LIST OF TABLES (2/3)
Table No.
Title
Page
9-1
9-2
Interval Time of Timer 4 ............................................................................................................................... 192
Interrupt Request Signal from Compare Register (timer 4) ....................................................................... 200
11-1
11-2
11-3
Conversion Time Set by FR Bit ................................................................................................................... 219
Time of A/D Conversion ............................................................................................................................... 224
Correspondence between Analog Input and A/D Conversion Result Register
(select mode: 1-buffer mode) ....................................................................................................................... 225
Correspondence between Analog Input and A/D Conversion Result Register
11-4
11-5
(select mode: 4-buffer mode) ....................................................................................................................... 226
Correspondence between Analog Input and A/D Conversion Result Register (scan mode).................... 228
12-1
12-2
12-3
12-4
12-5
Differences Between UART/IOE1 and UART2/IOE2 Names ..................................................................... 236
Causes of Receive Error .............................................................................................................................. 248
Methods of Baud Rate Setting ..................................................................................................................... 264
Examples of BRGC Settings When Baud Rate Generator Is Used ........................................................... 265
Examples of Settings When External Baud Rate Input (ASCK) Is Used................................................... 266
13-1
Pins P20 to P27 and Use of Detected Edge ............................................................................................... 273
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
Processing Modes of Interrupt Request ...................................................................................................... 281
Sources of Interrupt Request ....................................................................................................................... 281
Control Registers .......................................................................................................................................... 285
Interrupt Control Register Flags Corresponding to Interrupt Sources ....................................................... 286
Multiple Interrupt Processing ....................................................................................................................... 306
Interrupts for Which Macro Service Can Be Used ...................................................................................... 313
Classification of Macro Service Mode ......................................................................................................... 320
Specifying Operation of Counter Mode ....................................................................................................... 321
Specifying Operation in Block Transfer Mode............................................................................................. 322
Specifying Operation in Block Transfer Mode (with memory pointer)........................................................ 324
Interrupt Acceptance Processing Time ........................................................................................................ 335
Macro Service Processing Time .................................................................................................................. 336
16-1
16-2
16-3
16-4
16-5
16-6
Operating States in HALT Mode .................................................................................................................. 370
HALT Mode Release and Operations after Release................................................................................... 371
Operating States in STOP Mode ................................................................................................................. 373
STOP Mode Release and Operations after Release .................................................................................. 374
Operating States in IDLE Mode ................................................................................................................... 375
IDLE Mode Release and Operations after Release ................................................................................... 376
17-1
17-2
Pin Status during Reset Input and after Clearing Reset ............................................................................ 381
State of Hardware after Reset ..................................................................................................................... 382
User’s Manual U11719EJ3V1UD
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LIST OF TABLES (3/3)
Table No.
Title
Page
18-1
18-2
Communication Modes ................................................................................................................................. 386
Major Functions of Flash Memory Programming. ....................................................................................... 386
19-1
19-2
19-3
19-4
19-5
List of Instructions by 8-Bit Addressing ....................................................................................................... 417
List of Instructions by 16-Bit Addressing ..................................................................................................... 419
List of Instructions by 24-Bit Addressing ..................................................................................................... 421
List of Instructions by Bit Manipulation Instruction Addressing .................................................................. 421
List of Instructions by Call/Return Instruction/Branch Instruction Addressing ........................................... 422
26-1
Surface Mounting Type Soldering Conditions ............................................................................................. 453
User’s Manual U11719EJ3V1UD
27
CHAPTER 1 GENERAL
TheµPD784054isaproductinthe78K/IVseriesandisprovidedwitha10-bitA/Dconverter. The78K/IVseriesisacollection
of 16-bit single-chip microcontrollers with a high-performance CPU that has a function to access a 1M-byte memory space.
The µPD784054 is based on the µPD784046 Subseries in the 78K/IV series but does not have the real-time output function
and two timer/counter units of the µPD784046 Subseries. It is provided with a standby function invalid mode.
The µPD784054 has a 32K-byte mask ROM and a 1024-byte RAM. In addition, it also has a high-performance timer, 10-
bit A/D converter, and two independent serial interface channels.
TheµPD78F4046isavailableasaflashmemorymodelthatcanoperateatthesamesupplyvoltageasthemaskROMmodel.
The µPD78F4046 is a model of the µPD784046 Subseries and its functions are different from the µPD784054. For the
differences, refer to 1.8 Differences between µPD784054 and µPD784046 Subseries.
The µPD784054(A), 784054(A1), and 784054(A2) are the “special” quality revisions of the µPD784054.
µPD78F4046
µ
µ
µ
PD784046, 784046(A), (A1), (A2)
Flash memory 64K
RAM 2048
ROM 64K
RAM 2048
µPD784046
Subseries
PD784044, 784044(A), (A1), (A2)
ROM 32K
RAM 1024
PD784054, 784054(A), (A1), (A2)
ROM 32K
RAM 1024
On-chip flash memory model
Mask ROM model
These products can be used for the following applications.
[Standard models]
• Office machines such as PPCs and printers
• Factory machines such as robots and automatic machine tools
[Special models]
• Control units of automotive appliances
28
User’s Manual U11719EJ3V1UD
CHAPTER 1 GENERAL
78K/IV Series Product Lineup
: Products in mass-production
Supports I2C bus
Supports multimaster I2C bus
PD784225Y
µ
PD784038Y
PD784038
Enhanced internal memory capacity
µ
µ
µ
PD784225
Standard models
PD784026
80-pin, ROM correction added
Pin-compatible with the µPD784026
µ
Supports multimaster I2C bus
Supports multimaster I2C bus
Enhanced
A/D converter,
16-bit timer, and
power management
µ
PD784216AY
µ
PD784218AY
µ
PD784216A
µPD784218A
100-pin, enhanced I/O and
internal memory capacity
Enhanced internal memory
capacity, ROM correction added
µ
PD784054
µ
PD784046
On-chip 10-bit A/D converter
ASSP models
PD784956A
µ
µ
PD784938A
For DC inverter control
Enhanced functions of the
µ
PD784908, enhanced
µ
PD784908
internal memory capacity,
ROM correction added.
On-chip IEBusTM controller
Supports multimaster I2C bus
µ
PD784928Y
PD784928
Enhanced functions
µ
µ
PD784915
of the PD784915
µ
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
µ
PD784976A
On-chip VFD controller/driver
Remark VFD (Vacuum Florescent Display) is referred to as FIPTM (Florescent Indicator Panel) in some documents, but
the functions of the two are the same.
User’s Manual U11719EJ3V1UD
29
CHAPTER 1 GENERAL
1.1 Features
78K/IV series
•
•
•
Minimum instruction execution time: 125 ns (at internal 16-MHz)
Internal memory
• ROM
Mask ROM : 32K bytes
• RAM
: 1024 bytes
I/O port: 64 pins
Timer
•
•
•
•
•
: 16-bit timer × 3 units
Watchdog timer: 1 channel
A/D converter : 10-bit resolution × 16 channels
Serial interface
UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)
Interrupt controller (4 priority levels)
Vectored interrupt/macro service/context switching
Standby function
•
•
•
HALT/STOP/IDLE/standby function invalid mode
Supply voltage : VDD = 4.5 to 5.5 V
1.2 Ordering Information
Part Number
Package
µPD784054GC-×××-3B9
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
µPD784054GC(A)-×××-3B9
µPD784054GC(A1)-×××-3B9
µPD784054GC(A2)-×××-3B9
µPD784054GC-×××-3B9-A
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by “-A” are lead-free products.
1.3 Quality Grades
Part Number
Package
Quality Grade
µPD784054GC-×××-3B9
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
80-pin plastic QFP (14 x 14)
Standard
Special
Special
Special
Standard
µPD784054GC(A)-×××-3B9
µPD784054GC(A1)-×××-3B9
µPD784054GC(A2)-×××-3B9
µPD784054GC-×××-3B9-A
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by “-A” are lead-free products.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications.
30
User’s Manual U11719EJ3V1UD
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
• 80-pin plastic QFP (14 x 14)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
AVREF
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P22/INTP1/TO01
BWD
2
3
P21/INTP0/TO00
MODE
4
5
P20/NMI
VSS
6
7
VDD
8
MODE1
9
P12
AVDD
10
11
12
13
14
15
16
17
18
19
20
P11
VSS
P10
VDD
P03
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P02
P01
P00
P37/ASCK2/SCK2
P36/TxD2/SO2
P35/RxD2/SI2
P34/ASCK/SCK1
P33/TxD/SO1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Do not directly connect the MODE pin to VSS.
2. Normally, directly connect the MODE1 pin to VSS.
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CHAPTER 1 GENERAL
P40-P47
P50-P57
P60-P63
: Port 4
A16-A19
AD0-AD15
ANI0-ANI15
ASCK, ASCK2
ASTB
: Address Bus
: Port 5
: Address/Data Bus
: Analog Input
: Port 6
P70-P77
P80-P87
P90-P94
RD
: Port 7
: Asynchronous Serial Clock
: Address Strobe
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
: Bus Width Definition
: Clock Out
: Port 8
: Port 9
AVDD
: Read Strobe
: Reset
AVREF
RESET
AVSS
RxD, RxD2
SCK1, SCK2
SI1, SI2
SO1, SO2
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
BWD
CLKOUT
HWR
: High Address Write Strobe
: Interrupt from Peripherals
: Low Address Write Strobe
: Mode
INTP0-INTP6
LWR
TO00-TO03, TO10, TO11: Timer Output
TxD, TxD2
VDD
: Transmit Data
: Power Supply
: Ground
MODE, MODE1
NMI
: Non-maskable Interrupt
: Port0
VSS
P00-P03
P10-P12
P20-P27
P30-P37
WAIT
X1, X2
: Wait
: Port1
: Crystal
: Port2
: Port3
32
User’s Manual U11719EJ3V1UD
CHAPTER 1 GENERAL
1.5 System Configuration Example (PPC)
µPD784054
P60
P61
P62
P63
Paper detection
RxD
Serial communication
TxD
Paper feed detection
Paper ejection detection
Manuscript table (scanner) position detection
SCK2
SI2
SO2
Operation
panel
Paper feed/transporta-
tion detection
INTP0
High-voltage
control circuit
P10-P12
P40
Drum, toner, charge for transcription
Fusion unit
heater control
circuit
Fusion unit roller
Fusion unit heater
temperature
ANI0
ANI1
Manuscript illumination lamp,
lamp for elimination of electric charge
P41
Lamp regulator
Lamp light
quantity
(DC, stepping)
TO10
P00-P03
M
Main motor
Copy density
adjuster lever
ANI2
ANI3
Manuscript table (scanner)
stop clutch
SL
SL
P42
P43
P44
P45
P46
Manuscript table (scanner)
forward clutch
Driver
Copy density
correction
lever
SL Resist shutter clutch
SL Manual paper feed clutch
SL Cassette paper feed clutch
Reset
circuit
RESET
Solenoid
User’s Manual U11719EJ3V1UD
33
CHAPTER 1 GENERAL
1.6 Block Diagram
BWD
Programmable
interrupt
controller
NMI
AD0-AD15
A16-A19
RD
INTP0-INTP6
BUS I/F
LWR, HWR
ASTB
WAIT
INTP0-INTP3
TO00-TO03
Timer 0
(16 bits)
Port 0
Port 1
P00-P03
P10-P12
Timer 1
(16 bits)
TO10, TO11
P20
Port 2
Port 3
Port 4
P21-P27
78K/IV
ROM
Timer 4
(16 bits)
CPU core
P30-P37
P40-P47
ANI0-ANI15
AVDD
A/D
converter
AVSS
AVREF
INTP4
Port 5
Port 6
P50-P57
P60-P63
P70-P77
RAM
Watchdog
timer
Port 7
Port 8
Port 9
P80-P87
P90-P94
RxD/SI1
TxD/SO1
UART/IOE1
Baud-rate
generator
ASCK/SCK1
CLKOUT
RESET
MODE
MODE1
X1
RxD2/SI2
TxD2/SO2
System
control
UART/IOE2
Baud-rate
generator
ASCK2/SCK2
X2
V
DD
SS
V
34
User’s Manual U11719EJ3V1UD
CHAPTER 1 GENERAL
1.7 List of Functions
Item
Function
Number of basic instructions
(mnemonics)
113
General-purpose register
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
Minimum instruction execution time 125 ns (at internal 16 MHz operation)
Internal memory
ROM
RAM
32 KB (mask ROM)
1024 B
Memory space
I/O port
1 MB with program and data memories combined
Total
Input
I/O
64 lines
17 lines
47 lines
Pins with ancillary Pin with pull- 29 pins
functionsNote
up resistor
Timer
Timer 0 (16 bits)
Timer 1 (16 bits)
Timer 4 (16 bits)
: Timer register × 1
Capture/Compare register × 4
Pulse output
• Toggle output
• Set/Reset output
Pulse output
: Timer register × 1
Compare register × 2
• Toggle output
• Set/Reset output
: Timer register × 1
Compare register × 2
A/D converter
Serial interface
Watchdog timer
10-bit resolution × 16 channels
UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)
1 channel
Interrupt
Hardware source
Software source
Non-maskable
Maskable
23 (internal: 19, external: 8 (shared with internal: 4)
BRK instruction, BRKCS instruction, operand error
Internal : 1, external : 1
Internal : 18, external: 7 (shared with internal: 4)
• 4 priority levels
• Three processing formats: vectored interrupt/macro service/context switching
Bus sizing
Standby
8 bits/16 bits external data bus width selectable
HALT/STOP/IDLE/standby function invalid mode
VDD = 4.5 to 5.5 V
Supply voltage
Package
80-pin plastic QFP (14 x 14)
Note The pins with ancillary functions are included in the I/O pins.
User’s Manual U11719EJ3V1UD
35
CHAPTER 1 GENERAL
1.8 Differences between µPD784054 and µPD784046 Subseries
The differences between µPD784054 and µPD784046 Subseries are shown in Table 1-1.
Table 1-1. Differences between µPD784054 and µPD784046 Subseries
Part Number
µPD784054
µPD784046 Subseries
µPD784046
Item
µPD784044
µPD78F4046
64 KB
(flash memory)
Internal ROM
32 KB
64 KB
(mask ROM)
(mask ROM)
Internal RAM
Port 1
1024 B
2048 B
P10-P12
P10-P13
4 bits × 1
Real-time output port
Timer/counter
Not provided
16 bits timer
16 bits timer/counter × 2 units
16 bits timer × 3 units
× 3 units
Standby function
HALT/STOP/IDLE/
standby function
invalid mode
HALT/STOP/IDLE mode
MODE1 pin
Provided
Mode
23
Not provided
27
Function of pin 57
Interrupt hardware source
Mode/VPP
36
User’s Manual U11719EJ3V1UD
CHAPTER 1 GENERAL
1.9 Differences between µPD784054 and µPD784054(A)
Table 1-2. Differences between µPD784054 and µPD784054(A)
Part Number
µPD784054
µPD784054(A)
Item
Quality grade
Standard
Special
Operating ambient temperature (TA) –10 to +70°C
–40 to +85°C
8 to 25 MHz
Operating frequency
8 to 32 MHz
Minimum instruction execution time
DC characteristics
125 ns (operates at 16 MHz internally)
VDD supply current differs.
160 ns (operates at 12.5 MHz internally)
AC characteristics
Bus timing and serial operation differ.
Conversion time and sampling time differ.
A/D converter characteristics
1.10 Differences between µPD784054(A), 784054(A1), and 784054(A2)
Table 1-3. Differences between µPD784054(A), 784054(A1), and 784054(A2)
Part Number
µPD784054(A)
µPD784054(A1)
–40 to +110°C
µPD784054(A2)
–40 to +125°C
Item
Operating ambient temperature (TA) –40 to +85°C
Operating frequency
8 to 25 MHz
8 to 20 MHz
Minimum instruction execution time
160 ns
200 ns
(operates at 12.5 MHz internally) (operates at 10 MHz internally)
DC characteristics
Analog pin input leakage current, VDD supply current, and data retention current differ.
Bus timing and serial operation differ.
AC characteristics
A/D converter characteristics
AVREF current, A/D converter data retention current differ.
User’s Manual U11719EJ3V1UD
37
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1) Port (1/2)
Pin Name
P00-P03
I/O
I/O
Dual-Function Pins
Function
–
Port 0 (P0):
•
•
•
4-bit I/O port
Can be set in input/output mode bit-wise.
Pins in input mode can all be connected to pull-up resistors at once
via software by software settings.
P10-P12
I/O
–
Port 1 (P1):
•
•
3-bit I/O port
Can be set in input/output mode bit-wise.
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40-P47
Input
I/O
NMI
Port 2 (P2):
8-bit I/O port
Input only
INTP0/TO00
INTP1/TO01
INTP2/TO02
INTP3/TO03
INTP4
•
Can be set in input/output mode
bit-wise.
INTP5
INTP6
I/O
TO10
Port 3 (P3):
TO11
•
•
8-bit I/O port
Can be set in input/output mode bit-wise.
RxD/SI1
TxD/SO1
ASCK/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
AD0-AD7
I/O
I/O
I/O
Port 4 (P4):
•
•
•
8-bit I/O port
Can be set in input/output mode bit-wise.
Pins in input mode can all be connected to pull-up resistors at once
via software by software settings.
P50-P57
P60-P63
AD8-AD15
A16-A19
Port 5 (P5):
•
•
•
8-bit I/O port
Can be set in input/output mode bit-wise.
Pins in input mode can all be connected to pull-up resistors at once
via software by software settings.
Port 6 (P6):
•
•
•
4-bit I/O port
Can be set in input/output mode bit-wise.
Pins in input mode can all be connected to pull-up resistors at once
via software by software settings.
User’s Manual U11719EJ3V1UD
38
CHAPTER 2 PIN FUNCTIONS
(1) Port (2/2)
Pin Name
P70-P77
I/O
Dual-Function Pins
Function
Input
ANI0-ANI7
Port 7 (P7):
8-bit input port
Port 8 (P8):
8-bit input port
Port 9 (P9):
•
P80-P87
Input
I/O
ANI8-ANI15
•
P90
P91
P92
P93
P94
RD
LWR
HWR
ASTB
WAIT
•
•
•
5-bit I/O port
Can be set in input/output mode bit-wise.
Pins in input mode can all be connected to pull-up resistors at once
via software by software settings.
(2) Pins other than port pins (1/2)
Pin Name
NMI
I/O
Dual-Function Pins
P20
Function
Input
Non-maskable interrupt request input
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
TO00
TO01
TO02
TO03
TO10
TO11
RxD
P21/TO00
P22/TO01
P23/TO02
P24/TO03
P25
External interrupt
request input
Capture trigger signal of CC00
Capture trigger signal of CC01
Capture trigger signal of CC02
Capture trigger signal of CC03
Conversion start trigger input of A/D converter
–
P26
P27
Output P21/INTP0
P22/INTP1
P23/INTP2
P24/INTP3
P30
Timer output
P31
Input
P32/SI1
P35/SI2
Serial data input (UART0)
RxD2
TxD
Serial data input (UART2)
Output P33/SO1
P36/SO2
Serial data output (UART0)
TxD2
ASCK
ASCK2
SI1
Serial data output (UART2)
Input
P34/SCK1
P37/SCK2
P32/RxD
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Input
Serial data input (3-wire serial I/O1)
Serial data input (3-wire serial I/O2)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock input/output (3-wire serial I/O1)
Serial clock input/output (3-wire serial I/O2)
Lower multiplexed address/data bus when external memory is connected
SI2
P35/RxD2
SO1
Output P33/TxD
P36/TxD2
SO2
SCK1
SCK2
AD0-AD7
I/O
P34/ASCK
P37/ASCK2
P40 to P47
I/O
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CHAPTER 2 PIN FUNCTIONS
(2) Pins other than port pins (2/2)
Pin Name
I/O
I/O
Dual-Function Pins
P50 to P57
Function
AD8-AD15Note
•
•
When 8-bit bus is specified
Higher address bus when external memory is connected
When external 16-bit bus is specified
Higher multiplexed address/data bus when external memory is connected
A16-A19Note
RD
Output P60 to P63
Output P90
Higher address bus when external memory is connected
Read strobe to external memory
LWR
Output P91
•
When external 8-bit bus is specified
Write strobe to external memory
•
When external 16-bit bus is specified
Write strobe to external memory located at lower position
HWR
P92
Write strobe to external memory located at higher position when external
16-bit bus is specified
ASTB
Output P93
Timing signal output to externally latch address information output from
AD0 to AD15 pins to access external memory
WAIT
Input
Input
Input
Input
P94
Inserts wait.
BWD
–
–
–
Sets bus width.
MODE
MODE1
Directly connect this pin to VSS (this pin specifies test mode of IC).
Specifies standby function invalid mode.
Connect this pin to VSS when this mode is not used.
CLKOUT
Output
–
Clock output. Low level is output in the IDLE mode or STOP mode, otherwise
fXX (oscillation frequency) is always output.
X1
Input
–
–
–
–
Connect crystal for system clock oscillation (clock can also be input to X1).
X2
RESET
ANI0-ANI7
ANI8-ANI15
AVREF
AVDD
Input
Input
Chip reset
P70 to P77
Analog voltage input for A/D converter
P80 to P87
–
–
–
–
–
–
Reference voltage for A/D converter
Positive power for A/D converter
GND for A/D converter
Positive power
AVSS
VDD
VSS
–
GND
Note The number of pins used as address bus pins differs depending on the external address space (refer to
CHAPTER 15 LOCAL BUS INTERFACE FUNCTION).
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
(1) P00 to P03 (Port 0) ... 3-state I/O
Port 0 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 0 mode register (PM0). Each pin of this port is provided with a software programmable pull-up resistor.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
(2) P10 to P12 (Port 1) ... 3-state I/O
Port 1 is a 3-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 1 mode register (PM1).
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
(3) P20 to P27 (Port 2) ... 3-state I/O
Port 2 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 2 mode register (PM2) (however, P20 is input-only).
In addition to the input/output port function, port 2 also functions as external interrupt signals, and to output the
timer signal of timer 0 (refer to Table 2-1). P21 to P24 serve as the timer output pins of timer 0 if so specified by
port 2 mode control register (PMC2). The level of each pin of this port can always be read or tested regardless
of the multiplexed function. All the eight pins are Schmitt-trigger input pins to prevent malfunctioning due to noise.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
Table 2-1. Operation Mode of Port 2
(n = 0 to 7)
Mode
Port Mode
PMC2n = 0
Control Signal Output Mode
Set condition
PMC2n = 1
PM2n = ×
–
PM2n = 0
–
PM2n = 1
P20
P21
P22
P23
P24
P25
P26
P27
Input port/NMI inputNote
Input port/INTP0 input
Input port/INTP1 input
Input port/INTP2 input
Input port/INTP3 input
Input port/INTP4 input
Input port/INTP5 input
Input port/INTP6 input
Output port
TO00 output
TO01 output
TO02 output
TO03 output
–
Note The NMI input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled.
Remark ×: don’t care
(a) Port mode
(i) Function as port pin
Each port pin set in the port mode by the port 2 mode control register (PMC2) can be set in the input or
output mode in 1-bit units by the port 2 mode register (PM2) (however, P20 is fixed in input only).
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CHAPTER 2 PIN FUNCTIONS
(ii) Function as control signal input pins
If PMC2n (n = 0 to 7) bit of PMC2 is “0” and if PM2n (n = 0 to 7) bit of PM2 is “1”, the pins of port 2 can
be used as the following control signal input pins.
•
•
NMI (Non-maskable Interrupt)
This pin inputs an external non-maskable interrupt request. Whether the interrupt request is detected
at the rising or falling edge can be specified by using external interrupt mode register 0 (INTM0).
INTP0 to INTP6 (Interrupt from Peripherals)
Thesepinsinputexternalinterruptrequests. Whenthevalidedgespecifiedbyexternalinterruptmode
registers (INTM0 and INTM1) is detected on the INTP0 to INTP6 pins, an interrupt occurs (refer to
CHAPTER 13 EDGE DETECTION FUNCTION).
The INTP0 to INTP4 pins can also be used as external trigger input pins of each function, as follows:
•
•
•
•
•
INTP0 ... Capture trigger input pin of capture/compare register 00 (CC00) of timer 0
INTP1 ... Capture trigger input pin of capture/compare register 01 (CC01) of timer 0
INTP2 ... Capture trigger input pin of capture/compare register 02 (CC02) of timer 0
INTP3 ... Capture trigger input pin of capture/compare register 03 (CC03) of timer 0
INTP4 ... External trigger input pin of A/D converter
(b) Control signal output mode
The P21 to P24 pins can be used as the timer output pins (TO00 to TO03) of timer 0 in 1-bit units if so specified
by the port 2 mode control register (PMC2).
(4) P30 to P37 (Port 3) ... 3-state I/O
Port 3 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 3 mode register (PM3).
In addition to the input/output port function, port 3 also has a function to input or output control signals. The
operation mode of each pin can be specified by using port 3 mode control register (PMC3), as shown in Table 2-
2. The level of each pin of this port can always be read or tested regardless of the multiplexed function.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
Table 2-2. Operation Mode of Port 3
(n = 0 to 7)
Mode
Port Mode
PMC3n = 0
I/O port
Control Signal I/O Mode
PMC3n = 1
Setting condition
P30
P31
P32
P33
P34
P35
P36
P37
TO10 output
TO11 output
RxD/SI1 input
TxD/SO1 output
ASCK input/SCK1 I/O
RxD2/SI2 input
TxD2/SO2 output
ASCK2 input/SCK2 I/O
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CHAPTER 2 PIN FUNCTIONS
(a) Port mode
Each port pin set in the port mode by the port 3 mode control register (PMC3) can be set in the input or output
mode by the port 3 mode register (PM3).
(b) Control signal I/O mode
Eachpinofport3canbesetinthecontrolmodein1-bitunitsbyusingtheport3modecontrolregister(PMC3).
(i) TO10, TO11 (Timer Output)
These are timer output pins of timer 1.
(ii) RxD, RxD2 (Receive Data)
These are serial data input pins of the asynchronous serial interface.
(iii) TxD, TxD2 (Transmit data)
These are serial data output pins of the asynchronous serial interface.
(iv) SI1, SI2 (Serial Input)
These are serial data input pins of the 3-wire serial I/O.
(v) SO1, SO2 (Serial Output)
These are serial data output pins of the 3-wire serial I/O.
(vi) ASCK, ASCK2 (Asynchronous Serial Clock)
These are external baud rate clock input pins.
(vii) SCK1, SCK2 (Serial Clock)
These are serial clock I/O pins of the 3-wire serial I/O.
(5) P40 to P47 (Port 4) ... 3-state I/O
Port 4 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 4 mode register (PM4). Each pin is provided with a software programmable pull-up resistor.
Port 4 functions as the low-order multiplexed address/data bus (AD0 to AD7) if so specified by memory expansion
mode register (MM) when an external memory or I/O is connected, in addition to the I/O port function.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
(6) P50 to P57 (Port 5) ... 3-state I/O
Port 5 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 5 mode register (PM5). Each pin is provided with a software programmable pull-up resistor.
This port functions as follows if so specified by memory expansion mode register (MM) when an external memory
or I/O is connected:
•
•
When external 8-bit bus is specified
As the high-order address bus (AD8 to AD15)
When external 16-bit bus is specified
As the high-order multiplexed address/data bus (AD8 to AD15).
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
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CHAPTER 2 PIN FUNCTIONS
(7) P60 to P63 (Port 6) ... 3-state I/O
Port 6 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 6 mode register (PM6). Each pin is provided with a software programmable pull-up resistor.
In addition to as an I/O port, this port also functions as the high-order address bus (A16 to A19) if so specified by
the memory expansion mode register when an external memory or I/O is connected.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
(8) P70 to P77 (Port 7) ... Input
Port 7 is an 8-bit input port. In addition to as input port pins, its pins also function as an A/D converter analog input
(low-order 8 channels) pins (ANI0 to ANI7), and can always input analog signals. This port is set in the analog
input mode by using A/D converter mode register (ADM).
The level of each pin of this port can always be read or tested, regardless of the multiplexed function.
(9) P80 to P87 (Port 8) ... Input
Port 8 is an 8-bit input port. In addition to functioning as input port pins, its pins also functions as an A/D converter
analog input (high-order 8 channels) pins (ANI8 to ANI15), and can always input analog signals. This port is set
in the analog input mode by using A/D converter mode register (ADM).
The level of each pin of this port can always be read or tested, regardless of the multiplexed function.
(10) P90 to P94 (Port 9) ... 3-state I/O
Port 9 is a 5-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 9 mode register (PM9). Each pin is provided with a software programmable pull-up resistor.
In addition to the I/O port function, port 9 also functions as control signal pins (refer to Table 2-3). P90 to P93
function as read/write strobe signals and an address strobe signal if so specified by the memory extension mode
register (MM) when an external memory or I/O is connected. P94 functions as a wait signal input pin if so specified
by port 9 mode control register (PMC9).
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
Table 2-3. Operation Mode of Port 9
Pin Name Port Mode
Control Signal I/O Mode
Manipulation to Use Port 9 as Control Pins
Specifying external memory expansion mode by
MM0 to MM3 bits of MM
P90
P91
P92
P93
P94
I/O Port
RD
LWR
HWR
ASTB
WAIT
Setting of PMC94 bit of PMC9 to 1
Remark For details, refer to CHAPTER 15 LOCAL BUS INTERFACE FUNCTION.
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CHAPTER 2 PIN FUNCTIONS
(a) Port mode
Eachportpinnotsetinthecontrolmodecanbesetintheinputoroutputmodebyusingtheport9moderegister
(PM9).
(b) Control signal I/O mode
(i) RD (Read Strobe)
This pin outputs a strobe signal to read an external memory. The operation of this pin is specified by the
memory extension mode register (MM).
(ii) LWR, HWR (Low/High Write Strobe)
These pins output strobe signals to write an external memory. The operations of these pins are specified
by the memory extension mode register (MM).
(iii) ASTB (Address Strobe)
This is a timing signal output pin to latch the address information output from the AD0 to AD15 pins to
access the external memory. The operation of this pin is specified by the memory extension mode
register (MM).
(iv) WAIT (Wait)
This pin inputs a wait signal. The operation of this pin is specified by the port 9 mode control register
(PMC9).
(11) BWD (Bus Width Definition) ... Input
This pin specifies the width of the bus. Depending on the setting of this pin, the value of the bus width specification
register (BW) at reset differs as follows:
BWD
External Bus Width
8 bits
16 bits
Value of BW at Reset
0000H
00FFH
0
1
(12) MODE (Mode) ... Input
This pin is used by NEC Electronics for testing IC. Be sure to directly connect this pin to VSS.
(13) MODE1 (Mode) ... Input
This pin specifies the standby function invalid mode.
Connect this pin to VSS when this mode is not used.
(14) CLKOUT (Clock Output) ... Output
Clock output. Low level is output in the IDLE mode or STOP mode, otherwise fXX (oscillation frequency) is always
output.
(15) X1, X2 (Crystal)
These pins are used to connect a crystal for internal clock oscillation. To supply an external clock, input the clock
to the X1 pin. For the processing of the X2 pin at this time, refer to CHAPTER 4 CLOCK GENERATOR.
(16) RESET (Reset) ... Input
Active-low reset input
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CHAPTER 2 PIN FUNCTIONS
(17) AVREF (Analog Reference Voltage)
This pin inputs a reference voltage to the A/D converter.
(18) AVDD (Analog Power Supply)
This is the power supply pin of the A/D converter. Keep the potential at this pin same as that of the VDD pin.
(19) AVSS (Analog Ground)
This is the GND pin of the A/D converter. Keep the potential at this pin same as that of the VSS pin.
(20) VDD (Power Supply)
This is a positive power supply. Connect all the VDD pins to a positive power supply.
(21) VSS (Ground)
This is a GND pin. Ground all the VSS pins.
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CHAPTER 2 PIN FUNCTIONS
2.3 I/O Circuits of Pins and Processing of Unused Pins
Table 2-4 shows the I/O circuit type of each pin and recommended processing of the unused pins.
For the I/O circuit type, refer to Figure 2-1.
Table 2-4. I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins
Pin Name
P00-P03
I/O Circuit Type
I/O
I/O
Recommended Connection of Unused Pins
Input: Individually connect to VDD or VSS via resistor.
Output: Leave unconnected.
5-A
5
P10-P12
P20/NMI
2
Input
I/O
Connect to VSS.
P21/INTP0/TO00
P22/INTP1/TO01
P23/INTP2/TO02
P24/INTP3/TO03
P25/INTP4
8
Input: Individually connect to VDD or VSS via resistor.
Output: Leave unconnected.
P26/INTP5
P27/INTP6
P30/TO10
5
P31/TO11
P32/RxD/SI1
P33/TxD/SO1
P34/ASCK/SCK1
P35/RxD2/SI2
P36/TxD2/SO2
P37/ASCK2/SCK2
P40/AD0-P47/AD7
P50/AD8-P57/AD15
P60/A16-P63/A19
P70/ANI0-P77/ANI7
P80/ANI8-P87/ANI15
P90/RD
8
5
8
5-A
9
Input
I/O
Connect to VSS.
5-A
Input: Individually connect to VDD or VSS via resistor.
Output: Leave unconnected.
P91/LWR
P92/HWR
P93/ASTB
P94/WAIT
BWD
1
Input
Connect to VDD or VSS.
MODE, MODE1
RESET
Directly connect to VSS.
–
2
3
–
CLKOUT
Output Leave unconnected.
AVREF
–
Connect to VSS.
Connect to VDD.
AVSS
AVDD
Remark The circuit type numbers are serial in the 78K series but are not always so with some models (because some
models are not provided with particular circuits).
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. I/O Circuits of Pins
Type 1
Type 5-A
V
DD
Pull-up
Enable
V
DD
P-ch
V
DD
P-ch
Data
P-ch
IN
IN/OUT
N-ch
Output
Disable
N-ch
Input
Enable
Type 2
Type 8
VDD
Data
P-ch
N-ch
IN/OUT
IN
Output
Disable
Schmitt-trigger input with hysteresis characteristics
Type 3
Type 9
V
DD
Comparator
+
_
P-ch
N-ch
IN
P-ch
V
REF
OUT
(Threshold voltage)
N-ch
Input
enable
Type 5
V
DD
Data
P-ch
IN/OUT
Output
Disable
N-ch
Input
Enable
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD784054 can access a 1 M-byte memory space. The mapping of the internal data area (special function registers
and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after reset release,
and can only be used once.
The program after reset release must be as follows:
RSTVCT
CSEG
DW
AT 0
RSTSTRT
to
INITSEG
CSEG
BASE
RSTSTRT: LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
(1) When LOCATION 0H instruction is executed
The internal data area is mapped onto addresses 0FB00H to 0FFFFH.
Internal ROM is mapped onto addresses 0 to 07FFFH.
External memory is accessed in external memory extension mode.
(2) When LOCATION 0FH instruction is executed
The internal data area is mapped onto addresses FFB00H to FFFFFH.
Internal ROM is mapped onto addresses 0 to 07FFFH.
External memory is accessed in external memory extension mode.
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map
When LOCATION 0FH
Instruction Is Executed
Special Function Registers (SFRS)
Note 1
When LOCATION 0H
Instruction Is Executed
F F F F F H
F F F D F H
F F F D 0 H
F F F 0 0 H
FFFFFH
(256 Bytes)
0 FEFFH
FFEFFH
FFEFFH
Internal RAM
(1K Bytes)
FFB0 0H
FFAFFH
General-Purpose Registers
(128 Bytes)
Note 1
External Memory
Cannot Be Used
(1280 Bytes)
(960K Bytes)
0 FE8 0H
0 FE7 FH
FFE8 0H
FFE7 FH
FF 6 0 0H
FF 5 FFH
0 FE3 7H
FFE3 7H
FFE0 6H
Macro Service Control
Word Area (50 Bytes)
1 0 0 0 0H
0 FFFFH
0 FFDFH
0 FFD0H
0 FF 0 0H
0 FEFFH
Special Function Registers (SFRs)
0 FE0 6H
Note 1
Main RAM
Data Area (512 Bytes)
(256 Bytes)
0 FD0 0H
0 FCFFH
FFD0 0H
FFCFFH
Internal RAM
(1K Bytes)
Peripheral
RAM
0 FB0 0H
0 FAFFH
Program/Data Area
(512 Bytes)
External MemoryNote 1
(1013248 Bytes)
Cannot Be Used
(1280 Bytes)
0 FB0 0H
0 7 FFFH
FFB0 0H
0 F 6 0 0H
0 F 5 FFH
Note
2
Program/Data Area
(32K Bytes)
Note 1
External Memory
0 1 0 0 0H
0 0 FFFH
(30208 Bytes)
1 0 0 0 0H
0 FFFFH
CALLF Entry Area
(2K Bytes)
Note 2
0 0 8 0 0H
0 0 7 FFH
0 8 0 0 0H
0 7 FFFH
0 8 0 0 0H
0 7 FFFH
0 0 0 8 0H
0 0 0 7 FH
Internal ROM
(32K Bytes)
CALLT Table Area
Internal ROM
(32K Bytes)
(64 Bytes)
0 0 0 4 0H
0 0 0 3 FH
Vector Table Area
(64 Bytes)
0 0 0 0 0H
0 0 0 0 0H
0 0 0 0 0H
Notes 1. Accessed in the external memory extension mode.
2. Base area or entry area by reset or interrupt. The internal RAM is not reset.
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CHAPTER 3 CPU ARCHITECTURE
3.2 Internal ROM Area
The µPD784054 incorporates ROM which is used to store programs, table data, etc.
Table 3-1. Internal ROM Area
Address Space
Product Name
Internal ROM
Location 0H Instruction Location 0FH Instruction
00000H-07FFFH 00000H-07FFFH
µPD784054
32 K × 8 bits
The internal ROM can be accessed at high speed. Normally, fetches are performed at the same speed as external ROM,
but if the IFCH bit of the memory extension mode register (MM) is set (1), the high-speed fetch function is used and internal
ROM fetches are performed at high speed (2-byte fetch performed in 2 system clocks).
When the instruction execution cycle equal to an external ROM fetch is selected, wait insertion is performed by the wait
function, but when high-speed fetches are used, wait insertion is not performed for internal ROM.
RESET input sets the instruction execution cycle equal to the external ROM fetch cycle.
3.3 Base Area
The space from 0 to FFFFH comprises the base area. The base area is the object for the following uses:
•
•
•
•
•
•
•
•
Reset entry address
Interrupt entry address
CALLT instruction entry address
16-bit immediate addressing mode (with instruction address addressing)
16-bit direct addressing mode
16-bit register addressing mode (with instruction address addressing)
16-bit register indirect addressing mode
Short direct 16-bit memory indirect addressing mode
The vector table area, CALLT instruction table area and CALLF instruction entry area are allocated to the base area.
When the LOCATION 0H instruction is executed, the internal data area is located in the base area. Note that, in the
internal data area, program fetches cannot be performed from the internal high-speed RAM area or special function register
(SFR) area. Also, internal RAM area data should only be used after initialization has been performed.
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CHAPTER 3 CPU ARCHITECTURE
3.3.1 Vector table area
The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The vector table area stores the program
start addresses used when a branch is made as the result of RESET input or generation of an interrupt request. When context
switching is used by an interrupt, the number of the register bank to be switched to is stored here.
Any portion not used as the vector table can be used as program memory or data memory.
16-bit values can be written to the vector table. Therefore, branches can only be made within the base area.
Table 3-2. Vector Table
Vector Table Address
0003CH
Interrupt Cause
Operand error
0003EH
BRK
00000H
Reset (RESET input)
00002H
00004H
00006H
00008H
0000AH
0000CH
0000EH
00010H
00012H
00014H
00016H
00018H
0001AH
NMI
INTWDT
INTOV0
INTOV1
INTOV4
INTP0/INTCC00
INTP1/INTCC01
INTP2/INTCC02
INTP3/INTCC03
INTP4
INTP5
INTP6
INTCM10
0001CH
00026H
00028H
0002AH
0002CH
0002EH
00030H
00032H
00034H
00036H
INTCM11
INTCM40
INTCM41
INTSER
INTSR/INTCSI1
INTST
INTSER2
INTSR2/INTCSI2
INTST2
INTAD
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3.3.2 CALLT instruction table area
The 1-byte call instruction (CALLT) subroutine entry addresses can be stored in the 64-byte area from 00040H to 0007FH.
The CALLT instruction references this table, and branches to a base area address written in the table as a subroutine.
As the CALLT instruction is one byte in length, use of the CALLT instruction for subroutine calls written frequently throughout
the program enables the program object size to be reduced. The table can contain up to 32 subroutine entry addresses,
and therefore it is recommended that they be recorded in order of frequency.
If this area is not used as the CALLT instruction table, it can be used as ordinary program memory or data memory.
3.3.3 CALLF instruction entry area
A subroutine call can be made directly to the area from 00800H to 00FFFH with the 2-byte call instruction (CALLF).
As the CALLF instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of
the direct subroutine call CALL instruction (3 or 4 bytes).
Writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device.
If you wish to reduce the object size, writing an unconditional branch (BR) instruction in this area and locating the
subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more points.
In this case, only the 4 bytes of the BR instruction are occupied in the CALLF entry area, enabling the object size to be reduced
with a large number of subroutines.
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3.4 Internal Data Area
The internal data area consists of the internal RAM area and special function register area (refer to Figure 3-1).
The final address of the internal data area can be specified by means of the LOCATION instruction as either 0FFFFH
(when a LOCATION 0H instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed). Selection
of the addresses of the internal data area by means of the LOCATION instruction must be executed once immediately after
reset release, and once the selection is made, it cannot be changed. The program after reset release must be as shown
in the example below. If the internal data area and another area are allocated to the same addresses, the internal data
area is accessed and the other area cannot be accessed.
Example
RSTVCT
CSEG
DW
AT 0
RSTSTRT
to
INITSEG
CSEG
BASE
RSTSTRT: LOCATION 0H; or LOCATION 0FH
MOVG SP, #STKBGN
Caution When the LOCATION 0H instruction is executed, it is necessary to ensure that the program after reset
release does not overlap the internal data area. It is also necessary to make sure that the entry
addresses of the processing routines for non-maskable interrupts such as NMI do not overlap the
internal data area. Also, initialization must be performed for maskable interrupt entry areas, etc.,
before the internal data area is referenced.
3.4.1 Internal RAM area
The µPD784054 incorporates general-purpose static RAM.
This area is configured as follows:
Peripheral RAM (PRAM)
Internal RAM area
Internal high-speed RAM (IRAM)
Table 3-3. Internal RAM Area
Internal RAM
Product Name
µPD784054
Internal RAM Area
Peripheral RAM: PRAM
Internal High-Speed RAM: IRAM
1024 bytes
512 bytes
512 bytes
(0FB00H-0FEFFH)
(0FB00H-0FCFFH)
(0FD00H-0FEFFH)
Remark The addresses in the table are the values that apply when the LOCATION 0H instruction is executed. When
the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
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The internal RAM memory map is shown in Figure 3-2.
Figure 3-2. Internal RAM Memory Map
00FEFFH
00FE80H
General-Purpose
Register Area
Short Direct Addressing 1
Permissible Range
00FE37H
00FE06H
Macro Service
Control Word Area
Internal High-Speed RAM
00FE00H
00FDFFH
Short Direct Addressing 2
Permissible Range
00FD20H
00FD1FH
00FD00H
00FCFFH
Peripheral RAM
00FB00H
Remark The addresses in the figure are the values that apply when the LOCATION 0H instruction is executed. When
the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.
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(1) Internal high-speed RAM (IRAM)
The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode
for high-speed accesses can be used on FD20H to FEFFH in this area. There are two kinds of short direct addressing
mode, short direct addressing 1 and short direct addressing 2, according to the target address. The function is the
same in both of these addressing modes. With some instructions, the word length is shorter with short direct
addressing 2 than with short direct addressing 1. Refer to the 78K/IV Series User’s Manual - Instruction for details.
A program fetch cannot be performed from IRAM. If a program fetch is performed from an address onto which IRAM
is mapped, CPU inadvertent loop will result.
The following areas are reserved in IRAM.
•
•
•
General-purpose register area : FE80H to FEFFH
Macro service control word area : FE06H to FE37H
Macro service channel area
: FE00H to FEFFH (the address is specified by the macro service control word)
If the reserved function is not used in these areas, they can be used as ordinary data memory.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed. When
the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.
(2) Peripheral RAM (PRAM)
The peripheral RAM (PRAM) is used as ordinary program memory or data memory. When used as program memory,
the program must be written to the peripheral RAM beforehand by a program.
Program fetches from peripheral RAM are fast, with a 2-byte fetch being executed in 2 clocks.
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3.4.2 Special function register (SFR) area
The on-chip peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to 0FFFFH
(refer to Figure 3-1).
The area from 0FFD0H to 0FFDFH is mapped as an external SFR area, and allows externally connected peripheral I/
Os, etc., to be accessed in external memory extension mode (specified by the memory extension mode register (MM)).
Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an address
is accessed by mistake, the CPU may become deadlocked. A deadlock can only be released by reset
input.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed. When the
LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.
3.4.3 External SFR area
In µPD784054, the 16-byte area from 0FFD0H to 0FFDFH in the SFR area (when the LOCATION 0H is executed;
0FFFD0H to 0FFFDFH when the LOCATION 0FH instruction is executed) is mapped as an external SFR area. When the
external memory extension mode is externally connected peripheral I/Os, etc., can be accessed using the address bus or
address/data bus, etc.
As the external SFR area can be accessed by SFR addressing, peripheral I/O and similar operations can be performed
easily, the object size can be reduced, and macro service can be used.
Bus operations for accesses to the external SFR area are performed in the same way as for ordinary memory accesses.
3.5 External Memory Space
The external memory space is a memory space that can be accessed in accordance with the setting of the memory
extension mode register (MM). It can store programs, table data, etc., and can have peripheral I/O devices allocated to
it.
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3.6 Control Registers
Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP).
3.6.1 Program counter (PC)
This is a 20-bit binary counter that holds address information on the next program to be executed (refer to Figure 3-3).
Normally, the PC is incremented automatically by the number of bytes in the fetched instruction. When an instruction
associated with a branch is executed, the immediate data or register contents are set in the PC.
Upon RESET input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits
of the PC.
Figure 3-3. Format of Program Counter (PC)
19
0
PC
3.6.2 Program status word (PSW)
The program status word (PSW) is a 16-bit register comprising various flags that are set or reset according to the result
of instruction execution.
Read accesses and write accesses are performed in high-order 8-bit (PSWH) and low-order 8-bit (PSWL) units.
Individual flags can be manipulated by bit-manipulation instructions.
The contents of the PSW are automatically saved to the stack when a vectored interrupt request is acknowledged or
a BRK instruction is executed, and automatically restored when an RETI or RETB instruction is executed. When context
switching is used, the contents are automatically saved in RP3, and automatically restored when an RETCS or RETCSB
instruction is executed.
RESET input resets (0) all bits.
“0” must always be written to the bits written as “0” in Figure 3-4. The contents of bits written as “-” are undefined when
read.
Figure 3-4. Format of Program Status Word (PSW)
7
6
5
4
3
2
1
0
Symbol
PSWH
UF
RBS2
RBS1
RBS0
–
–
–
–
7
6
Z
5
4
3
2
1
0
0
PSWL
S
RSS
AC
IE
P/V
CY
The flags are described below.
(1) Carry flag (CY)
The carry flag records a carry or borrow resulting from an operation.
This flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit
accumulator when a bit-manipulation instruction is executed.
The status of the CY flag can be tested with a conditional branch instruction.
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(2) Parity/overflow flag (P/V)
The P/V flag performs the following two kinds of operation associated with execution of an operation instruction.
The status of the P/V flag can be tested with a conditional branch instruction.
•
Parity flag operation
Set (1) when the number of bits set (1) as the result of execution of a logical operation instruction, shift/rotate
instruction, or a CHKL or CHKLA instruction is even, and reset (0) if odd. When a 16-bit shift instruction is
executed, however, only the low-order 8 bits of the operation result are valid for the parity flag.
•
Overflow flag operation
Set (1) only when the numeric range expressed as a two’s complement is exceeded as the result of execution
of a arithmetic operation instruction, and reset (0) otherwise. More specifically, the value of this flag is the
exclusive OR of the carry into the MSB and the carry out of the MSB. For example, the two’s complement range
in an 8-bit arithmetic operation is 80H (–128) to 7FH (+127), and the flag is set (1) if the operation result is outside
this range, and reset (0) if within this range.
Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below.
When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225), and the
two’s complement limit is exceeded, with the result that the P/V flag is set (1). Expressed as a two’s
complement, E1H is -31.
78H (+120)
=
0111 1000
+) 69H (+105)
= +) 0110 1001
0
1110 0001
=
–31 P/V = 1
↑
CY
When the following two negative numbers are added together, the operation result is within the two’s
complement range, and therefore the P/V flag is reset (0).
FBH (–5)
=
1111 1011
+) F0H (–16)
= +) 1111 0000
1
1110 1011
=
–21 P/V = 0
↑
CY
(3) Interrupt request enable flag (IE)
This flag controls CPU interrupt request acknowledgment operations.
When “0”, interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be
acknowledged. All other interrupts are disabled.
When “1”, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the
interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts.
The IE flag is set (1) by execution of an EI instruction, and reset (0) by execution of a DI instruction or acknowledgment
of an interrupt.
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(4) Auxiliary carry flag (AC)
The AC flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset
(0) otherwise.
This flag is used when the ADJBA or ADJBS instruction is executed.
(5) Register set selection flag (RSS)
The RSS flag specifies the general-purpose registers that function as X, A, C and B, and the general-purpose register
pairs (16-bit) that function as AX and BC.
This flag is provided to maintain compatibility with the 78K/III series, and must be set to 0 except when using a 78K/
III series program.
(6) Zero flag (Z)
The Z flag records the fact that the result of an operation is “0”.
It is set (1) when the result of an operation is “0”, and reset (0) otherwise. The status of the Z flag can be tested
with a conditional branch instruction.
(7) Sign flag (S)
The S flag records the fact that the MSB is “1” as the result of an operation.
It is set (1) when the MSB is “1” as the result of an operation, and reset (0) otherwise. The status of the S flag can
be tested with a conditional branch instruction.
(8) Register bank selection flag (RBS0 to RBS2)
This is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (refer to Table
3-4).
It stores 3-bit information which indicates the register bank selected by execution of a SEL RBn instruction, etc.
Table 3-4. Register Bank Selection
RBS2
RBS1
RBS0
Specified Register Bank
Register bank 0
Register bank 1
Register bank 2
Register bank 3
Register bank 4
Register bank 5
Register bank 6
Register bank 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(9) User flag (UF)
This flag can be set and reset in the user program, and used for program control.
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3.6.3 Use of RSS bit
Basically, the RSS bit should be fixed at 0 at all times.
The following explanation refers to the case where a 78K/III series program is used, and the program used sets the RSS
bit to 1. This explanation can be skipped if the RSS bit is fixed at 0.
The RSS bit is provided to allow the functions of A (R1), X (R0), B (R3), C (R2), AX (RP0) and BC (RP1) to be used by
registers R4 to R7 (RP2, RP3) as well. Effective use of this bit enables efficient programs to be written in terms of program
size and program execution.
However, careless use can result in unforeseen problems. Therefore, the RSS bit should always be set to 0. The RSS
bit should only be set to 1 when a 78K/III series program is used.
Use of the RSS bit set to 0 in all programs will improve programming and debugging efficiency.
Even when using a program in which the RSS bit set to 1 is used, it is recommended that the program be amended if
possible so that it does not set the RSS bit to 1.
(1) RSS bit recommendations
•
Registers used by instructions for which the A, X, B, C and AX registers are directly entered in the operand column
of the operation list (refer to 19.2.)
•
•
Registers specified as implied by instructions that use the A, AX, B and C registers by means of implied addressing
Registers used in addressing by instructions that use the A, B and C registers in indexed addressing and based
indexed addressing
The registers used in these cases are switched as follows according to the RSS bit.
•
When RSS = 0
A→R1, X→R0, B→R3, C→R2, AX→RP0, BC→RP1
•
When RSS = 1
A→R5, X→R4, B→R7, C→R6, AX→RP2, BC→RP3
Registers used other than those mentioned above are always the same irrespective of the value of the RSS bit. With
the NEC Electronics assembler (RA78K4), the register operation code generated when the A, X, B, C, AX and BC
registers are described by those names is determined by the assembler RSS pseudo-instruction.
When the RSS bit is set or reset, an RSS pseudo-instruction must be written immediately before (or immediately
after) the relevant instruction (refer to example below).
<Program example>
•
When RSS is set to 0
RSS
0
; RSS pseudo-instruction
CLR1 PSWL.5
MOV B, A
; This code is equivalent to “MOV R3, R1”.
•
When RSS is set to 1
RSS
1
; RSS pseudo-instruction
SET1 PSWL.5
MOV B, A
; This code is equivalent to “MOV R7, R5”.
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(2) Operation code generation method with RA78K4
•
With the RA78K4, if there is an instruction with the same function as an instruction for which A or AX is directly
entered in the operand column of the instruction operation list, the operation code for which A or AX is directly
entered in the operand column is generated first.
Example The function is the same when B is used as r in a MOV A,r instruction, and when A is used as r and
B is used as r’ in a MOVr,r’ instruction, and the same code (MOV,A,B) is used in the assembler source
program. In this case, RA78K4 generates code equivalent to the MOV A, r instruction.
•
If A, X, B, C, AX or BC is written in an instruction for which r, r’, rp and rp’ are specified in the operand column,
the A, X, B, C, AX and BC instructions generate an operation code that specifies the following registers according
to the operand of the RA78K4 RSS pseudo-instruction.
Register
RSS = 0
R1
RSS = 1
R5
A
X
R0
R4
B
R3
R7
C
R2
R6
AX
BC
RP0
RP1
RP2
RP3
•
•
If R0 to R7 or RP0 to RP4 is written as r, r’, rp or rp’ in the operand column, an operation code in accordance
with that specification is output (an operation code for which A or AX is directly entered in the operand column
is not output.)
R1, R3, R2 or R5, R7, R6 cannot be used for registers A, B and C used in indexed addressing and based indexed
addressing.
(3) Operating precautions
Switching the RSS bit has the same effect as having two register sets. However, when writing a program, care must
be taken to ensure that the static program code and dynamic RSS bit changes at the time of program execution
always coincide.
Also, a program that sets RSS to 1 cannot be used by a program that uses the context switching function, and
therefore program usability is poor. Moreover, since different registers are used with the same name, program
readability is poor and debugging is difficult. Therefore, if it is necessary to set RSS to 1, these disadvantages must
be fully taken into consideration when writing a program.
A register not specified by the RSS bit can be accessed by writing its absolute name.
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3.6.4 Stack pointer (SP)
The stack pointer is a 24-bit register that holds the start address of the stack area (LIFO type: 00000H to FFFFFFH) (refer
to Figure 3-5). It is used to address the stack area when subroutine processing or interrupt processing is performed. Be
sure to write “0” in the high-order 4 bits.
The contents of the SP are decremented before a write to the stack area and incremented after a read from the stack
area (refer to Figures 3-6 and 3-7).
The SP is accessed by dedicated instructions.
The SP contents are undefined after RESET input, and therefore the SP must always be initialized by an initialization
program directly after reset release (before a subroutine call or interrupt acknowledgment).
Example SP initialization
MOVG SP, #0FEE0H;SP ← 0FEE0H (when used from FEDFH)
Figure 3-5. Format of Stack Pointer (SP)
23
0
SP
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Figure 3-6. Data Saved to Stack Area
PUSH sfr Instruction
Stack
PUSH sfrp Instruction
Stack
SP
SP
↓
↓
High-order Byte
Low-order Byte
SP– 1
SP– 1
SP– 2
↓
SP←SP– 1
SP←SP– 2
PUSH rg Instruction
Stack
PUSH PSW Instruction
Stack
SP
SP
↓
↓
PSWH
PSWH
7
4
to
Undefined
High-order Byte
Middle-order Byte
Low-order Byte
SP– 1
↓
SP– 2
SP– 1
↓
SP– 2
↓
PSWL
SP←SP– 2
SP– 3
SP←SP– 3
PUSH post, PUSHU post Instruction
(In case of PUSH AX, RP2, RP3)
Stack
CALL, CALLF, CALLT Instruction
Stack
Vectored Interrupt
Stack
SP
SP
SP
↓
↓
↓
PSWH
PSWH
7
4
to
PC19 to
PC16
PC19 to
PC16
R7
R6
R5
R4
A
SP– 1
↓
SP– 1
SP– 1
↓
Undefined
RP3
RP2
AX
↓
SP– 2
↓
SP– 2
↓
SP– 2
↓
PSWL
PC15 to PC8
PC7 to PC0
SP– 3
SP– 3
↓
SP– 3
↓
PC15 to PC8
PC7 to PC0
SP←SP– 3
SP– 4
SP– 4
↓
SP←SP– 4
SP– 5
↓
SP– 6
X
SP←SP– 6
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Figure 3-7. Data Restored from Stack Area
POP sfr Instruction
Stack
POP sfrp Instruction
Stack
SP←SP+1
SP←SP+2
SP+1
↑
SP
SP+1
↑
SP
High-order Byte
Low-order Byte
POP rg Instruction
Stack
POP PSW Instruction
Stack
SP←SP+2
SP←SP+3
↑
PSWH7 to
PSWH4
_Note
SP+1
↑
SP
SP+2
↑
HIgh-order Byte
Middle-order Byte
Low-order Byte
SP+1
↑
PSWL
SP
POP post, POPU post Instruction
(In case of POP AX, RP2, RP3)
Stack
RET Instruction
Stack
RETI, RETB Instruction
Stack
SP←SP+3
SP←SP+4
SP←SP+6
SP+5
PC19 to
PC16
PSWH7 to PC19 to
_Note
R7
R6
R5
R4
A
SP+2
↑
SP+3
↑
PSWH4
PC16
RP3
RP2
AX
↑
PSWL
PC15 to PC8
SP+1
↑
SP+2
↑
SP+4
↑
PC15 to PC8
PC7 to PC0
PC7 to PC0
SP
SP+1
↑
SP+3
↑
SP
SP+2
↑
SP+1
↑
SP
X
Note This 4-bit data is ignored.
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Cautions 1. With stack addressing, the entire 1 M-byte space can be accessed but a stack area cannot be
reserved in the SFR area or internal ROM area.
2. The stack pointer (SP) is undefined after RESET input. Moreover, non-maskable interrupts can
still be acknowledged when the SP is in an undefined state. An unanticipated operation may
therefore be performed if a non-maskable interrupt request is generated when the SP is in the
undefined state directly after reset release. To avoid this risk, the program after reset release must
be written as follows.
RSTVCT
CSEG AT
0
DW
RSTSTRT
to
INITSEG
CSEG BASE
RSTSTRT : LOCATION 0H ; or LOCATION 0FH
MOVG SP, #STKBGN
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3.7 General-Purpose Registers
3.7.1 Configuration
There are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a
16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an 8-bit
register for address extension, and used as 24-bit address specification registers.
General-purpose registers other than the V, U, T and W registers for address extension are mapped onto internal RAM.
These register sets are provided in 8 banks, and can be switched by means of software or the context switching function.
Upon RESET input, register bank 0 is selected. The register bank used during program execution can be checked by
reading the register bank selection flag (RBS0, RBS1, RBS2) in the PSW.
Figure 3-8. Format of General-Purpose Register
7
0 7
0
A(R1)
B (R3)
R5
X(R0)
C (R2)
R4
AX(RP0)
BC (RP1)
RP2
R7
R6
RP3
V
U
T
R9
R8
VP (RP4)
VVP (RG4)
UUP (RG5)
TDE (RG6)
WHL (RG7)
R11
R10
UP (RP5)
DE (RP6)
HL (RP7)
D (R13)
H (R15)
E (R12)
L (R14)
W
8 Banks
23
15
16
0
Remark Absolute names are shown in parentheses.
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Figure 3-9. General-Purpose Register Addresses
8-Bit Processing
16-Bit Processing
FEFFHNote
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
H(R15) (FH)
D(R13) (DH)
R11(BH)
L(R14) (EH)
E(R12) (CH)
R10 (AH)
R8 (8H)
HL(RP7) (EH)
DE(RP6) (CH)
UP(RP5) (AH)
VP(RP4) (8H)
RP3 (6H)
R9 (9H)
R7 (7H)
R6 (6H)
R5 (5H)
R4 (4H)
RP2 (4H)
B(R3) (3H)
A(R1) (1H)
C(R2) (2H)
X(R0) (0H)
BC(RP1) (2H)
AX(RP0) (0 H)
FE80HNote
7
0 7
0
15
0
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H
should be added to the address values shown above.
Caution R4, R5, R6, R7, RP2 and RP3 can be used as the X, A, C, B, AX and BC registers respectively by setting
the RSS bit of the PSW to 1, but this function should only be used when using a 78K/III series program.
Remark When the register bank is changed, and it is necessary to return to the original register bank, an SEL RBn
instruction should be executed after saving the PSW to the stack with a PUSH PSW instruction. When returning
to the original register bank, if the stack location does not change the POP PSW instruction should be used.
When the register bank is changed by a vectored interrupt processing program, etc., the PSW is automatically
saved to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so that,
if only one register bank is used in the interrupt service routine, only an SEL RBn instruction needs be executed,
and execution of a PUSH PSW and POP PSW instruction is not necessary.
Example When register bank 2 is specified
PUSH PSW
SEL RB2
Operations in register bank 2
POP PSW
Operations in original register bank
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3.7.2 Functions
In addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by
pairing two 8-bit registers. Also, four of the 16-bit registers can be combined with an 8-bit register for address extension
and manipulated in 24-bit units.
Each register can be used in a general-purpose way for temporary storage of an operation result and as the operand
of an inter-register operation instruction.
The area from 0FE80H to 0FEFFH (when the LOCATION 0H instruction is executed; 0FFE80H to 0FFEFFH when the
LOCATION 0FH instruction is executed) can be given an address specification and accessed as ordinary data memory
irrespective of whether or not it is used as the general-purpose register area.
As 8 register banks are provided in the 78K/IV series, efficient programs can be written by using different register banks
for normal processing and processing in the event of an interrupt.
The registers have the following specific functions.
A (R1):
• Register mainly used for 8-bit data transfers and operation processing. Can be used in combination with all
addressing modes for 8-bit data.
• Can also be used for bit data storage.
• Can be used as the register that stores the offset value in indexed addressing and based indexed addressing.
X (R0):
• Can be used for bit data storage.
AX (RP0):
• Register mainly used for 16-bit data transfers and operation processing. Can be used in combination with all
addressing modes for 16-bit data.
AXDE:
• Used for 32-bit data storage when a DIVUX, MACW or MACSW instruction is executed.
B (R3):
• Has a loop counter function, and can be used by the DBNZ instruction.
• Can be used as the register that stores the offset value in indexed addressing and based indexed addressing.
• Used as the MACW and MACSW instruction data pointer.
C (R2):
• Has a loop counter function, and can be used by the DBNZ instruction.
• Can be used as the register that stores the offset value in based indexed addressing.
• Used as the counter in a string instruction and the SACW instruction.
• Used as the MACW and MACSW instruction data pointer.
RP2:
• Used to save the low-order 16 bits of the program counter (PC) when context switching is used.
RP3:
• Used to save the high-order 4 bits of the program counter (PC) and the program status word (PSW) (excluding
bit 0 to bit 3 of PSWH) when context switching is used.
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CHAPTER 3 CPU ARCHITECTURE
VVP (RG4):
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing,
based addressing and based indexed addressing.
UUP (RG5):
• Has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means
of the PUSHU and POPU instructions.
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
DE (RP6), HL (RP7):
• Operate as the registers that store the offset value in indexed addressing and based indexed addressing.
TDE (RG6):
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
• Used as the pointer in a string instruction and the SACW instruction.
WHL (RG7):
• Register used mainly for 24-bit data transfers and operation processing.
• Has a pointer function, and operates as the register that specifies the base address in register indirect addressing
and based addressing.
• Used as the pointer in a string instruction and the SACW instruction.
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In addition to the function name that emphasizes the specific function of the register (X, A, C, B, E, D, L, H, AX, BC, VP,
UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be written by its absolute name (R0 to R15, RP0 to RP7, RG4
to RG7). The correspondence between these names is shown in Table 3-5.
Table 3-5. Correspondence between Function Names and Absolute Names
(a) 8-bit registers
(b) 16-bit registers
Function Name
Function Name
Absolute Name
Absolute Name
RSS = 0
RSS = 1Note
RSS = 0
RSS = 1Note
R0
X
A
C
B
RP0
RP1
RP2
RP3
RP4
RP5
RP6
RP7
AX
BC
R1
R2
AX
BC
VP
UP
DE
HL
R3
R4
X
A
C
B
VP
UP
DE
HL
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
(c) 24-bit registers
Absolute Name
RG4
Function Name
VVP
UUP
TDE
WHL
E
D
L
E
D
L
RG5
RG6
RG7
H
H
Note RSS should only be set to 1 when a 78K/III series program is used.
Remark R8 to R11 have no function name.
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CHAPTER 3 CPU ARCHITECTURE
3.8 Special Function Registers (SFRs)
These are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control
registers, etc. They are mapped onto the 256-byte space from 0FF00H to 0FFFFHNote
.
Note When the LOCATION 0H instruction is executed. When the LOCATION 0FH instruction is executed, the area is
FFF00H to FFFFFH.
Caution Addresses onto which SFRs are not assigned should not be accessed in this area. If such an address
is as accessed by mistake, the µPD784054 may become deadlocked. A deadlock can only be released
by reset input.
A list of special function registers (SFRs) is given in Table 3-6. The meaning of the items in the table is as explained
below.
• Symbol ................................... Symbol that indicates the incorporated SFR. This is a reserved word in the NEC
Electronics assembler (RA78K4). With the C compiler (CC78K4), this symbol can be
used as a sfr variable by means of a #pragma sfr command.
• R/W......................................... Indicates whether the corresponding SFR is read/write enabled.
R/W: Read/write enabled
R
: Read-only
: Write-only
W
• Bit Units for Manipulation ...... IndicatestheapplicablemanipulationbitunitswhenthecorrespondingSFRismanipulated.
A 16-bit-manipulable SFR can be written in the operand “sfrp”, and when specified by
an address, an even address is specified.
A bit-manipulable SFR can be written in a bit manipulation instruction.
• On Reset ................................ Indicates the status of the register after RESET input.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Registers (SFRs) List (1/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation On Reset
1 bit
8 bits
16 bits
0FF00H
0FF01H
0FF02H
0FF03H
0FF04H
0FF05H
0FF06H
0FF07H
0FF08H
0FF09H
0FF10H
0FF11H
0FF12H
0FF13H
0FF14H
0FF15H
0FF16H
0FF17H
0FF18H
0FF19H
0FF1AH
0FF1BH
0FF1CH
0FF1DH
0FF1EH
0FF1FH
0FF20H
0FF21H
0FF22H
0FF23H
0FF24H
0FF25H
0FF26H
0FF29H
0FF2FH
0FF30H
0FF31H
Port 0
P0
R/W
–
–
–
–
–
–
–
–
–
–
Undefined
Port 1
P1
P2
P3
P4
P5
P6
P7
P8
P9
TM0
Note 2
Port 2
Port 3
R/W
Port 4
Port 5
Port 6
Port 7
R
Port 8
Port 9
R/W
R
Timer register 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0000H
Capture/compare register 00
Capture/compare register 01
Capture/compare register 02
Capture/compare register 03
Timer register 1
CC00
CC01
CC02
CC03
TM1
R/W
Undefined
R
0000H
Compare register 10
CM10
CM11
R/W
Undefined
Compare register 11
Port 0 mode register
Port 1 mode register
Port 2 mode register
Port 3 mode register
Port 4 mode register
Port 5 mode register
Port 6 mode register
Port 9 mode register
Port read control register
Timer unit mode register 0
Timer mode control register
PM0
–
–
–
–
–
–
–
–
–
–
–
FFH
PM1
PM2Note 3
PM3
PM4
PM5
PM6
PM9
PRDC
TUM0
TMC
00H
Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH
instruction is executed.
2. Bit 0 of P2 can only be read. Bits 1 to 7 can be read/written.
3. Bit 0 of PM2 is fixed to “1” by hardware.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Registers (SFRs) List (2/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation On Reset
1 bit
8 bits
16 bits
0FF32H
0FF33H
0FF37H
0FF38H
0FF3AH
0FF3BH
0FF3CH
0FF3DH
0FF3EH
0FF3FH
0FF42H
0FF43H
0FF49H
0FF4EH
0FF4FH
0FF60H
0FF61H
0FF62H
0FF63H
0FF64H
0FF65H
0FF6EH
0FF70H
0FF71H
0FF71H
0FF72H
0FF73H
0FF73H
0FF74H
0FF75H
0FF75H
0FF76H
0FF77H
0FF77H
0FF78H
0FF79H
0FF79H
Timer output control register 0
Timer output control register 1
Timer mode control register 4
Prescaler mode register
TOC0
R/W
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00H
TOC1
TMC4
PRM
–
–
Prescaler mode register 4
PRM4
NPC
Noise protection control register
External interrupt mode register 0
External interrupt mode register 1
Interrupt valid edge flag register 1
Interrupt valid edge flag register 2
Port 2 mode control register
Port 3 mode control register
Port 9 mode control register
Pull-up resistor option register L
Pull-up resistor option register H
Timer register 4
INTM0
INTM1
IEF1
Undefined
00H
IEF2
PMC2Note 2
PMC3
PMC9
PUOL
PUOH
TM4
R
–
–
–
–
–
–
0000H
Compare register 40
Compare register 41
CM40
CM41
R/W
Undefined
A/D converter mode register
ADM
–
–
–
–
–
–
00H
A/D conversion result register 0
ADCR0
R
–
–
–
–
–
–
Undefined
A/D conversion result register 0H
A/D conversion result register 1
ADCR0H
ADCR1
–
–
A/D conversion result register 1H
A/D conversion result register 2
ADCR1H
ADCR2
–
–
A/D conversion result register 2H
A/D conversion result register 3
ADCR2H
ADCR3
–
–
A/D conversion result register 3H
A/D conversion result register 4
ADCR3H
ADCR4
–
–
A/D conversion result register 4H
ADCR4H
–
Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH
instruction is executed.
2. Bits 0, and 5 to 7 of PMC2 are fixed to “0” by hardware.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Registers (SFRs) List (3/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
ADCR5
R/W Bit Units for Manipulation On Reset
1 bit
–
8 bits
–
16 bits
0FF7AH
0FF7BH
0FF7BH
0FF7CH
0FF7DH
0FF7DH
0FF7EH
0FF7FH
0FF7FH
0FF84H
0FF85H
0FF88H
0FF89H
0FF8AH
0FF8BH
0FF8CH
A/D conversion result register 5
R
Undefined
A/D conversion result register 5H
A/D conversion result register 6
ADCR5H
ADCR6
–
–
–
–
–
–
A/D conversion result register 6H
A/D conversion result register 7
ADCR6H
ADCR7
–
–
A/D conversion result register 7H
ADCR7H
CSIM1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Clocked serial interface mode register 1
Clocked serial interface mode register 2
R/W
00H
CSIM2
Asynchronous serial interface mode register ASIM
Asynchronous serial interface mode register 2 ASIM2
Asynchronous serial interface status register ASIS
Asynchronous serial interface status register 2 ASIS2
R
Serial receive buffer: UART0
Serial transmit shift register: UART0
Serial shift register: IOE1
RXB
–
–
–
–
–
–
–
–
Undefined
TXS
W
R/W
R
SIO1
RXB2
TXS2
SIO2
BRGC
BRGC2
ISPR
IMC
0FF8DH
Serial receive buffer: UART2
Serial transmit shift register: UART2
Serial shift register: IOE2
W
R/W
0FF90H
0FF91H
0FFA8H
0FFAAH
0FFACH
0FFACH
0FFADH
0FFADH
0FFAEH
0FFAEH
0FFAFH
0FFAFH
0FFC0H
0FFC2H
0FFC4H
0FFC7H
Baud rate generator control register
Baud rate generator control register 2
In-service priority register
00H
R
Interrupt mode control register
Interrupt mask register 0L
R/W
80H
MK0L
MK0
FFH
Interrupt mask register 0
–
–
–
FFFFH
Interrupt mask register 0H
Interrupt mask register 1L
Interrupt mask register 1
MK0H
MK1L
MK1
–
–
FFH
FFFFH
Interrupt mask register 1H
MK1H
STBC
WDM
MM
–
–
–
–
–
FFH
30H
00H
20H
AAH
Standby control registerNote 2
–
–
Watchdog timer mode registerNote 2
Memory expansion mode register
Programmable wait control register 1
PWC1
–
Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH
instruction is executed.
2. These registers can be written only by using dedicated instructions MOV STBC, #byte and MOV WDM,
#byte, and cannot be written by any other instructions.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-6. Special Function Registers (SFRs) List (4/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation On Reset
1 bit
–
8 bits
–
16 bits
0FFC8H
0FFC9H
0FFCAH
0FFCBH
0FFCFH
0FFD0H-
0FFDFH
0FFE0H
0FFE1H
0FFE2H
0FFE3H
0FFE4H
0FFE5H
0FFE6H
0FFE7H
0FFE8H
0FFE9H
0FFEAH
0FFEBH
0FFF0H
0FFF1H
0FFF2H
0FFF3H
Programmable wait control register 2
Bus width specification register
PWC2
R/W
AAAAH
BW
–
–
–
Note 3
Oscillation stabilization time specification register OSTS
–
–
00H
External SFR area
–
Undefined
Interrupt control register (INTOV0)
Interrupt control register (INTOV1)
Interrupt control register (INTOV4)
Interrupt control register (INTP0)
Interrupt control register (INTP1)
Interrupt control register (INTP2)
Interrupt control register (INTP3)
Interrupt control register (INTP4)
Interrupt control register (INTP5)
Interrupt control register (INTP6)
Interrupt control register (INTCM10)
Interrupt control register (INTCM11)
Interrupt control register (INTCM40)
Interrupt control register (INTCM41)
Interrupt control register (INTSER)
Interrupt control register (INTSR)
Interrupt control register (INTCSI1)
Interrupt control register (INTST)
Interrupt control register (INTSER2)
Interrupt control register (INTSR2)
Interrupt control register (INTCSI2)
Interrupt control register (INTST2)
Interrupt control register (INTAD)
Internal memory size select registerNote 2
OVIC0
OVIC1
OVIC4
PIC0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
43H
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
CMIC10
CMIC11
CMIC40
CMIC41
SERIC
SRIC
CSIIC1
STIC
0FFF4H
0FFF5H
0FFF6H
SERIC2
SRIC2
CSIIC2
STIC2
ADIC
0FFF7H
0FFF8H
0FFFCH
IMS
–
CDH
Notes 1. When the LOCATION 0H instruction is executed. Add “F0000H” to this value when the LOCATION 0FH
instruction is executed.
2. Writing to IMS is valid only with the flash memory model (µPD78F4046). When writing to IMS with mask
ROM models (µPD784054), the value is not changed and remains the same as the value on reset.
3. The value of this register on reset differs depending on the setting of the BWD pin.
BWD = 0: 0000H
BWD = 1: 00FFH
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CHAPTER 3 CPU ARCHITECTURE
3.9 Cautions
(1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the
LOCATION 0H instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed).
(2) Special function registers (SFRs)
Addresses onto which SFRs are not assigned should not be accessed in the area 0FF00H to 0FFFFHNote
.
If such an address is accessed by mistake, the µPD784054 may become deadlocked. A deadlock can only
be released by reset input.
Note When the LOCATION 0H instruction is executed; FFF00H to FFFFFH when the LOCATION 0FH
instruction is executed.
(3) Stack pointer (SP) operation
With stack addressing, the entire 1 M-byte space can be accessed, but a stack area cannot be reserved in
the SFR area or internal ROM area.
(4) Stack pointer (SP) initialization
The SP is undefined after RESET input, while non-maskable interrupts can be acknowledged directly after
reset release. Therefore, an unforeseen operation may be performed if a non-maskable interrupt request is
generated while the SP is in the undefined state directly after reset release. To minimize this risk, the following
program should be coded without fail after reset release.
RSTVCT
CSEG AT
0
DW
to
RSTSTRT
INITSEG
CSEG BASE
RSTSTRT : LOCATION 0H ; or LOCATION 0FH
MOVG SP, #STKBGN
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CHAPTER 4 CLOCK GENERATOR
4.1 Configuration and Function
The clock generator generates and controls the internal system clock (CLK) supplied to the CPU and on-chip hardware. The
clock generator block diagram is shown in Figure 4-1.
Figure 4-1. Block Diagram of Clock Generator
Internal Bus
OSTS
STBC
HLT
EXTC
OSTS2 OSTS1 OSTS0
RESET
STP
RESET
Frequency Divider
X1
X2
Clock
Oscillator
fxx or f
x
fCLK
1/2
Internal System Clock (CLK)
Remark fXX : crystal/ceramic oscillation frequency
fX : external clock frequency
fCLK : internal system clock frequency
The clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the X1 and X2 pins. When
standby mode (STOP) is set, oscillation stops (refer to CHAPTER 16 STANDBY FUNCTION).
An external clock can also be input. In this case, input the clock signal to the X1 pin.
The processing of the X2 pin differs depending on the setting of the EXTC bit of the oscillation stabilization time specification
register (OSTS), as follows:
EXTC bit = 1: Input a clock in reverse phase to the clock input to X1 pin to the X2 pin.
EXTC bit = 0: Leave the X2 pin unconnected.
The frequency divider circuit divides the output (fXX or fX) of the clock oscillator by two, to generate an internal system clock
(fCLK).
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CHAPTER 4 CLOCK GENERATOR
Figure 4-2. Clock Oscillator External Circuitry
(a) Crystal/ceramic oscillation
µPD784054
V
SS
X1
X2
(b) External clock
• EXTC bit of OSTS = 1
• EXTC bit of OSTS = 0
µ
PD784054
µ
PD784054
X1
X1
X2
Open
X2
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.
2. No other signal lines should pass through the area enclosed by the dotted line.
Remark Use of crystal resonator and ceramic resonator
Generally speaking, the oscillation frequency of a crystal resonator is extremely stable. It is therefore ideal for
performing high-precision time management (in clocks, frequency meters, etc.).
A ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three
advantages: a fast oscillation start-up time, small size, and low price. It is therefore suitable for general use (when
high-precision time management is not required). In addition, there are products with a built-in capacitor, etc.,
which enable the number of parts and mounting area to be reduced.
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CHAPTER 4 CLOCK GENERATOR
4.2 Control Registers
4.2.1 Standby control register (STBC)
STBC is a register used to set the standby mode. Refer to CHAPTER 16 STANDBY FUNCTION for details of the standby
modes.
To prevent erroneous entry into standby mode due to an inadvertent program loop, the STBC register can only be written
tobyadedicated instruction. ThisinstructionistheMOVSTBC,#byteinstruction,andhasaspecialcodeconfiguration(4bytes).
A write is only performed if the 3rd and 4th bytes of the op code are mutual complements. If the 3rd and 4th bytes of the op code
are not mutual complements, a write is not performed, and an op error interrupt is generated. In this case, the return address
saved in the stack area is the address of the instruction which is the source of the error. The error source address can thus be
found from the return address saved on the stack area.
An endless loop will result if restore from an operand error is simply performed with an RETB instruction.
Since an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics
assembler RA78K4, only the correct dedicated instruction is generated when the MOV STBC, #byte instruction is written),
system initialization should be performed by the program.
Other write instructions (“MOV STBC, A”, “AND STBC, # byte”, “SET1 STBC.7”, etc.) are ignored, and no operation is
performed. That is, a write is not performed on the STBC, and an interrupt such as an operand error interrupt is not generated.
The STBC can be read at any time with a data transfer instruction.
RESET input sets the STBC register contents to 30H.
The format of the STBC is shown in Figure 4-3.
Figure 4-3. Standby Control Register (STBC) Format
Address : 0FFC0H
7
On reset : 30H
R/W
6
0
5
1
4
1
3
0
2
0
1
0
STBC
0
STP
HLT
STP
HLT
0
CPU Operating Mode Control
0
0
1
1
Normal mode
HALT mode
STOP mode
IDLE mode
1
0
1
Caution If the STOP mode is used when external clock input is used, the EXTC bit of the oscillation stabilization
timespecificationregister(OSTS)mustbeset(1)beforesettingtheSTOPmode. IftheSTOPmodeisused
when the EXTC bit of the OSTS is in the cleared (0) state when external clock input is used, the µPD784054
may be damaged or suffer reduced reliability.
When setting the EXTC bit to 1, be sure to input a clock in phase reverse to that of the clock input to the
X1 pin, to the X2 pin.
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CHAPTER 4 CLOCK GENERATOR
4.2.2 Oscillation stabilization time specification register (OSTS)
OSTS is a register used to specify the operation of the oscillator. The EXTC bit of the OSTS specifies whether a crystal/
ceramic resonator or an external clock is used. The STOP mode can be set during use of external clock input, only when the
EXTC bit is set (1).
The OSTS can be read/written to by an 8-bit manipulation instruction.
RESET input clears the OSTS register contents to 00H.
The format of the OSTS is shown in Figure 4-4.
Figure 4-4. Format of Oscillation Stabilization Time Specification Register (OSTS)
Address : 0FFCFH
On reset : 00H
R/W
7
6
0
5
0
4
0
3
0
2
1
0
OSTS EXTC
OSTS2 OSTS1 OSTS0
EXTC
0
Selects External Clock
Opens X2 pin when crystal/ceramic oscillation
is used or when external clock is used.
1
Inputs clock in reverse phase to clock input
X1 pin to X2 pin.
OSTS2 OSTS1 OSTS0 Selects oscillation stabilization time
(for details, refer to Figure 16-4).
Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit must be cleared (0). If the EXTC bit is set (1),
oscillation will stop.
2. IftheSTOPmodeisusedwithexternalclockinput, theEXTCbitmustbeset(1)beforesettingtheSTOP
mode. If the STOP mode is used when the EXTC bit is in the cleared (0) state, the µPD784054 may be
damaged or suffer reduced reliability.
3. When setting the EXTC bit to 1 during external clock input, be sure to input a clock in phase reverse
to that of the clock input to the X1 pin, to the X2 pin. When the EXTC bit is set to 1, the µPD784054
operates on only the clock input to the X2 pin.
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4.3 Clock Generator Operation
4.3.1 Clock oscillator
(1) When using crystal/ceramic oscillation
The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set
by the standby control register (STBC). Oscillation is resumed when the STOP mode is released.
(2) When using external clock
The clock oscillator supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.
The oscillator operates as follows when the EXTC bit of the oscillation stabilization time specification register (OSTS)
is set to 1.
•
•
The clock oscillator supplies the clock input to the X2 pin to the internal circuitry.
Thenecessarycircuitstopsoperatingduringthecrystal/ceramicoscillationoftheclockoscillator, toreducethepower
dissipation.
•
The STOP mode can be used even when the external clock is input.
Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit of the Oscillation stabilization time
specification register (OSTS) must be cleared (0). If the EXTC bit is set (1), oscillation will stop.
2. If the STOP mode is used with external clock input, the EXTC bit of the OSTS must be set (1) before
setting the STOP mode. If the STOP mode is used when the EXTC bit is in the cleared (0) state, not
only will the clock generator consumption current not be reduced, but the µPD784054 may also be
damaged or suffer reduced reliability.
3. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock
input to the X1 pin, to the X2 pin.
4.3.2 Frequency divider
The frequency divider divides the output from the clock oscillator by two, and supplies the result to the CPU and peripheral
hardware.
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4.4 Cautions
The following cautions apply to the clock generator.
4.4.1 When an external clock is input
(1) If the STOP mode is used with external clock input, the EXTC bit of the oscillation stabilization time specification register
(OSTS) must be set (1). If the STOP mode is used when the EXTC bit is in the cleared (0) state, the µPD784054 may
be damaged or suffer reduced reliability.
(2) When setting the EXTC bit of the OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the
X1 pin, to the X2 pin.
(3) When an external clock is input, this should be performed with a HCMOS device, or a device with the equivalent drive
capability.
(4) A signal should not be extracted from the X1 and X2 pins. If a signal is extracted, it should be extracted from point a in
Figure 4-5.
Figure 4-5. Signal Extraction with External Clock Input
µPD784054
a
X1
X2
(5) The wiring connecting the X1 pin to the X2 pin via an inverter, in particular, should be made as short as possible.
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4.4.2 When crystal/ceramic oscillation is used
(1) As the oscillator is a high-frequency analog circuit, considerable care is required.
The following points, in particular, require attention.
•
•
•
•
The wiring should be kept as short as possible.
No other signal lines should be crossed.
Avoid lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as the VSS pin. Do not ground to a
ground pattern carrying a high current.
•
A signal should not be taken from the oscillator.
If oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably,
either. Also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is
recommended.
Figure 4-6. Cautions on Resonator Connection
PD784054
µ
VSS
X1
X2
Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.
2. No other signal lines should pass through the area enclosed by the dotted line.
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Figure 4-7. Incorrect Example of Resonator Connection
(a) Wiring of connected circuits is too long
(b) Crossed signal lines
Pnm
µ
PD784054
µ
PD784054
VSS
X1
X2
VSS
X1
X2
(c) Wiring near high alternating current
(d) Current flowing through ground line of
oscillator
(Potentials at points A, B, and C fluctuate)
V
DD
µ
PD784054
VSS
X1
X2
Pnm
µ
PD784054
High
Alternating
Current
V
SS
X1
X2
A
B
C
High
Alternating
Current
(e) Signal extracted
µ
PD784054
V
SS
X1
X2
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(2) When the device is powered on, and when restoring from the STOP mode, sufficient time must be allowed for the
oscillation to stabilize. Generally speaking, the time required for oscillation stabilization is several milliseconds when a
crystal resonator is used, and several hundred microseconds when a ceramic resonator is used.
An adequate oscillation stabilization period should be secured by the following means:
<1> When powering-on
: RESET input (reset period)
<2> When returning from STOP mode :
(i) RESET input (reset period)
(ii) Time of the oscillation stabilization timer that automatically starts at the valid edge of NMI signal (set by the
oscillation stabilization time specification register (OSTS))
(3) The EXTC bit of the oscillation stabilization time specification register (OSTS) must be cleared (0). If the EXTC bit is
set (1), oscillation will stop.
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5.1 Digital Input/Output Port
The µPD784054 is provided with the ports shown in Figure 5-1, enabling various kinds of control to be performed. The
function of each port is shown in Table 5-1. For port 0, ports 4 to 6, and port 9, connection of an internal pull-up resistor
can be specified by software when used as input ports.
Figure 5-1. Port Configuration
P50
P00
Port 0
Port 1
P03
P10
P12
P20
Port 5
Port 6
P57
P60
P63
Port 2
Port 3
Port 4
P27
P30
P70-P77
8
Port 7
P37
P40
P80-P87
8
Port 8
P90
P94
Port 9
P47
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Table 5-1. Port Function
Port Name Pin Name
Function
Specification of Pull-Up Resistor by Software
Port 0
Port 1
Port 2
P00-P03
P10-P12
P20-P27
Can be set in input or output mode bit-wise.
All pins can be set in input mode
–
Can be set in input or output mode bit-wise
(however, P20 is input-only).
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
P30-P37
P40-P47
P50-P57
P60-P63
P70-P77
P80-P87
P90-P94
Can be set in input or output mode bit-wise.
All pins can be set in input mode
Input port
–
Can be set in input or output mode bit-wise.
All pins can be set in input mode
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5.2 Port 0
Port 0 is a 4-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 0 mode
register (PM0). Each pin incorporates a software programmable pull-up resistor.
When RESET is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are
undefined.
5.2.1 Hardware configuration
The port 0 hardware configuration is shown in Figure 5-2.
Figure 5-2. Block Diagram of Port 0
V
DD
WRPUO
WRPM0
WRP0
Pull-Up Resistor Option Register L
PUO0
Port 0 Mode Register
PM0n
Output Latch
P0n
P0n
n = 0-3
RDOUT
RDIN
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5.2.2 Input/output mode/control mode setting
The port 0 input/output mode is set by means of the port 0 mode register (PM0) as shown in Figure 5-3.
Figure 5-3. Format of Port 0 Mode Register (PM0)
Address : 0FF20H
7
On reset : FFH
R/W
6
1
5
1
4
1
3
2
1
0
PM0
1
PM03 PM02 PM01 PM00
PM0n
Specifies I/O Mode of P0n Pin (n = 0 to 3)
Output mode (output buffer on)
0
1
Input mode (output buffer off)
5.2.3 Operating status
Port 0 is an input/output port
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-4. Port Specified as Output Port
WRPORT
Output
Latch
P0n
n = 0-3
Internal
Bus
RDOUT
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(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes
can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is
stored in all output latches irrespective of the port input/output specification. However, since the output buffer of
a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input
is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output
latch of a bit specified as an input port cannot be loaded into an accumulator.
Figure 5-5. Port Specified as Input Port
WRPORT
Output
Latch
P0n
n = 0-3
Internal
Bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,
the contents of the output latch of pins specified as inputs will be undefined (excluding bits
manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits
which are switched between input and output.
Caution is also required when manipulating the port with other 8-bit manipulation instructions.
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5.2.4 Internal pull-up resistors
Port 0 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of
parts and the mounting area to be reduced.
Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO0 bit of the
pull-up resistor option register L (PUOL) and the port 0 mode register (PM0).
When PUO0 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the PM0 is valid when the PUO
bit is 1.
Figure 5-6. Pull-Up Resistor Option Register L (PUOL) Format
Address : 0FF4EH
7
On reset : 00H
R/W
6
5
4
3
0
2
0
1
0
0
PUOL
0
PUO6 PUO5 PUO4
PUO0
PUO6 Specifies Pull-up Resistor of Port 6
(refer to Figure 5-44).
PUO5 Specifies Pull-up Resistor of Port 5
(refer to Figure 5-38).
PUO4 Specifies Pull-up Resistor of Port 4
(refer to Figure 5-32).
PUO0
Specifies Pull-up Resistor of Port 0
Not used with port 0
Used with port 0
0
1
Remark When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.
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Figure 5-7. Pull-Up Resistor Specification (Port 0)
V
DD
P00
P01
P02
Input
Buffer
Internal
Bus
P03
(PUOL)
PUO0
Port 0 Mode Register
(PM0)
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5.3 Port 1
Port 1 is a 3-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 1 mode
register (PM1).
When RESET is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are
undefined.
5.3.1 Hardware configuration
The port 1 hardware configuration is shown in Figure 5-8.
Figure 5-8. Block Diagram of Port 1
WRPM1
WRP1
Port 1 Mode Register
PM1n
Output Latch
P1n
P1n
n = 0-2
RDOUT
RDIN
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5.3.2 Setting I/O mode/control mode
The input/output mode of port 1 is set by using the port 1 mode register (PM1) per pin, as shown in Figure 5-9.
Figure 5-9. Format of Port 1 Mode Register (PM1)
Address : 0FF21H
7
On reset : FFH
R/W
6
1
5
1
4
1
3
1
2
1
0
PM1
1
PM12 PM11 PM10
PM1n
Specifies I/O mode of P1n pin (n = 0 to 2)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
5.3.3 Operating status
Port 1 is an input/output port.
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-10. Port Specified as Output Port
WRPORT
Output
Latch
P1n
n = 0-2
Internal
Bus
RDOUT
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(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes
can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is
stored in all output latches irrespective of the port input/output specification. However, since the output buffer of
a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input
is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output
latch of a bit specified as an input port cannot be loaded into an accumulator.
Figure 5-11. Port Specified as Input Port
WRPORT
Output
Latch
P1n
n = 0-2
Internal
Bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port that has the I/O mode or port mode and
control mode, the contents of the output latch of the pin set in the input mode or control mode become
undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is
required when there are bits which are switched between input and output.
Caution is also required when manipulating the port with other 8-bit manipulation instructions.
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5.4 Port 2
Port 2 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 2 mode register (PM2) (however, P20 is input-only).
In addition to the input/output port function, port 2 also has a function to input control signals such as external interrupt
signals, and output the timer signal of timer 0 (refer to Table 5-2). P21 to P24 serve as the timer output pins of timer 0 if
so specified by port 2 mode control register (PMC2). The level of each pin of this port can always be read or tested regardless
of the multiplexed function.
All the eight pins are Schmitt-trigger input pins to prevent malfunctioning due to noise.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output
latch are undefined.
Table 5-2. Operation Mode of Port 2
(n = 0 to 7)
Mode
Port Mode
PMC2n = 0
Control Signal Output Mode
Set condition
PMC2n = 1
PM2n = ×
–
PM2n = 0
–
PM2n = 1
P20
P21
P22
P23
P24
P25
P26
P27
Input port/NMI inputNote
Input port/INTP0 input
Input port/INTP1 input
Input port/INTP2 input
Input port/INTP3 input
Input port/INTP4 input
Input port/INTP5 input
Input port/INTP6 input
Output port
TO00 output
TO01 output
TO02 output
TO03 output
–
Note The NMI input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled.
Remark ×: don’t care
(1) Port mode
(a) Function as port pin
Each port pin set in the port mode by the port 2 mode control register (PMC2) can be set in the input or output
mode in 1-bit units by the port 2 mode register (PM2) (however, P20 is fixed in the input mode).
(b) Function as control signal input pins
If PMC2n (n = 0 to 7) bit of PMC2 is “0” and if PM2n (n = 0-7) bit of PM2 is “1”, the pins of port 2 can be used
as the following control signal input pins.
(i) NMI (Non-maskable Interrupt)
This pin inputs an external non-maskable interrupt request. Whether the interrupt request is detected at
the rising or falling edge can be specified by using external interrupt mode register 0 (INTM0).
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(ii) INTP0 to INTP6 (Interrupt from Peripherals)
These pins input external interrupt requests. When the valid edge specified by external interrupt mode
registers (INTM0 and INTM1) is detected on the INTP0 to INTP6 pins, an interrupt occurs (refer toCHAPTER
13 EDGE DETECTION FUNCTION).
The INTP0 to INTP4 pins can also be used as external trigger input pins of each function, as follows:
•
•
•
•
•
INTP0 ... Capture trigger input pin of capture/compare register 00 (CC00) of timer 0
INTP1 ... Capture trigger input pin of capture/compare register 01 (CC01) of timer 0
INTP2 ... Capture trigger input pin of capture/compare register 02 (CC02) of timer 0
INTP3 ... Capture trigger input pin of capture/compare register 03 (CC03) of timer 0
INTP4 ... External trigger input pin of A/D converter
(2) Control signal output mode
The P21 to P24 pins can be used as the timer output pins (TO00 to TO03) of timer 0 in 1-bit units if so specified
by the port 2 mode control register (PMC2).
5.4.1 Hardware configuration
The port 2 hardware configuration is shown Figure 5-12 to 5-14.
Figure 5-12. Block Diagram of P20 (Port 2)
RDP20
Internal
Bus
P20
Edge
Detection
Circuit
NMI
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Figure 5-13. Block Diagram of P21 to P24 (Port 2)
WRPM2n
Port 2 Mode Register
PM2n
WRPMC2n
RDPMC2n
PMC2n
TO Output
WRP2n
RDP2n
Output Latch
P2n
n = 1-4
P2n
RDP2n
Edge
Detection
Circuit
INTPn-1
Figure 5-14. Block Diagram of P25 to P27 (Port 2)
WRPM2n
Port 2 Mode Register
PM2n
RDPM2n
WRP2n
Output Latch
P2n
(n = 5-7)
P2n
RDP2n
RDP2n
Edge
Detection
Circuit
INTPn-1
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5.4.2 Setting I/O mode/control mode
The input/output mode of P21 to P27 is set per pin by using the port 2 mode register (PM2), as shown in Figure 5-15.
P20 is input-only.
P21 to P24 also functions as timer output pins of timer 0, in addition to as input/output port pins. To use these pins as
timer output pins, set them in the control mode by using the port 2 mode control register (PMC2) as shown in Figure 5-16.
Figure 5-15. Format of Port 2 Mode Register (PM2)
Address : 0FF22H
7
On reset : FFH
R/W
6
5
4
3
2
1
0
1
PM2
PM27 PM26 PM25 PM24 PM23 PM22 PM21
PM2n Specifiesinput/outputmodeofP2npin(n=1to7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
Figure 5-16. Format of Port 2 Mode Control Register (PMC2)
Address : 0FF42H
7
On reset : 00H
R/W
6
0
5
0
4
3
2
1
0
0
PMC2
0
PMC24 PMC23 PMC22 PMC21
PMC24
Specifies Control Mode of P24 Pin
0
1
I/O port mode/INTP3 input mode
TO03 output mode
PMC23
Specifies Control Mode of P23 Pin
I/O port mode/INTP2 input mode
TO02 output mode
0
1
PMC22
Specifies Control Mode of P22 Pin
I/O port mode/INTP1 input mode
TO01 output mode
0
1
PMC21
Specifies Control Mode of P21 Pin
I/O port mode/INTP0 input mode
TO00 output mode
0
1
Caution Even when using the P21 to P27 pins in the output port mode or timer output mode, INTPn (n = 0 to
6) interrupt occurs depending on edge detection of the pin level. Therefore, mask the interrupt before
using the pins.
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5.4.3 Operating status
Port 2 is an I/O port (however, the P20 pin is input-only). The P21 to P24 pins can also be used as timer output pins
of timer 0.
(1) In output port mode
The output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction.
The contents of the output latch can be freely set by a logical operation instruction. Data that has been written to
the output latch is retained until new data is written to the output latchNote
.
Note Including when the other bits of the same port are manipulated by a bit manipulation instruction.
Figure 5-17. Port in Output Port Mode
WRPORT
Output
Latch
P2n
n = 1-7
RDOUT
(2) In input port mode
The level of a port pin can be loaded to the accumulator by using a transfer instruction. Even in this case, data can
be written to the output latch. Data transferred from the accumulator by a transfer instruction is stored to all the output
latches regardless of whether the input or output mode is specified. However, because the output buffer of a bit
(pin) set in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents
of the output latch are output to the port pin when the mode of the pin is changed from input to output). The contents
of the output latch of the pin set in the input port cannot be loaded to the accumulator.
Figure 5-18. Port in Input Port Mode
Note
WRPORT
Output
Latch
P2n
n = 0-7
RDIN
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Note P20 does not have the circuit enclosed by the dotted line in the above figure.
Caution Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses
a port in 8-bit units. If such an instruction is executed to manipulate a port with some pins set in
the input mode and the others in the control mode, the contents of the output latch are undefined
(except when a pin is manipulated by the SET1 or CLR1 instruction). Especially, care must be
exercised if the mode of some pins must be changed between input and output.
The same applies when manipulating the port by using the other 8-bit operation instructions.
(3) Pin in control mode
P21 to P24 can be used to output control signals in 1-bit units regardless of the setting of the port 2 mode register
(PM2), if the corresponding bit of the port 2 mode control register (PMC2) is set (1). When using each pin as a control
signal pin, the status of the control signal can be checked by executing an instruction that reads the port.
Figure 5-19. Port in Control Mode
P2n
n = 1-4
Control
(Output)
PM2n = 0
PM2n = 1
RD
Internal Bus
If the PM2n (n = 1 to 4) bit of PM2 is set (1), and if an instruction that reads the port is executed, the level of the
corresponding control signal pin can be read.
If the port read instruction is executed when the PM2n bit is reset (0), the status of the control signal in the µPD784054
can be read.
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5.5 Port 3
Port 3 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 3 mode
register (PM3).
In addition to its function as an input/output port, port 3 also has various dual-function control signal pin functions.
The operating mode can be specified bit-wise by means of the port 3 mode control register (PMC3), as shown in
Table 5-3. The pin level of all pins can always be read or tested regardless of the dual-function pin operation.
When RESET is input, port 3 is set as an input port (output high impedance state), and the output latch contents are
undefined.
Table 5-3. Port 3 Operating Modes
(n = 0 to 7)
Mode
Port Mode
PMC3n = 0
Control Signal Input/Output Mode
PMC3n = 1
Setting Condition
P30
P31
P32
P33
P34
P35
P36
P37
Input/output port
TO10 output
TO11 output
RxD/SI1 input
TxD/SO1 output
ASCK input/SCK1 input/output
RxD2/SI2 input
TxD2/SO2 output
ASCK2 input/SCK2 input/output
(a) Port mode
Each port specified as port mode by the port 3 mode control register (PMC3) can be specified as input/output bit-
wise by means of the port 3 mode register (PM3).
(b) Control signal input/output mode
Pins can be set as control pins bit-wise by setting the port 3 mode control register (PMC3).
(i) TO10, TO11 (Timer Output)
These are timer output pins of timer 1.
(ii) RxD, RxD2 (Receive Data)
These are serial data input pins of the asynchronous serial interface.
(iii) TxD, TxD2 (Transmit Data)
These are serial data output pins of the asynchronous serial interface.
(iv) SI1, SI2 (Serial Input)
These are serial data input pins of the 3-wire serial I/O.
(v) SO1, SO2 (Serial Output)
These are serial data output pins of the 3-wire serial I/O.
(vi) ASCK, ASCK2 (Asynchronous Serial Clock)
These are external baud rate clock input pins.
(vii) SCK1, SCK2 (Serial Clock)
These are serial clock I/O pins of the 3-wire serial I/O.
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5.5.1 Hardware configuration
The port 3 hardware configuration is shown in Figures 5-20 to 5-22.
Figure 5-20. Block Diagram of P30, P31, P33 and P36 (Port 3)
WRPM3n
Port 3 Mode Register
PM3n
WRPMC3n
RDPMC3n
PMC3n
TO, SO, TxD
Output
Internal
Bus
WRP3n
RDP3n
Selector
Output Latch
P3n
n = 0, 1, 3 and 6
P3n
RDP3n
Figure 5-21. Block Diagram of P32 and P35 (Port 3)
WRPM3n
Port 3 Mode Register
PM3n
WRPMC3n
PMC3n
RDPMC3n
WRP3n
RDP3n
Output Latch
P3n
P3n
n = 2, 5
Internal
Bus
SI, RxD Input
RDP3n
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Figure 5-22. Block Diagram of P34 and P37 (Port 3)
WRPM3n
Port 3 Mode Register
PM32
WRPMC3n
PMC32
External
SCK
RDPMC3n
SCK
Output
P3n
n = 4 and 7
WRP3n
RDP3n
Internal
Bus
Output Latch
P32
Selector
ASCK, SCK Input
RDP3n
5.5.2 Input/output mode/control mode setting
The port 3 input/output mode is set for each pin by means of the port 3 mode register (PM3) as shown in Figure 5-23.
In addition to their input/output port function, port 3 pins also have a dual function as various control signal pins, and
the control mode is specified by means of the port 3 mode control register (PMC3) as shown in Figure 5-24.
Figure 5-23. Format of Port 3 Mode Register (PM3)
Address : 0FF23H
7
On reset : FFH
R/W
6
5
4
3
2
1
0
PM3
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Specifies I/O Mode of P3n Pin (n = 0 to 7)
Output mode (output buffer ON)
0
1
Input mode (output buffer OFF)
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Figure 5-24. Format of Port 3 Mode Control Register (PMC3)
Address : 0FF43H
7
On reset : 00H
R/W
6
5
4
3
2
1
0
PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
PMC37
Specifies Control Mode of P37 Pin
I/O port mode
ASCK2/SCK2 I/O mode
0
1
PMC36
Specifies Control Mode of P36 Pin
0
1
I/O port mode
TxD2/SO2 output mode
PMC35
Specifies Control Mode of P35 Pin
0
1
I/O port mode
RxD2/SI2 input mode
PMC34
Specifies Control Mode of P34 Pin
0
1
I/O port mode
ASCK/SCK1 I/O mode
PMC33
Specifies Control Mode of P33 Pin
0
1
I/O port mode
TxD/SO1 output mode
PMC32
Specifies Control Mode of P32 Pin
0
1
I/O port mode
RxD/SI1 input mode
PMC31
Specifies Control Mode of P31 Pin
0
1
I/O port mode
TO11 output mode
PMC30
Specifies Control Mode of P30 Pin
0
1
I/O port mode
TO10 output mode
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5.5.3 Operating status
Port 3 is an input/output port, with a dual function as various control pins.
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-25. Port Specified as Output Port
WRPORT
Output
Latch
P3n
n = 0-7
Internal
Bus
RDOUT
(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes
can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is
stored in all output latches irrespective of the port input/output specification. However, since the output buffer of
a bit specified as an input port is high impedance, the data is not output to the port pin (when a bit specified as input
is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output
latch of a bit specified as an input port cannot be loaded into an accumulator.
Figure 5-26. Port Specified as Input Port
WRPORT
Output
Latch
P3n
n = 0-7
Internal
Bus
RDIN
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Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins
or port mode and control mode, the contents of the output latch of pins specified as inputs and
pins specified as control mode will be undefined (excluding bits manipulated with a SET1 or CLR1
instruction, etc.). Particular care is required when there are bits which are switched between input
and output.
Caution is also required when manipulating the port with other 8-bit manipulation instructions.
(3) When specified as control signal input/output
By setting (1) bits of the port 3 mode control register (PMC3), port 3 can be used as control signal input or output
bit-wise irrespective of the setting of the port 3 mode register (PM3). When a pin is used as a control signal, the
control signal status can be seen by executing a port read instruction.
Figure 5-27. Control Specification
Control (Input)
Control
P3n
(Output)
n = 0-7
PM3n = 0
PM3n = 1
RD
Internal Bus
(a) When port is control signal output
When PM3n (n = 0 to 7) bits of the port 3 mode register (PM3) is set (1), the control signal pin level can be read
by executing a port read instruction.
When PM3n bit is reset (0), the µPD784054 internal control signal status can be read by executing a port read
instruction.
(b) When port is control signal input
Only the port 3 mode register (PM3) is set (1), control signal pin levels can be read by executing a port read
instruction.
Caution Pins that function as input pins in the control mode may malfunction if the corresponding bits
of the port 3 mode control register (PMC3) are rewritten while the pins are operating.
Therefore, write PMC3 on initializing the system.
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5.6 Port 4
Port 4 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 4 mode
register (PM4). Each pin incorporates a software programmable pull-up resistor.
In addition to its function as input/output port, port 4 also functions as the low-order multiplexed address/data bus (AD0
to AD7) when external memory or I/Os are extended.
When RESET is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are
undefined.
5.6.1 Hardware configuration
The port 4 hardware configuration is shown in Figure 5-28.
Figure 5-28. Block Diagram of Port 4
WR
PUOPull-Up Resistor Option Register L
PUO4
RDPUO
V
DD
MM0-MM3
WRPM4n
Port 4 Mode Register
PM4n
Internal
Data
Bus
WRP4n
RDP4n
Output Latch
P4n
P4n
n = 0-7
Input/
Output
Control
Circuit
Internal
Address
Bus
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5.6.2 Input/output mode/control mode setting
The port 4 input/output mode is set for each pin by means of the port 4 mode register (PM4) as shown in Figure 5-29.
When port 4 is used as the address/data bus, it is set by means of the memory extension mode register (MM: Refer to Figure
15-1) as shown in Table 5-4.
Figure 5-29. Format of Port 4 Mode Register (PM4)
Address : 0FF24H
7
On reset : FFH
R/W
6
5
4
3
2
1
0
PM4
PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
PM4n
Specifies I/O Mode of P4n Pin (n = 0 to 7)
Output mode (output buffer ON)
0
1
Input mode (output buffer OFF)
Table 5-4. Operation Mode of Port 4
Bits of MM
Operation Mode
Remark
—
MM3 MM2 MM1 MM0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Port (P40-P47)
Address/data bus (AD0-AD7)
Setting prohibited when
external 16-bit bus specified
—
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5.6.3 Operating status
Port 4 is an input/output port, with a dual function as the address/data bus (AD0 to AD7).
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-30. Port Specified as Output Port
WRPORT
Output
Latch
P4n
n = 0-7
Internal
Bus
RDOUT
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(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes
can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is
stored in all output latches irrespective of the port input/output specification. However, since the output buffer of
a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input
is switched to an output port, the output latch contents are output to the port pin). Also, when a bit specified as an
input port, the output latch contents cannot be loaded into an accumulator.
Figure 5-31. Port Specified as Input Port
WRPORT
Output
Latch
P4n
n = 0-7
Internal
Bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,
the contents of the output latch of pins specified as inputs will be undefined (excluding bits
manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits
which are switched between input and output.
Caution is also required when manipulating the port with other 8-bit manipulation instructions.
(3) When used as address/data bus (AD0 to AD7)
Used automatically when an external access is performed.
Input/output instructions should not be executed on port 4.
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5.6.4 Internal pull-up resistors
Port 4 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of
parts and the mounting area to be reduced.
Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO4 bit of the
pull-up resistor option register L (PUOL) and the port 4 mode register (PM4).
When the PUO4 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the memory expansion mode
register (MM) and PM4 is valid.
Figure 5-32. Format of Pull-up Resistor Option Register L (PUOL)
Address : 0FF4EH
7
On reset : 00H
R/W
6
5
4
3
0
2
0
1
0
0
PUOL
0
PUO6 PUO5 PUO4
PUO0
PUO6 Specifies Pull-up Resistor of Port 6
(refer to Figure 5-44).
PUO5 Specifies Pull-up Resistor of Port 5
(refer to Figure 5-38).
PUO4
Specifies Pull-up Resistor of Port 4.
Not used with port 4
Used with port 4
0
1
PUO0 Specifies Pull-up Resistor of Port 0
(refer to Figure 5-6).
Caution When using port 4 as the address/data bus, be sure to reset the PUO4 bit to “0” to not connect the
internal pull-up resistor.
Remark When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.
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Figure 5-33. Pull-Up Resistor Specification (Port 4)
V
DD
P40
P41
P42
Input
Buffer
Internal
Bus
P46
P47
(PUOL)
PUO4
Port 4 Mode Register
(PM4)
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5.7 Port 5
Port 5 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 5 mode
register (PM5). Each pin incorporates a software programmable pull-up resistor.
In addition to as an I/O port, port 5 also functions as follows when an external memory or I/O is connected:
•
•
When external 8-bit bus is specified
As the high-order address bus (AD8 to AD15)
When external 16-bit bus is specified
As the high-order multiplexed address/data bus (AD8 to AD15)
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output
latch are undefined.
5.7.1 Hardware configuration
The port 5 hardware configuration is shown in Figure 5-34.
Figure 5-34. Block Diagram of Port 5
WR
PUOPull-Up Resistor Option Register L
PUO5
RDPUO
VDD
MM0-MM3
WRPM5n
Port 5 Mode Register
PM5n
Internal
Data
Bus
WRP5n
RDP5n
Output Latch
P5n
P5n
n = 0-7
Input/
Output
Control
Circuit
Internal
Address
Bus
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5.7.2 Input/output mode/control mode setting
The port 5 input/output mode is set for each pin by means of the port 5 mode register (PM5) as shown in Figure 5-35.
Whenport5pinscanbeusedasportoraddresspinsin2-bitunits, thesettingisperformedbymeansofthememoryextension
mode register (MM: Refer to Figure 15-1) as shown in Table 5-5.
Figure 5-35. Format of Port 5 Mode Register (PM5)
Address : 0FF25H
7
On reset : FFH
R/W
6
5
4
3
2
1
0
PM5
PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50
PM5n
Specifies I/O Mode of P5n Pin (n = 0 to 7)
Output mode (output buffer ON)
0
1
Input mode (output buffer OFF)
Table 5-5. Operation Mode of Port 5
Bits of MM
Operation mode
Remark
MM3 MM2 MM1 MM0 P50 P51 P52 P53 P54 P55 P56 P57
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Port (P50-P57)
—
Setting prohibited when external
16-bit bus specified. AD8-AD13
used as address bus
AD8 AD9 Port
AD8 AD9 AD10 AD11 Port
AD8 AD9 AD10 AD11 AD12 AD13 Port
AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
—
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5.7.3 Operating status
Port 5 is an input/output port, with a dual function as the address/data bus (AD8 to AD15).
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-36. Port Specified as Output Port
WRPORT
Output
Latch
P5n
n = 0-7
Internal
Bus
RDOUT
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(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can
be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored
in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit
specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is
switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch
of a bit specified as an input port cannot be loaded into an accumulator.
Figure 5-37. Port Specified as Input Port
WRPORT
Output
Latch
P5n
n = 0-7
Internal
Bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,
the contents of the output latch of pins specified as inputs will be undefined (excluding bits
manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits
which are switched between input and output.
Caution is also required when manipulating the port with other 8-bit operation instructions.
(3) When used as address/data bus (AD8 to AD15)
Port 5 is automatically used when an external address/data bus is accessed.
At this time, do not execute an I/O instruction to port 5.
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5.7.4 Internal pull-up resistors
Port 5 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of
parts and the mounting area to be reduced.
Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO5 bit of the
pull-up resistor option register L (PUOL) and the port 5 mode register (PM5).
When PUO5 bit is 1, the internal pull-up resistor of only the pin set in the input port by the memory expansion mode register
(MM) and PM5 is valid.
Figure 5-38. Format of Pull-Up Resistor Option Register L (PUOL)
Address : 0FF4EH
7
On reset : 00H
R/W
6
5
4
3
0
2
0
1
0
0
PUOL
0
PUO6 PUO5 PUO4
PUO0
PUO6 Specifies Pull-up Resistor of Port 6
(refer to Figure 5-44).
PUO5
Specifies Pull-up Resistor of Port 5.
Not used with port 5
Used with port 5
0
1
PUO4 Specifies Pull-up Resistor of Port 4
(refer to Figure 5-32).
PUO0 Specifies Pull-up Resistor of Port 0
(refer to Figure 5-6).
Caution When port 5 is used as the address/data bus, and “0” must be set in PUO5 bit so that internal pull-up
resistor connection is not performed.
Remark When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.
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Figure 5-39. Pull-Up Resistor Specification (Port 5)
VDD
P50
P51
P52
Input
Buffer
Internal
Bus
P56
P57
(PUOL)
PUO5
Port 5 Mode Register
(PM5)
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5.8 Port 6
Port 6 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using port
6 mode register (PM6). Each pin is provided with a software programmable pull-up resistor.
In addition to as an I/O port, this port also functions as the high-order address bus (A16 to A19) if so specified when an
external memory or I/O is connected.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output
latch are undefined.
5.8.1 Hardware configuration
The port 6 hardware configuration is shown in Figures 5-40.
Figure 5-40. Block Diagram of Port 6
WR
PUOPull-Up Resistor Option Register L
PUO6
RDPUO
V
DD
MM0-MM3
WRPM6n
Port 6 Mode Register
PM6n
Internal
Data
Bus
WRP6n
RDP6n
Output Latch
P6n
P6n
n = 0-3
Input/
Output
Control
Circuit
Internal
Address
Bus
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5.8.2 Setting of I/O mode/control mode
The input/output mode of port 6 is set in 1-bit units by using the port 6 mode register (PM6) as shown in Figure 5-41.
Port 6 can be used as port pins or address pins in 2-bit units. Whether it is used as port pins or address pins is specified
by using the memory extension mode register (MM: refer to Figure 15-1), as shown in Table 5-6.
Figure 5-41. Format of Port 6 Mode Register (PM6)
Address : 0FF26H
7
On reset : FFH
R/W
6
1
5
1
4
1
3
2
1
0
PM6
1
PM63 PM62 PM61 PM60
PM6n
Specifies I/O Mode of P6n Pin (n = 0 to 3)
Output mode (output buffer ON)
0
1
Input mode (output buffer OFF)
Table 5-6. Operation Mode of Port 6
Bits of MM
Operation mode
Remark
MM3 MM2 MM1 MM0 P60 P61 P62 P63
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Port (P60-P63)
—
Setting prohibited when external
16-bit bus specified.
—
A16 A17 Port
A16 A17 A18 A19
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5.8.3 Operating status
Port 6 is an input/output port, with a dual function as the address bus (A16 to A19).
(1) When set as an output port
The output latch is enabled, and data transfers between the output latch and accumulator are performed by means
of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once
data has been written to the output latch, it is retained until data is next written to the output latchNote
.
Note Including the case where another bit of the same port is manipulated by a bit manipulation instruction.
Figure 5-42. Port Specified as Output Port
WRPORT
Output
Latch
P6n
n = 0-3
Internal
Bus
RDOUT
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(2) When set as an input port
The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can
be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored
in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit
specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is
switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch
of a bit specified as an input port cannot be loaded into an accumulator.
Figure 5-43. Port Specified as Input Port
WRPORT
Output
Latch
P6n
n = 0-3
Internal
Bus
RDIN
Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.
Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,
or port mode and control mode, the contents of the output latch of pins specified as inputs or pins
specified as in the control mode will be undefined (excluding bits manipulated with a SET1 or CLR1
instruction, etc.). Particular care is required when there are bits which are switched between input
and output.
Caution is also required when manipulating the port with other 8-bit manipulation instructions.
(3) When used as address bus (A16 to A19)
Port 6 is automatically used for external access.
At this time, do not execute an I/O instruction to port 6.
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5.8.4 Internal pull-up resistors
Port 6 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of
parts and the mounting area to be reduced.
Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO6 bit of the
pull-up resistor option register L (PUOL) and the port 6 mode register (PM6).
The internal pull-up resistor of only the pin set in the input mode by PM6 is valid when the PUO6 bit is 1.
Even when port 6 is specified as the address bus, specifying the use of the internal pull-up resistor is valid. To not connect
the internal pull-up resistor, either set the output mode by using the port 6 mode register (PM6) (PM6n = 0: n = 0 to 3), or
reset PUO6 to 0.
Figure 5-44. Format of Pull-Up Resistor Option Register L (PUOL)
Address : 0FF4EH
7
On reset : 00H
R/W
6
5
4
3
0
2
0
1
0
0
PUOL
0
PUO6 PUO5 PUO4
PUO0
PUO6
Specifies Pull-up Resistor of Port 6
Not used with port 6
Used with port 6
0
1
PUO5 Specifies Pull-up Resistor of Port 5
(refer to Figure 5-38).
PUO4 Specifies Pull-up Resistor of Port 4
(refer to Figure 5-32).
PUO0 Specifies Pull-up Resistor of Port 0
(refer to Figure 5-6).
Remark When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.
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Figure 5-45. Pull-Up Resistor Specification (Port 6)
VDD
P60
P61
P62
P63
Input
Buffer
Internal
Bus
(PUOL)
PUO6
Port 6 Mode Register
(PM6)
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5.9 Port 7
Port 7 is an 8-bit input port. In addition to functioning as input port pins, its pins also function as an A/D converter analog
input (low-order 8 channels) pins (ANI0 to ANI7), and can always input analog signals. This port is set in the analog input
mode by using A/D converter mode register (ADM) (refer to Figure 11-3).
The level of each pin of this port can always be read or tested, regardless of the multiplexed function.
5.9.1 Hardware configuration
Figure 5-46 shows the hardware configuration of port 7.
Figure 5-46. Block Diagram of Port 7
RDIN
P7n
n = 0-7
A/D Converter
5.9.2 Notes
(1) Do not apply a voltage outside the range of AVSS to AVREF to the P70 to P77 pins when they are used as ANI0 to
ANI7. For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.
(2) If some pins of port 7 are used for analog input and the others are used for digital input, and if the digital input changes
at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is necessary, do
not use analog input and digital input simultaneously.
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5.10 Port 8
Port 8 is an 8-bit input port. In addition to functioning as input port pins, its pins also function as an A/D converter analog
input (high-order 8 channels) pins (ANI8 to ANI15), and can always input analog signals. This port is set in the analog input
mode by using A/D converter mode register (ADM) (refer to Figure 11-3).
The level of each pin of this port can always be read or tested, regardless of the multiplexed function.
5.10.1 Hardware configuration
Figure 5-47 shows the hardware configuration of port 8.
Figure 5-47. Block Diagram of Port 8
RDIN
P8n
n = 0-7
A/D Converter
5.10.2 Cautions
(1) Do not apply a voltage outside the range of AVSS to AVREF to the P80 to P87 pins when they are used as ANI8 to
ANI15. For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.
(2) If some pins of port 8 are used for analog input and the others are used for digital input, and if the digital input changes
at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is necessary, do
not use analog input and digital input simultaneously.
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5.11 Port 9
Port 9 is a 5-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using port
9 mode register (PM9). Each pin is provided with a software programmable pull-up resistor.
In addition to the I/O port function, port 9 also functions as control signal pins (refer to Table 5-7). P90 to P93 functions
as a read/write strobe signals and address strobe signal when an external memory or I/O is connected. P94 functions as
a wait signal input pin if so specified by port 9 mode control register (PMC9).
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output
latch are undefined.
Table 5-7. Operation Mode of Port 9
Pin Name
P90
Port Mode
I/O Port
Control Signal I/O Mode
RD
Manipulation to Use Port 9 as Control Pins
Specifying external memory expansion mode by
MM0 to MM3 bits of memory expansion
mode register (MM)
P91
LWR
HWR
ASTB
WAIT
P92
P93
P94
Setting of PMC94 bit of PMC9 to 1
Remark For details, refer to CHAPTER 15 LOCAL BUS INTERFACE FUNCTION.
(a) Port mode
Each port pin not set in the control mode can be set in the input or output mode in 1-bit units by using the port
9 mode register (PM9).
(b) Control signal I/O mode
(i) RD (Read Strobe)
This pin outputs a strobe signal to read an external memory. The operation of this pin is specified by the
memory expansion mode register (MM).
(ii) LWR, HWR (Low/High Write Strobe)
These pins output strobe signals to write an external memory. The operations of these pins are specified
by the memory expansion mode register (MM).
(iii) ASTB (Address Strobe)
This is a timing signal output pin to latch the address information output from the AD0 to AD15 pins to access
the external memory. The operation of this pin is specified by the memory expansion mode register (MM).
(iv) WAIT (Wait)
This pin inputs a wait signal. The operation of this pin is specified by the port 9 mode control register (PMC9).
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5.11.1 Hardware configuration
Figure 5-48 and Figure 5-49 show the hardware configuration of port 9.
Figure 5-48. Block Diagram of P90 to P93 (Port 9)
WRPUO
RDPUO
Pull-Up Resistor Option Register H
PUO9
WRPM9n
VDD
Port 9 Mode Register
PM9n
External Extension Mode
RD, LWR, HWR and ASTB signals
Internal
Bus
WRP9n
P9n
n = 0-3
Output Latch
P9n
Selector
RDOUT
RDIN
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Figure 5-49. Block Diagram of P94 (Port 9)
WRPUO
RDPUO
Pull-Up Resistor Option Register H
PUO9
WRPM94
Port 9 Mode Register
PM94
V
DD
WRPMC94
PMC94
RDPMC94
WRP94
RDP94
Output Latch
P94
P94
Wait Input
RDP94
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5.11.2 Setting of I/O mode/control mode
The input/output mode of port 9 is set per pin by using the port 9 mode register (PM9) as shown in Figure 5-50.
In addition to as an I/O port function, port 9 also has the following functions. P90 to P93 can be used as RD, LWR, HWR,
and ASTB pins, if so specified by the memory extension mode register (MM: refer to Figure 15-1), as shown in Table 5-
8. P94 can be used as a WAIT pin if so specified by the port 9 mode control register (PMC9) as shown in Figure 5-51.
Figure 5-50. Format of Port 9 Mode Register (PM9)
Address : 0FF29H
7
On reset : FFH
R/W
6
1
5
1
4
3
2
1
0
PM9
1
PM94 PM93 PM92 PM91 PM90
PM9n
Specifies I/O Mode of P9n Pin (n = 0 to 4)
Output mode (output buffer ON)
0
1
Input mode (output buffer OFF)
Table 5-8. Operation Mode of P90 to P93
Bits of MM
Operation mode
Remark
MM3 MM2 MM1 MM0 P90 P91 P92 P93
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Port (P90-P93)
—
RD LWR HWR ASTB Setting prohibited when external
16-bit bus specified.
—
Figure 5-51. Format of Port 9 Mode Control Register (PMC9)
Address : 0FF49H
7
On reset : 00H
R/W
6
0
5
0
4
3
0
2
0
1
0
0
0
PMC9
0
PMC94
PMC94
Specifies Control Mode of P94 Pin
0
1
I/O port mode
WAIT input mode
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5.11.3 Operating status
Port 9 is an input/output port and is multiplexed with control pins.
(1) In output port mode
The output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction.
The contents of the output latch can be freely set by a logical operation instruction. Data that has been written to
the output latch is retained until new data is written to the output latchNote
.
Note Including when the other bits of the same port are manipulated by a bit manipulation instruction.
Figure 5-52. Port in Output Port Mode
WRPORT
Output
Latch
P9n
n = 0-4
RDOUT
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(2) In input port mode
The level of a port pin can be loaded to the accumulator by using a transfer instruction. Even in this case, data can
be written to the output latch. Data transferred from the accumulator by a transfer instruction is stored to all the latches
regardless of whether the input or output mode is specified. However, because the output buffer of a bit (pin) set
in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents of the output
latch are output to the port pin when the mode of the pin is changed from input to output). The contents of the output
latch of the pin set in the input port cannot be loaded to the accumulator.
Figure 5-53. Port in Input Port Mode
WRPORT
Output
Latch
P9n
n = 0-4
RDIN
Caution Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port
in 8-bit units. If such an instruction is executed to manipulate a port with some pins set in the input
mode and the others in the control mode, the contents of the output latch are undefined (except when
a pin is manipulated by the SET1 or CLR1 instruction). Especially, care must be exercised if the mode
of some pins must be changed between input and output.
The same applies when manipulating the port by using the other 8-bit operation instructions.
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(3) Pin in control mode
•
P90 to P93
These pins are automatically used as the RD, LWR, HWR, and ASTB pins when the external memory or I/O is
accessed.
At this time, do not execute an I/O instruction to P90 to P93.
•
P94
This pin can be used as the WAIT pin, regardless of the setting of the port 9 mode register (PM9), if the PMC94
bit of the port 9 mode control register (PMC9) is set (1). When using P94 as the WAIT pin, the status of the WAIT
pin can be read by executing an instruction that reads the port only when the PM94 bit of PM9 is set (1).
Caution The pin that functions as an input pin in the control mode (P94) may malfunction if the PMC94
bit of the port 9 mode control register (PMC9) is rewritten while the pin is operating. Therefore,
write PMC9 on initializing the system.
5.11.4 Internal pull-up resistor
Port 9 is provided with pull-up resistors. When the port must be pulled up, the number of components and the mounting
area can be reduced by using these internal pull-up resistor.
Whether the internal pull-up resistors are used or not is specified per pin by using the PUO9 bit of the pull-up resistor
option register H (PUOH) and port 9 mode register (PM9).
When the PUO9 bit is 1, the internal pull-up resistor of only the pin specified as follows is valid.
•
•
P90 to P93 : Set in input port mode by memory extension mode register (MM) and PM9
P94 : Set in input mode by PM9
Even when P94 is specified as the WAIT pin, specifying its use as a pull-up resistor is valid. In order not to connect the
internal pull-up resistor, either specify the output mode by using PM9 (PM94 = 0), or reset (0) in PUO9.
Figure 5-54. Format of Pull-up Resistor Option register H (PUOH)
Address : 0FF4FH
7
On reset : 00H
R/W
6
0
5
0
4
0
3
0
2
0
1
0
0
PUOH
0
PUO9
PUO9
Specifies Pull-up Resistor of Port 9
0
1
Not used with port 9
Used with port 9
Caution When using P90 to P93 as the RD, LWR, HWR, and ASTB pins, be sure to reset the PUO9 bit to “0” in
order not to connect the internal pull-up resistor.
Remark Resetting PUOH to 00H is effective for decreasing the current consumption when the STOP mode is set.
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Figure 5-55. Specifying Pull-up Resistor (port 9)
VDD
P90
P91
P92
P93
P94
(PUOH)
PUO9
Port 9 Mode Register
(PM9)
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5.12 Port Output Data Check Function
The µPD784054 has a function to read the status of a port pin even in the output mode, to improve the reliability of the
system (pin access mode). Therefore, the output data and the actual pin status can be checked as necessary.
To read the pin status, set (1) bit 0 of the port read control register (PRDC), and then read the port.
When RESET is input, PRDC is reset to 00H.
Figure 5-56. Format of Port Read Control Register (PRDC)
Address : 0FF2FH
7
On reset : 00H
R/W
6
0
5
0
4
0
3
0
2
0
1
0
0
PRDC
0
PRDC0
PRDC0
Specifies Operation Mode
0
1
Normal mode
Pin access mode
Example To check the output data of ports 0 (P0), 4 (P4), and 5 (P5) by using the pin access mode.
TEST:
DI
; Disables interrupts
; Test data = 5AH
MOV
MOV
MOV
MOV
SET1
CMP
BNE
CMP
BNE
CMP
BNE
CLR1
EI
A, #5AH
P0, A
; Sets 5AH to output latch
P4, A
P5, A
PRDC.0
A, P0
; Sets pin access mode (sets PRDC)
; Compares pin level and output latch contents
; Error if unmatch
$ERR0
A, P4
$ERR4
A, P5
$ERR5
PRDC.0
; Returns to normal mode (resets PRDC)
; Enables interrupts
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Cautions 1. If a bit manipulation instruction is executed to manipulate the port, it is not executed normally in
the pin access mode (PRDC0 = 1). After checking the port, be sure to reset the mode to the normal
mode (PRDC0 = 0).
2. If an interrupt occurs in the pin access mode (PRDC0 = 1), a bit manipulation instruction may be
executed with this mode maintained, causing malfunctioning. Be sure to set the DI status before
checking the port.
Do not use a macro service that manipulates the port.
3. Occurrence of the non-maskable interrupt cannot be prevented. Take the following measures in
the program, depending on the system:
•
•
Do not manipulate the port in the non-maskable interrupt routine.
Save the level of PRDC.0 at the beginning of the non-maskable interrupt routine, and restore it on
returning execution from the interrupt routine.
If PRDC.0 is set (1), the switch enclosed by the dotted line in the figure below is connected to the pin, and the pin level
is read. If a bit manipulation instruction is executed in this status, the pin level is read and the bit is manipulated, affecting
the value of the output latch.
When PRDC.0 is reset (0), the normal operation is performed.
Figure 5-57. Concept of Control (in output port mode)
WRPORT
PXn
Output
Latch
RDOUT
PRDC.0 = 0
PRDC.0 = 1
Dedicated instructions (CHKL, CHKLA) that are used to frequently check the port status are available. These instructions
compare the pin status with the contents of the output latch (in port mode), or the pin status with the level of the internal
control output signal (in control mode) through exclusive OR.
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Example To check the pin status and the contents of the output latch using the CHKL or CHKLA instruction.
TEST:
SET1
CHKL
BNE
P0.3
P0
; Sets bit 3 of port 0
; Checks port 0
$ERR1
; Branches to error processing (ERR1) if contents of output
latch do not match pin status
.
.
.
ERR1:
CHKLA
BT
P0
; Checks defective bit
A.3, $BIT03
A.2, $BIT02
A.1, $BIT01
$BIT00
; Bit 3?
BT
; Bit 2?
BT
; Bit 1?
BR
; Bit 0 is defective if all other bits are valid.
Cautions 1. Use the CHKL or CHKLA instruction when the PRDC0 bit of the port read control register (PRDC)
is “0” (normal mode).
2. The result of comparison by the CHKL or CHKLA instruction always matches, regardless of
whether the pin set in the input port mode is set in the port mode or control mode. Because the
input level of the input-only pin is read when the CHKL or CHKLA instruction is executed, because
this pin does not have an output latch. In other words, executing the CHKL or CHKLA instruction
to the input-only pin is practically invalid, therefore, do not use the instruction to manipulate such
a pin.
3. To check the output level of a port with some of its bits set in the control output mode and others
in the port output mode, using the CHKL or CHKLA instruction, execute the instruction after
changing the input/output mode of the control output pin to the input mode (the output level of
the control output pin changes asynchronously and therefore cannot be checked by the CHKL or
CHKLA instruction).
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5.13 Cautions
(1) All the port pins go into a high-impedance state when the RESET signal is input (the internal pull-up resistor is also
disconnected from the pin).
If it is necessary to prevent a pin from going into a high-impedance state during RESET input, use an external circuit.
(2) Bits 1, 3, and 7 of the pull-up resistor option register L (PUOL) that specifies connection of the internal pull-up resistor,
and bits 0 and 2 to 7 of the pull-up resistor option register H (PUOH) are fixed to “0”. However, if “1” is written to
these bits, 1 can be read with an in-circuit emulator.
(3) The contents of the output latch are not initialized by RESET input. To use a port as an output port, be sure to initialize
the output latch before turning ON the output buffer. Unless the output buffer is initialized before the output buffer
is turned ON, unexpected data is output to the output port.
In the same way, when using a port as control pins, be sure to initialize the internal peripheral hardware, and then
set the port in the control mode.
(4) Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port in 8-bit units.
If such an instruction is executed to manipulate a port with some pins set in the input/output mode and the others
in the port mode and in the control mode, the contents of the output latch are undefined (except when a pin is
manipulated by the SET1 or CLR1 instruction). Especially, care must be exercised if the mode of some pins must
be changed between input and output.
The same applies when manipulating the port by using the other 8-bit operation instructions.
(5) Even when using the P21 to P27 pins in the output port mode or timer output mode, INTPn (n = 0 to 6) interrupt occurs
depending on the edge detection of the pin level. Mask the interrupt before using these pins.
(6) The pins used as input pins in the control mode (P32, P34, P35, P37, and P94) may malfunction if the corresponding
bit of the port n mode control register (PMCn: n = 3, 9) while these pins are operating. Therefore, write PMCn on
initializing the system.
(7) When using ports 4 and 5, and P90 to P93 as pins in the external memory extension mode, be sure to reset the
corresponding bits of the pull-up resistor option registers (PUOL, PUOH) to “0”, in order not to connect the internal
pull-up resistor.
(8) Do not apply a voltage outside the range of AVSS to AVREF to P70 to P77 and P80 to P87 used as ANI0 to ANI15.
For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.
(9) If some pins of ports 7 and 8 are used for analog input and the others are used for digital input, and if the digital
input changes at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is
necessary, do not use analog input and digital input simultaneously.
(10) A bit manipulation instruction executed to manipulate the port is not executed normally in the pin access mode
(PRDC0 of port read control register (PRDC) = 1). After checking the port, be sure to reset the mode to the normal
mode (PRDC0 = 0).
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(11) If an interrupt occurs in the pin access mode (PRDC0 of PRDC = 1), a bit manipulation instruction may be executed
with this mode maintained, causing malfunctioning. Be sure to set the DI status before checking the port.
Do not use a macro service that manipulates the port.
(12) Occurrence of the non-maskable interrupt cannot be prevented in the pin access mode (PRDC0 of PRDC = 1). Take
the following measures by using the program, depending on the system:
•
•
Do not manipulate the port in the non-maskable interrupt routine.
Save the level of PRDC.0 at the beginning of the non-maskable interrupt routine, and restore it on returning
execution from the interrupt routine.
(13) Use the CHKL or CHKLA instruction when the PRDC0 bit of PRDC is “0” (normal mode).
(14) The result of comparison by the CHKL or CHKLA instruction always matches, regardless of whether the pin set in
the input port mode is set in the port mode or control mode.
Because the input level of the input-only pin is read when the CHKL or CHKLA instruction is executed, because this
pin does not have an output latch. In other words, executing the CHKL or CHKLA instruction to the input-only pin
is practically invalid, and therefore, do not use the instruction to manipulate such a pin.
(15) To check the output level of a port with some of its bits set in the control output mode and others in the port output
mode, by using the CHKL or CHKLA instruction, execute the instruction after changing the input/output mode of the
control output pin to the input mode (the output level of the control output pin changes asynchronously and therefore
cannot be checked by the CHKL or CHKLA instruction).
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CHAPTER 6 OUTLINE OF TIMER
The µPD784054 incorporates three 16-bit time units.
These timer units can be used as eleven units of timers because the µPD784054 supports eleven interrupt requests.
Table 6-1. Operations of Timer
Name
Timer 0
Timer 1
Timer 4
Item
Operation mode
Function
Interval timer
Timer output
4 ch
4 ch
2 ch
2 ch
2 ch
—
Toggle output
—
Set/reset output
—
Overflow interrupt
Number of interrupt requests
5
3
3
142
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Figure 6-1. Block Diagram of Timer
Timer 0
Timer Register 0
fCLK
INTP0
INTP1
INTP2
INTP3
Prescaler
INTOV0
(TM0)
INTP0
INTP1
INTP2
INTP3
INTCC00
Edge
Detection
Match
Match
Match
Match
Capture/Compare
Register 00 (CC00)
TO00
TO01
TO02
TO03
Pulse
INTCC01 Output
Control
Capture/Compare
Register 01 (CC01)
Edge
Detection
INTCC02
Pulse
Capture/Compare
Register 02 (CC02)
Edge
Detection
Output
Control
INTCC03
Capture/Compare
Register 03 (CC03)
Edge
Detection
Prescaler: fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64
Timer 1
Clear
Control
Timer Register 1
(TM1)
f
CLK
Prescaler
INTOV1
INTCM10
Match
Compare Register 10
(CM10)
TO10
Pulse
Output
Control
Match
Compare Register 11
(CM11)
TO11
INTCM11
Prescaler: fCLK/8, fCLK/16, fCLK/32, fCLK/64, fCLK/128
Timer 4
Clear
Control
Timer Register 4
(TM4)
f
CLK
Prescaler
INTOV4
Match
Match
Compare Register 40
(CM40)
INTCM40
Compare Register 41
(CM41)
INTCM41
Prescaler: fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64
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CHAPTER 7 TIMER 0
7.1 Function
Timer 0 is a 16-bit free running timer.
Because this timer has four capture/compare registers and a toggle and set/reset timer output functions, it can be used
as an interval timer or to measure pulse width.
(1) Interval timer
When timer 0 is used as an interval timer, it generates an internal interrupt at interval set in advance.
Table 7-1. Interval Time of Timer 0
Minimum Interval TimeNote
4/fCLK (0.25 µs)
Maximum Interval Time
216 × 4/fCLK (16.4 ms)
216 × 8/fCLK (32.8 ms)
216 × 16/fCLK (65.5 ms)
216 × 32/fCLK (131 ms)
216 × 64/fCLK (262 ms)
Resolution
4/fCLK (0.25 µs)
8/fCLK (0.5 µs)
8/fCLK (0.5 µs)
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
( ): at fCLK = 16 MHz
Note The minimum interval time is limited by the data transfer processing time.
Consider the interrupt processing time or macro service processing time
used (refer to Table 14-11 Interrupt Acceptance Processing Time and
Table 14-12 Macro Service Processing Time).
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(2) Pulse width measurement
Timer 0 can be used to detect the pulse width of a signal input to an external interrupt request input pin (INTP0 to
INTP3).
Table 7-2. Pulse Width Measurement Range of Timer 0
Measurable Pulse WidthNote 1
Resolution
4/fCLK (0.25 µs)
8/fCLK (0.5 µs)
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
4/fCLK (0.25 µs)Note 2 – 216 × 4/fCLK (16.4 ms)
8/fCLK (0.5 µs)Note 2 – 216 × 8/fCLK (32.8 ms)
16/fCLK (1.0 µs)Note 2 – 216 × 16/fCLK (65.5 ms)
32/fCLK (2.0 µs)Note 2 – 216 × 32/fCLK (131 ms)
64/fCLK (4.0 µs)Note 2 – 216 × 64/fCLK (262 ms)
( ): at fCLK = 16 MHz
Notes 1. The minimum measurable pulse width changes depending on the sampling clock selected by the noise
protection control register (NPC). The minimum measurable pulse width is either of the values in the above
table and the table below, whichever greater.
Sampling Clock
Minimum Pulse Width
4/fCLK (0.25 µs)
fCLK
fCLK/4
16/fCLK (1.0 µs)
2. This value is limited by the data transfer processing time. Consider the interrupt processing time or macro
service processing time used (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-
12 Macro Service Processing Time).
7.2 Configuration
Timer 0 consists of the following registers:
•
•
Timer register (TM0) × 1
Capture/compare register (CC0n) × 4 (n = 0 to 3)
Figure 7-1 shows the block diagram of timer 0.
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Figure 7-1. Block Diagram of Timer 0
Internal Bus
External Interrupt
Mode Register 1
(INTM1)
External Interrupt Mode
Register 0
Timer Output Control
Register 0
1/8
1/8
16
16
16
16
1/8
(INTM0)
(TOC0)
Capture/Compare
Register 00 (CC00)
ES21 ES20 ES11 ES10 ES01 ES00
ES31 ES30
ENTO03 ALV03 ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00
16
16
Match
Output
INTP0
INTP1
INTP2
INTP3
Control
Circuit
TO00
Edge
Capture Trigger
Capture Trigger
16
Detection
Circuit
INTP0
INTP1
INTP2
INTP3
INTCC00
Capture/Compare
Register 01 (CC01)
Edge
Detection
Circuit
16
16
16
Output
Control
Circuit
Match
TO01
Edge
Detection
Circuit
INTCC01
Capture/Compare
Register 02 (CC02)
Edge
Detection
Circuit
16
16
Capture Trigger
Capture Trigger
Match
Output
Control
Circuit
TO02
16
INTCC02
Capture/Compare
Register 03 (CC03)
16
16
Output
Control
Circuit
Match
TO03
16
INTCC03
f
CLK/64
CLK/32
CLK/16
CLK/8
f
f
f
f
f
CLK
Overflow
Clear
INTOV0
Timer Register 0
(TM0)
CLK/4
RESET
Timer Mode
Control Register
(TMC)
Prescaler Mode
Register (PRM)
Timer Unit Mode
Register 0 (TUM0)
CE0
1/8
PRM02 PRM01 PRM00
TOM02 TOM00 CMS03 CMS02 CMS01 CMS00
1/8
1/8
16
Internal Bus
CHAPTER 7 TIMER 0
(1) Timer register 0 (TM0)
TM0 is a timer register that counts up the count clock specified by the prescaler mode register (PRM).
Counting of this timer register is enabled or disabled by the timer mode control register (TMC).
The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM0 is cleared
to 0000H and stops counting.
(2) Capture/compare registers (CC00 to CC03)
CC0n (n = 0 to 3) is a 16-bit register that can be used as a compare register to detect match between its value and
the count value of TM0 or as a capture register to capture the count value of TM0. Whether CC0n is used as a
compare register or capture register is specified by the timer unit mode register 0 (TUM0).
This register can be read or written by using a 16-bit manipulation instruction.
When RESET is input, the value of this register is undefined.
When the CE0 bit of the timer mode control register (TMC) is 0 and timer 0 is stopped, the capture operation is not
performed.
(a) As compare register
When used as a compare register, CC0n functions as a 16-bit register that holds the value determining the cycle
of the interval timer operation.
When the contents of CC0n matches with the contents of TM0, an interrupt request (INTCC0n: n = 0 to 3) and
a timer output control signal are generated.
(b) As capture register
When used as a capture register, CC0n functions as a 16-bit register that captures the contents of TM0 in
synchronization with the valid edge (capture trigger) input from an external interrupt input pin (INTPn: n = 0
to 3).
The contents of CC0n are retained until the next capture trigger is generated.
(3) Edge detection circuit
The edge detection circuit detects the valid edge of an external input.
It detects the valid edge of the INTP0 to INTP3 pin inputs, and generates an external interrupt request (INTP0 to
INTP3) and capture trigger. The valid edge is specified by the external interrupt mode registers (INTM0 and INTM1)
(for the details of INTM0 and INTM1, refer to Figures 13-1 and 13-2).
(4) Output control circuit
When the contents of CC0n (n = 0 to 3) and the contents of TM0 match, the timer output can be inverted. A square
wave can be output from a timer output pin (TO00 to TO03) if so specified by the timer output control register 0
(TOC0). The TO00 and TO02 pins can also output a set and reset signals if so specified by the timer unit mode
register 0 (TUM0).
The timer output can be enabled or disabled by TOC0. When the timer output is disabled, a fixed level is output
to the TO0n (n = 0 to 3) pin (the output level is fixed by TOC0).
(5) Prescaler
The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler
is selected by the selector, and TM0 performs the count operation by using this clock as a count clock.
(6) Selector
The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM0.
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7.3 Timer 0 Control Register
(1) Timer unit mode register 0 (TUM0)
TUM0 is a register that specifies the output mode of the timer output pins (TO00, TO02, and TO10) of timers 0 and
1, controls the clear operation of the timer register 1 (TM1), and specifies the operations of the capture/compare
registers (CC00 to CC03) of timer 0.
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
7-2 shows the format of TUM0.
When RESET is input, the value of TUM0 is cleared to 00H.
Figure 7-2. Format of Timer Unit Mode Register 0 (TUM0)
Address : 0FF30H
7
On reset : 00H
R/W
6
5
4
3
2
1
0
TUM0 TOM10 CLR1 TOM02 TOM00 CMS03 CMS02 CMS01 CMS00
TOM10 Specifies Output Mode of TO10 Pin
(refer to Figure 8-2).
CLR1 Controls Clear Operation of TM1
(refer to Figure 8-2).
TOM0n Specifies Output Mode of TO0n Pin (n = 0, 2)
0
1
Toggle output
Set/reset output
CMS0n
Specifies Operation of CC0n (n = 0 to 3)
Capture register
0
1
Compare register
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CHAPTER 7 TIMER 0
(2) Timer mode control register (TMC)
TMC is a register that controls the count operation of timer registers 0 and 1 (TM0 and TM1).
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
7-3 shows the format of TMC.
When RESET is input, the value of this register is cleared to 00H.
Figure 7-3. Format of Timer Mode Control Register (TMC)
Address : 0FF31H
7
On reset : 00H
R/W
6
0
5
0
4
0
3
2
0
1
0
0
0
TMC
CE1
CE0
CE1 Controls Count Operation of TM1
(refer to Figure 8-3).
CE0
0
Controls Count Operation of TM0
Clears and stops counting
Enables counting
1
(3) Timer output control register 0 (TOC0)
TOC0 is a register that specifies the operation and active level of the timer output pins (TO00 to TO03) of timer
0.
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
7-4 shows the format of TOC0.
When RESET is input, the value of this register is cleared to 00H.
Figure 7-4. Format of Timer Output Control Register 0 (TOC0)
Address : 0FF32H
7
On reset : 00H
R/W
6
5
4
3
2
1
0
TOC0 ENTO03 ALV03 ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00
ENTO0n Specifies Operation of TO0n Pin (n = 0 to 3)
0
1
Outputs ALV0n
Enables pulse output
ALV0n Specifies Active Level of TO0n Pin (n = 0 to 3)
0
1
Low level
High level
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CHAPTER 7 TIMER 0
(4) Prescaler mode register (PRM)
PRM is a register that specifies the count clock of timer registers 0 and 1 (TM0 and TM1).
This register can be read or written by using an 8-bit manipulation instruction. Figure 7-5 shows the format of PRM.
When RESET is input, the value of this register is cleared to 00H.
Figure 7-5. Format of Prescaler Mode Register (PRM)
Address : 0FF38H
7
On reset : 00H
R/W
6
5
4
3
0
2
1
0
PRM
0
PRM12 PRM11 PRM10
PRM02 PRM01 PRM00
PRM12 PRM11 PRM10 Specifies Count Clock of TM1
(refer to Figure 8-5).
(fCLK = 16 MHz )
PRM02 PRM01 PRM00 Specifies Count Clock of TM0.
Count Clock [Hz] Resolution [ s]
µ
0
0
0
1
1
0
0
1
0
1
0
fCLK/4
0.25
0.5
1.0
2.0
4.0
0
fCLK/8
0
0
fCLK/16
fCLK/32
fCLK/64
1
Other
Setting prohibited
Remark fCLK: internal system clock
7.4 Operation of Timer Register 0 (TM0)
7.4.1 Basic operation
Timer 0 counts up by using the count clock specified by the prescaler mode register (PRM).
Counting is enabled or disabled by the CE0 bit of the timer mode control register (TMC). When the CE0 bit is set (1)
by software, TM0 is set to 0001H at the first count clock, and starts counting up. When the CE0 bit is cleared (0) by software,
TM0 is immediately cleared to 0000H, and stops the capture operation and generation of the match signal.
If the CE0 bit is set (1) while it has been already set (1), TM0 is not cleared but continues counting.
If a count clock is input when TM0 reaches FFFFH, TM0 is cleared to 0000H, and an overflow interrupt (INTOV0) occurs,
but TM0 continues counting.
When RESET is input TM0 is cleared to 0000H and stops counting.
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Figure 7-6. Basic Operation of Timer Register 0 (TM0)
(a) Count started → count stopped → count started
Count Clock
TM0
101H
0H
1H
2H
3H
FFH 100H
0H
1H
2H
CE0
Count Started
CE0←1
Count Stopped
Count Started
CE0←1
CE0←0
(b) When “1” is written to the CE0 bit again after the count starts
Count Clock
TM0
CE0
0H
1H
2H
3H
4H
5H
6H
7H
Count Started
Rewritten
CE0←1
CE0←1
(c) Operation when TM0 = FFFFH
Count Clock
TM0
FFFFH
FFFEH
0H
1H
INTOV0
Interrupt Request
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7.4.2 Clear operation
Timer register 0 (TM0) is cleared by clearing (0) the CE0 bit of the timer mode control register (TMC). TM0 is cleared
as soon as the CE0 bit has been cleared (0).
Figure 7-7. Clear Operation of Timer Register 0 (TM0)
(a) Basic operation
Count Clock
n-1
n
0
TM0
CE0
(b) Restart before count clock input after clearance
Count Clock
0
n-1
n
1
2
3
TM0
CE0
If the CE0 bit is set (1) before this count clock, the count starts from 1 on the count clock.
(c) Restart after count clock input after clearance
Count Clock
n-1
n
0
0
1
2
TM0
CE0
If the CE0 bit is set (1) from this count clock onward, the count starts from 1
on the count clock after the CE0 bit is set (1).
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CHAPTER 7 TIMER 0
7.5 Operation of Capture/Compare Register
7.5.1 Compare operation
Timer 0 performs a compare operation by comparing the value set to a capture/compare register (CC00 to CC03)
specified as a compare register with the count value of a timer register 0 (TM0).
If the count value of TM0 matches with the value set in advance to CC0n (n = 0 to 3) as a result of counting by TM0,
the timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal
(INTCC0n: n = 0 to 3).
Table 7-3. Interrupt Request Signal from Compare Register (timer 0)
Compare Register
CC00
Interrupt Request Signal
INTCC00
CC01
CC02
INTCC01
INTCC02
CC03
INTCC03
Remark CC00 to CC03 are capture/compare regis-
ters. Whether these registers are used as
capture registers or compare registers is
specified by the timer unit mode register 0
(TUM0).
Timer 0 has four timer output pins (TO00 to TO03). Table 7-4 shows the operation mode of each of these pins (for details,
refer to 7.6 Basic Operation of Output Control Circuit).
Table 7-4. Operation Mode of Timer Output Pin (timer 0)
Timer Output Pin
TO00
Output Operation Mode
Specification of Operation Mode
Toggle
Toggle
Toggle
Toggle
Set/reset
—
TOM00 bit of TUM0
TO01
—
TOM02 bit of TUM0
—
TO02
Set/reset
—
TO03
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Figure 7-8. Compare Operation (timer 0)
FFFFH
FFFFH
TM0
Count Value
CC01 Value
CC01 Value
CC00 Value
CC00 Value
Match
0H
Match
Match
Match
Count Started
CE0←1
INTCC00
Interrupt Request
INTCC01
Interrupt Request
TO00 Pin Output
ENTO00 = 1
ALV00 = 1
Inactive Level
TO01 Pin Output
ENTO01 = 1
ALV01 = 0
Inactive Level
INTOV0
Interrupt Request
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CHAPTER 7 TIMER 0
7.5.2 Capture operation
In synchronization with an external trigger, timer 0 also performs a capture operation that captures and retains the count
value of timer register 0 (TM0) to a capture register.
As an external trigger, the valid edge detected from an external interrupt request input pin (INTP0 to INTP3) is used
(capture trigger). In synchronization with this capture trigger, the count value of TM0 is captured to a capture/compare
register (CC0n: n = 0 to 3) specified as a capture operation in synchronization with INTPn (n = 0 to 3).
The contents of CC00 to CC03 are retained until the following capture triggers each corresponding to CC00 to CC03
are generated.
Table 7-5. Capture Trigger Signal to Capture Register (timer 0)
Capture Register
CC00
Capture Trigger Signal
INTP0
CC01
CC02
CC03
INTP1
INTP2
INTP3
Remark CC00 to CC03 are capture/compare
registers. Whether these registers are used
as capture registers or compare registers is
specified by the timer unit mode register 0
(TUM0).
The valid edge of the capture trigger is specified by external interrupt mode registers (INTM0 and INTM1) If the capture
trigger is specified so that both the rising and falling edges are valid, the width of an externally input pulse can be measured.
If the capture trigger is generated with either of the edges specified as valid, the cycle of an input pulse can be measured.
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Figure 7-9. Capture Operation (timer 0)
FFFFH
TM0
Count Value
D4
D3
D2
D1
D7
D0
D6
D5
0H
Count Started
CE0←1
INTP1
Pin Input
INTP1
Interrupt Request
Capture Register
(CC01)
D1
D2
D4
D5
D7
INTP0
Pin Input
INTP0
Interrupt Request
Capture Register
(CC00)
D0
D3
D6
INTOV0
Interrupt Request
Remark Dn: TM0 count value (n = 0, 1, 2, ... )
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7.6 Basic Operation of Output Control Circuit
The output control circuit controls the levels of the timer output pins (TO00 to TO03) by using the match signals from
the compare registers (CC00 to CC03). The operation of the output control circuit is determined by the timer output control
register 0 (TOC0). Note that the TO01 and TO03 pin outputs can be used for toggle operation only. The TO00 and TO02
pin outputs can be used for toggle or set/reset operation, according to the specification by the timer unit mode register 0
(TUM0).
To output the signals TO00 to TO03 to pins, the corresponding pins must be set in the control mode by using the port
2 mode control register (PMC2).
Table 7-6. Toggle Signal of Timer Output Pin (timer 0)
Timer Output
Toggle Signal
INTCC00
TO00
TO01
TO02
TO03
INTCC01
INTCC02
INTCC03
Table 7-7. Set/Reset Signal of Timer Output Pin (timer 0)
Timer Output
Set Signal
INTCC00
Reset Signal
INTCC01
INTCC03
TO00
TO02
INTCC02
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Figure 7-10. Block Diagram of Timer Output Operation of Timer 0
T
Q
Q
TO00
TO01
TO02
TO03
INTCC00
INTCC01
S
R
T
T
Q
Q
INTCC02
INTCC03
S
R
Q
Q
T
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7.6.1 Basic operation
By setting (1) the ENTO0n (n = 0 to 3) bit of the timer output control register 0 (TOC0), a pulse can be output from the
TO0n (n = 0 to 3) pin.
Clearing (0) ENTO0n bit sets the TO0n to a fixed level. The fixed level is determined by the ALV0n (n = 0 to 3) bit of
the TOC0. The level is high when ALV0n bit is 0, and low when 1.
7.6.2 Toggle output
Toggle output is an operating mode in which the output level is inverted each time the compare register (CC0n: n = 0
to 3) value coincides with the timer register 0 (TM0) value. The output level of timer output (TO0n: n = 0 to 3) is inverted
by a match between CC0n and TM0.
When timer 0 is stopped by clearing (0) the CE0 bit of the timer mode control register (TMC), the output level at the time
it was stopped is retained as is.
Figure 7-11. Operation of Toggle Output
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
TM0
Count Value
CC01 Value
CC00 Value
CC01 Value
CC00 Value
CC01 Value
CC00 Value
CC01 Value
CC00 Value
0H
ENTO00
Instruction
Execution
Instruction
Execution
Instruction
Execution
TO00 Output
(ALV00 = 1)
ENTO01
Instruction
Execution
TO01 Output
(ALV01 = 0)
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Table 7-8. Toggle Output of TO00 to TO03 (fCLK = 16 MHz)
Count Clock
Minimum Pulse WidthNote
4/fCLK (0.25 µs)
Maximum Pulse Width
216 × 4/fCLK (16.4 ms)
216 × 8/fCLK (32.8 ms)
216 × 16/fCLK (65.5 ms)
216 × 32/fCLK (131 ms)
216 × 64/fCLK (262 ms)
fCLK/4
fCLK/8
8/fCLK (0.5 µs)
fCLK/16
fCLK/32
fCLK/64
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
Note The minimum interval time is limited by the data transfer processing time.
Consider the interrupt processing time or macro service processing time
used (refer to Table 14-11 Interrupt Acceptance Processing Time and
Table 14-12 Macro Service Processing Time).
7.6.3 Set/reset output
The set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare
register (CC0n: n = 0 to 3) matches with the value of timer register 0 (TM0).
If CC00 = CC01 and CC02 = CC03, interrupt requests are simultaneously generated, and timer outputs (TO00 and TO02)
are used as ALV00 and ALV02.
When timer 0 is stopped by clearing (0) the CE0 bit of the timer mode control register (TMC), the output level at which
the timer stops is retained as is.
Figure 7-12. Operation of Set/Reset Output (timer 0)
FFFFH
FFFFH
CC01
CC01
CC00
CC00
CC00
TM0
Count Value
0H
Count Started
CE0←1
INTCC00
Interrupt Request
INTCC01
Interrupt Request
TO00 Pin
ENTO00 ←1
ALV00 ←1
TOM00 ←1
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7.7 Examples of Use
7.7.1 Operation as interval timer
When timer register 0 (TM0) is made free-running and a fixed value is added to the compare register (CC0n: n = 0 to
3) in the interrupt processing routine, TM0 operates as an interval timer with the added fixed value as the cycle (refer to
Figure 7-13).
This interval timer can count within the range shown in Table 7-1 (internal system clock fCLK = 16 MHz).
Since TM0 has four capture compare registers, four interval timers with different cycles can be constructed.
Taking an example where compare register CC00 is used, the control register settings are shown in Figure 7-14, the
setting procedure in Figure 7-15, and the processing in the interrupt processing routine in Figure 7-16.
Figure 7-13. Timing of Interval Timer Operation
FFFFH
FFFFH
MOD(3n)
n
TM0
Count Value
MOD(2n)
0H
Timer Started
Compare Register
(CC00)
MOD(2n)
MOD(3n)
MOD(4n)
n
INTCC00
Interrupt Request
Rewritten by
Interrupt Program
Rewritten by
Interrupt Program
Rewritten by
Interrupt Program
Interval
Interval
Interval
Remark Interval time = n × x/fCLK
y ≤ n ≤ FFFFH
x = 4, 8, 16, 32, 64
y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro
service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12
Macro Service Processing Time).
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Figure 7-14. Set Contents of Control Register for Interval Timer Operation
(a) Prescaler mode register (PRM)
7
0
6
5
4
3
0
2
1
0
PRM
×
×
×
PRM02 PRM01 PRM00
Specifies count clock
(fCLK/x ; x = 4, 8, 16, 32, 64)
(b) Timer unit mode register 0 (TUM0)
7
6
5
4
0
3
2
1
0
1
TUM0
×
×
×
×
×
×
Specifies CC00 as compare register
Specifies TO00 for toggle output
× : don’t care
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Figure 7-15. Setting Procedure of Interval Timer Operation
Interval timer
Sets PRM
Sets count value to CC00
CC00←n
Sets TUM0
Count starts
; Sets bit 3 of TMC to 1
CE0←1
INTCC00 interrupt
Figure 7-16. Interrupt Request Processing of Interval Timer Operation
INTCC00 interrupt
Calculates timer value at which
interrupt is generated next time
CC00←CC00 + n
Other interrupt processing program
RETI
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7.7.2 Pulse width measurement operation
In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request
input pin (INTP0 to INTP3) is measured.
When the sampling clock is fCLK both the high-level and low-level widths of pulses input to the INTPn (n = 0 to 3) pin must
be at least 4 system clocks (0.25 µs: fCLK = 16 MHz); if shorter than this, the valid edge will not be detected and a capture
operation will not be performed.
When a pulse width is measured, the pulse width in a range shown in Table 7-2 can be measured (fCLK = 16 MHz). How
a pulse width is measured is explained below where the INTP3 pin is used as an external input pin.
As shown in Figure 7-17, the timer register 0 (TM0) value being counted is fetched into the capture register (CC03) in
synchronization with a valid edge (specified as both rising and falling edges) in the INTP3 pin input, and held there. The
pulse width is obtained from the product of the difference between the TM0 count value (Dn) fetched into and held in the
CC03 on detection of the nth valid edge and the count value (Dn-1) fetched and held on detection of valid edge n-1, and
the number of count clocks (x/fCLK; x = 4, 8, 16, 32, 64).
The control register settings are shown in Figure 7-18, the setting procedure in Figure 7-19, and the processing at interrupt
processing routine in Figure 7-20.
Figure 7-17. Timing of Pulse Width Measurement
FFFFH
FFFFH
TM0
Count Value
D1
D3
D2
D0
0H
Capture
Capture
Capture
Capture
Count Started
INTP3
External Input Signal
_
_
_
(10000H D1+
(D3 D2) × x/fCLK
(D1 D0) × x/fCLK
D2) × x/fCLK
INTP3
Interrupt Request
Capture Register
(CC03)
D0
D1
D2
D3
INTOV0
Interrupt Request
Remark Dn: TM0 count value (n = 0, 1, 2, ...)
x = 4, 8, 16, 32, 64
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Figure 7-18. Control Register Settings for Pulse Width Measurement
(a) Prescaler mode register (PRM)
7
0
6
5
4
3
0
2
1
0
PRM
×
×
×
PRM02 PRM01 PRM00
Specifies count clock
(fCLK/x ; x = 4, 8, 16, 32, 64)
(b) Timer unit mode register 0 (TUM0)
7
6
5
4
3
0
2
1
0
TUM0
×
×
×
×
×
×
×
Specifies CC03 as capture register
(c) External interrupt mode register 1 (INTM1)
7
6
5
4
3
2
1
0
1
INTM1
×
×
×
×
×
×
1
Specifies both rising & falling edges
as INTP3 input valid edges
× : Don’t care
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Figure 7-19. Pulse Width Measurement Setting Procedure
Pulse Width Measurement
Set PRM
Set TUM
; Specify both edges as
Set INTM1,
INTP3 input valid edges,
Set MK0L
release interrupt masking
Initialize capture value buffer memory
X0← 0
Start Count
CE0←1
; Set 1 to bit 3 of TMC
Enable Interrupt
INTP3 Interrupt
Figure 7-20. Interrupt Request Processing that Calculates Pulse Width
INTP3 Interrupt
Calculate pulse width
_
Y
n
= CC03
X
n
Store capture value in memory
X
n+1←CC03
RETI
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7.8 Cautions
(1) The prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer
4). If one of the timers sets the CE bit to “1”, the time base starts counting. If another timer sets the CE bit to “1”
while one timer is operating, the first count clock of the timer may be shortened because the time base has already
started counting.
For example, when using timer/counter 0 as an interval timer, the first interval time is shortened by up to 1 count
clock. The second and those that follow are at the specified interval.
Figure 7-21. Operation When Counting Is Started
Count Clock
TM0
CE0
0
1
2
3
4
Count Start Command (CE0 ← 1)
by Software
(2) While timer 0 is operating (while the CE0 bit of the timer mode control register (TMC) is set), malfunctioning may
occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence
in a contention the change in the hardware functions due to rewriting the register, or the change in the status because
of the function before rewriting.
Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following
registers.
•
•
•
Timer unit mode register 0 (TUM0)
Timer output control register 0 (TOC0)
Prescaler mode register (PRM)
(3) If the contents of the compare register (CC0n: n = 0 to 3) match with those of TM0 operation when an instruction
that stops timer register 0 (TM0) operation is executed, the counting operation of TM0 stops, but an interrupt request
is generated.
In order not to generate the interrupt when stopping the operation of TM0, mask the interrupt in advance by using
the interrupt mask register before stopping TM0.
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Example
Program that may generate interrupt request
Program that does not generate interrupt request
CLR1 CE0
OR MK0L, #78H
← Interrupt request
from timer 0
OR
MK0L, #78H
← Disables interrupt
from timer 0
CLR1 CE0
CLR1 PIF0
CLR1 PIF1
CLR1 PIF2
CLR1 PIF3
occurs between
these instructions
← Clears interrupt request
flag from timer 0
.
.
.
.
.
.
.
.
(4) Match between timer register 0 (TM0) and compare register (CC0n: n = 0 to 3) is detected only when TM0 is
.
incremented. Therefore, the interrupt request is not generated even if the same value as TM0 is written to CC0n,
and the timer output (TO0n: n = 0 to 3) does not change.
.
.
(5) When the compare register (CC00 to CC03) is set to 0000H, the compare operation is performed after counting by
.
TM0. Therefore, the match interrupt (INTCC00 to INTCC03) does not occur immediately after counting has been
started. If CC0n (n = 0 to 3) is set to 0000H, TM0 counts up to FFFFH, the timer overflows, and match interrupt
INTCC0n (n = 0 to 3) occurs.
Figure 7-22. Operation When Compare Register (CC00 to CC03) Is Set to 0000H
Count Clock
TM0 0H
1H
2H
FFFFH
0H
1H
2H
FFFFH
0H
1H
CE0
Count Started
CC0n
0000H
Match
Match
INTCC0n
Interrupt Occurred
Interrupt Occurred
Remark n = 0 to 3
(6) If the timer output is enabled when the active level is changed, the output level of pins may change momentarily.
To prevent this, enable the timer output after the active level have been changed.
(7) To change the active level specification (ALV0n bit (n = 0 to 3) of the timer output control register 0 (TOC0)), change
the active level specification after the timer output of the corresponding timer output pins has been disabled.
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8.1 Function
Timer 1 is a 16-bit timer.
In addition to a function as an interval timer, this timer has a toggle and set/reset function as timer output.
When used as an interval timer, timer 1 generates an internal interrupt at interval determined in advance.
Table 8-1. Interval Time of Timer 1
Minimum Interval Time
8/fCLK (0.5 µs)
Maximum Interval Time
216 × 8/fCLK (32.8 ms)
216 × 16/fCLK (65.5 ms)
216 × 32/fCLK (131 ms)
216 × 64/fCLK (262 ms)
216 × 128/fCLK (524 ms)
Resolution
8/fCLK (0.5 µs)
16/fCLK (1.0 µs)
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
128/fCLK (8.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
128/fCLK (8.0 µs)
( ): at fCLK = 16 MHz
8.2 Configuration
Timer 1 consists of the following registers:
•
•
Timer register (TM1) × 1
Compare register (CM1n) × 2 (n = 0, 1)
Figure 8-1 shows the block diagram of timer 1.
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Figure 8-1. Block Diagram of Timer 1
Internal Bus
Timer Output Control
Register 1 (TOC1)
1/8
1/8
Timer Unit Mode
Register 0
16
16
(TUM0)
TOM10 CLR1
ENTO11 ALV11 ENTO10 ALV10
Compare Register 10
(CM10)
16
Match
Output
Control
Circuit
TO10
16
Compare Register 11
(CM11)
INTCM10
16
Output
Control
Circuit
Match
TO11
16
INTCM11
Clear
RESET
fCLK/128
fCLK/64
fCLK/32
fCLK/16
fCLK/8
Overflow
Timer Register
(TM1)
fCLK
INTOV1
Prescaler Mode
Register (PRM)
Timer Mode Control
Register (TMC)
PRM12 PRM11 PRM10
1/8
CE1
1/8
16
Internal Bus
CHAPTER 8 TIMER 1
(1) Timer register 1 (TM1)
TM1 is a timer register that counts up the count clock specified by the prescaler mode register (PRM).
Counting of this timer register is enabled or disabled by the timer mode control register (TMC).
The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM1 is cleared
to 0000H and stops counting.
(2) Compare registers (CM10, CM11)
CM1n (n = 0, 1) is a 16-bit register that holds the value determining the cycle of the interval timer operation.
When the contents of CM1n matches with the contents of TM1, an interrupt request (INTCM1n: n = 0, 1) and a timer
output control signal are generated. The count value of TM1 can be cleared when its value matches with the contents
of CM10.
These compare registers can be read or written by using 16-bit manipulation instructions. When RESET is input,
their contents are undefined.
(3) Output control circuit
When the contents of CM1n (n = 0, 1) and the contents of TM1 match, the timer output can be inverted. A square
wave can be output from a timer output pin (TO10, TO11) if so specified by the timer output control register 1 (TOC1).
The TO10 pin can also output a set and reset signals if so specified by the timer unit mode register 0 (TUM0).
The timer output can be enabled or disabled by TOC1. When the timer output is disabled, a fixed level is output
to the TO1n (n = 0, 1) pin (the output level is fixed by TOC1).
(4) Prescaler
The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler
is selected by the selector, and TM1 performs the count operation by using this clock as a count clock.
(5) Selector
The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM1.
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8.3 Timer 1 Control Register
(1) Timer unit mode register 0 (TUM0)
TUM0 is a register that specifies the output mode of the timer output pins (TO00, TO02, and TO10) of timers 0 and
1, controls the clear operation of the timer register 1 (TM1), and specifies the operations of the capture/compare
registers (CC00 to CC03) of timer 0.
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
8-2 shows the format of TUM0.
When RESET is input, the value of TUM0 is cleared to 00H.
Figure 8-2. Format of Timer Unit Mode Register 0 (TUM0)
Address : 0FF30H
7
On reset : 00H
R/W
6
5
4
3
2
1
0
TUM0 TOM10 CLR1 TOM02 TOM00 CMS03 CMS02 CMS01 CMS00
Specifies Output Mode of TO10 Pin
Toggle output
TOM10
0
1
Set/reset output
Controls Clear Operation of TM1 by match with CM10
Disabled (free running mode)
CLR1
0
1
Enabled (interval timer mode)
TOM0n Specifies Output Mode of TO0n Pin (n = 0, 2)
(refer to Figure 7-2).
CMS0n Specifies Operation of CC0n (n = 0 to 3)
(refer to Figure 7-2).
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(2) Timer mode control register (TMC)
TMC is a register that controls the count operation of timer registers 0 and 1 (TM0 and TM1).
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
8-3 shows the format of TMC.
When RESET is input, the value of this register is cleared to 00H.
Figure 8-3. Format of Timer Mode Control Register (TMC)
Address : 0FF31H
7
On reset : 00H
R/W
6
0
5
0
4
0
3
2
0
1
0
0
0
TMC
CE1
CE0
CE1
0
Controls Count Operation of TM1
Clears and stops counting
Enables counting operation
1
CE0 Controls Count Operation of TM0
(refer to Figure 7-3).
(3) Timer output control register 1 (TOC1)
TOC1 is a register that specifies the operation and active level of the timer output pins (TO10, TO11) of timer 1.
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
8-4 shows the format of TOC1.
When RESET is input, the value of this register is cleared to 00H.
Figure 8-4. Format of Timer Output Control Register 1 (TOC1)
Address : 0FF33H
7
On reset : 00H
R/W
6
0
5
0
4
0
3
2
1
0
TOC1
0
ENTO11 ALV11 ENTO10 ALV10
ENTO1n
Specifies Operation of TO1n Pin (n = 0, 1)
Outputs ALV1n
0
1
Enables pulse output
ALV1
n
Specifies Active Level of TO1n Pin (n = 0, 1)
0
1
Low level
High level
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(4) Prescaler mode register (PRM)
PRM is a register that specifies the count clock of timer registers 0 and 1 (TM0, TM1).
This register can be read or written by using an 8-bit manipulation instruction. Figure 8-5 shows the format of PRM.
When RESET is input, the value of this register is cleared to 00H.
Figure 8-5. Format of Prescaler Mode Register (PRM)
Address : 0FF38H
7
On reset : 00H
R/W
6
5
4
3
0
2
1
0
PRM
0
PRM12 PRM11 PRM10
PRM02 PRM01 PRM00
(fCLK = 16 MHz)
PRM12 PRM11 PRM10 Specifies Count Clock of TM1
µ
Count Clock [Hz] Resolution [ s]
0
0
0
1
1
0
0
1
0
1
0
f
f
f
f
f
CLK/8
0.5
1.0
2.0
4.0
8.0
0
CLK/16
CLK/32
CLK/64
CLK/128
0
0
1
Other
Setting prohibited
PRM02 PRM01 PRM00 Specifies Count Clock of TM0
(refer to Figure 7-5).
Remark fCLK: internal system clock
8.4 Operation of Timer Register 1 (TM1)
8.4.1 Basic operation
Timer 1 counts up by using the count clock specified by the prescaler mode register (PRM).
Counting is enabled or disabled by the CE1 bit of the timer mode control register (TMC). When the CE1 bit is set (1)
by software, TM1 is set to 0001H at the first count clock, and starts counting up. When the CE1 bit is cleared (0) by software,
TM1 is immediately cleared to 0000H, and stops the generation of the match signal.
If the CE1 bit is set (1) while it has been already set (1), TM1 is not cleared but continues counting.
If a count clock is input when TM1 reaches FFFFH, TM1 is cleared to 0000H, and an overflow interrupt (INTOV1) occurs.
When RESET is input, TM1 is cleared to 0000H and stops counting.
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Figure 8-6. Basic Operation of Timer Register 1 (TM1)
(a) Count started → count stopped → count started
Count Clock
TM1
CE1
101H
0H
1H
2H
3H
FFH 100H
0H
1H
2H
Count Started
CE1←1
Count Stopped
Count Started
CE1←1
CE1←0
(b) When “1” is written to the CE1 bit again after the count starts
Count Clock
0H
1H
2H
3H
4H
5H
6H
7H
TM1
CE1
Count Started
Rewritten
CE1←1
CE1←1
(c) Operation when TM1 = FFFFH
Count Clock
FFFEH FFFFH 0H
1H
TM1
INTOV1
Interrupt Request
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8.4.2 Clear operation
(1) Clear operation after match with compare register
Timer register 1 (TM1) can be cleared automatically after a match with the compare register (CM10). When a
clearance source arises, TM1 is cleared to 000H on the next count clock. Therefore, even if a clearance source arises,
the value at the point at which the clearance source arose is retained until the next count clock arrives.
Figure 8-7. TM1 Clear Operation by Match with Compare Register (CM10)
Count Clock
_
TM1
n 1
n
0
1
Compare Register
(CM10)
n
TM1 and CM10 Match
Cleared Here
(2) Clear operation by CE1 bit of timer mode control register (TMC)
Timer register 1 (TM1) is also cleared when the CE1 bit of TMC is cleared (0) by software. The clear operation is
performed immediately after the clearance (0) of the CE1 bit.
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Figure 8-8. TM1 Clear Operation When CE1 Bit is Cleared (0)
(a) Basic operation
Count Clock
_
n
n 1
0
TM1
CE1
(b) Restart before count clock is input after clearance
Count Clock
_
n 1
n
0
1
2
3
TM1
CE1
If the CE1 bit is set (1) before this count clock, this count clock starts counting from 1.
(c) Restart after count clock is input after clearance
Count Clock
_
n 1
n
0
0
1
2
TM1
CE1
If the CE1 bit is set (1) from this count clock onward, the count clock starts counting
from 1 after the CE1 bit is set (1).
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8.5 Operation of Compare Register
Timer 1 performs a compare operation by comparing the value set to a compare register (CM10, CM11) specified as
a compare register with the count value of a timer register 1 (TM1).
If the count value of TM1 matches with the value set in advance to CM1n (n = 0, 1) as a result of counting by TM1, the
timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal
(INTCM10, INTCM11).
After the value of TM1 has matched with the value of CM10, the count value of TM1 can be cleared, so that TM1 can
be used as an interval timer that repeatedly counts the value set to CM10.
Table 8-2. Interrupt Request Signal from Compare Register (timer 1)
Compare Register
CM10
Interrupt Request Signal
INTCM10
CM11
INTCM11
Timer 1 has two timer output pins (TO10, TO11). Table 8-3 shows the operation mode of each of these pins (for details,
refer to 8.6 Basic Operation of Output Control Circuit).
Table 8-3. Operation Mode of Timer Output Pin (timer 1)
Timer Output Pin
TO10
Output Operation Mode
Specification of Operation Mode
Toggle
Toggle
Set/reset
–
TUM10 bit of TUM0
–
TO11
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Figure 8-9. Compare Operation (timer 1)
FFFFH
FFFFH
TM1
Count value
CM11 Value
CM11 Value
CM10 Value
CM10 Value
Match
0H
Match
Match
Match
Count Started
CE1←1
INTCM10
Interrupt Request
INTCM11
Interrupt Request
TO10 Pin Output
ENTO10 = 1
ALV10 = 1
Inactive Level
Inactive Level
TO11 Pin Output
ENTO11 = 1
ALV11 = 0
INTOV1
Interrupt Request
Remark CLR1 = 0
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Figure 8-10. Clearing TM1 after Detection of Match
FFFFH
CM11
TM1
Count Value
CM10
CM10
CM10
0H
Count Started
CE1←1
CLR1←0
Count Disabled Count
Cleared
Cleared
CE1←0
Started
CE1←1
CLR1←1
INTCM11
Interrupt Request
INTCM10
Interrupt Request
TO11 Pin Output
ENTO11←1
ALV11←1
Inactive Level
TO10 Pin Output
ENTO10←1
ALV10←1
Inactive Level
INTOV1
Interrupt Request
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8.6 Basic Operation of Output Control Circuit
The output control circuit controls the levels of the timer output pins (TO10, TO11) by using the coincidence signals from
the compare registers (CM10, CM11). The operation of the output control circuit is determined by the timer output control
register 1 (TOC1). Note that the TO11 pin output can be used for toggle operation only. The TO10 pin output can be used
for toggle or set/reset operation, according to the specification by the timer unit mode register 0 (TUM0).
To output the TO10 and TO11 signals to pins, the corresponding pins must be set in the control mode by using the port
3 mode control register (PMC3).
Table 8-4. Toggle Signal of Timer Output Pin (timer 1)
Timer Output
Toggle Signal
INTCM10
INTCM11
TO10
TO11
Table 8-5. Set/Reset Signal of Timer Output Pin (timer 1)
Timer Output
Set Signal
INTCM10
Reset Signal
INTCM11
TO10
Figure 8-11. Block Diagram of Timer Output Operation of Timer 1
T
Q
Q
Q
TO10
INTCM10
INTCM11
S
R
T
TO11
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8.6.1 Basic operation
By setting (1) the ENTO1n (n = 0, 1) bit of the timer output control register 1 (TOC1), a pulse can be output from the
TO1n (n = 0, 1) pin.
By clearing (0) the ENTO1n bit, the level of TO1n is fixed. The level to which TO1n is fixed is determined by the ALV1n
(n = 0, 1) bit of TOC1. When the ALV1n bit is 0, TO1n is fixed to the high level; when ALV1n bit is 1, it is fixed to the low
level.
8.6.2 Toggle output
Toggle output is an operation mode in which the output level is inverted each time the value of the compare register
(CM10, CM11) matches with the value of timer register 1 (TM1). The output level of the timer output TO10 is inverted when
the value of CM10 matches with TM1, and the output level of TO11 is inverted when the value of CM11 matches with the
value of TM1.
When timer 1 is stopped by clearing (0) the CE1 bit of the timer mode control register (TMC), the output level is retained
as is.
Figure 8-12. Operation of Toggle Output
FFFFH
FFFFH
FFFFH
FFFFH
FFFFH
TM1
Count Value
CM11 Value
CM10 Value
CM11 Value
CM10 Value
CM11 Value
CM10 Value
CM11 Value
CM10 Value
0H
ENTO10
Instruction
Execution
Instruction
Execution
Instruction
Execution
TO10 Output
(ALV10 = 1)
ENTO11
Instruction
Execution
TO11 Output
(ALV11 = 0)
Table 8-6. Toggle Output of TO10 and TO11 (fCLK = 16 MHz)
Count Clock
Minimum Pulse Width
8/fCLK (0.5 µs)
Maximum Pulse Width
216 × 8/fCLK (32.8 ms)
216 × 16/fCLK (65.5 ms)
216 × 32/fCLK (131 ms)
216 × 64/fCLK (262 ms)
216 × 128/fCLK (524 ms)
fCLK/8
fCLK/16
fCLK/32
fCLK/64
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
fCLK/128
128/fCLK (8.0 µs)
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8.6.3 Set/reset output
The set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare
register (CM1n: n = 0, 1) matches with the value of timer register 1 (TM1).
If CM10 = CM11, interrupt requests are simultaneously generated, and timer output (TO10) is used as ALV10.
When timer 1 is stopped by clearing (0) the CE1 bit of the timer mode control register (TMC), the output level at which
the timer stops is retained as is.
Figure 8-13. Operation of Set/Reset Output (timer 1)
FFFFH
FFFFH
CM11
CM11
TM1
Count Value
CM10
CM10
CM10
0H
Count Started
CE1←1
INTCM10
Interrupt Request
INTCM11
Interrupt Request
TO10 pin
ENTO10 ←1
ALV10 ←1
TOM10 ←1
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8.7 Examples of Use
8.7.1 Operation as interval timer (1)
When timer register 1 (TM1) is made free-running and a fixed value is added to the compare register (CM1n: n = 0, 1)
in the interrupt processing routine, TM1 operates as an interval timer with the added fixed value as the cycle (refer to Figure
8-14).
This interval timer can count in the range shown in Table 8-1 (internal system clock fCLK = 16 MHz).
Because TM1 has two compare registers, interval timers of two types of cycles can be created.
Figure 8-15 shows the set contents of the control registers, Figure 8-16 shows how to set the registers, and Figure 8-
17 shows the processing in an interrupt routine, where compare register CM10 is used.
Figure 8-14. Timing of Interval Timer Operation (1)
FFFFH
FFFFH
MOD(3n)
n
TM1
Count Value
MOD(2n)
0H
Timer Started
Compare Register
(CM10)
n
MOD(2n)
MOD(3n)
MOD(4n)
INTCM10
Interrupt Request
Rewrittern by
Interrupt Program
Rewrittern by
Interrupt Program
Rewrittern by
Interrupt Program
Interval
Interval
Interval
Remark Interval time = n × x/fCLK
y ≤ n ≤ FFFFH
x = 4, 8, 16, 32, 64
y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro
service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12
Macro Service Processing Time).
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Figure 8-15. Control Register Settings for Interval Timer Operation (1)
(a) Prescaler mode register (PRM)
7
0
6
5
4
3
0
2
1
0
PRM
PRM12 PRM11 PRM10
×
×
×
Specifies count clock
(fCLK/x ; x = 8, 16, 32, 64, 128)
(b) Timer unit mode register 0 (TUM0)
7
0
6
0
5
4
3
2
1
0
TUM0
×
×
×
×
×
×
Disables TM1 clearing by match of CM10 and TM1
Specifies TO10 for toggle output
× : don’t care
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Figure 8-16. Setting Procedure of Interval Timer Operation (1)
Interval Timer (1)
Set PRM
Set count value to CM10
CM10 ← n
Set TUM0
Start Count
CE1 ← 1
; Set 1 to bit 7 of TMC
INTCM10 Interrupt
Figure 8-17. Interrupt Request Processing of Interval Timer Operation (1)
INTCM10 Interrupt
Calculate timer value that will
generate next interrupt
CM10 ← CM10 + n
Other Interrupt Processing Program
RETI
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8.7.2 Operation as interval timer (2)
TM1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (refer
to Figure 8-18).
This interval timer can count in the range shown in Table 8-1 (internal system clock fCLK = 16 MHz)
The control register settings are shown in Figure 8-19, and the setting procedure in Figure 8-20.
Figure 8-18. Timing of Interval Timer Operation (2)
n
n
TM1
Count Value
0H
Count Started
Cleared
Match
Cleared
Match
Compare Register
(CM10)
n
INTCM10
Interrupt Request
Interrupt Acknowledged
Interval
Interrupt Acknowledged
Interval
Remark Interval = (n+1) × x/fCLK
0 ≤ n ≤ FFFFH
x = 8, 16, 32, 64, 128
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Figure 8-19. Control Register Settings for Interval Timer Operation (2)
(a) Prescaler mode register (PRM)
7
0
6
5
4
3
0
2
1
0
PRM12
PRM11 PRM10
PRM
×
×
×
Specifies count clock
(fCLK/x ; x = 8, 16, 32, 64, 128)
(b) Timer unit mode register 0 (TUM0)
7
0
6
1
5
4
3
2
1
0
TUM0
×
×
×
×
×
×
Clears TM1 by match of CM10 and TM1
Specifies TO10 for toggle output
× : don’t care
Figure 8-20. Setting Procedure of Interval Timer Operation (2)
Interval Timer (2)
Set PRM
Set count value to CM10
CM10 ← n
Set TUM0
Start Count
CE1 ← 1
; Set 1 to bit 7 of TMC
INTCM10 Interrupt
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8.8 Cautions
(1) The prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer
4). If one of the timers sets the CE bit to “1”, the time base starts counting. If another timer sets the CE bit to “1”
while one timer operates, the first count clock of the timer may be shortened because the time base has already
started counting.
For example, when using timer/counter 1 as an interval timer, the first interval time is shortened by up to 1 count
clock. The second and those that follow are at the specified interval.
Figure 8-21. Operation When Counting Is Started
Count Clock
TM1
CE1
0
1
2
3
4
Count Start Command (CE1 ← 1)
by Software
(2) While timer 1 is operating (while the CE1 bit of the timer mode control register (TMC) is set), malfunctioning may
occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence
in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because
of the function before rewriting.
Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following
registers.
•
•
•
Timer unit mode register 0 (TUM0)
Timer output control register 1 (TOC1)
Prescaler mode register (PRM)
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(3) If the contents of the compare register (CM1n: n = 0, 1) matches with those of TM1 when an instruction that stops
timer register 1 (TM1) operation is executed, the counting operation of TM1 stops, but an interrupt request is
generated.
In order not to generate the interrupt when stopping the operation of TM1, mask the interrupt in advance by using
the interrupt mask register before stopping TM1.
Example
Program that may generate interrupt request
Program that does not generate interrupt request
← Disables interrupt
from timer 1
CLR1 CE1
OR
MK0H, #0CH
← Interrupt request
OR
MK0H, #0CH
CLR1 CE1
from timer 1 occurs
between these
instructions
← Clears interrupt request
flag from timer 1
CLR1 CMIF10
CLR1 CMIF11
(4) A match between the timer register 1 (TM1) and compare register (CM1n: n = 0, 1) is detected only when TM1 is
incremented. Therefore, the interrupt request is not generated even if the same value as TM1 is written to CM1n,
and the timer output (TO1n: n = 0, 1) does not change.
(5) When the compare register (CM10, CM11) is set to 0000H, the compare operation is performed after counting by
TM1. Therefore, the interrupt due to a match (INTCM10, INTCM11) does not occur immediately after counting has
been started. If CM1n (n = 0, 1) is set to 0000H, TM1 counts up to FFFFH, the timer overflows, and the interrupt
due to a match INTCM1n (n = 0, 1) occurs.
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CHAPTER 8 TIMER 1
Figure 8-22. Operation When Compare Register (CM10, CM11) Is Set to 0000H
(a) CM10
Count Clock
TM1
0H
1H
2H
3H
4H
5H
FFFFH
0H
0H
0H
0H
Cleared Cleared Cleared
CE1
Count Started
CM10
0000H
Match Match Match Match
INTCM10
Interrupt Occurred
(b) CM11
Count Clock
TM1
CE1
0H
1H
2H
FFFFH
0H
1H
2H
FFFFH
0H
1H
Count Started
CM11
0000H
Match
Match
INTCM11
Interrupt Occurred
Interrupt Occurred
(6) If the timer output is enabled when the active level is changed, the output level of pins may change momentarily.
To prevent this, enable the timer output after the active level have been changed.
(7) To change the active level specification (ALV1n bit (n = 0, 1) of the timer output control register 1 (TOC1)), change
the active level specification after the timer output of the corresponding timer output pins has been disabled.
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CHAPTER 9 TIMER 4
9.1 Function
Timer 4 is a 16-bit timer.
This timer functions as an interval timer.
When used as an interval timer, timer 4 generates an internal interrupt at a predetermined interval.
Table 9-1. Interval Time of Timer 4
Minimum Interval Time
4/fCLK (0.25 µs)
8/fCLK (0.5 µs)
Maximum Interval Time
Resolution
4/fCLK (0.25 µs)
16
2
2
2
2
2
× 4/fCLK (16.4 ms)
16
× 8/fCLK (32.8 ms)
8/fCLK (0.5 µs)
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
16
16/fCLK (1.0 µs)
32/fCLK (2.0 µs)
64/fCLK (4.0 µs)
× 16/fCLK (65.5 ms)
16
× 32/fCLK (131 ms)
16
× 64/fCLK (262 ms)
( ): at fCLK = 16 MHz
9.2 Configuration
Timer 4 consists of the following registers:
•
•
Timer register (TM4) × 1
Compare register (CM4n) × 2 (n = 0, 1)
Figure 9-1 shows the block diagram of timer 4.
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Figure 9-1. Block Diagram of Timer 4
Internal Bus
16
16
1/8
Compare Register 40
(CM40)
Timer Mode Control
Register 4 (TMC4)
CE4
CLR41 CLR40
16
Match
INTCM40
16
Compare Register 41
(CM41)
RESET
16
Match
INTCM41
INTOV4
16
fCLK/64
fCLK/32
fCLK/16
fCLK/8
Clear
Timer Register 4
(TM4)
Overflow
fCLK
fCLK/4
Prescaler Mode
Register 4 (PRM4)
PRM42 PRM41 PRM40
1/8
16
Internal Bus
CHAPTER 9 TIMER 4
(1) Timer register 4 (TM4)
TM4 is a timer register that counts up the count clock specified by the prescaler mode register 4 (PRM4).
Counting of this timer register is enabled or disabled by the timer mode control register 4 (TMC4).
The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM4 is cleared
to 0000H and stops counting.
(2) Compare registers (CM40, CM41)
CM4n (n = 0, 1) is a 16-bit register that holds the contents determining the cycle of the interval timer operation.
When the contents of CM4n matches with the contents of TM4, an interrupt request (INTCM4n: n = 0, 1) is generated.
The count value of TM4 can be cleared when its value matches with the contents of CM4n.
These compare registers can be read or written by using 16-bit manipulation instructions. When RESET is input,
their contents are undefined.
(3) Prescaler
The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler
is selected by the selector, and TM4 performs the count operation by using this clock as a count clock.
(4) Selector
The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM4.
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CHAPTER 9 TIMER 4
9.3 Timer 4 Control Register
(1) Timer mode control register 4 (TMC4)
TMC 4 is a register that controls the count and clear operations of timer register 4 (TM4).
This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure
9-2 shows the format of TMC4.
When RESET is input, the value of this register is cleared to 00H.
Figure 9-2. Format of Timer Mode Control Register 4 (TMC4)
Address: 0FF37H
7
On reset: 00H
R/W
6
0
5
0
4
0
3
2
0
1
0
TMC4
0
CE4
CLR41 CLR40
CE4
0
Controls Count Operation of TM4
Clears and stops counting
Enables counting operation
1
CLR41 Clear Operation of TM4 by Match with CM41
0
1
Disables (free running mode)
Enables (interval timer mode)
CLR40 Clear Operation of TM4 by Match with CM40
0
1
Disables (free running mode)
Enables (interval timer mode)
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CHAPTER 9 TIMER 4
(2) Prescaler mode register 4 (PRM4)
PRM4 is a register that specifies the count clock of timer register 4 (TM4).
This register can be read or written by using an 8-bit manipulation instruction. Figure 9-3 shows the format of PRM4.
When RESET is input, the value of this register is cleared to 00H.
Figure 9-3. Format of Prescaler Mode Register 4 (PRM4)
Address: 0FF3AH
7
On reset: 00H
R/W
6
0
5
0
4
0
3
0
2
1
0
PRM4
0
PRM42 PRM41 PRM40
(fCLK = 16 MHz)
PRM42 PRM41 PRM40
Specifies Count Clock of TM4.
Count Clock [Hz]
fCLK/4
Resolution [
0.25
0.5
µs]
0
0
0
1
1
0
0
1
0
1
0
0
fCLK/8
0
0
fCLK/16
1.0
fCLK/32
2.0
1
fCLK/64
4.0
Other
Setting prohibited
Remark fCLK: internal system clock
9.4 Operation of Timer Register 4 (TM4)
9.4.1 Basic operation
Timer 4 counts up by using the count clock specified by the prescaler mode register 4 (PRM4).
Counting is enabled or disabled by the CE4 bit of the timer mode control register 4 (TMC4). When the CE4 bit is set
(1) by software, TM4 is set to 0001H at the first count clock, and starts counting up. When the CE4 bit is cleared (0) by
software, TM4 is immediately cleared to 0000H, and stops generation of the match signal.
If the CE4 bit is set (1) while it has been already set (1), TM4 is not cleared but continues counting.
If a count clock is input when TM4 reaches FFFFH, TM4 is cleared to 0000H, and an overflow interrupt (INTOV4) occurs.
When RESET is input, TM4 is cleared to 0000H and stops counting.
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CHAPTER 9 TIMER 4
Figure 9-4. Basic Operation of Timer Register 4 (TM4)
(a) When counting starts, stops, and then starts again
Count Clock
TM4
CE4
0H
1H
2H
3H
FFH 100H 101H
0H
1H
2H
Count Started
CE4 ← 1
Count Stopped
CE4 ← 0
Count Started
CE4 ← 1
(b) If CE4 bit is set to “1” again after counting has been started
Count Clock
TM4
CE4
0H
1H
2H
3H
4H
5H
6H
7H
Count Started
CE4 ← 1
Rewritten
CE4 ← 1
(c) Operation when TM4 is FFFFH
Count Clock
TM4
FFFEH FFFFH 0H
1H
INTOV4
Interrupt Request
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CHAPTER 9 TIMER 4
9.4.2 Clear operation
(1) Clear operation by match with compare register
Timer register 4 (TM4) can be automatically cleared when its value matches with the value of a compare register
(CM4n: n = 0, 1). When a clearance source arises, TM3 is cleared to 0000H on the next count clock. Therefore,
even if a clearance source arises, the value at the point at which the clearance source arose is retained until the
next count clock arrives.
Figure 9-5. TM4 Clear Operation by Match with Compare Register (CM40, CM41)
Count Clock
_
n 1
n
0
n
1
TM4
Compare Register
(CM4n)
TM4 and CM4n Match Cleared Here
Remark n = 0, 1
(2) Clear operation by CE4 bit of timer mode control register 4 (TMC4)
Timer register 4 (TM4) is also cleared when the CE4 bit of TMC4 is cleared (0) by software. The clear operation
is performed following clearance (0) of the CE4 bit in the same way.
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CHAPTER 9 TIMER 4
Figure 9-6. Clear Operation of TM4 When CE4 Bit is Cleared (0)
(a) Basic operation
Count Clock
_
TM4
CE4
n 1
n
0
(b) Restart before count clock is input after clearance
Count Clock
_
TM4
n 1
n
0
1
2
3
CE4
If the CE4 bit is set (1) before this count clock, the count starts from 1 on
this count clock
(c) Restart when count clock is input after clearance
Count Clock
_
TM4
n 1
n
0
0
1
2
CE4
If the CE4 bit is set (1) from this count clock onward, the count starts from 1
on the count clock after the CE4 bit is set (1).
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CHAPTER 9 TIMER 4
9.5 Operation of Compare Register
Timer 4 performs a compare operation by comparing the value set to a compare register (CM40, CM41) with the count
value of a timer register 4 (TM4).
If the count value of TM4 matches with the value set in advance to CM4n (n = 0, 1) as a result of counting by TM4, an
interrupt request (INTCM4n: n = 0, 1) is generated.
Moreover, the contents of TM4 can be cleared after it has matched with the value of CM4n, so that TM4 can operate
as an interval timer that repeatedly counts the value set to CM4n.
Table 9-2. Interrupt Request Signal from Compare Register (timer 4)
Compare Register
CM40
CM41
Interrupt Request Signal
INTCM40
INTCM41
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CHAPTER 9 TIMER 4
Figure 9-7. Compare Operation (timer 4)
FFFFH
FFFFH
TM4
Count Value
CM41 Value
CM41 Value
CM40 Value
CM40 Value
Match
0H
Match
Match
Match
Count Started
CE4←1
INTCM40
Interrupt Request
INTCM41
Interrupt Request
INTOV4
Interrupt Request
Remark CLR40 = 0, CLR41 = 0
Figure 9-8. TM4 Clearance after Match Detection
CM41
CM40
CM40
CM40
TM4
Count Value
0H
Count Started
CE4←1
CLR40← 0
CLR41← 1
Cleared
Count Started
Cleared
Cleared
CE4← 0
CLR40← 1
CLR41← 0
Count Disabled
CE4← 0
INTCM40
Interrupt Request
INTCM41
Interrupt Request
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CHAPTER 9 TIMER 4
9.6 Example of Use
9.6.1 Operation as interval timer (1)
By setting the timer register 4 (TM4) in the free running mode and adding a specific value to a compare register (CM4n:
n = 0, 1) in an interrupt processing routine, TM4 can be used as an interval timer whose cycle is determined by the specific
value to be added (refer to Figure 9-9).
Figure 9-10 shows the set contents of the control registers, Figure 9-11 shows how to set the control registers, and Figure
9-12 shows the processing in the interrupt routine, where compare register CM40 is used.
Figure 9-9. Timing of Interval Timer Operation (1)
FFFFH
FFFFH
MOD(3n)
n
TM4 Count Value
MOD(2n)
0H
Timer Started
Compare Register
(CM40)
n
MOD(2n)
MOD(3n)
MOD(4n)
INTCM40
Interrupt Request
Rewriting by
Interrupt Program
Rewriting by
Interrupt Program
Rewriting by
Interrupt Program
Interval Time
Interval Time
Interval Time
Remark Interval time = n × x/fCLK
y ≤ n ≤ FFFFH
x = 4, 8, 16, 32, 64
y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro
service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12
Macro Service Processing Time).
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CHAPTER 9 TIMER 4
Figure 9-10. Set Contents of Control Registers for Interval Timer Operation (1)
(a) Prescaler mode register 4 (PRM4)
7
0
6
0
5
0
4
0
3
0
2
1
0
PRM42 PRM41 PRM40
PRM4
Specifies count clock
(fCLK/x ; x = 4, 8, 16, 32, 64)
(b) Timer mode control register 4 (TMC4)
7
6
5
0
4
0
3
1
2
0
1
0
0
0
TMC4
0
0
Disables TM4 clearing
Enables count operation
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CHAPTER 9 TIMER 4
Figure 9-11. Setting Procedure of Interval Timer Operation (1)
Interval Timer (1)
Sets PRM4
Sets count value to CM40
CM40←n
Sets TMC4
INTCM40 Interrupt
Figure 9-12. Interrupt Request Processing of Interval Timer Operation (1)
INTCM40 Interrupt
Calculates timer value at which interrupt occurs next
CM40←CM40 + n
Other Interrupt Processing Program
RETI
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CHAPTER 9 TIMER 4
9.6.2 Operation as interval timer (2)
TM4 can be used as an interval timer that repeatedly generates an interrupt at interval determined by the count value
set in advance (refer to Figure 9-13).
Figure 9-4 shows the set contents of the control registers, and Figure 9-15 shows how to set the control registers, where
compare register CM41 is used.
Figure 9-13. Timing of Interval Timer Operation (2)
n
n
TM4
Count Value
0H
Count Started
Cleared
Cleared
Compare Register
(CM41)
n
INTCM41
Interrupt Request
Interrupt Accepted
Interval Time
Interrupt Accepted
Interval Time
Remark Interval time = (n+1) × x/fCLK
0 ≤ n ≤ FFFFH
x = 4, 8, 16, 32, 64
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CHAPTER 9 TIMER 4
Figure 9-14. Set Contents of Control Register for Interval Timer Operation (2)
(a) Prescaler mode register 4 (PRM4)
7
0
6
0
5
0
4
0
3
0
2
1
0
PRM4
PRM42 PRM41 PRM40
Specifies count clock
(fCLK/x ; x = 4, 8, 16, 32, 64)
(b) Timer mode control register 4 (TMC4)
7
0
6
0
5
0
4
0
3
1
2
0
1
1
0
0
TMC4
TM4 clearing by match of CM41 and TM4
Enables count operation
Figure 9-15. Setting Procedure of Interval Timer Operation (2)
Interval timer (2)
Sets PRM4
Sets count value to CM41
CM41←n
Sets TMC4
INTCM41 Interrupt
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CHAPTER 9 TIMER 4
9.7 Cautions
(1) The prescaler uses one time base commonly with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer
4). If one of the timers sets the CE bit to “1”, the time base starts counting. If another timer sets the CE bit to “1”
while one timer operates, the first count clock of the timer may be shortened because the time base has already
started counting.
For example, if a timer/counter is used as an interval timer, the first interval will be shortened by up to one count
clock. The second and subsequent intervals will be as specified.
Figure 9-16. Operation When Count Starts
Count Clock
TM4
CE4
0
1
2
3
4
Software count start directive (CE4←1)
(2) There is a possibility of misoperation if the next register contents are rewritten while the timer 4 is running (when
the CE4 bit of the timer mode control register 4 (TMC4) is set). The misoperation occurs as there is no defined order
of priority in the event of contention between the timings at which the hardware function changes due to a register
rewrite and the status changes in the function prior to the rewrite.
When the contents of following registers are rewritten, counter operations must be stopped first to ensure stability.
•
•
CLR40 and CLR41 bits of timer mode control register 4 (TMC4)
Prescaler mode register 4 (PRM4)
(3) If the compare register (CM4n: n = 0, 1) and TM4 contents match when an instruction that stops timer register 4
(TM4) operation is executed, the TM4 count operation stops, but an interrupt request is generated.
If you do not want an interrupt to be generated when TM4 operation is stopped, interrupts should be masked by means
of interrupt the mask register before stopping the TM4.
Example
Program in which an interrupt request may be
Program in which an interrupt request is not generated
generated
.
.
.
.
.
.
← Disables interrupts from timer 4
MK1L, #03H
CLR1 CE4
OR
CLR1 CE4
← Interrupt request gener-
OR
MK1L, #03H
ated by timer 4 here
.
.
.
← Clears timer 4 interrupt request flag
CLR1 CMIF40
CLR1 CMIF41
.
.
.
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CHAPTER 9 TIMER 4
(4) Match between timer register 4 (TM4) and compare register (CM4n: n = 0, 1) is detected only when TM4 is
incremented. Therefore, the interrupt request is not generated even if the same value as TM4 is written to CM4n.
(5) If a compare register (CM40, CM41) is set to 0000H, the compare operation is performed after counting has been
completed. Therefore, the interrupt due to a match (INTCM40, INTCM41) does not occur immediately after counting
has been started. If CM4n (n = 0, 1) is set to 0000H, TM4 counts up to FFFFH, overflows, and then the interrupt
due to a match INTCM4n (n = 0, 1) occurs.
Figure 9-17. Operation When Compare Register (CM40, CM41) Is Set to 0000H
Count Clock
TM4
CE4
0H
1H
2H
3H
4H
5H
FFFFH
0H
0H
0H
0H
Cleared Cleared Cleared
Count Started
CM4n
0000H
Match Match Match Match
INTCM4n
Interrupt Occured
Remark n = 0, 1
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CHAPTER 10 WATCHDOG TIMER FUNCTION
The watchdog timer is a timer that detects inadvertent program loops.
Watchdog timer interrupts are used to detect system or program errors. For this purpose, instructions that clear the
watchdog timer (start the count) within a given period are inserted at various places in a program.
If an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a
watchdog timer interrupt (INTWDT) is generated and a program error is reported.
10.1 Configuration
The watchdog timer block diagram is shown in Figure 10-1.
Figure 10-1. Block Diagram of Watchdog Timer
f
f
f
f
CLK/29
Overflow
Watchdog Timer
(8-bit)
CLK/211
CLK/212
CLK/213
INTWDT
Frequency
Divider
f
CLK
WDT CLR
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CHAPTER 10 WATCHDOG TIMER FUNCTION
10.2 Watchdog Timer Mode Register (WDM)
The WDM is an 8-bit register that controls the watchdog timer operation.
To prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by
a dedicated instruction. This dedicated instruction, MOV WDM,#byte, has a special code configuration (4 bytes), and a write
is not performed unless the 3rd and 4th bytes of the operation code are mutual complements.
If the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt
is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source
of the error, and thus the address that was the source of the error can be identified from the return address saved in the
stack area.
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.
As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics
assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system
initialization should be performed by the program.
Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any
operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.
After a system reset (RESET input), once the watchdog timer has been started (by setting (1) the RUN bit), the WDM
contents cannot be changed. The watchdog timer can only be stopped by a reset, but can be cleared at any time with a
dedicated instruction.
The WDM can be read at any time by a data transfer instruction.
RESET input clears the WDM to 00H.
The WDM format is shown in Figure 10-2.
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Figure 10-2. Format of Watchdog Timer Mode Register (WDM)
Address: 0FFC2H
7
On reset: 00H
R/W
6
0
5
0
4
3
0
2
1
0
0
WDM
RUN
PRC
WDI2 WDI1
Specifies Operation of Watchdog Timer
Stops watchdog timer
RUN
0
1
Clears watchdog timer to start counting
Priority of Interrupt Request of Watchdog Timer
Interrupt request of watchdog timer
< interrupt request of NMI pin input
Interrupt request of watchdog timer
> interrupt request of NMI pin input
PRC
0
1
WDI2 WDI1
Count
Clock
Overflow Time [ms]
f
CLK = 12.5 MHz
fCLK = 16.0 MHz
0
0
1
1
0
1
0
1
f
f
f
f
CLK/29
10.5
41.9
83.9
167.8
8.2
CLK/211
CLK/212
CLK/213
32.8
65.5
131.1
Remark fCLK: internal system clock
Cautions 1. The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV
WDM, #byte).
2. The same value should be written each time in writes to the WDM to set (1) the RUN bit. The
contents written the first time cannot be changed even if a different value is written.
3. Once the RUN bit has been set (1), it cannot be reset (0) by software.
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CHAPTER 10 WATCHDOG TIMER FUNCTION
10.3 Operation
10.3.1 Count operation
The watchdog timer is cleared, and the count started, by setting (1) the RUN bit of the watchdog timer mode register
(WDM). When overflow time specified by the WDI2 and WDI1 bits of WDM has elapsed after the RUN bit has been set
(1), a non-maskable interrupt (INTWDT) is generated.
If the RUN bit is set (1) again before the overflow time elapses, the watchdog timer is cleared and the count operation
is started again.
10.3.2 Interrupt priorities
The watchdog timer interrupt (INTWDT) is a non-maskable interrupt. Other non-maskable interrupts are interrupts from
the NMI pin (NMI). The order of acknowledgment when an INTWDT interrupt and NMI interrupt are generated simultaneously
can be specified by the setting of bit 4 of the watchdog timer mode register (WDM).
Even if INTWDT is generated while the NMI processing program is executed when NMI acknowledgement is specified
to take precedence, INTWDT is not acknowledged until completion of execution of the NMI processing program.
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10.4 Cautions
10.4.1 General cautions on use of watchdog timer
(1) The watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program
loops. Therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog
timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing
to be performed that will restore the normal state or establish a stable state and then stop the operation.
(2) The watchdog timer cannot detect inadvertent program loops in the following cases.
<1> If watchdog timer clearance is performed in the timer interrupt processing program
<2> If cases where an interrupt request or macro service is held pending (refer to 14.9) occur consecutively
<3> If the watchdog timer is cleared periodically when the program is looping inadvertently due to an error in the
program logic (if each module of the program functions normally but the overall program does not)
<4> If the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program
loop occurs
<5> If the STOP mode, HALT mode, or IDLE mode is entered as the result of an inadvertent program loop
<6> If an inadvertent program loop of watchdog timer also occurs in the event of CPU hang up due to external noise
In cases <1>, <2> and <3> the program can be amended to allow detection to be performed.
In case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. Similarly, in case <5>, the
STOP mode, HALT mode, or IDLE mode cannot be set unless a 4-byte dedicated instruction is used. For state <2>
to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a
specific pattern (e.g. BT PSWL. bit, $$, etc.). Therefore, the establishment of state <2> as the result of <4>, <5>
or an inadvertent program loop is likely to be extremely rare.
10.4.2 Cautions on µPD784054 watchdog timer
(1) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte).
(2) The same value should be written each time in writes to the watchdog timer mode register (WDM) to set (1) the RUN
bit. The contents written the first time cannot be changed even if a different value is written.
(3) Once the RUN bit has been set (1), it cannot be reset (0) by software.
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CHAPTER 11 A/D CONVERTER
The µPD784054 incorporates an analog/digital (A/D) converter with 16 multiplexed analog inputs (ANI0 to ANI15).
The successive approximation conversion method is used, and the conversion result is held in the 10-bit A/D conversion
result register (ADCR0 to ADCR7). This allows fast, high-precision conversion to be performed (conversion time of 13 µs
when fCLK = 16 MHz and high-speed conversion is used).
There are two modes for starting A/D conversion, as follows:
•
•
Hardware start : Conversion started by trigger input (INTP4).
Software start : Conversion started in accordance with A/D converter mode register (ADM) bit setting.
After start-up, there are two operating modes, as follows:
•
•
Scan mode
: Multiple analog inputs are selected in order, and conversion data is obtained from all pins.
Select mode : One pin is used as the analog input, and conversion values are obtained in succession.
Stoppage of all the above modes and conversion operations is specified by the ADM register.
In each mode, the conversion result is held in ADCRn (n = 0 to 7) each time A/D conversion has been completed. When
A/D conversion has been completed, an A/D conversion end interrupt request (INTAD) is generated. This interrupt can start
a macro service that automatically transfers data by hardware.
11.1 Configuration
Figure 11-1 shows the block diagram of the A/D converter.
The high-order 8 channels (ANI8 to ANI15) and low-order 8 channels (ANI0 to ANI7) of the A/D converter are selected
by using the A/D converter mode register (ADM).
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Figure 11-1. Block Diagram of A/D Converter
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Input
Selector
Series Resistor String
Sample & Hold Circuit
AVREF
R/2
R
ANI8
ANI9
Voltage
Comparator
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
Input
Selector
Successive
Approximation Register
(SAR)
Conversion
Trigger
R/2
Edge
Detection
Circuit
INTAD
Control
Circuit
AVSS
INTP4
10
Trigger Enable
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
A/D Converter Mode Register
(ADM)
RESET
A/D Conversion Result Register
8
10
Internal Bus
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Cautions 1. A capacitor should be connected between the analog input pins (ANI0 to ANI15) and AVSS and
between the reference voltage input pin (AVREF) and AVSS to prevent misoperation due to noise.
Be sure to connect the capacitor as closely to ANI0 to ANI15 and AVREF as possible.
Figure 11-2. Example of Capacitor Connection on A/D Converter Pins
µPD784054
Analog
Input
ANI0-ANI15
100 to
500 pF
Reference
Voltage Input
AVREF
AVSS
2. A voltage outside the range AVSS to AVREF should not be applied to pins used as A/D converter input
pins. Refer to 11.6 Cautions for details.
(1) Input circuit
The input circuit selects the analog input in accordance with the specification of the A/D converter mode register
(ADM), and sends the analog input to the sample & hold circuit according to the operating mode,
(2) Sample & hold circuit
The sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input
in the process of A/D conversion.
(3) Voltage comparator
The voltage comparator determines the voltage difference between the analog input and the series resistor string
value tap.
(4) Series resistor string
The series resistor string is used to generate voltages that match the analog inputs.
The series resistor string is connected between the A/D converter reference voltage pin (AVREF) and the A/D
converter GND pin (AVSS). To provide 1024 equal voltage steps between the two pins, it is made up of 1023 equal
resistors and two resistors with half that resistance value.
The series resistor string voltage tap is selected by a tap selector controlled by the successive approximation register
(SAR).
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(5) SAR: Successive Approximation Register
The SAR is a 10-bit register in which the data for which the series resistor string voltage tap value matches the analog
input voltage value is set bit by bit starting from the most significant bit (MSB).
When data has been set up to the least significant bit (LSB) of the SAR (when A/D conversion is completed), the
SAR contents (conversion result) are stored in the A/D conversion result register (ADCRn: n = 0-7).
(6) Edge detection circuit
The edge detection circuit detects a valid edge from the interrupt request input pin (INTP4) input, and generates
an external interrupt request signal (INTP4) and A/D conversion operation external trigger.
The INTP4 pin input valid edge is specified by external interrupt mode register 1 (INTM1) (refer to Figure 13-2).
External trigger enabling/disabling is set by means of the A/D converter mode register (ADM) (refer to 11.2 A/D
Converter Mode Register (ADM)).
11.2 A/D Converter Mode Register (ADM)
ADM is an 8-bit register that controls A/D converter operations.
The ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format
is shown in Figure 11-3.
Bits 0 to 2 (ANIS0 to ANIS2) select input analog signals to be converted. Bit 3 (PS) selects whether ANI0 to ANI7 (low-
order 8 channels) or ANI8 to ANI15 (high-order 8 channels) are used as analog input pins. The low-order 8 channels and
high-order 8 channels have identical functions.
Bit 5 (AM0) and bit 6 (AM1) control the operation mode of A/D conversion. If the AM0 and AM1 bits are cleared (0), all
conversion operations under execution are stopped. At this time, ADCRn (n = 0 to 7) is not updated, nor is the INTAD interrupt
request generated. Moreover, power supply to the voltage comparator is stopped to reduce the current consumption of
the A/D converter.
Bit 7 (TRG) enables external synchronization of the A/D conversion operation. If the TRG bit is set (1) when the AM0
or AM1 bits are set, the conversion operation is initialized each time the valid edge is input to the INTP4 pin as an external
trigger. If the TRG bit is cleared (0), the conversion operation is performed regardless of the INTP4 pin input.
If data is written to ADM during conversion, the conversion operation is initialized and started from the beginning again.
When RESET is input, the value of ADM is reset to 00H.
Caution When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing
(0) the AM0 bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit or AM1 bit remains
set (1), the conversion operation will be stopped by entering the STOP or IDLE mode, but the power
supply to the voltage comparator will not be stopped, and therefore the A/D converter consumption
current will not be reduced.
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Figure 11-3. Format of A/D Converter Mode Register (ADM)
Address: 0FF6EH
7
On reset: 00H
R/W
6
5
4
3
2
1
0
TRG AM1 AM0
ANIS2 ANIS1 ANIS0
ADM
FR
PS
TRG
Controls External Trigger
Disables external trigger
Enables external trigger
0
1
AM1 AM0
Specifies A/D Conversion Operation Mode
Stops conversion
0
0
1
1
0
1
0
1
Scan mode
Select mode
1-buffer mode
4-buffer mode
FR
0
Selects Conversion Time
208 clocks (fCLK > 12.5 MHz)
1
169 clocks (fCLK ≤ 12.5 MHz)
PS
0
Selects Analog Input Pin
ANI0 to ANI7 (port 7)
1
ANI8 to ANI15 (port 8)
ANIS2 ANIS1 ANIS0
Selects Analog Input
In select
mode
In scan
mode
ANI0/ANI8
ANI1/ANI9
ANI0/ANI8
ANI0/ANI8,
ANI1/ANI9
ANI0/ANI8-
ANI2/ANI10
ANI0/ANI8-
ANI3/ANI11
ANI0/ANI8-
ANI4/ANI12
ANI0/ANI8-
ANI5/ANI13
ANI0/ANI8-
ANI6/ANI14
ANI0/ANI8-
ANI7/ANI15
0
0
0
0
0
1
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Remark fCLK: internal system clock
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Table 11-1. Conversion Time Set by FR Bit
Internal system clock: fCLK (MHz)
FR bit
16
0
14
0
12.5
1
10
1
Conversion time (µs)
13
14.9
13.5
16.9
Caution Once the A/D converter starts operating, conversion operations are performed repeatedly until the AM0
bit and AM1 bit of the A/D converter mode register (ADM) is cleared (0). Therefore, a superfluous
interrupt may be generated if ADM setting is performed after interrupt-related registers, etc., when A/
D converter mode conversion, etc., is performed. The result of this superfluous interrupt is that the
conversion result storage address appears to have been shifted when the scan mode is used. Also,
when the select mode is used, the first conversion result appears to have been an abnormal value, such
as the conversion result for the other channel. It is therefore recommended that A/D converter mode
conversion be carried out using the following procedure.
<1> Write to the ADM
<2> Interrupt request flag (ADIF) clearance (0)
<3> Interrupt mask flag setting
Operations <1> to <3> should not be divided by an interrupt or macro service.
Alternatively, the following procedure is recommended.
<1> Stop the A/D conversion operation by clearing (0) the AM0 bit and AM1 bit of the ADM.
<2> Interrupt request flag (ADIF) clearance (0).
<3> Interrupt mask flag setting
<4> Write to the ADM
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11.3 A/D Conversion Result Registers (ADCR0 to ADCR7)
The µPD784054 has eight 10-bit A/D conversion result registers (ADCR0 to ADCR7) that store the results of A/D
conversion.
Each ADCRn (n = 0 to 7) can be only read by using a 16-bit manipulation instruction or an 8-bit manipulation instruction.
The conversion result can be read from ADCRn in the following two ways:
(1) Word access (by execution of 16-bit manipulation instruction)
Of the word data read, the low-order 10 bits are valid.
The high-order 6 bits are always “0” when read.
Figure 11-4 illustrates word access to ADCRn.
Figure 11-4. Word Access to A/D Conversion Result Register
Symbol
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
R/W
R
ADCRn
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
(n = 0-7)
Symbol
ADCR0
Address
0FF70H
On reset
Undefined
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
0FF72H
0FF74H
0FF76H
0FF78H
0FF7AH
0FF7CH
0FF7EH
Remark AD0-AD9: A/D conversion result
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(2) Byte access (by execution of 8-bit manipulation instruction)
Of the 10-bit data of the A/D conversion result, the high-order 8 bits are read.
Figure 11-5 illustrates byte access to ADCRn
Figure 11-5. Byte Access to A/D Conversion Result Register
Symbol
7
6
5
4
3
2
1
0
R/W
R
ADCRnH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
(n = 0-7)
Symbol
ADCR0H
ADCR1H
ADCR2H
ADCR3H
ADCR4H
ADCR5H
ADCR6H
ADCR7H
Address
0FF71H
On reset
Undefined
0FF73H
0FF75H
0FF77H
0FF79H
0FF7BH
0FF7DH
0FF7FH
Remark AD2-AD9: A/D conversion result (high-order 8 bits of 10 bits)
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11.4 Operation
11.4.1 Basic A/D converter operation
(1) A/D Conversion Operation procedure
A/D conversion is performed by means of the following procedure:
(a) Analog pin selection and operating mode specification are set with the A/D converter mode register (ADM), and
the A/D conversion is started.
(b) When conversion starts, the MSB (bit 9) of the successive approximation register (SAR) is set (1) automatically.
(c) When bit 9 of the SAR is set (1), the tap selector sets the series resistor string voltage tap to
1023
·
AVREF (= 1/2 AVREF).
·
2048
(d) The voltage difference between the series resistor string voltage tap and the analog input is determined by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of the SAR remains set (1), and
if it is less than (1/2) AVREF, the MSB is cleared (0).
(e) Next, bit 8 of the SAR is set (1) automatically, and the next comparison is performed. Here, the series resistor
string voltage tap is selected according to the value of bit 9 for which the result has already been set, as shown
below.
3
4
1535
2048
·
•
•
Bit 9 = 1 ........
Bit 9 = 0 ........
AVREF =
AVREF
AVREF
·
511
2048
1
4
·
AVREF =
·
This voltage tap is compared with the analog input voltage, and bit 8 of the SAR is manipulated as follows
according to the result:
•
•
Analog input voltage ≥ voltage tap: Bit 8 = 1
Analog input voltage < voltage tap: Bit 8 = 0
(f) The same kind of comparison is continued up to the LSB (bit 0) of the SAR (binary search method).
(g) When comparison of the 10 bits is completed, a valid digital result is left in the SAR, and that value is transferred
to the A/D conversion result register (ADCR0 to ADCR7) and latched.
An A/D conversion operation end interrupt request (INTAD) can be generated at the same time.
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CHAPTER 11 A/D CONVERTER
Figure 11-6. Basic Operation of A/D Converter
Conversion Time
Sampling Time
Sampling
A/D Converter
Operation
A/D Conversion
300H
Conversion
Result
SAR
Undefined
200H
or
100H
Conversion
Result
ADCRn
(n = 0 to 7)
INTAD
A/D conversion operations are performed successively until the AM0 bit and AM1 bit is cleared (0) by software. If
a write operation is performed on the ADM during an A/D conversion operation, the conversion operation is initialized,
and if the AM0 bit and AM1 bit is set (1), conversion will be started from the beginning.
The contents of the ADCR n (n = 0 to 7) are undefined after RESET input.
(2) Input voltage and conversion result
The relationship between the analog input voltage input to an analog input pin (ANI0 to ANI15) and the A/D conversion
result (value stored in ADCRn) is shown by the following expression:
VIN
AVREF
ADCRn = INT(
or
× 1024 + 0.5)
AVREF
1024
AVREF
1024
(ADCRn – 0.5) ×
≤ VIN < (ADCRn + 0.5) ×
Remark INT( ) : Function that returns the integer part of the value in ( )
VIN : Analog input voltage
AVREF : AVREF pin voltage
ADCRn : ADCR n (n = 0 to 7) value
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Figure 11-7 shows the relationship between the analog input voltage and the A/D conversion result in graphic form.
Figure 11-7. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
A/D Conversion Result
(ADCRn: n = 0 to 7)
1021
3
2
1
0
1
1
3
2
5
3
2043 1022 2045 1023 2047
2048 1024 2048 1024 2048
1
2048 1024 2048 1024 2048 1024
Input Voltage/AVREF
(3) A/D conversion time
The A/D conversion time is determined by the system clock frequency (fCLK) and the FR bit of the A/D converter mode
register (ADM).
The A/D conversion time includes the entire time required for one A/D conversion operation, and the sampling time
is also included in the A/D conversion time.
These values are shown in Table 11-2.
Table 11-2. Time of A/D Conversion
System Clock (fCLK) Range
fCLK > 12.5 MHz
FR Bit
Conversion Time
208 clocks
0
1
fCLK ≤ 12.5 MHz
169 clocks
(4) A/D converter operating modes
There are two A/D converter operating modes, scan mode and select mode. These modes are selected according
to the setting of bit 5 (AM0) and bit 6 (AM1) of the A/D converter mode register (ADM).
Operation in either mode continues until the ADM is rewritten.
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11.4.2 Select mode
In the select mode, one analog input pin is selected by bits 0 to 2 (ANIS0 to ANIS2) of the A/D converter mode select
register (ADM), and the specified analog input is converted. The result of the conversion is stored to the A/D conversion
result register corresponding to the analog input.
In this mode, the following two modes can be selected depending on how the A/D conversion result is stored.
•
•
1-buffer mode
4-buffer mode
(1) 1-buffer mode
One analog input is converted once, and the result is stored to one A/D conversion result register. Therefore, the
analog input and A/D conversion result register correspond on a one-to-one basis (refer to Table 11-3).
Each time the conversion has been completed once, an A/D conversion end interrupt request (INTAD) occurs.
Table 11-3. Correspondence between Analog Input and A/D Conversion Result Register
(select mode: 1-buffer mode)
Analog Input
ANI0/ANI8
A/D Conversion Result Register
ACDR0
ANI1/ANI9
ADCR1
ACDR2
ADCR3
ACDR4
ADCR5
ACDR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 11-8. Operating Timing in Select Mode (1-buffer mode) (1/2)
(a) TRG bit ← 0
A/D Conversion
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
Conversion Started Conversion Ended Conversion Ended Conversion Ended Conversion Ended Conversion Ended Conversion Ended
AM1, AM0←10
PS←0
ANIS2-ANIS0←011
ADCR3
ANI3
ANI3
ANI3
ANI3
ANI3
INTAD
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CHAPTER 11 A/D CONVERTER
Figure 11-8. Operation Timing in Select Mode (1-buffer mode) (2/2)
(b) TRG bit ← 1
INTP4
Initialization
ANI0
Initialization
ANI0 ANI0
Initialization
ANI0 ANI0
ANI0
ANI0
A/D Conversion
Conversion Started Conversion Ended
Conversion Ended Conversion Ended
Conversion Ended Conversion Ended
AM1, AM0←10
PS←0
ANIS2-ANIS0←000
ADCR0
ANI0
ANI0
ANI0
ANI0
INTAD
(2) 4-buffer mode
One analog input is converted four times, and the result is stored to four A/D conversion result registers. When one
of the analog inputs of ANI0 to ANI3 (ANI8 to ANI11) is selected, the conversion result is stored to A/D conversion
result registers ADCR0 to ADCR3. If one of the analog inputs of ANI4 to ANI7 (ANI12 to ANI15) is selected, the
conversion result is stored to the A/D conversion result register ADCR4 to ADCR7 (refer to Table 11-4).
Each time A/D conversion has been completed four times, A/D conversion end interrupt request (INTAD) is
generated.
Table 11-4. Correspondence between Analog Input and A/D Conversion Result Register
(select mode: 4-buffer mode)
Analog Input
ANI0/ANI8
A/D Conversion Result Register
ADCR0-ADCR3
ANI1/ANI9
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
ADCR4-ADCR7
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Figure 11-9. Operation Timing in Select Mode (4-buffer mode)
(a) TRG bit ← 0
A/D Conversion
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
Conversion Started
Conversion Ended
Conversion Ended
AM1, AM0←11
PS←0
ANIS2-ANIS0←011
ADCR0-
ADCR3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
(ADCR0) (ADCR1) (ADCR2) (ADCR3) (ADCR0) (ADCR1) (ADCR2)
INTAD
(b) TRG bit ← 1
INTP4
Initialization
Initialization
ANI3 ANI3
Initialization
ANI3 ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
A/D Conversion
Conversion Started
AM1, AM0←11
Conversion Ended
PS←0
ANIS2-ANIS0←011
ADCR0-
ADCR3
ANI3
(ADCR0)
ANI3
ANI3
(ADCR3)
ANI3
(ADCR0)
(ADCR0) (ADCR1) (ADCR2)
INTAD
11.4.3 Scan mode
In this mode, analog input pins specified by the ANIS0 to ANIS2 bits of the A/D converter mode register (ADM) are
sequentially selected, starting from ANI0 pin, and A/D conversion is executed. The result of the conversion is stored to the
A/D conversion result register that corresponds to an analog input on a one-to-one basis (refer to Table 11-5).
When all the analog inputs have been converted, the A/D conversion end interrupt request (INTAD) is generated.
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Table 11-5. Correspondence between Analog Input and A/D Conversion Result Register (scan mode)
Analog Input
ANI0/ANI8
A/D Conversion Result Register
ADCR0
ANI1/ANI9
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ANI2/ANI10
ANI3/ANI11
ANI4/ANI12
ANI5/ANI13
ANI6/ANI14
ANI7/ANI15
Figure 11-10. Operation Timing in Scan Mode
(a) TRG bit ← 0
A/D Conversion
ANI0
ANI1
ANI2
ANI0
ANI1
ANI2
ANI0
ANI1
Conversion Started
Conversion Ended
Conversion Ended
AM1, AM0←01
PS←0
ANIS2-ANIS0←010
ADCR0-
ADCR2
ANI0
ANI1
ANI2
ANI0
ANI1
ANI2
ANI0
(ADCR0) (ADCR1) (ADCR2) (ADCR0) (ADCR1) (ADCR2) (ADCR0)
INTAD
(b) TRG bit ← 1
INTP4
Initialization
Initialization
ANI1 ANI0
Initialization
ANI1 ANI0
A/D Conversion
ANI0
ANI1
ANI2
ANI0
ANI1
Conversion Started
Conversion Ended
AM1, AM0←01
PS←0
ANIS2-ANIS0←010
ADCR0-
ADCR2
ANI0
(ADCR0)
ANI0
ANI1
ANI2
ANI0
(ADCR0)
ANI0
(ADCR0)
(ADCR0) (ADCR1) (ADCR2)
INTAD
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11.4.4 A/D conversion operation start by software
An A/D conversion operation start by software is performed by writing a value to the A/D converter mode register (ADM)
that sets the TRG bit of the ADM register to 0 and the AM0 bit or AM1 bit to 1.
If a value is written to the ADM during an A/D conversion operation (AM0 bit or AM1 bit = 1) such that the TRG bit is
set to 0 and the AM0 bit or AM1 bit to 1 again, the A/D conversion operation being performed at that time is suspended,
and A/D conversion is started immediately in accordance with the written value.
Once A/D conversion operation is started, as soon as one A/D conversion operation ends the next A/D conversion
operation is started in accordance with the operating mode set by the ADM, and conversion operations continue repeatedly
until an instruction that writes to the ADM is executed.
When A/D conversion operation is started by software (TRG bit = 0), INTP4 pin (P25 pin) input does not affect the A/
D conversion operation.
(1) A/D conversion in select mode (1-buffer mode)
A/D conversion of the analog input set by the A/D converter mode register (ADM) is started. When conversion has
been completed, the same analog input is converted again. Each time A/D conversion has been completed, the
A/D conversion end interrupt request (INTAD) is generated.
Figure 11-11. A/D Conversion in Select Mode (1-buffer mode) Started by Software
A/D Conversion
ANI1
ANI1
ANI1
ANI1
ANI1
ANI1
ANI5
ANI5
ANI5
ADM Written
TRG←0
ADM Rewritten
TRG←0
AM1, AM0←10
PS←0
ANIS2-ANIS0←001
AM1, AM0←10
PS←0
ANIS2-ANIS0←101
ADCR1,
ADCR5
ANI1
ANI1
ANI1
ANI1
ANI1
(ADCR1)
ANI5
(ADCR5)
(ADCR1) (ADCR1) (ADCR1) (ADCR1)
INTAD
(2) A/D conversion in select mode (4- buffer mode)
The analog input set by the A/D converter mode register (ADM) is converted. One analog input is converted four
times. When A/D conversion has been executed four times, the same analog input is converted four times again.
Each time conversion has been executed four times, the A/D conversion end interrupt request (INTAD) is generated.
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Figure 11-12. A/D Conversion in Select Mode (4-buffer mode) Started by Software
A/D Conversion
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI5
ANI5
ANI5
ADM Written
TRG←0
ADM Rewritten
TRG←0
AM1, AM0←11
PS←0
ANIS2-ANIS0←011
AM1, AM0←11
PS←0
ANIS2-ANIS0←101
ADCR0-
ADCR7
ANI3
ANI3
ANI3
ANI3
ANI3
(ADCR0)
ANI5
(ADCR4)
(ADCR0) (ADCR1) (ADCR2) (ADCR3)
INTAD
(3) A/D conversion in scan mode
When conversion is started, analog inputs selected by the ANIS0 to ANIS2 bits of the A/D converter mode register
(ADM) are sequentially converted, starting from the ANI0 pin. When conversion of all the selected analog inputs
has been completed, the same operation (conversion from the ANI0 pin to the specified analog input pin) is repeated
again. When a series of A/D conversion from the ANI0 pin to the specified analog input has been completed, the
A/D conversion end interrupt request (INTAD) is generated.
Figure 11-13. A/D Conversion in Scan Mode Started by Software
A/D Conversion
ANI0
ANI1
ANI2
ANI0
ANI1
ANI0
ANI1
ANI0
ANI1
ADM Written
TRG←0
ADM Rewritten
TRG←0
AM1, AM0←01
PS←0
ANIS2-ANIS0←010
AM1, AM0←01
PS←0
ANIS2-ANIS0←001
ADCR0-
ADCR2
ANI0
ANI1
ANI2
ANI0
(ADCR0)
ANI0
ANI1
(ADCR0) (ADCR1) (ADCR2)
(ADCR0) (ADCR1)
INTAD
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11.4.5 A/D conversion operation start by hardware
An A/D conversion operation start by hardware is made possible by setting both the TRG bit and the AM0 bit or AM1
bit of the A/D converter mode register (ADM) to 1. When the TRG bit and the AM0 bit or AM1 bit of the ADM are both set
to 1, external signals are placed in the standby state, and an A/D conversion operation is started when a valid edge is input
to the INTP4 pin (P25 pin).
If another valid edge is input to the INTP4 pin after the A/D conversion operation has been started by a valid edge input
to the INTP4 pin, the A/D conversion operation being performed at that time is suspended, and A/D conversion is performed
from the beginning in accordance with the contents set in the ADM.
If a value is written to the ADM during an A/D conversion operation (AM0 bit or AM1 = 1) such that the TRG bit and AM0
bit or AM1 bit are both set to 1 again, the A/D conversion operation being performed at that time is suspended (the standby
state is also suspended), and a state is entered in which the A/D converter waits for input of a valid edge to the INTP4 pin
in the A/D conversion operation mode in accordance with the written value, and a conversion operation is started when
a valid edge is input.
Use of this function allows A/D conversion operations to be synchronized with external signals. Once A/D conversion
operation is started, as soon as one A/D conversion operation ends the next A/D conversion operation is started in
accordance with the operating mode set by the ADM (the A/D converter does not wait for INTP4 pin input), and conversion
operations continue repeatedly until an instruction that writes to the ADM is executed, or a valid edge is input to the INTP4
pin.
(1) A/D conversion in select mode (1-buffer mode)
A/D conversion of the analog input set by the A/D converter mode register (ADM) is started. When conversion has
been completed, the same analog input is converted again. Each time A/D conversion has been completed, the
A/D conversion end interrupt request (INTAD) is generated.
If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped
once, and then conversion is newly started.
Figure 11-14. A/D Conversion in Select Mode (1-buffer mode) Started by Hardware
INTP4
A/D Conversion
ADM Written
Standby State
ANI1
ANI1
ANI1
ANI1 Standby State
ANI5
ANI5
ADM Rewritten
TRG←1
TRG←1
AM1, AM0←10
PS←0
ANIS2-ANIS0←001
AM1, AM0←10
PS←0
ANIS2-ANIS0←101
ADCR1,
ADCR5
ANI1
(ADCR1)
ANI1
(ADCR1)
ANI5
(ADCR5)
INTAD
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(2) A/D conversion in select mode (4-buffer mode)
The analog input set by the A/D converter mode register (ADM) is converted. One analog input is converted four
times. When A/D conversion has been executed four times, the same analog input is converted four times again.
Each time conversion has been executed four times, the A/D conversion end interrupt request (INTAD) is generated.
If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped
once, and then conversion is newly started.
Figure 11-15. A/D Conversion in Select Mode (4-buffer mode) Started by Hardware
INTP4
Standby
State
Standby
State
A/D Conversion
ANI3
ANI3
ANI3
ANI3
ANI3
ANI3
ANI5
ADM Written
TRG←1
ADM Rewritten
TRG←1
AM1, AM0←11
PS←0
ANIS2-ANIS0←011
AM1, AM0←11
PS←0
ANIS2-ANIS0←101
ADCR0-
ADCR7
ANI3
ANI3
ANI3
ANI3
(ADCR3)
ANI3
(ADCR0)
(ADCR0) (ADCR1) (ADCR2)
INTAD
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(3) A/D conversion in scan mode
When conversion is started, analog inputs selected by the ANIS0 to ANIS2 bits of the A/D converter mode register
are sequentially converted, starting from the ANI0 pin. When conversion of all the selected analog inputs has been
completed, the same operation (conversion from the ANI0 pin to the specified analog input pin) is repeated again.
When a series of A/D conversion from the ANI0 pin to the specified analog input has been completed, the A/D
conversion end interrupt request (INTAD) is generated.
If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped
once, and then conversion is newly started.
Figure 11-16. A/D Conversion in Scan Mode Started by Hardware
INTP4
Standby
A/D Conversion
ANI0
ANI1
ANI2
ANI0 ANI0
Standby State
ANI0
ANI1
State
ADM Written
TRG←1
AM1, AM0←01
PS←0
ANIS2-ANIS0←010
ADM Rewritten
TRG←1
AM1, AM0←01
PS←0
ANIS2-ANIS0←001
ADCR0-
ADCR2
ANI0
ANI1
ANI2
(ADCR2)
ANI0
(ADCR0)
(ADCR0) (ADCR1)
INTAD
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CHAPTER 11 A/D CONVERTER
11.5 External Circuit of A/D Converter
The A/D converter is provided with a sample & hold circuit to stabilize its conversion operation. This sample & hold circuit
outputs sampling noise during sampling immediately after an A/D conversion channel has been changed.
To absorb this sampling noise, an external capacitor must be connected. If the impedance of the signal source is high,
an error may occur in the conversion result due to the sampling noise. Especially when the scan mode is used, the impedance
of the signal source must be kept low because the channel whose signal is to be converted changes one after another.
One way to absorb the sampling noise is to increase the capacitance of the capacitor. However, if the capacitance is
increased too much, the sampling noise is accumulated. Therefore, the most effective way is to reduce the resistance
component.
11.6 Cautions
(1) Range of voltages applied to analog input pins
The following must be noted concerning A/D converter analog input pins ANI0 to ANI15 (P70 to P77, P80 to P87).
•
A voltage outside the range AVSS to AVREF should not be applied to pins subject to A/D conversion during an A/
D conversion operation.
If this restriction is not observed, the µPD784054 may be damaged.
(2) Connecting capacitor to analog input pins
A capacitor should be connected between the analog input pins (ANI0 to ANI15) and AVSS and between the reference
voltage input pin (AVREF) and AVSS to prevent misoperation due to noise.
Be sure to connect the capacitor as close to ANI0 through ANI15 and AVREF as possible.
Figure 11-17. Example of Capacitor Connection on A/D Converter Pins
µPD784054
Analog
Input
ANI0-ANI15
100 to
500 pF
Reference
Voltage Input
AVREF
AVSS
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CHAPTER 11 A/D CONVERTER
(3) When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing (0) the AM0
bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit and AM1 bit remains set (1), the conversion
operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage comparator will
not be stopped, and therefore the A/D converter consumption current will not be reduced.
(4) Once the A/D converter starts operating, conversion operations are performed repeatedly until the AM0 bit and AM1
bit of the A/D converter mode (ADM) is cleared (0). Therefore, a superfluous interrupt may be generated if ADM
setting is performed after interrupt-related registers, etc., are set when A/D converter mode conversion, etc., is
performed. The result of this superfluous interrupt is that the conversion result storage address appears to have
been shifted when the scan mode is used. Also, when the select mode is used, the first conversion result appears
to have been an abnormal value, such as the conversion result for the other channel. It is therefore recommended
that A/D converter mode conversion be carried out using the following procedure.
<1> Write to the ADM
<2> Interrupt request flag (ADIF) clearance (0)
<3> Interrupt mask flag setting
Operations <1> to <3> should not be divided by an interrupt or macro service.
Alternatively, the following procedure is recommended.
<1> Stop the A/D conversion operation by clearing (0) the AM0 bit and AM1 bit of the ADM.
<2> Interrupt request flag (ADIF) clearance (0).
<3> Interrupt mask flag setting
<4> Write to the ADM
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
The µPD784054 incorporates two serial interface channels for which asynchronous serial interface (UART) mode or
3-wire serial I/O (IOE) mode can be selected.
The two UART/IOE channels have completely identical functions. In this chapter, therefore, unless stated otherwise,
UART/IOE1 will be described as representative of both UART/IOEs. When used as UART2/IOE2, the UART/IOE1 register
names, bit names and pin names should be read as their UART2/IOE2 equivalents as shown in Table 12-1.
Table 12-1. Differences Between UART/IOE1 and UART2/IOE2 Names
Item
UART/IOE1
UART2/IOE2
Pin names
P32/RxD/SI1, P33/TxD/SO1,
P34/ASCK/SCK1
P35/RxD2/SI2, P36/TxD2/SO2,
P37/ASCK2/SCK2
Asynchronous serial interface mode register
ASIM
ASIM2
Asynchronous serial interface mode register bit names
TXE, RXE, PS1, PS0, CL, SL,
ISRM, SCK
TXE2, RXE2, PS21, PS20, CL2,
SL2, ISRM2, SCK2
Asynchronous serial interface status register
Asynchronous serial interface status register bit names
Clocked serial interface mode register
Clocked serial interface mode register bit names
Baud rate generator control register
ASIS
ASIS2
PE, FE, OVE
PE2, FE2, OVE2
CSIM2
CSIM1
CTXE1, CRXE1, DIR1, CSCK1
BRGC
CTXE2, CRXE2, DIR2, CSCK2
BRGC2
Baud rate generator control register bit names
Interrupt request names
TPS0-TPS3, MDL0-MDL3
INTSR/ITCSI1, INTSER, INTST
TPS20-TPS23, MDL20-MDL23
INTSR2/INTCSI2, INTSER2,
INTST2
Interrupt control registers and bit names used in this
chapter
SRIC, CSIIC1, SERIC, STIC,
SRIF, CSIIF1, SERIF, STIF
SRIC2, CSIIC2, SERIC2, STIC2,
SRIF2, CSIIF2, SERIF2, STIF2
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
12.1 Switching between Asynchronous Serial Interface Mode and 3-wire Serial I/O Mode
The asynchronous serial interface mode and 3-wire serial I/O mode cannot be used simultaneously. Switching between
these modes is performed in accordance with the settings of the asynchronous serial interface mode register (ASIM/ASIM2)
and the clocked serial interface mode register (CSIM1/CSIM2) as shown in Figure 12-1.
Figure 12-1. Switching Between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode
7
6
5
4
3
2
1
0
Address
0FF88H
On Reset
00H
R/W
R/W
ASIM
TXE
RXE
PS1
PS0
CL
SL
ISRM SCK
ASIM2
0FF89H
00H
R/W
TXE2 RXE2 PS21 PS20
CL2
SL2 ISRM2 SCK2
Asynchronous serial interface mode operation
specification (refer to Figure 12-3)
TXE
RXE CTXE1 CRXE1
Operating Mode
TXE2 RXE2 CTXE2 CRXE2
Operation-stopped
mode
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
3-wire serial
I/O mode
Asynchronous
serial interface
mode
Other than the above
Setting prohibited
Address
0FF84H
7
6
5
0
4
0
3
0
2
1
0
0
On Reset
00H
R/W
R/W
CSIM1 CTXE1 CRXE1
DIR1 CSCK1
CSIM2
0FF85H
00H
R/W
CTXE2 CRXE2
0
0
0
DIR2 CSCK2
0
3-wire serial I/O mode operation specification
(refer to Figure 12-12)
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
12.2 Asynchronous Serial Interface Mode
A UART (Universal Asynchronous Receiver Transmitter) mode is incorporated as the asynchronous serial interface. With
this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible.
A baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates.
Also, the baud rate can be defined by scaling the clock input to the ASCK pin.
12.2.1 Configuration in asynchronous serial interface mode
The block diagram of the asynchronous serial interface is described in Figure 12-2.
Refer to 12.4 Baud Rate Generator for details of the baud rate generator.
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Figure 12-2. Block Diagram of Asynchronous Serial Interface
Internal Bus
1/8
TXE RXE PS1 PS0
1/8
ASIM, ASIM2
SL ISRM SCK
SL2 ISRM2 SCK2
1/8
CL
RXB, RXB2 Receive Buffer
RESET
TXE2 RXE2 PS21 PS20 CL2
ASIS, ASIS2
OVE
PE
FE
P32/R
P35/R
X
X
D,
D2
Transmit
Shift Register
TXS,
TXS2
RESET
Shift Register
PE2 FE2 OVE2
P33/T
X
D,
P36/T
X
D2
Transmission
Control Parity
Addition
Reception
Control
Parity Check
INTSER,
INTSER2
INTST,
INTST2
INTSR, INTSR2
Baud Rate Generator
1
1
m
m
f
CLK
1
Selector
n
2
P34/ASCK,
P37/ASCK2
Remark m = 16 to 30, n = 0 to 11
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(1) Receive buffer (RXB/RXB2)
This is the register that holds the receive data. Each time one byte of data is received, the receive data is transferred
from the shift register.
If a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of RXB/RXB2, and the MSB of RXB/RXB2
is always “0”.
RXB/RXB2 can be read only by an 8-bit manipulation instruction. The contents of RXB/RXB2 are undefined after
RESET input.
(2) Transmit shift register (TXS/TXS2)
This is the register in which the data to be transmitted is set. Data written to the TXS/TXS2 is transmitted as serial
data.
If a 7-bit data length is specified, bits 0 to 6 of the data written in the TXS/TXS2 are treated as transmit data. A transmit
operation starts when a write to the TXS/TXS2 is performed. The TXS/TXS2 cannot be written to during a transmit
operation.
TXS/TXS2 can be written to only by an 8-bit manipulation instruction. The contents of TXS/TXS2 are undefined after
RESET input.
(3) Shift register
This is the shift register that converts the serial data input to the RxD, and RxD2 pin to parallel data. When one byte
of data is received, the receive data is transferred to the receive buffer.
The shift register cannot be manipulated directly by the CPU.
(4) Reception control parity check
Receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode
register (ASIM/ASIM2). In addition, parity error and other error checks are performed during receive operations, and
if an error is detected, a value is set in the asynchronous serial interface status register (ASIS/ASIS2) according
to the type of error.
(5) Transmission control parity addition
Transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the transmit
shift registers (TXS and TXS2) in accordance with the contents set to the asynchronous serial interface mode
registers (ASIM and ASIM2).
(6) Selector
Selects the baud rate clock source.
12.2.2 Asynchronous serial interface control registers
(1) Asynchronous serial interface mode register (ASIM), Asynchronous serial interface mode register 2 (ASIM2)
The ASIM and ASIM2 are 8-bit registers that specify the UART mode operation.
These registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. The
format of ASIM and ASIM is shown in Figure 12-3.
These registers are cleared to 00H by RESET input.
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 12-3. Formats of Asynchronous Serial Interface Mode Register (ASIM) and
Asynchronous Serial Interface Mode Register 2 (ASIM2)
Address: 0FF88H, 0FF89H
On reset: 00H
R/W
7
6
5
4
3
2
1
0
ASIM
TXE
RXE
PS1
PS0
CL
SL
ISRM SCK
ASIM2 TXE2 RXE2 PS21 PS20 CL2
SL2 ISRM2 SCK2
TXE
RXE
Transmission/Reception
TXE2 RXE2
0
0
Disables transmission/reception,
or sets 3-wire serial I/O mode
Enables reception
0
1
1
1
0
1
Enables transmission
Enables transmission/reception
PS1
PS0
Specifies Parity Bit
PS21 PS20
0
0
0
1
No parity
Transmission: 0 parity appended
Reception: Parity error does not occur
Odd parity
1
1
0
1
Even parity
CL
CL2
0
Specifies Character Length of Data
7 bits
8 bits
1
SL
SL2
0
Specifies Stop Bit Length (transmission only)
1 bit
1
2 bits
ISRM Enables or Disables Occurrence of Reception
ISRM2 End Interrupt in Case of Reception ErrorNote
0
1
Enables
Disables
SCK
SCK2
0
Specifies Input Clock To Baud Rate Generator
External clock input (ASCK, ASCK2)
1
Internal clock (fCLK)
Remark fCLK: internal system clock
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Note To disable the reception completion interrupt when a reception error occurs, make sure that wait time
equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the
reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is not inserted, the
reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can
be calculated by the following expression:
2n+2
Wait time =
fCLK
Remark
fCLK : Internal system clock frequency
n
: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-
bit prescaler (n = 0 to 11)
Caution An asynchronous serial interface mode register (ASIM/ASIM2) rewrite should not be performed
during a transmit operation. If an ASIM/ASIM2 register rewrite is performed during a transmit
operation, subsequent transmit operations may not be possible (normal operation is restored by
RESET input). Software can determine whether transmission is in progress by using a
transmission completion interrupt (INTST/INTST2) or the interrupt request flag (STIF/STIF2) set by
INTST/INTST2.
(2) Asynchronous serial interface status register (ASIS), Asynchronous serial interface status register 2 (ASIS2)
The ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (1)
when a receive error occurs, and cleared (0) when data is read from the receive buffer (RXB/RXB2). If the next data
is received before RXB/RXB2 is read, the overrun error flag (OVE/OVE2) is set (1), and the other error flags are
cleared (0) (if there is an error in the next data, the corresponding error flag is set (1)).
These registers can be read only by an 8-bit manipulation instruction or bit manipulation instruction. The format of
ASIS and ASIS2 is shown in Figure 12-4.
These registers are cleared to 00H by RESET input.
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
Figure 12-4. Formats of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial
Interface Status Register 2 (ASIS2)
Address : 0FF8AH, 0FF8BH
On reset : 00H
R
7
0
6
0
5
0
4
0
3
0
2
1
0
ASIS
PE
FE
OVE
ASIS2
0
0
0
0
0
PE2
FE2 OVE2
PE
PE2
0
Parity Error Flag
Parity error does not occur
Parity error occurs
1
FE
FE2
0
Framing Error Flag
Framing error does not occur
Framing error occurs
1
OVE
OVE2
0
Overrun Error Flag
Reception overrun error does not occur
Reception overrun error occurs
1
Cautions 1. The receive buffer (RXB/RXB2) must be read even if there is a receive error. If RXB/RXB2 is not
read, an overrun error will occur when the next data is received, and the receive error state will
continue indefinitely.
2. To disable the reception completion interrupt when a reception error occurs, make sure that wait
time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse
after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is
not inserted, the reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate
clock can be calculated by the following expression:
2n+2
Wait time =
fCLK
Remark
fCLK : Internal system clock frequency
n
: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-
bit prescaler (n = 0 to 11)
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
12.2.3 Data format
Serial data transmission/reception is performed in full-duplex asynchronous mode.
The transmit/receive data format is shown in Figure 12-5. One data frame is made up of a start bit, character bits, parity
bit, and stop bit(s).
Character bit length specification, parity selection and stop bit length specification for one data frame are performed by
means of the asynchronous serial interface mode register (ASIM).
Figure 12-5. Data Format of Asynchronous Serial Interface Transmit/Receive
1 Data Frame
Start
Bit
Parity
Bit
Stop
Bit(s)
D0
D1
D2
D3
D4
D5
D6
D7
•
•
•
•
Start bit................... 1 bit
Character bits ........ 7 bits/8 bits
Parity bit ................. Even parity/odd parity/0 parity/no parity
Stop bit(s)............... 1 bit/2 bits
The serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate
generator settings. If a serial data receive error occurs, the nature of the receive error can be determined by reading the
asynchronous serial interface status register (ASIS) status.
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
12.2.4 Parity types and operations
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on
the transmission side and the reception side. With even parity and odd parity, 1 bit (odd number) errors can be detected.
With 0 parity and no parity, errors cannot be detected.
•
Even parity
If the number of bits with a value of “1” in the transmit data is odd, the parity bit is set to “1”, and if the number of “1”
bits is even, the parity bit is set to “0”. Control is thus performed to make the number of “1” bits in the transmit data
plus the parity bit an even number. In reception, the number of “1” bits in the receive data plus the parity bit is counted,
and if this number is odd, a parity error is generated.
•
•
•
Odd parity
Conversely to the case of even parity, control is performed to make the number of “1“ bits in the transmit data plus
the parity bit an odd number.
In reception, a parity error is generated if the number of “1” bits in the receive data plus the parity bit is even.
0 parity
In transmission, the parity bit is set to “0” irrespective of the receive data.
In reception, parity bit detection is not performed. Therefore, no parity error is generated irrespective of whether the
parity bit is “0” or “1”.
No parity
In transmission, a parity bit is not added.
In reception, reception is performed on the assumption that there is no parity bit. Since there is no parity bit, no parity
error is generated.
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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
12.2.5 Transmission
The µPD784054’s asynchronous serial interface is set to the transmission enabled state when the TXE bit of the
asynchronous serial interface mode register (ASIM) is set (1). A transmit operation is started by writing transmit data to
the transmit shift register (TXS) when transmission is enabled. The start bit, parity bit and stop bit(s) are added automatically.
When a transmit operation is started, the data in the TXS is shifted out, and a transmission completion interrupt (INTST)
is generated when the TXS is empty.
If no more data is written to the TXS, the transmit operation is discontinued.
If the TXE bit is cleared (0) during a transmit operation, the transmit operation is discontinued immediately.
Figure 12-6. Interrupt Timing of Asynchronous Serial Interface Transmission Completion
(a) Stop bit length: 1
STOP
D0
D1
D2
D6
D7
Parity
TxD (Output)
INTST
START
(b) Stop bit length: 2
STOP
D0
D1
D2
D6
D7
Parity
TxD (Output)
INTST
START
Cautions 1. After RESET input the transmit shift register (TXS) is emptied but a transmission completion
interrupt is not generated. A transmit operation can be started by writing transmit data to the TXS.
2. An asynchronous serial interface mode register (ASIM) rewrite should not be performed during
a transmit operation. If an ASIM rewrite is performed during a transmit operation, subsequent
transmit operations may not be possible (normal operation is restored by RESET input). Software
can determine whether transmission is in progress by using a transmission completion interrupt
(INTST) or the interrupt request flag (STIF) set by INTST.
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12.2.6 Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), receive operations are enabled
and sampling of the RxD input pin is performed.
RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band
rate generator control register (BRGC).
When the RxD pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal
is output on the m'th count. If the RxD pin input is low when sampled again by this start timing signal, the input is recognized
as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. When the
character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends.
When reception of one data frame ends, the receive data in the shift register is transferred to the receive buffer, RXB,
and a reception completion interrupt (INTSR) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of the ASIM
was cleared (0) when the error occurred, INTSR is generated.
If the ISRM was set (1), INTSR is not generated.
If the RXE bit is cleared (0) during a receive operation, the receive operation is stopped immediately. In this case the
contents of RXB and ASIS are not changed, and no INTSR or INTSER interrupt is generated.
Figure 12-7. Interrupt Timing of Asynchronous Serial Interface Reception Completion
STOP
D0
D1
D2
D6
D7
Parity
RxD (Input)
INTSR
START
Cautions 1. The receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun
error will occur when the next data is received, and the receive error state will continue indefinitely.
2. To disable the reception completion interrupt when a reception error occurs, make sure that wait
time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse
after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is
not inserted, the reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate
clock can be calculated by the following expression:
2n+2
Wait time =
fCLK
Remark
fCLK : Internal system clock frequency
n
: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-
bit prescaler (n = 0 to 11)
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12.2.7 Receive errors
Three kinds of errors can occur in a receive operation: parity errors, framing errors and overrun errors. As the result
of data reception, an error flag is raised in the asynchronous serial interface status register (ASIS) and a receive error
interrupt (INTSER) is generated. Receive error causes are shown in Table 12-2.
It is possible to detect the occurrence of any of the above errors during reception by reading the contents of the ASIS
(refer to Figures 12-4 and 12-8).
The contents of the ASIS register are cleared (0) by reading the receive buffer (RXB) or by reception of the next data
(if there is an error in the next data, the corresponding error flag is set).
Table 12-2. Causes of Receive Error
Receive Error
Parity error
Cause
Transmit data parity specification and receive data parity do not match
Stop bit not detected
Framing error
Overrun error
Reception of next data completed before data is read from receive buffer
Figure 12-8. Timing of Receive Error
STOP
RxD (Input)
D0
D1
D2
D6
D7
Parity
START
INTSRNote
INTSER
Note If a receive error occurs while the ISRM bit is set (1), INTSR is not generated.
Remark In the µPD784054, a break signal cannot be detected by hardware. As a break signal is a low-level signal
of two characters or more, a break signal may be judged to have been input if software detects the occurrence
of two consecutive framing errors in which the receive data was 00H. The chance occurrence of two
consecutive framing errors can be distinguished from a break signal by having the RxD pin level read by
software (confirmation is possible by setting “1” in bit 2 of the port 3 mode register (PM3) and reading port 3
(P3)) and confirming that it is “0”.
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are cleared (0) by reading
the receive buffer (RXB) or by reception of the next data. If you want to find the details of an error,
therefore, ASIS must be read before reading RXB.
2. The RXB must be read even if there is a receive error. If RXB is not read, an overrun error will occur
when the next data is received, and the receive error state will continue indefinitely.
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3. To disable the reception completion interrupt when a reception error occurs, make sure that wait
time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse
after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is
not inserted, the reception completion interrupt occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate
clock can be calculated by the following expression:
2n+2
Wait time =
fCLK
Remark
fCLK : Internal system clock frequency
n
: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-
bit prescaler (n = 0 to 11)
12.2.8 Transmitting/receiving data with macro service
When data is transmitted using a macro service, a vectored interrupt occurs two times. On the other hand, the
interrupt occurs only once when data is received using the macro service.
•
Transmitting/receiving data by using macro service
Transmission is started by writing data to the transmit shift register (TXS). If this is executed by using a macro service,
data is written to TXS and transmitted the specified number of times. The transmission end interrupt (INTST) that
occurs after completion of the transmission performs the macro service processing that writes the next data. When
the last data has been written to TXS, the macro service is completed (MSC = 0), and a vectored interrupt request
is generated (refer to <1> in Figure 12-9).
When data transmission is completed after that (when one frame has been transmitted), INTST is generated again,
and the vectored interrupt request is generated again (<2> in Figure 12-9).
To start a macro service by INTST in this way, therefore, a vectored interrupt is generated two times by the same
interrupt request (INTST in this case).
When reception is executed, however, a vectored interrupt request is not generated two times. Because macro service
processing that transfers received data to memory is executed by the reception and interrupt (INTSR) that occurs after
reception has been completed, a vectored interrupt request is generated only once after the macro service has been
completed.
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Figure 12-9. Transmission/Reception with Macro Service
(a) Transmission
Main Routine
EI
Macro Service Request
Macro Service Processing
Macro Service Processing
(INTST)
Last Macro Service Request
(INTST)
Interrupt request is generated
and accepted after end of macro
service (MSC = 0).
Vectored Interrupt Processing after
End of macro Service ... <1>
Transmission End Interrupt
(INTST)
Vectored Interrupt Processing after
End of UART Transmission ... <2>
(b) Reception
Main Routine
EI
Macro Service Request
(INTSR)
Macro Service Processing
Macro Service Processing
Last Macro Service Request
(INTSR)
Interrupt request is generated and
accepted after end of macro service
(MSC = 0).
Vectored Interrupt Processing
after End of Macro Service
Processing
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12.3 3-Wire Serial I/O Mode
The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface.
Basically, communication is performed using three lines: the serial clock (SCK), serial data output (SO), and serial data
input (SI). Handshaking lines are required when a number of devices are connected.
Figure 12-10. Example of 3-Wire Serial I/O System Configuration
3-wire serial I/O ↔ 3-wire serial I/O
Master CPU
Slave CPU
SCK
SCK
SI
SO
SI
Port (Interrupt)
Port
SO
Port
Note
Interrupt (Port)
Note Handshaking lines
12.3.1 Configuration in 3-wire serial I/O mode
The block diagram in the 3-wire serial I/O mode is shown in Figure 12-11.
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Figure 12-11. Block Diagram of 3-Wire Serial I/O Mode
Internal Bus
8
8
CSIM1, CSIM2
CTXE1 CRXE1 DIR1 CSCK1
CTXE2 CRXE2 DIR2 CSCK2
Direction Control Circuit
8
RESET
SIO1, SIO2
SO Latch
P32/SI1,
P35/SI2
Shift Register
D
Q
P33/SO1,
P36/SO2
N-ch Open-Drain
Output Possible
Interrupt Signal
Generator
P34/SCK1,
P37/SCK2
INTCSI1, INTCSI2
Serial Clock Counter
Baud Rate Generator
Selector
Serial Clock Control Circuit
CSCK1, CSCK2
CSCK1, CSCK2
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(1) Shift register (SIO1/SIO2)
The SIO1 and SIO2 convert 8-bit serial data to 8-bit parallel data, and vice versa. SIO1/SIO2 is used for both
transmission and reception.
Actual transmit/receive operations are controlled by writing to/reading from SIO1/SIO2.
Reading/writing can be performed by 8-bit manipulation instruction.
The contents of SIO1/SIO2 are undefined after RESET input.
(2) SO latch
The SO latch holds the SO1/SO2 pin output level.
(3) Serial clock selector
Selects the serial clock to be used.
(4) Serial clock counter
Counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/
reception has been performed.
(5) Interrupt signal generator
Generates an interrupt request when 8 serial clocks have been counted by the serial clock counter.
(6) Serial clock control circuit
Controls the supply of the serial clock to the shift register, and also controls the clock output to the SCK1/SCK2 pins
when the internal clock is used.
(7) Direction control circuit
Switches between MSB-first and LSB-first modes.
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12.3.2 Clocked serial interface mode registers (CSIM1, CSIM2)
The CSIM1 and CSIM2 are 8-bit registers that specify operations in the 3-wire serial I/O mode.
These registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. The CSIM1
and CSIM2 format is shown in Figure 12-12.
These registers are cleared to 00H by RESET input.
Figure 12-12. Formats of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface
Mode Register 2 (CSIM2)
Address : 0FF84H, 0FF85H
On reset: 00H
R/W
1
7
6
5
0
4
0
3
0
2
0
0
CTXE1 CRXE1
DIR1 CSCK1
CSIM1
CSIM2
CTXE2 CRXE2
DIR2 CSCK2
0
0
0
0
(n = 1, 2)
Transmission/Reception
CTXEn CRXEn
0
0
Disables transmission/reception,
or asynchronous serial interface mode
Enables reception
0
1
1
1
0
1
Enables transmission
Enables transmission/reception
DIRn
Specifies Operation Mode (transfer bit sequence)
0
1
MSB first
LSB first
CSCKn
Serial Clock Select Bit
Source Clock
SCKn
(when CTXEn,
CRXEn = 1)
0
1
External input clock to SCKn pin Input
Baud rate generator output
CMOS output
Caution Even if the DIRn (n = 1, 2) bit is changed after writing to the shift register (SIOn: n = 1, 2), data is output
with the setting before change. Therefore, set the DIRn bit before writing to SIOn.
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12.3.3 Basic operation timing
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit
by bit in MSB-first or LSB-first order in synchronization with the serial clock.
MSB/LSB switching is specified by the DIR1 bit of the clock serial interface mode register (CSIM1).
Transmit data is output in synchronization with the fall of SCK1, and receive data is sampled on the rise of SCK1.
An interrupt request (INTCSI1) is generated on the 8th rise of SCK1.
When the internal clock is used as SCK1, SCK1 output is stopped on the 8th rise of SCK1 and SCK1 remains high until
the next data transmit or receive operation is started.
3-wire serial I/O mode timing is shown in Figure 12-13.
Figure 12-13. Timing of 3-Wire Serial I/O Mode (1/2)
(a) MSB-first
SCK1Note
1
2
3
4
5
6
7
8
DI7 DI6 DI5
DI4 DI3 DI2 DI1
DI0
SI1 (Input)
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SO1 (Output)
INTCSI1
Transfer End
Interrupt Generation
Start of transfer synchronized with fall of SCK1
Execution of instruction that writes to SIO1, etc.
: Output
: Input
Master CPU
Slave CPU
Note
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Figure 12-13. Timing of 3-Wire Serial I/O Mode (2/2)
(b) LSB-first
SCK1Note
SI1 (Input)
1
2
3
4
5
6
7
8
DI0 DI1 DI2 DI3 DI4 DI5 DI6
DI7
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
SO1 (Output)
INTCSI1
Transfer End
Interrupt Generation
Start of transfer synchronized with fall of SCK1
Execution of instruction that writes to SIO1, etc.
: Output
: Input
Note Master CPU
Slave CPU
Remark If the µPD784054 is connected to a 2-wire serial I/O device, a buffer should be connected to the SO1 pin as
shown in Figure 12-14. In the example shown in Figure 12-14, the output level is inverted by the buffer, and
therefore the inverse of the data to be output should be written to SIO1.
In addition, non-connection of the internal pull-up resistor should be specified for the P33/SO1 pin.
Figure 12-14. Example of Connection to 2-Wire Serial I/O
µPD784054
2-Wire Serial I/O
Device
SCK1
SCK
SI1
SIO
SO1
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12.3.4 Operation when transmission only is enabled
A transmit operation is performed when the CTXE1 bit of clocked serial interface mode register (CSIM1) is set (1). The
transmit operation starts when a write to the shift register (SIO1) is performed while the CTXE1 bit is set (1).
When the CTXE1 bit is cleared (0), the SO1 pin is in the output high level.
(1) When the internal clock is selected as the serial clock
When transmission starts, the serial clock is output from the SCK1 pin and data is output in sequence from SIO1
to the SO1 pin in synchronization with the fall of the serial clock, and SI1 pin signals are shifted into SIO1 in
synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.
If transmission is disabled during the transmit operation (by clearing (0) the CTXE1 bit), SCK1 clock output is stopped
and the transmit operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is
not generated, and the SO1 pin becomes output high level.
(2) When an external clock is selected as the serial clock
When transmission starts, data is output in sequence from SIO1 to the SO1 pin in synchronization with the fall of
the serial clock input to the SCK1 pin after the start of transmission, and SI1 pin signals are shifted into SIO1 in
synchronization with the rise of the SCK1 pin input. If transmission has not started, shift operations are not performed
and the SO1 pin output level does not change even if the serial clock is input to the SCK1 pin.
If transmission is disabled during the transmit operation (by clearing (0) the CTXE1 bit), the transmit operation is
discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated,
and the SO1 pin becomes output high level.
12.3.5 Operation when reception only is enabled
A receive operation is performed when the CRXE1 bit of the clocked serial interface mode register (CSIM1) is set (1).
The receive operation starts when the CRXE1 changes from “0” to “1”, or when a read from shift register (SIO1) is performed.
(1) When the internal clock is selected as the serial clock
When reception starts, the serial clock is output from the SCK1 pin and the SI1 pin data is fetched in sequence into
shift register (SIO1) in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of reception and the first fall of SCK1.
If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), SCK1 clock output is stopped
and the receive operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is
not generated, and the contents of the SIO1 are undefined.
(2) When an external clock is selected as the serial clock
When reception starts, the SI1 pin data is fetched into shift register (SIO1) in synchronization with the rise of the
serial clock input to the SCK1 pin after the start of reception. If reception has not started, shift operations are not
performed even if the serial clock is input to the SCK1 pin.
If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), the receive operation is
discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated.
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12.3.6 Operation when transmission/reception is enabled
When the CTXE1 bit and CRXE1 bit of the clocked serial interface mode register (CSIM1) register are both set (1), a
transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/
receive operation is started when the CRXE1 bit is changed from “0” to “1”, or by performing a write to shift register (SIO1).
When a transmit/receive operation is started for the first time, the CRXE1 bit always changes from “0” to “1”, and there
is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first
transmit data should therefore be written to SIO1 beforehand when both transmission and reception are disabled (when
the CTXE1 bit and CRXE1 bit are both cleared (0)), before enabling transmission/reception.
When transmission/reception is disabled (CTXE1 = CRXE1 = 0), the SO1 pin is in the output high level.
(1) When the internal clock is selected as the serial clock
When transmission/reception starts, the serial clock is output from the SCK1 pin, data is output in sequence from
shift register (SIO1) to the (SO1) pin in synchronization with the fall of the serial clock, and SI1 pin data is shifted
in order into SIO1 in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, SCK1 clock output is stopped and the transmit and receive
operations are discontinued on the next rise of SCK1. When transmission and reception are disabled simultaneously,
the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output
high level.
(2) When an external clock is selected as the serial clock
When transmission/reception starts, data is output in sequence from shift register (SIO1) to the SO1 pin in
synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission/reception, and
SI1 pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. If transmission/reception
has not started, the SIO1 shift operations are not performed and the SO1 pin output level does not change even
if the serial clock is input to the SCK1 pin.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and
subsequent SCK1 input is ignored. When transmission and reception are disabled simultaneously, the contents of
SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level.
12.3.7 Corrective action in case of slippage of serial clock and shift operations
When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and
shift operations due to noise, etc. In this case, since the serial clock counter is initialized by disabling both transmit operations
and receive operations (by clearing (0) the CTXE1 bit and CRXE1 bit), synchronization of the shift operations and the serial
clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock.
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12.4 Baud Rate Generator
The baud rate generator is the circuit that generates the UART/IOE serial clock. Two independent circuits are
incorporated, one for each serial interface.
12.4.1 Baud rate generator configuration
The baud rate generator block diagram is shown in Figure 12-15.
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Figure 12-15. Block Diagram of Baud Rate Generator
Start Bit Detection
Internal Bus
1/8
RESET
1/8
8
CSIM1, CSIM2
ASIM, ASIM2
BRGC, BRGC2
Asynchronous Serial
Interface Mode
Registers
Clocked Serial
Interface Mode
Registers
Baud Rate Generator
Control Register
5-Bit Counter
RESET
Clear
1/2
Start Bit Detection
Sampling Clock
Match
UART Reception
Shift Clock
CSCK1,
CSCK2
SCK,
SCK2
Shift Clock
for UART
Transmission
& IOE
Match
Selector
1/2
Selector
fCLK
fPRS
Frequency
Divider
Selector
Selector
CSCK1,
CSCK2
5-Bit Counter
P34/ASCK/SCK1,
P37/ASCK2/SCK2
BRGC Write
RESET
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(1) 5-bit counter
Counter that counts the clock (fPRS) by which the output from the frequency divider is selected. Generates a signal
with the frequency selected by the low-order 4 bits of the baud rate generator control registers (BRGC/BRGC2).
(2) Frequency divider
Scales the internal clock (fCLK) or, in asynchronous serial interface mode, a clock that is twice the external baud rate
input (ASCK/ASCK2), and selects fPRS with the next-stage selector.
(3) Both-edge detection circuit
Detects both edges of the ASCK/ASCK2 pin input signal and generates a signal with a frequency twice that of the
ASCK/ASCK2 input clock.
12.4.2 Baud rate generator control register
The BRGC and BRGC2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift
clock in 3-wire serial I/O mode.
These registers can be read or written to with an 8-bit manipulation instruction. The BRGC and BRGC2 format is shown
in Figure 12-16.
RESET input clears the BRGC register to 00H.
Caution When a baud rate generator control register (BRGC, BRGC2) write instruction is executed, the 5-bit
counter and 1/2 frequency divider operations are reset. Consequently, if a write to the BRGC and
BRGC2 is performed during communication, the generated baud rate clock may be disrupted,
preventing normal communication from continuing. The BRGC and BRGC2 should therefore not be
written to during communication.
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Figure 12-16. Formats of Baud Rate Generator Control Register (BRGC) and
Baud Rate Generator Control Register 2 (BRGC2)
Address: 0FF90H, 0FF91H
On reset: 00H
R/W
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
BRGC
TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20
BRGC2
TPS3 TPS2 TPS1 TPS0
TPS23 TPS22 TPS21 TPS20
n
Selects Prescaler
Output (fPRS)
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fCLK/2, fASCK/2 Note 1
0
fCLK/4, fASCK/4
0
2
fCLK/8, fASCK/8
0
3
fCLK/16, fASCK/16
fCLK/32, fASCK/32
fCLK/64, fASCK/64
fCLK/128, fASCK/128
fCLK/256, fASCK/256
fCLK/512, fASCK/512
0
4
0
5
0
6
0
7
1
8
1
1
9
fCLK/1024, fASCK/1024
fCLK/2048, fASCK/2048
fCLK/4096, fASCK/4096
10
11
1
Other
Setting prohibited
MDL3 MDL2 MDL1 MDL0
MDL23 MDL22 MDL21 MDL20
k
Input Clock of Baud
Rate Generator Note 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
fPRS/16
fPRS/17
fPRS/18
fPRS/19
fPRS/20
fPRS/21
fPRS/22
fPRS/23
fPRS/24
fPRS/25
10 fPRS/26
11 fPRS/27
12 fPRS/28
13 fPRS/29
14 fPRS/30
Note 3
15 fPRS
Notes 1. This cannot be selected when k = 15 is selected by MDL3 to MDL0 (MDL23 to MDL20).
2. Only fPRS/16 can be selected when ASCK (ASCK2) input is used.
3. This can be used only in the 3-wire serial I/O mode.
Remark fASCK : ASCK (ASCK2) input clock
fCLK : internal system clock
fPRS : Selected clock of prescaler output
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12.4.3 Baud rate generator operation
The baud rate generator only operates when UART/IOE transmit/receive operations are enabled. The generated baud
rate clock is a signal scaled from the internal clock (fCLK) or a signal scaled from the clock input from the external baud rate
input (ASCK) pin.
Caution If a write to the baud rate generator control register (BRGC) is performed during communication, the
generated baud rate clock may be disrupted, preventing normal communication from continuing. The
BRGC should therefore not be written to during communication.
(1) Baud rate clock generation in UART mode
(a) Using internal clock (fCLK)
This function is selected by setting (1) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).
The internal clock (fCLK) is scaled by the frequency divider, this signal (fPRS) is scaled by the 5-bit counter, and
the signal further divided by 2 is used as the baud rate. The baud rate is given by the following expression:
fCLK
(Baud rate) =
(k + 16) • 2n + 2
fCLK : Internal system clock frequency
k
: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14)
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)
n
(b) Using external baud rate input
This function is selected by clearing (0) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).
When this function is used, bit MDL3 to bit MDL0 of the baud rate generator control register (BRGC) must all
be cleared (0) (k= 0).
Set P34 pin (when used with UART2, set P37 pin) in the control mode by using the port 3 mode control register
(PMC3).
The ASCK pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by
32 (fPRS) (division by 16 and division by 2) is used as the baud rate. The baud rate is given by the following
expression:
f
ASCK
(Baud rate) =
2n+6
fASCK: ASCK pin input clock frequency
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)
n
When this function is used, a number of baud rates can be generated by one external input clock.
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(3) Serial clock generation in 3-wire serial I/O mode
Selected when the CSCK1 bit of the clocked serial interface mode register 1 (CSIM1) is set (1) and SCK1 is output.
(a) Normal mode
The internal clock (fCLK) is scaled by the frequency divider, this signal (fPRS) is scaled by the 5-bit counter, and
the signal further divided by 2 is used as the serial clock. The serial clock is given by the following expression:
fCLK
(Serial clock) =
(k + 16) • 2n + 2
fCLK : Internal system clock frequency
k
: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14)
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)
n
(b) High-speed mode
When this function is used, bit MDL3 to bit MDL0 of the baud rate generator control register (BRGC) are all set
(1) (k= 15).
The internal clock (fCLK) is scaled by the frequency divider, and this signal (fPRS) divided by 2 is used as the serial
clock. The serial clock is given by the following expression:
fCLK
(Serial clock) =
2n + 2
fCLK : Internal system clock frequency
n
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 1 to 11)
12.4.4 Baud rate setting in asynchronous serial interface mode
There are two methods of setting the baud rate, as shown in Table 12-3.
This table shows the range of baud rates that can be generated, the baud rate calculation expression and selection
method for each case.
Table 12-3. Methods of Baud Rate Setting
Baud Rate Calculation
Baud Rate Clock Source
Selection Method
Baud Rate Range
Expression
fCLK
fCLK
fCLK
64
Baud rate generator Internal system clock SCK in ASIM = 1
_
_
(k + 16)•2n + 2
245760
fASCK
Note
fASCK
64
fASCK
2n+6
ASCK input
SCK in ASIM = 0
131072
fCLK : Internal system clock frequency
k
: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14; refer to Figure 12-16)
n
: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11; refer to Figure 12-16)
fCLK
fASCK : ASCK input clock frequency (0 –
)
2
fCLK
Note Including fASCK input range: (0 –
)
128
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(1) Examples of settings when baud rate generator is used
Examples of baud rate generator control register (BRGC) settings when the baud rate generator is used are shown
below.
When the baud rate generator is used, the SCK bit of the asynchronous serial interface mode register (ASIM) should
be set (1).
Table 12-4. Examples of BRGC Settings When Baud Rate Generator Is Used
Internal System Clock
(fCLK)
16.0 MHz
12.5 MHz
10.0 MHz
8.0 MHz
Baud Rate
[bps]
BRGC Baud Rate Error BRGC Baud Rate Error BRGC Baud Rate Error BRGC Baud Rate Error
Value
BAH
B2H
AAH
9AH
8AH
7AH
6AH
5AH
4AH
3AH
30H
2AH
1AH
(%)
Value
B4H
ACH
A4H
94H
84H
74H
64H
54H
44H
34H
29H
24H
14H
(%)
Value
B0H
A6H
A0H
90H
80H
70H
60H
50H
40H
30H
24H
20H
10H
(%)
Value
AAH
A2H
9AH
8AH
7AH
6AH
5AH
4AH
3AH
2AH
20H
1AH
0AH
(%)
75
0.16
1.36
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
1.73
0.92
1.73
1.73
1.73
1.73
1.73
1.73
1.73
1.73
0.00
1.73
1.73
1.73
0.88
1.73
1.73
1.73
1.73
1.73
1.73
1.73
1.73
0.00
1.73
1.73
0.16
1.36
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
110
150
300
600
1200
2400
4800
9600
19200
31520
38400
76800
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(2) Examples of settings when external baud rate input (ASCK) is used
Table 12-5 shows an example of setting when external baud rate input (ASCK) is used. When using the ASCK input,
clear (0) the SCK bit of the asynchronous serial interface mode register (ASIM), and set P34 pin (when used with
UART2, set P37 pin) in the control mode by using port 3 mode control register (PMC3).
Table 12-5. Examples of Settings When External Baud Rate Input (ASCK) Is Used
fASCK
153.6 kHz
4.9152 MHz
(ASCK Input Frequency)
Baud Rate [bps]
75
BRGC Value
BRGC Value
A0H
50H
40H
30H
20H
10H
00H
—
150
90H
300
80H
600
70H
1200
60H
2400
50H
4800
40H
9600
—
30H
19200
38400
76800
—
20H
—
10H
—
00H
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12.5 Cautions
(1) An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation.
If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible
(normal operation is restored by RESET input). Software can determine whether transmission is in progress by using
a transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by INTST.
(2) After RESET input the transmit shift register (TXS) is emptied but a transmission completion interrupt is not
generated. A transmit operation can be started by writing transmit data to the TXS.
(3) The receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun error will occur
when the next data is received, and the receive error state will continue indefinitely.
(4) To disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent
to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs
until the receive buffers (RXB, RXB2) are read. If the wait time is not inserted, the reception completion interrupt
occurs even when it is disabled.
The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be
calculated by the following expression:
2n+2
Wait time =
fCLK
Remark
fCLK : Internal system clock frequency
n
: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-bit
prescaler (n = 0 to 11)
(5) The contents of the asynchronous serial interface status register (ASIS) are cleared (0) by reading the receive buffer
(RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read before
reading RXB.
(6) In the 3-wire serial I/O mode, even if the DIRn (n = 1, 2) bit of the clocked serial interface mode register (CSIMn:
n = 1, 2) is changed after writing to the shift register (SIOn: n = 1, 2), data is output with the setting before change.
Therefore, set the DIRn bit before writing to SIOn.
(7) The baud rate generator control register (BRGC) should not be written to during communication. If a write instruction
is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock
may be disrupted, preventing normal communication from continuing.
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(8) The start bit may not be output correctly if the timing at which the shift register shifts data conflicts with a write to
the shift register in asynchronous serial interface mode.
When writing data to the shift register, restart the baud rate generator to prevent the timing at which the UART shift
register shifts data matching the timing of a write to the shift register is performed. At this time, disable
acknowledgement of interrupt requests, as shown in the preventive program below, so that the UART transmission
enable and the write processing to the shift register can be performed successively. At the same time, disable the
activation and operation of the macro service during UART transmission. In addition, set the data to be transmitted
next to the shift register after the time of 1/2 the bits of the baud rate has elapsed after the transmission end flag
was set.
[Flowchart of preventive program]
No
Interrupt servicing or transmission
end flag check
Transmission end flag = 1
Yes
Wait for 1/2 bits of baud rate
Disable interrupts
Disable UART transmission (baud rate generator stopped)
Enable UART transmission (baud rate generator activated)
Write to the shift register
DI
CLR1 TXE
SET1 TXE
MOV TXS, #byte
EI
Enable interrupts
Note that the relationship between the division ratio of the internal system clock to the oscillation frequency and the
baud rate must satisfy the following expressions <1> to <4> when the above preventive program is used.
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• When high-speed fetch is selected (the IFCH bit of the memory expansion mode register (MM) is set to 1) and
the internal clock is specified as the clock to generate the baud rate clock:
(k+15) × 2n+3 > 17 × a ..... <1>
• When high-speed fetch is selected (the IFCH bit of the memory expansion mode register (MM) is set to 1) and
the clock input from the ASCK pin is specified as the clock to generate the baud rate clock:
15 × 2n+2/fASCK > 17 × a/fXX ..... <2>
• When normal fetch is selected (the IFCH bit of the memory expansion mode register (MM) is set to 0) and the
internal clock is specified as the clock to generate the baud rate clock:
(k+15) × 2n+3 > {3 × (3+b+c)+13} × a ..... <3>
• When normal fetch is selected (the IFCH bit of the memory expansion mode register (MM) is set to 0) and the clock
input from the ASCK pin is specified as the clock to generate the baud rate clock:
15 × 2n+2/fASCK > {3 × (3+b+c)+13} × a/fXX ..... <4>
Remark fXX:
Oscillation frequency or external clock input frequency
fASCK: Frequency of clock input from ASCK pin
a:
b:
c:
k:
n:
Division ratio of internal clock to oscillation frequency
Access wait value to read/write when external memory is accessed
Address wait value to address output when external memory is accessed
Set value of the MDL3 to MDL0 bits (MDL23 to MDL20) of the BRGC (BRGC2) register
Set value of the TPS3 to TPS0 bits (TPS23 to TPS20) of the BRGC (BRGC2) register
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<Formats of Baud Rate Generator Control Register (BRGC) and Baud Rate Generator Control Register 2 (BRGC2)>
Address: 0FF90H, 0FF91H
On reset: 00H
R/W
7
6
5
4
3
2
1
0
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
BRGC2 TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20
TPS3 TPS2 TPS1 TPS0
TPS23 TPS22 TPS21 TPS20
n
Selects Prescaler
Output (fPRS
)
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
f
f
f
f
f
f
f
f
f
f
XX/4, fASCK/2Note 1
0
XX/8, fASCK/4
0
XX/16, fASCK/8
0
XX/32, fASCK/16
XX/64, fASCK/32
XX/128, fASCK/64
XX/256, fASCK/128
XX/512, fASCK/256
XX/1024, fASCK/512
XX/2048, fASCK/1024
0
0
0
0
1
1
1
10 fXX/4096, fASCK/2048
11 fXX/8192, fASCK/4096
Setting prohibited
1
Other
MDL3 MDL2 MDL1 MDL0
MDL23 MDL22 MDL21 MDL20
k
Input Clock of Baud
Rate GeneratorNote 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
f
f
f
f
f
f
f
f
f
f
PRS/16
PRS/17
PRS/18
PRS/19
PRS/20
PRS/21
PRS/22
PRS/23
PRS/24
PRS/25
10 fPRS/26
11 fPRS/27
12 fPRS/28
13 fPRS/29
14 fPRS/30
Note 3
15 fPRS
Notes 1. This cannot be selected when k = 15 is selected by MDL3 through MDL0 (MDL23 through MDL20).
2. Only fPRS/16 can be selected when ASCK (ASCK2) input is used.
3. This can be used only in the 3-wire serial I/O mode.
Remark fASCK : ASCK (ASCK2) input clock
fXX
: Oscillation frequency or external clock input frequency
fPRS : Selected clock of prescaler output
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[Usage example for expression <3>]
For example, assume that when normal fetch is selected and the internal clock is specified as the clock to generate the
baud rate clock, no waits are set to the external memory (b = c = 0), and the highest baud rate is set (k = n = 0).
Under these conditions, the result of expression <3> is as follows.
a < 5.45
This example shows that 1/2 or 1/4 of the oscillation frequency can be used for the internal system clock, but not for 1/
8 or 1/16.
[Cautions on using preventive program]
This bug also occurs if the timing at which the UART shift register shifts data matches a write to the shift register when
the UART transmission is performed using a macro service. This bug, however, can be prevented if the following three
methods are implemented (these methods eliminate the timing that causes this bug.)
• Activate the macro service immediately after enabling UART transmission (SET1 TXE).
• Set a longer cycle for the baud rate than the time from a macro service request to its termination.
• Make sure that the macro service for UART transmission is not held pending by another macro service. (When UART
transmission is performed using a macro service, disable the processing of other macro service requests with a higher
priority.)
The execution time from a macro service request to its termination is the sum of a, b, and c in the figure below.
a
b
c
Interrupt request flag
Instruction
Macro service
a: Time for judging the interrupt priority after the interrupt request flag is set
It takes 8 system clocks to judge the interrupt priority after the interrupt request flag is set.
b: Time from when the interrupt request flag is set until the instruction being executed is terminated
The macro service is executed when the instruction that was being executed when the interrupt request flag was set
is terminated. If the instruction being executed is an instruction to hold the macro service pending temporarily, the
macro service is acknowledged when the instruction after instruction is terminated.
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[Instruction to hold the macro service pending temporarily]
• EI
• RETCSB !addr16
• RETI
• POP PSW
• DI
• POPU post
• BRK
• BRKCS
• RETCS
• RETB
• MOV PSWL,A
• MOV PSWL,#byte
• MOVG SP,#imm24
• LOCATION 0H
• LOCATION 0FH
• Write and bit manipulation instructions for the interrupt control registers, MK0, MK1L, IMC, ISPR, SNMNote 1
• Bit manipulation instruction of PSWNote 2
Notes 1. Except for the BT, BF instructions
2. Except for the following instructions
• BT PSWL.bit,$ADDR20
• BF PSWL.bit,$ADDR20
• BT PSWH.bit,$ADDR20
• BF PSWH.bit,$ADDR20
• SET1 CY
• NOT1 CY
• CLR1 CY
c: Time for macro service processing
The macro service processing time when data is transferred to the SFR is shown below.
Macro Service Processing Type
Data Area
IRAM
Other
–
Memory to SFR
(1 byte)
Block transfer mode:
: BLKTRS
24
Block transfer mode (with memory pointer)
: BLKTRS-P
30
32
Unit: Clock = 1/fCLK
Remarks 1. Add the number of waits (number of clocks) at data access to the above value when using the data area
as external memory or internal ROM not specified for high-speed fetch (EMEM16, EMEM8).
2. IRAM:
Internal high-speed RAM
EMEM16: Memory that is external memory or internal ROM not specified for high-speed fetch, and is set
to a 16-bit bus width.
EMEM8: Memory that is external memory or internal ROM not specified for high-speed fetch, and is set
to an 8-bit bus width.
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CHAPTER 13 EDGE DETECTION FUNCTION
P20 to P27 have an edge detection function that allows a rising edge/falling edge to be set programmably, and the
detected edge is sent to internal hardware. The relation between pins P20 to P27 and the use of the detected edge is shown
in Table 13-1.
Table 13-1. Pins P20 to P27 and Use of Detected Edge
Pin
Use
Detected Edge Specification Register
INTM0
P20 NMI, standby circuit control
P21 INTP0, CC00 capture signal of timer 0
P22 INTP1, CC01 capture signal of timer 0
P23 INTP2, CC02 capture signal of timer 0
P24 INTP3, CC03 capture signal of timer 0
P25 INTP4, conversion start signal of A/D converter
P26 INTP5
INTM1
P27 INTP6
The edge detection function operates at all times except in STOP mode and IDLE mode (although the edge detection
function for pin P20 also operates in STOP mode and IDLE mode).
For pins P21 to P27, the noise elimination time when edge detection is performed can be selected by software.
13.1 Edge Detection Function Control Registers
13.1.1 External interrupt mode registers (INTM0, INTM1)
The INTMn (n = 0, 1) specify the valid edge to be detected on pins P20 to P27. The INTM0 specifies the valid edge
for pins P20 to P23, and the INTM1 specifies the valid edge for pins P24 to P27.
The INTMn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format
of INTM0 and INTM1 are shown in Figures 13-1 and 13-2 respectively.
RESET input clears these registers to 00H.
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Figure 13-1. Format of External Interrupt Mode Register 0 (INTM0)
Address: 0FF3CH
7
On reset: 00H
R/W
6
5
4
3
2
1
0
0
INTM0 ES21 ES20 ES11 ES10 ES01 ES00
ESNMI
ES21 ES20 Specifies Edge To Be Detected of P23
(INTP2, CC02 capture trigger) pin input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES11 ES10 Specifies Edge To Be Detected of P22
(INTP1, CC01 capture trigger) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES01 ES00 Specifies Edge To Be Detected of P21
(INTP0, CC00 capture trigger) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ESNMI Specifies Edge To Be Detected of P20 (NMI) Pin Input
0
1
Falling edge
Rising edge
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Figure 13-2. Format of External Interrupt Mode Register 1 (INTM1)
Address : 0FF3DH
7
On reset : 00H
R/W
6
5
4
3
2
1
0
INTM1 ES61 ES60 ES51 ES50 ES41 ES40 ES31 ES30
ES61 ES60 Specifies Edge To Be Detected of P27
(INTP6) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES51 ES50 Specifies Edge To Be Detected of P26
(INTP5) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES41 ES40 Specifies Edge To Be Detected of P25 (INTP4,
A/D conversion start trigger) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES31 ES30 Specifies Edge To Be Detected of P24
(INTP3, CC03 capture trigger) Pin Input
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Caution If the valid edge is changed by writing to the external interrupt mode register (INTMn: n = 0, 1), the valid
edge is not detected. If the edge is input while the valid edge is changed, whether the input edge is
judged as the valid edge or not is undefined.
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CHAPTER 13 EDGE DETECTION FUNCTION
13.1.2 Interrupt valid edge flag registers (IEF1, IEF2)
IEF1 and IEF2 are flag registers that indicate which of the rising or falling edge is generated when an edge is detected
by the INPT0 to INTP6 pin. By checking these flag registers, which of the rising or falling edge is generated can be determined
if both the rising and falling edges are specified as the valid edge of an interrupt.
These registers can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figures
13-3 and 13-4 show the formats of IEF1 and IEF2.
The values of these registers are undefined when RESET is input.
Figure 13-3. Format of Interrupt Valid Edge Flag Register 1 (IEF1)
Address : 0FF3EH
7
On reset : undefined
R/W
6
5
4
3
2
1
0
IEF1
IEFH3 IEFL3 IEFH2 IEFL2 IEFH1 IEFL1 IEFH0 IEFL0
IEFHn
Rising Edge Flag of INTPn Pin (n = 0 to 3)
Rising edge is not generated
0
1
Rising edge is generated
IEFLn
Falling Edge Flag of INTPn Pin (n = 0 to 3)
Falling edge is not generated
0
1
Falling edge is generated
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Figure 13-4. Format of Interrupt Valid Edge Flag Register 2 (IEF2)
Address : 0FF3FH
7
On reset : undefined
R/W
6
0
5
4
3
2
1
0
IEF2
0
IEFH6 IEFL6 IEFH5 IEFL5 IEFH4 IEFL4
IEFHn
Rising Edge Flag of INTPn Pin (n = 4 to 6)
Rising edge is not generated
0
1
Rising edge is generated
IEFLn
Falling Edge Flag of INTPn Pin (n = 4 to 6)
Falling edge is not generated
0
1
Falling edge is generated
Cautions 1. After checking the flag, clear the flag to “0” by software.
2. The interrupt valid edge flag register (IEFn: n = 1, 2) indicates that an edge has been generated,
and has nothing to do with specification of a valid edge. For example, if the valid edge of the INTP0
pin is specified to be the rising edge, and if the falling edge is generated, the interrupt request
signal is not generated, but the IEFL0 flag is set to “1”.
3. If the INTPn (n = 0 to 6) pin is “1” after the reset signal has been deasserted, the rising edge is
recognized, and the IEFHn (n = 0 to 6) flag is set to “1”. Even when the IEFHn flag is used as a
digital port (P21 to P27), it may be set to 1. Be sure to clear (0) the IEFHn flag before checking the
edge of an external interrupt.
13.1.3 Noise protection control register (NPC)
NPC is a register that specifies a sampling clock used to reject the digital noise on the P21/INTP0 to P27/INTP6 pins.
This register is read or written by using an 8-bit manipulation instruction or a bit manipulation instruction.
Figure 13-5 shows the format of NPC.
The value of this register is cleared to 00H when RESET is input.
Figure 13-5. Format of Noise Protection Control Register (NPC)
Address : 0FF3BH
7
On reset : undefined
R/W
6
5
4
3
2
1
0
NPC
0
NI6
NI5
NI4
NI3
NI2
NI1
NI0
(fCLK = 16 MHz)
NIn Specifies Sampling Clock to Reject Noise on INTPn Pin
(n = 0 to 6) Pulse Width Minimum Pulse Width
Rejected as Noise Recognized as Signal
0
1
fCLK
3/fCLK (0.19 µs)
12/fCLK (0.75 µs)
4/fCLK (0.25 µs)
16/fCLK (1.0 µs)
fCLK/4
Remark fCLK: internal system clock
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CHAPTER 13 EDGE DETECTION FUNCTION
13.2 Edge Detection for Pin P20
On pin P20 noise elimination is performed by means of analog delay before edge detection. Therefore, an edge cannot
be detected unless the pulse width is a given time (10 µs) or longer.
Figure 13-6. Edge Detection for Pin P20
10
µ
s (MIN.)
P20 Input
10 µs
(MAX.)
10
(MAX.)
µ
s
P20 Input Signal after
Noise Elimination
Rising Edge
Falling Edge
Short Pulse
Eliminated as Noise
Rising Edge Detected Since
Pulse Is Sufficiently Wide
Short Pulse
Eliminated as Noise
Falling Edge Detected Since
Pulse is Sufficiently Wide
Caution Since analog delay noise elimination is performed on pin P20, an edge is detected up to 10 µs after it
is actually input. Also, unlike pins P21 to P27, the delay before an edge is detected is not a specific
value, because of differences in the characteristics of various devices.
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13.3 Pin Edge Detection for Pins P21 to P27
Edge detection for pins P21 to P27 is performed after digital noise elimination by means of clock sampling. The sampling
clock is fixed to fCLK.
In digital noise elimination, input is sampled using the fCLK clock, and if the input level is not the same at least four times
in succession (if it is the same only three or fewer times in succession), it is eliminated as noise. Therefore, the level must
be maintained for at least 4 fCLK clock cycles (0.25 µs: fCLK = 16 MHz, fCLK = 1/2 fXX, fXX = 32 MHz) in order to be recognized
as a valid edge.
Figure 13-7. Edge Detection for Pins P21 to P27
Pins P21 to P27
fCLK
P21 to P27 Input Signal
after Noise Elimination
Rising Edge
Falling Edge
Digital Noise Elimination
with fCLK Clock
Cautions 1. Since digital noise elimination is performed with the fCLK clock, there is a delay of 4 fCLK clocks
between input of an edge to the pin and the point at which the edge is actually detected.
2. If the input pulse width is 4 fCLK clocks, it is uncertain whether a valid edge will be detected.
Therefore, to ensure reliable operation, the level should be held for at least 4 clocks.
3. If noise input to a pin is synchronized with the fCLK clock in the µPD784054, it may not be recognized
as noise. If there is a possibility of such noise being input, noise should be eliminated by adding
a filter to the input pins.
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CHAPTER 13 EDGE DETECTION FUNCTION
13.4 Cautions
(1) Valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode
register (INTMn: n = 0, 1). Also, if an edge is input during a change of the valid edge, that edge may or may not
be judged to be a valid edge.
(2) After checking the flag by using the interrupt valid edge flag register (IEFn: n = 1, 2), clear the flag to “0” by software.
(3) The interrupt valid edge flag register (IEFn: n = 1, 2) indicates that an edge has been generated, and has nothing
to do with specification of a valid edge. For example, if the valid edge of the INTP0 pin is specified to be the rising
edge, and if the falling edge is generated, the interrupt request signal is not generated, but the IEFL0 flag is set to
“1”.
(4) If the INTPn (n = 0 to 6) pin is “1” after the reset signal has been deasserted, the rising edge is recognized, and the
IEFHn (n = 0 to 6) flag of the interrupt valid edge flag register (IEFn: n = 1, 2) is set to “1”. Even when the IEFHn
flag is used as a digital port (P21 to P27), it may be set (1). Be sure to clear (0) the IEFHn flag before checking
the edge of an external interrupt.
(5) Since analog delay noise elimination is performed on pin P20 an edge is detected up to 10 ms after it is actually
input. Also, unlike pins P21 to P27, the delay before an edge is detected is not a specific value, because of differences
in the characteristics of various devices.
(6) Since digital noise elimination is performed on pins P21 to P27 with the fCLK clock, there is a delay of 4 fCLK clocks
between input of an edge to the pin and the point at which the edge is actually detected.
(7) If the input pulse width on pins P21 to P27 is 4 fCLK clocks, it is uncertain whether a valid edge will be detected or
not. Therefore, to ensure reliable operation, the period of at least 4 clocks and the level must be fixed.
(8) If noise input to pins P21 to P27 is synchronized with the fCLK clock in the µPD784054, it may not be recognized as
noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input
pins.
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CHAPTER 14 INTERRUPT FUNCTIONS
The µPD784054 is provided with three interrupt request processing modes (refer to Table 14-1). These three service
modes can be set as required in the program. However interrupt processing by macro service can only be selected for
interrupt request sources provided with the macro service processing mode shown in Table 14-2. Context switching cannot
be selected for non-maskable interrupts or operand error interrupts.
Multi-processing control using 4 priority levels can easily be performed for maskable vectored interrupts.
Table 14-1. Processing Modes of Interrupt Request
Interrupt Request
Processing Performed
Software
PC & PSW Contents
Processing
Processing Mode
Vectored interrupts
Saving to & restoration
from stack
Executed by branching to service program at
Note
address
specified by vector table
Context switching
Macro service
Saving to & restoration
from fixed area in
register bank
Executed by automatic switching to register
bank specified by vector table and branching
Note
to service program at address
fixed area in register bank
specified by
Hardware
(firmware)
Retained (however, PSW
is 0x00H in CPU monitor
Execution of pre-set processing such as data
transfers between memory and I/O
mode 0)
Note The start addresses of all interrupt service programs must be in the base area. If the body of a service program
cannot be located in the base area, a branch instruction to the service program should be written in the base area.
14.1 Interrupt Request Sources
The µPD784054 has the 29 interrupt request sources shown in Table 14-2, with a vector table allocated to each.
Table 14-2. Sources of Interrupt Request (1/2)
Macro
Interrupt
Type of
Interrupt
Request
Service
Control
Word
Vector
Table
Default
Priority
Interrupt Request
Generating Source
Generating Control
Context
Macro
Unit
Register
Name
Switching
Service
Address
Address
Software
None
BRK instruction execution
—
—
—
—
—
—
Not
Not
—
—
—
3EH
—
possible
possible
BRKCS instruction execution
Possible
Not
possible
Operand
error
None
None
Invalid operand in MOV STBC,
#byte instruction or MOV WDM,
#byte instruction, and LOCATION
instruction
Not
Not
3CH
possible
possible
Non-
NMI (pin input edge detection)
Edge
—
—
Not
Not
—
—
2H
4H
maskable
detection
possible
possible
INTWDT (watchdog timer
overflow)
Watchdog
timer
Not
Not
possible
possible
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CHAPTER 14 INTERRUPT FUNCTIONS
Table 14-2. Sources of Interrupt Request (2/2)
Macro
Service
Control
Word
Interrupt
Type of
Interrupt
Request
Vector
Table
Default
Priority
Interrupt Request
Generating Source
Generating
Unit
Control
Context
Macro
Register Switching Service
Name
Address
Address
Maskable 0 (highest) INTOV0 (overflow of timer 0)
Timer 0
OVIC0
OVIC1
OVIC4
PIC0
Possible Possible 0FE06H
6H
8H
1
2
3
INTOV1 (overflow of timer 1)
Timer 1
0FE08H
0FE0AH
0FE0CH
INTOV4 (overflow of timer 4)
Timer 4
0AH
0CH
INTP0 (pin input edge detection)
Edge detection
Timer 0
INTCC00 (TM0-CC00 match signal generation)
INTP1 (pin input edge detection)
4
5
6
Edge detection
Timer 0
P1C1
PIC2
PIC3
0FE0EH
0FE10H
0FE12H
0EH
10H
12H
INTCC01 (TM0-CC01 match signal generation)
INTP2 (pin input edge detection)
Edge detection
Timer 0
INTCC002 (TM0-CC02 match signal generation)
INTP3 (pin input edge detection)
Edge detection
Timer 0
INTCC03 (TM0-CC03 match signal generation)
INTP4 (pin input edge detection)
7
Edge detection
Edge detection
Edge detection
Timer 1
PIC4
0FE14H
0FE16H
0FE18H
0FE1AH
0FE1CH
0FE26H
0FE28H
0FE2AH
0FE2CH
14H
16H
18H
1AH
1CH
26H
28H
2AH
2CH
8
INTP5 (pin input edge detection)
PIC5
9
INTP6 (pin input edge detection)
PIC6
10
11
12
13
14
15
INTCM10 (TM1-CM10 match signal generation)
INTCM11 (TM1-CM11 match signal generation)
INTCM40 (TM4-CM40 match signal generation)
INTCM41 (TM4-CM41 match signal generation)
INTSER (UART0 reception error)
CMIC10
CMIC11
CMIC40
CMIC41
SERIC
Timer 1
Timer 4
Timer 4
Asynchronous
INTSR (UART0 reception end)
serial interface 0 SRIC
3-wire serial I/O1 CSIIC1
INTCSI1 (3-wire serial I/O1 transfer end)
INTST (UART0 transmission end)
16
Asynchronous
serial interface 0
Asynchronous
STIC
0FE2EH
2EH
17
18
INTSER2 (UART2 reception error)
INTSR2 (UART2 reception end)
SERIC2
0FE30H
0FE32H
30H
32H
serial interface 2 SRIC2
3-wire serial I/O2 CSIIC2
INTCSI2 (3-wire serial I/O2 transfer end)
INTST2 (UART2 transmission end)
19
Asynchronous
serial interface 2
A/D converter
STIC2
0FE34H
0FE36H
34H
36H
20 (lowest) INTAD (A/D conversion end)
ADIC
Remarks 1. Th e default priority is a fixed number. This indicates the order of priority when interrupt requests specified
as having the same priority are generated simultaneously,
2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used
simultaneously). Therefore, although the same hardware is used for the interrupts, two names are
provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.1.1 Software interrupts
Interrupts by software consist of the BRK instruction which generates a vectored interrupt and the BRKCS instruction
which performs context switching.
Software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.
14.1.2 Operand error interrupts
These interrupts are generated if there is an illegal operand in an MOV STBC, #byte instruction or MOV WDM, #byte
instruction, and LOCATION instruction.
Operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.
14.1.3 Non-maskable interrupts
A non-maskable interrupt is generated by NMI pin input or the watchdog timer.
Non-maskable interrupts are acknowledged unconditionallyNote, even in the interrupt disabled state. They are not subject
to interrupt priority control, and are of higher priority that any other interrupt.
Note Except during execution of the service program for the same non-maskable interrupt, and during execution of the
service program for a higher-priority non-maskable interrupt
14.1.4 Maskable interrupts
A maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. In addition,
acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the IE flag in the program status
word (PSW).
In addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro
service.
The priority order for maskable interrupt requests when interrupt requests of the same priority are generated
simultaneously is predetermined (default priority) as shown in Table 14-2. Also, multi-processing control can be performed
with interrupt priorities divided into 4 levels. However, macro service requests are acknowledged without regard to priority
control or the IE flag.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.2 Interrupt Processing Modes
There are three µPD784054 interrupt processing modes, as follows:
•
•
•
Vectored interrupt processing
Macro service
Context switching
14.2.1 Vectored interrupt processing
When an interrupt is acknowledged, the program counter (PC) and program status word (PSW) are automatically saved
to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt processing
routine is executed.
14.2.2 Macro service
When an interrupt is acknowledged, CPU execution is temporarily suspended and a data transfer is performed by
hardware. Since macro service is performed without the intermediation of the CPU, it is not necessary to save or restore
CPU statuses such as the program counter (PC) and program status word (PSW) contents. This is therefore very effective
in improving the CPU service time (refer to 14.8 Macro Service Function).
14.2.3 Context switching
When an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre-
set vector address in the register bank, and at the same time the current program counter (PC) and program status word
(PSW) are saved in the register bank (refer to 14.4.2 BRKCS instruction software interrupt (software context switching)
acknowledgment operation and 14.7.2 Context switching).
Remark “Context” refers to the CPU registers that can be accessed by a program while that program is being executed.
These registers include general registers, the program counter (PC), program status word (PSW), and stack
pointer (SP).
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CHAPTER 14 INTERRUPT FUNCTIONS
14.3 Interrupt Processing Control Registers
µPD784054 interrupt processing is controlled for each interrupt request by various control registers that perform interrupt
processing specification. The interrupt control registers are listed in Table 14-3.
Table 14-3. Control Registers
Register Name
Symbol
Function
Interrupt control registers
OVIC0, OVIC1, OVIC4,
PIC0, PIC1, PIC2, PIC3,
PIC4, PIC5, PIC6, CMIC10,
CMIC11, CMIC40, CMIC41,
SERIC, SRIC, CSIIC1,
STIC, SERIC2, SRIC2,
CSIIC2, STIC2, ADIC
Registers to record generation of interrupt request, control
masking, specify vectored interrupt processing or macro
service processing, enable or disable context switching
function, and specify priority.
Interrupt mask registers
MK0 (MK0L, MK0H)
MK1 (MK1L, MK1H)
Control masking of maskable interrupt request. Associated
with mask control flag in interrupt control register. Can be
accessed in word or byte units.
In-service priority register
ISPR
IMC
Records priority of interrupt request currently accepted.
Interrupt mode control register
Controls nesting of maskable interrupt with priority specified
to lowest level (level 3).
Watchdog timer mode register
Program status word
WDM
PSW
Specifies priorities of interrupt by NMI pin input and overflow
of watchdog timer.
Enables or disables accepting maskable interrupt.
An interrupt control register is allocated to each interrupt source. The flags of each register perform control of the contents
corresponding to the relevant bit position in the register. The interrupt control register flag names corresponding to each
interrupt request signal are shown in Table 14-4.
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CHAPTER 14 INTERRUPT FUNCTIONS
Table 14-4. Interrupt Control Register Flags Corresponding to Interrupt Sources
Interrupt Control Registers
Interrupt
Request
Signal
Default
Priority
Interrupt
Request Flag
Interrupt
Mask Flag
Macro Service Context Switching Priority Speci-
Enable Flag
Enable Flag
fication Flag
0 (highest)
INTOV0
OVIC0
OVIC1
OVIC4
PIC0
OVIF0
OVIF1
OVIF4
PIF0
OVMK0
OVMK1
OVMK4
PMK0
OVISM0
OVCSE0
OVPR00
OVPR01
OVPR10
OVPR11
OVPR40
OVPR41
PPR00
1
INTOV1
INTOV4
OVISM1
OVISM4
PISM0
OVCSE1
OVCSE4
PCSE0
2
3
INTP0
INTCC00
INTP1
PPR01
4
PIC1
PIF1
PMK1
PISM1
PCSE1
PPR10
INTCC01
INTP2
PPR11
5
PIC2
PIF2
PMK2
PISM2
PCSE2
PPR20
INTCC02
INTP3
PPR21
6
PIC3
PIF3
PMK3
PISM3
PCSE3
PPR30
INTCC03
INTP4
PPR31
7
PIC4
PIF4
PMK4
PISM4
PCSE4
PPR40
PPR41
8
INTP5
PIC5
PIF5
PMK5
PISM5
PCSE5
PPR50
PPR51
9
INTP6
PIC6
PIF6
PMK6
PISM6
PCSE6
PPR60
PPR61
10
11
12
13
14
15
INTCM10
INTCM11
INTCM40
INTCM41
INTSER
INTSR
CMIC10
CMIC11
CMIC40
CMIC41
SERIC
SRIC
CMIF10
CMIF11
CMIF40
CMIF41
SERIF
SRIF
CMMK10
CMMK11
CMMK40
CMMK41
SERMK
SRMK
CMISM10
CMISM11
CMISM40
CMISM41
SERISM
SRISM
CMCSE10
CMCSE11
CMCSE40
CMCSE41
SRCSE
CMPR100
CMPR101
CMPR110
CMPR111
CMPR400
CMPR401
CMPR410
CMPR411
SERPR0
SERPR1
SRPR0
SRCSE
SRPR1
INTCSI1
INTST
CSIIC1
STIC
CSIIF1
STIF
CSIMK1
STMK
CSIISM1
STISM
CSICSE1
STCSE
CSIPR10
CSIPR11
STPR0
16
17
18
STPR1
INTSER2
INTSR2
INTCSI2
INTST2
INTAD
SERIC2
SRIC2
CSIIC2
STIC2
ADIC
SERIF2
SRIF2
CSIIF2
STIF2
ADIF
SERMK2
SRMK2
CSIMK2
STMK2
ADMK
SERISM2
SRISM2
CSIISM2
STISM2
ADISM
SERCSE2
SRCSE2
CSICSE2
STCSE2
ADCSE
SERPR20
SERPR21
SRPR20
SRPR21
CSIPR20
CSIPR21
STPR20
STPR21
ADPR0
19
20 (lowest)
ADPR1
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CHAPTER 14 INTERRUPT FUNCTIONS
14.3.1 Interrupt control registers
An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for
the corresponding interrupt request. The interrupt control register format is shown in Figure 14-1.
(1) Priority specification flags (××PR1, ××PR0)
The priority specification flags specify the priority on an individual interrupt source basis for the 21 maskable
interrupts.
Up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. Among
maskable interrupt sources, level 0 is the highest priority.
If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they
are acknowledged in default priority order.
These flags can be manipulated bit-wise by software.
RESET input sets all bits to “1”.
(2) Context switching enable flag (××CSE)
The context switching enable flag specifies that a maskable interrupt request is to be processed by context switching.
In context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector
address stored beforehand in the register bank, and at the same time the current contents of the program counter
(PC) and program status word (PSW) are saved in the register bank.
Context switching is suitable for real-time processing, since execution of interrupt processing can be started faster
than with normal vectored interrupt processing.
This flag can be manipulated bit-wise by software.
RESET input sets all bits to “0”.
(3) Macro service enable flag (××ISM)
The macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by
vectored interruption or context switching, or by macro service.
When macro service processing is selected, at the end of the macro service the macro service enable flag is
automatically cleared (0) by hardware (vectored interrupt processing/context switching processing).
This flag can be manipulated bit-wise by software.
RESET input sets all bits to “0”.
(4) Interrupt mask flag (××MK)
An interrupt mask flag specifies enabling/disabling of vectored interrupt processing and macro service processing
for the interrupt request corresponding to that flag.
The interrupt mask flag contents are not changed by the start of interrupt processing, etc., and are the same as the
interrupt mask register contents (refer to 14.3.2 Interrupt mask registers (MK0, MK1)).
Macro service processing requests are also subject to mask control, and macro service requests can also be masked
with this flag.
This flag can be manipulated by software.
RESET input sets all bits to “1”.
(5) Interrupt request flag (××IF)
An interrupt request flag is set (1) by generation of the interrupt request that corresponds to that flag. When the
interrupt is acknowledged, the flag is automatically cleared (0) by hardware.
This flag can be manipulated by software.
RESET input sets all bits to “0”.
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Registers (××ICn) (1/3)
Address : 0FFE0H-0FFE9H
On reset : 43H
R/W
7
6
5
4
3
0
2
0
1
0
OVIC0 OVIF0 OVMK0 OVISM0 OVCSE0
OVIC1 OVIF1 OVMK1 OVISM1 OVCSE1
OVIC4 OVIF4 OVMK4 OVISM4 OVCSE4
OVPR01 OVPR00
OVPR11 OVPR10
OVPR41 OVPR40
PPR01 PPR00
PPR11 PPR10
PPR21 PPR20
PPR31 PPR30
0
0
0
0
0
0
0
0
0
0
0
0
PIC0
PIC1
PIC2
PIC3
PIF0 PMK0 PISM0 PCSE0
PIF1 PMK1 PISM1 PCSE1
PIF2 PMK2 PISM2 PCSE2
PIF3 PMK3 PISM3 PCSE3
PIC4
PIC5
PIC6
PIF4 PMK4 PISM4 PCSE4
PIF5 PMK5 PISM5 PCSE5
PIF6 PMK6 PISM6 PCSE6
0
0
0
0
0
0
PPR41 PPR40
PPR51 PPR50
PPR61 PPR60
Generation of Interrupt Request
No interrupt request (interrupt signal is not generated)
Interrupt request (interrupt signal is generated)
××IFn
0
1
Enables or Disables Interrupt Processing
Enables interrupt processing
××MKn
0
1
Disables interrupt processing
Specifies Interrupt Processing Format
Vectored interrupt processing/context switching processing
Macro service processing
××ISMn
0
1
Specifies Context Switching Processing
Processed by vectored interrupt
××CSEn
0
1
Processed by context switching
Specifies Priority of Interrupt Request
××PRn1 ××PRn0
0
0
1
1
0
1
0
1
Priority 0 (highest priority)
Priority 1
Priority 2
Priority 3
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-1. Interrupt Control Registers (××ICn) (2/3)
Address : 0FFEAH-0FFF5H
On reset : 43H
R/W
7
6
5
4
3
2
0
1
0
CMIC10 CMIF10 CMMK10 CMISM10 CMCSE10
0
CMPR101 CMPR100
CMIC11 CMIF11 CMMK11 CMISM11 CMCSE11
0
0
CMPR111 CMPR110
CMIC40 CMIF40 CMMK40 CMISM40 CMCSE40
CMIC41 CMIF41 CMMK41 CMISM41 CMCSE41
SERIC SERIF SERMK SERISM SERCSE
0
0
0
0
0
0
0
0
0
0
CMPR401 CMPR400
CMPR411 CMPR410
SERPR1 SERPR0
SRPR1 SRPR0
CSIPR11 CSIPR10
SRIC
SRIF SRMK SRISM SRCSE
CSIIC1 CSIIF1 CSIMK1 CSIISM1 CSICSE1
STIC
STIF STMK STISM STCSE
0
0
0
0
STPR1 STPR0
SERIC2 SERIF2 SERMK2 SERISM2 SERCSE2
SERPR21 SERPR20
××IFn
Generation of Interrupt Request
No interrupt request (interrupt signal is not generated)
Interrupt request (interrupt signal is generated)
0
1
××MKn
Enables or Disables Interrupt Processing
Enables interrupt processing
0
1
Disables interrupt processing
××ISMn
Specifies Interrupt Processing Format
Vectored interrupt processing/context switching processing
Macro service processing
0
1
××CSEn
Specifies Context Switching Processing
Processed by vectored interrupt
0
1
Processed by context switching
××PRn1 ××PRn0 Specifies Priority of Interrupt Request
0
0
1
1
0
1
0
1
Priority 0 (highest priority)
Priority 1
Priority 2
Priority 3
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Figure 14-1. Interrupt Control Registers (××ICn) (3/3)
Address : 0FFF6H-0FFF8H
On reset : 43H
R/W
7
6
5
4
3
0
2
0
1
0
SRIC2 SRIF2 SRMK2 SRISM2 SRCSE2
CSIIC2 CSIIF2 CSIMK2 CSIISM2 CSICSE2
STIC2 STIF2 STMK2 STISM2 STCSE2
SRPR21 SRPR20
CSIPR21 CSIPR20
STPR21 STPR20
ADPR1 ADPR0
0
0
0
0
0
0
ADIC
ADIF ADMK ADISM ADCSE
××IFn
Generation of Interrupt Request
No interrupt request (interrupt signal is not generated)
Interrupt request (interrupt signal is generated)
0
1
××MKn
Enables or Disables Interrupt Processing
Enables interrupt processing
0
1
Disables interrupt processing
××ISMn
Specifies Interrupt Processing Format
Vectored interrupt processing/context switching processing
Macro service processing
0
1
××CSEn
Specifies Context Switching Processing
Processed by vectored interrupt
0
1
Processed by context switching
××PRn1 ××PRn0
Specifies Priority of Interrupt Request
0
0
1
1
0
1
0
1
Priority 0 (highest priority)
Priority 1
Priority 2
Priority 3
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14.3.2 Interrupt mask registers (MK0, MK1)
The MK0 and MK1 are composed of interrupt mask flags. MK0 and MK1 are 16-bit registers which can be manipulated
as a 16-bit unit. MK0 can be manipulated in 8 bit units using MK0L and MK0H, and similarly MK1 can be manipulated using
MK1L and MK1H.
In addition, each bit of the MK0 and MK1L can be manipulated individually with a bit manipulation instruction. Each
interrupt mask flag controls enabling/disabling of the corresponding interrupt request.
When an interrupt mask flag is set (1), acknowledgment of the corresponding interrupt request is disabled.
When an interrupt mask flag is cleared (0), the corresponding interrupt request can be acknowledged as a vectored
interrupt or macro service request.
Each interrupt mask flag in the MK0 and MK1 is the same flag as the interrupt mask flag in the interrupt control register.
The MK0 and MK1 are provided for en bloc control of interrupt masking.
After RESET input, the MK0 and MK1 are set to FFFFH, and all maskable interrupts are disabled.
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Figure 14-2. Format of Interrupt Mask Registers (MK0, MK1)
<Byte access>
Address : 0FFACH-0FFAFH
On reset : FFH
R/W
7
6
5
4
3
2
1
0
MK0L PMK4 PMK3 PMK2 PMK1 PMK0 OVMK4 OVMK1 OVMK0
MK0H
1
1
1
1
CMMK11 CMMK10 PMK6 PMK5
MK1L STMK2 SRMK2 SERMK2 STMK SRMK SERMK CMMK41 CMMK40
MK1H
1
1
1
1
1
1
1
ADMK
××MKn
Enables or Disables Interrupt Request
0
1
Enables interrupt processing
Disables interrupt processing
<Word access>
Address : 0FFACH, 0FFAEH
On reset : FFFFH
R/W
9
15
1
14
1
13
1
12
1
11
10
8
MK0
CMMK11 CMMK10 PMK6 PMK5
7
6
5
4
3
2
1
0
PMK4 PMK3 PMK2 PMK1 PMK0 OVMK4 OVMK1 OVMK0
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
MK1
ADMK
7
6
5
4
3
2
1
0
STMK2 SRMK2 SERMK2 STMK SRMK SERMK CMMK41 CMMK40
××MKn
Enables or Disables Interrupt Request
Enables interrupt processing
0
1
Disables interrupt processing
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14.3.3 In-service priority register (ISPR)
The ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being
processed. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request
is set (1), and remains set until the service program ends. When a non-maskable interrupt is acknowledged, the bit
corresponding to the priority of that non-maskable interrupt is set (1), and remains set until the service program ends.
When an RETI instruction or RETCS instruction is executed, the bit, among those set (1) in the ISPR, that corresponds
to the highest-priority interrupt request is automatically cleared (0) by hardware.
The contents of the ISPR are not changed by execution of an RETB or RETCSB instruction.
RESET input clears the ISPR register to 00H.
Figure 14-3. Format of In-Service Priority Register (ISPR)
Address : 0FFA8H
7
On reset : 00H
R
6
5
0
4
0
3
2
1
0
ISPR
NMIS WDTS
ISPR3 ISPR2 ISPR1 ISPR0
NMIS
NMI Processing Status
0
1
NMI interrupt is not accepted.
NMI interrupt is accepted
WDTS Watchdog Timer Interrupt Processing Status
0
1
Watchdog timer interrupt is not accepted.
Watchdog timer interrupt is accepted.
ISPRn
Priority level (n = 0 to 3)
0
1
Interrupt of priority level n is not accepted.
Interrupt of priority level n is accepted.
Caution The in-service priority register (ISPR) is a read-only register. The microcontroller may malfunction if
this register is written.
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14.3.4 Interrupt mode control register (IMC)
The IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which
the lowest priority level (level 3) is specified.
When the IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent misoperation.
The IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
RESET input sets the IMC register to 80H.
Figure 14-4. Format of Interrupt Mode Control Register (IMC)
Address : 0FFAAH
7
On reset : 80H
R
6
0
5
0
4
0
3
0
2
0
1
0
0
0
IMC
PRSL
PRSL Controls Nesting of Maskable Interrupt
(lowest level)
0
Interrupts with level 3 (lowest level) can be
nested.
1
Nesting of interrupts with level 3 (lowest level)
is disabled.
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14.3.5 Watchdog timer mode register (WDM)
The PRC bit of the WDM specifies the priority of NMI pin input non-maskable interrupts and watchdog timer overflow
non-maskable interrupts.
The WDM can be written to only by a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special
code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual
complements.
If the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt
is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source
of the error, and thus the address that was the source of the error can be identified from the return address saved in the
stack area.
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.
As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics
assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system
initialization should be performed by the program.
Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any
operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.
The WDM can be read at any time by a data transfer instruction.
RESET input clears the WDM register to 00H.
Figure 14-5. Format of Watchdog Timer Mode Register (WDM)
Address : 0FFC2H
7
On reset : 00H
R/W
6
0
5
0
4
3
0
2
1
0
0
WDM
RUN
PRC
WDI2 WDI1
RUN Specifies Operation of Watchdog Timer
(refer to Figure 10-2).
PRC Priority of Watchdog Timer Interrupt Request
0
Watchdog timer interrupt request
< NMI pin input interrupt request
Watchdog timer interrupt request
> NMI pin input interrupt request
1
WDI2 WDI1 Specifies count clock of watchdog
timer (refer to Figure 10-2).
Caution The watchdog timer mode register (WDM) can be written only by using a dedicated instruction (MOV
WDM, #byte).
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14.3.6 Program status word (PSW)
The PSW is a register that holds the current status regarding instruction execution results and interrupt requests. The
IE flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the PSW (PSWL).
PSWL can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation
instruction or dedicated instruction (EI/DI).
When a vectored interrupt is acknowledged or a BRK instruction is executed, PSWL is saved to the stack and the IE
flag is cleared (0). PSWL is also saved to the stack by the PUSH PSW instruction, and is restored from the stack by the
RETI, RETB and POP PSW instructions.
When context switching or a BRKCS instruction is executed, PSWL is saved to a fixed area in the register bank, and
the IE flag is cleared (0). PSWL is restored from the fixed area in the register bank by an RETCSI or RETCSB instruction.
RESET input clears PSWL to 00H.
Figure 14-6. Format of Program Status Word (PSWL)
On reset : 00H
7
6
Z
5
4
3
2
1
0
0
PSWL
S
RSS
AC
IE
P/V
CY
S
Z
Used when executing a normal operation
RSS
AC
Enables or Disables Interrupt Accepting
Disables interrupt accepting
IE
0
1
Enables interrupt accepting
P/V Used when executing a normal operation
CY
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14.4 Software Interrupt Acknowledgment Operations
A software interrupt is acknowledged in response to execution of a BRK or BRKCS instruction. Software interrupts cannot
be disabled.
14.4.1 BRK instruction software interrupt acknowledgment operation
When a BRK instruction is executed, the program status word (PSW), program counter (PC) are saved in that order to
the stack, the IE flag is cleared (0), the vector table (003EH/003FH) contents are loaded into the low-order 16 bits of the
PC, and 0000B into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base
area).
The RETB instruction must be used to return from a BRK instruction software interrupt.
Caution The RETI instruction must not be used to return from a BRK instruction software interrupt.
14.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation
The context switching function can be initiated by executing a BRKCS instruction.
The register bank to be used after context switching is specified by the BRKCS instruction operand.
When a BRKCS instruction is executed, the program branches to the start address of the interrupt service program (which
must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word
(PSW) and program counter (PC) are saved in the register bank.
Figure 14-7. Context Switching Operation by Execution of a BRKCS Instruction
0000B
Register Bank
(0 to 7)
7 Transfer
Register Bank n (n = 0 to 7)
PC19-16
PC15-0
A
X
B
C
6 Exchange
R5
R7
R4
R6
2 Save
(Bits 8 to 11 of
Temporary Register)
5 Save
V
U
T
VP
UP
3
4
Register Bank Switching
(RBS0-RBS2 ← n)
RSS ← 0
Temporary Register
D
H
E
L
(
IE ← 0
)
W
1 Save
PSW
The RETCSB instruction is used to return from a software interrupt due to a BRKCS instruction. The RETCSB instruction
must specify the start address of the interrupt service program for the next time context switching is performed by a BRKCS
instruction. This interrupt service program start address must be in the base area.
Caution The RETCS instruction must not be used to return from a BRKCS instruction software interrupt.
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Figure 14-8. Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation)
Register Bank n (n = 0 to 7)
A
B
X
C
PC19-16
PC15-0
1 Restoration
RETCSB Instruction Operand
R5
R7
R4
R6
2 Restoration
3 Transfer
V
VP
UP
4 Restoration
U
T
(To Original
Register Bank)
D
H
E
L
W
PSW
14.5 Operand Error Interrupt Acknowledgment Operation
An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand
of an MOV STBC, #byte instruction or LOCATION instruction or an MOV WDM,#byte instruction does not match the 4th
byte of the operand. Operand error interrupts cannot be disabled.
When an operand error interrupt is generated, the program status word (PSW) and the start address of the instruction
that caused the error are saved to the stack, the IE flag is cleared (0), the vector table value is loaded into the program counter
(PC), and a branch is performed (within the base area only).
As the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an
RETB instruction at the end of the operand error interrupt service program will result in generation of another operand error
interrupt. You should therefore either process the address in the stack or initialize the program by referring to 14.12
Restoring Interrupt Function To Initial State.
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14.6 Non-Maskable Interrupt Acknowledgment Operation
Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be
acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non-
maskable interrupt of higher priority.
The relative priorities of non-maskable interrupts are set by the PRC bit of the watchdog timer mode register (WDM) (refer
to 14.3.5 Watchdog timer mode register (WDM)).
Except in the cases described in 14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending,
a non-maskable interrupt request is acknowledged immediately. When a non-maskable interrupt request is acknowledged,
the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (0),
the in-service priority register (ISPR) bit corresponding to the acknowledged non-maskable interrupt is set (1), the vector
table contents are loaded into the PC, and a branch is performed. The ISPR bit that is set (1) is the NMIS bit in the case
of a non-maskable interrupt due to edge input to the NMI pin, and the WDTS bit in the case of watchdog timer overflow.
When the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as
the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable
interrupt currently being executed are held pending. A pending non-maskable interrupt is acknowledge after completion
of the non-maskable interrupt service program currently being executed (after execution of the RETI instruction). However,
even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt
service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service
program.
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Figure 14-9. Operations of Non-Maskable Interrupt Request Acknowledgment (1/2)
(a) When a new NMI request is generated during NMI service program execution
Main Routine
(NMIS = 1)
NMI request held pending since NMIS = 1
Pending NMI request is serviced
NMI Request
NMI Request
(b) When a watchdog timer interrupt request is generated during NMI service program execution (when the
watchdog timer interrupt priority is higher (when PRC in the WDM = 1))
Main Routine
Watchdog
Timer Interrupt
Request
NMI Request
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Figure 14-9. Operations of Non-Maskable Interrupt Request Acknowledgment (2/2)
(c) When a watchdog timer interrupt request is generated during NMI service program execution (when the
NMI interrupt priority is higher (when PRC in the WDM = 0))
Main Routine
Watchdog
Timer
Interrupt
Request
Watchdog timer interrupt is kept
pending because PRC = 0
NMI Request
Pending watchdog timer interrupt is processed
(d) When an NMI request is generated twice during NMI service program execution
Main Routine
NMI Held pending since NMI service
Request program is being executed
NMI Request
NMI
Held pending since NMI service
Request program is being executed
NMI request was generated more than
once, but is only acknowledged once
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Cautions 1. Macro service requests are acknowledged and serviced even during execution of a non-maskable
interrupt service program. If you do not want macro service processing to be performed during
a non-maskable interrupt service program, you should manipulate the interrupt mask register in
the non-maskable interrupt service program to prevent macro service generation.
2. The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt
acknowledgment will not be performed normally if a different instruction is used.
3. Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service
program execution (except when a high non-maskable interrupt request is generated during
execution of a low-priority non-maskable interrupt service program) and for a certain period after
execution of the special instructions shown in 14.9. Therefore, a non-maskable interrupt will be
acknowledged even when the stack pointer (SP) value is undefined, in particular after reset release,
etc. In this case, depending on the value of the SP, it may happen that the program counter (PC)
and program status word (PSW) are written to the address of a write-inhibited special function
register (SFR) (refer to Table 3-6 in 3.8 Special Function Registers (SFRs)), and the CPU becomes
deadlocked, or an unexpected signal is output from a pin, or the PC and PSW are written to an
address in which RAM is not mounted, with the result that the return from the non-maskable
interrupt processing program is not performed normally and a software upsets occurs.
Therefore, the program following RESET release must be as shown below.
CSEG AT 0
DW
STRT
CSEG BASE
STRT:
LOCATION 0FH; or LOCATION 0H
MOVG SP, #imm24
14.7 Maskable Interrupt Acknowledgment Operation
A maskable interrupt can be acknowledged when the interrupt request flag is set (1) and the mask flag for that interrupt
is cleared (0). When processing is performed by macro service, the interrupt is acknowledged and processed by macro
service immediately. In the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt
enabled state (when the IE flag is set (1)) if the priority of that interrupt is one for which acknowledgment is permitted.
If maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by
the priority specification flag is acknowledged. If the interrupts have the same priority specified, they are acknowledged
in accordance with their default priorities.
A pending interrupt is acknowledged when a state in which it can be acknowledged is established.
The interrupt acknowledgment algorithm is shown in Figure 14-10.
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Figure 14-10. Algorithm of Interrupt Acknowledgment Processing
No
××IF = 1
Interrupt Request?
Yes
No
××MK = 0
Interrupt Mask Released?
Yes
Yes
××ISM = 1
Macro Service?
No
Highest
default priority among
No
Interrupt Enabled State?
No
IE = 1
Yes
macro service
requests?
Yes
Higher priority
than interrupt currently
being serviced?
No
Macro service
processing execution
Yes
Higher priority
than other existing interrupt
requests?
No
No
Interrupt request
held pending
Yes
Highest default
priority among interrupt
requests of same
priority?
Interrupt request
held pending
Yes
Yes
××CSE = 1
Context Switching?
No
Context switching
generation
Vectored interrupt
generation
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14.7.1 Vectored interrupt
When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program
counter (PC) are saved in that order to the stack, the IE flag is cleared (0) (the interrupt disabled state is set), and the in-
service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (1). Also, data in the
vector table predetermined for each interrupt request is loaded into the PC, and a branch is performed. The return from
a vectored interrupt is performed by means of the RETI instruction.
Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used
to return from the interrupt. Subsequent interrupt acknowledgment will not be performed normally if
a different instruction is used.
14.7.2 Context switching
Initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt control
register.
When an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified
by 3 bits of the lower address (even address) of the corresponding vector table address is selected.
The vector address stored beforehand in the selected register bank is transferred to the program counter (PC), and at
the same time the contents of the PC and program status word (PSW) up to that time are saved in the register bank and
a branch is made to the interrupt service program.
Figure 14-11. Context Switching Operation by Generation of an Interrupt Request
3 Register Bank Switching
(RBS0-RBS2 ← n)
Vector Table
n
0000B
Register Bank
(0 to 7)
7 Transfer
Register Bank n (n = 0 to 7)
PC19-16
PC15-0
A
X
B
C
6 Exchange
R5
R7
R4
R6
2 Save
(Temporary
Register
V
VP
UP
5 Save
Bit 8-11)
U
T
4
RSS ← 0
Temporary Register
(
IE ← 0
)
D
H
E
L
1 Save
W
PSW
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The RETCS instruction is used to return from an interrupt that uses the context switching function. The RETCS instruction
must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next.
This interrupt service program start address must be in the base area.
Caution The RETCS instruction must be used to return from an interrupt serviced by context switching.
Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used.
Figure 14-12. Return from Interrupt that Uses Context Switching by Means of RETCS Instruction
Register Bank n (n = 0 to 7)
A
B
X
C
PC19-16
PC15-0
1 Restoration
RETCS Instruction Operand
R5
R7
R4
R6
2 Restoration
3 Transfer
V
U
T
VP
UP
4 Restoration
(To Original
Register Bank)
D
H
E
L
PSW
W
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14.7.3 Maskable interrupt priority levels
The µPD784054 performs multiple interrupt processing in which an interrupt is acknowledged during processing of
another interrupt. Multiple interrupts can be controlled by priority levels.
There are two kinds of priority control, control by default priority and programmable priority control in accordance with
the setting of the priority specification flag. In priority control by means of default priority, interrupt service is performed in
accordance with the priority preassigned to each interrupt request (default priority) (refer to Table 14-2). In programmable
priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. Interrupt
requests for which multiple interruption is permitted are shown in Table 14-5.
Since the IE flag is cleared (0) automatically when an interrupt is acknowledged, when multiple interruption is used, the
IE flag should be set (1) to enable interrupts by executing an EI instruction in the interrupt processing program, etc.
Table 14-5. Multiple Interrupt Processing
Priority of Interrupt Currently
Being Acknowledged
PRSL in
ISPR Value
00000000
IE Flag in PSW
Acknowledgeable Maskable Interrupts
IMC Register
No interrupt being
acknowledged
3
0
1
0
1
1
×
×
×
0
1
•
•
•
•
All macro service only
All maskable interrupts
All macro service only
All maskable interrupts
00001000
•
•
All macro service
Maskable interrupts specified as
priority 0/1/2
2
1
0000×100
0000××10
0000×××1
0
1
×
×
•
All macro service only
•
•
All macro service
Maskable interrupts specified as
priority 0/1
0
1
×
×
•
All macro service only
•
•
All macro service
Maskable interrupts specified as
priority 0
0
×
×
×
×
•
•
All macro service only
All macro service only
Non-maskable interrupts
1000××××
0100××××
1100××××
Remark ×: don’t care
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Figure 14-13. Examples of Processing When Another Interrupt Request
Is Generated During Interrupt Processing (1/3
)
Main routine
a Processing
b Processing
EI
EI
Interrupt Request a
(Level 3)
Interrupt
Request b
(Level 2)
Since interrupt request b has a higher
priority than interrupt request a, and
interrupts are enabled, interrupt
request b is acknowledged.
c Processing
Interrupt
Request d
(Level 2)
Interrupt Request c
(Level 3)
The priority of interrupt request d is
higher than that of interrupt request c,
but since interrupts are disabled,
interrupt request d is held pending.
d Processing
e Processing
f Processing
EI
Interrupt
Request f
(Level 3)
Although interrupts are enabled,
interrupt request f is held pending
since it has a lower priority than
interrupt request e.
Interrupt Request e
(Level 2)
g Processing
h Processing
Although interrupts are enabled,
interrupt request h is held pending
since it has the same priority as
interrupt request g.
EI
Interrupt
Request h
(Level 1)
Interrupt Request g
(Level 1)
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CHAPTER 14 INTERRUPT FUNCTIONS
Figure 14-13. Examples of Processing When Another Interrupt Request
Is Generated During Interrupt Processing (2/3
)
Main routine
EI
i Processing
Interrupt Request i
(Level 1)
Macro Service
Request j
(Level 2)
j Macro Service
The macro service request is
serviced irrespective of interrupt
enabling/disabling and priority.
k Processing
m Processing
EI
Interrupt
Request l
(Level 3)
Interrupt
The interrupt request is held
pending since it has a lower
priority than interrupt request k.
Interrupt request m generated
after interrupt request l has a
higher priority, and is therefore
acknowledged first.
Interrupt Request k
(Level 2)
Request m
(Level 1)
l Processing
n Processing
Interrupt
Request o
(Level 3)
Interrupt
Request p
(Level 1)
Since processing of interrupt
request n performed in the
interrupt disabled state,
interrupt requests o and p
are held pending.
After interrupt request n
processing, the pending interrupt
requests are acknowledged.
Although interrupt request o
was generated first, interrupt
request p has a higher priority
and is therefore acknowledged
first.
Interrupt Request n
(Level 2)
p Processing
o Processing
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Figure 14-13. Examples of Processing When Another Interrupt Request
Is Generated During Interrupt Processing (3/3
)
Main routine
EI
q Processing
r Processing
s Processing
EI
EI
EI
Interrupt
Request r
(Level 2)
Interrupt Request q
Level 3)
t Processing
Interrupt
Request s
(Level 1)
Interrupt
Request t
(Level 0)
EI
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC is set (1), only
macro service requests and non-maskable
interrupts generate nesting beyond this.
If the PRSL bit of the IMC is cleared (0),
level 3 interrupts can also be nested during
level 3 interrupt processing (refer to Figure
14-15).
u Processing
EI
Even though the interrupt enabled state is
set during processing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
processed irrespective of its level and even
though there is a pending interrupt with a
higher priority level.
Interrupt
Request v
(Level 0)
Interrupt
Interrupt Request u
(Level 0)
w Macro Service
Request w
(Level 3)
v Processing
x Processing
Interrupt
Request yNote 1
(Level 2)
Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.
Interrupt
Request zNote 2
(Level 2)
Interrupt Request x
(Level 1)
z Processing
y Processing
Notes 1. Low default priority
2. High default priority
Remarks 1. “a” to “z” in the figure are arbitrary names used to differentiate between the interrupt requests and macro
service requests.
2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.
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Figure 14-14. Examples of Processing of Simultaneously Generated Interrupts
Main Routine
EI
Interrupt Request a (Level 2)
Macro Service Request b Processing
Macro Service Request c Processing
Macro Service Request f Processing
• When requests are generated
simultaneously, they are
acknowledged in order starting
with macro service.
• Macro service requests are
acknowledged in default priority
order (b/c/f) (not dependent
upon the programmable priority
order).
Macro Service Request b (Level 3)
Macro Service Request c (Level 1)
(Level 1)
Interrupt Request d
Interrupt Request e (Level 1)
Macro Service Request f (Level 1)
Interrupt Request d Processing
• As interrupt requests are
acknowledged in high-to-low
priority level order, d and e are
acknowledged first.
• As d and e have the same
priority level, the interrupt
request with the higher default
priority, d, is acknowledged
first.
Interrupt Request e Processing
Interrupt Request a Processing
Default Priority Order
a > b > c > d > e > f
Remark “a” to “f” in the figure are arbitrary names used to differentiate between the interrupt requests and macro service
requests.
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Figure 14-15. Differences in Level 3 Interrupt Acknowledgment According
to Setting of Interrupt Mode Control Register (IMC)
Main Routine
The PRSL bit of the IMC is set to 1, and
nesting between level 3 interrupts is
IMC ← 80H
disabled.
a Processing
b Processing
EI
EI
Interrupt Request a
(Level 3)
Interrupt
Request b
(Level 3)
Even though interrupts are enabled, interrupt
request b is held pending since it has the
same priority as interrupt request a.
Main Routine
The PRSL bit of the IMC is set to 0, so that a
level 3 interrupt is acknowledged even during
level 3 interrupt processing (nesting is
possible).
c Processing
IMC ← 00H
EI
EI
d Processing
Interrupt
Request d
(Level 3)
Interrupt Request c
(Level 3)
Since level 3 interrupt request c is being
processed in the interrupt enabled state and
PRSL = 0, interrupt request d, which is also
level 3, is acknowledged.
Bit 3 (ISPR3) of the in-service priority register (ISPR)
is cleared by returning from processing d.
Main Routine
IMC ← 00H
As interrupt request 3 and f are both of the
same level, the one with the higher default
priority, f, is acknowledged first.
Interrupt Request eNote 1
(Level 3)
When the interrupt enabled state is set
during processing of interrupt request f,
pending interrupt request e is acknowledged
since PRSL = 0.
Interrupt Request fNote 2
(Level 3)
f Processing
e Processing
EI
EI
Notes 1. Low default priority
2. High default priority
Remarks 1. “a” to “f” in the figure are arbitrary names used to differentiate between the interrupt requests and
macro service requests.
2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt
requests.
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14.8 Macro Service Function
14.8.1 Outline of macro service function
Macro service is one method of processing interrupts. With a normal interrupt, the program counter (PC) and program
status word (PSW) are saved, and the start address of the interrupt service program is loaded into the PC, but with macro
service, different processing (mainly data transfers) is performed instead of this processing. This enables interrupt requests
to be responded to quickly, and moreover, since transfer processing is faster than processing by a program, the processing
time can also be reduced.
Also, since a vectored interrupt is generated after processing has been performed the specified number of times, another
advantage is that vectored interrupt programs can be simplified.
Figure 14-16. Differences between Vectored Interrupt and Macro Service Processing
Macro Service
Processing
Macro Service
Context SwitchingNote 1
Vectored InterruptNote 1
Main Routine
Main Routine
Main Routine
Main Routine
Interrupt
Processing
Note 2
Note 3
Main Routine
Interrupt
Processing
Restore
PC, PSW
SEL
RBn
Main Routine
Note 4
Note 4
Save
Initialize
General
Registers
Restore
General
Registers
Interrupt
Processing
Restore
PC & PSW
Main Routine
General
Vectored Interrupt
Main Routine
Registers
Interrupt Request Generation
Notes 1. When register bank switching is used, and an initial value has been set in the register beforehand
2. Register bank switching by context switching, saving of PC and PSW
3. Register bank, PC and PSW restoration by context switching
4. PC and PSW saved to the stack, vector address loaded into PC
14.8.2 Types of macro service
Macro service can be used with the 21 kinds of interrupt shown in Table 14-6 (18 of which can be used simultaneously).
There are seven kinds of operation mode, which can be used to suit the application.
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Table 14-6. Interrupts for Which Macro Service Can Be Used
Default
Priority
Macro Service Control
Word Address
Interrupt Request Generation Source
Generating Unit
Timer 0
0 (highest) INTOV0 (overflow of timer 0)
0FE06H
0FE08H
0FE0AH
0FE0CH
1
2
3
INTOV1 (overflow of timer 1)
Timer 1
INTOV4 (overflow of timer 4)
Timer 4
INTP0 (pin input edge detection)
Edge detection
Timer 0
INTCC00 (TM0-CC00 match signal generation)
INTP1 (pin input edge detection)
4
5
6
Edge detection
Timer 0
0FE0EH
0FE10H
0FE12H
INTCC01 (TM0-CC01 match signal generation)
INTP2 (pin input edge detection)
Edge detection
Timer 0
INTCC002 (TM0-CC02 match signal generation)
INTP3 (pin input edge detection)
Edge detection
Timer 0
INTCC03 (TM0-CC03 match signal generation)
INTP4 (pin input edge detection)
7
Edge detection
Edge detection
Edge detection
Timer 1
0FE14H
0FE16H
0FE18H
0FE1AH
0FE1CH
0FE26H
0FE28H
8
INTP5 (pin input edge detection)
9
INTP6 (pin input edge detection)
10
11
12
13
14
15
INTCM10 (TM1-CM10 match signal generation)
INTCM11 (TM1-CM11 match signal generation)
INTCM40 (TM4-CM40 match signal generation)
INTCM41 (TM4-CM41 match signal generation)
INTSER (UART0 reception error)
Timer 1
Timer 4
Timer 4
Asynchronous serial interface 0 0FE2AH
0FE2CH
INTSR (UART0 reception end)
INTCSI1 (3-wire serial I/O1 transfer end)
INTST (UART0 transmission end)
3-wire serial I/O1
16
17
18
Asynchronous serial interface 0 0FE2EH
Asynchronous serial interface 2 0FE30H
0FE32H
INTSER2 (UART2 reception error)
INTSR2 (UART2 reception end)
INTCSI2 (3-wire serial I/O2 transfer end)
INTST2 (UART2 transmission end)
3-wire serial I/O2
19
Asynchronous serial interface 2 0FE34H
20 (lowest) INTAD (A/D conversion end)
A/D converter
0FE36H
Remarks 1. The default priority is a fixed number. This indicates the order of priority when macro service requests
are generated simultaneously,
2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used
simultaneously). Therefore, although the same hardware is used for the interrupts, two names are
provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.
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The macro service operation is performed in the following seven modes:
(1) Counter mode: EVTCNT
In this mode, each time an interrupt request has been generated, the macro service counter (MSC) is incremented
(+1) or decremented (–1). When MSC reaches 00H, a vectored interrupt request is generated.
This mode is used to divide the number of times an interrupt request is generated.
(2) Block transfer mode: BLKTRS
Each time an interrupt request has been generated, 1-byte or 1-word data is transferred between a special function
register (SFR) pointed to by the SFR pointer (SFR.PTR) and buffer. When data has been transferred the specified
number of times, a vectored interrupt request is generated.
The buffer with which data is to be transferred is limited to the addresses 0FD00H to 0FEFFHNote of the main RAM.
This mode is easy to specify and is used for high-speed transfer of a small amount of data.
Note When the LOCATION 0H instruction is executed. FFD00H to FFEFFH when the LOCATION 0FH instruction
is executed.
(3) Block transfer mode (with memory pointer): BLKTRS-P
Like the block transfer mode, 1-byte or 1-word data is transferred between an SFR specified by SFR.PTR and buffer
each time an interrupt request has been generated, and a vectored interrupt request is generated when data has
been transferred the specified number of times.
The buffer with which data is to be transferred is specified by the memory pointer (MEM.PTR) (data can be transferred
with the entire 1M-byte memory).
This mode is a general-purpose type of the block transfer mode and is used to transfer a large quantity of data.
(4) Data differential mode: DTADIF
Each time an interrupt request has been generated, the difference between the current value of an SFR specified
by SFR.PRT and the “value immediately before” stored in memory is written to the buffer, and the current value is
used as the “value immediately before”.
When data has been transferred the specified number of times, a vectored interrupt request is generated.
The buffer with which data is to be transferred is limited to the main RAM of the addresses 0FD00H to 0FEFFHNote
.
This mode is used to measure the cycle of an input pulse, or width of a pulse by using a capture register.
Note When the LOCATION 0H instruction is executed. FFD00H to FFEFFH when the LOCATION 0FH instruction
is executed.
(5) Data differential mode (with memory pointer): DTADIF-P
Like the data differential mode, each time an interrupt request has been generated, the difference between the
current value of an SFR specified by SFR.PTR and the “value immediately before” stored in memory is written to
the buffer, and the current value is used as the “value immediately before”.
When data has been transferred the specified number of times, a vectored interrupt request is generated.
The buffer with which data is to be transferred is specified by the memory pointer (MEM.PTR) (the entire 1M-byte
memory can be specified).
This mode is a general-purpose type of the data differential mode, and is used to transfer a large quantity of data.
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(6) CPU monitor mode 0: SELF0
Each time an interrupt request has been generated, the internal operation of the CPU is checked. If each block
operates normally, a value resulting from subtracting 10 from the initial data is transferred to an SFR specified by
SFR.PTR.
This mode is used for self-check of the CPU at initialization.
(7) CPU monitor mode 1: SELF1
Each time an interrupt request has been generated, the internal operation of the CPU is checked. If each block
operates normally, a value resulting from subtracting 8 from the initial data is transferred to an SFR specified by
SFR.PTR.
This mode is used for self-check of the CPU during normal operation.
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14.8.3 Basic operation of macro service (except CPU monitor modes 0 and 1)
The macro service function is to transfer data between the special function register area and memory space by hardware,
using an interrupt request.
When a macro service request is generated, the CPU temporarily stops program execution, and automatically transfers
1/2-byte data between a special function register (SFR) and memory. When data transfer has been completed, an interrupt
request flag is reset (0), and the CPU starts program execution again. Data is transferred the number of times set to the
macro service counter (MSC) and then a vectored interrupt request is generated.
Figure 14-17. Example of Macro Service Processing Sequence
Generation of Interrupt Request
That Executes Mocro Service Processing
Executes macro service
; Transfers data, controls real-time output port
processing
_
_
; Decrements ( 1) macro service counter (MSC)
MSC←MSC
1
YES
NO
MSC = 0?
Macro Service Enable Flag←0
Interrupt Request Flag←0
Generation of Vectored Interrupt Request
Execution of Next Instruction
Unlike other interrupt processing, processing using the macro service function is automatically performed without starting
an interrupt processing program. Therefore, operations such as branching to an interrupt service routine, saving/restoring
registers, and returning from the interrupt service routine are not performed. This means that the service time of the CPU
can be improved and that the number of program steps can be decreased.
When macro service processing is executed, the status before execution of the macro service processing, such as the
contents of the general-purpose registers and instruction queue of the CPU, are retained.
The interrupt request that specifies the macro service processing is not affected by the status of the IE flag in the program
status word (PSWL). The macro service processing can be executed even in the interrupt disabled status or while an
interrupt processing program is executed. It is disabled only when the corresponding bit in the interrupt mask registers (MK0,
MK1) is set (1).
If two or more macro service requests are issued at the same time, the sequence in which the macro service requests
are processed is determined by the default priority. Until all the macro service requests are processed, instructions are
not executed.
The µPD784054 supports macro service processing for all the internal interrupt requests.
Basically, the macro service processing executes the following two operations:
•
•
Data transfer from memory to special function register (SFR)
Data transfer from special function register (SFR) to memory
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14.8.4 Operation on completion of macro servicing (except CPU monitor modes 0 and 1)
The macro service performs processing the number of times specified during other program is executed. When the
processing has been performed the specified number of times (when the macro service counter (MSC) has reached 0), the
macro service is completed.
Figure 14-18. Operation on Completion of Macro Service
Main Routine
EI
Macro Service Request
Macro Service Processing
Last Macro Service Request
Macro Service Processing
Interrupt request is generated and
accepted after completion of macro
service (MSC = 0).
Interrupt Request Service on
Completion of Macro Service
Main Routine
EI
Other Interrupt Processing
Last Macro
Service Request
Other Interrupt Request
Macro Service
Processing
If last macro service is executed on
completion of macro service while
other interrupt processing is under execution,
last macro service is kept pending until
interrupt request is accepted.
Interrupt Request Processing on
Completion of Macro Service
Caution If data is transmitted with UART by using the macro service, a vectored interrupt request is generated
two times (refer to 12.2.8 Transmitting/receiving data with macro service).
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14.8.5 Macro service control register
(1) Macro service control word
The macro service control word consists of a macro service mode register that controls the macro service function,
and a macro service channel pointer. It is located in the address space from 0FE06H to 0FE37HNote in the main
RAM area (refer to Figure 14-20).
Figure 14-19 shows the basic configuration of the macro service control word.
Note When the LOCATION 0H instruction is executed. FFE06H to FFE37H when the LOCATION 0FH instruction
is executed.
Figure 14-19. Basic Configuration of Macro Service Control Word
Address
MSB
LSB
(FE××+1)H
FE××H
Macro Service Channel Pointer
Macro Service Mode Register
The macro service mode register sets a macro service processing mode, and the macro service channel pointer
specifies the address of the macro service channel.
To perform macro service processing, a value must be set in advance to the macro service mode register and channel
pointer corresponding to the interrupt request that can specify macro service processing.
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Figure 14-20. Format of Macro Service Control Word
Reserved Word Address
Cause
ADCHP
ADMMD
0 F E 3 7 H
0 F E 3 6 H
0 F E 3 5 H
0 F E 3 4 H
0 F E 3 3 H
0 F E 3 2 H
0 F E 3 1 H
0 F E 3 0 H
0 F E 2 F H
0 F E 2 EH
0 F E 2 DH
0 F E 2 CH
0 F E 2 B H
0 F E 2 A H
0 F E 2 9 H
0 F E 2 8 H
0 F E 2 7 H
0 F E 2 6 H
0 F E 1 DH
0 F E 1 CH
0 F E 1 B H
0 F E 1 A H
0 F E 1 9 H
0 F E 1 8 H
0 F E 1 7 H
0 F E 1 6 H
0 F E 1 5 H
0 F E 1 4 H
0 F E 1 3 H
0 F E 1 2 H
0 F E 1 1 H
0 F E 1 0 H
0 F E 0 F H
0 F E 0 EH
0 F E 0 DH
0 F E 0 CH
0 F E 0 B H
0 F E 0 A H
0 F E 0 9 H
0 F E 0 8 H
0 F E 0 7 H
0 F E 0 6 H
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
Channel Pointer
Mode Register
INTAD
STCHP2
INTST2
STMMD2
SRCHP2/CSICHP2
SRMMD2/CSIMMD2
SERCHP2
SERMMD2
STCHP
INTSR2/INTCSI2
INTSER2
INTST
STMMD
SRCHP/CSICHP1
SRMMD/CSIMMD1
SERCHP
INTSR/INTCSI1
INTSER
INTCM41
INTCM40
INTCM11
INTCM10
INTP6
SERMMD
CMCHP41
CMMMD41
CMCHP40
CMMMD40
CMCHP11
CMMMD11
CMCHP10
CMMMD10
PCHP6
PMMD6
PCHP5
INTP5
PMMD5
PCHP4
INTP4
PMMD4
PCHP3
INTP3
PMMD3
PCHP2
INTP2
PMMD2
PCHP1
INTP1
PMMD1
PCHP0
INTP0
PMMD0
OVCHP4
INTOV4
INTOV1
INTOV0
OVMMD4
OVCHP1
OVMMD1
OVCHP0
OVMMD0
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(2) Macro service mode register
The macro service mode register is an 8-bit register that specifies the operation of the macro service. This register
is mapped to the main RAM area as a part of the macro service control word (refer to Figure 14-19)
14.8.6 Macro service mode
The operation of the macro service is specified by using the macro service mode register. The macro service mode is
specified by the low-order 6 bits of the macro service mode register, and is divided into groups 0 to 2.
•
•
•
Group 0 ... Type with only control word and without channel
Group 1 ... Type with both control word and channel
Group 2 ... Macro service for monitoring CPU
The high-order 2 bits of the macro service mode register of groups 0 and 1 function as a subcommand (refer to Table
14-7).
14.8.7 Operation of macro service
The operation of the macro service is performed in the following seven modes:
Table 14-7. Classification of Macro Service Mode
Group
Group 0
Group 1
Macro Service Mode Register
CC000001
Function
Counter mode
EVTCNT
BLKTRS
BLKTRS-P
DTADIF
DTADIF-P
SELF0
CC010011
Block transfer mode
CC010100
Block transfer mode (with memory pointer)
Data differential mode
10011001
10011010
Data differential mode (with memory pointer)
CPU monitor mode 0
Group 2
10101011
10001011
CPU monitor mode 1
SELF1
The most significant bit (MSB) C of the macro service mode registers for BLKTRS and BLKTRS-P indicates the length
of the data to be handled.
•
•
When C = 0: byte data
When C = 1: word data
BLKTRS and BLKTRS-P are expressed here in terms of byte buffers. When word data is specified, read byte buffer as
word buffer.
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(1) Counter mode: EVCNT
[Macro service control word]
High-Order Address
Low-Order Address
MSC
CC000001
MSB
LSB
[Operation]
Increments (+1) or decrements (–1) the macro service counter (MSC) each time a macro service has been
generated. When the value of MSC has reached 00H (overflow), a vectored interrupt request is generated.
Table 14-8. Specifying Operation of Counter Mode
CC
00
01
10
11
Operation
Increment
Decrement
Setting prohibited
In this mode, the macro service function serves as a counter that divides the number of times the interrupt request
is generated.
Example To divide the number of times the INTOV0 interrupt request has been generated by five by using
the macro service
_
1
0 F E 0 7 H
0 F E 0 6 H
05H
01000001
[Usage]
Event counter, measurement of number of times of capture
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(2) Block transfer mode: BLKTRS
[Macro service control word]
High-Order Address
SFR. PTR
MSC
_
1
Buffer N
MSC = 1
_
MSC = N
MSC = N
1
Buffer 2
Buffer 1
CH. PTR
CC010011
Low-Order Address
MSB
LSB
[Operation]
Specifies an SFR pointer (SFR.PTR) by using a channel pointer (CH.PTR). Addresses a buffer by using CH.PTR
and the macro service counter (MSC).
Data is transferred between the SFR specified by SFR.PTR and buffer, starting from buffer 1.
Each time transfer has been completed, MSC is decremented (–1). When MSC has reached 0, a vectored
interrupt request is generated.
Table 14-9. Specifying Operation in Block Transfer Mode
CC
00
01
10
11
Operation
Buffer ← SFR
SFR ← buffer
Buffer ← SFR
SFR ← buffer
Transfer Data
Byte
Buffer Address
(Contents of CH.PTR) – (Contents of MSC) – 1
Word
(Contents of CH.PTR) – (Contents of MSC × 2) – 1
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Example To transfer the contents of port 1 (P1) (0FF01H) to a buffer by using the INTOV1 interrupt request
0 F E 5 1 H
0 F E 5 0 H
0 F E 4 FH
0 F E 4 EH
0 F E 4 DH
01H
_
03H
1
Buffer 3
Buffer 2
Buffer 1
0 F E 0 9 H
0 F E 0 8 H
51H
00010011
[Usage]
Data transmission/reception with serial interface
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(3) Block transfer mode (with memory pointer): BLKTRS-P
[Macro service control word]
High-Order Address
SFR. PTR
MSC
Buffer N
MSC = 1
_
1
MEM. PTR
Buffer 2
Buffer 1
MSC = N
MSC = N
CH. PTR
Low-Order Address
CC010100
MSB
LSB
[Operation]
An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR). Data is transferred between an
SFR specified by the SFR.PTR and the buffer addressed by the memory pointer (MEM.PTR), starting from
buffer 1.
On completion of transferring byte data, the MEM.PTR is incremented (+1). On completion of transferring word
data, the MEM.PTR is incremented (+2). Each time transfer has been completed, the macro service counter
(MSC) is decremented (–1). When MSC = 0, a vectored interrupt request is generated.
Table 14-10. Specifying Operation in Block Transfer Mode (with memory pointer)
CC
00
01
10
11
Operation
Buffer ← SFR
SFR ← buffer
Buffer ← SFR
SFR ← buffer
Transfer Data
Byte
Word
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Example To transfer the contents of the serial receive buffer: UART0 (RXB) (0FF8CH) to a buffer by using
the INTSR interrupt request
0 F E 5 0 H
8CH
03H
00H
FCH
80H
_
1
0 F E 4 FH
0 F E 4 EH
0 F E 4 DH
0 F E 4 CH
3rd Time
0 F C 8 2 H
0 F C 8 1 H
0 F C 8 0 H
Buffer 3
Buffer 2
Buffer 1
2nd Time
RXB
1st Time
+1
0 F E 2 DH
0 F E 2 CH
50H
00010100
[Usage]
Data transmission/reception with serial interface
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(4) Data differential mode: DTADIF
[Macro service control word]
High-Order Address
SFR. PTR
MSC
_
1
Value Immediately
Before
MSC = 1
Buffer N
_
MSC = N
MSC = N
1
Buffer 2
Buffer 1
CH. PTR
10011001
Low-Order Address
MSB
LSB
[Operation]
An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR), and a buffer is addressed by the CH.PTR
and macro service counter (MSC).
The difference between the current value of the SFR (including capture registers) specified by the SFR.PTR
and the “value immediately before” is written to the buffer. This current value of the SFR is used as the “value
immediately before”. Writing data is started from buffer 1.
Each time data has been written, the MSC is decremented (–1). When MSC = 0, a vectored interrupt request
is generated.
The buffer address is determined as follows:
(Buffer address) = (Contents of CH.PTR) – (Contents of MSC × 2) – 3
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Example To write the difference between the capture/compare register 00 (CC00) (0FF12H) and the “value
immediately before) to the buffer by using the INTP0 input signal as a trigger. The cycle of the INTP0
input signal is measured by using the difference in the vectored interrupt processing routine.
0 F E 6 1 H
0 F E 6 0 H
0 F E 5 FH
0 F E 5 EH
0 F E 5 DH
0 F E 5 CH
0 F E 5 BH
0 F E 5 A H
0 F E 5 9 H
0 F E 5 8 H
12H
03H
00H
00H
_
1
Buffer 3
Buffer 2
Buffer 1
0 F E 0 DH
0 F E 0 CH
61H
10011001
[Usage]
To measure cycles and pulse widths by using a capture register
Cautions 1. Do not clear the macro service counter (MSC) to 00H.
2. Initialize the “value immediately before” (with dummy data) in advance.
3. Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR).
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CHAPTER 14 INTERRUPT FUNCTIONS
(5) Data differential mode (with memory pointer): DTADIF-P
[Macro service control word]
High-Order Address
SFR. PTR
MSC
Buffer N
MSC = 1
Value Immediately
Before
_
Buffer 2
Buffer 1
MSC = N
MSC = N
1
MEM. PTR
CH. PTR
Low-Order Address
10011010
MSB
LSB
[Operation]
An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR), and a buffer is addressed by the memory
pointer (MEM.PTR) and macro service counter (MSC).
The difference between the current value of the SFR (including capture registers) specified by the SFR.PTR
and the “value immediately before” is written to the buffer. This current value of the SFR is used as the “value
immediately before”. Writing data is started from buffer 1.
Each time data has been written, the MSC is decremented (–1). When MSC = 0, a vectored interrupt request
is generated.
The MEM.PTR is not affected.
The buffer address is determined as follows:
(Buffer address) = (Contents of MEM.PTR) – (Contents of MSC × 2) + 2
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Example To write the difference between the capture/compare register 00 (CC00) (0FF12H) and the “value
immediately before” to the buffer by using the INTP0 input signal as a trigger. The cycle of the INTP0
input signal is measured by using the difference in the vectored interrupt routine.
0 F E 6 1 H
0 F E 6 0 H
0 F E 5 F H
0 F E 5 EH
0 F E 5 DH
0 F E 5 CH
0 F E 5 BH
12H
03H
00H
00H
00H
FCH
80H
0 F C 8 1 H
0 F C 8 0 H
0 F C 7 F H
0 F C 7 EH
0 F C 7 DH
0 F C 7 CH
Buffer 3
Buffer 2
Buffer 1
– 1
0 F E 0 DH
0 F E 0 CH
61H
10011010
[Usage]
To measure cycles and pulse widths by using a capture register
Cautions 1. Do not clear the macro service counter (MSC) to 00H.
2. Initialize the “value immediately before” (with dummy data) in advance.
3. Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR).
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(6) CPU monitor mode 0: SELF0
[Macro service control word]
High-Order Address
Initial Data
SFR. PTR
CH. PTR
10101011
Low-Order Address
MSB
LSB
[Operation]
Checks the internal operation of the CPU. The items to be checked are as follows:
•
•
•
•
•
Writing to program status word (PSW)
Stack pointer (SP)
Main RAM
Main RAM addressing
Compare operation
If the CPU is operating normally, the value resulting from subtracting 10 from the initial data is transferred to
an SFR specified by the SFR pointer (SFR.PTR). If an abnormality of the CPU is detected, a value different
from that transferred during normal operation is transferred.
After completion of this macro service, the contents of the main RAM and the value of SP are not destroyed,
but the value of PSW is set to 0x00H.
Therefore, this macro service must be executed when initialization is performed. After that, use CPU monitor
mode 1 to be explained next.
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CHAPTER 14 INTERRUPT FUNCTIONS
(7) CPU monitor mode 1: SELF1
[Macro service control word]
High-Order Address
Initial data
SFR. PTR
CH. PTR
10001011
Low-Order Address
MSB
LSB
[Operation]
Checks the internal operation of the CPU. The items to be checked are as follows:
•
•
•
•
Stack pointer (SP)
Main RAM
Main RAM addressing
Compare operation
If the CPU is operating normally, the value resulting from subtracting 8 from the initial data is transferred to an
SFR specified by the SFR pointer (SFR.PTR). If an abnormality of the CPU is detected, a value different from
that transferred during normal operation is transferred.
After completion of this macro service, the contents of the main RAM and the value of SP are not destroyed.
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CHAPTER 14 INTERRUPT FUNCTIONS
14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending
When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for
8 system clock cycles. However, software interrupts are not deferred.
EI
DI
BRK
BRKCS
RETCS
RETCSB !addr16
RETI
RETIB
LOCATION 0H or LOCATION 0FH
POP PSW
POPU post
MOV PSWL, A
MOV PSWL, #byte
MOVG SP, #imm24
Write instruction and bit manipulation instruction to an interrupt control registerNote, or the MK0, MK1L, IMC or ISPR
register (Excluding BT and BF instructions)
PSW bit manipulation instruction
(Excluding the BT PSWL. bit, $addr20, BF PSWL. bit, $addr20, BT PSWH. bit, $addr20, BF PSWH. bit, $addr20, SET1
CY, NOT1 CY, and CLR1 CY instructions)
Note Interrupt control registers: OVIC0, OVIC1, OVIC4, PIC0-PIC6, CMIC10, CMIC11, CMIC40, CMIC41, SERIC,
SRIC, CSIIC1, STIC, SERIC2, SRIC2, CSIIC2, STIC2, ADIC
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Cautions 1. When an interrupt related register is polled using a BF instruction, etc., the branch destination of
that BR instruction, etc., should not be that instruction. If a program is written in which a branch
is made to that instruction itself, all interrupts and macro service requests will be held pending
until a condition whereby a branch is not made by that instruction arises.
Bad Example
.
.
.
LOOP : BF PIC0.7, $LOOP
All interrupts and macro service requests are held pending until
PIC0.7 is 1.
× × ×
← Interrupts and macro service requests are not serviced until
after execution of the instruction following the BF instruction.
.
.
.
Good Example (1)
.
.
.
LOOP : NOP
BF PIC0.7, $LOOP
← Interrupts and macro service requests are serviced after execu
tion of the NOP instruction, so that interrupts are never held
pending for a long period.
.
.
.
Good Example (2)
.
.
.
LOOP : BT PIC0.7, $NEXT
Using a BTCLR instruction instead of a BT instruction has the
advantage that the flag is cleared (0) automatically.
← Interrupts and macro service requests are serviced after execu-
tion of the BR instruction, so that interrupts are never held
pending for a long period.
BR $LOOP
.
.
NEXT :
.
2. For a similar reason, if problems are caused by a long pending period for interrupts and macro
service when instructions to which the above applies are used in succession, a time at which
interrupts and macro service requests can be acknowledged should be provided by inserting an
NOP instruction, etc., in the series of instructions.
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14.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service
Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro
service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed after
completion of the interrupt service program or macro service processing.
Temporarily suspended instructions:
MOVM, XCHM, MOVBK, XCHBK
CMPME, CMPMNE, CMPMC, CMPMNC
CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
SACW
14.11 Interrupt and Macro Service Operation Timing
Interrupt requests are generated by hardware. The generated interrupt request sets (1) an interrupt request flag.
When the interrupt request flag is set (1), a time of 8 clocks (0.5 µs: fCLK = 16 MHz) is taken to determine the priority,
etc.
Following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment
processing is performed when the instruction being executed ends. If the instruction being executed is one which temporarily
defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (refer to 14.9 When
Interrupt Request and Macro Service Are Temporarily Held Pending for deferred instructions).
Figure 14-21. Interrupt Request Generation and Acknowledgment (Unit: Clocks)
Interrupt Request Flag
8 Clocks
Instruction
Interrupt Request Acknowledgment Processing/Macro Service Processing
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14.11.1 Interrupt acceptance processing time
To accept an interrupt, the time shown in Table 14-11 is required. After this time has elapsed, the interrupt processing
routine is executed.
Table 14-11. Interrupt Acceptance Processing Time
(unit: clock)
Interrupt Processing Mode
Vector table
Vectored Interrupt
Context
IROM, EMEM16
PRAM EMEM16 EMEM8 IRAM
EMEM8
Switching
Branch Detection
Stack
IRAM
26
PRAM EMEM16 EMEM8
IROM, PRAM
30
31
30+2n
31+2n
38+4n
39+4n
30
31
34
35
34+2n
35+2n
42+4n
43+4n
22
23
EMEM16, EMEM8
27
Remarks 1. IROM
: internal ROM (with high-speed fetch specified)
: internal high-speed RAM
IRAM
PRAM : peripheral RAM (only when the LOCATION 0H instruction is executed in the case of branch
destination)
EMEM16: external memory and internal ROM not specified for high-speed fetch and set to 16-bit bus
width
EMEM8 : external memory and internal ROM not specified for high-speed fetch and set to 8-bit bus
width
2. n indicates the number of wait states per byte necessary for writing to the stack.
3. If the vector table is EMEM16 or EMEM8 and if wait states are inserted when reading the vector table,
the processing time is extended. Add 2m in the case of vector interrupt with EMEM8 or m in the case
of context switching with EMEM16 to the values in the above table. m is the number of wait states per
byte necessary for reading the vector table.
4. If the branch destination is EMEM16 or EMEM8, and if wait states are inserted when reading the
instruction at the branch destination, add the number of wait states to the value in the above table.
5. If the stack is in PRAM and the value of the stack pointer (SP) is odd, add 8 to the value in the above
table. If the value of SP is odd with EMEM16, add 8+2n to the value in the above table.
6. The number of wait states is the total number of address wait and access wait states.
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14.11.2 Processing time of macro service
The processing time of the macro service differs depending on the type of the macro service, as shown in Table 14-12.
Table 14-12. Macro Service Processing Time
(unit: clock)
Type of Macro Service
Processing Time
IRAM
Other
Data Area
Group 0
Group 1
Counter mode: EVTCNT
18
24
25
24
25
30
31
30
31
28
33
—
—
—
—
—
—
32
33
32
33
—
35
78
60
Block transfer mode: BLKTRS
Buffer ← SFR
SFR ← buffer
Buffer ← SFR
SFR ← buffer
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Block transfer mode
(with memory pointer): BLKTRS-P
Data differential mode: DTADIF
Data differential mode (with memory pointer): DTADIF-P
CPU monitor mode 0: SELF0
Group 2
CPU monitor mode 1: SELF1
—
Remarks 1. Add the number of clocks specified for each case in the following cases in the other data areas.
•
•
If data size is word and data is located at an odd address in IROM or PRAM: 8 clocks
If data size is byte in EMEM16 or EMEM8, or if data size is word in EMEM16 and data is located
at an even address: n (n is the number of wait states per byte)
•
If data size is word in EMEM8, or if data size is word in EMEM16 and data is located at an
odd address: 4 + 2n (n is the number of wait states per byte)
2. Data is output to an SFR in the CPU monitor modes.
3. IRAM
: internal high-speed RAM
IROM
: internal ROM (with high-speed fetch specified)
PRAM : peripheral RAM
EMEM16: external memory and internal ROM not specified for high-speed fetch and set to 16-
bit bus width
EMEM8 : external memory and internal ROM not specified for high-speed fetch and set to 8-
bit bus width
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14.12 Restoring Interrupt Function To Initial State
If an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer,
NMI pin input, etc., the entire system must be restored to its initial state. In theµPD784054, interrupt acknowledgment related
priority control is performed by hardware. This interrupt acknowledgment related hardware must also be restored to its initial
state, otherwise subsequent interrupt acknowledgment control may not be performed normally.
A method of initializing interrupt acknowledgment related hardware in the program is shown below. The only way of
performing initialization by hardware is by RESET input.
Example
MOVW MK0, #0FFFFH
;
;
Mask all maskable interrupts
MOV
:
MK1, #0FFFFH
IRESL
CMP
BZ
ISPR, #0
$NEXT
No interrupt service programs running?
MOVG SP, #RETVAL
RETI
;
;
Forcibly change SP location
Forcibly terminate running interrupt service program, return
address = IRESL
RETVAL :
DW
LOWW (IRESL)
0
;
;
Stack data to return to IRESL with RETI instruction
DB
DB
HIGHW (IRESL)
LOWW & HIGHW are assembler operators for calculating low-order
16 bits and high-order 16 bits respectively of symbol NEXT
NEXT
:
• It is necessary to ensure that a non-maskable interrupt request is not generated via the NMI pin
during execution of this program.
• After this, on-chip peripheral hardware initialization and interrupt control register initialization are
performed.
• When interrupt control register initialization is performed, the interrupt request flags must be
cleared (0).
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14.13 Cautions
(1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation.
(2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte).
(3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.
(4) The RETCS instruction must not be used to return from a software interrupt caused by a BRKCS instruction.
(5) Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service
program. If you do not want macro service processing to be performed during a non-maskable interrupt service
program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent
macro service generation.
(6) The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledgment
will not be performed normally if a different instruction is used.
(7) Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execu-
tion (except when a high non-maskable interrupt request is generated during execution of a low-priority non-
maskable interrupt service program) and for a certain period after execution of the special instructions shown in 14.9.
Therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is undefined, in
particular after reset release, etc. In this case, depending on the value of the SP, it may happen that the program
counter (PC) and program status word (PSW) are written to the address of a write-inhibited special function register
(SFR) (refer to Table 3-6 in 3.8 Special Function Registers (SFR)), and the CPU becomes deadlocked, or the PC
and PSW are written to an unexpected signal is output from a pin, or an address is which RAM is not mounted, with
the result that the return from the non-maskable interrupt service program is not performed normally and a software
upsets occurs.
Therefore, the program following RESET release must be as follows.
CSEG AT 0
DW
STRT
CSEG BASE
STRT:
LOCATION 0FH; or LOCATION 0H
MOVG SP, #imm24
(8) When a maskable interrupt is acknowledged by vectored interruption, the RETI instruction must be used to return
from the interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction
is used.
(9) The RETCS instruction must be used to return from a context switching interrupt. Subsequent interrupt related
operations will not be performed normally if a different instruction is used.
(10) If data is transmitted with UART by using the macro service, a vectored interrupt is generated two times (refer to
12.2.8 Transmitting/receiving data with macro service).
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(11) Do not clear the macro service counter (MSC) to 00H in the data differential mode and data differential mode (with
memory pointer).
(12) Initialize the “value immediately before” (with dummy data) in advance in the data differential mode and data
differential mode (with memory pointer).
(13) Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR) in the data differential mode and data differential
mode (with memory pointer).
(14) When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction,
etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all
interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that
instruction arises.
Bad Example
.
.
.
LOOP: BF PIC0.7, $LOOP
All interrupts and macro service requests are held pending until PIC0.7 is
1.
× × ×
← Interrupts and macro service requests are not processed until after exe-
cution of the instruction following the BF instruction.
.
.
.
Good Example (1)
.
.
.
LOOP: NOP
BF PIC0.7, $LOOP
← Interrupts and macro service requests are serviced after execution of the
NOP instruction, so that interrupts are never held pending for a long period.
.
.
.
Good Example (2)
.
.
.
LOOP: BT PIC0.7, $NEXT
Using a BTCLR instruction instead of a BT instruction has the advantage
that the flag is cleared (0) automatically.
BR $LOOP
.
← Interrupts and macro service requests are serviced after execution of the
BR instruction, so that interrupts are never held pending for a long period.
.
NEXT:
.
(15) For a similar reason to that given in (14), if problems are caused by a long pending period for interrupts and macro
service when instructions to which the above applies are used in succession, a time at which interrupts and macro
service requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the series of
instructions.
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CHAPTER 15 LOCAL BUS INTERFACE FUNCTION
The local bus interface function is provided for the connection of external memory (ROM and RAM) and I/Os.
External memory (ROM and RAM) and I/Os are accessed using the RD, LWR, HWR and ASTB pin signals, with pins
AD0 to AD15 used as the multiplexed address/data bus and pins A16 to A19 as the address bus.
The basic bus interface timing is shown in Figures 15-3 to 15-8.
In addition, a wait function that is used to interface with a low-speed memory, and a bus sizing function that can change
the external data bus width between 8 bits and 16 bits are also provided.
15.1 Memory Extension Function
With the µPD784054, external memory and I/O extension can be performed by setting the memory extension mode
register (MM).
15.1.1 Memory extension mode register (MM)
The MM is an 8-bit register that performs external extension memory control, address wait number specification, and
internal fetch cycle control.
The MM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The MM
format is shown in Figure 15-1.
RESET input sets the MM register to 20H.
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Figure 15-1. Format of Memory Expansion Mode Register (MM)
Address : 0FFC4H
7
On reset : 20H
R/W
6
0
5
4
0
3
2
1
0
MM
IFCH
AW
MM3 MM2 MM1 MM0
IFCH
0
Fetches Internal ROM
Fetches at same speed as external memory.
All setting of wait control is valid.
High-speed fetch.
1
Specification of wait control is invalid.
AW
0
Specifies Address Wait
Disabled
Enabled
1
MM3 MM2 MM1 MM0
Mode
Port 4
Port 5
Port 6
P90-P93
(P40 to P47) (P50 to P57) (P60 to P63)
Port
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Single-chip
mode
0
256-byte
extension
modeNote 1
AD0-AD7
P90 : RD
P91 : LWR
P92 : HWR
P93 : ASTB
0
1K-byte
AD8,
Port
extension
AD9Note2
AD8-
modeNote 1
0
4K-byte
Port
extension
AD11Note2
modeNote 1
0
16K-byte
extension
modeNote 1
AD8-
Port
AD13Note2
AD8-AD15
0
1
64K-byte
extension
mode
256K-byte
extension
mode
A16, Port
A17
1
1M-byte
extension
mode
A16-A19
Setting prohibited
Other
Notes 1. Setting prohibited when external 16-bit bus is specified.
2. Used as an address bus.
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15.1.2 Memory map with external memory extension
The memory map when memory extension is used is shown in Figure 15-2. External devices at the same addresses
as the internal ROM area, internal RAM area and SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot
be accessed. If an access is made to these addresses, the memory or SFR in the µPD784054 has access priority and no
ASTB signal, RD signal, LWR, or HWR signal is output (these pins remain at the inactive level). The address bus output
level remains at the level output prior to this, and the address/data bus output becomes high-impedance.
Except in 1M-byte extension mode, the address output externally is output with the upper part of the address specified
by the program masked.
Example 1:
In 256-byte extension mode, when address 54321H is accessed by the program, the output address is 21H.
Example 2:
In 256-byte extension mode, when address 67821H is accessed by the program, the output address is 21H.
Figure 15-2. Memory Map (1/2)
(a) When LOCATION 0H instruction is executed
FFFFFH
External MemoryNote 1
External Memory
0FFFFH
0FFE0H
SFR
SFR
SFR
External MemoryNote 2
Note 2
0FFCFH
SFR
SFR
SFR
Internal RAM
Internal RAM
Internal RAM
0FB00H
0F600H
Use Prohibited
Use prohibited
External Memory
07FFFH
Internal ROM
Internal ROM
Internal ROM
00000H
Single-Chip Mode
256-Byte to 256 K-Byte
Extension Modes
1 M-Byte Extension Mode
Notes 1. Any extension size area in unshaded part
2. External SFR area
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Figure 15-2. Memory Map (2/2)
(b) When LOCATION 0FH instruction is executed
FFFFFH
FFFE0H
SFR
SFR
SFR
External MemoryNote 2
Note 2
FFFCFH
SFR
SFR
SFR
Internal RAM
Internal RAM
Internal RAM
FFB00H
FF600H
Use Prohibited
Use Prohibited
External MemoryNote 1
External Memory
07FFFH
00000H
Internal ROM
Internal ROM
Internal ROM
Single-Chip Mode
256-Byte to 256 K-Byte
Extension Modes
1 M-Byte Extension Mode
Notes 1. Any extension size area in unshaded part
2. External SFR area
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15.1.3 Basic operation of local bus interface
The local bus interface accesses external memory using ASTB, RD, LWR, HWR, an address/data bus (AD0 to AD15)
and address bus (A8 to A19). When the local bus interface is used, port 4 and P90 to P93 automatically operate as AD0
to AD7, RD, LWR, HWR, and ASTB. In ports 5 and 6, only the pins that correspond to the extension memory size operate
as address bus pins.
An outline of the memory access timing is shown in Figures 15-3 to 15-8.
Figure 15-3. Read Timing (8 Bits)
Condition • Bus Size : 8 bits
•
Bus Cycle : No Wait
AD8-AD15Note
,
High-Order Address
A16-A19Note
(Output)
Hi-Z
Hi-Z
Hi-Z
Low-Order Address
(Output)
AD0-AD7
Data (Input)
ASTB (Output)
RD (Output)
Note The number of address bus pins used depends on the extension mode size.
Figure 15-4. Write Timing (8 Bits)
Condition • Bus Size : 8 bits
•
Bus Cycle : No Wait
AD8-AD15Note
,
High-order Address
Data
A16-A19Note
(Output)
Hi-Z
Low-Order Address
Hi-Z
Hi-Z
AD0-AD7 (Output)
ASTB (Output)
LWR (Output)
Note The number of address bus pins used depends on the extension mode size.
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Figure 15-5. Read Timing (16 Bits, Even Address Access)
Condition • Bus Size : 16 bits
Bus Cycle : No Wait
•
•
Low-Order 8-Bit Data : Even Address
High-Order 8-Bit Data : Odd Address
•
A16-A19Note
(Output)
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order Address
(Output)
AD0-AD15
Data (Input)
ASTB (Output)
RD (Output)
Note The number of address bus pins used depends on the extension mode size.
Figure 15-6. Write Timing (16 Bits, Even Address Access)
Condition • Bus Size : 16 bits
Bus Cycle : No Wait
•
•
Low-Order 8-Bit Data : Even Address
High-Order 8-Bit Data : Odd Address
•
A16-A19Note
(Output)
High-order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order Address
Data
AD0-AD15 (Output)
ASTB (Output)
LWR, HWR (Output)
Note The number of address bus pins used depends on the extension mode size.
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Figure 15-7. Read Timing (16 Bits, Odd Address Access)
Condition • Bus Size : 16 bits
Bus Cycle : No Wait
•
•
Low-Order 8-Bit Data : Odd Address
High-Order 8-Bit Data : Even Address
•
A16-A19Note
(Output)
High-Order Address
Low-Order Address :
Odd Address
(Output)
Low-Order Address :
Even Address
(Output)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AD0-AD15
ASTB (Output)
RD (Output)
Data (Input)
Data (Input)
Note The number of address bus pins used depends on the extension mode size.
Figure 15-8. Write Timing (16 Bits, Odd Address Access)
Condition • Bus Size : 16 bits
Bus Cycle : No Wait
•
•
Low-Order 8-Bit Data : Odd Address
High-Order 8-Bit Data : Even Address
•
A16-A19Note
(Output)
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low-Order Address :
Odd Address
Low-Order Address :
Even Address
AD0-AD15 (Output)
Data
Data
ASTB (Output)
LWR (Output)
HWR (Output)
Note The number of address bus pins used depends on the extension mode size.
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15.2 Wait Function
When a low-speed memory or I/O is connected externally to theµPD784054, waits can be inserted in the external memory
access cycle.
There are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing
the access time.
15.2.1 Wait function control registers
(1) Memory extension mode register (MM)
The IFCH bit of the MM performs wait control setting for internal ROM accesses, and the AW bit performs address
wait setting.
The MM can be read or written to with an 8-bit manipulation instruction. The MM format is shown in Figure 15-9.
When RESET is input, the MM register is set to 20H, the same cycle as for external memory is used for internal ROM
accesses, and the address wait function is validated.
Figure 15-9. Format of Memory Extension Mode Register (MM)
Address : 0FFC4H
7
On reset : 20H
R/W
6
0
5
4
0
3
2
1
0
MM
IFCH
AW
MM3 MM2 MM1 MM0
IFCH
0
Fetches Internal ROM
Fetches at same speed as external memory.
All setting of wait control is valid.
High-speed fetch.
1
Specification of wait control is invalid.
AW
0
Specifies Address Wait
Disabled
Enabled
1
MM3 MM2 MM1 MM0 Sets memory
extension mode
(refer to Figure 15-1).
(2) Programmable wait control registers (PWC1/PWC2)
The PWC1 and PWC2 specify the number of waits.
PWC1 is an 8-bit register that divides the space from 0 to FFFFH into four, and specifies wait control for each of
these four spaces. PWC2 is a 16-bit register that divides the space from 10000H to FFFFH into four, and specifies
wait control for each of these four spaces.
The PWC1 can be read or written to with an 8-bit manipulation instruction, and the PWC2 with a 16-bit manipulation
instruction. The PWC1 and PWC2 formats are shown in Figures 15-10 and 15-11.
The high-order 8 bits of the PWC2 are fixed at AAH, and therefore ensure that the high-order 8 bits are set to AAH.
When RESET is input, the PWC1 is set to AAH, and the PWC2 to AAAAH, and 2-wait insertion is performed on the
entire space.
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Figure 15-10. Format of Programmable Wait Control Register 1 (PWC1)
Address : 0FFC7H
7
On reset : AAH
R/W
2
6
5
4
3
1
0
PWC1 PW31 PW30 PW21 PW20 PW11 PW10 PW01 PW00
Valid
PW31 PW30 Inserted Wait Data Access
Cycle,
Address
Cycle
Fetch Cycle
00C000H-
0
0
1
1
0
1
0
1
0
1
2
3
4
5
–
Note
00FFFFH
Time of low
level input to
WAIT pin
Valid
PW21 PW20 Inserted Wait Data Access
Cycle,
Address
008000H-
00BFFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
–
Time of low
level input to
WAIT pin
Valid
PW11 PW10 Inserted Wait Data Access
Cycle,
Address
004000H-
007FFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
–
Time of low
level input to
WAIT pin
Valid
PW01 PW00 Inserted Wait Data Access
Cycle,
Address
000000H-
003FFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
–
Time of low
level input to
WAIT pin
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Note Except the portion overlapping the internal data area.
Cautions 1. The above number of cycles is when no address cycle is appended. If an address cycle is
appended, one cycle must be added.
2. No wait cycle is inserted when fetching instructions from the internal ROM or peripheral RAM area
at high-speed.
3. Do not insert a wait cycle in the internal ROM area by using the WAIT pin.
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Figure 15-11. Format of Programmable Wait Control Register 2 (PWC2)
Address : 0FFC8H
15
On reset : AAAAH
R/W
14
0
13
1
12
0
11
1
10
0
9
1
1
8
0
0
PWC2
1
7
6
5
4
3
2
PW71 PW70 PW61 PW60 PW51 PW50 PW41 PW40
Valid
PW71 PW70 Inserted Wait Data Access
Cycle,
Address
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
080000H-
Note
4
0FFFFFH
5
Time of low
level input to
WAIT pin
—
Valid
PW61 PW60 Inserted Wait Data Access
Cycle,
Address
040000H-
07FFFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
Time of low
level input to
WAIT pin
—
Valid
PW51 PW50 Inserted Wait Data Access
Cycle,
Address
020000H-
03FFFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
Time of low
level input to
WAIT pin
—
Valid
PW41 PW40 Inserted Wait Data Access
Cycle,
Address
010000H-
01FFFFH
Cycle
Fetch Cycle
0
0
1
1
0
1
0
1
0
1
2
3
4
5
Time of low
level input to
WAIT pin
—
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Note Except the portion overlapping the internal data area.
Cautions 1. The above number of cycles is when no address cycle is appended. If an address cycle is
appended, one cycle must be added.
2. No wait cycle is inserted when fetching instructions from the peripheral RAM area.
15.2.2 Address waits
Address waits are used to secure the address decoding time. If the AW bit of the memory extension mode register (MM)
is set (1), waits are inserted in every memory accessNote. When an address wait is inserted, the high-level period of the
ASTB signal is extended by one system clock cycle (62.5 ns: fCLK = 16 MHz).
Note Except for the internal RAM, internal SFRs, and internal ROM during high-speed fetch.
If it is specified that the internal ROM is accessed in the same cycle as the external ROM, an address wait state
is inserted even when the internal ROM is accessed.
Figure 15-12. Read/Write Timing of Address Wait Function (1/3)
(a) Read timing with no address wait insertion
Note
CLK
f
AD8-AD15,
A16-A19
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
ASTB
RD
Input Data
Note fCLK: Internal system clock frequency. This signal is present inside the µPD784054 only.
Remark The above figure is an example of the 8-bit bus.
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Figure 15-12. Read/Write Timing of Address Wait Function (2/3)
(b) Read timing with address wait insertion
Note
CLK
f
AD8-AD15,
A16-A19
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order Address
Input Data
AD0-AD7
ASTB
RD
Note fCLK: Internal system clock frequency. This signal is present inside the µPD784054 only.
Remark The above figure is an example of the 8-bit bus.
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Figure 15-12. Read/Write Timing of Address Wait Function (3/3)
(c) Write timing with no address wait insertion
Note
CLK
f
AD8-AD15,
A16-A19
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
ASTB
Output Data
LWR
(d) Write timing with address wait insertion
Note
f
CLK
AD8-AD15,
A16-A19
High-Order Address
Hi-Z
Hi-Z
Hi-Z
AD0-AD7
ASTB
Low-Order Address
Output Data
LWR
Note fCLK: Internal system clock frequency. This signal is present inside the µPD784054 only.
Remark The above figure is an example of the 8-bit bus.
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15.2.3 Access waits
Access waits are inserted in the RD, LWR, or HWR signal low-level period, and extend the low-level period by 1/fCLK (62.5
ns: fCLK = 16 MHz) per cycle.
There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset
number of cycles, or the external wait function controlled by a wait signal from outside.
For wait cycle insertion control, the 1 M-byte memory space is divided into eight as shown in Figure 15-14, and control
is specified for each space by means of the programmable wait control registers (PWC1/PWC2). Waits are not inserted
in accesses to internal ROM or internal RAM using high-speed fetches. In accesses to internal SFRs, waits are inserted
at the necessary times regardless of this specification.
If access operations are specified as being performed in the same number of cycles as for external ROM, waits are
inserted also in internal ROM accesses in accordance with the PWC1 settings.
The P94 pin functions as a WAIT input pin when the PMC94 bit of the port 9 mode control register (PMC9) is set (1).
The P94 pin operates as a general-purpose I/O port pin when RESET is input (refer to Figure 15-13).
Bus timing in the case of access wait insertion is shown in Figures 15-15 to 15-17.
Caution Do not insert a wait cycle in the internal ROM area by using the WAIT pin.
Figure 15-13. Format of Port 9 Mode Control Register (PMC9)
Address : 0FF49H
7
On reset : 00H
R/W
6
0
5
0
4
3
0
2
1
0
0
0
PMC9
0
PMC94
0
PMC94
Specifies Control Mode of Pin P94
0
1
I/O port mode
WAIT input mode
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Figure 15-14. Wait Control Spaces
FFFFFH
Controlled by Bits
PW70 & PW71
512K Bytes
80000H
7FFFFH
Controlled by PWC2
Controlled by Bits
PW60 & PW61
256K Bytes
40000H
3FFFFH
Controlled by Bits
PW50 & PW51
128K Bytes
64K Bytes
20000H
1FFFFH
Controlled by Bits
PW40 & PW41
10000H
0FFFFH
Controlled by Bits
PW30 & PW31
16K Bytes
16K Bytes
16K Bytes
16K Bytes
0C000H
0BFFFH
Controlled by Bits
PW20 & PW21
08000H
07FFFH
Controlled by PWC1
Controlled by Bits
PW10 & PW11
04000H
03FFFH
Controlled by Bits
PW00 & PW01
00000H
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Figure 15-15. Read Timing of Access Wait Function (1/2)
(a) 0 wait cycles set
Note
CLK
f
AD8-AD15,
A16-A19
(Output)
High-Order Address
Hi-Z
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
Data (Input)
ASTB (Output)
RD (Output)
(b) 1 wait cycle set
Note
CLK
f
AD8-AD15,
A16-A19
(Output)
High-Order Address
Data (Input)
Hi-Z
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
ASTB (Output)
RD (Output)
Note fCLK: Internal system clock frequency. This signal is only present inside the µPD784054.
Remark The above figure is an example of the 8-bit bus.
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Figure 15-15. Read Timing of Access Wait Function (2/2)
(c) 2 wait cycles set
Note
CLK
f
AD8-AD15,
A16-A19
(Output)
High-Order Address
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
Data (Input)
ASTB (Output)
RD (Output)
Note fCLK: Internal system clock frequency. This signal is only present inside the µPD784054.
Remark The above figure is an example of the 8-bit bus.
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CHAPTER 15 LOCAL BUS INTERFACE FUNCTION
Figure 15-16. Write Timing of Access Wait Function (1/2)
(a) 0 wait cycles set
Note
fCLK
AD8-AD15,
A16-A19
(Output)
High-Order Address
Hi-Z
Hi-Z
Hi-Z
AD0-AD7
(Output)
Low-Order
Address
Data
ASTB (Output)
LWR (Output)
(b) 1 wait cycle set
Note
CLK
f
AD8-AD15,
A16-A19
(Output)
High-Order Address
Data
Hi-Z
Hi-Z
Hi-Z
AD0-AD7
(Output)
Low-Order
Address
ASTB (Output)
LWR (Output)
Note fCLK: Internal system clock frequency. This signal is only present inside the µPD784054.
Remark The above figure is an example of the 8-bit bus.
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Figure 15-16. Write Timing of Access Wait Function (2/2)
(c) 2 wait cycles set
Note
CLK
f
AD8-AD15,
A16-A9
High-Order Address
(Output)
Hi-Z
Hi-Z
Hi-Z
AD0-AD7
(Output)
Low-Order
Address
Data
ASTB (Output)
LWR (Output)
Note fCLK: Internal system clock frequency. This signal is only present inside the µPD784054.
Remark The above figure is an example of the 8-bit bus.
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CHAPTER 15 LOCAL BUS INTERFACE FUNCTION
Figure 15-17. Timing with External Wait Signal
(a) Read timing
Note
CLK
f
AD8-AD15,
A16-A9
High-Order Address
(Output)
Hi-Z
Hi-Z
Low-Order
Address
AD0-AD7
Data (Input)
ASTB (Output)
RD (Output)
WAIT (Input)
(b) Write timing
Note
CLK
f
AD8-AD15,
A16-A9
High-Order Address
(Output)
Hi-Z
AD0-AD7
(Output)
Hi-Z
Low-Order
Address
Data
ASTB (Output)
LWR (Output)
WAIT (Input)
Note fCLK: Internal system clock frequency. This signal is only present inside the µPD784054.
Remark The above figure is an example of the 8-bit bus.
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15.3 Bus Sizing Function
The µPD784054 has a bus sizing function that changes the external data bus width between 8 bits and 16 bits when
an external device is connected. By using this function, the 1M-byte memory space can be divided by eight, and the external
bus width can be specified in each memory space by using the bus width specification register (BW).
15.3.1 Bus width specification register (BW)
BW is a 16-bit register that specifies the bus width when an external device is connected.
This register cannot be accessed in 8-bit units. Be sure to access it by using a 16-bit data manipulation instruction. Figure
15-18 shows the format of BW
The value of BW differs depending on the setting of the BWD pin after RESET is input. When BWD = 0, the value of
BW is 0000H; when BWD = 1, it is 00FFH.
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Figure 15-18. Format of Bus Width Specification Register (BW)
Address : 0FFCAH
On reset : Note
R/W
15
0
14
13
0
12
0
11
0
10
0
9
0
1
8
0
0
BW
0
6
7
5
4
3
2
BW7 BW6 BW5 BW4 BW3 BW2 BW1 BW0
Valid
BW7
Specifies external data bus width
Address
080000H-
0FFFFFH
0
1
8-bit bus
16-bit bus
Valid
BW6
Specifies external data bus width
Address
040000H-
07FFFFH
0
1
8-bit bus
16-bit bus
Valid
BW5
Specifies external data bus width
Address
020000H-
03FFFFH
0
1
8-bit bus
16-bit bus
Valid
BW4
Specifies external data bus width
Address
010000H-
01FFFFH
0
1
8-bit bus
16-bit bus
Valid
BW3
Specifies external data bus width
Address
00C000H-
00FFFFH
0
1
8-bit bus
16-bit bus
Valid
BW2
Specifies external data bus width
Address
008000H-
00BFFFH
0
1
8-bit bus
16-bit bus
Valid
BW1
Specifies external data bus width
Address
004000H-
007FFFH
0
1
8-bit bus
16-bit bus
Valid
BW0
Specifies external data bus width
Address
000000H-
003FFFH
0
1
8-bit bus
16-bit bus
Note The value of this register on reset differs depending on the setting of the BWD pin, as follows:
BWD = 0: 0000H
BWD = 1: 00FFH
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15.4 Cautions
(1) No wait cycle is inserted when instructions are fetched from the internal ROM or peripheral RAM area at high speeds.
(2) Do not insert a wait cycle in the internal ROM area by using the WAIT pin.
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CHAPTER 16 STANDBY FUNCTION
16.1 Configuration and Function
The µPD784054 has a standby function that enables the system power consumption to be reduced. The standby function
includes four modes as follows:
•
•
HALT mode ....................... In this mode the CPU operating clock is stopped. Intermittent operation in combination
with the normal operating mode enables the total system power consumption to be
reduced.
IDLE mode ........................ In this mode the oscillator continues operating while the entire remainder of the system
is stopped. Normal program operation can be restored at a low power consumption close
to that of the STOP mode and in a time equal to that of the HALT mode.
•
•
STOP mode ...................... In this mode the oscillator is stopped and the entire system is stopped.
........................................... Ultra-low power consumption can be achieved, consisting of leakage current only.
Standby function mode .... In this mode the standby function (HALT/IDLE/STOP mode) can be made invalid by
inputting a high level to the MODE 1 pin.
It can be used when the standby mode must not be used for some reason in an application.
These modes are set by software. The diagram of the standby mode (STOP/IDLE/HALT mode) transition is shown in
Figure 16-1, and the block diagram of the standby function in Figure 16-2.
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Figure 16-1. Diagram of Standby Mode Transition
MODE1 = H
Standby
Function
Invalid
MODE1 = H
MODE1 = L
MODE1 = L
Macro Service Request
End of 1st Service
Program
Operation
Macro
Service
End of Macro Service
Wait of
Oscillation
Stabilization
Interrupt Request
P Setting
STO
ESET Input
Note
R
IDLE Setting
acro Service Request
M
End of 1st Service
IDLE
(Standby)
HALT
(Standby)
STOP
(Standby)
Masked Interrupt
Request
RESET input
RESET input
Note Unmasked interrupt request only
Remark Only external input is valid as NMI. The watchdog timer must not be used to release the standby mode (STOP,
HALT, or IDLE mode).
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Figure 16-2. Block Diagram of Standby Function
Oscillation Stabilization
Timer (19)
RAM PROTECT
OSTS0
OSTS1
OSTS2
EXTC
To Peripheral Circuit
Selector
System
Clock
Oscillator
f
XX/2 (fCLK)
f
XX
Frequency
Divider
CPU CLK
HLT F/F
HLT Bit Setting
STOP Bit Setting
MODE1
Q
S
EXTC
Q
R
Macro Service
Request
IDLE F/F
Q
S
Q
R
STP F/F2
Q
S
ESNMI
Rising Edge
Q
R
Detection
NMI
Selector
STP F/F1
Q
Rising Edge
Detection
S
Q
R
INTC
Interrupt
Macro Service
Request
RESET
CHAPTER 16 STANDBY FUNCTION
16.2 Control Registers
16.2.1 Standby control register (STBC)
The STBC is a register used to control the standby mode.
To prevent entry into the standby mode due to an inadvertent program loop, the STBC register can only be written to
with a dedicated instruction. This dedicated instruction, MOV STBC, #byte, has a special code configuration (4 bytes), and
a write is only performed if the 3rd and 4th bytes of the operation code are mutual complements.
If the 3rd and 4th bytes of the operation code are not mutual complements, a write is not performed and an operand error
interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that was
the source of the error, and thus the address that was the source of the error can be identified from the return address saved
in the stack area.
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.
As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics
assembler, RA78K4, only the correct dedicated instruction is generated when MOV STBC, #byte is written), system
initialization should be performed by the program.
Other write instructions (MOV STBC, A, AND STBC, #byte, SET1 STBC.7, etc.) are ignored and do not perform any
operation. That is, a write is not performed to the STBC, and an interrupt such as an operand error interrupt is not generated.
The STBC can be read at any time by a data transfer instruction.
RESET input sets the STBC register to 30H.
The format of the STBC is shown in Figure 16-3.
Figure 16-3. Standby Control Register (STBC) Format
Address : 0FFC0H
7
On reset : 30H
R/W
6
0
5
1
4
1
3
0
2
1
0
STBC
0
0
STP HLT
STP HLT
Controls CPU Operation Control
Normal operating mode
HALT mode
0
0
1
1
0
1
0
1
STOP mode
IDLE mode
Caution If the STOP mode is used when using external clock input, the EXTC bit of the oscillation stabilization
time specification register (OSTS) must be set (1) before setting STOP mode. If the STOP mode is used
with the EXTC bit cleared (0) when using external clock input, the µPD784054 may suffer damage or
reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock
input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
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16.2.2 Oscillation stabilization time specification register (OSTS)
The OSTS specifies the oscillator operation and the oscillation stabilization time when STOP mode is released. Set the
state of the clock oscillator operation to the EXTC bit of the OSTS. STOP mode can be set when external clock input is
used only when the EXTC bit is set (1).
Bits OSTS0 to OSTS2 of the OSTS select the oscillation stabilization time when STOP mode is released. In general,
an oscillation stabilization time of at least 40 ms should be selected when a crystal resonator is used, and at least 4 ms
when a ceramic oscillator is used.
The time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the
capacitance of the connected capacitor. Therefore, if you want to set a short oscillation stabilization time, you should consult
the crystal resonator or ceramic resonator manufacturer.
The OSTS can be read/written only with an 8-bit manipulation instruction.
RESET input clears the OSTS register to 00H.
The format of the OSTS is shown in Figure 16-4.
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Figure 16-4. Format of Oscillation Stabilization Time Specification Register (OSTS)
Address : 0FFCFH
On reset : 00H
R/W
7
6
0
5
0
4
0
3
0
2
1
0
OSTS EXTC
OSTS2 OSTS1 OSTS0
EXTC
0
Selects External Clock
X2 pin is open when crystal/ceramic oscillation
is used or when external clock is used.
1
Input signal in reverse phase to that input to
X1 pin to X2 pin when external clock is used.
(fCLK = 16 MHz)
Selects Oscillation
Stabilization Time
EXTC OSTS2 OSTS1 OSTS0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
×
0
0
1
1
0
0
1
1
×
0
1
0
1
0
1
0
1
×
219/fCLK (32.8 ms)
218/fCLK (16.4 ms)
217/fCLK (8.19 ms)
216/fCLK (4.10 ms)
215/fCLK (2.05 ms)
214/fCLK (1.02 ms)
213/fCLK (512 µs)
212/fCLK (256 µs)
28/fCLK (16 µs)
Remark fCLK : internal system clock
: don’t care
×
Cautions 1. When crystal/ceramic oscillation is used, the EXTC bit of the oscillation stabilization time
specification register (OSTS) must be cleared (0) before use. If the EXTC bit is set (1), oscillation
will stop.
2. If the STOP mode is used when using external clock input, the EXTC bit must be set (1) before
setting STOP mode. If the STOP mode is used with the EXTC bit cleared (0) the µPD784054 may
suffer damage or reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the
clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
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16.3 HALT Mode
16.3.1 HALT mode setting and operating states
The HALT mode is selected by setting (1) the HLT bit of the standby control (STBC) register or clearing (0) the STP bit.
The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. HALT
mode setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If a condition that releases the HALT mode comes into effect when the HALT mode is being set, the
HALT mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt
service program is performed. Before this branch execution, the instructions after the HALT mode
setting may be executed for 6 clocks. After restoring from the interrupt service, to execute an
instruction after setting the HALT mode, insert three NOP instructions before the instruction. To be
sure to set the HALT mode, take the necessary precautions such as clearing the interrupt request
before setting the HALT mode.
Table 16-1. Operating States in HALT Mode
Clock oscillator
Internal system clock
CPU
Operating
Operating
Note 1
Operation stopped
I/O lines
Retain state prior to HALT mode setting
Continue operating
Peripheral functions
Internal RAM
Bus lines
Retained
AD0 to AD7
AD8 to AD15
A16 to A19
High-impedance
Note 2
Retained
RD, LWR, HWR output
ASTB output
High level
Low level
Notes 1. Macro service processing is executed.
2. If the fetch address is in external memory with 16-bit bus width, AD8 to AD15 are made high-impedance after
the interrupt processing of the macro service is executed.
16.3.2 HALT mode release
HALT mode can be released by the following three sources.
•
•
•
Non-maskable interrupt request
Maskable interrupt request (vectored interrupt/context switching/macro service)
RESET input
Release sources and an outline of operations after release are shown in Table 16-2.
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Table 16-2. HALT Mode Release and Operations after Release
Note 1
Note 2
Release Source MK
IE
State on Release
Operation after Release
Non-maskable
interrupt request
(NMI pin input
only. Excluding
×
×
•
•
Non-maskable interrupt service program
not being executed
Interrupt request acknowledgment
Low-priority non-maskable interrupt
service program being executed
watchdog
•
•
Service program for same request being
executed
Execution of instruction after MOV STBC/
#byte instruction (interrupt request that
Note 5
timer
.)
Note 3
High-priority non-maskable interrupt
service program being executed
released HALT mode is held pending
)
Maskable
0
1
•
•
•
Interrupt service program not being
executed
Interrupt request acknowledgment
interrupt request
(excluding macro
service request)
Low-priority maskable interrupt service
program being executed
Note 4
PRSL bit
cleared (0) during execution
of priority level 3 interrupt service program
•
Same-priority maskable interrupt service
Execution of instruction after MOV STBC/
program being executed
#byte instruction (interrupt request that
Note 4
Note 3
(If PRSL bit
is cleared (0), excluding
released HALT mode is held pending
)
execution of priority level 3 interrupt
service program)
•
High-priority interrupt service program
being executed
0
1
0
0
×
×
—
—
—
HALT mode maintained
Macro service
request
Macro service processing execution
End condition not established → HALT
mode again
End condition established → Same as
release by maskable interrupt request
1
×
×
—
—
HALT mode maintained
Normal reset operation
RESET input
×
Notes 1. Interrupt mask bit in individual interrupt request source
2. Interrupt enable flag in program status word (PSW)
3. Pending interrupt requests are acknowledged when acknowledgment becomes possible.
4. Bit in interrupt mode control register (IMC)
5. The HALT mode cannot be released by the watchdog timer.
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(1) Release by non-maskable interrupt
When a non-maskable interrupt is generated, the µPD784046 is released from HALT mode irrespective of whether
the interrupt acknowledgment enabled state (EI) or disabled state (DI) is in effect.
When the µPD784054 is released from HALT mode, if the non-maskable interrupt that released HALT mode can
be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service
program. If the interrupt cannot be acknowledged, the instruction following the instruction that set the HALT mode
(the MOV STBC, #byte instruction) is executed, and the non-maskable interrupt that released the HALT mode is
acknowledged when acknowledgment becomes possible. Refer to 14.6 Non-Maskable Interrupt
Acknowledgment Operation for details of non-maskable interrupt acknowledgment.
(2) Release by maskable interrupt request
HALT mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt
mask flag is 0.
When HALT mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (IE) is
set (1), a branch is made to the interrupt service program. If the interrupt cannot be acknowledged and if the IE flag
is cleared (0), execution is resumed from the instruction following the instruction that set the HALT mode. Refer
to 14.7 Maskable Interrupt Acknowledgment Operation for details of interrupt acknowledgment.
With macro service, HALT mode is released temporarily, service is performed once, then HALT mode is restored.
When macro service has been performed the specified number of times, HALT mode is released. The operation
after release in this case is the same as for release by a maskable interrupt described earlier.
(3) Release by RESET input
The program is executed after branching to the reset vector address, as in a normal reset operation. However,
internal RAM contents retain their value directly before HALT mode was set.
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CHAPTER 16 STANDBY FUNCTION
16.4 STOP Mode
16.4.1 STOP mode setting and operating states
The STOP mode is selected by setting (1) the STP bit of the standby control register (STBC) register or clearing (0) the
HLT bit.
The only writes that can be performed on the STBC register are 8-bit data writes by means of a dedicated instruction.
STOP mode setting is therefore performed by means of the “MOV STBC, #byte” instruction,
Caution If a condition that releases the HALT mode comes into effect when the STOP mode is being set (refer
to 16.3.2 HALT mode release), the STOP mode is not entered, and the next instruction is executed,
or a branch to a vectored interrupt service program is performed. Before this branch execution, the
instructions after the STOP mode setting may be executed for 6 clocks. After restoring from the
interrupt service, to execute an instruction after setting the STOP mode, insert three NOP instructions
before the instruction. To be sure to set the STOP mode, take the necessary precautions such as
clearing the interrupt request before setting the STOP mode.
Table 16-3. Operating States in STOP Mode
Clock oscillator
Internal system clock
CPU
Oscillation stopped
Stopped
Operation stopped
I/O lines
Retain state prior to STOP mode setting
Note
Peripheral functions
Internal RAM
Bus lines
All operation stopped
Retained
AD0 to AD15
A16 to A19
High-impedance
High-impedance
High-impedance
High-impedance
RD, LWR, HWR output
ASTB output
Note A/D converter operation is stopped, but if the AM0 bit or AM1 bit of the A/D converter mode register (ADM) is
set (1), the current consumption does not decrease.
Cautions 1. If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS)
register is cleared (0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock
generator leakage. Therefore, when the STOP mode is used in a system that uses an external clock,
the EXTC bit of the OSTS must be set (1). If STOP mode setting is performed in a system to which
an external clock is input when the EXTC bit of the OSTS is cleared (0), the µPD784054 may suffer
damage or reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the
clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
2. Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register
(ADM)) before setting the STOP mode.
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16.4.2 STOP mode release
STOP mode is released by NMI input, INTP4 input, INTP5 input, and RESET input.
Table 16-4. STOP Mode Release and Operations after Release
Release
State after Release
Operation after Release
Source
NMI pin input • Non-maskable interrupt service
program not being executed
Interrupt request acknowledgment
• Low-priority non-maskable interrupt
service program being executed
• NMI pin input service program being
executed
Execution of instruction after MOV STBC/
#byte instruction (interrupt request that
Note
• High-priority non-maskable interrupt
service program being executed
released STOP mode is held pending
)
RESET input
—
Normal reset operation
Note Pending interrupt requests are acknowledged when acknowledgment becomes possible.
(1) STOP mode release by NMI input
The oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (INTM0) is
input to the NMI input. STOP mode is released after the oscillation stabilization time specified by the oscillation
stabilization time specification register (OSTS) elapses.
When the µPD784054 is released from STOP mode, if a non-maskable interrupt by NMI pin input can be
acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if
the STOP mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following
the instruction that set the STOP mode, and a branch is made to the NMI interrupt service program when
acknowledgment becomes possible (by execution of an RETI instruction, etc.).
Refer to 14.6 Non-Maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment.
Figure 16-5. STOP Mode Release by NMI Input
STOP
Oscillator
fCLK
STP F/F1
STP F/F2
NMI Input
Rising Edge
Specified
Oscillator Stopped
Oscillation Stabilization
Count Time
(2) STOP mode release by RESET input
When RESET input falls from high to low and the reset state is established, the oscillator resumes oscillation. The
oscillation stabilization time should be secured while RESET is active. Thereafter, normal operation is started when
RESET rises.
Unlike an ordinary reset operation, data memory retains its contents prior to STOP mode setting.
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CHAPTER 16 STANDBY FUNCTION
16.5 IDLE Mode
16.5.1 IDLE mode setting and operating states
The IDLE mode is selected by setting (1) both the STP bit and the HLT bit of the standby control (STBC) register.
The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE mode
setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If a condition that releases the HALT mode comes into effect when the IDLE mode is being set (refer
to 16.3.2 HALT mode release), the IDLE mode is not entered, and the next instruction is executed, or
a branch to a vectored interrupt service program is performed. Before this branch execution, the
instructions after the IDLE mode setting may be executed for 6 clocks. After restoring from the
interrupt service, to execute an instruction after setting the IDLE mode, insert three NOP instructions
before the instruction. To be sure to set the IDLE mode, take the necessary precautions such as
clearing the interrupt request before setting the IDLE mode.
Table 16-5. Operating States in IDLE Mode
Clock oscillator
Internal system clock
CPU
Oscillation continues
Stopped
Operation stopped
I/O lines
Retain state prior to IDLE mode setting
Note
Peripheral functions
Internal RAM
Bus lines
All operation stopped
Retained
AD0 to AD15
A16 to A19
High-impedance
High-impedance
High-impedance
High-impedance
RD, LWR, HWR output
ASTB output
Note A/D converter operation is stopped, but if the AM0 bit or AM1 bit of the A/D converter mode register (ADM) is
set, the current consumption does not decrease.
Caution Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register (ADM))
before setting the IDLE mode.
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16.5.2 IDLE mode release
IDLE mode is released by NMI input, or RESET input.
Table 16-6. IDLE Mode Release and Operations after Release
Release
Source
State after Release
Operation after Release
NMI pin input • Non-maskable interrupt service
program not being executed
Interrupt request acknowledgment
• Low-priority non-maskable interrupt
service program being executed
• NMI pin input service program being
executed
Execution of instruction after MOV STBC/
#byte instruction (interrupt request that
Note
• High-priority non-maskable interrupt
service program being executed
released IDLE mode is held pending
)
RESET input
—
Normal reset operation
Note Pending interrupt requests are acknowledged when acknowledgment becomes possible.
(1) IDLE mode release by NMI input
IDLE mode is released when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the
NMI input.
When the µPD784054 is released from IDLE mode, if a non-maskable interrupt by NMI pin input can be
acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if
the IDLE mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following
the instruction that set the IDLE mode, and a branch is made to the NMI interrupt service program when
acknowledgment becomes possible (by execution of an RETI instruction, etc.).
Refer to 14.6 Non-Maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment.
(2) IDLE mode release by RESET input
Normal operation is started when RESET rises after RESET input falls from high to low.
Unlike an ordinary reset operation, data memory retains its contents prior to IDLE mode setting.
Caution When the execution of the IDLE mode instruction contends with the interrupt of release source of
the IDLE mode, the STOP mode is released after the STOP mode has been executed, instead of the
normal operation where the IDLE mode is released after the IDLE mode has been executed, because
of a malfunction of the µPD784054. Therefore, when the IDLE mode is released, the wait operation
for the oscillation stabilization time set by the oscillation stabilization time specification register
(OSTS) may be executed even though the IDLE mode is set in software (Usually, the µPD784054
does not wait the oscillation stabilization time when the IDLE mode is released.) If there are
problems with waiting for the oscillation stabilization time when the IDLE mode is released, set the
value of the oscillation stabilization time set by the OSTS as short as possible.
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16.6 Check Items When STOP Mode/IDLE Mode Is Used
Check items required to reduce the current consumption when STOP mode/IDLE mode is used are shown below.
(1) Is the output level of each output pin appropriate?
The appropriate output level for each pin varies according to the next-stage circuit. You should select the output
level that minimizes the current consumption.
•
If high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power
supply to the port, resulting in an increased current consumption. This applies when the next-stage circuit is a
CMOS IC, etc. When the power supply is off, the input impedance of a CMOS IC is low. In order to suppress
the current consumption, or to prevent an adverse effect on the reliability of the CMOS IC, low level should be
output. If a high level is output, latchup may result when power is turned on again.
•
•
Depending on the next-stage circuit, inputting low level may increase the current consumption. In this case, high-
level or high-impedance output should be used to reduce the current consumption.
If the next-stage circuit is a CMOS IC, the current consumption of the CMOS IC may increase if the output is made
high-impedance when power is supplied to it (the CMOS IC may also be overheated and damaged). In this case
you should output an appropriate level, or pull the output high or low with a resistor.
The method of setting the output level depends on the port mode.
•
•
When a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore
the on-chip hardware status must be taken into consideration when setting the output level.
In port mode, the output level can be set by writing to the port output latch and port mode register by software.
When a port is in control mode, its output level can be set easily by changing to port mode.
(2) Is the input pin level appropriate?
The voltage level input to each pin should be in the range between VSS potential and VDD potential. If a voltage outside
this range is applied, the current consumption will increase and the reliability of the µPD784054 may be adversely
affected.
Also ensure that an intermediate potential is not applied.
(3) Are pull-up resistors necessary?
An unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. A mode
should be specified in which pull-up resistors are used only for parts that require them.
If there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull-
up resistor externally and specify a mode in which the on-chip pull-up resistor is not used.
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(4) Is processing of the address bus, address/data bus, etc., appropriate?
In STOP mode and IDLE mode, the address bus, address/data bus, RD and LWR, HWR pins become high-
impedance. Normally, these pins are pulled high with a pull-up resistor. If this pull-up resistor is connected to the
backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is
low, a current will flow through the pull-up resistor, and the current consumption will increase. Therefore, the pull-
up resistor should be connected to the non-backed-up power supply side as shown in Figure 16-6.
Also, in STOP mode and IDLE mode the ASTB pin also becomes high impedance. Countermeasures should be
taken with reference to the points noted in (1).
Figure 16-6. Example of Address/Data Bus Processing
Backed-Up Power Supply
Non-Backed-Up Power Supply
VDD
VDD
µ
PD784054
CMOS IC, etc.
IN/OUT
ADn
(n = 0-15)
VSS
VSS
(5) A/D converter
The current flowing to the AVDD, AVREF1 pins can be reduced by clearing (0) the AM0 and AM1 bits of the A/D converter
mode register (ADM).
Make sure that the AVDD pin is not at the same potential as the VDD pin. Unless power is supplied to the AVDD pin
in the STOP mode, not only does the current consumption increase, but the reliability is also affected.
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16.7 Cautions
(1) If a condition that releases the HALT mode comes into effect when the HALT/STOP/IDLE mode (hereafter referred
to as standby mode) is being set (refer to 16.3.2 HALT mode release), the standby mode is not entered, and the
next instruction is executed, or a branch to a vectored interrupt service program is performed. Before this branch
execution, the instructions after the standby mode setting may be executed for 6 clocks. After restoring from the
interrupt service, to execute an instruction after setting the standby mode, insert three NOP instructions before the
instruction. To be sure to set the standby mode, take the necessary precautions such as clearing the interrupt request
before setting the standby mode.
(2) When crystal/ceramic oscillation is used, the EXTC bit must be cleared (0) before use. If the EXTC bit is set (1),
oscillation will stop.
(3) If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS) register is cleared
(0), the X1 pin is shorted internally to VSS (GND potential) to suppress clock generator leakage. Therefore, when
the STOP mode is used in a system that uses an external clock, the EXTC bit of the OSTS must be set (1). If STOP
mode setting is performed in a system to which an external clock is input when the EXTC bit of the OSTS is cleared
(0), the µPD784054 may suffer damage or reduced reliability.
When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the
X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).
(4) Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register (ADM)) before
setting the STOP or IDLE mode.
(5) When the execution of the IDLE mode instruction contends with the interrupt of release source of the IDLE mode,
the STOP mode is released after the STOP mode has been executed, instead of the normal operation where the
IDLE mode is released after the IDLE mode has been executed, because of a malfunction of the µPD784054.
Therefore, when the IDLE mode is released, the wait operation for the oscillation stabilization time set by the
oscillation stabilization time specification register (OSTS) may be executed even though the IDLE mode is set in
software (Usually, the µPD784054 does not wait the oscillation stabilization time when the IDLE mode is released.)
If there are problems with waiting for the oscillation stabilization time when the IDLE mode is released, set the value
of the oscillation stabilization time set by the OSTS as short as possible.
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CHAPTER 17 RESET FUNCTION
17.1 Reset Function
When low level is input to the RESET input pin, a system reset is affected, the various hardware units are set to the states
shown in Table 17-2, and all pins except the power supply pins and the X1 and X2 CLKOUT pins are placed in the high-
impedance state. Table 17-1 shows the pin statuses on reset and after reset release.
When the RESET input changes from low to high level, the reset state is released, the contents of address 00000H of
the reset vector table are set in bits 0 to 7 of the program counter (PC), the contents of address 00001H in bits 8 to 15, and
0000B in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. A reset start
can therefore be performed from any address in the base area.
The contents of the various registers should be initialized as required in the program in the base area.
To prevent misoperation due to noise, the RESET input pin incorporates an analog delay noise elimination circuit (refer
to Figure 17-1).
Figure 17-1. Acknowledgment of Reset Signal
Execution of Instruction
at Reset Start Address
Delay
Delay
Delay PC Initialization, etc.
RESET
(Input)
Internal Reset Signal
Reset Start
Reset End
In a reset operation upon powering on and STOP mode release by reset, the RESET signal must be kept active until
the oscillation stabilization time has elapsed (approx. 40 ms, depending on the resonator used).
Figure 17-2. Power-On Reset Operation
Execution of Instruction at
Reset Start Address
Oscillation Stabilization Time
Delay PC Initialization, etc.
VDD
RESET
(Input)
Internal Reset Signal
Reset End
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Table 17-1. Pin Status during Reset Input and after Clearing Reset
Pin Name
P00-P03
P10-P12
P20
I/O
I/O
During Reset
Hi-Z
Immediately after Clearing Reset
Hi-Z (input port mode)
Input
I/O
Hi-Z (input port)
P21-P27
P30-P37
P40-P47
P50-P57
P60-P63
P70-P77
P80-P87
P90-P94
CLKOUT
Hi-Z (input port mode)
Input
Hi-Z (input port)
I/O
Hi-Z (input port mode)
Clock output
Output
Clock output
Figure 17-3. Timing on Reset Input
RESET
(Input)
CLKOUT
(output)
Hi-Z
Other I/O Ports
Reset Period
Clearing Reset - Instruction Execution Time
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Table 17-2. State of Hardware after Reset (1/2)
Hardware
State after Reset
Contents of reset vector table
(0000H, 0001H) are set
Program counter (PC)
Note
Stack pointer (SP)
Undefined
Program status word (PSW)
02H
Note
On-chip RAM
Data memory
General-purpose register
Undefined
Port
Port 0 to port 9
Undefined (high impedance)
Mode registers (PM0 to PM6, PM9)
FFH
00H
Mode control registers (PMC2, PMC3, PMC9)
Port read control register (PRDC)
Pull-up resistor option register (PUOL, PUOH)
Timer registers (TM0, TM1, TM4)
Timer/counter
0000H
Capture/compare registers (CC00 to CC03)
Compare registers (CM10, CM11, CM40, CM41)
Timer unit mode registers (TUM0)
Undefined
00H
Timer mode control registers (TMC, TMC4)
Timer output control registers (TOC0, TOC1)
Prescaler mode registers (PRM, PRM4)
Noise protection control register (NPC)
Interrupt valid edge flag registers (IEF1, IEF2)
Undefined
00H
Watchdog timer mode register (WDM)
A/D converter
A/D converter mode register (ADM)
A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to ADCR7H)
Asynchronous serial interface mode registers (ASIM, ASIM2)
Asynchronous serial interface status registers (ASIS, ASIS2)
Serial receive buffers (RXB, RXB2)
Undefined
00H
Serial interface
Undefined
Serial transmit shift registers (TXS, TXS2)
Clocked serial interface mode registers (CSIM1, CSIM2)
Serial shift registers (SIO1, SIO2)
00H
Undefined
00H
Baud rate generator control registers (BRGC, BRGC2)
External interrupt mode registers (INTM0, INTM1)
Note If the HALT, STOP, or IDLE mode is released by using the RESET input, the values immediately before each mode
has been set are retained.
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Table 17-2. State of Hardware after Reset (2/2)
Hardware
State after Reset
Interrupt
Interrupt control registers (OVIC0, OVIC1, OVIC4, PIC0 to PIC6, CMIC10,
CMIC11, CMIC40, CMIC41, SERIC, SRIC, CSIIC1, STIC, SERIC2, SRIC2,
CSIIC2, STIC2, ADIC)
43H
Interrupt mask registers
MK0, MK1
FFFFH
FFH
MK0L, MK0H, MK1L, MK1H
Interrupt mode control register (IMC)
In-service priority register (ISPR)
80H
00H
Memory extension mode register (MM)
Programmable wait control register
20H
PWC1
PWC2
AAH
AAAAH
Bus width specification register (BW)
0000H (BWD = 0)
00FFH (BWD = 1)
Standby control register (STBC)
30H
00H
CDH
Oscillation stabilization time specification register (OSTS)
Internal memory size switching register (IMS)
17.2 Caution
Reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached
the prescribed voltage.
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CHAPTER 18 µPD78F4046
18.1 Memory Mapping of µPD78F4046
The µPD78F4046 has 64K bytes of flash memory and 2048 bytes of internal RAM.
The µPD78F4046 has a function to not use part of the internal memory (memory size select function). This function is
effected by software.
The memory size is changed by using the internal memory size select register (IMS).
This register can be read or written by using an 8-bit manipulation instruction. Data can be only written to the IMS of
the µPD78F4046, however. The IMS of the µPD784054 retains the value at reset even if data is written to it.
Therefore, the value of the IMS at RESET differs depending on the model. In the case of the µPD784054, it is CDH.
The value of the IMS of the µPD78F4046 is set to DEH at RESET.
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Figure 18-1. Format of Internal Memory Size Select Register (IMS)
Address : 0FFFCH
On reset : Note
7
1
6
5
4
3
1
2
1
1
0
IMS
1
ROM1 ROM0
RAM1 RAM0
ROM1 ROM0
Selects Internal ROM Capacity
PD784054
µ
PD78F4046
µ
32K bytes
64K bytes
0
0
0
1
32K bytes
Invalid
Other
Setting prohibited
RAM1 RAM0
Selects Peripheral RAM Capacity
PD784054
µPD78F4046
768 bytes
µ
0
1
1
0
512 bytes
Invalid
1.5K bytes
Other
Setting prohibited
Note The value at reset differs depending on the model.
µPD784054 : CDH
µPD78F4046 : DEH
Cautions 1. Writing to the internal memory size select register (IMS) is valid only with the µPD78F4046. The
IMS of the µPD784054 holds the value at RESET even if data is written to it.
2. To develop a program for the µPD784054 using the µPD78F4046, set the value of the IMS to CDH.
When the value of the IMS is set to CDH, the peripheral RAM capacity of the µPD78F4046 is 768
bytes, but the peripheral RAM capacity of the µPD784054 is 512 bytes. When using a mask ROM,
therefore, exercise care that addresses 0FA00H to 0FAFFH of the peripheral RAM area of the
µPD78F4046 are not used (when the LOCATION 0H instruction is executed).
18.2 Programming µPD78F4046
The flash memory can be written with the µPD78F4046 mounted on the target system (on-board). Connect a dedicated
flash programmer (Flashpro II (part number: FL-PR2)/Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and
target system to write the flash memory.
The flash memory can also be written using the adapter for writing flash memory connected to Flashpro II/Flashpro III.
Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.
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CHAPTER 18 µPD78F4046
18.2.1 Selecting communication mode
The flash memory is written by using a Flashpro II/Flashpro III and by means of serial communication. Select a
communication mode from those listed in Table 18-1. To select a communication mode, the format shown in Figure 18-
2 is used. Each communication mode is selected by the number of VPP pulses shown in Table 18-1.
Table 18-1. Communication Modes
Communication Mode
3-wire serial I/O
Number of Channels
Pins Used
Number of VPP Pulses
2
P34/ASCK/SCK1
P33/TxD/SO1
P32/RxD/SI1
0
P37/ASCK2/SCK2
P36/TxD2/SO2
P35/RxD2/SI2
1
UART
2
P33/TxD/SO1
P32/RxD/SI1
8
9
P36/TxD2/SO2
P35/RxD2/SI2
Caution Be sure to select the communication mode with the number of VPP pulses as shown in Table 18-1.
Figure 18-2. Selecting Format of Communication Mode
10V
MODE/VPP
RESET
V
DD
1
2
n
V
SS
VDD
V
SS
18.2.2 Function of flash memory programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the
flash memory are performed. Table 18-2 shows the major functions of flash memory programming.
Table 18-2. Major Functions of Flash Memory Programming.
Function
Batch erase
Description
Erases all contents of memory.
Block erase
Erases specified memory block with one block consisting of 16K bytes.
Checks erased state of entire memory.
Batch blank check
Block blank check
Data write
Checks erased state of specified block.
Writes to flash memory based on write start address and number of data written (number of bytes).
Compares all contents of memory with input data.
Batch verify
Block verify
Compares contents of specified memory block with input data.
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18.2.3 Connecting Flashpro II/Flashpro III
How the Flashpro II/Flashpro III is connected to the µPD78F4046 differs to the µPD78F4046 depending on the
communication mode (3-wire serial I/O or UART). Figures 18-3 and 18-4 show the connections in the respective modes.
Figure 18-3. Connecting Flashpro II/Flashpro III in 3-Wire Serial I/O Mode
Flashpro II/Flashpro III
µ
PD78F4046
VPP
VDD
V
PP
V
DD
RESET
SCK
RESET
SCK1 or SCK2
SI1 or SI2
SO
SI
SO1 or SO2
GND
V
SS
Figure 18-4. Connecting Flashpro II/Flashpro III in UART Mode
Flashpro II/Flashpro III
µ
PD78F4046
VPP
VDD
V
PP
V
DD
RESET
SO
RESET
RxD or RxD2
TxD or TxD2
SI
GND
V
SS
18.3 Cautions
(1) Writing to the internal memory size select register (IMS) is valid only with the µPD78F4046. The IMS of the µPD784054
holds the value at RESET even if data is written to it.
(2) To develop a program for the µPD784054 using the µPD78F4046, set the value of the IMS to CDH. When the value
of the IMS is set to CDH, the peripheral RAM capacity of the µPD78F4046 is 768 bytes, but the peripheral RAM capacity
of the µPD784054 is 512 bytes. When using a mask ROM, therefore, exercise care that addresses 0FA00H to 0FAFFH
of the peripheral RAM area of the µPD78F4046 are not used (when the LOCATION 0H instruction is executed).
(3) Number of rewrites
Number of guaranteed rewrites: 10
Perform erasure and writing in area mode or chip mode. Block mode cannot be used to write only a specific block.
(4) Operating ambient temperature
Operating ambient temperature: TA = –10 to +70°C
However, the temperature during rewrite is TPRG = +10 to +40°C.
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CHAPTER 18 µPD78F4046
(5) Use of pre-writing
Pre-writing is required before erasure.
When Flashpro II (Ver. 2.50 or later) or Flashpro III (PG-FP3 Ver. 3.040 or later) is used, use of the pre-write function
can automatically be set by loading the parameter file.
(6) Use of ECC function
Write ECC data to the ECC area in the on-chip flash memory.
Convert the HEX file into a HEX file with ECC using the ECC generator included in the assembler package (PC version
Ver.1.20 or later). Then download this HEX file with ECC to Flashpro II or Flashpro III and execute writing.
[How to create ECC data]
<1> Prepare a HEX file created by the object converter in the assembler package.
<2> Convert the HEX file into a HEX file with ECC (program data + ECC data) using the ECC generator (eccgen.exe)
included in the assembler package.
Example When converting the file “file.hex” into the HEX file with ECC “file_ec.hex”
eccgen file.hex -ofile_ec.hex -a0ffffh, 1000h, 14000h, 14004h
(7) How to set and write using Flashpro II or Flashpro III
Perform pre-writing and write to ECC using Flashpro II or Flashpro III.
[How to write]
<1> Download the HEX file with ECC to Flashpro II or Flashpro III.
<2> Set CHIP mode and execute writing using the E.P.V button.
Do not use the Program command; otherwise ECC may not be written.
When Flashpro II Ver. 2.50 or earlier is used, the pre-write and ECC functions must be validated using the following
procedure before executing a write.
[How to set using Flashpro II Ver.2.50 or earlier]
<1> Connect the PC and the FL-PR2 and activate the control software (flashpro.exe)
<2> Press the CRTL, SHIFT, GRPH (ALT), and P keys at the same time
Pre-write setting
<3> Select “Pre-Write set”
<4> Click the OK button.
<5> Select “Setting”
<6> Select “Option”.
<7> Select “ECC code area” in the menu window.
<8> Input “14004” to the “ECC END ADDRESS” field.
ECC write setting
<9> Click the OK button.
<10> Click the TYPE button.
<11> Input “14004” to the “ECC ADDRESS” field
<12> Click the OK button.
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19.1 Legend
(1) Explanation of operand identifiers (1/2)
Identifier
Explanation
Note 1
r, r’
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7
Note 1
r1
r2
R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)
V, U, T, W
r3
Note 2
rp, rp’
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)
AX(RP0), BC(RP1), RP2, RP3
Note 2
rp1
rp2
VP(RP4), UP(RP5), DE(RP6), HL(RP7)
rg, rg’
sfr
VVP(RG4), UUP(RG5), TDE(RG6), WHL(RG7)
Special function register symbol
sfrp
Special function register symbol (register for which 16-bit operation is possible)
Note 2
post
AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5)/PSW, DE(RP6), HL(RP7)
Multiple descriptions are permissible. However, UP is only used with PUSH/POP instructions, and PSW
with PUSHU/POPU instructions.
mem
[TDE], [WHL], [TDE+], [WHL+], [TDE–], [WHL–], [VVP], [UUP]: Register indirect addressing
[TDE+byte], [WHL+byte], [SP+byte], [UUP+byte], [VVP+byte]: Based addressing
imm24 [A], imm24 [B], imm24 [DE], imm24 [HL]: Indexed addressing
[TDE+A], [TDE+B], [TDE+C], [WHL+A], [WHL+B], [WHL+C],
[VVP+DE], [VVP+HL]: Based indexed addressing
mem1
mem2
mem3
All mem except [WHL+] and [WHL–]
[TDE], [WHL]
[AX], [BC], [RP2], [RP3], [VVP], [UUP], [TDE], [WHL]
Notes 1. Setting the RSS bit to 1 enables R4 to R7 to be used as X, A, C and B, but this function should only be used
when using a 78K/III series program.
2. Setting the RSS bit to 1 enables RP2 and RP3 to be used as AX and BC, but this function should only be used
when using a 78K/III series program.
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(1) Explanation of operand identifiers (2/2)
Identifier
Explanation
Note
saddr, saddr’
saddr1
FD20H to FF1FH immediate data or label
FE00H to FEFFH immediate data or label
saddr2
FD20H to FDFFH, FF00H to FF1FH immediate data or label
FD20H to FF1EH immediate data or label (16-bit operation)
FE00H to FEFFH immediate data or label (16-bit operation)
FD20H to FDFFH, FF00H to FF1EH immediate data or label (16-bit operation)
FD20H to FEFDH immediate data or label (24-bit operation)
FE00H to FEFDH immediate data or label (24-bit operation)
FD20H to FDFFH immediate data or label (24-bit operation)
saddrp
saddrp1
saddrp2
saddrg
saddrg1
saddrg2
addr24
addr20
addr16
addr11
addr8
0H to FFFFFFH immediate data or label
0H to FFFFFH immediate data or label
0H to FFFFH immediate data or label
800H to FFFH immediate data or label
0FE00H to 0FEFFH* immediate data or label
40H to 7EH immediate data or label
addr5
imm24
word
byte
bit
24-bit immediate data or label
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data
n
locaddr
0H or 0FH
Note The addresses shown here apply when 0H is specified by the LOCATION instruction.
When 0FH is specified by the LOCATION instruction, F0000H should be added to the address values shown.
(2) Operand column symbols
Symbol
Explanation
+
–
#
!
Auto-increment
Auto-decrement
Immediate data
16-bit absolute address
24-bit/20-bit absolute address
8-bit relative address
16-bit relative address
Bit inversion
!!
$
$!
/
[
]
Indirect addressing
24-bit indirect addressing
[%]
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(3) Flag column symbols
Symbol
Explanation
(Blank)
No change
0
1
Cleared to 0
Set to 1
×
Set or cleared depending on result
P/V flag operates as parity flag
P/V flag operates as overflow flag
Previously saved value is restored
P
V
R
(4) Operation column symbols
Symbol
Explanation
jdisp8
Signed two’s complement data (8 bits) indicating relative address distance between start address of next
instruction and branch address
jdisp16
Signed two’s complement data (16 bits) indicating relative address distance between start address of
next instruction and branch address
PC bits 16 to 19
PCHW
PCLW
PC bits 0 to 15
(5) Number of bytes of instruction that includes mem in operands
Based
Indexed
Based Indexed
Addressing
mem Mode
Register Indirect Addressing
Addressing
Addressing
Note
Number of bytes
1
2
3
5
2
Note One-byte instruction only when [TDE], [WHL], [TDE+], [TDE-], [WHL+] or [WHL–] is written as mem in an MOV
instruction.
(6) Number of bytes of instruction that includes saddr, saddrp, r or rp in operands
For some instructions that include saddr, saddrp, r or rp in their operands, two “Bytes” entries are given, separated by
a slash (“/”). The entry that applies is shown in the table below.
Identifier
saddr
saddrp
r
Left-Hand “Bytes” Figure
Right-Hand “Bytes” Figure
saddr2
saddrp2
r1
saddr1
saddrp1
r2
rp
rp1
rp2
(7) Code of instructions that include mem in operands and string instructions
Operands TDE, WHL, VVP and UUP (24-bit registers) can also be written as DE, HL, VP and UP respectively. However,
they are still treated as TDE, WHL, VVP and UUP (24-bit registers) when written as DE, HL, VP and UP.
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19.2 List of Operations
(1) 8-bit data transfer instruction: MOV
Flags
Mnemonic
MOV
Operands
r, #byte
Bytes
Operation
S
Z
AC P/V CY
2/3
3/4
3
r ← byte
saddr, #byte
sfr, #byte
!addr16, #byte
!!addr24, #byte
r, r’
(saddr) ← byte
sfr ← byte
5
(saddr16) ← byte
(addr24) ← byte
r ← r’
6
2/3
1/2
2
A, r
A ← r
A, saddr2
r, saddr
A ← (saddr2)
r ← (saddr)
(saddr2) ← A
(saddr) ← r
A ← sfr
3
saddr2, A
saddr, r
2
3
A, sfr
2
r, sfr
3
r ← sfr
sfr, A
2
sfr ← A
sfr, r
3
sfr ← r
saddr, saddr’
r, !addr16
!addr16, r
r, !!addr24
!!addr24, r
A, [saddrp]
A, [%saddrg]
A, mem
4
(saddr) ← (saddr’)
r ← (addr16)
(addr16) ← r
r ← (addr24)
(addr24) ← r
A ← ((saddrp))
A ← ((saddrg))
A ← (mem)
((saddrp)) ← A
((saddrg)) ← A
(mem) ← A
PSWL ← byte
PSWH ← byte
PSWL ← A
PSWH ← A
A ← PSWL
A ← PSWH
r3 ← byte
4
4
5
5
2/3
3/4
1-5
2/3
3/4
1-5
3
[saddrp], A
[%saddrg], A
mem, A
PSWL, #byte
PSWH, #byte
PSWL, A
PSWH, A
A, PSWL
A, PSWH
r3, #byte
A, r3
×
×
×
×
×
×
×
×
×
×
3
2
2
2
2
3
2
A ← r3
r3, A
2
r3 ← A
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(2) 16-bit data transfer instruction: MOVW
Flags
Mnemonic
MOVW
Operands
rp, #word
Bytes
Operation
S
Z
AC P/V CY
3
4/5
4
rp ← word
saddrp, #word
sfrp, #word
!addr16, #word
!!addr24, #word
rp, rp’
(saddrp) ← word
sfrp ← word
(addr16) ← word
(addr24) ← word
rp ← rp’
6
7
2
AX, saddrp2
rp, saddrp
saddrp2, AX
saddrp, rp
AX, sfrp
2
AX ← (saddrp2)
rp ← (saddrp)
(saddrp2) ← AX
(saddrp) ← rp
AX ← sfrp
3
2
3
2
rp, sfrp
3
rp ← sfrp
sfrp, AX
2
sfrp ← AX
sfrp, rp
3
sfrp ← rp
saddrp, saddrp’
rp, !addr16
!addr16, rp
rp, !!addr24
!!addr24, rp
AX, [saddrp]
AX, [%saddrg]
AX, mem
4
(saddrp) ← (saddrp’)
rp ← (addr16)
(addr16) ← rp
rp ← (addr24)
(addr24) ← rp
AX ← ((saddrp))
AX ← ((saddrg))
AX ← (mem)
4
4
5
5
3/4
3/4
2-5
3/4
3/4
2-5
[saddrp], AX
[%saddrg], AX
mem, AX
((saddrp)) ← AX
((saddrg)) ← AX
(mem) ← AX
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(3) 24-bit data transfer instruction: MOVG
Flags
Mnemonic
MOVG
Operands
rg, #imm24
Bytes
Operation
S
Z
AC P/V CY
5
2
rg ← imm24
rg, rg’
rg ← rg’
rg, !!addr24
!!addr24, rg
rg, saddrg
5
rg ← (addr24)
(addr24) ← rg
rg ← (saddrg)
(saddrg) ← rg
WHL ← ((saddrg))
((saddrg)) ← WHL
WHL ← (mem1)
(mem1) ← WHL
5
3
saddrg, rg
3
WHL, [%saddrg]
[%saddrg], WHL
WHL, mem1
mem1, WHL
3/4
3/4
2-5
2-5
(4) 8-bit data exchange instruction: XCH
Flags
Mnemonic
XCH
Operands
Bytes
Operation
S
Z
AC P/V CY
r, r’
A, r
2/3
1/2
2
r ↔ r’
A ↔ r
A, saddr2
r, saddr
A ↔ (saddr2)
r ↔ (saddr)
r ↔ sfr
3
r, sfr
3
saddr, saddr’
r, !addr16
r, !!addr24
A, [saddrp]
A, [%saddrg]
A, mem
4
(saddr) ↔ (saddr’)
r ↔ (addr16)
r ↔ (addr24)
A ↔ ((saddrp))
A ↔ ((saddrg))
A ↔ (mem)
4
5
2/3
3/4
2-5
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(5) 16-bit data exchange instruction: XCHW
Flags
Mnemonic
XCHW
Operands
Bytes
Operation
S
Z
AC P/V CY
rp, rp’
2
2
rp ↔ rp’
AX, saddrp2
rp, saddrp
AX ↔ (saddrp2)
rp ↔ (saddrp)
rp ↔ sfrp
3
rp, sfrp
3
AX, [saddrp]
AX, [%saddrg]
AX, !addr16
AX, !!addr24
saddrp, saddrp’
AX, mem
3/4
3/4
4
AX ↔ ((saddrp))
AX ↔ ((saddrg))
AX ↔ (addr16)
AX ↔ (addr24)
5
4
(saddrp) ↔ (saddrp’)
AX ↔ (mem)
2-5
(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, CMP, AND, OR, XOR
Flags
Mnemonic
ADD
Operands
A, #byte
Bytes
Operation
A, CY ← A + byte
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
r, CY ← r + byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr), CY ← (saddr) + byte
sfr, CY ← sfr + byte
2/3
2
r, CY ← r + r’
A, saddr2
r, saddr
A, CY ← A + (saddr2)
r, CY ← r + (saddr)
3
saddr, r
3
(saddr), CY ← (saddr) + r
r, CY ← r + sfr
r, sfr
3
sfr, r
3
sfr, CY ← sfr + r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) + (saddr’)
A, CY ← A + ((saddrp))
A, CY ← A + ((saddrg))
((saddrp)), CY ← ((saddrp)) + A
((saddrg)), CY ← ((saddrg)) + A
A, CY ← A + (addr16)
A, CY ← A + (addr24)
(addr16), CY ← (addr16) + A
(addr24), CY ← (addr24) + A
A, CY ← A + (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) + A
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Flags
Mnemonic
ADDC
Operands
A, #byte
Bytes
Operation
A, CY ← A + byte + CY
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
r, CY ← r + byte + CY
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr), CY ← (saddr) + byte + CY
sfr, CY ← sfr + byte + CY
2/3
2
r, CY ← r + r’ + CY
A, saddr2
r, saddr
A, CY ← A + (saddr2) + CY
r, CY ← r + (saddr) + CY
3
saddr, r
3
(saddr), CY ← (saddr) + r + CY
r, CY ← r + sfr + CY
r, sfr
3
sfr, r
3
sfr, CY ← sfr + r + CY
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) + (saddr’) + CY
A, CY ← A + ((saddrp)) + CY
A, CY ← A + ((saddrg)) + CY
((saddrp)), CY ← ((saddrp)) + A + CY
((saddrg)), CY ← ((saddrg)) + A + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (addr24) + CY
(addr16), CY ← (addr16) + A + CY
(addr24), CY ← (addr24) + A + CY
A, CY ← A + (mem) + CY
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) + A + CY
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CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
SUB
Operands
A, #byte
Bytes
Operation
A, CY ← A – byte
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
r, CY ← r – byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr), CY ← (saddr) – byte
sfr, CY ← sfr – byte
2/3
2
r, CY ← r – r’
A, saddr2
r, saddr
A, CY ← A – (saddr2)
r, CY ← r – (saddr)
3
saddr, r
3
(saddr), CY ← (saddr) – r
r, CY ← r – sfr
r, sfr
3
sfr, r
3
sfr, CY ← sfr – r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) – (saddr’)
A, CY ← A – ((saddrp))
A, CY ← A – ((saddrg))
((saddrp)), CY ← ((saddrp)) – A
((saddrg)), CY ← ((saddrg)) – A
A, CY ← A – (addr16)
A, CY ← A – (addr24)
(addr16), CY ← (addr16) – A
(addr24), CY ← (addr24) – A
A, CY ← A – (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) – A
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
SUBC
Operands
A, #byte
Bytes
Operation
A, CY ← A – byte – CY
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
r, CY ← r – byte – CY
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr), CY ← (saddr) – byte – CY
sfr, CY ← sfr – byte – CY
2/3
2
r, CY ← r – r’ – CY
A, saddr2
r, saddr
A, CY ← A – (saddr2) – CY
r, CY ← r – (saddr) – CY
3
saddr, r
3
(saddr), CY ← (saddr) – r – CY
r, CY ← r – sfr – CY
r, sfr
3
sfr, r
3
sfr, CY ← sfr – r – CY
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr), CY ← (saddr) – (saddr’) – CY
A, CY ← A – ((saddrp)) – CY
A, CY ← A – ((saddrg)) – CY
((saddrp)), CY ← ((saddrp)) – A – CY
((saddrg)), CY ← ((saddrg)) – A – CY
A, CY ← A – (addr16) – CY
A, CY ← A – (addr24) – CY
(addr16), CY ← (addr16) – A – CY
(addr24), CY ← (addr24) – A – CY
A, CY ← A – (mem) – CY
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem), CY ← (mem) – A – CY
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
CMP
Operands
A, #byte
Bytes
Operation
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
A – byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, #byte
r – byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr) – byte
sfr – byte
2/3
2
r – r’
A, saddr2
r, saddr
A – (saddr2)
r – (saddr)
(saddr) – r
r – sfr
3
saddr, r
3
r, sfr
3
sfr, r
3
sfr – r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) – (saddr’)
A – ((saddrp))
A – ((saddrg))
((saddrp)) – A
((saddrg)) – A
A – (addr16)
A – (addr24)
(addr16) – A
(addr24) – A
A – (mem)
(mem) – A
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
AND
Operands
A, #byte
Bytes
Operation
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
A ← A ∧ byte
r ← r ∧ byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr) ← (saddr) ∧ byte
sfr ← sfr ∧ byte
2/3
2
r ← r ∧ r’
A, saddr2
r, saddr
A ← A ∧ (saddr2)
r ← r ∧ (saddr)
(saddr) ← (saddr) ∧ r
r ← r ∧ sfr
3
saddr, r
3
r, sfr
3
sfr, r
3
sfr ← sfr ∧ r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr) ∧ (saddr’)
A ← A ∧ ((saddrp))
A ← A ∧ ((saddrg))
((saddrp)) ← ((saddrp)) ∧ A
((saddrg)) ← ((saddrg)) ∧ A
A ← A ∧ (addr16)
A ← A ∧ (addr24)
(addr16) ← (addr16) ∧ A
(addr24) ← (addr24) ∧ A
A ← A ∧ (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem) ← (mem) ∧ A
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
OR
Operands
A, #byte
Bytes
Operation
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
A ← A ∨ byte
r ← r ∨ byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr) ← (saddr) ∨ byte
sfr ← sfr ∨ byte
2/3
2
r ← r ∨ r’
A, saddr2
r, saddr
A ← A ∨ (saddr2)
r ← r ∨ (saddr)
(saddr) ← (saddr) ∨ r
r ← r ∨ sfr
3
saddr, r
3
r, sfr
3
sfr, r
3
sfr ← sfr ∨ r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr) ∨ (saddr’)
A ← A ∨ ((saddrp))
A ← A ∨ ((saddrg))
((saddrp)) ← ((saddrp)) ∨ A
((saddrg)) ← ((saddrg)) ∨ A
A ← A ∨ (addr16)
A ← A ∨ (addr24)
(addr16) ← (addr16) ∨ A
(addr24) ← (addr24) ∨ A
A ← A ∨ (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem) ← (mem) ∨ A
401
User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
XOR
Operands
A, #byte
Bytes
Operation
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
2
3
A ← A ∨ byte
r ← r ∨ byte
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
r, #byte
saddr, #byte
sfr, #byte
r, r’
3/4
4
(saddr) ← (saddr) ∨ byte
sfr ← sfr ∨ byte
2/3
2
r ← r ∨ r’
A, saddr2
r, saddr
A ← A ∨ (saddr2)
r ← r ∨ (saddr)
(saddr) ← (saddr) ∨ r
r ← r ∨ sfr
3
saddr, r
3
r, sfr
3
sfr, r
3
sfr ← sfr ∨ r
saddr, saddr’
A, [saddrp]
A, [%saddrg]
[saddrp], A
[%saddrg], A
A, !addr16
A, !!addr24
!addr16, A
!!addr24, A
A, mem
4
(saddr) ← (saddr) ∨ (saddr’)
A ← A ∨ ((saddrp))
A ← A ∨ ((saddrg))
((saddrp)) ← ((saddrp)) ∨ A
((saddrg)) ← ((saddrg)) ∨ A
A ← A ∨ (addr16)
A ← A ∨ (addr24)
(addr16) ← (addr16) ∨ A
(addr24) ← (addr24) ∨ A
A ← A ∨ (mem)
3/4
3/4
3/4
3/4
4
5
4
5
2-5
2-5
mem, A
(mem) ← (mem) ∨ A
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
(7) 16-bit operation instructions: ADDW, SUBW, CMPW
Flags
Mnemonic
ADDW
Operands
AX, #word
Bytes
Operation
AX, CY ← AX + word
S
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC P/V CY
3
4
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
rp, #word
rp, rp’
rp, CY ← rp + word
rp, CY ← rp + rp’
2
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX, CY ← AX + (saddrp2)
rp, CY ← rp + (saddrp)
(saddrp), CY ← (saddrp) + rp
rp, CY ← rp + sfrp
sfrp, CY ← sfrp + rp
(saddrp), CY ← (saddrp) + word
sfrp, CY ← sfrp + word
(saddrp), CY ← (saddrp) + (saddrp’)
AX, CY ← AX – word
rp, CY ← rp – word
rp, CY ← rp – rp’
3
3
3
sfrp, rp
3
saddrp, #word
sfrp, #word
saddrp, saddrp’
AX, #word
rp, #word
rp, rp’
4/5
5
4
SUBW
3
4
2
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX, CY ← AX – (saddrp2)
rp, CY ← rp – (saddrp)
(saddrp), CY ← (saddrp) – rp
rp, CY ← rp – sfrp
sfrp, CY ← sfrp – rp
(saddrp), CY ← (saddrp) – word
sfrp, CY ← sfrp – word
(saddrp), CY ← (saddrp) – (saddrp’)
AX – word
3
3
3
sfrp, rp
3
saddrp, #word
sfrp, #word
saddrp, saddrp’
AX, #word
rp, #word
rp, rp’
4/5
5
4
CMPW
3
4
rp – word
2
rp – rp’
AX, saddrp2
rp, saddrp
saddrp, rp
rp, sfrp
2
AX – (saddrp2)
3
rp – (saddrp)
3
(saddrp) – rp
3
rp – sfrp
sfrp, rp
3
sfrp – rp
saddrp, #word
sfrp, #word
saddrp, saddrp’
4/5
5
(saddrp) – word
sfrp – word
4
(saddrp) – (saddrp’)
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
(8) 24-bit operation instructions: ADDG, SUBG
Flags
Mnemonic
ADDG
Operands
Bytes
Operation
S
×
×
×
×
×
×
Z
×
×
×
×
×
×
AC P/V CY
rg, rg’
2
5
3
2
5
3
rg, CY ← rg + rg’
×
×
×
×
×
×
V
V
V
V
V
V
×
×
×
×
×
×
rg, # imm24
WHL, saddrg
rg, rg’
rg, CY ← rg + # imm24
WHL, CY ← WHL + (saddrg)
rg, CY ← rg – rg’
SUBG
rg, # imm24
WHL, saddrg
rg, CY ← rg – imm24
WHL, CY ← WHL – (saddrg)
(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX
Flags
Mnemonic
MULU
Operands
Bytes
Operation
S
Z
AC P/V CY
r
2/3
2
AX ← A × r
MULUW
MULW
DIVUW
DIVUX
rp
rp
r
AX (upper half), rp (lower half) ← AX × rp
AX (upper half), rp (lower half) ← AX × rp
2
Note 1
2/3
2
AX (quotient), r (remainder) ← AX ÷ r
rp
AXDE (quotient), rp (remainder) ← AXDE ÷ rpNote 2
Notes 1. When r = 0, r ← X, AX ← FFFFH
2. When rp = 0, pr ← DE, AXDE ← FFFFFFFFH
(10) Special operation instructions: MACW, MACSW, SACW
Flags
Mnemonic
MACW
Operands
Bytes
3
Operation
S
Z
AC P/V CY
byte
byte
AXDE ← (B) × (C) + AXDE, B ← B + 2,
C ← C + 2, byte ← byte – 1
End if(byte = 0 or P/V = 1)
×
×
×
×
V
×
MACSW
3
AXDE ← (B) × (C) + AXDE, B ← B + 2,
C ← C + 2, byte ← byte – 1
if byte = 0 then End
×
×
×
×
V
×
if P/V = 1 then
if overflow AXDE ← 7FFFFFFFH, End
if underflow AXDE ← 80000000H, End
SACW
[TDE + ], [WHL + ]
4
AX ← |(TDE) – (WHL)| + AX,
×
V
×
TDE ← TDE + 2, WHL ← WHL + 2
C ← C – 1 End if(C = 0 or CY = 1)
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User’s Manual U11719EJ3V1UD
CHAPTER 19 INSTRUCTION OPERATIONS
(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG
Flags
Mnemonic
INC
Operands
Bytes
Operation
S
×
×
×
×
Z
×
×
×
×
AC P/V CY
r
1/2
2/3
1/2
2/3
2/1
3/4
2/1
3/4
2
r ← r + 1
×
×
×
×
V
V
V
V
saddr
r
(saddr) ← (saddr) + 1
r ← r –1
DEC
saddr
rp
(saddr) ← (saddr) – 1
rp ← rp + 1
INCW
DECW
saddrp
rp
(saddrp) ← (saddrp) + 1
rp ← rp – 1
saddrp
rg
(saddrp) ← (saddrp) – 1
rg ← rg + 1
INCG
DECG
rg
2
rg ← rg – 1
(12) Adjustment instructions: ADJBA, ADJBS, CVTBW
Flags
Mnemonic
ADJBA
Operands
Bytes
Operation
S
×
×
Z
×
×
AC P/V CY
2
2
1
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
×
×
P
P
×
×
ADJBS
CVTBW
X ← A, A ← 00H if A7 = 0
X ← A, A ← FFH if A7 = 1
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CHAPTER 19 INSTRUCTION OPERATIONS
(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4
Flags
Mnemonic
ROR
Operands
Bytes
Operation
S
Z
AC P/V CY
r, n
r, n
r, n
r, n
r, n
r, n
rp, n
2/3
2/3
2/3
2/3
2/3
2/3
2
(CY, r7 ← r0, rm – 1 ← rm) × n times n = 0 – 7
(CY, r0 ← r7, rm + 1 ← rm) × n times n = 0 – 7
(CY← r0, r7 ← CY, rm – 1 ← rm) × n times n = 0 – 7
(CY← r7, r0 ← CY, rm + 1 ← rm) × n times n = 0 – 7
(CY← r0, r7 ← 0, rm – 1 ← rm) × n times n = 0 – 7
(CY← r7, r0 ← 0, rm + 1 ← rm) × n times n = 0 – 7
P
P
P
P
P
P
P
×
×
×
×
×
×
×
ROL
RORC
ROLC
SHR
×
×
×
×
×
×
0
0
0
SHL
SHRW
(CY← rp0, rp15 ← 0, rpm – 1 ← rpm) × n times
n = 0 – 7
SHLW
ROR4
ROL4
rp, n
2
2
2
(CY← rp15, rp0 ← 0, rpm + 1 ← rpm) × n times
n = 0 – 7
×
×
0
P
×
mem3
mem3
A3 – 0 ← (mem3)3 – 0, (mem3)7 – 4 ← A3 – 0,
(mem3)3 – 0 ← (mem3)7 – 4
A3 – 0 ← (mem3)7 – 4, (mem3)3 – 0 ← A3 – 0,
(mem3)7 – 4 ← (mem3)3 – 0
(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1
Flags
Mnemonic
MOV1
Operands
Bytes
Operation
S
Z
AC P/V CY
CY, saddr. bit
CY, sfr. bit
3/4
3
CY ← (saddr. bit)
CY ← sfr. bit
×
×
×
×
×
×
×
×
×
CY, X. bit
2
CY ← X. bit
CY, A. bit
2
CY ← A. bit
CY, PSWL. bit
CY, PSWH. bit
CY, !addr16. bit
CY, !!addr24. bit
CY, mem2. bit
saddr. bit, CY
sfr. bit, CY
2
CY ← PSWL. bit
CY ← PSWH. bit
CY ← !addr16.bit
2
5
2
CY ← !!addr24. bit
CY ← mem2. bit
(saddr. bit) ← CY
sfr. bit ← CY
2
3/4
3
X. bit, CY
2
X.bit ← CY
A. bit, CY
2
A. bit ← CY
PSWL. bit, CY
PSWH. bit, CY
!addr16. bit, CY
!!addr24.bit, CY
mem2. bit, CY
2
PSWL. bit ← CY
PSWH. bit ← CY
!addr16.bit ← CY
!!addr24.bit ← CY
mem2. bit ← CY
×
×
×
×
×
2
5
6
2
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CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
AND1
Operands
Bytes
Operation
CY ← CY ∧ (saddr. bit)
CY ← CY ∧ (saddr. bit)
CY ← CY ∧ sfr. bit
CY ← CY ∧ sfr. bit
CY ← CY ∧ X. bit
CY ← CY ∧ X. bit
CY ← CY ∧ A. bit
CY ← CY ∧ A. bit
CY ← CY ∧ PSWL. bit
CY ← CY ∧ PSWL. bit
CY ← CY ∧ PSWH. bit
CY ← CY ∧ PSWH. bit
CY ← CY ∧ !addr16. bit
CY ← CY ∧ !addr16. bit
CY ← CY ∧ !!addr24. bit
CY ← CY ∧ !!addr24. bit
CY ← CY ∧ mem2. bit
CY ← CY ∧ mem2. bit
CY ← CY ∨ (saddr. bit)
CY ← CY ∨ (saddr. bit)
CY ← CY ∨ sfr. bit
S
Z
AC P/V CY
CY, saddr. bit
CY, /saddr. bit
CY, sfr. bit
3/4
3/4
3
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CY, /sfr. bit
3
CY, X. bit
2
CY, /X. bit
2
CY, A. bit
2
CY, /A. bit
2
CY, PSWL. bit
CY, /PSWL. bit
CY, PSWH. bit
CY, /PSWH. bit
CY, !addr16. bit
CY, /!addr16. bit
CY, !!addr24. bit
CY, /!!addr24. bit
CY, mem2. bit
CY, /mem2. bit
CY, saddr. bit
CY, /saddr. bit
CY, sfr. bit
2
2
2
2
5
5
2
6
2
2
OR1
3/4
3/4
3
CY, /sfr. bit
3
CY ← CY ∨ sfr. bit
CY ← CY ∨ X. bit
CY ← CY ∨ X. bit
CY ← CY ∨ A. bit
CY, X. bit
2
CY, /X. bit
2
CY, A. bit
2
CY, /A. bit
2
CY ← CY ∨ A. bit
CY, PSWL. bit
CY, /PSWL. bit
CY, PSWH. bit
CY, /PSWH. bit
CY, !addr16. bit
CY, /!addr16. bit
CY, !!addr24. bit
CY, /!!addr24. bit
CY, mem2. bit
CY, /mem2. bit
2
CY ← CY ∨ PSWL. bit
CY ← CY ∨ PSWL. bit
CY ← CY ∨ PSWH. bit
CY ← CY ∨ PSWH. bit
CY ← CY ∨ !addr16. bit
CY ← CY ∨ !addr16. bit
CY ← CY ∨ !!addr24. bit
CY ← CY ∨ !!addr24. bit
CY ← CY ∨ mem2. bit
CY ← CY ∨ mem2. bit
2
2
2
5
5
2
6
2
2
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Flags
Mnemonic
XOR1
Operands
Bytes
Operation
CY ← CY ∨ (saddr. bit)
S
Z
AC P/V CY
CY, saddr. bit
CY, sfr. bit
CY, X. bit
CY, A. bit
CY, PSWL. bit
CY, PSWH. bit
CY, !addr16. bit
CY, !!addr24. bit
CY, mem2. bit
saddr. bit
sfr. bit
3/4
3
×
×
×
×
×
×
×
×
×
CY ← CY ∨ sfr. bit
CY ← CY ∨ X. bit
CY ← CY ∨ A. bit
CY ← CY ∨ PSWL. bit
CY ← CY ∨ PSWH. bit
CY ← CY ∨ !addr16. bit
CY ← CY ∨ !!addr24. bit
CY ← CY ∨ mem2. bit
(saddr. bit) ← (saddr. bit)
sfr. bit ← sfr. bit
X. bit ← X. bit
2
2
2
2
5
2
2
NOT1
SET1
CLR1
3/4
3
X. bit
2
A. bit
2
A. bit ← A. bit
PSWL. bit
PSWH. bit
!addr16. bit
!!addr24. bit
mem2. bit
CY
2
PSWL. bit ← PSWL. bit
PSWH. bit ← PSWH. bit
!addr16. bit ← !addr16. bit
!!addr24. bit ← !!addr24. bit
mem2. bit ← mem2. bit
CY ← CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
×
0
2
5
2
2
1
saddr. bit
sfr. bit
2/3
3
(saddr. bit) ← 1
sfr. bit ← 1
X. bit
2
X. bit ← 1
A. bit
2
A. bit ← 1
PSWL. bit
PSWH. bit
!addr16. bit
!!addr24. bit
mem2. bit
CY
2
PSWL. bit ← 1
2
PSWH. bit ← 1
5
!addr16. bit ← 1
!!addr24. bit ← 1
mem2. bit ← 1
2
2
1
CY ← 1
saddr. bit
sfr. bit
2/3
3
(saddr. bit) ← 0
sfr. bit ← 0
X. bit
2
X. bit ← 0
A. bit
2
A. bit ← 0
PSWL. bit
PSWH. bit
!addr16. bit
!!addr24. bit
mem2. bit
CY
2
PSWL. bit ← 0
2
PSWH. bit ← 0
5
!addr16. bit ← 0
!!addr24. bit ← 0
mem2. bit ← 0
2
2
1
CY ← 0
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(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG
Flags
Mnemonic
PUSH
Operands
Bytes
Operation
S
Z
AC P/V CY
PSW
sfrp
sfr
1
3
3
2
2
2
1
3
3
2
2
2
5
2
2
4
4
2
2
(SP – 2) ← PSW, SP ← SP – 2
(SP – 2) ← sfrp, SP ← SP – 2
(SP – 1) ← sfr, SP ← SP – 1
post
rg
{(SP – 2) ← post, SP ← SP – 2} × m timesNote
(SP – 3) ← rg, SP ← SP – 3
Note
PUSHU
POP
post
PSW
sfrp
sfr
{(UUP – 2) ← post, UUP ← UUP – 2} × m times
PSW ← (SP), SP ← SP + 2
sfrp ← (SP), SP ← SP + 2
sfr ← (SP), SP ← SP + 1
R
R
R
R
R
Note
post
rg
{post ← (SP), SP ← SP + 2} × m times
rg ← (SP), SP ← SP + 3
Note
POPU
MOVG
post
{post ← (UUP), UUP ← UUP + 2} × m times
SP, # imm24
SP, WHL
WHL, SP
SP, #word
SP, #word
SP
SP ← imm24
SP ← WHL
WHL ← SP
ADDWG
SUBWG
INCG
SP ← SP + word
SP ← SP – word
SP ← SP + 1
SP ← SP – 1
DECG
SP
Note m = number of registers specified by “post”
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(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB
Flags
Mnemonic
CALL
Operands
!addr16
Bytes
3
Operation
S
Z
AC P/V CY
(SP – 3) ← (PC + 3), SP ← SP – 3,
PCHW ← 0, PCLW ← addr16
!!addr20
rp
4
2
2
2
2
3
2
1
1
(SP – 3) ← (PC + 4), SP ← SP – 3,
PC ← addr20
(SP – 3) ← (PC + 2), SP ← SP – 3,
PCHW ← 0, PCLW ← rp
rg
(SP – 3) ← (PC + 2), SP ← SP – 3,
PC ← rg
[rp]
(SP – 3) ← (PC + 2), SP ← SP – 3,
PCHW ← 0, PCLW ← (rp)
[rg]
(SP – 3) ← (PC + 2), SP ← SP – 3,
PC ← (rg)
$!addr20
!addr11
[addr5]
(SP – 3) ← (PC + 3), SP ← SP – 3,
PC ← PC + 3 + jdisp16
CALLF
CALLT
BRK
(SP – 3) ← (PC + 2), SP ← SP – 3,
PC19 – 12 ← 0, PC11 ← 1, PC10 – 0 ← addr11
(SP – 3) ← (PC + 1), SP ← SP – 3,
PCHW ← 0, PCLW ← (addr5)
(SP – 2) ← PSW, (SP – 1)0 – 3 ← (PC + 1)HW,
(SP – 4) ← (PC + 1)LW,
SP ← SP – 4
PCHW ← 0, PCLW ← (003EH)
BRKCS
RBn
2
PCLW ← RP2, RP3 ← PSW, RBS2 – 0 ← n,
RSS ← 0, IE ← 0, RP38 – 11 ← PCHW, PCHW ← 0
RET
1
1
PC ← (SP), SP ← SP + 3
RET1
PCLW ← (SP), PCHW ← (SP + 3)0 – 3,
PSW ← (SP + 2), SP ← SP + 4
Clears to 0 flag with highest priority of flags
of ISPR that are set (1)
R
R
R
R
R
RETB
1
3
PCLW ← (SP), PCHW ← (SP + 3)0 – 3,
PSW ← (SP + 2), SP ← SP + 4
R
R
R
R
R
R
R
R
R
R
RETCS
!addr16
!addr16
PSW ← RP3, PCLW ← RP2, RP2 ← addr16,
PCHW ← RP38 – 11
Clears to 0 flag with highest priority of flags
of ISPR that are set (1)
RETCSB
4
PSW ← RP3, PCLW ← RP2, RP2 ← addr16,
PCHW ← RP38 – 11
R
R
R
R
R
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(17) Unconditional branch instruction: BR
Flags
Mnemonic
BR
Operands
!addr16
Bytes
Operation
S
Z
AC P/V CY
3
4
2
2
2
2
2
3
PCHW ← 0, PCLW ← addr16
PC ← addr20
!!addr20
rp
PCHW ← 0, PCLW ← rp
PC ← rg
rg
[rp]
PCHW ← 0, PCLW ← (rp)
PC ← (rg)
[rg]
$addr20
$!addr20
PC ← PC + 2 + jdisp8
PC ← PC + 3 + jdisp16
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CHAPTER 19 INSTRUCTION OPERATIONS
(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT,
BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Flags
Mnemonic
BNZ
Operands
$addr20
Bytes
2
Operation
S
Z
AC P/V CY
PC ← PC + 2 + jdisp8 if Z = 0
BNE
BZ
$addr20
$addr20
$addr20
$addr20
$addr20
2
2
2
2
2
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if P/V = 0
PC ← PC + 2 + jdisp8 if P/V = 1
BE
BNC
BNL
BC
BL
BNV
BPO
BV
BPE
BP
$addr20
2
2
PC ← PC + 2 + jdisp8 if S = 0
BN
$addr20
PC ← PC + 2 + jdisp8 if S = 1
BLT
BGE
BLE
BGT
BNH
BH
$addr20
3
PC ← PC + 3 + jdisp8 if P/V ∨ S = 1
PC ← PC + 3 + jdisp8 if P/V ∨ S = 0
PC ← PC + 3 + jdisp8 if (P/V ∨ S) ∨ Z = 1
PC ← PC + 3 + jdisp8 if (P/V ∨ S) ∨ Z = 0
PC ← PC + 3 + jdisp8 if Z ∨ CY = 1
$addr20
3
$addr20
3
$addr20
3
$addr20
3
$addr20
3
PC ← PC + 3 + jdisp8 if Z ∨ CY = 0
Note
BF
saddr. bit, $addr20
sfr. bit, $addr20
X. bit, $addr20
A. bit, $addr20
PSWL. bit, $addr20
PSWH. bit, $addr20
!addr16. bit, $addr20
!!addr24. bit, $addr20
mem2. bit, $addr20
4/5
4
PC ← PC + 4
+ jdisp8 if (saddr. bit) = 0
PC ← PC + 4 + jdisp8 if sfr. bit = 0
PC ← PC + 3 + jdisp8 if X. bit = 0
3
3
PC ← PC + 3 + jdisp8 if A. bit = 0
3
PC ← PC + 3 + jdisp8 if PSWL. bit = 0
PC ← PC + 3 + jdisp8 if PSWH. bit = 0
PC ← PC + 3 + jdisp8 if !addr16. bit = 0
PC ← PC + 3 + jdisp8 if !!addr24. bit = 0
PC ← PC + 3 + jdisp8 if mem2. bit = 0
3
6
3
3
Note When the number of bytes is 4. When 5, the operation is: PC ← PC + 5 + jdisp8.
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Flags
Mnemonic
Operands
Bytes
Operation
S
Z
AC P/V CY
Note 1
BT
saddr. bit, $addr20
sfr. bit, $addr20
3/4
4
PC ← PC + 3
+ jdisp8 if (saddr. bit) = 1
PC ← PC + 4 + jdisp8 if sfr. bit = 1
PC ← PC + 3 + jdisp8 if X. bit = 1
PC ← PC + 3 + jdisp8 if A. bit = 1
PC ← PC + 3 + jdisp8 if PSWL. bit = 1
PC ← PC + 3 + jdisp8 if PSWH. bit = 1
PC ← PC + 3 + jdisp8 if !addr16. bit = 1
PC ← PC + 3 + jdisp8 if !!addr24. bit = 1
X. bit, $addr20
3
A. bit, $addr20
3
PSWL. bit, $addr20
PSWH. bit, $addr20
!addr16. bit, $addr20
!!addr24. bit, $addr20
mem2. bit, $addr20
saddr. bit, $addr20
3
3
6
3
3
PC ← PC + 3 + jdisp8 if mem2. bit = 1
Note 2
BTCLR
4/5
{PC ← PC + 4
+ jdisp8, (saddr. bit) ← 0}
if (saddr. bit) = 1
sfr. bit, $addr20
X. bit, $addr20
A. bit, $addr20
PSWL. bit, $addr20
4
3
3
3
{PC ← PC + 4 + jdisp8, sfr. bit ← 0} if sfr. bit = 1
{PC ← PC + 3 + jdisp8, X. bit ← 0} if X. bit = 1
{PC ← PC + 3 + jdisp8, A. bit ← 0} if A. bit = 1
{PC ← PC + 3 + jdisp8, PSWL. bit ← 0}
×
×
×
×
×
if PSWL. bit = 1
PSWH. bit, $addr20
!addr16. bit, $addr20
!!addr24. bit, $addr20
mem2. bit, $addr20
3
6
3
3
{PC ← PC + 3 + jdisp8, PSWH. bit ← 0}
if PSWH. bit = 1
{PC ← PC + 3 + jdisp8, !addr16. bit ← 0}
if !addr16. bit = 1
{PC ← PC + 3 + jdisp8, !!addr24. bit ← 0}
if !!addr24. bit = 1
{PC ← PC + 3 + jdisp8, mem2. bit ← 0}
if mem2. bit = 1
Notes 1. When the number of bytes is 3. When 4, the operation is: PC ← PC + 4 + jdisp8.
2. When the number of bytes is 4. When 5, the operation is: PC ← PC + 5 + jdisp8.
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Flags
Mnemonic
BFSET
Operands
Bytes
4/5
Operation
S
Z
AC P/V CY
Note 2
saddr. bit, $addr20
{PC ← PC + 4
if (saddr. bit) = 0
+ jdisp8, (saddr. bit) ← 1}
sfr. bit, $addr20
X. bit, $addr20
A. bit, $addr20
PSWL. bit, $addr20
4
3
3
3
{PC ← PC + 4 + jdisp8, sfr. bit ← 1} if sfr. bit = 0
{PC ← PC + 3 + jdisp8, X. bit ← 1} if X. bit = 0
{PC ← PC + 3 + jdisp8, A. bit ← 1} if A. bit = 0
{PC ← PC + 3 + jdisp8, PSWL. bit ← 1}
×
×
×
×
×
if PSWL. bit = 0
PSWH. bit, $addr20
!addr16. bit, $addr20
!!addr24. bit, $addr20
mem2. bit, $addr20
3
6
3
3
{PC ← PC + 3 + jdisp8, PSWH. bit ← 1}
if PSWH. bit = 0
{PC ← PC + 3 + jdisp8, !addr16. bit ← 1}
if !addr16. bit = 0
{PC ← PC + 3 + jdisp8, !!addr24. bit ← 1}
if !!addr24. bit = 0
{PC ← PC + 3 + jdisp8, mem2. bit ← 1}
if mem2. bit = 0
DBNZ
B, $addr20
2
2
B ← B – 1, PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C – 1, PC ← PC + 2 + jdisp8 if C ≠ 0
C, $addr20
$addr, $addr20
3/4
(saddr) ← (saddr) – 1,
Note 1
PC ← PC + 3
= jdisp8 if (saddr) ≠ 0
Notes 1. When the number of bytes is 3. When 4, the operation is: PC ← PC + 4 + jdisp8.
2. When the number of bytes is 4. When 5, the operation is: PC ← PC + 5 + jdisp8.
(19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI
Flags
Mnemonic
MOV
Operands
STBC, #byte
Bytes
Operation
S
Z
AC P/V CY
4
4
4
STBC ← byte
WDM ← byte
WDM, #byte
locaddr
LOCATION
SEL
SFR, internal data area location address
upper word specification
RBn
2
2
2
1
1
1
RSS ← 0, RBS2 – 0 ← n
RSS ← 1, RBS2 – 0 ← n
RSS ← RSS
RBn, ALT
SWRS
NOP
EI
No Operaton
IE ← 1 (Enable interrupt)
IE ← 0 (Disable interrupt)
DI
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CHAPTER 19 INSTRUCTION OPERATIONS
(20) Special instructions: CHKL, CHKLA
Flags
Mnemonic
Operands
Bytes
Operation
S
×
×
Z
×
×
AC P/V CY
CHKL
CHKLA
sfr
sfr
3
3
(Pin level) ∨ (output latch)
A ← (pin level) ∨ (output latch)
P
P
(21) String instructions: MOVTBLW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC,
CMPBKE, CMPBKNE, CMPBKC, CMPBKNC
Flags
Mnemonic
MOVTBLW
Operands
!addr8, byte
Bytes
4
Operation
S
Z
AC P/V CY
(addr8 + 2) ← (addr8), byte ← byte – 1,
addr8 ← addr8 – 2 End if byte = 0
MOVW
XCHM
[TDE + ], A
2
2
2
2
2
(TDE) ← A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ← A, TDE ← TDE – 1, C ← C – 1 End if C = 0
(TDE) ↔ A, TDE ← TDE + 1, C ← C – 1 End if C = 0
(TDE) ↔ A, TDE ← TDE – 1, C ← C – 1 End if C = 0
[TDE – ], A
[TDE + ], A
[TDE – ], A
MOVBK
[TDE + ], [WHL +]
(TDE) ← (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0
[TDE – ], [WHL –]
[TDE + ], [WHL +]
[TDE – ], [WHL –]
2
2
2
(TDE) ← (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0
XCHBK
(TDE) ↔ (WHL), TDE ← TDE +1,
WHL ← WHL + 1, C ← C – 1 End if C = 0
(TDE) ↔ (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0
CMPME
[TDE + ], A
[TDE – ], A
[TDE + ], A
[TDE – ], A
[TDE + ], A
[TDE – ], A
[TDE + ], A
[TDE – ], A
[TDE + ], [WHL +]
2
2
2
2
2
2
2
2
2
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 0
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or Z = 1
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – A, TDE ← TDE + 1, C ← C – 1 End if C = 0 or CY = 1
(TDE) – A, TDE ← TDE – 1, C ← C – 1 End if C = 0 or CY = 1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
V
V
V
V
V
V
V
V
V
×
×
×
×
×
×
×
×
×
CMPMNE
CMPMC
CMPMNC
CMPBKE
(TDE) ← (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or Z = 0
[TDE – ], [WHL –]
2
(TDE) ← (WHL), TDE ← TDE – 1,
×
×
×
V
×
WHL ← WHL – 1, C ← C – 1 End if C = 0 or Z = 0
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CHAPTER 19 INSTRUCTION OPERATIONS
Flags
Mnemonic
CMPBKNE
Operands
Bytes
2
Operation
S
Z
AC P/V CY
[TDE + ], [WHL +]
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or Z = 1
×
×
×
×
×
×
×
×
V
V
V
V
V
V
×
×
×
×
×
×
[TDE – ], [WHL –]
[TDE + ], [WHL +]
[TDE – ], [WHL –]
[TDE + ], [WHL +]
[TDE – ], [WHL –]
2
2
2
2
2
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or Z = 1
×
×
×
×
×
×
×
×
×
×
CMPBKC
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or CY = 0
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or CY = 0
CMPBKNC
(TDE) – (WHL), TDE ← TDE + 1,
WHL ← WHL + 1, C ← C – 1 End if C = 0 or CY = 1
(TDE) – (WHL), TDE ← TDE – 1,
WHL ← WHL – 1, C ← C – 1 End if C = 0 or CY = 1
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CHAPTER 19 INSTRUCTION OPERATIONS
19.3 Instructions Listed by Type of Addressing
(1) 8-bit instructions (combinations expressed by writing A for r are shown in parentheses)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND OR XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,
SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK,
XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
Table 19-1. List of Instructions by 8-Bit Addressing (1/2)
2nd Operand
r
saddr
saddr’
# byte
A
sfr
r’
1st Operand
A
Note 6
(MOV)
(MOV)
(XCH)
(ADD)
MOV
XCH
(MOV)
(XCH)
(ADD)
MOV
Note 1
Note 6
ADD
(XCH)
(ADD)
Note 1
Note 1
Note 1
Notes 1, 6
Note 1
(ADD)
r
MOV
ADD
(MOV)
(XCH)
(ADD)
MOV
XCH
MOV
XCH
MOV
XCH
Note 1
Note 1
Note 1
Note 1
ADD
ADD
ADD
Note 6
Note 1
saddr
sfr
MOV
ADD
(MOV)
(ADD)
MOV
ADD
MOV
XCH
ADD
Note 1
Note 1
Note 1
Note 1
MOV
ADD
MOV
MOV
ADD
Note 1
Note 1
(ADD)
!addr16
!!addr24
MOV
MOV
MOV
Note 1
ADD
mem
MOV
ADD
Note 1
[saddrp]
[%saddrg]
mem3
r3
MOV
MOV
MOV
PSWL
PSWH
B, C
STBC, WDM
[TDE +]
[TDE –]
(MOV)
(ADD)
MOVM
Note 1
Note 4
(See the following page for the explanation of Note.)
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CHAPTER 19 INSTRUCTION OPERATIONS
Table 19-1. List of Instructions by 8-Bit Addressing (2/2)
2nd Operand
mem
r3
!addr16
!!addr24
[WHL +]
[WHL –]
Note 2
[saddrp]
[%saddrg]
PSWL
PSWH
n
None
1st Operand
A
(MOV)
(XCH)
MOV
MOV
(MOV)
XCH
ADD
(XCH)
(ADD)
Note 1
Note 1
Note 1
ADD
Note 3
r
MOV
XCH
ROR
MULU
DIVUW
INC
DEC
saddr
sfr
INC
DEC
DBNZ
PUSH
POP
CHKL
CHKLA
!addr16
!!addr24
mem
[saddrp]
[%saddrg]
mem3
ROR4
ROL4
r3
PSWL
PSWH
B, C
DBNZ
STBC, WDM
Note 5
[TDE +]
[TDE –]
MOVBK
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR and CMP are the same as ADD.
2. There is no 2nd operand, or the 2nd operand is not an operand address.
3. ROL, RORC, ROLC, SHR and SHL are the same as ROR.
4. XCHM, CMPME, CMPMNE, CMPMNC and CMPMC are the same as MOVM.
5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC and CMPBKC are the same as MOVBK.
6. If saddr is saddr2 in this combination, there is a short code length instruction.
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CHAPTER 19 INSTRUCTION OPERATIONS
(2) 16-bit instructions (combinations expressed by writing AX for rp are shown in parentheses)
MOVM, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,
ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 19-2. List of Instructions by 16-Bit Addressing (1/2)
2nd Operand
rp
saddrp
saddrp’
# word
AX
sfrp
rp’
1st Operand
AX
Note 3
(MOVW)
(MOVW)
(XCHW)
(MOVW)
(XCHW)
(ADDW)
(MOVW)
MOVW
Note 1
Note 1
Note 1
Note 1
Note 3
ADDW
(XCHW)
(ADDW)
(XCHW)
(ADDW)
Note 1
Note 1
Notes 1,3
Note 1
(ADD)
rp
MOVW
ADDW
(MOVW)
(XCHW)
(ADDW)
MOVW
XCHW
MOVW
XCHW
MOVW
XCHW
Note 1
Note 1
Note 1
Note 1
ADDW
ADDW
ADDW
Note 3
Note 1
saddrp
sfrp
MOVW
ADDW
(MOVW)
(ADDW)
MOVW
ADDW
MOVW
XCHW
ADDW
Note 1
Note 1
MOVW
ADDW
MOVW
MOVW
ADDW
Note 1
Note 1
(ADDW)
!addr16
!!addr24
MOVW
(MOVW)
MOVW
MOVW
mem
[saddrp]
[%saddrg]
PSW
SP
ADDWG
SUBWG
post
[TDE +]
byte
(MOVW)
(See the following page for the explanation of Note.)
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CHAPTER 19 INSTRUCTION OPERATIONS
Table 19-2. List of Instructions by 16-Bit Addressing (2/2)
2nd Operand
mem
!!addr16
!!addr24
Note 2
[saddrp]
[WHL +]
byte
n
None
1st Operand
AX
[%saddrg]
(MOVW)
MOVW
XCHW
(MOVW)
(XCHW)
XCHW
Note 4
rp
MOVW
SHRW
SHLW
MULW
INCW
DECW
saddrp
sfrp
INCW
DECW
PUSH
POP
!addr16
!!addr24
MOVTBLW
mem
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
post
PUSH
POP
PUSHU
POPU
[TDE +]
byte
SACW
MACW
MACSW
Notes 1. SUBW and CMPW are the same as ADDW.
2. There is no 2nd operand, or the 2nd operand is not an operand address.
3. If saddrp is saddrp2 in this combination, there is a short code length instruction.
4. MULUW and DIVUX are the same as MULW.
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CHAPTER 19 INSTRUCTION OPERATIONS
(3) 24-bit instructions (combinations expressed by writing WHL for rg are shown in parentheses)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
Table 19-3. List of Instructions by 24-Bit Addressing
2nd Operand
rg
# imm24
WHL
saddrg
!!addr24
(MOVG)
mem1
MOVG
[%saddrg]
MOVG
SP
None*
rg’
1st Operand
WHL
(MOVG)
(ADDG)
(SUBG)
(MOVG)
(ADDG)
(SUBG)
(MOVG)
(ADDG)
(SUBG)
(MOVG)
ADDG
SUBG
MOVG
rg
MOVG
ADDG
SUBG
(MOVG)
(ADDG)
(SUBG)
MOVG
ADDG
SUBG
MOVG
MOVG
INCG
DECG
PUSH
POP
saddrg
!!addr24
mem1
(MOVG)
(MOVG)
MOVG
MOVG
MOVG
MOVG
MOVG
[%saddrg)
SP
MOVG
INCG
DECG
*
There is no 2nd operand, or the 2nd operand is not an operand address.
(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
Table 19-4. List of Instructions by Bit Manipulation Instruction Addressing
2nd Operand
saddr. bit sfr. bit
A.bit X. bit
/saddr.bit /sfr. bit
/A. bit /X. bit
PSWL. bit PSWH. bit
mem2. bit
/PSWL. bit /PSWH. bit
/mem2. bit
CY
None*
!addr16. bit
/!addr16. bit
1st Operand
!!addr24. bit
/!!addr24. bit
CY
MOV1
AND1
OR1
AND1
OR1
NOT
SET1
CLR1
XOR1
saddr. bit
sfr. bit
MOV1
NOT1
SET1
CLR1
BF
A. bit
X. bit
PSWL. bit
PSWH. bit
mem2. bit
!addr16. bit
!!addr24. bit
BT
BTCLR
BFSET
*
There is no 2nd operand, or the 2nd operand is not an operand address.
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CHAPTER 19 INSTRUCTION OPERATIONS
(5) Call/return instructions / branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC,
BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Table 19-5. List of Instructions by Call/Return Instruction/Branch Instruction Addressing
Instruction
Address
Operand
$addr20 $!addr20 !addr16 !!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
None
Basic
BC*
CALL
BR
CALL
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALLF
CALLT
BRKCS BRK
RET
instructions
BR
BR
RETCS
RETCSB
RETI
RETB
Compound
instructions
BF
BT
BTCLR
BFSET
DBNZ
*
BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same
as BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
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CHAPTER 20 ELECTRICAL SPECIFICATIONS (µPD784054)
Refer to CHAPTER 24 TIMING CHARTS for the timing charts.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to +0.5
–0.5 to VDD + 0.5 ≤ 7.0
–0.5 to VDD + 0.5
15
Unit
V
AVDD
AVSS
VI
V
V
Input voltage
Note 1
V
Output voltage
Output current, low
VO
V
IOL
All output pins
mA
mA
mA
mA
V
Total of all output pins
All output pins
150
Output current, high
Analog input voltage
IOH
VIAN
–10
Total of all output pins
–100
Note 2
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–10 to +70
A/D converter reference
input voltage
AVREF
V
Operating ambient
temperature
TA
°C
°C
Storage temperature
Tstg
–65 to +150
Notes 1. Pins other than the pins in Note 2.
2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation Frequency
TA
VDD
8 MHz ≤ fXX ≤ 32 MHz
–10 to +70°C
4.5 to 5.5 V
Capacitance (TA = 25°C, VSS = VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V.
CO
10
pF
CIO
10
pF
User’s Manual U11719EJ3V1UD
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CHAPTER 20 ELECTRICAL SEPCIFICATIONS (µPD784054)
Oscillator Characteristics (TA = –10 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Item
MIN.
8
MAX.
32
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
X1 input rise, fall time
8
0
32
5
MHz
ns
X1
X2
OpenNote
HCMOS inverter
X1 input high-, low-level
width
20
105
ns
Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse
phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to prevent an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with any other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 20 ELECTRICAL SEPCIFICATIONS (µPD784054)
DC Characteristics (TA = –10 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Input voltage, low
Input voltage, high
Symbol
VIL
Conditions
MIN.
0
TYP.
MAX.
0.8
Unit
V
VIH1
VIH2
VOL
Note 1
Note 2
2.2
VDD
V
0.8VDD
VDD
Output voltage, low
IOL = 2.0 mA
IOH = –400 µA
Note 3
0.45
V
Output voltage, high
Input leakage current
Analog pin input leakage current
Output leakage current
VDD supply current
VOH
ILI
VDD – 1.0
V
0 V ≤ VI ≤ VDD
10
1
µA
µA
µA
mA
mA
mA
V
ILIAN
ILO
Note 4
0 V ≤ VI ≤ AVDD
0 V ≤ VO ≤ VDD
10
80
60
20
IDD1
IDD2
IDD3
VDDDR
IDDDR
Operating mode (fXX = 32 MHz)
HALT mode (fXX = 32 MHz)
IDLE mode (fXX = 32 MHz)
STOP mode
50
30
10
Data retention voltage
Data retention current
2.5
15
STOP mode VDDDR = 2.5 V
VDDDR = 5 V 10%
2
15
50
80
µA
µA
kΩ
15
40
Pull-up resistor
RL
Notes 1. Pins other than pins in the Note 2
2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/
INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET
3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as
analog inputs)
4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog input, only during the non-
sampling operation)
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CHAPTER 20 ELECTRICAL SEPCIFICATIONS (µPD784054)
AC Characteristics (TA = –10 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
(1) Read/write operation
Parameter
Symbol
Expression
MIN.
62.5
11.2
11.2
14.2
47.5
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock cycle time
tCYK
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
ASTB high-level width
tSAST
tHSTA
tWSTH
tDAR
(0.5 + a) T – 20
0.5T – 20
(0.5 + a) T – 17
(1 + a) T – 15
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from RD↓
tFRA
0
tDAID
(2.5 + a + n) T – 56
(1.5 + n) T – 48
0.5T – 16
100.2
45.7
tDRID
RD↓ delay time from ASTB↓
Data hold time (to RD↑)
tDSTR
tHRID
15.3
0
Address active time from RD↑
RD low-level width
tDRA
0.5T – 14
17.2
63.7
47.5
tWRL
(1.5 + n) T – 30
(1 + a) T – 15
LWR, HWR↓ delay time from address
Data output time from LWR, HWR↓
LWR, HWR↓ delay time from ASTB↓
Data setup time (to LWR, HWR↑)
Data hold time (from LWR, HWR↑)
ASTB↑ delay time from LWR, HWR↑
LWR, HWR low-level width
tDAW
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
15
0.5T – 16
15.3
68.7
17.2
78.8
57.7
(1.5 + n) T – 25
0.5T – 14
1.5T – 15
(1.5 + n) T – 36
(2 + a) T – 50
1.5T – 40
WAIT↓ input time from address
WAIT↓ input time from ASTB↓
WAIT hold time from ASTB↓
WAIT↑ delay time from ASTB↓
WAIT↓ input time from RD↓
WAIT hold time from RD↓
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWT
tHRWT
tDRWTH
tDWWT
tHWWT
tDWWTH
75
53.7
(1.5 + n) T + 5
(2.5 + n) T – 40
T – 40
98.8
67.5
67.5
116.2Note
22.5
(1 + n) T + 5
(1 + n) T – 40
T – 40
WAIT↑ delay time from RD↓
WAIT↓ input time from LWR, HWR↓
WAIT hold time from LWR, HWR↓
WAIT↑ delay time from LWR, HWR↓
85Note
22.5
(1 + n) T + 5
(1 + n) T – 40
85Note
Note Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise, 0.
3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (tCYK = T). The values in the above expression
column are calculated based on T = 62.5 ns.
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CHAPTER 20 ELECTRICAL SEPCIFICATIONS (µPD784054)
(2) Serial Operation (TA = –10 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TSFT
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle time
tCYSK
SCK1, SCK2 output BRG
SCK1, SCK2 input
External clock
500
Serial clock low-level width
Serial clock high-level width
tWSKL
tWSKH
SCK1, SCK2 output BRG
0.5TSFT–40
210
SCK1, SCK2 input
External clock
SCK1, SCK2 output BRG
0.5TSFT–40
210
SCK1, SCK2 input
External clock
SI1, SI2 setup time
tSSSK
tHSSK
tDSBSK
80
(to SCK1, SCK2↑)
SI1, SI2 hold time
80
0
ns
ns
(from SCK1, SCK2↑)
SO1, SO2 output
R = 1 kΩ, C = 100 pF
150
delay time from SCK1, SCK2↓
Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8.
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
(3) Other Operations (TA = –10 to +70°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
MAX.
Unit
µs
NMI high-, low-level width
tWNIH, tWNIL
INTP0 to INTP6 high-, low-level width tWITH, tWITL
tWRSH, tWRSL
4
tCYSMP
µs
RESET high-, low-level width
10
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software.
When NIn = 0, tCYSMP = tCYK
When NIn = 1, tCYSMP = tCYK × 4
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
3. NIn: Bit n of NPC (n = 0 to 6)
User’s Manual U11719EJ3V1UD
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CHAPTER 20 ELECTRICAL SEPCIFICATIONS (µPD784054)
A/D Converter Characteristics (TA = –10 to +70 °C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Total errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
0.5
0.7
1/2
%FSRNote 2
%FSRNote 2
LSB
Quantization error
Conversion time
tCONV
80 ns ≤ tCYK ≤ 250 ns
62.5 ns ≤ tCYK < 80 ns
80 ns ≤ tCYK ≤ 250 ns
62.5 ns ≤ tCYK < 80 ns
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
169
208
20
tCYK
tCYK
Sampling time
tSAMP
tCYK
24
tCYK
Zero-scale errorNote 1
Full-scale errorNote 1
Integral linearity errorNote 1
Analog input voltage
1.5
1.5
1.5
1.5
1.5
1.5
3.5
4.5
LSB
LSB
3.5
LSB
4.5
LSB
2.5
LSB
4.5
LSB
VIAN
–0.3
3.4
AVREF+0.3
AVDD
V
A/D converter reference input
voltage
AVREF
V
AVREF current
AIREF
AIDD
1.0
2.0
2
3.0
6.0
10
mA
mA
µA
AVDD supply current
A/D converter data retention
current
AIDDDR
STOP
mode
AVDDDR = 2.5 V
AVDDDR = 5 V 10%
10
50
µA
Notes 1. The quantization error is excluded.
2. Indicated as a ratio (%FSR) to the full-scale value.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
428
User’s Manual U11719EJ3V1UD
CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
Refer to CHAPTER 24 TIMING CHARTS for the timing charts.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to +0.5
–0.5 to VDD + 0.5 ≤ 7.0
–0.5 to VDD + 0.5
15
Unit
V
AVDD
AVSS
VI
V
V
Input voltage
Note 1
V
Output voltage
Output current, low
VO
V
IOL
All output pins
mA
mA
mA
mA
V
Total of all output pins
All output pins
150
Output current, high
Analog input voltage
IOH
VIAN
–10
Total of all output pins
–100
Note 2
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–40 to +85
A/D converter reference
input voltage
AVREF
V
Operating temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Notes 1. Pins other than the pins in Note 2.
2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation Frequency
TA
VDD
8 MHz ≤ fXX ≤ 25 MHz
–40 to +85°C
4.5 to 5.5 V
Capacitance (TA = 25°C, VSS = VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V.
CO
10
pF
CIO
10
pF
User’s Manual U11719EJ3V1UD
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
Oscillator Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Item
MIN.
8
MAX.
25
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
V
SS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
X1 input rise, fall time
8
0
25
5
MHz
ns
X1
X2
OpenNote
X1 input high-, low-level
width
20
105
ns
HCMOS inverter
Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse
phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to prevent an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with any other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
430
User’s Manual U11719EJ3V1UD
CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
DC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Input voltage, low
Input voltage, high
Symbol
VIL
Conditions
MIN.
0
TYP.
MAX.
0.8
Unit
V
VIH1
VIH2
VOL
Note 1
Note 2
2.2
VDD
V
0.8VDD
VDD
Output voltage, low
IOL = 2.0 mA
IOH = –400 µA
Note 3
0.45
V
Output voltage, high
Input leakage current
Analog pin input leakage current
Output leakage current
VDD supply current
VOH
ILI
VDD – 1.0
V
0 V ≤ VI ≤ VDD
10
1
µA
µA
µA
mA
mA
mA
V
ILIAN
ILO
Note 4
0 V ≤ VI ≤ AVDD
0 V ≤ VO ≤ VDD
10
70
50
20
IDD1
Operating mode (fXX = 25 MHz)
HALT mode (fXX = 25 MHz)
IDLE mode (fXX = 25 MHz)
STOP mode
40
25
10
IDD2
IDD3
Data retention voltage
Data retention current
VDDDR
IDDDR
2.5
15
STOP mode VDDDR = 2.5 V
VDDDR = 5 V 10 %
2
15
50
80
µA
µA
kΩ
15
40
Pull-up resistor
RL
Notes 1. Pins other than pins in Note 2.
2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/
INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET
3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as
analog inputs)
4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog input, only during the non-
sampling operation)
User’s Manual U11719EJ3V1UD
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
AC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
(1) Read/write operation
Parameter
Symbol
Expression
MIN.
80
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock cycle time
tCYK
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
ASTB high-level width
tSAST
tHSTA
tWSTH
tDAR
(0.5 + a) T – 20
20
0.5T – 20
20
(0.5 + a) T – 17
(1 + a) T – 15
23
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from RD↓
65
tFRA
0
tDAID
(2.5 + a + n) T – 56
(1.5 + n) T – 48
0.5T – 16
144
72
tDRID
RD↓ delay time from ASTB↓
Data hold time (to RD↑)
tDSTR
tHRID
24
0
Address active time from RD↑
RD low-level width
tDRA
0.5T – 14
26
90
65
tWRL
(1.5 + n) T – 30
(1 + a) T – 15
LWR, HWR↓ delay time from address
Data output time from LWR, HWR↓
LWR, HWR↓ delay time from ASTB↓
Data setup time (to LWR, HWR↑)
Data hold time (from LWR, HWR↑)
ASTB↑ delay time from LWR, HWR↑
LWR, HWR low-level width
tDAW
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
15
0.5T – 16
24
95
(1.5 + n) T – 25
0.5T – 14
26
1.5T – 15
105
84
(1.5 + n) T – 36
(2 + a) T – 50
1.5T – 40
WAIT↓ input time from address
WAIT↓ input time from ASTB↓
WAIT hold time from ASTB↓
WAIT↑ delay time from ASTB↓
WAIT↓ input time from RD↓
WAIT hold time from RD↓
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWT
tHRWT
tDRWTH
tDWWT
tHWWT
tDWWTH
110
80
(1.5 + n) T + 5
(1.5 + n) T – 40
T – 40
125
85
160Note
40
(1 + n) T + 5
(1 + n) T – 40
T – 40
WAIT↑ delay time from RD↓
WAIT↓ input time from LWR, HWR↓
WAIT hold time from LWR, HWR↓
WAIT↑ delay time from LWR, HWR↓
120Note
40
(1 + n) T + 5
(1 + n) T – 40
85
120Note
Note Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise, 0.
3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (tCYK = T). The values in the above expression
column are calculated based on T = 80 ns.
432
User’s Manual U11719EJ3V1UD
CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
(2) Serial Operation (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TSFT
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle time
tCYSK
SCK1, SCK2 output BRG
SCK1, SCK2 input
External clock
640
Serial clock low-level width
Serial clock high-level width
tWSKL
tWSKH
SCK1, SCK2 output BRG
0.5TSFT–40
280
SCK1, SCK2 input
External clock
SCK1, SCK2 output BRG
0.5TSFT–40
280
SCK1, SCK2 input
External clock
SI1, SI2 setup time
tSSSK
tHSSK
tDSBSK
80
(to SCK1, SCK2↑)
SI1, SI2 hold time
80
0
ns
ns
(from SCK1, SCK2↑)
SO1, SO2 output delay time
R = 1 kΩ, C = 100 pF
150
from SCK1, SCK2↓
Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8.
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
(3) Other Operations (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
tWNIH, tWNIL
tWITH, tWITL
Conditions
MIN.
10
MAX.
Unit
µs
NMI high, low-level width
INTP0-INTP6 high, low-level width
RESET high, low-level width
4
tCYSMP
µs
tWRSH, tWRSL
10
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software.
When NIn = 0, tCYSMP = tCYK
When NIn = 1, tCYSMP = tCYK × 4
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
3. NIn: Bit n of NPC (n = 0-6)
User’s Manual U11719EJ3V1UD
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CHAPTER 21 ELECTRICAL SPECIFICATIONS (µPD784054(A))
A/D Converter Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Total errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
0.5
0.7
1/2
%FSRNote 2
%FSRNote 2
LSB
Quantization error
Conversion time
Sampling time
tCONV
80 ns ≤ tCYK ≤ 250 ns
80 ns ≤ tCYK ≤ 250 ns
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
169
20
tCYK
tSAMP
tCYK
Zero-scale errorNote 1
1.5
1.5
1.5
1.5
1.5
1.5
3.5
4.5
LSB
LSB
Full-scale errorNote 1
3.5
LSB
4.5
LSB
Integral linearity errorNote 1
2.5
LSB
4.5
LSB
Analog input voltage
VIAN
–0.3
3.4
AVREF+0.3
AVDD
V
A/D converter reference input
voltage
AVREF
V
AVREF current
AIREF
AIDD
1.0
2.0
2
3.0
6.0
10
mA
mA
µA
AVDD supply current
A/D converter data retention
current
AIDDDR
STOP
mode
AVDDDR = 2.5 V
AVDDDR = 5 V 10%
10
50
µA
Notes 1. The quantization error is excluded.
2. Indicated as a ratio (%FSR) to the full-scale value.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
434
User’s Manual U11719EJ3V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
Refer to CHAPTER 24 TIMING CHARTS for the timing charts.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to +0.5
–0.5 to VDD + 0.5 ≤ 7.0
–0.5 to VDD + 0.5
15
Unit
V
AVDD
AVSS
VI
V
V
Input voltage
Note 1
V
Output voltage
Output current, low
VO
V
IOL
All output pins
mA
mA
mA
mA
V
Total of all output pins
All output pins
150
Output current, high
Analog input voltage
IOH
VIAN
–10
Total of all output pins
–100
Note 2
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–40 to +110
–65 to +150
A/D converter reference
input voltage
AVREF
V
Operating temperature
Storage temperature
TA
°C
°C
Tstg
Notes 1. Pins other than the pins in Note 2.
2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation Frequency
TA
VDD
8 MHz ≤ fXX ≤ 20 MHz
–40 to +110°C
4.5 to 5.5 V
Capacitance (TA = 25°C, VSS = VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V.
CO
10
pF
CIO
10
pF
User’s Manual U11719EJ3V1UD
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
Oscillator Characteristics (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Item
MIN.
8
MAX.
20
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
X1 input rise, fall time
8
0
20
5
MHz
ns
X1
X2
OpenNote
X1 input high-, low-level
width
20
105
ns
HCMOS inverter
Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse
phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to prevent an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with any other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
436
User’s Manual U11719EJ3V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
DC Characteristics (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Input voltage, low
Input voltage, high
Symbol
VIL
Conditions
MIN.
0
TYP.
MAX.
0.8
Unit
V
VIH1
VIH2
VOL
Note 1
Note 2
2.2
VDD
V
0.8VDD
VDD
Output voltage, low
IOL = 2.0 mA
IOH = –400 µA
Note 3
0.45
V
Output voltage, high
Input leakage current
Analog pin input leakage current
Output leakage current
VDD supply current
VOH
ILI
VDD – 1.0
V
0 V ≤ VI ≤ VDD
10
2
µA
µA
µA
mA
mA
mA
V
ILIAN
ILO
Note 4
0 V ≤ VI ≤ AVDD
0 V ≤ VO ≤ VDD
10
60
30
20
IDD1
Operating mode (fXX = 20 MHz)
HALT mode (fXX = 20 MHz)
IDLE mode (fXX = 20 MHz)
STOP mode
30
15
10
IDD2
IDD3
Data retention voltage
Data retention current
VDDDR
IDDDR
2.5
15
STOP mode VDDDR = 2.5 V
VDDDR = 5 V 10 %
2
100
1000
80
µA
µA
kΩ
15
40
Pull-up resistor
RL
Notes 1. Pins other than pins in Note 2.
2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/
INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET
3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as
analog inputs)
4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog input, only during the non-
sampling operation)
User’s Manual U11719EJ3V1UD
437
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
AC Characteristics (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
(1) Read/write operation
Parameter
Symbol
Expression
MIN.
100
30
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock cycle time
tCYK
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
ASTB high-level width
tSAST
tHSTA
tWSTH
tDAR
(0.5 + a) T – 20
0.5T – 20
30
(0.5 + a) T – 17
(1 + a) T – 15
33
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from RD↓
85
tFRA
0
tDAID
(2.5 + a + n) T – 56
(1.5 + n) T – 53
0.5T – 16
194
97
tDRID
RD↓ delay time from ASTB↓
Data hold time (to RD↑)
tDSTR
tHRID
34
0
Address active time from RD↑
RD low-level width
tDRA
0.5T – 14
36
120
85
tWRL
(1.5 + n) T – 30
(1 + a) T – 15
LWR, HWR↓ delay time from address
Data output time from LWR, HWR↓
LWR, HWR↓ delay time from ASTB↓
Data setup time (to LWR, HWR↑)
Data hold time (from LWR, HWR↑)
ASTB↑ delay time from LWR, HWR↑
LWR, HWR low-level width
tDAW
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
15
0.5T – 16
34
125
36
(1.5 + n) T – 25
0.5T – 14
1.5T – 15
135
114
(1.5 + n) T – 36
(2 + a) T – 50
1.5T – 40
WAIT↓ input time from address
WAIT↓ input time from ASTB↓
WAIT hold time from ASTB↓
WAIT↑ delay time from ASTB↓
WAIT↓ input time from RD↓
WAIT hold time RD↓
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWT
tHRWT
tDRWTH
tDWWT
tHWWT
tDWWTH
150
110
(1.5 + n) T + 5
(1.5 + n) T – 40
T – 40
155
105
105
210Note
60
(1 + n) T + 5
(1 + n) T – 40
T – 40
WAIT↑ delay time from RD↓
WAIT↓ input time from LWR, HWR↓
WAIT hold time from LWR, HWR↓
WAIT↑ delay time from LWR, HWR↓
160Note
60
(1 + n) T + 5
(1 + n) T – 40
160Note
Note Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise, 0.
3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (tCYK = T). The values in the above expression
column are calculated based on T = 100 ns.
438
User’s Manual U11719EJ3V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
(2) Serial Operation (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TSFT
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle time
tCYSK
SCK1, SCK2 output BRG
SCK1, SCK2 input
External clock
800
Serial clock low-level width
Serial clock high-level width
tWSKL
tWSKH
SCK1, SCK2 output BRG
0.5TSFT–40
360
SCK1, SCK2 input
External clock
SCK1, SCK2 output BRG
0.5TSFT–40
360
SCK1, SCK2 input
External clock
SI1, SI2 setup time
tSSSK
tHSSK
tDSBSK
80
(to SCK1, SCK2↑)
SI1, SI2 hold time
80
0
ns
ns
(from SCK1, SCK2↑)
SO1, SO2 output delay time
R = 1 kΩ, C = 100 pF
150
from SCK1, SCK2↓
Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8.
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
(3) Other Operations (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
tWNIH, tWNIL
tWITH, tWITL
Conditions
MIN.
10
MAX.
Unit
µs
NMI high, low-level width
INTP0-INTP6 high, low-level width
RESET high, low-level width
4
tCYSMP
µs
tWRSH, tWRSL
10
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software.
When NIn = 0, tCYSMP = tCYK
When NIn = 1, tCYSMP = tCYK × 4
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
3. NIn: Bit n of NPC (n = 0-6)
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CHAPTER 22 ELECTRICAL SPECIFICATIONS (µPD784054(A1))
A/D Converter Characteristics (TA = –40 to +110°C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Total errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
0.5
0.7
1/2
%FSRNote 2
%FSRNote 2
LSB
Quantization error
Conversion time
Sampling time
tCONV
169
20
tCYK
tSAMP
tCYK
Zero-scale errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
1.5
1.5
1.5
1.5
1.5
1.5
3.5
4.5
LSB
LSB
Full-scale errorNote 1
3.5
LSB
4.5
LSB
Integral linearity errorNote 1
2.5
LSB
4.5
LSB
Analog input voltage
VIAN
–0.3
3.4
AVREF+0.3
AVDD
V
A/D converter reference input
voltage
AVREF
V
AVREF current
AIREF
AIDD
3.0
2.0
2
4.0
6.0
mA
mA
µA
µA
AVDD supply current
A/D converter data retention
current
AIDDDR
STOP
mode
AVDDDR = 2.5 V
100
1000
AVDDDR = 5 V 10%
10
Notes 1. The quantization error is excluded.
2. Indicated as a ratio (%FSR) to the full-scale value.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
Refer to CHAPTER 24 TIMING CHARTS for the timing charts.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
–0.5 to +7.0
–0.5 to VDD + 0.5
–0.5 to +0.5
–0.5 to VDD + 0.5 ≤ 7.0
–0.5 to VDD + 0.5
15
Unit
V
AVDD
AVSS
VI
V
V
Input voltage
Note 1
V
Output voltage
Output current, low
VO
V
IOL
All output pins
mA
mA
mA
mA
V
Total of all output pins
All output pins
150
Output current, low
Analog input voltage
IOH
VIAN
–10
Total of all output pins
–100
Note 2
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–0.5 to VDD + 0.5
–0.5 to AVDD + 0.5
–40 to +125
–65 to +150
A/D converter reference
input voltage
AVREF
V
Operating temperature
Storage temperature
TA
°C
°C
Tstg
Notes 1. Pins other than the pins in Note 2.
2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions
that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation Frequency
TA
VDD
8 MHz ≤ fXX ≤ 20 MHz
–40 to +125°C
4.5 to 5.5 V
Capacitance (TA = 25°C, VSS = VDD = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
Unmeasured pins returned to 0 V.
CO
10
pF
CIO
10
pF
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
Oscillator Characteristics (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Item
MIN.
8
MAX.
20
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
VSS
X1
X2
C1
C2
External clock
X1 input frequency (fX)
X1 input rise, fall time
8
0
20
5
MHz
ns
X1
X2
OpenNote
X1 input high-, low-level
width
20
105
ns
HCMOS inverter
Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse
phase clock of the pin X1 to the pin X2 when the EXTC bit = 1.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to prevent an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with any other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
DC Characteristics (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Input voltage, low
Input voltage, high
Symbol
VIL
Conditions
MIN.
0
TYP.
MAX.
0.8
Unit
V
VIH1
VIH2
VOL
Note 1
Note 2
2.2
VDD
V
0.8VDD
VDD
Output voltage, low
IOL = 2.0 mA
IOH = –400 µA
Note 3
0.45
V
Output voltage, high
Input leakage current
Analog pin input leakage current
Output leakage current
VDD supply current
VOH
ILI
VDD – 1.0
V
0 V ≤ VI ≤ VDD
10
2
µA
µA
µA
mA
mA
mA
V
ILIAN
ILO
Note 4
0 V ≤ VI ≤ AVDD
0 V ≤ VO ≤ VDD
10
60
30
20
IDD1
Operating mode (fXX = 20 MHz)
HALT mode (fXX = 20 MHz)
IDLE mode (fXX = 20 MHz)
STOP mode
30
15
10
IDD2
IDD3
Data retention voltage
Data retention current
VDDDR
IDDDR
2.5
15
STOP mode VDDDR = 2.5 V
VDDDR = 5 V 10 %
2
100
1000
80
µA
µA
kΩ
15
40
Pull-up resistor
RL
Notes 1. Pins other than pins in Note 2.
2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/
INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET
3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as
analog inputs)
4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog input, only during the non-
sampling operation)
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
AC Characteristics (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
(1) Read/write operation
Parameter
Symbol
Expression
MIN.
100
30
MAX.
250
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock cycle time
tCYK
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
ASTB high-level width
tSAST
tHSTA
tWSTH
tDAR
(0.5 + a) T – 20
0.5T – 20
30
(0.5 + a) T – 17
(1 + a) T – 15
33
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from RD↓
85
tFRA
0
tDAID
(2.5 + a + n) T – 56
(1.5 + n) T – 53
0.5T – 16
194
97
tDRID
RD↓ delay time from ASTB↓
Data hold time (to RD↑)
tDSTR
tHRID
34
0
Address active time from RD↑
RD low-level width
tDRA
0.5T – 14
36
120
85
tWRL
(1.5 + n) T – 30
(1 + a) T – 15
LWR, HWR↓ delay time from address
Data output time from LWR, HWR↓
LWR, HWR↓ delay time from ASTB↓
Data setup time (to LWR, HWR↑)
Data hold time (from LWR, HWR↑)
ASTB↑ delay time from LWR, HWR↑
LWR, HWR low-level width
tDAW
tDWOD
tDSTW
tSODW
tHWOD
tDWST
tWWL
15
0.5T – 16
34
125
36
(1.5 + n) T – 25
0.5T – 14
1.5T – 15
135
114
(1.5 + n) T – 36
(2 + a) T – 50
1.5T – 40
WAIT↓ input time from address
WAIT↓ input time from ASTB↓
WAIT hold time from ASTB↓
WAIT↑ delay time from ASTB↓
WAIT↓ input time from RD↓
WAIT hold time from RD↓
tDAWT
tDSTWT
tHSTWT
tDSTWTH
tDRWT
tHRWT
tDRWTH
tDWWT
tHWWT
tDWWTH
150
110
(1.5 + n) T + 5
(1.5 + n) T – 40
T – 40
155
105
105
210Note
60
(1 + n) T + 5
(1 + n) T – 40
T – 40
WAIT↑ delay time from RD↓
WAIT↓ input time LWR, HWR↓
WAIT hold time LWR, HWR↓
WAIT↑ delay time from LWR, HWR↓
160Note
60
(1 + n) T + 5
(1 + n) T – 40
160Note
Note Specification when an external wait is inserted
Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise, 0.
3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or program-
mable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (tCYK = T). The values in the above expression
column are calculated based on T = 100 ns.
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
(2) Serial Operation (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TSFT
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle time
tCYSK
SCK1, SCK2 output BRG
SCK1, SCK2 input
External clock
800
Serial clock low-level width
Serial clock high-level width
tWSKL
tWSKH
SCK1, SCK2 output BRG
0.5TSFT–40
360
SCK1, SCK2 input
External clock
SCK1, SCK2 output BRG
0.5TSFT–40
360
SCK1, SCK2 input
External clock
SI1, SI2 setup time
tSSSK
tHSSK
tDSBSK
80
(to SCK1, SCK2↑)
SI1, SI2 hold time
80
0
ns
ns
(from SCK1, SCK2↑)
SO1, SO2 output delay time
R = 1 kΩ, C = 100 pF
150
from SCK1, SCK2↓
Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8.
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
(3) Other Operations (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = 0 V)
Parameter
Symbol
tWNIH, tWNIL
tWITH, tWITL
Conditions
MIN.
10
MAX.
Unit
µs
NMI high, low-level width
INTP0-INTP6 high, low-level width
RESET high, low-level width
4
tCYSMP
µs
tWRSH, tWRSL
10
Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software.
When NIn = 0, tCYSMP = tCYK
When NIn = 1, tCYSMP = tCYK × 4
2. tCYK = 1/fCLK (fCLK is internal system clock frequency)
3. NIn: Bit n of NPC (n = 0-6)
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CHAPTER 23 ELECTRICAL SPECIFICATIONS (µPD784054(A2))
A/D Converter Characteristics (TA = –40 to +125°C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD)
Parameter
Resolution
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Total errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
0.5
0.7
1/2
%FSRNote 2
%FSRNote 2
LSB
Quantization error
Conversion time
Sampling time
tCONV
169
20
tCYK
tSAMP
tCYK
Zero-scale errorNote 1
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
4.5 V ≤ AVREF ≤ AVDD
3.4 V ≤ AVREF < 4.5 V
1.5
1.5
1.5
1.5
1.5
1.5
3.5
4.5
LSB
LSB
Full-scale errorNote 1
3.5
LSB
4.5
LSB
Integral linearity errorNote 1
2.5
LSB
4.5
LSB
Analog input voltage
VIAN
–0.3
3.4
AVREF+0.3
AVDD
V
A/D converter reference input
voltage
AVREF
V
AVREF current
AIREF
AIDD
3.0
2.0
2
4.0
6.0
mA
mA
µA
µA
AVDD supply current
A/D converter data retention
current
AIDDDR
STOP
mode
AVDDDR = 2.5 V
100
1000
AVDDDR = 5 V 10%
10
Notes 1. The quantization error is excluded.
2. Indicated as a ratio (%FSR) to the full-scale value.
Remark tCYK = 1/fCLK (fCLK is internal system clock frequency).
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CHAPTER 24 TIMING CHARTS
AC Timing Test Points
V
DD
0.8VDD or 2.2 V
0.8 V
0.8VDD or 2.2 V
0.8 V
Test points
0 V
Read Operation (8 bits)
tCYK
(CLK)
AD8 to AD15
(Output)
Higher address
Higher address
t
DAID
t
SAST
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AD0 to AD7
(I/O)
Lower address (output)
Data (input)
Lower address (output)
t
WSTH
t
HRID
ASTB
(Output)
t
HSTA
t
FRA
RD
(Output)
tDSTR
t
DRID
t
DRA
t
DAR
t
WRL
t
t
DSTWTH
HSTWT
t
DSTWT
t
tHDRRWWTTH
t
DRWT
tDAWT
WAIT
(Input)
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CHAPTER 24 TIMING CHARTS
Write Operation (8 bits)
t
CYK
(CLK)
AD8 to AD15
(Output)
Higher address
Higher address
t
SAST
AD0 to AD7
(Output)
Lower address (output)
Undefined
Data (output)
Lower address (output)
t
HWOD
t
WSTH
ASTB
(Output)
t
DWST
t
HSTA
LWR
(Output)
t
DSTW
t
DWOD
t
SODW
t
DAW
t
WWL
t
DSTWTH
HSTWT
t
t
DSTWT
t
HWWT
DWWTH
t
t
DWWT
t
DAWT
WAIT
(Input)
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CHAPTER 24 TIMING CHARTS
Read Operation (16 bits)
t
CYK
(CLK)
t
DAID
tSAST
AD8 to AD15
AD0 to AD7
(I/O)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Address (output)
Data (input)
Address (output)
t
WSTH
t
HRID
ASTB
(Output)
t
HSTA
t
FRA
RD
(Output)
tDSTR
tDRA
t
DRID
t
DAR
t
WRL
t
DSTWTH
HSTWT
t
t
DSTWT
tHDRRWWTTH
t
t
DRWT
tDAWT
WAIT
(Input)
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CHAPTER 24 TIMING CHARTS
Write Operation (16 bits)
tCYK
(CLK)
t
SAST
AD8 to AD15
AD0 to AD7
(Output)
Address (output)
Undefined
Data (output)
Address (output)
tHWOD
tWSTH
ASTB
(Output)
tDWST
tHSTA
HWR, LWR
(Output)
tDSTW
tDWOD
tSODW
tDAW
tWWL
t
DSTWTH
HSTWT
t
t
DSTWT
t
HWWT
tDWWTH
tDWWT
tDAWT
WAIT
(Input)
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CHAPTER 24 TIMING CHARTS
Serial Operation
t
CYSK
t
WSKH
t
WSKL
SCK1, SCK2
t
DSBSK
SO1, SO2
SI1, SI2
t
SSSK
t
HSSK
Interrupt Input Timing
tWNIH
tWNIL
0.8VDD
0.8 V
NMI
tWITH
tWITL
0.8VDD
0.8 V
INTP0 to INTP6
Reset Input Timing
tWRSH
tWRSL
0.8VDD
0.8 V
RESET
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CHAPTER 25 PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C D
R
Q
21
20
80
1
F
G
J
M
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
17.2 0.4
14.0 0.2
14.0 0.2
17.2 0.4
0.825
0.825
0.30 0.10
0.13
J
0.65 (T.P.)
1.6 0.2
0.8 0.2
K
L
+0.10
0.15
M
−0.05
N
P
Q
R
S
0.10
2.7 0.1
0.1 0.1
5° 5°
3.0 MAX.
S80GC-65-3B9-6
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CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS
The µPD784054 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 26-1. Surface Mounting Type Soldering Conditions
µPD784054GC-×××-3B9:
80-pin plastic QFP (14 x 14)
µPD784054GC(A)-×××-3B9: 80-pin plastic QFP (14 x 14)
µPD784054GC(A1)-×××-3B9: 80-pin plastic QFP (14 x 14)
µPD784054GC(A2)-×××-3B9: 80-pin plastic QFP (14 x 14)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), IR35-00-3
Count: three times or less
VPS
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher), VP15-00-3
Count: three times or less
Wave soldering
Partial heating
Solder bath temperature: 260°C Max., Time 10 sec. Max., Count: once,
Preheating temperature: 120°C Max. (package surface temperature)
Pin temperature: 350°C Max., Time: 3 sec. Max. (per pin row)
WS60-00-1
–
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD784054GC-×××-3B9-A: 80-pin plastic QFP (14 x 14)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
higher), Count: Three times or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 20 to 72 hours)
IR60-207-3
Wave soldering
Partial heating
For details, contact an NEC Electronics sales representative.
–
–
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
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CHAPTER 27 CAUTIONS ON USING DEVELOPMENT TOOLS
When developing a program by using in-circuit emulator IE-784000-R, note the following point.
(1) Setting of standby control register (STBC)
•
Include an instruction that sets the standby control register (STBC) to 00H following the LOCATION instruction and
initialization of the stack pointer (SP) in the program after reset is cleared.
Program example:
RSTVCT
CSEG
DW
AT 0
RSTSTRT
to
INITSEG
CSEG
BASE
RSTSTRT: LOCATION 0H; or LOCATION 0FH
MOVG
MOV
SP, #STKBGN
STBC, #0H
Reason: The internal system clock of the µPD784054 is fixed to fXX/2. However, the internal system clock of the
in-circuit emulator is set to fXX/16 after reset has been cleared. Therefore, the setting of the STBC must
be changed as described above.
Even if the instruction that sets the STBC to 00H is executed, the operation is not affected because the STBC of the real
chip is fixed to 30H. For the same reason, the value of the STBC of the real chip is always 30H when it is read. The value
of the STBC on the in-circuit emulator, however, is changed to 00H when the above setting is made. Therefore, note that
the value of the STBC of the in-circuit emulator and that of the real chip differ when they are read.
(2) Output of CLKOUT pin
The CLKOUT pin of the real chip always outputs the oscillation frequency (fXX). However, in the case of the in-circuit
emulator IE-784000-R, the internal system clock (fXX/2 or fXX/16Note) is output. Note that fXX is not output from the in-
circuit emulator.
Note The CLKOUT pin output of the in-circuit emulator is set to fXX/16 after the reset has been released, and set to
fXX/2 when 00H is set to the standby control register (STBC).
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the µPD784046
Subseries.
Figure A-1 shows the development tool configuration.
• Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles can be used for PC98-NX series
computers. When using PC98-NX series computers, refer to the description for IBM PC/AT compatibles.
• Windows
Unless otherwise specified, “Windows” means the following OSs.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Ver. 4.0
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulator IE-78K4-NS
Language Processing Software
• Assembler package
• C compiler package
• C library source file
• Device file
Debugging Tool
• System simulator
• Integrated debugger
• Device file
Embedded Software
• Real-time OS
Host Machine (PC)
Interface adapter,
PC card interface, etc
Flash Memory
Write Environment
In-circuit Emulator
Emulation board
Flash programmer
Power supply unit
Flash memory
write adapter
Emulation probe
On-chip flash
memory version
Conversion socket or
conversion adapter
Target system
456
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration (2/2)
(2) When using the in-circuit emulator IE-784000-R
Language Processing Software
• Assembler package
• C compiler package
• C library source file
• Device file
Debugging Tool
• System simulator
• Integrated debugger
• Device file
Embedded Software
• Real-time OS
Host Machine (PC or EWS)
Interface board
Flash Memory
Write Environment
In-circuit Emulator
Interface adapter
Emulation board
I/O emulation board
Probe board
Flash programmer
Flash memory
write adapter
On-chip flash
memory version
Emulation probe conversion board
Emulation probe
Conversion socket or
conversion adapter
Target system
Remark Items in broken line boxes differ according to the development environment. Refer to A.3.1 Hardware.
User’s Manual U11719EJ3V1UD
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APPENDIX A DEVELOPMENT TOOLS
A.1 Language Processing Software
Development tools (software) common to the 78K/IV Series are combined in this
package.
SP78K4
78K/IV Series Software package
Part number: µS××××SP78K4
This assembler converts programs written in mnemonics into an object codes
executable with a microcomputer.
RA78K4
Assembler package
Further, this assembler is provided with functions capable of automatically creating
symbol tables and branch instruction optimization.
This assembler should be used in combination with an optical device file (DF784046).
<Precaution when using RA78K4 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Win-
dows.
Part number: µS××××RA78K4
CC78K4
This compiler converts programs written in C language into object codes executable
with a microcomputer.
C compiler package
This compiler should be used in combination with an optical assembler package and
device file.
<Precaution when using CC78K4 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Win-
dows, however, by using the Project Manager (included in assembler package) on
Windows.
Part number: µS××××CC78K4
Note
DF784046
This file contains information peculiar to the device.
Device file
This device file should be used in combination with an optional tool (RA78K4,
CC78K4, SM78K4, ID78K4-NS, and ID78K4).
Corresponding OS and host machine differ depending on the tool to be used with.
Part number: µS××××DF784046
CC78K4-L
This is a source file of functions configuring the object library included in the C
compiler package (CC78K4).
C library source file
This file is required to match the object library included in C compiler package to the
customer’s specifications.
The operating environment does not depend on the OS because this is a source file.
Part number: µS××××CC78K4-L
Note The DF784046 can be used commonly for all the RA78K4, CC78K4, SM78K4, ID78K4-NS, and ID78K4.
458
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APPENDIX A DEVELOPMENT TOOLS
Remark The ×××× part number differs depending on the host machine and operating system used.
µS××××SP78K4
××××
AB17
BB17
Host Machine
PC-9800 series,
IBM PC/AT compatibles
OS
Japanese Windows
English Windows
Supply Medium
CD-ROM
µS××××RA78K4
µS××××CC78K4
××××
AB13
BB13
AB17
BB17
3P17
3K17
Host Machine
OS
Japanese Windows
English Windows
Japanese Windows
Supply Medium
3.5-inch 2HD FD
PC-9800 series,
IBM PC/AT compatibles
CD-ROM
English Windows
TM
TM
HP9000 series 700
HP-UX
(Rel. 10.10)
TM
TM
SPARCstation
SunOS
(Rel. 4.1.4),
(Rel. 2.5.1)
TM
Solaris
µS××××DF784046
µS××××CC78K4-L
××××
AB13
BB13
3P16
3K13
3K15
Host Machine
OS
Supply Medium
PC-9800 series,
Japanese Windows
English Windows
3.5-inch 2HD FD
IBM PC/AT compatibles
HP9000 series 700
SPARCstation
HP-UX (Rel. 10.10)
SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1)
DAT
3.5-inch 2HD FD
1/4-inch CGMT
A.2 Flash Memory Writing Tools
Flash programmer dedicated to microcontrollers with on-chip flash memory.
Flashpro II (part number: FL-PR2)
Flashpro III (part number: FL-PR3, PG-FP3)
Flash programmer
Flash memory writing adapter used connected to the Flashpro II/Flashpro III.
• FA-80GC : 80-pin plastic QFP (GC-3B9 type)
FA-80GC
Flash memory writing adapter
Remark Flashpro II, Flashpro III, and FA-80GC are products of Naito Densei Machida Mfg. Co., Ltd.
Phone: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
User’s Manual U11719EJ3V1UD
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APPENDIX A DEVELOPMENT TOOLS
A.3 Debugging Tools
A.3.1 Hardware (1/2)
(1) When using the in-circuit emulator IE-78K4-NS
The in-circuit emulator serves to debug hardware and software when developing
IE-78K4-NS
application systems using a 78K/IV Series product. It corresponds to integrated
debugger (ID78K4-NS). This emulator should be used in combination with power
supply unit, emulation probe, and interface adapter which is required to connect this
emulator to the host machine.
In-circuit emulator
This adapter is used for supplying power from a receptacle of 100 V to 200 V AC.
IE-70000-MC-PS-B
Power supply unit
This adapter is required when using the PC-9800 Series computer (except notebook
type) as the IE-78K4-NS host machine (C bus supported).
IE-70000-98-IF-C
Interface adapter
This is PC card and interface cable required when using the PC-9800 Series
notebook-type computer as the IE-78K4-NS host machine.
IE-70000-CD-IF
PC card interface
This adapter is required when using the IBM PC/AT compatible computers as the
IE-78K4-NS host machine (ISA bus supported).
IE-70000-PC-IF-C
Interface adapter
Interface adapter required when using a PC that incorporates PCI bus as the host
machine for the IE-78K4-NS
IE-70000-PCI-IF-A
Interface adapter
This board emulates the operations of the peripheral hardware peculiar to a device.
It should be used in combination with an in-circuit emulator.
IE-784046-NS-EM1
Emulation board
This probe is used to connect the in-circuit emulator to the target system and is
designed for 80-pin plastic QFP (GC-3B9 type).
NP-80GC-TQ
NP-H80GC-TQ
Emulation probe
This conversion socket connects the NP-80GC-TQ or NP-H80GC-TQ to the target
system board designed to mount a 80-pin plastic QFP (GC-3B9 type).
TGC-080SBP
Conversion socket
(Refer to Figure
A-3)
Remarks 1. NP-80GC-TQ and NP-H80GC-TQ are products made by Naito Densei Machida Mfg.Co., Ltd.
For further information, contact Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-45-475-4191)
2. TGC-080SBP is a product made by Tokyo Eletech Corporation.
For further information, contact Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL: +81-3-3820-7112)
Osaka Electronics Department (TEL: +81-6-6244-6672)
3. The TGC-080SBP is sold individually.
460
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APPENDIX A DEVELOPMENT TOOLS
A.3.1 Hardware (2/2)
(2) When using the in-circuit emulator IE-784000-R
IE-784000-R
The IE-784000-R is an in-circuit emulator common to the 78K/IV Series, and is used in
In-circuit emulator
combination with IE-784000-R-EM and IE-784046-R-EM1, which are sold separately.
This in-circuit emulator debugs the connected host machine. An integrated debugger
(ID78K4) and device file (sold separately) are required to enable debugging in C
language and structured assembly language at the source program level. More
efficient debugging and program verification is possible with functions such as C0
TM
coverage. Connect to a host machine via Ethernet
adapter (sold separately) is required for connection.
or a dedicated bus. An interface
IE-70000-98-IF-C
Interface adapter
Interface adapter required when a PC-9800 series (except notebook type PC) is used
as the host machine for the IE-784000-R (C bus supported).
IE-70000-PC-IF-C
Interface adapter
Interface adapter required when using an IBM PC/AT compatible as the host machine
(ISA bus supported).
IE-78000-R-SV3
Interface adapter
Interface adapter and cable required when an EWS is used as the host machine for
the IE-784000-R. Connect to a board inside the IE-784000-R.
Note that 10Base-5 is supported as the Ethernet. A commercial conversion adapter is
required for other systems.
IE-784000-R-EM
Emulation board common to 78K/IV Series
IE-784046-R-EM1
Emulation board
Board to emulate peripheral hardware specific to device
IE-78K4-R-EX2
Conversion board for 80-pin packages required when using the IE-784046-R-EM1 on
IE-784000-R
Emulation probe conversion board
EP-78230GC-R
Emulation probe
Probe to connect the in-circuit emulator and the target system. For 80-pin plastic QFP
(GC-3B9 type).
EV-9200GC-80
Conversion socket
(Refer to Figures A-4
and A-5)
Conversion socket to connect the EP-78230GC-R and a target system board on which
an 80-pin plastic QFP (GC-3B9 type) can be mounted
Remark EV-9200GC-80 is sold in five units.
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APPENDIX A DEVELOPMENT TOOLS
A.3.2 Software
SM78K4
This system simulator is used to perform debugging at C source level or assembler
level while simulating the operation of the target system on a host machine.
This simulator runs on Windows.
System simulator
Use of the SM78K4 allows the execution of application logical testing and
performance testing on an independent basis from hardware development without
having to use an in-circuit emulator, thereby providing higher development efficiency
and software quality.
The SM78K4 should be used in combination with the optional device file (DF784046).
Part number: µS××××SM78K4
ID78K4-NS
This debugger is a control program to debug 78K/IV Series microcontrollers.
It adopts a graphical user interface, which is equivalent visually and operationally to
Windows. It also has an enhanced debugging function for C language programs, and
thus trace results can be displayed on screen in C-language level by using the
windows integration function which links a trace result with its source program,
disassembled display, and memory display. In addition, by incorporating function
modules such as task debugger and system performance analyzer, the efficiency of
debugging programs, which run on real-time OSs can be improved.
Integrated debugger
(supporting in-circuit emulator
IE-78K4-NS)
ID78K4
Integrated debugger
(supporting in-circuit emulator
IE-784000-R)
It should be used in combination with the optional device file (DF784046).
Part number: µS××××ID78K4-NS, µS××××ID78K4
Remark ×××× in the part number differs depending on the host machine and OS used.
µS××××SM78K4
µS××××ID78K4-NS
µS××××ID78K4
××××
AB13
BB13
AB17
BB17
Host Machine
OS
Japanese Windows
English Windows
Japanese Windows
English Windows
Supply Medium
3.5-inch 2HC FD
IBM PC/AT compatible
CD-ROM
462
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APPENDIX A DEVELOPMENT TOOLS
A.4 Cautions on Designing Target System
The connection condition diagrams for the emulation probe and conversion socket are shown below. Design the
system considering the shape of components, etc. to be mounted on the target system in accordance with this
configuration.
Figure A-2. Distance Between In-Circuit Emulator and Conversion Socket
In-circuit emulator
IE-78K4-NS
Target system
Emulation board
IE-784046-NS-EM1
CN2 connection
150 mmNote
Emulation probe
NP-80GC-TQ, NP-H80GC-TQ
CN2
Conversion socket
TGC-080SBP
CN1
Note 350 mm in case of the NP-H80GC-TQ.
User’s Manual U11719EJ3V1UD
463
APPENDIX A DEVELOPMENT TOOLS
Figure A-3. Target System Connection Conditions
Emulation probe
NP-80GC-TQ, NP-H80GC-TQ
Emulation board
IE-784046-NS-EM1
25 mm
50 mm
35 mm
10 mm
10 mm
Conversion socket
TGC-080SBP
Pin 1
35 mm
18.7 mm
60 mm
Target system
Remarks 1. NP-80GC-TQ and NP-H80GC-TQ are products made by Naito Densei Machida Mfg. Co., Ltd.
2. TGC-080SBP is a product made by Tokyo Eletech Corporation.
464
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APPENDIX A DEVELOPMENT TOOLS
A.5 Deminsions of Conversion Socket (EV-9200GC-80) and Recommended Board Mounting Pattern
Figure A-4. Dimensions of EV-9200GC-80 (reference)
A
B
M
N
E
O
F
EV-9200GC-80
1
No.1 pin index
P
G
H
I
EV-9200GC-80-G1E
ITEM
A
MILLIMETERS
18.0
14.4
14.4
18.0
4-C 2.0
0.8
INCHES
0.709
0.567
0.567
0.709
4-C 0.079
0.031
0.236
0.63
B
C
D
E
F
G
H
I
6.0
16.0
18.7
6.0
0.736
0.236
0.63
J
K
16.0
18.7
8.2
L
0.736
0.323
0.315
0.098
0.079
0.014
0.091
0.059
M
N
O
P
8.0
2.5
2.0
Q
R
0.35
2.3
S
1.5
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APPENDIX A DEVELOPMENT TOOLS
Figure A-5. Recommended Board Mounting Pattern of EV-9200GC-80 (reference)
G
J
K
L
C
B
A
EV-9200GC-80-P1E
ITEM
MILLIMETERS
INCHES
0.776
A
B
C
D
E
F
G
H
I
19.7
15.0
0.591
+0.001
+0.003
–0.002
0.65 0.02 × 19=12.35 0.05 0.026
× 0.748=0.486
× 0.748=0.486
–0.002
+0.001
–0.002
+0.003
–0.002
0.65 0.02 × 19=12.35 0.05 0.026
15.0
0.591
0.776
0.236
0.236
0.014
19.7
+0.003
–0.002
6.0 0.05
6.0 0.05
0.35 0.02
2.36 0.03
2.3
+0.003
–0.002
+0.001
–0.001
+0.001
–0.002
J
0.093
0.091
0.062
K
L
+0.001
–0.002
1.57 0.03
Caution Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"Semiconductor Device Mount Manual" website
(http://www.necel.com/pkg/en/mount/index.html).
466
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APPENDIX B EMBEDDED SOFTWARE
For efficient development and maintenance of the µPD784054, the following embedded products are available.
RX78K4
RX78K4 is a real-time OS conforming to the µITRON specifications.
Tool (configurator) for generating nucleus of RX78K4 and plural information tables
is supplied.
Real-time OS
Used in combination with an optional assembler package (RA78K4) and device file
(DF784046).
<Precaution when using RX78K4 in PC environment>
The real-time OS is a DOS-based application. It should be used in the DOS Prompt
when using in Windows.
Part number: µS××××RX78K4
Caution When purchasing the RX78K4, fill in the purchase application form in advance and sign the User
Agreement.
Remark ×××× and ∆∆∆ in the part number differ depending on the host machine and OS used.
µS××××RX78K4-∆∆∆∆
∆∆∆∆
Product Outline
Evaluation object
Maximum Number for Use in Mass Production
Do not use for mass-produced product.
001
100K
001M
010M
S01
Mass-production object
0.1 million units
1 million units
10 million units
Source program
Host Machine
Source program for mass-produced object
××××
AA13
AB13
BB13
3P16
3K13
3K15
OS
Supply Medium
3.5-inch 2HD FD
Note
Note
PC-9800 Series
Windows (Japanese version)
Windows (Japanese version)
IBM PC/AT compatibles
3.5-inch 2HC FD
Note
Windows (English version)
HP-UX (Rel. 9.05)
HP9000 Series 700
SPARCstation
DAT (DDS)
SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1)
3.5-inch 2HC FD
1/4-inch CGMT
Note Can also be operated in DOS environment.
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APPENDIX C REGISTER INDEX
[A]
ADCR0
ADCR0H
ADCR1
ADCR1H
ADCR2
ADCR2H
ADCR3
ADCR3H
ADCR4
ADCR4H
ADCR5
ADCR5H
ADCR6
ADCR6H
ADCR7
ADCR7H
ADIC
: A/D Conversion Result Register 0 ..........................................................................................
: A/D Conversion Result Register 0H .......................................................................................
: A/D Conversion Result Register 1 ..........................................................................................
: A/D Conversion Result Register 1H .......................................................................................
: A/D Conversion Result Register 2 ..........................................................................................
: A/D Conversion Result Register 2H .......................................................................................
: A/D Conversion Result Register 3 ..........................................................................................
: A/D Conversion Result Register 3H .......................................................................................
: A/D Conversion Result Register 4 ..........................................................................................
: A/D Conversion Result Register 4H .......................................................................................
: A/D Conversion Result Register 5 ..........................................................................................
: A/D Conversion Result Register 5H .......................................................................................
: A/D Conversion Result Register 6 ..........................................................................................
: A/D Conversion Result Register 6H .......................................................................................
: A/D Conversion Result Register 7 ..........................................................................................
: A/D Conversion Result Register 7H .......................................................................................
: Interrupt Control Register ........................................................................................................
: A/D Converter Mode Register .................................................................................................
: Asynchronous Serial Interface Mode Register .......................................................................
: Asynchronous Serial Interface Mode Register 2....................................................................
: Asynchronous Serial Interface Status Register .....................................................................
: Asynchronous Serial Interface Status Register 2 ..................................................................
220
221
220
221
220
221
220
221
220
221
220
221
220
221
220
221
290
218
241
241
243
243
ADM
ASIM
ASIM2
ASIS
ASIS2
[B]
BRGC
BRGC2
BW
: Baud Rate Generator Control Register ..................................................................................
: Baud Rate Generator Control Register 2 ...............................................................................
: Bus Width Specification Register............................................................................................
262
262
362
[C]
CC00
: Capture/Compare Register 00 ................................................................................................
: Capture/Compare Register 01 ................................................................................................
: Capture/Compare Register 02 ................................................................................................
: Capture/Compare Register 03 ................................................................................................
: Compare Register 10 ..............................................................................................................
: Compare Register 11 ..............................................................................................................
: Compare Register 40 ..............................................................................................................
: Compare Register 41 ..............................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Clocked Serial Interface Mode Register 1..............................................................................
: Clocked Serial Interface Mode Register 2..............................................................................
147
147
147
147
171
171
194
194
289
289
289
289
289
290
254
254
CC01
CC02
CC03
CM10
CM11
CM40
CM41
CMIC10
CMIC11
CMIC40
CMIC41
CSIIC1
CSIIC2
CSIM1
CSIM2
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APPENDIX C REGISTER INDEX
[I]
IEF1
IEF2
IMC
: Interrupt Valid Edge Flag Register 1 ......................................................................................
: Interrupt Valid Edge Flag Register 2 ......................................................................................
: Interrupt Mode Control Register..............................................................................................
: Internal Memory Size Select Register ....................................................................................
: External Interrupt Mode Register 0.........................................................................................
: External Interrupt Mode Register 1.........................................................................................
: In-Service Priority Register .....................................................................................................
276
277
294
385
274
275
293
IMS
INTM0
INTM1
ISPR
[M]
MK0
MK0H
MK0L
MK1
MK1H
MK1L
MM
: Interrupt Mask Register 0 ........................................................................................................
: Interrupt Mask Register 0H .....................................................................................................
: Interrupt Mask Register 0L ......................................................................................................
: Interrupt Mask Register 1 ........................................................................................................
: Interrupt Mask Register 1H .....................................................................................................
: Interrupt Mask Register 1L ......................................................................................................
292
292
292
292
292
292
: Memory Extension Mode Register .......................................................................................... 341, 347
[N]
NPC
: Noise Protection Control Register ..........................................................................................
277
[O]
OSTS
OVIC0
OVIC1
OVIC4
: Oscillation Stabilization Time Specification Register ............................................................. 81, 369
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
288
288
288
[P]
P0
: Port 0 ........................................................................................................................................
: Port 1 ........................................................................................................................................
: Port 2 ........................................................................................................................................
89
94
P1
P2
98, 99
P3
: Port 3 ........................................................................................................................................ 104, 105
P4
: Port 4 ........................................................................................................................................
: Port 5 ........................................................................................................................................
: Port 6 ........................................................................................................................................
: Port 7 ........................................................................................................................................
: Port 8 ........................................................................................................................................
: Port 9 ........................................................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Port 0 Mode Register ..............................................................................................................
: Port 1 Mode Register ..............................................................................................................
: Port 2 Mode Register ..............................................................................................................
109
115
121
127
128
129
288
288
288
288
288
288
288
90
P5
P6
P7
P8
P9
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PM0
PM1
PM2
95
100
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APPENDIX C REGISTER INDEX
PM3
: Port 3 Mode Register ..............................................................................................................
: Port 4 Mode Register ..............................................................................................................
: Port 5 Mode Register ..............................................................................................................
: Port 6 Mode Register ..............................................................................................................
: Port 9 Mode Register ..............................................................................................................
: Port 2 Mode Control Register .................................................................................................
: Port 3 Mode Control Register .................................................................................................
: Port 9 Mode Control Register .................................................................................................
: Port Read Control Register .....................................................................................................
105
110
116
122
132
100
106
132
137
PM4
PM5
PM6
PM9
PMC2
PMC3
PMC9
PRDC
PRM
: Prescaler Mode Register ......................................................................................................... 150, 174
PRM4
PUOH
PUOL
PWC1
PWC2
: Prescaler Mode Register 4......................................................................................................
: Pull-Up Resistor Option Register H ........................................................................................
196
135
: Pull-Up Resistor Option Register L.............................................................................. 92, 113, 119, 125
: Programmable Wait Control Register 1 ..................................................................................
: Programmable Wait Control Register 2 ..................................................................................
348
350
[R]
RXB
RXB2
: Serial Receive Buffer: UART0 ...............................................................................................
: Serial Receive Buffer: UART2 ...............................................................................................
240
240
[S]
SERIC
SERIC2
SIO1
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
: Serial Shift Register: IOE1 .....................................................................................................
: Serial Shift Register: IOE2 .....................................................................................................
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
289
289
253
253
289
290
SIO2
SRIC
SRIC2
STBC
STIC
: Standby Control Register ........................................................................................................ 80, 367
: Interrupt Control Register ........................................................................................................
: Interrupt Control Register ........................................................................................................
289
290
STIC2
[T]
TM0
: Timer Register 0 ......................................................................................................................
: Timer Register 1 ......................................................................................................................
: Timer Register 4 ......................................................................................................................
147
171
194
TM1
TM4
TMC
TMC4
TOC0
TOC1
TUM0
TXS
: Timer Mode Control Register .................................................................................................. 149, 173
: Timer Mode Control Register 4...............................................................................................
: Timer Output Control Register 0 .............................................................................................
: Timer Output Control Register 1 .............................................................................................
: Timer Unit Mode Register 0 ....................................................................................................
: Serial Transmit Shift Register: UART0..................................................................................
: Serial Transmit Shift Register: UART2..................................................................................
195
149
173
172
240
240
TXS2
[W]
WDM
: Watchdog Timer Mode Register ............................................................................................. 210, 295
User’s Manual U11719EJ3V1UD
470
APPENDIX D REVISION HISTORY
The revision history is described below. The “Applied to” column indicates the chapters in each edition.
(1/2)
Edition
Major Revisions from Previous Edition
Applied to
Throughout
2nd edition
Change of µPD784054 from “under development” to “development completed”.
Addition of the following products to the relevant products:
µPD784054(A), 784054(A1), 784054(A2)
Change of 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM.
CHAPTER 1 GENERAL
Change of the minimum value of the supply voltage (VDD) from 4.0 V to 4.5 V.
Addition of 1.3 Quality Grades.
Addition of 1.9 Differences between µPD784054 and µPD784054(A).
Additionof1.10DifferencesbetweenµPD784054(A), 784054(A1), and784054(A2).
Addition of the functional description of the CLKOUT pin.
CHAPTER 2 PIN FUNCTIONS
CHAPTER 7 TIMER 0
Addition of description in (2) Capture/compare registers (CC00 through CC03).
Addition of caution when the timer output is enabled while the active level is changed.
Addition of caution when the active level of the timer output is changed.
Addition of caution when the timer output is enabled while the active level is changed.
Addition of caution when the active level of the timer output is changed.
CHAPTER 8 TIMER 1
CHAPTER 10 WATCHDOG
TIMER FUNCTION
Change of the description of <5> in (2) of 10.4.1 General cautions on use of
watchdog timer from “If the STOP mode or IDLE mode is entered as the result of
an inadvertent program loop” to “If the STOP mode, HALT mode, or IDLE mode is
entered as the result of an inadvertent program loop”.
CHAPTER 12 ASYNCHRO-
NOUS SERIAL INTERFACE/3-
WIRE SERIAL I/O
Addition of caution and calculating method of the wait time if the reception completion
interrupt is disabled when a reception error occurs.
CHAPTER 14 INTERRUPT
FUNCTIONS
Change of instructions in 14.9 When Interrupt Request and Macro Service Are
Temporarily Held Pending.
Change of description from “The watchdog timer must not be used to release the CHAPTER 16 STANDBY
standby mode (STOP or IDLE mode)” to “The watchdog timer must not be used to FUNCTION
release the standby mode (STOP, HALT, or IDLE mode)”.
Deletion of watchdog timer of “Non-maskable interrupt request (NMI pin input/
watchdog timer)”.
Addition of Caution concerning the malfunction that causes a wait for the oscillation
stabilization time when the IDLE mode is released.
Addition of note on output of CLKOUT pin.
CHAPTER 20 CAUTIONS ON
USING DEVELOPMENT
TOOLS
General revision for supporting IE-78K4-NS.
APPENDIX A DEVELOPMENT
TOOLS
APPENDIX B EMBEDDED
SOFTWARE
Change of target host machines.
Change of versions of OSs to be supported.
User’s Manual U11719EJ3V1UD
471
APPENDIX D REVISION HISTORY
(2/2)
Edition
Major Revisions from Previous Edition
Applied to
3rd edition • Completion of development of the following product
µPD78F4046
CHAPTER 1 GENERAL
• Update of 78K/IV Series Product Lineup
Addition of description on BWD pin in Table 2-4 I/O Circuit Type of Each Pin and
CHAPTER 2 PIN
FUNCTIONS
Recommended Processing of Unused Pins
Addition of cautions on start bit during UART transmission to 12.5 Cautions
CHAPTER 12 ASYNCHRO-
NOUS SERIAL INTERFACE/
3-WIRE SERIAL I/O
• Modification of Figure 16-1 Diagram of Standby Mode Transition
• Modification of description in 16.6 (5) A/D converter
CHAPTER 16 STANDBY
FUNCTION
• Addition of description on Flashpro III
CHAPTER 18
• Addition of cautions in 18.3 Cautions
µPD78F4046
Addition of chapter
Addition of chapter
Addition of chapter
Addition of chapter
CHAPTER 20 ELECTRICAL
SPECIFICATIONS
(µPD784054)
CHAPTER 21 ELECTRICAL
SPECIFICATIONS
(µPD784054(A))
CHAPTER 22 ELECTRICAL
SPECIFICATIONS
(µPD784054(A1)
CHAPTER 23 ELECTRICAL
SPECIFICATIONS
(µPD784054(A2))
Addition of chapter
Addition of chapter
Addition of chapter
CHAPTER 24 TIMING
CHARTS
CHAPTER 25 PACKAGE
DRAWING
CHAPTER 26
RECOMMENDED
SOLDERING CONDITIONS
• Addition of description on host machines and OSs
• Addition of SP78K4 to A.1 Language Processing Software, modification of
description in Remark
APPENDIXADEVELOPMENT
TOOLS
• Addition of description on Flashpro III in Remark in A.2 Flash Memory Writing
Tools
• Addition and modification of description in A.3.1 Hardware
• Modification of description in Remark in A.3.2 Software
• Addition of A.4 Cautions on Designing Target System
Modification of description
APPENDIX B EMBEDDED
SOFTWARE
3rd edition Modification of 1.2 Ordering Information
(Modification Modification of 1.3 Quality Grades
CHAPTER 1 GENERAL
Version)
Addition of Table 26-1. Surface Mounting Type Soldering Conditions (2)
CHAPTER 26
RECOMMENDED
SOLDERING CONDITIONS
472
User’s Manual U11719EJ3V1UD
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