UPD789072MC-XXX-5A4 [NEC]
Microcontroller, 8-Bit, MROM, 5MHz, MOS, PDSO30, 0.300 INCH, PLASTIC, SSOP-30;
| 型号： | UPD789072MC-XXX-5A4 |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, MOS, PDSO30, 0.300 INCH, PLASTIC, SSOP-30 微控制器 光电二极管 |
| 文件： | 总211页 (文件大小：1482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
µPD789074 Subseries
8-Bit Single-Chip Microcontrollers
µPD789071
µPD789072
µPD789074
µPD78F9076
Document No. U14801EJ2V0UD00 (2nd edition)
Date Published January 2002 N CP(K)
2000, 2002
©
Printed in Japan
[MEMO]
2
User's Manual U14801EJ2V0UD
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM and FIP are trademarks of NEC Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun-Microsystems, Inc.
3
User's Manual U14801EJ2V0UD
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µPD78F9076
The customer must judge the need for license: µPD789071, 789072, 789074
•
The information in this document is current as of September, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
4
User's Manual U14801EJ2V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics (France) S.A.
Vélizy-Villacoublay, France
Tel: 01-3067-58-00
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 01-3067-58-99
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Representación en España
Madrid, Spain
Tel: 091-504-27-87
Fax: 091-504-28-60
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
NEC Electronics Italiana S.R.L.
Milano, Italy
Tel: 02-66 75 41
•
Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
Fax: 250-3583
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
•
Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.12
5
User's Manual U14801EJ2V0UD
MAJOR REVISIONS IN THIS EDITION
Page
Description
Throughout
Status of µPD789071, 789072, 789074, and 78F9076 changed from under development to
development complete.
pp. 28 and 29 Modification of description of VPP pin connection
p. 84
Modification of Caution on rewriting CR90 in 6.4.1 Operation as timer interrupt
P.131
p. 168
Addition of description on reading receive data of UART
Addition of Note on unused pins to Table 13-2 Communication Mode
pp. 172 and
173
Addition of Note and Remark to Figures 13-2 Flashpro III Connection Example in 3-Wire
Serial I/O Mode, 13-3 Flashpro III Connection Example in UART Mode, and 13-4 Flashpro III
Connection Example in Pseudo 3-Wire Mode
p. 171
Value of UART modified in Table 13-4 Setting Example with PG-FP3
pp. 185 to 197 Addition of CHAPTER 15 ELECTRICAL SPECIFICATIONS
p. 198
p. 199
Addition of CHAPTER 16 PACKAGE DRAWING
Addition of CHAPTER 17 RECOMMENDED SOLDERING CONDITIONS
pp. 200 to 205 Overall modification of descriptions in APPENDIX A DEVELOPMENT TOOLS
Deletion of Embedded Software
The mark shows major revised points.
6
User's Manual U14801EJ2V0UD
INTRODUCTION
Readers
This manual is intended for user engineers who wish to gain an understanding of the
functions of the µPD789074 Subseries in order to design and develop its application
systems and programs.
Purpose
This manual is intended to give users an understanding of the functions described in
the Organization below.
Organization
Two manuals are available for the µPD789074 Subseries: this manual and the
Instruction Manual (common to the 78K/0S Series).
µPD789074 Subseries
78K/0S Series
User's Manual
Instructions
User's Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupts
• Instruction set
• Instruction description
• Other internal peripheral functions
• Electrical specifications
How to Read This Manual
It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
◊ To understand the overall functions of the µPD789074 Subseries
→ Read this manual in the order of the CONTENTS.
◊ How to read register formats
→ The name of a bit whose number is enclosed with <> is reserved in the
assembler and is defined in the C compiler by the header file sfrbit.h.
◊ To learn the detailed functions of a register whose register name is known
→ See APPENDIX B REGISTER INDEX.
◊ To learn details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User's Manual (U11047E) available
separately.
◊ To learn the electrical specifications of the µPD789074 Subserires
→ Refer to CHAPTER 15 ELECTRICAL SPECIFICATIONS.
Conversions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation: ××× (Overscore over pin or signal name)
Note:
Footnote for item marked Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
7
User's Manual U14801EJ2V0UD
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CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................18
1.1 Features.......................................................................................................................................18
1.2 Applications................................................................................................................................18
1.3 Ordering Information .................................................................................................................18
1.4 Pin Configuration (Top View)....................................................................................................19
1.5 78K/0S Series Lineup.................................................................................................................20
1.6 Block Diagram ............................................................................................................................23
1.7 Overview of Functions...............................................................................................................24
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................25
2.1 Pin Function List ........................................................................................................................25
2.2 Description of Pin Functions ....................................................................................................27
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
P00 to P07 (Port 0)......................................................................................................................27
P10 to P15 (Port 1)......................................................................................................................27
P20 to P27 (Port 2)......................................................................................................................27
P30, P31 (Port 3).........................................................................................................................28
RESET ........................................................................................................................................28
X1, X2..........................................................................................................................................28
VDD...............................................................................................................................................28
VSS...............................................................................................................................................28
VPP (µPD78F9076 only)...............................................................................................................28
IC (mask ROM version only) .......................................................................................................29
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................30
CHAPTER 3 CPU ARCHITECTURE ......................................................................................................32
3.1 Memory Space ............................................................................................................................32
3.1.1
3.1.2
3.1.3
3.1.4
Internal program memory space..................................................................................................36
Internal data memory (internal high-speed RAM) space.............................................................36
Special function register (SFR) area ...........................................................................................36
Data memory addressing ............................................................................................................37
3.2 Processor Registers...................................................................................................................41
3.2.1
3.2.2
3.2.3
Control registers..........................................................................................................................41
General-purpose registers...........................................................................................................44
Special function registers (SFRs)................................................................................................45
3.3 Instruction Address Addressing...............................................................................................48
3.3.1
3.3.2
3.3.3
3.3.4
Relative addressing.....................................................................................................................48
Immediate addressing.................................................................................................................49
Table indirect addressing ............................................................................................................50
Register addressing ....................................................................................................................50
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User's Manual U14801EJ2V0UD
3.4 Operand Address Addressing ..................................................................................................51
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
Direct addressing ........................................................................................................................51
Short direct addressing ...............................................................................................................52
Special function register (SFR) addressing.................................................................................53
Register addressing ....................................................................................................................54
Register indirect addressing........................................................................................................55
Based addressing .......................................................................................................................56
Stack addressing.........................................................................................................................56
CHAPTER 4 PORT FUNCTIONS ...........................................................................................................57
4.1 Port Functions............................................................................................................................57
4.2 Port Configuration .....................................................................................................................59
4.2.1
4.2.2
4.2.3
4.2.4
Port 0...........................................................................................................................................59
Port 1...........................................................................................................................................60
Port 2...........................................................................................................................................61
Port 3...........................................................................................................................................65
4.3 Port Function Control Registers...............................................................................................66
4.4 Operation of Port Functions .....................................................................................................69
4.4.1
4.4.2
4.4.3
Writing to I/O port ........................................................................................................................69
Reading from I/O port..................................................................................................................69
Arithmetic operation of I/O port ...................................................................................................69
CHAPTER 5 CLOCK GENERATOR ......................................................................................................70
5.1 Clock Generator Functions.......................................................................................................70
5.2 Clock Generator Configuration.................................................................................................70
5.3 Clock Generator Control Register............................................................................................71
5.4 System Clock Oscillators ..........................................................................................................72
5.4.1
5.4.2
System clock oscillator................................................................................................................72
Frequency divider........................................................................................................................74
5.5 Clock Generator Operation .......................................................................................................75
5.6 Changing Setting of CPU Clock................................................................................................76
5.6.1
5.6.2
Time required for switching CPU clock .......................................................................................76
Switching CPU clock ...................................................................................................................76
CHAPTER 6 16-BIT TIMER 90 ..............................................................................................................77
6.1 16-Bit Timer 90 Functions .........................................................................................................77
6.2 16-Bit Timer 90 Configuration...................................................................................................77
6.3 16-Bit Timer 90 Control Registers ............................................................................................80
6.4 16-Bit Timer 90 Operation .........................................................................................................84
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Operation as timer interrupt.........................................................................................................84
Operation as timer output............................................................................................................86
Capture operation........................................................................................................................87
16-bit timer counter 90 readout ...................................................................................................88
Buzzer output operation..............................................................................................................89
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User's Manual U14801EJ2V0UD
CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80 ...............................................................................90
7.1 Functions of 8-Bit Timer/Event Counter 80 .............................................................................90
7.2 8-Bit Timer/Event Counter 80 Configuration ...........................................................................91
7.3 8-Bit Timer/Event Counter 80 Control Registers.....................................................................92
7.4 Operation of 8-Bit Timer/Event Counter 80 .............................................................................94
7.4.1
7.4.2
7.4.3
7.4.4
Operation as interval timer ..........................................................................................................94
Operation as external event counter ...........................................................................................96
Operation as square-wave output ...............................................................................................97
Operation as PWM output...........................................................................................................99
7.5 Notes on Using 8-Bit Timer/Event Counter 80 ......................................................................100
CHAPTER 8 WATCHDOG TIMER........................................................................................................102
8.1 Watchdog Timer Functions.....................................................................................................102
8.2 Watchdog Timer Configuration ..............................................................................................103
8.3 Watchdog Timer Control Registers........................................................................................104
8.4 Watchdog Timer Operation.....................................................................................................106
8.4.1
8.4.2
Operation as watchdog timer ....................................................................................................106
Operation as interval timer ........................................................................................................107
CHAPTER 9 SERIAL INTERFACE 20.................................................................................................108
9.1 Serial Interface 20 Functions ..................................................................................................108
9.2 Serial Interface 20 Configuration............................................................................................108
9.3 Serial Interface 20 Control Registers .....................................................................................112
9.4 Serial Interface 20 Operation...................................................................................................119
9.4.1
9.4.2
9.4.3
Operation stop mode.................................................................................................................119
Asynchronous serial interface (UART) mode ............................................................................120
3-wire serial I/O mode ...............................................................................................................133
CHAPTER 10 INTERRUPT FUNCTIONS.............................................................................................143
10.1 Interrupt Function Types.........................................................................................................143
10.2 Interrupt Sources and Configuration .....................................................................................143
10.3 Interrupt Function Control Registers.....................................................................................146
10.4 Interrupt Processing Operation ..............................................................................................151
10.4.1
10.4.2
10.4.3
10.4.4
Non-maskable interrupt request acknowledgement operation..................................................151
Maskable interrupt request acknowledgement operation..........................................................153
Multiple interrupt servicing.........................................................................................................155
Interrupt request reserve...........................................................................................................157
CHAPTER 11 STANDBY FUNCTION...................................................................................................158
11.1 Standby Function and Configuration.....................................................................................158
11.1.1
11.1.2
Standby function........................................................................................................................158
Standby function control register...............................................................................................159
11.2 Operation of Standby Function...............................................................................................160
11.2.1
HALT mode ...............................................................................................................................160
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User's Manual U14801EJ2V0UD
11.2.2
STOP mode...............................................................................................................................162
CHAPTER 12 RESET FUNCTION........................................................................................................164
CHAPTER 13 µPD78F9076 ...................................................................................................................167
13.1 Flash Memory Programming...................................................................................................168
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
Selecting communication mode ................................................................................................168
Function of flash memory programming....................................................................................169
Flashpro III connection example ...............................................................................................169
Setting Example with Flashpro III (PG-FP3) .............................................................................171
On-board pin connections.........................................................................................................172
CHAPTER 14 INSTRUCTION SET OVERVIEW .................................................................................175
14.1 Operation ..................................................................................................................................175
14.1.1
14.1.2
14.1.3
Operand identifiers and description methods............................................................................175
Description of "Operation" column ............................................................................................176
Description of "Flag" column .....................................................................................................176
14.2 Operation List...........................................................................................................................177
14.3 Instructions Listed by Addressing Type................................................................................182
CHAPTER 15 ELECTRICAL SPECIFICATIONS .................................................................................185
CHAPTER 16 PACKAGE DRAWING...................................................................................................198
CHAPTER 17 RECOMMENDED SOLDERING CONDITIONS ...........................................................199
APPENDIX A DEVELOPMENT TOOLS...............................................................................................200
A.1 Software Package.....................................................................................................................202
A.2 Language Processing Software..............................................................................................202
A.3 Control Software ......................................................................................................................203
A.4 Flash Memory Writing Tools...................................................................................................204
A.5 Debugging Tools (Hardware)..................................................................................................204
A.6 Debugging Tools (Software) ...................................................................................................205
APPENDIX B REGISTER INDEX .........................................................................................................206
B.1 Register Name Index (Alphabetic Order)...............................................................................206
B.2 Register Symbol Index (Alphabetic Order)............................................................................208
APPENDIX C REVISION HISTORY......................................................................................................210
12
User's Manual U14801EJ2V0UD
LIST OF FIGURES (1/3)
Figure No.
Title
Page
2-1
Pin I/O Circuits...............................................................................................................................................31
3-1
Memory Map (µPD789071) ...........................................................................................................................32
Memory Map (µPD789072) ...........................................................................................................................33
Memory Map (µPD789074) ...........................................................................................................................34
Memory Map (µPD78F9076) .........................................................................................................................35
Data Memory Addressing (µPD789071)........................................................................................................37
Data Memory Addressing (µPD789072)........................................................................................................38
Data Memory Addressing (µPD789074)........................................................................................................39
Data Memory Addressing (µPD78F9076)......................................................................................................40
Program Counter Configuration.....................................................................................................................41
Program Status Word Configuration..............................................................................................................41
Stack Pointer Configuration...........................................................................................................................43
Data to Be Saved to Stack Memory...............................................................................................................43
Data to Be Restored from Stack Memory ......................................................................................................43
General-Purpose Register Configuration.......................................................................................................44
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
Port Types .....................................................................................................................................................57
Block Diagram of P00 to P07.........................................................................................................................59
Block Diagram of P10 to P15.........................................................................................................................60
Block Diagram of P20....................................................................................................................................61
Block Diagram of P21....................................................................................................................................62
Block Diagram of P22 to P26.........................................................................................................................63
Block Diagram of P27....................................................................................................................................64
Block Diagram of P30 and P31......................................................................................................................65
Format of Port Mode Register .......................................................................................................................66
Format of Pull-up Resistor Option Register 0................................................................................................67
Format of Pull-up Resistor Option Register B2..............................................................................................68
5-1
5-2
5-3
5-4
5-5
Block Diagram of Clock Generator ................................................................................................................70
Format of Processor Clock Control Register .................................................................................................71
External Circuit of System Clock Oscillator ...................................................................................................72
Example of Incorrect Resonator Connection ................................................................................................73
Switching Between System Clock and CPU Clock........................................................................................76
6-1
6-2
6-3
6-4
6-5
6-6
6-7
Block Diagram of 16-Bit Timer 90..................................................................................................................78
Format of 16-Bit Timer Mode Control Register 90.........................................................................................81
Format of Buzzer Output Control Register 90 ...............................................................................................82
Format of Port Mode Register 3 ....................................................................................................................83
Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation.........................................84
Timing of Timer Interrupt Operation...............................................................................................................85
Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation ...........................................86
13
User's Manual U14801EJ2V0UD
LIST OF FIGURES (2/3)
Figure No.
Title
Page
6-8
Timer Output Timing......................................................................................................................................86
Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation ...................................................87
Capture Operation Timing (with Both Edges of CPT90 Pin Specified)..........................................................87
16-Bit Timer Counter 90 Readout Timing......................................................................................................88
Settings of Buzzer Output Control Register 90 for Buzzer Output Operation................................................89
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
Block Diagram of 8-Bit Timer/Event Counter 80............................................................................................91
Format of 8-Bit Timer Mode Control Register 80...........................................................................................92
Format of Port Mode Register 2 ....................................................................................................................93
Interval Timer Operation Timing ....................................................................................................................95
External Event Counter Operation Timing (with Rising Edge Specified).......................................................96
Square-Wave Output Timing .........................................................................................................................98
PWM Output Timing ......................................................................................................................................99
Start Timing of 8-Bit Timer Counter 80........................................................................................................100
External Event Counter Operation Timing...................................................................................................100
8-1
8-2
8-3
Block Diagram of Watchdog Timer..............................................................................................................103
Format of Watchdog Timer Clock Selection Register..................................................................................104
Format of Watchdog Timer Mode Register..................................................................................................105
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
Block Diagram of Serial Interface 20...........................................................................................................109
Block Diagram of Baud Rate Generator 20 .................................................................................................110
Format of Serial Operation Mode Register 20.............................................................................................112
Format of Asynchronous Serial Interface Mode Register 20.......................................................................113
Format of Asynchronous Serial Interface Status Register 20......................................................................115
Format of Baud Rate Generator Control Register 20 ..................................................................................116
Format of Asynchronous Serial Interface Transmit/Receive Data...............................................................126
Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................128
Asynchronous Serial Interface Reception Completion Interrupt Timing ......................................................129
Receive Error Timing...................................................................................................................................130
3-Wire Serial I/O Mode Timing ...................................................................................................................136
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
Basic Configuration of Interrupt Function ....................................................................................................145
Format of Interrupt Request Flag Register ..................................................................................................147
Format of Interrupt Mask Flag Register.......................................................................................................148
Format of External Interrupt Mode Register 0 .............................................................................................149
Program Status Word Configuration............................................................................................................150
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement...................................152
Timing of Non-Maskable Interrupt Request Acknowledgement...................................................................152
Acknowledgement of Non-Maskable Interrupt Request ..............................................................................152
Interrupt Request Acknowledgement Processing Algorithm........................................................................154
10-10 Interrupt Request Acknowledgement Timing (Example of MOV A,r)...........................................................155
14
User's Manual U14801EJ2V0UD
LIST OF FIGURES (3/3)
Figure No.
Title
Page
10-11 Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Set at Last Clock During
Instruction Execution)..................................................................................................................................155
10-12 Example of Multiple Interrupts .....................................................................................................................156
11-1
11-2
11-3
11-4
11-5
Format of Oscillation Stabilization Time Selection Register ........................................................................159
Releasing HALT Mode by Interrupt .............................................................................................................160
Releasing HALT Mode by RESET Input......................................................................................................161
Releasing STOP Mode by Interrupt.............................................................................................................163
Releasing STOP Mode by RESET Input .....................................................................................................163
12-1
12-2
12-3
12-4
Block Diagram of Reset Function ................................................................................................................164
Reset Timing by RESET Input.....................................................................................................................165
Reset Timing by Watchdog Timer Overflow ................................................................................................165
Reset Timing by RESET Input in STOP Mode ............................................................................................165
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
Format of Communication Mode Selection..................................................................................................168
Flashpro III Connection Example in 3-Wire Serial I/O Mode .......................................................................169
Flashpro III Connection Example in UART Mode........................................................................................170
Flashpro III Connection Example in Pseudo 3-Wire Mode..........................................................................170
VPP Pin Connection Example.......................................................................................................................172
Signal Conflict (Serial Interface Input Pin)...................................................................................................173
Malfunction of Another Device.....................................................................................................................173
Signal Conflict (RESET Pin) ........................................................................................................................174
A-1
Development Tools......................................................................................................................................201
15
User's Manual U14801EJ2V0UD
LIST OF TABLES (1/2)
Table No.
Title
Page
2-1
Types of Pin I/O Circuits and Recommended Connection of Unused Pins...................................................30
3-1
3-2
3-3
Internal ROM Capacity ..................................................................................................................................36
Vector Table ..................................................................................................................................................36
Special Function Registers ...........................................................................................................................46
4-1
4-2
4-3
Port Functions ...............................................................................................................................................58
Configuration of Port......................................................................................................................................59
Port Mode Register and Output Latch Settings for Using Alternate Functions..............................................67
5-1
5-2
Configuration of Clock Generator..................................................................................................................70
Maximum Time Required for Switching CPU Clock.......................................................................................76
6-1
6-2
6-3
6-4
Configuration of 16-Bit Timer 90....................................................................................................................77
Interval Time of 16-Bit Timer 90 ....................................................................................................................84
Settings of Capture Edge ..............................................................................................................................87
Buzzer Frequency of 16-Bit Timer 90............................................................................................................89
7-1
7-2
7-3
7-4
7-5
Interval Time of 8-Bit Timer/Event Counter 80 ..............................................................................................90
Square-Wave Output Range of 8-Bit Timer/Event Counter 80......................................................................90
Configuration of 8-Bit Timer/Event Counter 80..............................................................................................91
Interval Time of 8-Bit Timer/Event Counter 80 ..............................................................................................94
Square-Wave Output Range of 8-Bit Timer/Event Counter...........................................................................97
8-1
8-2
8-3
8-4
8-5
Inadvertent Loop Detection Time of Watchdog Timer .................................................................................102
Interval Time................................................................................................................................................102
Configuration of Watchdog Timer................................................................................................................103
Inadvertent Loop Detection Time of Watchdog Timer .................................................................................106
Interval Generated Using Interval Timer......................................................................................................107
9-1
9-2
9-3
9-4.
9-5
9-6.
9-7
Configuration of Serial Interface 20.............................................................................................................108
Serial Interface 20 Operating Mode Settings...............................................................................................114
Example of Relationship Between System Clock and Baud Rate...............................................................117
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ......118
Example of Relationship Between System Clock and Baud Rate...............................................................125
Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) ......125
Receive Error Causes .................................................................................................................................130
10-1
10-2
10-3
Interrupt Sources.........................................................................................................................................144
Interrupt Request Signals and Corresponding Flags...................................................................................146
Time from Generation of Maskable Interrupt Request to Servicing.............................................................153
16
User's Manual U14801EJ2V0UD
LIST OF TABLES (2/2)
Table No.
Title
Page
11-1
11-2
11-3
11-4
Operation Statuses in HALT Mode..............................................................................................................160
Operation After Releasing HALT Mode .......................................................................................................161
Operation Statuses in STOP Mode .............................................................................................................162
Operation After Releasing STOP Mode.......................................................................................................163
12-1
Status of Hardware After Reset...................................................................................................................166
13-1
13-2
13-3
13-4
Differences Between Flash Memory and Mask ROM Versions...................................................................167
Communication Mode..................................................................................................................................168
Major Functions of Flash Memory Programming.........................................................................................169
Setting Example with PG-FP3 .....................................................................................................................171
14-1
17-1
Operand Identifiers and Description Methods .............................................................................................175
Surface Mounting Type Soldering Conditions .............................................................................................199
17
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
1.1 Features
• ROM and RAM capacity
Item
Program Memory
Data Memory
Product Name
µPD789071
µPD789072
µPD789074
µPD78F9076
(Internal High-Speed RAM)
Mask ROM
2 KB
4 KB
8 KB
16 KB
256 KB
Flash memory
•
Minimum instruction execution time can be changed from high-speed (0.4 µs) to ultra-low speed (122 µs) at
5.0 MHz operation with system clock.
I/O ports: 34
•
•
Serial interface: 1 channel
3-wire serial I/O mode/UART mode: 1 channel
Timer: 3 channels
•
•
•
•
16-bit timer:
8-bit timer/event counter: 1 channel
Watchdog timer: 1 channel
1 channel
•
•
•
Vectored interrupt sources: 9
Supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: TA = −40 to +85°C
1.2 Applications
Small, general home electrical appliances, telephones, etc.
1.3 Ordering Information
Part Number
Package
Internal ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
µPD789071MC-×××-5A4
µPD789072MC-×××-5A4
µPD789074MC-×××-5A4
µPD78F9076MC-5A4
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
30-pin plastic SSOP (7.62 mm (300))
Remark ××× indicates ROM code suffix.
18
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
30-pin plastic SSOP (7.62 mm (300))
µPD789071MC-×××-5A4
µPD789072MC-×××-5A4
µPD789074MC-×××-5A4
µPD78F9076MC-5A4
P10
1
P11
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P31/BZO90
2
P12
IC (VPP
)
3
P13
RESET
X2
4
P14
5
P15
X1
6
P00
VSS
7
P01
VDD
8
P02
P30/TO90
P27/TI80/TO80
P26/INTP2/CPT90
P25/INTP1
9
P03
10
11
12
13
14
15
P04
P05
P06
P24/INTP0
P07
P23/SS20
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
Caution Connect the IC (Internally Connected) pin directly to VSS.
Remark Pin connections in parentheses are intended for the µPD78F9076.
ASCK20:
BZO90:
Asynchronous serial input
Buzzer output
Capture trigger input
Internally connected
External interrupt input
Port 0
SCK20:
SI20:
Serial clock
Serial input
CPT90:
SO20:
SS20:
TI80:
Serial output
IC:
Chip select input
Timer input
INTP0 to INTP2:
P00 to P07:
P10 to P15:
P20 to P27:
P30, P31:
RESET:
TO80, TO90:
TxD20:
VDD:
Timer output
Port 1
Transmit data
Power supply
Programming power supply
Ground
Port 2
Port 3
VPP:
Reset
VSS:
RxD20:
Receive data
X1, X2:
Crystal/ceramic oscillator
19
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y Subseries products support SMB.
Small-scale package, general-purpose applications
44-pin
µ
µ
µ
µ
µ
PD789074 with added subsystem clock
PD789046
42-/44-pin
30-pin
PD789014 with enhanced timer and increased ROM, RAM capacity
PD789074 with enhanced timer and increased ROM and RAM capacity
PD789026 with enhanced timer
µ
µ
µ
µ
PD789026
PD789088
PD789074
PD789014
30-pin
28-pin
On-chip UART and capable of low voltage (1.8 V) operation
Small-scale package, general-purpose applications and A/D converter
µ
µ
PD789177Y
PD789167Y
µ
µ
µ
µ
µ
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
µ
µ
PD789177
PD789167
PD789156
PD789146
PD789134A
PD789124A
PD789114A
PD789104A
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
30-pin
30-pin
µ
µ
µ
µ
PD789146 with enhanced A/D converter (10 bits)
TM
PD789104A with added EEPROM
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the
µ
PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added A/D converter and multiplier
µ
µ
µ
µ
LCD drive
144-pin
88-pin
80-pin
80-pin
80-pin
UART, 8-bit A/D converter, and dot LCD (Display output total: 96)
UART and dot LCD (40 × 16)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
µ
µ
PD789835
PD789830
µ
µ
µ
µ
µ
PD789488
PD789477
µ
PD789407A with enhanced A/D converter (10 bits)
78K/0S
Series
PD789417A
PD789407A
PD789456
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
80-pin
64-pin
µ
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15 × 4)
64-pin
64-pin
64-pin
µ
µ
µ
PD789446
PD789436
PD789426
µ
PD789426 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
µ
µ
µ
µ
PD789316
PD789306
PD789467
64-pin
64-pin
52-pin
SIO and on-chip voltage booster type LCD (24 × 4)
8-bit A/D converter and on-chip voltage booster type LCD (23 × 4)
SIO and resistance division type LCD (24 × 4)
52-pin
µ
PD789327
USB
For PC keyboard, on-chip USB HUB function
For PC keyboard, on-chip USB function
µ
µ
64-pin
44-pin
PD789803
PD789800
Inverter control
PD789842
µ
44-pin
30-pin
On-chip inverter controller and UART
On-chip CAN controller
On-chip bus controller
PD789850
µ
Keyless entry
RC oscillation version of the PD789860
µ
20-pin
20-pin
µ
µ
PD789861
PD789860
On-chip POC and key return circuit
VFD drive
µ
PD789871
52-pin
On-chip VFD controller (display output total: 25)
Meter control
µ
UART and resistance division type LCD (26 × 4)
PD789881
64-pin
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
20
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
The major functional differences between the subseries are listed below.
Series for LCD drive, general-purpose applications
Function
ROM
Timer
8-Bit 10-Bit
Serial
I/O VDD
Remarks
Capacity
A/D
A/D
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
Subseries Name
Small-scale µPD789046
16 KB
1 ch 1 ch
1 ch
1 ch
−
−
1 ch (UART: 34 1.8 V
1 ch)
−
package,
general-
purpose
µPD789026
4 KB to 16 KB
−
µPD789088
16 KB to
32 KB
3 ch
1 ch
24
applications
µPD789074
2 KB to 8 KB
2 KB to 4 KB
µPD789014
2 ch
−
22
Small-scale µPD789177
16 KB to
24 KB
3 ch 1 ch
1 ch
1 ch
−
8 ch
−
8 ch 1 ch (UART: 31 1.8 V
−
package,
general-
purpose
1 ch)
µPD789167
−
µPD789156
8 KB to
16 KB
1 ch
−
4 ch
−
20
On-chip
EEPROM
µPD789146
4 ch
−
applications
and A/D
converter
µPD789134A 2 KB to
4 ch
−
RC oscillation
version
8 KB
µPD789124A
4 ch
−
µPD789114A
µPD789104A
4 ch
−
−
4 ch
LCD drive µPD789835
24 KB to
60 KB
6 ch
–
1 ch
1 ch 3 ch
–
1 ch (UART: 37 1.8 V Dot LCD
Note
1 ch)
supported
µPD789830
µPD789488
µPD789477
24 KB
32 KB
24 KB
1 ch 1 ch
3 ch
–
30 2.7 V
8 ch 2 ch (UART: 45 1.8 V
−
1 ch)
8 ch
−
−
µPD789417A 12 KB to
7 ch 1 ch (UART: 43
24 KB
1 ch)
µPD789407A
7 ch
−
−
µPD789456
µPD789446
µPD789436
µPD789426
µPD789316
12 KB to
16 KB
2 ch
6 ch
–
30
40
6 ch
–
6 ch
–
6 ch
–
8 KB to
16 KB
2 ch (UART: 23
1 ch)
RC oscillation
version
µPD789306
µPD789467
µPD789327
–
4 KB to
24 KB
–
1 ch
–
18
21
–
1 ch
Note Flash memory version: 3.0V
21
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
Series for ASSP
Subseries Name
Function
ROM
Capacity
Timer
8-Bit 10-Bit
Serial
Interface
I/O VDD
Remarks
A/D
A/D
8-Bit 16-Bit Watch WDT
MIN.
Value
USB
µPD789803
µPD789800
8 KB to 16 KB 2 ch
8 KB
–
−
1 ch
–
–
2 ch
(USB: 1 ch)
41 3.6 V
31 4.0 V
−
Inverter
control
µPD789842
8 KB to
16 KB
3 ch Note 1 1 ch
1 ch 8 ch
1 ch 4 ch
−
−
1 ch (UART: 30 4.0 V
1 ch)
−
−
On-chip
bus
controller
µPD789850
16 KB
1 ch 1 ch
−
−
2 ch (UART: 18 4.0 V
1 ch)
Keyless
entry
µPD789861
µPD789860
4 KB
2 ch
−
1 ch
−
−
–
14 1.8 V RC oscillation
version,
on-chip
EEPROM
On-chip
EEPROM
VFD drive µPD789871
4 KB to 8 KB
16 KB
3 ch
–
1 ch
1 ch
1 ch
–
–
–
–
1 ch
33 2.7 V
–
–
Meter
µPD789881
2 ch 1 ch
–
1 ch (UART: 28 2.7 V
1 ch)
Note 2
control
Notes 1. 10-bit timer: 1 channel
2. Flash memory version: 3.0 V
22
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
1.6 Block Diagram
8-bit timer/event
counter 80
Port 0
Port 1
Port 2
P00 to P07
P10 to P15
P20 to P27
TI80/TO80/P27
TO90/P30
BZO90/P31
CPT90/P26
ROM
78K/0S
CPU core
memory)
16-bit timer 90
Watchdog timer
(flash
P30, P31
Port 3
RAM
SCK20/ASCK20
/P20
RESET
X1
Serial
interface 20
SO20/TxD20/P21
SI20/RxD20/P22
SS20/P23
System control
X2
INTP0/P24
INTP1/P25
Interrupt control
INTP2/P26
VDD
VSS
IC
(VPP
)
Remarks 1. The internal ROM capacity varies depending on the product.
2. Pin connections in parentheses are intended for the µPD78F9076.
23
User's Manual U14801EJ2V0UD
CHAPTER 1 GENERAL
1.7 Overview of Functions
Part Number
µPD789071
µPD789072
µPD789074
µPD78F9076
Item
Internal memory
ROM
Mask ROM
Flash memory
16 KB
2 KB
4 KB
8 KB
High-speed RAM
256 bytes
Minimum instruction execution time
General-purpose registers
Instruction set
0.4/1.6 µs (@5.0 MHz operation with system clock)
8 bits × 8 registers
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
CMOS I/O: 24
I/O ports
Switchable between 3-wire serial I/O and UART modes: 1 channel
• 16-bit timer: 1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
Serial interface
Timers
Timer outputs
2
Vectored interrupt
sources
Maskable
Internal: 5, external: 3
Internal: 1
Non-maskable
Power supply voltage
VDD = 1.8 to 5.5 V
TA = −40 to +85°C
Operating ambient temperature
Package
30-pin plastic SSOP (7.62 mm (300))
The outline of the timer is as follows.
16-Bit Timer 90
8-Bit Timer/Event
Watchdog Timer
Counter 80
Operating
mode
Interval timer
−
1 channel
1 channelNote
External event counter
Timer outputs
−
1 channel
−
−
−
−
−
−
1
Function
1
1
1
1
−
−
1
PWM outputs
−
Square-wave outputs
Buzzer outputs
Capture
−
1
1 input
1
Interrupt sources
Note The watchdog timer provides the watchdog timer function and interval timer function. Use either of the
functions.
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CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
(1) Port pins
Pin Name
P00 to P07
I/O
I/O
Function
After Reset Alternate Function
Port 0
Input
Input
Input
−
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
P10 to P15
I/O
I/O
Port 1
−
6-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
P20
P21
P22
P23
P24
P25
P26
P27
P30
Port 2
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SS20
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by setting pull-up resistor
option register B2 (PUB2).
INTP0
INTP1
INTP2/CPT90
TI80/TO80
TO90
I/O
Port 3
Input
2-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
P31
BZO90
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
Input
P24
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
INTP1
INTP2
SCK20
SI20
P25
P26/CPT90
I/O
Serial interface (SIO10) serial clock input
Serial interface (SIO20) serial data input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
−
P20/ASCK20
Input
P22/RxD20
SO20
SS20
ASCK20
RxD20
TxD20
TO90
BZO90
CPT90
TO80
TI80
Output Serial interface (SIO20) serial data output
P21/TxD20
Input
Input
Input
Serial interface chip select input
P23
Serial clock input for asynchronous serial interface
Serial data input for asynchronous serial interface
P20/SCK20
P22/SI20
Output Serial data output for asynchronous serial interface
Output 16-bit timer (TM90) output
P21/SO20
P30
Output Buzzer output
P31
Input
Capture edge input
P26/INTP2
Output 8-bit timer (TM80) output
P27/TI80
Input
External count clock input to 8-bit timer (TM80)
P27/TO80
X1
Input
Connecting crystal resonator for system clock oscillation
−
−
−
−
−
−
−
X2
−
−
RESET
VDD
Input
System reset input
Input
−
−
−
−
−
Positive supply voltage
VSS
Ground potential
−
IC
Internally connected. Connect directly to VSS.
−
VPP
This pin is used to set the flash memory programming mode
and applies a high voltage when a program is written or
verified. In normal operation mode, connect directly to VSS.
−
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P07 (Port 0)
These pins constitute an 8-bit I/O port and can be set to input or output port mode in 1-bit units by using port
mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by
setting pull-up resistor option register 0 (PU0).
2.2.2 P10 to P15 (Port 1)
These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode
register 1 (PM1). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-
up resistor option register 0 (PU0).
2.2.3 P20 to P27 (Port 2)
These pins constitute an 8-bit I/O port. In addition, these pins provide a function to perform input/output to/from
the timer, to input/output the data and clock of the serial interface, and to input the external interrupt.
Port 2 can be set to the following operation modes in 1-bit units.
(1) Port mode
In port mode, P20 to P27 function as an 8-bit I/O port. Port 2 can be set to input or output mode in 1-bit
units by using port mode register 2 (PM2). For P20 to P27, whether to use on-chip pull-up resistors can be
specified in 1-bit units by using pull-up resistor option register B2 (PUB2), regardless of the setting of port
mode register 2 (PM2).
(2) Control mode
In this mode, P20 to P27 function as the timer input/output and the serial interface data and clock
input/output.
(a) TI80
This is the external clock input pin for the 8-bit timer/event counter 80.
(b) TO80
This is the timer output pin of the 8-bit timer/event counter 80.
(c) INTP0 to INTP2
These are external interrupt input pins for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(d) CPT90
This is the capture edge input pin of the 16-bit timer counter 90.
(e) SI20, SO20
This is the serial data I/O pin of the serial interface.
(f) SCK20
This is the serial clock I/O pin of the serial interface.
(g) SS20
This is the chip select input pin of the serial interface.
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CHAPTER 2 PIN FUNCTIONS
(h) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
(i) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
Caution When using P20 to P27 as serial interface pins, the input/output mode and output latch
must be set according to the functions to be used. For details of the setting, see Table
9-2 Serial Interface 20 Operation Mode Settings.
2.2.4 P30, P31 (Port 3)
These pins constitute a 2-bit I/O port. In addition, these pins function as the timer output and the buzzer output.
Port 3 can be set to the following operation modes in 1-bit units.
(1) Port mode
When this port is used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor
option register 0 (PU0).
(2) Control mode
In this mode, P30 and P31 function as the timer output and the buzzer output.
(a) TO90
This is the output pin of the 16-bit timer 90.
(b) BZO90
This is the buzzer output pin of the 16-bit timer 90.
2.2.5 RESET
An active-low system reset signal is input to this pin.
2.2.6 X1, X2
These pins are used to connect a crystal resonator for system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.7 VDD
This pin supplies positive power.
2.2.8 VSS
This pin is the ground potential pin.
2.2.9 VPP (µPD78F9076 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Handle this pin in either of the following ways.
• Connect a 10 kΩ pull-down resistor to the pin.
• Provide a jumper on the board so that the pin is connected to a dedicated flash programmer in programming
mode and to VSS during normal operation.
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CHAPTER 2 PIN FUNCTIONS
2.2.10 IC (mask ROM version only)
The IC (Internally Connected) pin is used to set the µPD789071, 789072, and 789074 to test mode before
shipment. In normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible.
If a potential difference is generated between the IC pin and the VSS pin due to a long wiring length between
these pins or an external noise superimposed on the IC pin, the user program may not run correctly.
• Directly connect the IC pin to the VSS pin.
V
SS IC
Keep short
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the I/O circuit configuration of each type, refer to Figure 3-1.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
P00 to P07
I/O Circuit Type
5-A
I/O
I/O
Recommended Connection of Unused Pins
Connect to VDD or VSS via a resistor.
Input:
Output: Leave open.
P10 to P15
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SS20
8-A
Input:
Connect to VSS via a resistor.
P24/INTP0
P25/INTP1
P26/INTP2/CPT90
P27/TI80/TO80
P30/TO90
Output: Leave open.
Input:
Connect to VDD or VSS via a resistor.
Output: Leave open.
5-A
P31/BZO90
RESET
2
Input
−
IC
−
−
Connect directly to VSS.
VPP
Connect to a 10 kΩ pull-down resistor or directly to VSS.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits
Type 2
Type 8-A
V
DD
Pull-up
enable
P-ch
IN
VDD
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
VSS
Type 5-A
V
DD
Pull-up
enable
P-ch
V
DD
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS
Input
enable
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the µPD789074 Subseries can each access up to 64 KB of memory space. Figures 3-1 through 3-4
show the memory maps.
Figure 3-1. Memory Map (µPD789071)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
256 × 8 bits
F E 0 0 H
F D F F H
Reserved
Data memory space
0 7 F F H
0 8 0 0 H
0 7 F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal ROM
CALLT table area
2,048 × 8 bits
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 8 H
0 0 1 7 H
Vector table area
0 0 0 0 H
0 0 0 0 H
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Figure 3-2. Memory Map (µPD789072)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
256 × 8 bits
F E 0 0 H
F D F F H
Reserved
Data memory space
0 F F F H
1 0 0 0 H
0 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal ROM
4,096 × 8 bits
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 1 8 H
0 0 1 7 H
Vector table area
0 0 0 0 H
0 0 0 0 H
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Figure 3-3. Memory Map (µPD789074)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
256 × 8 bits
F E 0 0 H
F D F F H
Reserved
Data memory space
1 F F F H
2 0 0 0 H
1 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal ROM
8,192 × 8 bits
CALLT table area
Program area
0 0 4 0 H
0 0 3 F H
0 0 1 8 H
0 0 1 7 H
Vector table area
0 0 0 0 H
0 0 0 0 H
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Figure 3-4. Memory Map (µPD78F9076)
F F F F H
Special function registers
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
256 × 8 bits
F E 0 0 H
F D F F H
Reserved
Data memory space
3 F F F H
4 0 0 0 H
3 F F F H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal flash memory
CALLT table area
16,384 × 8 bits
0 0 4 0 H
0 0 3 F H
Program area
0 0 1 8 H
0 0 1 7 H
Vector table area
0 0 0 0 H
0 0 0 0 H
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
Products in the µPD789074 Subseries provide the following internal ROMs (or flash memory) containing the
following capacities.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
Capacity
2,048 × 8 bits
µPD789071
µPD789072
µPD789074
µPD78F9076
4,096 × 8 bits
8,192 × 8 bits
16,384 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space:
(1) Vector table area
The 24-byte area of addresses 0000H to 0017H is reserved as a vector table area. This area stores
program start addresses to be used when branching by RESET input or interrupt request generation. Of a
16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in
an odd address.
Table 3-2. Vector Table
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
000CH
Interrupt Request
INTSR20/INTCSI20
INTST20
0004H
0006H
0008H
000AH
INTWDT
INTP0
INTP1
INTP2
000EH
0014H
0016H
INTTM80
INTTM90
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
3.1.2 Internal data memory (internal high-speed RAM) space
The µPD789074 Subseries provides 256-byte internal high-speed RAM.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH
(see Table 3-3).
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3.1.4 Data memory addressing
Each product of the µPD789074 Subseries is provided with a wide range of addressing modes to make memory
manipulation as efficient as possible. The data memory area (FE00H to FFFFH) can be accessed using a unique
addressing mode according to its use, such as a special function register (SFR). Figures 3-5 through 3-8 illustrate
the data memory addressing.
Figure 3-5. Data Memory Addressing (µPD789071)
F F F F H
Special function registers (SFRs)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
256 × 8 bits
F E 2 0 H
F E 1 F H
F E 0 0 H
F D F F H
Direct addressing
Register indirect addressing
Based addressing
Reserved
0 8 0 0 H
0 7 F F H
Internal ROM
2,048 × 8 bits
0 0 0 0 H
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Figure 3-6. Data Memory Addressing (µPD789072)
F F F F H
Special function registers (SFRs)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
256 × 8 bits
F E 2 0 H
F E 1 F H
F E 0 0 H
F D F F H
Direct addressing
Register indirect addressing
Based addressing
Reserved
1 0 0 0 H
0 F F F H
Internal ROM
4,096 × 8 bits
0 0 0 0 H
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Figure 3-7. Data Memory Addressing (µPD789074)
F F F F H
Special function registers (SFRs)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
256 × 8 bits
F E 2 0 H
F E 1 F H
F E 0 0 H
F D F F H
Direct addressing
Register indirect addressing
Based addressing
Reserved
2 0 0 0 H
1 F F F H
Internal ROM
8,192 × 8 bits
0 0 0 0 H
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Figure 3-8. Data Memory Addressing (µPD78F9076)
F F F F H
Special function registers (SFRs)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
256 × 8 bits
F E 2 0 H
F E 1 F H
F E 0 0 H
F D F F H
Direct addressing
Register indirect addressing
Based addressing
Reserved
4 0 0 0 H
3 F F F H
Internal flash memory
16,384 × 8 bits
0 0 0 0 H
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3.2 Processor Registers
The µPD789074 Subseries provides the following on-chip processor registers.
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-9. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets the PSW to 02H.
Figure 3-10. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
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(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable
interrupt are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-11. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-12 and 3-13.
Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-12. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP
SP
SP
SP
SP
3
3
2
1
_
_
_
_
_
_
SP
SP
SP
SP
2
2
1
SP
SP
SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower half
register pairs
PC7 to PC0
Upper half
register pairs
PC15 to PC8
SP
SP
SP
Figure 3-13. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower half
register pairs
SP
SP
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Upper half
register pairs
PC15 to PC8
SP + 1
SP + 2
SP + 1
SP + 2
SP + 1
SP + 2
SP + 3
SP
SP
SP
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3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition to each register being used as an 8-bit register, two 8-bit registers can be used in pairs as a 16-bit
register (AX, BC, DE, and HL).
Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 3-14. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Function names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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3.2.3 Special function registers (SFRs)
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer,
and bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function
register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
specifying an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows.
• Symbol
Indicates the addresses of the implemented special function registers. The symbols shown in this column are
reserved words in the assembler, and have already been defined in a header file called "sfrbit.h" in the C
compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated
debugger is used.
• R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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Table 3-3. Special Function Registers (1/2)
Address Special Function Register (SFR) Name Symbol
R/W Number of Bits Manipulated Simultaneously After Reset
1 Bit
8 Bits
16 Bits
FF00H
FF01H
FF02H
FF03H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF20H
FF21H
FF22H
FF23H
FF32H
FF42H
Port 0
P0
R/W
√
√
√
√
−
√
√
√
√
−
−
−
−
00H
Port 1
P1
Port 2
P2
Port 3
P3
Note 2
Note 3
16-bit compare register 90
CR90Note 1
W
R
√
√
FFFFH
0000H
Undefined
FFH
Note 2
Note 3
16-bit timer counter 90
TM90Note 1
−
−
√
√
Note 2
Note 3
16-bit capture register 90
TCP90Note 1
√
√
Port mode register 0
PM0
R/W
√
√
√
√
√
−
√
√
√
√
√
√
−
−
−
−
−
−
Port mode register 1
PM1
Port mode register 2
PM2
Port mode register 3
PM3
Pull-up resistor option register B2
PUB2
WDCS
00H
Watchdog timer clock selection
register 2
FF48H
FF49H
FF50H
FF51H
FF53H
FF70H
16-bit timer mode control register 90
Buzzer output control register 90
8-bit compare register 80
TMC90
BZC90
CR80
√
√
−
−
√
√
√
√
√
√
√
√
−
−
−
−
−
−
W
R
Undefined
00H
8-bit timer counter 80
TM80
8-bit timer mode control register 80
TMC80
ASIM20
R/W
Asynchronous serial interface mode
register 20
FF71H
Asynchronous serial interface status
register 20
ASIS20
R
√
√
−
FF72H
FF73H
Serial operation mode register 20
CSIM20
R/W
√
−
√
√
−
−
Baud rate generator control register 20 BRGC20
Notes 1. These SFRs are for 16-bit access only.
2. CR90, TM90, and TCP90 are designed only for 16-bit access. In direct addressing, however, 8-bit
access can also be performed.
3. 16-bit access is allowed only in short direct addressing.
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CHAPTER 3 CPU ARCHITECTURE
Table 3-3. Special Function Registers (2/2)
Address Special Function Register (SFR) Name
Symbol
R/W Number of Bits Manipulated Simultaneously After Reset
1 Bit
−
8 Bits
16 Bits
FF74H
Transmission shift register 20
Receive buffer register 20
W
R
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
FFH
TXS20 SIO20
RXB20
IF0
−
Undefined
00H
FFE0H
FFE1H
FFE4H
FFE5H
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt mask flag register 0
Interrupt mask flag register 1
R/W
√
IF1
√
MK0
√
FFH
00H
MK1
√
FFECH External interrupt mode register 0
INTM0
PU0
−
FFF7H
FFF9H
FFFAH
Pull-up resistor option register 0
Watchdog timer mode register
√
WDTM
√
Oscillation stabilization time selection OSTS
register
−
04H
02H
FFFBH
Processor clock control register
PCC
√
√
−
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination address
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User's Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes the sign bit.
In other words, the range of branch in relative addressing is between –128 and +127 of the start address of the
following instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates that all bits are "0".
When S = 1, α indicates that all bits are "1".
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low addr.
High addr.
15
8 7
0
PC
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3.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the immediate
data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can
be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.
[Illustration]
7
0
6
1
5
1
0
0
Instruction code
Effective address
ta4–0
15
0
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
7
Memory (Table)
Low addr.
0
High addr.
Effective address + 1
15
8
7
0
PC
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods (addressing) are available to specify the register and memory to undergo manipulation
during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP Code
00H
FEH
[Illustration]
7
0
OP code
addr16 (low)
addr16 (high)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction
word.
The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to
FF1FH.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In
this area, ports which are frequently accessed in a program and a compare register of the timer counter are
mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
8
0
Effective
address
1
1
1
1
1
1
1
α
α
When 8-bit immediate data is 20H to FFH, = 0.
α
When 8-bit immediate data is 00H to 1FH, = 1.
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3.4.3 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction
word.
This addressing is applied to the 256-byte spaces FF00H to FFFFH. However, SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Register addressing
[Function]
A general-purpose register is accessed as an operand.
The general-purpose register to be accessed is specified with the register specify code and functional name in
the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A,
C, B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
1
0
0
0
1
0
0
0
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specify code
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3.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address specified
by register pair DE
The contents of addressed
memory are transferred
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN
instructions are executed or the register is saved/restored upon interrupt request generation.
Stack addressing can be used to access the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The µPD789074 Subseries is provided with the ports shown in Figure 4-1. These ports enable several types of
control. Table 4-1 lists the functions of each port.
These ports, while originally designed as digital I/O ports, have alternate functions. For the alternate functions,
refer to 2.1 Pin Function List.
Figure 4-1. Port Types
P20
P00
Port 2
Port 0
P27
P07
P10
P30
P31
Port 3
Port 1
P15
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CHAPTER 4 PORT FUNCTIONS
Table 4-1. Port Functions
Pin Name
P00 to P07
I/O
I/O
Function
After Reset Alternate Function
Port 0
Input
Input
Input
−
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
P10 to P15
I/O
I/O
Port 1
−
6-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
Port 2
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SS20
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by setting pull-up resistor
option register B2 (PUB2).
INTP0
INTP1
INTP2/CPT90
TI80/TO80
TO90
I/O
Port 3
Input
2-bit I/O port
BZO90
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by setting pull-up resistor option register 0 (PU0).
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CHAPTER 4 PORT FUNCTIONS
4.2 Port Configuration
Ports include the following hardware.
Table 4-2. Configuration of Port
Parameter
Configuration
Control registers
Port mode registers (PMm: m = 0 to 3)
Pull-up resistor option register 0 (PU0)
Pull-up resistor option register B2 (PUB2)
Ports
CMOS I/O: 24
Pull-up resistors
Software control: 24
4.2.1 Port 0
This is an 8-bit I/O port with an output latch. Port 0 can be set to input or output mode in 1-bit units by using port
mode register 0 (PM0). When pins P00 to P07 are used as input port pins, on-chip pull-up resistors can be
connected in 8-bit units by setting pull-up resistor option register 0 (PU0).
RESET input sets port 0 to input mode.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P07
VDD
WRPU0
PU00
P-ch
RD
WRPORT
Output latch
(P00 to P07)
P00 to P07
WRPM
PM00 to PM07
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
This is a 6-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units by using port
mode register 1 (PM1). When the P10 to P15 pins are used as input port pins, on-chip pull-up resistors can be
connected in 6-bit units by setting pull-up resistor option register 0 (PU0).
RESET input sets port 1 to input mode.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 to P15
VDD
WRPU0
PU01
P-ch
RD
WRPORT
Output latch
(P10 to P15)
P10 to P15
WRPM
PM10 to PM15
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
This is an 8-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port
mode register 2 (PM2). For pins P20 to P27, on-chip pull-up resistors can be connected in 1-bit units by setting pull-
up resistor option register B2 (PUB2).
The port is also used as external interrupt input, serial interface I/O, and timer I/O.
RESET input sets port 2 to input mode.
Figures 4-4 through 4-7 show block diagrams of port 2.
Caution When using the pins of port 2 for the serial interface, the I/O and output latches must be set
according to the function to be used. For details of the settings, see Table 9-2 Serial Interface
20 Operation Mode Settings.
Figure 4-4. Block Diagram of P20
V
DD
WRPUB2
PUB20
P-ch
Alternate
function
RD
WRPORT
Output latch
(P20)
P20/ASCK20/
SCK20
WRPM
PM20
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-5. Block Diagram of P21
V
DD
WRPUB2
PUB21
P-ch
RD
WRPORT
WRPM
Output latch
(P21)
P21/TxD20/
SO20
PM21
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-6. Block Diagram of P22 to P26
VDD
WRPUB2
PUB22 to PUB26
P-ch
Alternate
function
RD
WRPORT
Output latch
(P22 to P26)
P22/RxD20/SI20
P23/SS20
P24/INTP0
P25/INTP1
WRPM
P26/INTP2/CPT90
PM22 to PM26
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
Figure 4-7. Block Diagram of P27
V
DD
WRPUB2
PUB27
P-ch
Alternate
function
RD
WRPORT
Output latch
(P27)
P27/TI80/TO80
WRPM
PM27
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 3
This is a 2-bit I/O port with an output latch. Port 3 can be set to input or output mode in 1-bit units by using port
mode register 3 (PM3). When P30 and P31 are used as input port pins, on-chip pull-up resistors can be connected
in 2-bit units by setting pull-up resistor option register 0 (PU0).
The port is also used as timer output and buzzer output.
RESET input sets port 3 to input mode.
Figure 4-9 shows a block diagram of port 3.
Figure 4-8. Block Diagram of P30 and P31
V
DD
WRPU0
PU03
P-ch
RD
WRPORT
Output latch
(P30, P31)
P30/TO90
P31/BZO90
WRPM
PM30, PM31
Alternate
function
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 3 read signal
WR: Port 3 write signal
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CHAPTER 4 PORT FUNCTIONS
4.3 Port Function Control Registers
The following two types of registers are used to control the ports.
• Port mode registers (PM0 to PM3)
• Pull-up resistor option registers (PU0 and PUB2)
(1) Port mode registers (PM0 to PM3)
The port mode registers separately set each port bit to either input or output.
Each port mode register is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the port mode registers to FFH.
When port pins are used for alternate functions, the corresponding port mode register and output latch must
be set or reset as described in Table 4-3.
Caution When port 2 is acting as an output port, and its output level is changed, an interrupt
request flag is set, because this port is also used as the input for an external interrupt. To
use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
Figure 4-9. Format of Port Mode Register
Symbol
PM0
7
6
5
4
3
2
1
0
Address
FF20H
After reset
FFH
R/W
R/W
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
PM1
PM2
PM3
1
PM27
1
1
PM26
1
PM15
PM25
1
PM14
PM24
1
PM13
PM23
1
PM12
PM22
1
PM11
PM21
PM31
PM10
PM20
PM30
FF21H
FF22H
FF23H
FFH
FFH
FFH
R/W
R/W
R/W
Pmn pin input/output mode selection
(m = 0 to 3, n = 0 to 7)
PMmn
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 4 PORT FUNCTIONS
Table 4-3. Port Mode Register and Output Latch Settings for Using Alternate Functions
Pin Name
Alternate Function
Input/Output
PM××
P××
Name
P24
INTP0
INTP1
INTP2
CPT90
TI80
Input
1
1
1
1
1
0
0
0
×
×
×
×
×
0
0
0
P25
P26
Input
Input
Input
P27
Input
TO80
TO90
BZO90
Output
Output
Output
P30
P31
Caution When using the pins of port 2 for the serial interface, the I/O or output latch must be set
according to the function to be used. For details of the settings, see Table 9-2 Serial
Interface 20 Operation Mode Settings.
Remark ×:
PM××: Port mode register
P××: Port output latch
Don't care
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor is used on port 0, 1, or 3.
For ports specified by PU0 to use on-chip pull-up resistors, pull-up resistors can be internally used only for
the bits set to input mode. No on-chip pull-up resistors can be used for the bits set to output mode
regardless of the setting of PU0. On-chip pull-up resistors cannot be used even when the pins are used as
the alternate-function output pins.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 4-10. Format of Pull-up Resistor Option Register 0
Symbol
PU0
7
0
6
0
5
0
4
0
<3>
2
0
<1>
<0>
Address
FFF7H
After reset
00H
R/W
R/W
PU03
PU01
PU00
PU0m
Pm on-chip pull-up resistor selection (m = 0, 1, 3)
0
1
On-chip pull-up resistor is not used.
On-chip pull-up resistor is used.
Caution Bits 2 and 4 to 7 must all be set to 0.
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CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option register B2 (PUB2)
This register specifies whether an on-chip pull-up resistor connected to each pin of port 2 is used. The pins
for which use of an on-chip pull-up resistor is specified by PUB2 can use a pull-up register internally,
regardless of the setting of the port mode register.
PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB2 to 00H.
Figure 4-11. Format of Pull-up Resistor Option Register B2
Symbol
PUB2
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address
FF32H
After reset
00H
R/W
R/W
PUB27
PUB26
PUB25
PUB24
PUB23
PUB22
PUB21 PUB20
PUB2n
P2n on-chip pull-up resistor selection (n = 0 to 7)
0
1
On-chip pull-up resistor is not used.
On-chip pull-up resistor is used.
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CHAPTER 4 PORT FUNCTIONS
4.4 Operation of Port Functions
The operation of a port differs depending on whether the port is set to input or output mode, as described below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the
output latch can be output from the pins of the port.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
The data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the
contents of the output latch of the pin that is set to input mode and not subject to
manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output
latch are not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation
is written to the output latch. The contents of the output latch are output from the port pins.
The data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate one bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of a port consisting both of inputs and outputs, therefore, the
contents of the output latch of the pin that is set to input mode and not subject to
manipulation become undefined.
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CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following type of system clock oscillator is used.
• System clock oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction.
5.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Control register
Oscillator
Configuration
Processor clock control register (PCC)
Crystal/ceramic oscillator
Figure 5-1. Block Diagram of Clock Generator
Prescaler
Clock to peripheral
hardware
X1
X2
System clock
oscillator
Prescaler
f
X
f
X
22
Standby
controller
Wait
controller
STOP
CPU clock (fCPU
)
PCC1
Processor clock control
register (PCC)
Internal bus
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CHAPTER 5 CLOCK GENERATOR
5.3 Clock Generator Control Register
The clock generator is controlled by the following register.
• Processor clock control register (PCC)
(1) Processor clock control register (PCC)
PCC selects the CPU clock and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol
PCC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Address
FFFBH
After reset
02H
R/W
R/W
PCC1
PCC1
CPU clock (fCPU) selection
µ
0
1
f
X
X
(0.2 s)
2
µ
f
/2 (0.8 s)
Caution Bits 0 and 2 to 7 must all be set to 0.
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
3. Minimum instruction execution time: 2fCPU
• fCPU = 0.2 µs: 0.4 µs
• fCPU = 0.8 µs: 1.6 µs
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CHAPTER 5 CLOCK GENERATOR
5.4 System Clock Oscillators
5.4.1 System clock oscillator
The system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the
X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 5-3 shows the external circuit of the system clock oscillator.
Figure 5-3. External Circuit of System Clock Oscillator
(a) Crystal or ceramic oscillation
(b) External clock
V
X1
SS
External
clock
X1
X2
X2
Crystal
or
ceramic resonator
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken
lines in Figure 5-3 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Figure 5-4 shows an example of incorrect resonator connections.
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CHAPTER 5 CLOCK GENERATOR
Figure 5-4. Example of Incorrect Resonator Connection (1/2)
(a) Wiring too long
(b) Crossed signal line
PORTn
(n = 0 to 3)
VSS
X1
X2
VSS
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD
P
mn
VSS
X1
X2
V
SS
X1
X2
High current
A
B
C
High current
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CHAPTER 5 CLOCK GENERATOR
Figure 5-4. Example of Incorrect Resonator Connection (2/2)
(e) Signal is fetched
VSS
X1
X2
5.4.2 Frequency divider
The frequency divider divides the system clock oscillator output (fX) and generates clocks.
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CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as
standby mode.
• System clock
• CPU clock
fX
fCPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC) as follows.
(a) The slow mode 2fCPU (1.6 µs: at 5.0 MHz operation) of the system clock is selected when the RESET signal
is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.
(b) Two types of CPU clocks (fCPU) (0.2 µs, 0.8 µs: at 5.0 MHz operation) can be selected by the PCC setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock for the peripheral hardware is generated by dividing the frequency of the system clock.
Therefore, the peripheral hardware stops when the system clock stops (except for an external input clock).
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CHAPTER 5 CLOCK GENERATOR
5.6 Changing Setting of CPU Clock
5.6.1 Time required for switching CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 5-2).
Table 5-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching
PCC1
Set Value After Switching
PCC1 PCC1
0
1
0
1
4 clocks
2 clocks
Remark Two clocks are the minimum instruction execution time of the CPU clock before switching.
5.6.2 Switching CPU clock
The following figure illustrates how the CPU clock is switched.
Figure 5-5. Switching Between System Clock and CPU Clock
V
DD
RESET
f
X
f
X
CPU Clock
Slow
Fast operation
operation
Wait (6.55 ms: @ 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is
released when the RESET pin is later made high, and the system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the system clock (1.6 µs: @
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at the high
speed has elapsed, the processor clock control register (PCC) is rewritten so that the high-speed operation
can be selected.
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CHAPTER 6 16-BIT TIMER 90
6.1 16-Bit Timer 90 Functions
16-bit timer 90 has the following functions.
• Timer interrupt
• Timer output
• Buzzer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when a count value and compare value match.
(2) Timer output
Timer output can be controlled when a count value and compare value match.
(3) Buzzer output
Buzzer output can be controlled by software.
(4) Count value capture
A count value of 16-bit timer counter 90 (TM90) is latched into a capture register synchronizing with the
capture trigger and retained.
6.2 16-Bit Timer 90 Configuration
16-bit timer 90 includes the following hardware.
Table 6-1. Configuration of 16-Bit Timer 90
Item
Timer counter
Configuration
16 bits × 1 (TM90)
Registers
Compare register:16 bits × 1 (CR90)
Capture register: 16 bits × 1 (TCP90)
Timer outputs
1 (TO90)
Control registers
16-bit timer mode control register 90 (TMC90)
Buzzer output control register 90 (BZC90)
Port mode register 3 (PM3)
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Figure 6-1. Block Diagram of 16-Bit Timer 90
Internal bus
16-bit timer mode control
register 90 (TMC90)
P30
Output latch
TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
PM30
TO90/P30
16-bit compare register
F/F
TOD90
90 (CR90)
f
f
f
X
X
X
/22
/24
/26
Match
INTTM90
OVF
BZO90/P31
16-bit timer counter
90 (TM90)
CTP90/INTP2/
P26
P31
Output latch
/
3
PM31
Edge detection
circuit
16-bit capture
register 90 (TCP90)
16-bit counter
read buffer
BCS902 BCS901 BCS900 BZOE90
Buzzer output control
register 90 (BZC90)
Write controller
Write controller
fX/2
CPU clock
Internal bus
CHAPTER 6 16-BIT TIMER 90
(1) 16-bit compare register 90 (CR90)
A value specified in CR90 is compared with the count in 16-bit timer counter 90 (TM90). If they match, an
interrupt request (INTTM90) is issued by CR90.
CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can
be set.
RESET input sets CR90 to FFFFH.
Cautions 1. CR90 is designed to be manipulated with a 16-bit memory manipulation instruction. It
can also be manipulated with 8-bit memory manipulation instructions, however. When
an 8-bit memory manipulation instruction is used to set CR90, it must be accessed by
direct addressing.
2. To re-set CR90 during a count operation, it is necessary to disable interrupts in
advance, using interrupt mask flag register 1 (MK1). It is also necessary to disable
inversion of the timer output data, using 16-bit timer mode control register 90 (TMC90).
If CR90 is rewritten with interrupts enabled, an interrupt request may be issued
immediately.
(2) 16-bit timer counter 90 (TM90)
TM90 is used to count the number of pulses.
The contents of TM90 are read with an 8-bit or 16-bit memory manipulation instruction.
RESET input clears TM90 to 0000H.
Cautions 1. The count becomes undefined when STOP mode is released, because the count
operation is performed before oscillation stabilizes.
2. TM90 is designed to be manipulated with a 16-bit memory manipulation instruction. It
can also be manipulated with 8-bit memory manipulation instructions, however. When
an 8-bit memory instruction is used to manipulate TM90, it must be accessed by direct
addressing.
3. When an 8-bit memory manipulation instruction is used to manipulate TM90, the lower
and higher bytes must be read as a pair, in that order.
(3) 16-bit capture register 90 (TCP90)
TCP90 captures the contents of 16-bit timer counter 90 (TM90).
This register is set with an 8-bit or 16-bit memory manipulation instruction.
RESET input makes TCP90 undefined.
Caution TCP90 is designed to be manipulated with a 16-bit memory manipulation instruction. It
can also be manipulated with 8-bit memory manipulation instructions, however. When an
8-bit memory manipulation instruction is used to manipulate TCP90, it must be accessed
by direct addressing.
(4) 16-bit counter read buffer 90
This buffer is used to latch and hold the count for 16-bit timer counter 90 (TM90).
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CHAPTER 6 16-BIT TIMER 90
6.3 16-Bit Timer 90 Control Registers
The following three registers are used to control 16-bit timer 90.
• 16-bit timer mode control register 90 (TMC90)
• Buzzer output control register 90 (BZC90)
• Port mode register 3 (PM3)
(1) 16-bit timer mode control register 90 (TMC90)
16-bit timer mode control register 90 (TMC90) controls the setting of the count clock, capture edge, etc.
TMC90 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC90 to 00H.
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CHAPTER 6 16-BIT TIMER 90
Figure 6-2. Format of 16-Bit Timer Mode Control Register 90
Symbol
7
<6>
5
4
3
2
1
<0>
Address
FF48H
After reset
00H
R/W
TMC90 TOD90 TOF90 CPT901CPT900 TOC90 TCL901 TCL900 TOE90
R/WNote
TOD90
Timer output data
0
1
Timer output of 0
Timer output of 1
TOF90
Overflow flag setting
0
1
Reset or cleared by software
Set when the 16-bit timer overflows
CPT901 CPT900
Capture edge selection
0
0
1
1
0
1
0
1
Capture operation disabled
Captured at the rising edge at the CPT90 pin
Captured at the falling edge at the CPT90 pin
Captured at both the rising and falling edges at the CPT90 pin
TOC90
Timer output data inversion control
0
1
Inversion disabled
Inversion enabled
TCL901 TCL900
16-bit timer counter 90 count clock (fcl) selection
0
0
1
1
0
1
0
1
f
f
f
f
X
X
X
/22 (1.25 MHz)
/26 (78.125 kHz)
/24 (31.1 kHz)
XT (32.768 kHz)
TOE90
16-bit timer counter output control
0
1
Output disabled (port mode)
Output enabled
Note Bit 7 is read-only.
Caution Disable interrupts in advance using interrupt mask flag register 1 (MK1) when changing
the data of TCL901 and TCL900. Also, prevent the timer output data from being inverted
by setting TOC90 to 1.
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 90
(2) Buzzer output control register 90 (BZC90)
This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and
TCL900), and controls the output of a square wave.
BZC90 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears BZC90 to 00H.
Figure 6-3. Format of Buzzer Output Control Register 90
Address After reset R/W
Symbol
BZC90
7
0
6
0
5
0
4
0
3
<0>
2
1
BCS902 BCS901 BCS900 BZOE90
FF49H
00H
R/W
Buzzer frequency
BCS902 BCS901 BCS900
fcl = f
X
/22
fcl = f
X
/26
fcl = f
/24
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fcl/24 (78.125 kHz)
fcl/25 (39.063 kHz)
fcl/28 (4.88 kHz)
fcl/29 (2.44 kHz)
fcl/210 (1.22 kHz)
fcl/211 (610 Hz)
fcl/212 (305 Hz)
fcl/213 (153 Hz)
fcl/24 (4.88 kHz)
fcl/25 (2.44 kHz)
fcl/28 (305 Hz)
fcl/29 (153 Hz)
fcl/210 (76 Hz)
fcl/211 (38 Hz)
fcl/212 (19 Hz)
fcl/213 (10 Hz)
fcl/24 (19.5 kHz)
fcl/25 (9.77 kHz)
fcl/28 (1.22 kHz)
fcl/29 (610 Hz)
fcl/210 (305 Hz)
fcl/211 (153 Hz)
fcl/212 (76.3 Hz)
fcl/213 (38.1 Hz)
BZOE90
0
Buzzer port output control
Disables buzzer port output.
Enables buzzer port output.
1
Caution Bits 4 to 7 must all be set to 0.
Remarks 1. fX: System clock oscillation frequency
2. fcl: Count clock frequency of 16-bit timer 90.
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 90
(3) Port mode register 3 (PM3)
PM3 is used to set each bit of port 3 to input or output.
When pin P30/TO90 is used for timer output, reset the output latch of P30 and PM30 to 0; when pin
P31/BZO90 is used for buzzer output, reset the output latch of P31 and PM31 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 6-4. Format of Port Mode Register 3
Address After reset R/W
FF23H FFH R/W
Symbol
PM3
7
1
6
1
5
1
4
1
3
1
0
2
1
1
PM31
PM30
P3n pin I/O mode (n = 0, 1)
PM3n
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 6 16-BIT TIMER 90
6.4 16-Bit Timer 90 Operation
6.4.1 Operation as timer interrupt
In the timer interrupt function, interrupts are repeatedly generated at the count value preset in 16-bit compare
register 90 (CR90) taking the value set in TCL901 and TCL900 as the interval.
To operate 16-bit timer 90 as a timer interrupt, the following settings are required.
• Set count values in CR90
• Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-5.
Figure 6-5. Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
TMC90
−
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Setting of count clock (see Table 6-2)
Caution If both the CPT901 and CPT900 flags are set to 0, the capture operation is disabled.
When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, counting of TM90
continues and an interrupt request signal (INTTM90) is generated.
Table 6-2 shows the interval time, and Figure 6-6 shows the timing of the timer interrupt operation.
Caution Perform the following processing when rewriting CR90 during a count operation.
<1> Disable interrupts (TMMK90 (bit 1 of interrupt mask flag register 1 (MK1)) = 1).
<2> Disable inversion control of timer output data (TOC90 = 0).
If CR90 is rewritten with interrupts enabled, an interrupt request may be issued immediately.
Table 6-2. Interval Time of 16-Bit Timer 90
TCL901
TCL900
Count Clock
Interval Time
0
0
1
1
0
1
0
1
22/fX (0.8 µs)
218/fX (52.4 ms)
222/fX (838.9 ms)
220/fX (210.0 ms)
26/fX (12.8 µs)
24/fX (3.2 µs)
Setting prohibited
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 6 16-BIT TIMER 90
Figure 6-6. Timing of Timer Interrupt Operation
t
Count clock
TM90 count value
CR90
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
N
N
N
N
N
INTTM90
Interrupt
acknowledgement
Interrupt
acknowledgement
TO90
TOF90
Overflow flag set
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 90
6.4.2 Operation as timer output
Timer outputs are repeatedly generated at the count value preset in 16-bit compare register 90 (CR90) taking the
value set in TCL901 and TCL900 as the interval.
To operate 16-bit timer 90 as a timer output, the following settings are required.
• Set P30 to output mode (PM30 = 0).
• Reset the output latch of P30 to 0.
• Set the count value in CR90.
• Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-7.
Figure 6-7. Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
TMC90
−
0/1
0/1
0/1
1
0/1
0/1
1
TO90 output enable
Setting of count clock (see Table 6-2)
Inverse enable of timer output data
Caution If both the CPT901 and CPT900 flags are set to 0, the capture operation is disabled.
When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, the output status of the
TO90/P30 pin is inverted. This enables timer output. At that time, the TM90 count continues and an interrupt
request signal (INTTM90) is generated.
Figure 6-8 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 90).
Figure 6-8. Timer Output Timing
t
Count clock
TM90 count value
CR90
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
N
N
N
N
N
INTTM90
Interrupt
acknowledgement
Interrupt
acknowledgement
TO90Note
TOF90
Overflow flag set
Note The TO90 initial value becomes low level during output enable (TOE90 = 1).
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 90
6.4.3 Capture operation
The capture operation consists of latching the count value of 16-bit timer counter 90 (TM90) into a capture
register in synchronization with a capture trigger, and retaining the count value.
Set TMC90 as shown in Figure 6-9 to allow 16-bit timer 90 to start the capture operation.
Figure 6-9. Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation
TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90
TMC90
−
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Count clock selection
Capture edge selection (see Table 6-3)
16-bit capture register 90 (TCP90) starts a capture operation after the CPT90 capture trigger edge is detected,
and latches and retains the count value of 16-bit timer counter 90. TCP90 fetches the count value within 2 clocks
and retains the count value until the next capture edge detection.
Table 6-3 and Figure 6-10 show the settings of the capture edge and capture operation timing, respectively.
Table 6-3. Settings of Capture Edge
CPT901
CPT900
Capture Edge Selection
0
0
1
1
0
1
0
1
Capture operation disabled
CPT90 pin rising edge
CPT90 pin falling edge
CPT90 pin both edges
Caution Because TCP90 is rewritten when a capture trigger edge is detected during a TCP90 read,
disable the capture trigger edge detection during a TCP90 read.
Figure 6-10. Capture Operation Timing (with Both Edges of CPT90 Pin Specified)
Count clock
TM90
Count read buffer
TCP90
0000H 0001H
0000H 0001H
N
N
M – 1
M
M
Undefined
N
M
Capture start
Capture start
CPT90
Capture edge detection
Capture edge detection
Remark N = 0000H to FFFFH
M = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 90
6.4.4 16-bit timer counter 90 readout
The count value of 16-bit timer counter 90 (TM90) is read out with a 16-bit manipulation instruction.
TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count
value. The buffer operation is then held pending at the CPU clock falling edge after the read signal of the TM90
lower byte rises and the count value is retained. The counter read buffer value at the retention state can be read out
as the count value.
Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM90
higher byte falls.
RESET input clears TM90 to 0000H and TM90 resumes counting in the freerunning mode.
Figure 6-11 shows the timing of 16-bit timer counter 90 readout.
Cautions 1. The count value after releasing the stop mode becomes undefined because the count
operation is executed during the oscillation stabilization time.
2. Though TM90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can
also be used.
When using the 8-bit transfer instruction, execute it by direct addressing.
3. When using the 8-bit transfer instruction, execute in the order from the lower byte to the
higher byte in pairs. If only the lower byte is read, the pending state of the counter read
buffer is not canceled, and if only the higher byte is read, an undefined count value is read.
Figure 6-11. 16-Bit Timer Counter 90 Readout Timing
CPU clock
Count clock
TM90
Count read buffer
TM90 read signal
0000H
0000H
0001H
0001H
N
N + 1
N
Read signal latch
prohibited period
Remark N = 0000H to FFFFH
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CHAPTER 6 16-BIT TIMER 90
6.4.5 Buzzer output operation
The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected
with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output.
Table 6-4 shows the buzzer frequency.
To operate 16-bit timer 90 as a buzzer output, the following settings are required.
• Set P31 to output mode (PM31 = 0).
• Reset output latch of P31 to 0.
• Set a count clock by using TCL901 and TCL900.
• Set BZC90 as shown in Figure 6-12.
Figure 6-12. Settings of Buzzer Output Control Register 90 for Buzzer Output Operation
BCS902 BCS901 BCS900 BZOE90
BZC90
0
0
0
0
0/1
0/1
0/1
1
Enables buzzer output
Setting of buzzer frequency (see Table 6-4)
Table 6-4. Buzzer Frequency of 16-Bit Timer 90
BCS902
BCS901
BCS900
Buzzer Frequency
fcl = fX/22
fcl/24 (78.1 kHz)
fcl = fX/26
fcl/24 (4.88 kHz)
fcl = fX/24
fcl/24 (19.5 kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fcl/25 (39.1 kHz)
fcl/28 (4.88 kHz)
fcl/29 (2.44 kHz)
fcl/210 (1.22 kHz)
fcl/211 (610 Hz)
fcl/212 (305 Hz)
fcl/213 (153 Hz)
fcl/25 (2.44 kHz)
fcl/28 (305 Hz)
fcl/29 (153 Hz)
fcl/210 (76 Hz)
fcl/211 (38 Hz)
fcl/212 (19 Hz)
fcl/213 (10 Hz)
fcl/25 (9.77 kHz)
fcl/28 (1.22 kHz)
fcl/29 (610 Hz)
fcl/210 (305 Hz)
fcl/211 (153 Hz)
fcl/212 (76.3 Hz)
fcl/213 (38.1 Hz)
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.1 Functions of 8-Bit Timer/Event Counter 80
8-bit timer/event counter 80 has the following functions.
• Interval timer
• External event counter
• Square wave output
• PWM output
(1) 8-bit interval timer
When 8-bit timer/event counter 80 is used as an interval timer, it generates an interrupt at a time interval set
in advance.
Table 7-1. Interval Time of 8-Bit Timer/Event Counter 80
Minimum Interval Time
Maximum Interval Time
28/fX (51.2 µs)
Resolution
1/fX (200 ns)
28/fX (51.2 µs)
1/fX (200 ns)
28/fX (51.2 µs)
216/fX (13.1 ms)
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
(2) External event counter
The number of pulses of an externally input signal can be counted.
(3) Square-wave output
A square-wave of arbitrary frequency can be output.
Table 7-2. Square-Wave Output Range of 8-Bit Timer/Event Counter 80
Minimum Pulse Width
Maximum Pulse Width
28/fX (51.2 µs)
216/fX (13.1 ms)
Resolution
1/fX (200 ns)
28/fX (51.2 µs)
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
1/fX (200 ns)
28/fX (51.2 µs)
(4) PWM output
8-bit resolution PWM output can be produced.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.2 8-Bit Timer/Event Counter 80 Configuration
8-bit timer/event counter 80 includes the following hardware.
Table 7-3. Configuration of 8-Bit Timer/Event Counter 80
Configuration
Item
Timer counter
Register
8 bits × 1 (TM80)
Compare register: 8 bits × 1 (CR80)
1 (TO80)
Timer outputs
Control registers
8-bit timer mode control register 80 (TMC80)
Port mode register 2 (PM2)
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
8-bit compare
register 80 (CR80)
Match
INTTM80
TI80/P27/
TO80
CLEAR
8-bit timer counter
80 (TM80)
f
X
R
INV Q
f
/28
X
OVF
Q
S
TO80/P27/TI80
P27
Output
latch
PM27
TCE80 PWME80TCL801TCL800TOE80
8-bit timer mode control register 80 (TMC80)
Internal bus
(1) 8-bit compare register 80 (CR80)
A value specified in CR80 is compared with the count in 8-bit timer counter 80 (TM80). If they match, an
interrupt request (INTTM80) is issued.
CR80 is set with an 8-bit memory manipulation instruction. Any value from 00H to FFH can be set.
RESET input makes CR80 undefined.
Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer
operation is enabled, the match interrupt request signal may be generated
immediately.
2. Do not clear CR80 to 00H in PWM output mode (when PWME80 = 1: bit 6 of 8-bit timer
mode control register 80 (TMC80)); otherwise, PWM output may not be produced
normally.
(2) 8-bit timer counter 80 (TM80)
TM80 is used to count the number of pulses.
Its contents are read with an 8-bit memory manipulation instruction.
RESET input clears TM80 to 00H.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.3 8-Bit Timer/Event Counter 80 Control Registers
The following two registers are used to control 8-bit timer/event counter 80.
• 8-bit timer mode control register 80 (TMC80)
• Port mode register 2 (PM2)
(1) 8-bit timer mode control register 80 (TMC80)
TMC80 determines whether to enable or disable 8-bit timer counter 80 (TM80), specifies the count clock for
TM80, and controls the operation of the output control circuit of 8-bit timer/event counter.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.
Figure 7-2. Format of 8-Bit Timer Mode Control Register 80
Symbol <7>
<6>
5
0
4
0
3
0
2
1
<0>
Address
FF53H
After reset
00H
R/W
R/W
TMC80 TCE80 PWME80
TCL801 TCL800 TOE80
TCE80
8-bit timer counter 80 operation control
0
1
Operation disabled (TM80 is cleared to 0.)
Operation enabled
PWME80
Operation mode selection
0
1
Timer counter operation mode
PWM output mode
TCL801 TCL800
8-bit timer counter 80 count clock selection
f
X
X
(5.0 MHz)
0
0
1
1
0
1
0
1
f
/28 (19.5 kHz)
Rising edge of TI80Note
Falling edge of TI80Note
TOE80
8-bit timer/event counter output control
0
1
Output disabled (port mode)
Output enabled
Note When inputting a clock signal externally, timer output cannot be used.
Caution Always stop the timer before setting TMC80.
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
(2) Port mode register 2 (PM2)
PM2 specifies whether each bit of port 2 is used for input or output.
To use the TO80/P27/TI80 pin for timer output, the PM27 and P27 output latch must be reset to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 7-3. Format of Port Mode Register 2
Symbol
PM2
7
6
5
4
3
2
1
0
Address
FF22H
After reset
FFH
R/W
R/W
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
PM2n
P2n pin input/output mode selection (n = 0 to 5)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.4 Operation of 8-Bit Timer/Event Counter 80
7.4.1 Operation as interval timer
The interval timer repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit
compare register 80 (CR80).
To operate 8-bit timer/event counter 80 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of 8-bit timer mode control register 80
(TMC80)) = 0).
<2> Set the count clock of 8-bit timer/event counter 80 (see Table 7-4).
<3> Set a count value in CR80.
<4> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 is cleared to 0 and
continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Table 7-4 shows interval time, and Figure 7-4 shows the timing of interval timer operation.
Cautions 1. Stop the timer operation before rewriting CR80. If CR80 is rewritten while the timer
operation is enabled, a match signal may be generated immediately (an interrupt request
will be generated if interrupts are enabled).
2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the
same time with an 8-bit memory manipulation instruction, the error one cycle after the timer
has been started may exceed one clock. To use 8-bit timer/event counter 80 as an interval
timer, therefore, make the settings in the above sequence.
Table 7-4. Interval Time of 8-Bit Timer/Event Counter 80
TCL801
TCL800
Minimum Interval Time
1/fX (200 ns)
Maximum Interval Time
28/fX (51.2 µs)
Resolution
1/fX (200 ns)
0
0
1
1
0
1
0
1
28/fX (51.2 µs)
216/fX (13.1 ms)
28/fX (51.2 µs)
TI80 input cycle
TI80 input cycle
28 × TI80 input cycle
28 × TI80 input cycle
TI80 input edge cycle
TI80 input edge cycle
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
Figure 7-4. Interval Timer Operation Timing
t
Count clock
TM80 count value
00H
01H
N
00H 01H
Clear
N
00H 01H
Clear
N
CR80
N
N
N
N
TCE80
Count start
INTTM80
Interrupt acknowledgement
Interrupt acknowledgement
TO80
Interval time
Interval time
Interval time
Remark Interval time = (N + 1) × t
N = 00H to FFH
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses input to the TI80/P27/TO80 pin by using
8-bit timer counter 80 (TM80).
To operate 8-bit timer/event counter 80 as an external event counter, settings must be made in the following
sequence.
<1> Set P27 to input mode (PM27 = 1).
<2> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 (bit 7 of 8-bit timer mode control register 80
(TMC80)) = 0).
<3> Specify the rising or falling edge of TI80 (see Table 7-4). Disable output of TO80 (TOE80 (bit 0 of TMC80)
= 0) and PWM output (PWME80 (bit 6 of TMC80) = 0).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80
(TM80) is incremented.
When the count value of TM80 matches the value set in CR80, TM80 is cleared to 0 and continues counting. At
the same time, an interrupt request signal (INTTM80) is generated.
Figure 7-5 shows the timing of the external event counter operation (with rising edge specified).
Cautions 1. Before rewriting CR80, stop the timer operation. If CR80 is rewritten while the timer
operation is enabled, a match interrupt request signal may be generated immediately.
2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the
same time with an 8-bit memory manipulation instruction, the error one cycle after the timer
has been started may exceed one clock. To use 8-bit timer/event counter 80 as an external
event counter, therefore, make the settings in the above sequence.
Figure 7-5. External Event Counter Operation Timing (with Rising Edge Specified)
TI80 pin input
TM80 count value
CR80
00H
02H
04H 05H
N
00H
02H 03H
01H
03H
N – 1
01H
N
TCE80
INTTM80
Remark N = 00H to FFH
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.4.3 Operation as square-wave output
8-bit timer/event counter 80 can generate square-wave output of an arbitrary frequency at an interval specified by
the count value preset in 8-bit compare register 80 (CR80).
To use 8-bit timer/event counter 80 for square-wave output, settings must be made in the following sequence.
<1> Set P27 to output mode (PM27 = 0). Set the output latch of P27 to 0.
<2> Disable operation of 8-bit timer counter 80 (TM80) (TCE80 = 0).
<3> Set a count clock for 8-bit timer/event counter 80 (see Table 7-5), enable output of TO80 (TOE80 = 1), and
disable PWM output (PWME80 = 0).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, the TO80 pin output will
be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a
match occurs, TM80 is cleared to 0 and continues counting, generating an interrupt request signal (INTTM80).
Setting bit 7 (TCE80) of TMC80 to 0 clears the square-wave output to 0.
Table 7-5 shows the square-wave output range, and Figure 7-6 shows timing of square-wave output.
Cautions 1. Stop the timer operation before rewriting CR80. If CR80 is rewritten while the timer
operation is enabled, a match interrupt request signal may be generated immediately.
2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the
same time with an 8-bit memory manipulation instruction, the error one cycle after the timer
has been started may exceed one clock. To use 8-bit timer/event counter 80 as a square-
wave output, therefore, make the settings in the above sequence.
Table 7-5. Square-Wave Output Range of 8-Bit Timer/Event Counter
TCL801
TCL800
Minimum Pulse Width
Maximum Pulse Width
28/fX (51.2 µs)
216/fX (13.1 ms)
Resolution
0
0
0
1
1/fX (200 ns)
28/fX (51.2 µs)
1/fX (200 ns)
28/fX (51.2 µs)
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
Figure 7-6. Square-Wave Output Timing
Count clock
TM80 count value
00H
01H
N
00H 01H
Clear
N
00H 01H
Clear
N
CR80
N
N
N
N
TCE80
Count start
INTTM80
Interrupt acknowledgement
Interrupt acknowledgement
TO80Note
Note The initial value of TO80 is low for output enable (TOE80 = 1).
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.4.4 Operation as PWM output
PWM output enables an interrupt to be generated repeatedly at an interval specified by the count value preset in
8-bit compare register 80 (CR80).
To use 8-bit timer/event counter 80 for PWM output, the following settings are required.
<1> Set P27 to output mode (PM27 = 0). Set the output latch of P27 to 0.
<2> Disable the operation of 8-bit timer counter 80 (TM80) (TCE80 = 0).
<3> Set a count clock for 8-bit timer/event counter (see Table 7-4), and enable output of TO80 (TOE80 = 1) and
PWM output (PWME80 = 1).
<4> Set a count value in CR80.
<5> Enable the operation of TM80 (TCE80 = 1).
When the count value of 8-bit timer counter 80 (TM80) matches the value set in CR80, TM80 continues counting,
and an interrupt request signal (INTTM80) is generated.
Cautions 1. If CR80 is rewritten during timer operation, a high level may be output during the next cycle
(see 7.5 (2) Setting of 8-bit compare register 80).
2. If setting the count clock to TMC80 and enabling the operation of TM80 are performed at the
same time with an 8-bit memory manipulation instruction, the error one cycle after the timer
has been started may exceed one clock. To use 8-bit timer/event counter 80 as a PWM
output, therefore, make the settings in the above sequence.
Figure 7-7. PWM Output Timing
Count clock
00H 01H •••
M
••• FFH 00H 01H 02H •••
M
M
M + 1 M + 2 ••• FFH 00H 01H •••
M
••• •••
TM80
CR80
TCE80
OVF
INTTM80
TO80Note
M = 01H to FFH
Note The initial value of TO80 is low for output enable (TOE80 = 1).
Caution Do not set CR80 to 00H in PWM output mode, otherwise, PWM may not be output normally.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
7.5 Notes on Using 8-Bit Timer/Event Counter 80
(1) Error on starting timer
An error of up to 1 clock is included in the time between the timer being started and a match signal being
generated. This is because 8-bit timer counter 80 (TM80) is started asynchronously to the count pulse.
Figure 7-8. Start Timing of 8-Bit Timer Counter 80
Count pulse
TM80
00H
01H
02H
03H
04H
count value
Timer start
(2) Setting of 8-bit compare register 80
8-bit compare register 80 (CR80) can be set to 00H.
Therefore, one pulse can be counted when 8-bit timer/event counter 80 operates as an event counter.
Figure 7-9. External Event Counter Operation Timing
Tl80 input
CR80
00H
TM80
count value
00H
00H
00H
00H
Interrupt request flag
Cautions 1. Before rewriting CR80 in timer counter operation mode (PWME80 (bit 6 of 8-bit timer
mode control register 80 (TMC80) = 0), stop the timer operation. If CR80 is rewritten
while the timer operation is enabled, a match interrupt request signal may be
generated immediately.
2. If CR80 is rewritten during timer operation in PWM output operation mode (PWME80 =
1), a high level may be output during the next cycle (count pulse × 256). This occurs
when CR80 is set to a value smaller than the TM80 value at the time CR80 is rewritten.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 80
Count clock
TM80
00H 01H
•••
M
•••
FFH 00H 01H 02H
•••
FFH 00H 01H
01H
•••
•••
M
CR80
TCE80
OVF
INTTM80
TO80
M = 02H to FFH
Change of CR80
M → 01H
3. Do not set CR80 to 00H in PWM operation mode (when PWME80 = 1) otherwise, PWM
may not be output normally.
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CHAPTER 8 WATCHDOG TIMER
8.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect inadvertent program loops. When an inadvertent loop is detected, a
non-maskable interrupt or a RESET signal can be generated.
Table 8-1. Inadvertent Loop Detection Time of Watchdog Timer
Inadvertent Loop Detection Time
211 × 1/fX
At fX = 5.0 MHz
410 µs
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: System clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at an arbitrary preset interval.
Table 8-2. Interval Time
Interval
At fX = 5.0 MHz
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
410 µs
1.64 ms
6.55 ms
26.2 ms
fX: System clock oscillation frequency
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CHAPTER 8 WATCHDOG TIMER
8.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 8-3. Configuration of Watchdog Timer
Configuration
Item
Control registers
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
Figure 8-1. Block Diagram of Watchdog Timer
Internal bus
f
X
24
WDTMK
WDTIF
Prescaler
f
X
26
f
X
f
X
210
28
INTWDT
Maskable
interrupt request
7-bit counter
Clear
Controller
RESET
INTWDT
Non-maskable
interrupt request
3
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer clock selection
register 2 (WDCS)
Watchdog timer mode register (WDTM)
Internal bus
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CHAPTER 8 WATCHDOG TIMER
8.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer.
•
•
Watchdog timer clock selection register (WDCS)
Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input clears WDCS to 00H.
Figure 8-2. Format of Watchdog Timer Clock Selection Register
Symbol
WDCS
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF42H
After reset
00H
R/W
R/W
WDCS2 WDCS1 WDCS0
WDCS2 WDCS1 WDCS0
Interval time
Count clock selection
/24 (313 kHz)
/26 (78.1 kHz)
/28 (19.5 kHz)
/210 (4.88 kHz)
0
0
1
1
0
0
0
0
0
211/f
213/f
215/f
217/f
X
X
X
X
(410 µs)
fX
fX
fX
fX
1
(1.64 ms)
(6.55 ms)
(26.2 ms)
0
1
Other than above
Setting prohibited
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) Watchdog timer mode register (WDTM)
This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 8-3. Format of Watchdog Timer Mode Register
Symbol
WDTM
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address
FFF9H
After reset
00H
R/W
R/W
RUN
WDTM4 WDTM3
Watchdog timer operation selectionNote 1
RUN
0
1
Stops counting.
Clears counter and starts counting.
Watchdog timer operation mode selectionNote 2
WDTM4 WDTM3
0
0
1
1
0
1
0
1
Operation stop
Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)Note 3
Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.)
Watchdog timer mode 2 (Starts a reset operation upon overflow occurrence.)
Notes 1. Once RUN has been set to 1, it cannot be cleared to 0 by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set to 1, they cannot be cleared to 0 by software.
3. The watchdog timer starts operation as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock selection register
(WDCS).
2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming WDTIF (bit 0 of
interrupt request flag register 0 (IF0)) being set to 0. When watchdog timer mode 1 or 2
is selected with WDTIF set to 1, a non-maskable interrupt is generated upon the
completion of rewriting WDTM.
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CHAPTER 8 WATCHDOG TIMER
8.4 Watchdog Timer Operation
8.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode
register (WDTM) is set to 1.
The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2
(WDCS0 to WDCS2) of the watchdog timer clock selection register (WDCS). By setting bit 7 (RUN) of WDTM to 1,
the watchdog timer is started. Set RUN to 1 within the set inadvertent loop detection time interval after the watchdog
timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not
set to 1, and the inadvertent loop detection time is exceeded, a system reset signal or a non-maskable interrupt is
generated, depending on the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1
to clear the watchdog timer before executing the STOP instruction.
Caution The actual inadvertent loop detection time may be up to 0.8% shorter than the set time.
Table 8-4. Inadvertent Loop Detection Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Inadvertent Loop Detection Time
At fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: System clock oscillation frequency
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8.4.2 Operation as interval timer
When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at an interval
specified by a preset count value.
Select a count clock (or interval time) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock
selection register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of
WDTM) is set to 1.
In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to
clear the interval timer before executing the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval
timer mode is not set unless a RESET signal is input.
2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been
set.
Table 8-5. Interval Generated Using Interval Timer
WDCS2 WDCS1 WDCS0
Interval Time
At fX = 5.0 MHz
410 µs
0
0
1
1
0
1
0
1
0
0
0
0
211 × 1/fX
213 × 1/fX
215 × 1/fX
217 × 1/fX
1.64 ms
6.55 ms
26.2 ms
fX: System clock oscillation frequency
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CHAPTER 9 SERIAL INTERFACE 20
9.1 Serial Interface 20 Functions
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(2) Asynchronous serial interface (UART) mode
This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface 20 contains a UART-dedicated baud rate generator, enabling communication over a wide
range of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to
the ASCK20 pin.
(3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data
lines (SI20 and SO20).
As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing
time for data transmission than asynchronous serial interface mode.
Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the
MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is
designed for MSB-first or LSB-first transmission.
3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional synchronous serial interfaces, such as those of the 75X/XL, 78K, and 17K Series devices.
9.2 Serial Interface 20 Configuration
Serial interface 20 includes the following hardware.
Table 9-1. Configuration of Serial Interface 20
Item
Configuration
Registers
Transmission shift register 20 (TXS20)
Reception shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control registers
Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
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Figure 9-1. Block Diagram of Serial Interface 20
Internal bus
Serial operation mode
register 20 (CSIM20)
Asynchronous serial interface
status register 20 (ASIS20)
Asynchronous serial interface
mode register 20 (ASIM20)
Receive buffer
register 20 (RXB20)
TXE20 RXE20 PS201 PS200 CL20 SL20
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20
PE20 FE20 OVE20
Switching of the first bit
Transmission shift
register 20 (TXS20) Transmission
shift clock
Reception shift
register 20 (RXS20)
SI20/P22/
RxD20
Selector
CSIE20
DAP20
Reception
shift clock
Port mode
register (PM21)
Data phase
control
SO20/P21/
TxD20
Parity operation
Stop bit addition
INTST20
4
Transmission data counter
Parity detection
Stop bit detection
SL20, CL20, PS200, PS201
INTSR20/INTCSI20
Transmission
and reception
clock control
Reception data counter
Reception enabled
CSIE20
CSCK20
/2 to f
/28
Baud rate
generatorNote
Reception clock
Start bit
detection
Detection clock
f
X
X
Reception detected
4
CSIE20
SS20/P23
TPS203
TPS202 TPS201 TPS200
Internal clock output
CSCK20
Baud rate generator
control register 20 (BRGC20)
Clock phase
control
SCK20/P20/
ASCK20
External clock input
Internal bus
Note See Figure 9-2 for the configuration of the baud rate generator.
Figure 9-2. Block Diagram of Baud Rate Generator 20
Reception detection clock
Transmission shift clock
Transmission
clock counter
1/2
f
X
/2
fX
fX
fX
fX
fX
fX
fX
/22
/23
/24
/25
/26
/27
/28
1/2
Reception shift clock
Reception
clock counter
TXE20
SCK20/ASCK20/P20
RXE20
CSIE20
Reception detected
4
TPS203 TPS202 TPS201 TPS200
Baud rate generator control
register 20 (BRGC20)
Internal bus
CHAPTER 9 SERIAL INTERFACE 20
(1) Transmission shift register 20 (TXS20)
TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20
bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data
to TXS20 triggers transmission.
TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS20 to FFH.
Caution Do not write to TXS20 during transmission.
TXS20 and receive buffer register 20 (RXB20) are mapped at the same address, so that any
attempt to read from TXS20 results in a value being read from RXB20.
(2) Reception shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one
entire byte has been received, RXS20 feeds the reception data to receive buffer register 20 (RXB20).
RXS20 cannot be manipulated directly by a program.
(3) Receive buffer register 20 (RXB20)
RXB20 holds a reception data. A new reception data is transferred from reception shift register 20 (RXS20)
every 1-byte data reception.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is
always fixed to 0.
RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written.
RESET input makes RXB20 undefined.
Caution RXB20 and transmission shift register 20 (TXS20) are mapped at the same address, so that
any attempt to write to RXB20 results in a value being written to TXS20.
(4) Transmission controller
The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the
data in transmission shift register 20 (TXS20), according to the setting of asynchronous serial interface
mode register 20 (ASIM20).
(5) Reception controller
The reception controller controls reception according to the setting of asynchronous serial interface mode
register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is
detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the
error.
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CHAPTER 9 SERIAL INTERFACE 20
9.3 Serial Interface 20 Control Registers
Serial interface 20 is controlled by the following registers.
• Serial operation mode register 20 (CSIM20)
• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)
(1) Serial operation mode register 20 (CSIM20)
CSIM20 is set when serial interface 20 is used in 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Figure 9-3. Format of Serial Operation Mode Register 20
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20 pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
External clock input to the SCK20 pin
Output of the dedicated baud rate generator
CSCK20
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is at high level in the idle state.
Clock is active high, and SCK20 is at low level in the idle state.
Cautions 1. Bits 4 and 5 must both be set to 0.
2. CSIM20 must be cleared to 00H, if UART mode is selected.
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CHAPTER 9 SERIAL INTERFACE 20
(2) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set when serial interface 20 is used in asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Figure 9-4. Format of Asynchronous Serial Interface Mode Register 20
Symbol <7> <6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmit operation control
0
1
Transmit operation stop
Transmit operation enable
RXE20
Receive operation control
0
1
Receive operation stop
Receive operation enable
PS201 PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception (No parity error is generated).
1
1
0
1
Odd parity
Even parity
CL20
Transmit data character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must both be set to 0.
2. If 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operating modes after halting the serial transmit/receive operation.
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CHAPTER 9 SERIAL INTERFACE 20
Table 9-2. Serial Interface 20 Operating Mode Settings
(1) Operation stop mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Function
Function
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
0
0
0
×
×
×
×
×
×
×
×
−
−
P22
P21
P20
Other than above
Setting prohibited
(2) 3-wire serial I/O mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Function
Function
Note 2
0
0
1
1
0
1
0
1
0
1
1Note 2
×
0
1
1
0
1
0
×
1
×
1
MSB
SI20Note 2
External
SO20
(CMOS output)
SCK20
input
clock
SCK20
output
Internal
clock
LSB
SCK20
input
External
clock
SCK20
output
Internal
clock
Other than above
Setting prohibited
(3) Asynchronous serial interface mode
ASIM20
CSIM20
PM22 P22 PM21 P21 PM20 P20
First
Bit
Shift
P22/SI20/
P21/SO20/ P20/SCK20/
TxD20 Pin ASCK20 Pin
Clock RxD20 Pin
Function
TXE20 RXE20 CSIE20 DIR20 CSCK20
Function
Function
Note 1
Note 1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
×
×
0
1
1
×
LSB
P22
TxD20
(CMOS output)
ASCK20
input
External
clock
Note 1
Note 1
×
×
×
×
×
×
P20
Internal
clock
Note 1
Note 1
1
1
×
×
×
×
1
×
RxD20
P21
ASCK20
input
External
clock
Note 1
Note 1
P20
Internal
clock
0
1
1
×
TxD20
ASCK20
input
External
clock
(CMOS output)
Note 1
Note 1
P20
Internal
clock
Other than above
Setting prohibited
Notes 1. These pins can be used for port functions.
2. When only transmission is used, this pin can be used as P22 (CMOS I/O).
Remark ×: Don't care.
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CHAPTER 9 SERIAL INTERFACE 20
(3) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.
Figure 9-5. Format of Asynchronous Serial Interface Status Register 20
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE20 FE20 OVE20
PE20
Parity error flag
0
1
No parity error has occurred.
A parity error has occurred (parity mismatch in transmission data).
FE20
Flaming error flag
No framing error has occurred.
0
1
A framing error has occurred (no stop bit detected).Note 1
OVE20
Overrun error flag
0
1
No overrun error has occurred.
An overrun error has occurredNote 2
.
(Before data was read from the receive buffer register, the subsequent receive operation was
completed.)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every
time the data is received an overrun error is generated.
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CHAPTER 9 SERIAL INTERFACE 20
(4) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the serial clock for serial interface 20.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Figure 9-6. Format of Baud Rate Generator Control Register 20
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
TPS203 TPS202 TPS201 TPS200
3-bit counter source clock selection
n
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
External clock input to the ASCK20 pinNote
Setting prohibited
Other than above
Note An external clock can be used only in UART mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output
of the baud rate generator is disrupted and communication cannot be performed
normally. Be sure not to write to BRGC20 during a communication operation.
2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting baud
rate exceeds the rated range.
3. When the external input clock is selected, set port mode register 2 (PM2) to input
mode.
Remarks 1. fX: System clock oscillation frequency
2. n: Value determined by setting TPS200 through TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a
signal scaled from the clock input from the ASCK20 pin.
(a) Generation of baud rate transmit/receive clock form system clock
The transmit/receive clock is generated by scaling the system clock. The baud rate of a clock
generated from the system clock is estimated by using the following expression.
fX
[Baud rate] =
[Hz]
2n + 1 × 8
fX: System clock oscillation frequency
n: Value determined by values of TPS200 through TPS203 as shown in Figure 9-6 (2 ≤ n ≤ 8)
Table 9-3. Example of Relationship Between System Clock and Baud Rate
Baud Rate (bps)
n
BRGC20 Set Value
Error (%)
f = 5.0 MHz
1.73
f = 4.9152 MHz
0
1,200
2,400
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
4,800
9,600
19,200
38,400
76,800
Caution Do not select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds
the rated range.
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CHAPTER 9 SERIAL INTERFACE 20
(b) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate
of a clock generated from the clock input from the ASCK20 pin is estimated by using the following
expression.
fASCK
16
[Baud rate] =
[Hz]
fASCK: Frequency of clock input from the ASCK20 pin
Table 9-4. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
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CHAPTER 9 SERIAL INTERFACE 20
9.4 Serial Interface 20 Operation
Serial interface 20 provides the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
9.4.1 Operation stop mode
In operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The
P20/SCK20/ASCK20, P21/SO20/TxD20, and P22/SI20/RxD20 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial
interface mode register 20 (ASIM20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol
<7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20
DIR20
CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
Caution Bits 4 and 5 must both be set to 0.
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
Receive operation control
0
1
Transmit operation stop
Transmit operation enable
RXE20
0
1
Receive operation stop
Receive operation enable
Caution Bits 0 and 1 must both be set to 0.
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CHAPTER 9 SERIAL INTERFACE 20
9.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communication
is possible.
This device incorporates a UART-dedicated baud rate generator that enables communication at a desired baud
rate from many options. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin.
The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI
standard.
(1) Register setting
UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), and baud rate generator
control register 20 (BRGC20).
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(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Set CSIM20 to 00H when UART mode is selected.
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20 pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock input to the SCK20 pin
Output of the dedicated baud rate generator
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is high level in the idle state.
Clock is active high, and SCK20 is low level in the idle state.
Caution Bits 4 and 5 must both be set to 0.
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CHAPTER 9 SERIAL INTERFACE 20
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE20
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS201
PS200
Parity bit specification
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception. (No parity error is generated.)
Odd parity
Even parity
1
1
0
1
CL20
Character length specification
0
1
7 bits
8 bits
SL20
Transmit data stop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must both be set to 0.
2. Switch operating modes after halting the serial transmit/receive operation.
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CHAPTER 9 SERIAL INTERFACE 20
(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF71H
After reset
00H
R/W
R
PE20
FE20
OVE20
PE20
Parity error flag
0
1
Parity error not generated
Parity error generated (when the parity of transmit data does not match)
Flaming error flag
FE20
0
1
Framing error not generated
Framing error generated (when stop bit is not detected)Note 1
OVE20
Overrun error flag
Overrun error not generated
0
1
Overrun error generatedNote 2
(when the next receive operation is completed before the data is read from the receive buffer register)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1
bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not,
every time the data is received an overrun error is generated.
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(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
n
1
2
3
4
5
6
7
8
TPS203 TPS202 TPS201 TPS200
3-bit counter source clock selection
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
External clock input to ASCK20 pin
Setting prohibited
Other than above
Cautions 1. When writing to BRGC20 is performed during a communication operation, the
output of the baud rate generator is disrupted and communication cannot be
performed normally. Be sure not to write to BRGC20 during a communication
operation.
2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting
baud rate exceeds the rated range.
3. When the external input clock is selected, set port mode register 2 (PM2) to input
mode.
Remarks 1. fX: System clock oscillation frequency
2. n: Value determined by setting TPS200 through TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or
a signal scaled from the clock input from the ASCK20 pin.
(i) Generation of baud rate transmit/receive clock from system clock
The transmit/receive clock is generated by scaling the system clock. The baud rate of the clock
generated from the system clock is estimated by using the following expression.
fX
[Baud rate] =
[Hz]
2n + 1 × 8
fX: System clock oscillation frequency
n: Value determined by setting TPS200 through TPS203 as shown in the above table (2 ≤ n ≤ 8)
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Table 9-5. Example of Relationship Between System Clock and Baud Rate
Baud Rate (bps)
n
BRGC20 Set Value
Error (%)
fX = 5.0 MHz
1.73
fX = 4.9152 MHz
0
1,200
2,400
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
4,800
9,600
19,200
38,400
76,800
Caution Do not select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds
the rated range.
(ii) Generation of baud rate transmit/receive clock from external clock input from ASCK20 pin
The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud
rate of the clock generated from the clock input from the ASCK20 pin is estimated by using the
following expression.
fASCK
16
[Baud rate] =
[Hz]
fASCK: Frequency of clock input from the ASCK20 pin
Table 9-6. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps)
75
ASCK20 Pin Input Frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
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CHAPTER 9 SERIAL INTERFACE 20
(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 9-7. One data frame consists of a start bit,
character bits, a parity bit, and stop bit(s).
The specification of the character bit length in one data frame, parity selection, and specification of the
stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20).
Figure 9-7. Format of Asynchronous Serial Interface Transmit/Receive Data
One data frame
Start
bit
Parity
bit
D0 D1 D2 D3 D4 D5 D6 D7
Stop bit
• Start bits ................... 1 bit
• Character bits ........... 7 bits/8 bits
• Parity bits.................. Even parity/odd parity/0 parity/no parity
• Stop bit(s) ................. 1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always "0".
The serial transfer rate is selected by ASIM20 and baud rate generator control register 20 (BRGC20).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of asynchronous serial interface status register 20 (ASIS20).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit
(odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The parity bit is determined so that the number of bits with a value of "1" in the transmit data
including the parity bit may be even. The parity bit value should be as follows.
The number of bits with a value of "1" is an odd number in transmit data:
1
The number of bits with a value of "1" is an even number in transmit data: 0
• At reception
The number of bits with a value of "1" in the receive data including the parity bit is counted, and if
the number is odd, a parity error is generated.
(ii) Odd parity
• At transmission
Conversely to even parity, the parity bit is determined so that the number of bits with a value of
"1" in the transmit data including the parity bit may be odd. The parity bit value should be as
follows.
The number of bits with a value of "1" is an odd number in transmit data:
0
The number of bits with a value of "1" is an even number in transmit data: 1
• At reception
The number of bits with a value of "1" in the receive data including the parity bit is counted, and if
the number is even, a parity error is generated.
(iii) 0 parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated,
irrespective of whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data.
At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a
parity error is not generated.
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CHAPTER 9 SERIAL INTERFACE 20
(c) Transmission
A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The
start bit, parity bit, and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.
Figure 9-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
STOP
TxD20 (Output)
INTST20
D0
D1
D2
D6
D7
Parity
START
(b) Stop bit length: 2
D0
D1
D2
D6
D7
Parity
TxD20 (Output)
INTST20
STOP
START
Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a
transmit operation. If the ASIM20 register is rewritten during transmission,
subsequent transmission may not be performed (the normal state is restored by
RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set
by INTST20.
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(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set to 1, a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by ASIM20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the
time determined by the specified baud rate has passed, the data sampling start timing signal is output.
If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start
bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character
data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to
receive buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and
INTSR20 is generated.
If the RXE20 bit is reset to 0 during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are
not changed, and INTSR20 is not generated.
Figure 9-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
INTSR20
START
Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and the
receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, a framing error, and an
overrun error. After data reception, an error flag is set in asynchronous serial interface status register
20 (ASIS20). Receive error causes are shown in Table 9-7.
It is possible to determine what kind of error occurred during reception by reading the contents of
ASIS20 in the reception error interrupt servicing (see Figures 9-9 and 9-10).
The contents of ASIS20 are reset to 0 by reading receive buffer register 20 (RXB20) or receiving the
next data (if there is an error in the next data, the corresponding error flag is set).
Table 9-7. Receive Error Causes
Receive Errors
Cause
Transmission-time parity and reception data parity do not match.
Stop bit not detected
Parity error
Framing error
Overrun error
Reception of next data is completed before data is read from receive buffer register.
Figure 9-10. Receive Error Timing
(a) Parity error occurred
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
START
INTSR20
(b) Framing error or overrun error occurred
STOP
D0
D1
D2
D6
D7
Parity
RxD20 (Input)
INTSR20
START
Cautions 1. The contents of the ASIS20 register are reset to 0 by reading receive buffer register
20 (RXB20) or receiving the next data. To ascertain the error contents, read
ASIS20 before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will occur when the next data is received, and
the receive error state will continue indefinitely.
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(f) Reading receive data
When the reception completion interrupt (INTSR20) is generated, read the value of receive buffer
register 20 (RXB20) to read the receive data.
When reading the receive data stored in receive buffer register 20 (RXB20), enable the receive
operation (RXE20 = 1).
Remark If the receive data must be read after the receive operation has been disabled (RXE20 = 0),
use either method below.
(a) After waiting for 1 cycle or more of the source clock selected by BRGC20, set RXE20 to
0, and then read the receive data.
(b) Set bit 2 (DIR20) of serial operation mode register 20 (CSIM20) to 1, and read the
receive data.
Example program for (a) (BRGC29 = 00H (source clock = fx/2))
INTRXE:
;Reception completion interrupt routine
;2 clocks
NOP
CLR1 RXE20
;Stop reception operation
;Read receive data
MOV
A,RXB20
Example program for (b)
INTRXE:
;Reception completion interrupt routine
;Set the DIR20 flag to LSB first
;Stop reception operation
SET1 CSIM20.2
CLR1 RXE20
MOV A,RXB20
;Read receive data
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(3) Cautions related to UART mode
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before
executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as
follows.
RxD20 Pin
Parity
RXB20
INTSR20
<1>
<3>
<2>
When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and INTSR20 is not
generated.
When RXE20 is set to 0 at a time indicated by <2>, RXB20 renews the data and INTSR20 is not generated.
When RXE20 is set to 0 at a time indicated by <3>, RXB20 renews the data and INTSR20 is generated.
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9.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., that
incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.
Communication is performed using three lines: the serial clock (SCK20), serial output (SO20), and serial input
(SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20),
asynchronous serial interface mode register 20 (ASIM20), and baud rate generator control register 20
(BRGC20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Symbol <7>
6
5
0
4
0
3
2
1
0
Address
FF72H
After reset
00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
3-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Function of SS20/P23 pin
Port function
SS20 pin selection
0
1
Not used
Used
Communication enabled
0
1
Communication enabled
Communication disabled
DAP20
3-wire serial I/O mode data phase selection
0
1
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
First-bit specification
0
1
MSB
LSB
3-wire serial I/O mode clock selection
CSCK20
External clock input to the SCK20 pin
Output of the dedicated baud rate generator
0
1
CKP20
3-wire serial I/O mode clock phase selection
0
1
Clock is active low, and SCK20 is at high level in the idle state.
Clock is active high, and SCK20 is at low level in the idle state.
Caution Bits 4 and 5 must both be set to 0.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H.
Symbol
ASIM20
<7>
<6>
5
4
3
2
1
0
0
0
Address
FF70H
After reset
00H
R/W
R/W
TXE20
RXE20
PS201
PS200
CL20
SL20
TXE20
Transmit operation control
Receive operation control
Parity Bit specification
0
1
Transmit operation stop
Transmit operation enable
RXE20
0
1
Receive operation stop
Receive operation enable
PS201
PS200
0
0
0
1
No parity
Always add 0 parity at transmission.
Parity check is not performed at reception. (No parity error is generated.)
Odd parity
Even parity
1
1
0
1
CL20
Character length specification
0
1
7 bits
8 bits
SL20
Transmit data sop bit length specification
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must both be set to 0.
2. Switch operating modes after halting the serial transmit/receive operation.
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address
FF73H
After reset
00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
n
1
2
3
4
5
6
7
8
TPS203 TPS202 TPS201 TPS200
3-bit counter source clock selection
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX
fX
fX
fX
fX
fX
fX
fX
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
Other than above
Setting prohibited
Cautions 1. When writing to BRGC20 is performed during a communication operation, the
baud rate generator output is disrupted and communication cannot be performed
normally. Be sure not to write to BRGC20 during a communication operation.
2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting
baud rate exceeds the rated range.
3. When the external input clock is selected, set port mode register 2 (PM2) to input
mode.
Remarks 1. fX: System clock oscillation frequency
2. n: Value determined by setting TPS200 through TPS203 (1 ≤ n ≤ 8)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 to
set the frequency of the serial clock. To obtain the frequency to be set, use the following expression.
When an external serial clock is used, setting BRGC20 is not necessary.
fX
Serial clock frequency =
[Hz]
2n + 1
fX: System clock oscillation frequency
n: Value determined by setting TPS200 to TPS203 as shown in the above table (1 ≤ n ≤ 8)
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CHAPTER 9 SERIAL INTERFACE 20
(2) Communication operation
In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
transmitted/received bit by bit in synchronization with the serial clock.
Data is
Transmission shift register 20 (TXS20/SIO20) and reception shift register 20 (RXS20) shift operations are
performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the
SO20 latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in receive
buffer register 20 (RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and the
interrupt request signal (INTCSI20) is generated.
Figure 9-11. 3-Wire Serial I/O Mode Timing (1/7)
(i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SO20
1
2
3
4
5
6
7
8
Note
DO7
DI7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
SI20
INTCSI20
Note The value of the last bit previously output is output.
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Figure 9-11. 3-Wire Serial I/O Mode Timing (2/7)
(ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0)
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
Note
INTCSI20
Note The value of the last bit previously output is output.
(iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1)
SS20
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0Note 2
SO20
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
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CHAPTER 9 SERIAL INTERFACE 20
Figure 9-11. 3-Wire Serial I/O Mode Timing (3/7)
(iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SO20
DO7
DO6
DI6
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
DO0
DI0
DI7
SI20
INTCSI20
(v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SIO20 Write (master)Note
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the
first bit before the first rising of SCK20.
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CHAPTER 9 SERIAL INTERFACE 20
Figure 9-11. 3-Wire Serial I/O Mode Timing (4/7)
(vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20
1
DI7
2
3
4
5
6
7
8
SIO20 Write (master)Note 1
SI20
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs
the first bit before the first rising of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
(vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
SIO20
Write
1
2
DO6
DI6
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
8
DO0
DI0
SCK20
SO20
DO7
DI7
SI20
INTCSI20
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CHAPTER 9 SERIAL INTERFACE 20
Figure 9-11. 3-Wire Serial I/O Mode Timing (5/7)
(viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0)
SIO20
Write
1
2
3
4
5
6
7
8
SCK20
SIO20 Write (master)Note
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the
first bit before the first falling of SCK20.
(ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1)
SS20
SIO20
Write
SCK20
1
2
3
4
5
6
7
8
SIO20 Write (master)Note 1
SI20
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
Note 2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs
the first bit before the first falling of SCK20.
2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a
high-impedance state.
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CHAPTER 9 SERIAL INTERFACE 20
Figure 9-11. 3-Wire Serial I/O Mode Timing (6/7)
(x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SO20
1
2
3
4
5
6
7
8
Note
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI20
INTCSI20
Note The value of the last bit previously output is output.
(xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0)
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Note
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO20
INTCSI20
Note The value of the last bit previously output is output.
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CHAPTER 9 SERIAL INTERFACE 20
Figure 9-11. 3-Wire Serial I/O Mode Timing (7/7)
(xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1)
SS20
SIO20
Write
SCK20
SI20
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Hi-Z
Hi-Z
DO0Note 2
Note 1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
SO20
INTCSI20
Notes 1. The value of the last bit previously output is output.
2. DO0 is output until SS20 rises.
When SS20 is high, SO20 is in a high-impedance state.
(3) Transfer start
Serial transfer is started by setting transfer data to the transmission shift register (TXS20/SIO20) when the
following two conditions are satisfied.
• Serial operation mode register 20 (CSIM20) bit 7 (CSIE20) = 1
• Internal serial clock is stopped or SCK20 is high after 8-bit serial transfer.
Caution If CSIE20 is set to "1" after data is written to TXS20/SIO20, transfer does not start.
The termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request
signal (INTCSI20).
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CHAPTER 10 INTERRUPT FUNCTIONS
10.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt
priority control and is given top priority over all other interrupt requests.
A standby release signal is generated.
An interrupt from the watchdog timer is the only non-maskable interrupt source.
(2) Maskable interrupt
These interrupts undergo mask control. If two or more interrupts are simultaneously generated, each
interrupt has a predetermined priority as shown in Table 10-1.
A standby release signal is generated.
There are three external sources and five internal sources of maskable interrupts.
10.2 Interrupt Sources and Configuration
There are a total of 9 non-maskable and maskable interrupt sources (see Table 10-1).
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Table 10-1. Interrupt Sources
Interrupt Type
PriorityNote 1
Interrupt Source
Trigger
Internal/External Vector Table
Basic
Address
Configuration
TypeNote 2
Name
Non-maskable
interrupt
−
INTWDT
Watchdog timer overflow
(when watchdog timer mode 1
is selected)
Internal
0004H
(A)
(B)
(C)
Maskable
interrupt
0
INTWDT
Watchdog timer overflow
(when interval timer mode is
selected)
1
2
3
4
INTP0
Pin input edge detection
External
Internal
0006H
0008H
000AH
000CH
INTP1
INTP2
INTSR20
End of UART reception on
serial interface 20
(B)
INTCSI20
INTST20
INTTM80
INTTM90
End of 3-wire SIO transfer
reception on serial interface 20
5
6
7
End of UART transmission on
serial interface 20
000EH
0014H
0016H
Generation of match signal for
8-bit timer/event counter 80
Generation of match signal for
16-bit timer 90
Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time.
0 is the highest and 7 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 10-1.
Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable interrupts and
maskable interrupts. Either one (but not both) should be selected for actual use.
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Figure 10-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
Interrupt request
IF
Standby release signal
(C) External maskable interrupt
Internal bus
External interrupt mode
register 0 (INTM0)
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
IF:
Interrupt request flag
Interrupt enable flag
Interrupt mask flag
IE:
MK:
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10.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following four types of registers.
• Interrupt request flag registers 0 and 1 (IF0 and IF1)
• Interrupt mask flag registers 0 and 1 (MK0 and MK1)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
Table 10-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Table 10-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Signal
INTWDT
Interrupt Request Flag
Interrupt Mask Flag
WDTIF
PIF0
WDTMK
PMK0
INTP0
INTP1
PIF1
PMK1
INTP2
PIF2
PMK2
INTSR20/INTCSI20
INTST20
INTTM80
INTTM90
SRIF20
STIF20
TMIF80
TMIF90
SRMK20
STMK20
TMMK80
TMMK90
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(1) Interrupt request flag registers 0 and 1 (IF0 and IF1)
An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the related
instruction is executed. It is cleared to 0 when the interrupt request is acknowledged, when a RESET signal
is input, or when a related instruction is executed.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 and IF1 to 00H.
Figure 10-2. Format of Interrupt Request Flag Register
7
0
7
0
6
0
6
0
<5> <4> <3> <2> <1> <0>
STIF20 SRIF20 PIF2 PIF1 PIF0 WDTIF
Symbol
IF0
Address
FFE0H
After reset
00H
R/W
R/W
5
0
4
0
3
0
2
0
<1> <0>
IF1
TMIF90 TMIF80
FFE1H
00H
R/W
××IF×
Interrupt request flag
No interrupt request signal has been issued.
An interrupt request signal has been issued; an interrupt request has been made.
0
1
Cautions 1. Bits 6 and 7 of IF0 and bits 2 to 7 of IF1 must all be set to 0.
2. The WDTIF flag can be read- and write-accessed only when the watchdog timer is
being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in
watchdog timer mode 1 or 2.
3. When port 2 is being used as an output port, and its output level is changed, an interrupt
request flag is set, because this port is also used as an external interrupt input. To use
port 2 in output mode, therefore, the interrupt mask flag must be preset to 1.
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(2) Interrupt mask flag registers 0 and 1 (MK0 and MK1)
The interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 and MK1 to FFH.
Figure 10-3. Format of Interrupt Mask Flag Register
7
6
1
6
1
<5> <4> <3> <2> <1> <0>
STMK20 SRMK20 PMK2 PMK1 PMK0 WDTMK
Symbol
MK0
Address
FFE4H
After reset
FFH
R/W
R/W
1
7
5
4
3
2
1
<1> <0>
MK1
1
1
1
1
TMMK90 TMMK80
FFE5H
FFH
R/W
××MK
Interrupt handling control
0
1
Enables interrupt handling.
Disables interrupt handling.
Cautions 1. Bits 6 and 7 of MK0 and bits 2 to 7 of MK1 must all be set to 1.
2. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to
read the WDTMK flag results in an undefined value being detected.
3. When port 2 is being used as an output port, and its output level is changed, an
interrupt request flag is set, because this port is also used as an external interrupt
input. To use port 2 in output mode, therefore, the interrupt mask flag must be preset
to 1.
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(3) External interrupt mode register 0 (INTM0)
INTM0 is used to specify a valid edge for INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 10-4. Format of External Interrupt Mode Register 0
Symbol
7
6
5
4
3
2
1
0
0
0
Address
FFECH
After reset
00H
R/W
R/W
INTM0 ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20
INTP2 valid edge selection
INTP1 valid edge selection
INTP0 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES11 ES10
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES01 ES00
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Bits 0 and 1 must both be set to 0.
2. Before setting INTM0, set the corresponding interrupt mask flag to 1 to disable
interrupts.
To enable interrupts, clear to 0 the corresponding interrupt request flag, then the
corresponding interrupt mask flag.
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(4) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the
interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.
The PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
RESET input sets PSW to 02H.
Figure 10-5. Program Status Word Configuration
Symbol
PSW
7
6
Z
5
0
4
3
0
2
0
1
1
0
After reset
02H
IE
AC
CY
Used in the execution of ordinary instructions
IE
0
Whether to enable/disable interrupt acknowledgement
Disabled
Enabled
1
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10.4 Interrupt Processing Operation
10.4.1 Non-maskable interrupt request acknowledgement operation
The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order,
the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 10-6 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure
10-7 shows the timing of non-maskable interrupt request acknowledgement.
acknowledgement operation if multiple non-maskable interrupts are generated.
Figure 10-8 shows the
Caution During a non-maskable interrupt service program execution, do not input another non-
maskable interrupt request; if it is input, the service program will be interrupted and the new
interrupt request will be acknowledged.
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Figure 10-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
Overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing is started
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 10-7. Timing of Non-Maskable Interrupt Request Acknowledgement
Interrupt servicing
program
Saving PSW and PC, and
jump to interrupt processing
CPU processing
WDTIF
Instruction
Instruction
Figure 10-8. Acknowledgement of Non-Maskable Interrupt Request
Main routine
First interrupt processing
NMI request
(second)
NMI request
(first)
Second interrupt processing
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10.4.2 Maskable interrupt request acknowledgement operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown
in Table 10-3.
See Figures 10-10 and 10-11 for the interrupt request acknowledgement timing.
Table 10-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
9 clocks
Maximum TimeNote
19 clocks
Note The wait time is maximum when an interrupt
request is generated immediately before BT and
BF instruction.
1
fCPU
Remark 1 clock:
(fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
Figure 10-9 shows the algorithm of interrupt requests acknowledgement.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
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Figure 10-9. Interrupt Request Acknowledgement Processing Algorithm
Start
No
××IF = 1 ?
Yes (Interrupt request generated)
No
××MK = 0 ?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1 ?
Yes
Vectored interrupt
servicing
××IF:
Interrupt request flag
××MK: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)
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Figure 10-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r)
8 clocks
Clock
Saving PSW and PC, jump
to interrupt processing
Interrupt servicing program
CPU
MOV A,r
Interrupt
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
the interrupt is acknowledged after the instruction under execution is complete. Figure 10-10 shows an example of
the interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement
processing is performed after the MOV A,r instruction is executed.
Figure 10-11. Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Set at Last
Clock During Instruction Execution)
8 clocks
Clock
Interrupt
Saving PSW and PC, jump
to interrupt processing
servicing
CPU
NOP
MOV A,r
program
Interrupt
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgement
processing starts after the next instruction is executed. Figure 10-11 shows an example of the interrupt
acknowledgement timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In
this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acknowledgement
processing is performed.
Caution Interrupt requests are held pending while interrupt request flag register 0 or 1 (IF0 or IF1) or
interrupt mask flag register 0 or 1 (MK0 or MK1) is being accessed.
10.4.3 Multiple interrupt servicing
Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being processed can
be performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing
is performed according to the priority assigned to each interrupt request in advance (see Table 10-1).
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Figure 10-12. Example of Multiple Interrupts
Example 1. A multiple interrupt is acknowledged
INTxx servicing
INTyy servicing
Main processing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
The EI instruction is issued before each interrupt request acknowledgement, and the interrupt request
acknowledgement enable state is set.
Example 2. Multiple interrupts are not generated because interrupts are not enabled
INTxx servicing
INTyy servicing
Main processing
EI
IE = 0
INTyy is kept pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is reserved and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgement disabled
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10.4.4 Interrupt request reserve
Some instructions may reserve the acknowledgement of an instruction request until the completion of the
execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and
external interrupt) is generated during the execution. The following shows such instructions (interrupt request
reserve instruction).
• Manipulation instruction for interrupt request flag registers 0 and 1 (IF0 and IF1)
• Manipulation instruction for interrupt mask flag registers 0 and 1 (MK0 and MK1)
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CHAPTER 11 STANDBY FUNCTION
11.1 Standby Function and Configuration
11.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. HALT mode stops the operation clock of the CPU.
The system clock oscillator continues oscillating. This mode does not reduce the current consumption as
much as STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The current consumption of the CPU can be substantially reduced in
this mode.
The low voltage (VDD = 1.8 V max.) of the data memory can be retained. Therefore, this mode is useful for
retaining the contents of the data memory at an extremely low current consumption.
STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after STOP mode has
been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting standby mode are
all retained. In addition, the statuses of the output latches of the I/O ports and output buffers are also retained.
Caution To set STOP mode, be sure to stop the operations of the peripheral hardware, and then execute
the STOP instruction.
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11.1.2 Standby function control register
The wait time after STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with
the oscillation stabilization time selection register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 215/fX, instead of
217/fX.
Figure 11-1. Format of Oscillation Stabilization Time Selection Register
6
0
5
0
4
0
3
0
2
1
0
Address
After reset
04H
R/W
R/W
Symbol
OSTS
7
0
OSTS2
OSTS1
OSTS0 FFFAH
OSTS2 OSTS1
OSTS0
Oscillation stabilization time selection
212/f
215/f
217/f
X
0
0
1
0
1
0
0
0
0
µ
(819 s)
X
X
(6.55 ms)
(26.2 ms)
Other than above
Setting prohibited
Caution The wait time after STOP mode is released does not include the time from STOP mode release
to clock oscillation start ("a" in the figure below), regardless of release by RESET input or by
interrupt generation.
STOP mode release
X1 pin voltage
Waveform
a
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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11.2 Operation of Standby Function
11.2.1 HALT mode
(1) HALT mode
HALT mode is set by executing the HALT instruction.
The operation statuses in HALT mode are shown in the following table.
Table 11-1. Operation Statuses in HALT Mode
Item
HALT Mode Operation Status
System clock oscillation enabled
Clock supply to CPU stopped
System clock generator
CPU
Operation disabled
Port (output latch)
16-bit timer 90
Remains in the state existing before the selection of HALT mode
Operation enabled
8-bit timer/event counter 80
Watchdog timer
Serial interface 20
External interrupt
Operation enabled
Operation enabled
Operation enabled
Operation enabledNote
Note Maskable interrupt that is not masked
(2) Releasing HALT mode
HALT mode can be released by the following three sources.
(a) Releasing by unmasked interrupt request
HALT mode is released by an unmasked interrupt request. In this case, if interrupt request
acknowledgement is enabled, vectored interrupt processing is performed. If interrupt acknowledgement
is disabled, the instruction at the next address is executed.
Figure 11-2. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operating
mode
HALT mode
Operating mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case where the interrupt request that has released standby
mode is acknowledged.
2. The wait time is as follows.
• When vectored interrupt processing is performed:
9 to 10 clocks
• When vectored interrupt processing is not performed: 1 to 2 clocks
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(b) Releasing by non-maskable interrupt request
HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt
processing is performed.
(c) Releasing by RESET input
When HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as the ordinary reset operation, and program execution starts.
Figure 11-3. Releasing HALT Mode by RESET Input
Wait
HALT
instruction
(215/f
: 6.55 ms)
X
RESET
signal
Oscillation
stabilization
wait status
Reset
period
Operating
mode
Operating
mode
HALT mode
Oscillation
Oscillation
stop
Oscillation
Clock
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 11-2. Operation After Releasing HALT Mode
Releasing Source
MK××
IE
0
Operation
Maskable interrupt request
0
0
1
−
−
Executes next address instruction.
Executes interrupt servicing.
Retains HALT mode.
1
×
Non-maskable interrupt request
RESET input
×
Executes interrupt servicing.
Reset processing
−
×: Don't care
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11.2.2 STOP mode
(1) Setting and operation status of STOP mode
STOP mode is set by executing the STOP instruction.
Caution Because standby mode can be released by an interrupt request signal, standby mode is
released as soon as it is set if there is an interrupt source whose interrupt request flag is
set and interrupt mask flag is reset. When STOP mode is set, therefore, HALT mode is set
immediately after the STOP instruction has been executed, the wait time set by the
oscillation stabilization time selection register (OSTS) elapses, and then the operation
mode is set.
The operation statuses in STOP mode are shown in the following table.
Table 11-3. Operation Statuses in STOP Mode
Item
Clock generator
STOP Mode Operation Status
System clock oscillation stopped
CPU
Operation stopped
Port (output latch)
16-bit timer 90
Remains in the state existing before STOP mode was set
Operation stopped
8-bit timer/event counter 80
Watchdog timer
Serial interface 20
External interrupt
Operation enabled only when TI80 is selected for count clock
Operation stopped
Operation enabled only when external clock is input to serial clock
Operation enabledNote
Note Maskable interrupt that is not masked
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(2) Releasing STOP mode
STOP mode can be released by the following two sources.
(a) Releasing by unmasked interrupt request
STOP mode can be released by an unmasked interrupt request. In this case, vectored interrupt
processing is performed if interrupt acknowledgement is enabled after the oscillation stabilization time
has elapsed. If interrupt acknowledgement is disabled, the instruction at the next address is executed.
Figure 11-4. Releasing STOP Mode by Interrupt
Wait
STOP
instruction
(time set by OSTS)
Standby
release signal
Oscillation stabilization
wait status
Operating
mode
Operating
mode
STOP mode
Oscillation
stop
Oscillation
Oscillation
Clock
Remark The broken lines indicate the case where the interrupt request that has released standby
mode is acknowledged.
(b) Releasing by RESET input
When STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 11-5. Releasing STOP Mode by RESET Input
Wait
STOP
instruction
(215/f
: 6.55 ms)
X
RESET
signal
Oscillation
stabilization
wait status
Operating
mode
Reset
period
Operating
mode
STOP mode
Oscillation
Oscillation
stop
Oscillation
Clock
Remarks 1. fX: System clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Table 11-4. Operation After Releasing STOP Mode
Releasing Source
MK××
IE
0
Operation
Maskable interrupt request
0
0
1
−
Executes next address instruction.
Executes interrupt servicing.
Retains STOP mode.
1
×
RESET input
−
Reset processing
×: Don't care
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CHAPTER 12 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input by RESET signal input
(2) Internal reset by watchdog timer runaway time detection
External and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by reset signal input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each
hardware is set to the status shown in Table 12-1. Each pin is high impedance during reset input or during the
oscillation stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 12-2
through 12-4).
Cautions 1. For an external reset, input a low level of 10 µs or more to the RESET pin.
2. When STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pins become high impedance.
Figure 12-1. Block Diagram of Reset Function
RESET
Reset signal
Reset controller
Over-
flow
Interrupt function
Count clock
Watchdog timer
Stop
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Figure 12-2. Reset Timing by RESET Input
X1
Reset period
(oscillation
stops)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Normal operation
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 12-3. Reset Timing by Watchdog Timer Overflow
X1
Reset period
(oscillation
continues)
Oscillation
stabilization
time wait
Normal operation
(reset processing)
Normal operation
Watchdog
timer overflow
Internal
reset signal
Hi-Z
Port pin
Figure 12-4. Reset Timing by RESET Input in STOP Mode
X1
STOP instruction execution
Oscillation
Stop status
(oscillation
stops)
Reset period
(oscillation
stops)
Normal operation
(reset processing)
stabilization
time wait
Normal operation
RESET
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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Table 12-1. Status of Hardware After Reset
Hardware
Status After Reset
Program counter (PC)Note 1
Loaded with the contents of
the reset vector table
(0000H, 0001H)
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
Data memory
UndefinedNote 2
UndefinedNote 2
00H
General-purpose registers
Ports (P0 to P3) (output latch)
Port mode registers (PM0 to PM3)
FFH
Pull-up resistor option registers (PU0, PUB2)
00H
Oscillation stabilization time selection register (OSTS)
04H
16-bit timer
Timer counter (TM90)
0000H
FFFFH
00H
Compare register (CR90)
Control register (TMC90)
Capture register (TCP90)
Undefined
00H
8-bit timer/event counter
Timer counter (TM80)
Compare register (CR80)
Undefined
00H
Mode control register (TMC80)
Clock selection register (WDCS)
Mode register (WDTM)
Watchdog timer
Serial interface
00H
00H
Serial operation mode register (CSIM20)
Asynchronous serial interface mode register (ASIM20)
Asynchronous serial interface status register (ASIS20)
Baud rate generator control register (BRGC20)
Transmission shift register (TXS20)
Receive buffer register (RXB20)
Request flag registers (IF0, IF1)
Mask flag registers (MK0, MK1)
External interrupt mode register (INTM0)
00H
00H
00H
00H
FFH
Undefined
00H
Interrupts
FFH
00H
Notes 1. While a reset signal is being input, and during the oscillation stabilization period, the contents of the
PC will be undefined, while the remainder of the hardware will be the same as after the reset.
2. In standby mode, the RAM enters the hold state after a reset.
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CHAPTER 13 µPD78F9076
The µPD78F9076 replaces the internal ROM of the µPD789071, 789072, and 789074 with flash memory. The
differences between the flash memory and the mask ROM versions are shown in Table 13-1.
Table 13-1. Differences Between Flash Memory and Mask ROM Versions
Item
Flash Memory
Version
Mask ROM Version
µPD78F9076
Flash memory
16 KB
µPD789071
Mask ROM
2 KB
µPD789072
µPD789074
Internal memory
ROM structure
ROM capacity
4 KB
8 KB
High-speed RAM 256 bytes
Provided
VPP pin
Electrical characteristics
Not provided
Varies depending on flash memory or mask ROM version.
Caution The flash memory and mask ROM versions have different noise immunity and noise radiation
characteristics. Do not use ES versions for evaluation when considering switching from flash
memory versions to those using mask ROM upon the transition from preproduction to mass-
production. CS versions (mask ROM versions) should be used in this case.
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CHAPTER 13 µPD78F9076
13.1 Flash Memory Programming
The on-chip program memory in the µPD78F9076 is flash memory.
The flash memory can be written with the µPD78F9076 mounted on the target system (on-board write). Connect
the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target
system to write the flash memory.
Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
13.1.1 Selecting communication mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a
communication mode from those listed in Table 13-2. To select a communication mode, the format shown in Figure
13-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 13-2.
Table 13-2. Communication Mode
Communication Mode
3-wire serial I/O
Pins UsedNote 1
Number of VPP Pulses
SCK20/ASCK20/P20
0
SO20/TxD20/P21
SI20/RxD20/P22
UART
TxD20/SO20/P21
RxD20/SI20/P22
8
Pseudo 3-wire modeNote 2
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)
12
Notes 1. Shifting to the flash memory programming mode sets all pins not used for flash memory programming
to the same state as the immediately after reset. If the external device connected to each port does
not acknowledge the state immediately after reset, pin handling such as connecting to VDD or VSS via a
resistor is required.
2. Serial transfer is performed by controlling a port by software.
Caution Be sure to select a communication mode depending on the number of VPP pulses shown in
Table 13-2.
Figure 13-1. Format of Communication Mode Selection
10 V
VPP
VDD
1
2
n
V
SS
V
DD
RESET
V
SS
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CHAPTER 13 µPD78F9076
13.1.2 Function of flash memory programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to
the flash memory are performed. Table 13-3 shows the major functions of flash memory programming.
Table 13-3. Major Functions of Flash Memory Programming
Function
Batch erase
Description
Erases all contents of memory.
Batch blank check
Data write
Checks erased state of entire memory.
Writes to flash memory based on write start address and number of data written (number of bytes).
Compares all contents of memory with input data.
Batch verify
13.1.3 Flashpro III connection example
The connection between the Flashpro III and the µPD78F9076 differs depending on the communication mode (3-
wire serial I/O, UART, or pseudo 3-wire mode). Figures 13-2 to 13-4 show the connection in the respective modes.
Figure 13-2. Flashpro III Connection Example in 3-Wire Serial I/O Mode
µ
Flashpro III
PD78F9076
V
PPnNote 1
V
V
PP
DD
V
DD
RESET
RESET
CLKNote 2
SCK
SO
X1
SCK20
SI20
SO20
SI
GND
V
SS
Notes 1. n = 1, 2
2. Connect the CLK pin when the system clock is input from the Flashpro III. When the resonator has
already been connected to the X1 pin, there is no need to connect the CLK pin to X1 pin.
Caution Be sure to connect the VDD pin to the VDD pin of Flashpro III, even if the power supply is
connected to the pin. When using the power supply, apply the voltage before starting
programming.
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CHAPTER 13 µPD78F9076
Figure 13-3. Flashpro III Connection Example in UART Mode
Flashpro III
µPD78F9076
V
PPnNote 1
V
V
PP
DD
V
DD
RESET
CLKNote 2
SO
RESET
X1
RxD20
TxD20
SI
GND
V
SS
Notes 1. n = 1, 2
2. Connect the CLK pin when the system clock is input from the Flashpro III. When the resonator has
already been connected to the X1 pin, there is no need to connect the CLK pin to X1 pin.
Caution Be sure to connect the VDD pin to the VDD pin of Flashpro III, even if the power supply is
connected to the pin. When using the power supply, apply the voltage before starting
programming.
Figure 13-4. Flashpro III Connection Example in Pseudo 3-Wire Mode
Flashpro III
µ
PD78F9076
V
PPnNote 1
V
V
PP
DD
V
DD
RESET
CLKNote 2
SCK
RESET
X1
P00 (Serial clock)
P02 (Serial input)
P01 (Serial output)
SO
SI
GND
V
SS
Notes 1. n = 1, 2
2. Connect the CLK pin when the system clock is input from the Flashpro III. When the resonator has
already been connected to the X1 pin, there is no need to connect the CLK pin to X1 pin.
Caution Be sure to connect the VDD pin to the VDD pin of Flashpro III, even if the power supply is
connected to the pin. When using the power supply, apply the voltage before starting
programming.
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CHAPTER 13 µPD78F9076
13.1.4 Setting Example with Flashpro III (PG-FP3)
When writing data to the flash memory by using the Flashpro III (PG-FP3), set as follows.
<1> Load the parameter file.
<2> Select a serial mode and serial clock by using the type command.
<3> An example of setting PG-FP3 is shown below.
Table 13-4. Setting Example with PG-FP3
Communication Mode
3-wire serial I/O
Setting Example with PG-FP3
SIO-ch0
Number of VPP PulsesNote 1
COMM PORT
CPU CLK
0
On Target Board
In Flashpro
4.1943 MHz
1.0 MHz
On Target Board
SIO CLK
In Flashpro
SIO CLK
4.0 MHz
1.0 MHz
UART
COMM PORT
CPU CLK
UART-ch0
On Target Board
4.91 MHz
9,600 bpsNote 2
Port A
8
On Target Board
UART BPS
COMM PORT
CPU CLK
Pseudo 3-wire mode
12
On Target Board
In Flashpro
4.1943 MHz
1 kHz
On Target Board
SIO CLK
In Flashpro
SIO CLK
4.0 MHz
1 kHz
Notes 1. The number of VPP pulses supplied from the Flashpro III when serial communication is initialized.
These pulse counts determine the pins used for communication.
2. Select 9,600 bps, 19,200 bps, 38,400 bps, or 76,800 bps.
Remark COMM PORT: Selects serial port.
SIO CLK:
CPU CLK:
Selects serial clock frequency.
Selects source of CPU clock to be input.
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CHAPTER 13 µPD78F9076
13.1.5 On-board pin connections
When programming on the target system, provide a connector on the target system to connect to the dedicated
flash programmer.
There may be cases in which an on-board function that switches from the normal operation mode to flash
memory programming mode is required.
<VPP pin>
Input 0 V to the VPP pin in the normal operation mode. A writing voltage of 10.0 V (TYP.) is supplied to the VPP
pin in the flash memory programming mode. Therefore, connect the VPP pin as follows.
(1) Connect a pull-down resistor of RVPP = 10 kΩ to the VPP pin.
(2) Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND.
The following shows an example of VPP pin connection.
Figure 13-5 VPP Pin Connection Example
PD78F9076
µ
Connection pin of dedicated flash programmer
VPP
Pull-down resistor (RVPP
)
<Serial interface pins>
The following shows the pins used by each serial interface.
Serial Interface
3-wire serial I/O
UART
Pins Used
SI20/SO20/SCK20
RxD0/TxD0
Pseudo 3-wire
P00/P01/P02
Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that
is connected to another device is connected to the dedicated flash programmer.
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CHAPTER 13 µPD78F9076
(1) Signal conflict
A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin
(input) connected to another device (output). To prevent this signal conflict, isolate the connection with the
other device or put the other device in the output high impedance status.
Figure 13-6. Signal Conflict (Serial Interface Input Pin)
µ
PD78F9076
Input pin
Connection pin of dedicated flash
programmer
Signal conflict
Other device
Output pin
In the flash memory programming mode, the signal
output by another device and the signal sent by the
dedicated flash programmer conflict. To prevent this,
isolate the signal on the device side.
(2) Malfunction of another device
When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or
output) connected to another device (input), a signal may be output to the device, causing a malfunction.
To prevent such malfunction, isolate the connection with other device or set so that the input signal to the
device is ignored.
Figure 13-7. Malfunction of Another Device
µ
PD78F9076
Pin
Connection pin of dedicated flash
programmer
Other device
Input pin
If the signal output by the
flash memory programming mode, isolate the signal on the device side.
µ
PD78F9076 affects another device in the
µ
PD78F9076
Pin
Connection pin of dedicated flash
programmer
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device, isolate the signal on the device side.
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CHAPTER 13 µPD78F9076
<RESET pin>
When the reset signal of the dedicated flash programmer is connected to the RESET signal connected to the
reset signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the
connection with the reset signal generator.
If a reset signal is input from the user system in the flash memory programming mode, a normal programming
operation will not be performed. Do not input signals other than reset signals from the dedicated flash
programmer during this period.
Figure 13-8. Signal Conflict (RESET Pin)
µ
PD78F9076
RESET
Connection pin of dedicated
flash writer
Signal conflict
Reset signal generator
Output pin
In the flash memory programming mode, the signal output
by the reset signal generator and the signal output by the
dedicated flash writer conflict, therefore, isolate the
signal on the reset signal generator side
<Port pins>
Shifting to the flash memory programming mode sets all the pins except those used for flash memory
programming communication to the status immediately after reset.
Therefore, if the external device does not acknowledge an initial status such as the output high impedance
status, connect the external device to VDD or VSS via a resistor.
<Oscillation pins>
When using an on-board clock, connection of X1 and X2 must conform to the methods in the normal operation
mode.
When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board main
oscillator disconnected, and leave the X2 pin open.
<Power supply>
To use the power output of the flash programmer, connect the VDD and VSS pins to VDD and GND of the flash
programmer, respectively.
To use the on-board power supply, connection must conform to that in the normal operation mode. However,
because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be
connected.
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CHAPTER 14 INSTRUCTION SET OVERVIEW
This chapter lists the instruction set of the µPD789074 Subseries. For details of the operation and machine
language (instruction code) of each instruction, refer to 78K/0S Series User's Manual Instructions (U11047E).
14.1 Operation
14.1.1 Operand identifiers and description methods
Operands are described in the "Operand" column of each instruction in accordance with the description method
of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !:
Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 14-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark For symbols of special function registers, see Table 3-3 Special Function Registers.
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14.1.2 Description of "Operation" column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS:
( ):
Flag indicating non-maskable interrupt servicing in progress
Memory contents indicated by address or register contents in parentheses
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
×H, ×L:
∧:
∨:
Logical sum (OR)
∨:
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
14.1.3 Description of "Flag" column
(Blank): Unchanged
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is stored
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CHAPTER 14 INSTRUCTION SET OVERVIEW
14.2 Operation List
Mnemonic
MOV
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r Note 1
(saddr) ← byte
sfr ← byte
A ← r
r, A Note 1
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
×
×
×
×
×
×
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL + byte]
[HL + byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
A, r Note 2
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A, [HL]
A, [HL, byte]
A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 14 INSTRUCTION SET OVERVIEW
Mnemonic
MOVW
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rp Note
rp, AX Note
AX, rp Note
A, #byte
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
rp ← AX
XCHW
ADD
AX ↔ rp
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
ADDC
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
SUB
saddr, #byte
A, r
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, !addr16
A, [HL]
A, [HL + byte]
A, CY ← A − (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic
SUBC
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A ∧ (HL + byte)
A ← A ∨ byte
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A ∨ (HL + byte)
A ← A ∨ byte
XOR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL + byte]
A ← A ∨ (HL + byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 14 INSTRUCTION SET OVERVIEW
Mnemonic
CMP
Operand
Bytes Clocks
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
A − byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
ADDW
SUBW
CMPW
INC
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r + 1
DEC
saddr
rp
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
×
×
×
×
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
PSW.bit ← 1
×
×
×
×
×
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
×
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
×
CY
CY ← 0
CY
CY ← CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 14 INSTRUCTION SET OVERVIEW
Mnemonic
Operand
Bytes Clocks
Operation
Flag
Z
AC CY
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
PSW
4
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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14.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte
A
r
sfr
saddr !addr16
PSW
MOV
[DE]
[HL]
$addr16
1
None
[HL + byte]
A
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
ROL
ADD
ADDC
SUB
SUBC
AND
OR
RORC
ROLC
ADDC
SUB
SUBC
XOR
CMP
AND
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL + byte]
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
sp
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16
None
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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CHAPTER 14 INSTRUCTION SET OVERVIEW
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
VPP
VI
Conditions
Ratings
−0.3 to +6.5
−0.3 to +10.5
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
−10
Unit
V
µPD78F9076 only
V
Input voltage
V
Output voltage
Output current, high
VO
V
IOH
Per pin
mA
mA
mA
mA
°C
°C
°C
°C
Total for all pins
Per pin
−30
Output current, low
IOL
30
Total for all pins
During normal operation
During flash memory programming
Mask ROM version
µPD78F9076
160
Operating ambient temperature
Storage temperature
TA
−40 to +85
10 to 40
Tstg
−65 to +150
−40 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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System Clock Oscillator Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
Ceramic
Oscillation frequency
(fX)Note 1
VDD = oscillation voltage
range
1.0
5.0
MHz
V
SS X1
X2
X2
X2
resonator
C1
C2
C2
Oscillation stabilization
timeNote 2
After VDD reaches oscillation
voltage range MIN.
4
ms
Crystal
Oscillation frequency
(fX)Note 1
1.0
5.0
MHz
V
SS X1
C1
resonator
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
VDD = 1.8 to 5.5 V
10
30
ms
X1 input frequency (fX)Note 1
1.0
85
5.0
MHz
ns
X1
External
clock
X1 input high-/low-level width
(tXH, tXL)
500
X1 input frequency (fX)Note 1
VDD = 2.7 to 5.5 V
1.0
85
5.0
MHz
ns
X1
X2
X1 input high-/low-level width VDD = 2.7 to 5.5 V
(tXH, tXL)
500
OPEN
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator that
stabilizes oscillation within the oscillation wait time.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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Recommended Oscillator Constant
Ceramic resonator (TA = –45 to +85°C) (Mask ROM version)
Manufacturer
Part Number
Frequency
(MHz)
Recommended Circuit
Constant (pF)
Oscillation Voltage Range
(VDD)
Remarks
C1
C2
MIN.
1.9
MAX.
5.5
Rd = 1.0
kΩ
Murata Mfg.
Co., Ltd.
CSB1000JNote
1.0
2.0
100
100
CSBF1000JNote
CSTLS2M00G56-B0
CSTCC2.00MG0H6
CSTS0400MG03
CSTCR4M00G53-R0
CSTS0419MG03
CSTCR4M19MG03
CSTS0491MG03
CSTCR4M91G53-R0
CSTS0500MG03
CSTCR5M00G53-R0
−
−
1.8
5.5
On-chip
capacitor
4.0
4.194
4.915
5.0
Note A limiting resistor (Rd = 1.0 kΩ) is required when CSB1000J or CSBF1000J (1.0 MHz) manufactured by
Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when
using one of the other recommended resonators.
X1
X2
CSB1000J,
CSBF1000J
Rd
C2
C1
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
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Ceramic resonator (TA = –45 to +85°C) (µPD78F9076)
Manufacturer
Part Number
Frequency
(MHz)
Recommended Circuit
Constant (pF)
Oscillation Voltage Range
(VDD)
Remarks
C1
C2
MIN.
2.1
MAX.
5.5
Rd = 1.0
kΩ
Murata Mfg.
Co., Ltd.
CSB1000JNote
1.0
2.0
100
100
CSBF1000JNote
CSTLS2M00G56-B0
CSTCC2.00MG0H6
CSTS0400MG03
CSTCR4M00G53-R0
CSTS0419MG03
CSTCR4M19MG03
CSTS0491MG03
CSTCR4M91G53-R0
CSTS0500MG03
CSTCR5M00G53-R0
−
−
1.9
5.5
On-chip
capacitor
4.0
4.194
4.915
5.0
2.0
5.5
Note A limiting resistor (Rd = 1.0 kΩ) is required when CSB1000J or CSBF1000J (1.0 MHz) manufactured by
Murata Mfg. Co., Ltd. is used as the ceramic resonator (see the figure below). This is not necessary when
using one of the other recommended resonators.
X1
X2
CSB1000J,
CSBF1000J
Rd
C2
C1
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
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DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IOH
Conditions
MIN.
TYP.
MAX.
−1
Unit
mA
mA
mA
mA
V
Output current,
high
Per pin
Total for all pins
Per pin
−15
Output current, low
IOL
10
Total for all pins
80
Input voltage, high
VIH1
P00 to P07, P10 to P15,
P30, P31
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0.7VDD
VDD
0.9VDD
VDD
V
VIH2
RESET, P20 to P27
0.8VDD
VDD
V
0.9VDD
VDD
V
VIH3
VIL1
X1, X2
VDD − 0.1
VDD
V
Input voltage, low
P00 to P07, P10 to P15,
P30, P31
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
0
V
VIL2
RESET, P20 to P27
0
V
0
V
VIL3
VOH
X1, X2
0
V
Output voltage,
high
VDD = 4.5 to 5.5 V, IOH = −1 mA
VDD = 1.8 to 5.5 V, IOH = −100 µA
VDD = 4.5 to 5.5 V, IOL = 10 mA
VDD = 1.8 to 5.5 V, IOL = 400 µA
VDD − 1.0
VDD − 0.5
V
V
Output voltage,
low
VOL
1.0
0.5
3
V
V
Input leakage
current, high
ILIH1
VIN = VDD
Pins other than X1,
X2
µA
ILIH2
ILIL1
X1, X2
20
µA
µA
Input leakage
current, low
VIN = 0 V
Pins other than X1,
X2
−3
ILIL2
ILOH
X1, X2
−20
µA
µA
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
VIN = 0 V
3
Output leakage
current, low
ILOL
−3
µA
kΩ
Software pull-up
resistor
R1
50
100
200
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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DC Characteristics (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IDD1
Conditions
MIN.
TYP.
1.3
MAX.
2.6
0.5
0.30
1
Unit
mA
mA
mA
mA
mA
mA
µA
Power supply
currentNote 1
(mask ROM
version)
5.0 MHz crystal oscillation VDD = 5.0 V 10%Note 2
operating mode
VDD = 3.0 V 10%Note 3
0.26
0.14
0.5
(C1 = C2 = 22 pF)
VDD = 2.0 V 10%Note 3
IDD2
IDD3
IDD1
IDD2
IDD3
5.0 MHz crystal oscillation VDD = 5.0 V 10%Note 2
HALT mode
VDD = 3.0 V 10%Note 3
0.17
0.08
0.1
0.35
0.2
10
(C1 = C2 = 22 pF)
VDD = 2.0 V 10%Note 3
STOP mode
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.05
0.05
4.0
5.0
3.0
15.0
5.0
3.0
5.0
2.5
1.0
10
µA
µA
Power supply
currentNote 1
5.0 MHz crystal oscillation VDD = 5.0 V 10%Note 2
mA
mA
mA
mA
mA
mA
µA
operating mode
VDD = 3.0 V 10%Note 3
1.0
(µPD78F9076)
(C1 = C2 = 22 pF)
VDD = 2.0 V 10%Note 3
0.8
5.0 MHz crystal oscillation VDD = 5.0 V 10%Note 2
0.8
HALT mode
VDD = 3.0 V 10%Note 3
0.5
(C1 = C2 = 22 pF)
VDD = 2.0 V 10%Note 3
0.3
STOP mode
0.1
VDD = 5.0 V 10%
VDD = 3.0 V 10%
VDD = 2.0 V 10%
0.05
0.05
5.0
3.0
µA
µA
Notes 1. The port current (including the current flowing through the on-chip pull-up resistor) is not included.
2. High-speed mode operation (when processor clock control register (PCC) is set to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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AC Characteristics
(1) Basic operation (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
Conditions
MIN.
0.4
TYP.
MAX.
Unit
µs
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
8
8
(Minimum instruction
execution time)
1.6
µs
MHz
kHz
µs
TI80 input
frequency
fTI
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
4
0
275
TI80 input high-
/low-level width
tTIH, tTIL
0.1
1.8
10
µs
Interrupt input high- tINTH, tINTL INTP0 to INTP2
/low-level width
µs
RESET input
tRSL
10
10
µs
µs
low-level width
CPT90 input high-
/low-level width
tCPH, tCPL
TCY vs VDD
60
10
µ
Guaranteed
operation range
1.0
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
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(2) Serial interface (TA = −40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK20...Internal clock)
Parameter
Symbol
tKCY1
Conditions
MIN.
800
TYP.
MAX.
Unit
SCK20 cycle time
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
ns
ns
ns
ns
3,200
tKCY1/2−50
tKCY1/2−150
150
SCK20 high-/low-
level width
tKH1, tKL1 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SI20 setup time
tSIK1
tKSI1
tKSO1
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(to SCK20 ↑)
500
SI20 hold time
400
ns
ns
ns
ns
(from SCK20 ↑)
600
SO20 output delay
R = 1 kΩ,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
0
250
time from SCK20 ↓
C = 100 pFNote
0
1,000
Note R and C are the load resistance and load capacitance of the SO20 output line.
(b) 3-wire serial I/O mode (SCK20...External clock)
Parameter
Symbol
tKCY2
Conditions
MIN.
800
3,200
400
1,600
100
150
400
600
0
TYP.
MAX.
Unit
SCK20 cycle time
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
ns
ns
ns
ns
SCK20 high-/low-
level width
tKH2, tKL2 VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
SI20 setup time
tSIK2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(to SCK20 ↑)
SI20 hold time
tKSI2
ns
ns
ns
ns
ns
ns
(from SCK20 ↑)
SO20 output delay
tKSO2
R = 1 kΩ,
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
300
1000
120
time from SCK20 ↓
C = 100 pFNote
0
SO20 setup time
(when using SS20,
to SS20 ↓)
tKAS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
400
SO20 disable time
(when using SS20,
from SS20↑)
tKDS2
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
240
800
ns
ns
Note R and C are the load resistance and load capacitance of the SO20 output line.
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(c) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
78,125
19,531
Unit
bps
bps
Transfer rate
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
(d) UART mode (External clock input)
Parameter
Symbol
tKCY3
Conditions
MIN.
800
TYP.
MAX.
Unit
ASCK20 cycle
time
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
ns
ns
3,200
400
ASCK20 high-/low- tKH3, tKL3 VDD = 2.7 to 5.5 V
ns
level width
VDD = 1.8 to 5.5 V
1,600
ns
bps
bps
Transfer rate
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
39,063
9,766
1
ASCK20 rise/fall
time
tR, tF
µs
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AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fX
t
XL
tXH
V
IH3 (MIN.)
IL3 (MAX.)
X1 input
V
TI Timing
1/fTI
tTIL
tTIH
TI80
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP2
RESET Input Timing
t
RSL
RESET
CPT90 Input Timing
tCPL
tCPH
CPT90
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Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK20
t
SIKm
t
KSIm
Input data
SI20
t
KSOm
Output data
SO20
Remark m = 1, 2
3-wire serial I/O mode (when using SS20):
SS20
tKAS2
tKDS2
SO20
Output data
UART mode (external clock input):
tKCY3
tKL3
tKH3
tR
tF
ASCK20
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Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T = −40 to +85°C)
A
Parameter
Symbol
VDDDR
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention power
supply voltage
Release signal set time
tSREL
tWAIT
0
µs
ms
ms
Oscillation stabilization
wait timeNote 1
Release by RESET
Release by interrupt request
215/fX
Note 2
Notes 1. Oscillation stabilization wait time is a time for stopping the CPU operation to prevent the unstable
operation when the oscillation is started.
2. Selection of 212/fX, 215/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remark fX: System clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
STOP mode
Operation mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
196
User's Manual U14801EJ2V0UD
CHAPTER 15 ELECTRICAL SPECIFICATIONS
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
fX
Conditions
VDD = 2.7 to 5.5 V
MIN.
1.0
TYP.
MAX.
5
Unit
MHz
MHz
mA
Operating frequency
VDD = 1.8 to 5.5 V
1.0
1.25
18
Write currentNote
(VDD pin)
IDDW
IPPW
IDDE
IPPE
When VPP supply
voltage = VPP1
During fX = 5.0 MHz
operation
Write currentNote
(VPP pin)
When VPP supply voltage = VPP1
7.5
18
mA
mA
mA
Erase currentNote
(VDD pin)
When VPP supply
voltage = VPP1
During fX = 5.0 MHz
operation
Erase currentNote
(VPP pin)
When VPP supply voltage = VPP1
100
Unit erase time
Total erase time
Write count
ter
0.5
1
1
1
20
s
tera
s
Times
V
Erase/write are regarded as 1 cycle
In normal operation
1
0
20
VPP supply voltage
VPP0
VPP1
0.2VDD
10.3
During flash memory programming
9.7
10.0
V
Note The port current (including the current that flows to the on-chip pull-up resistors) is not included.
197
User's Manual U14801EJ2V0UD
CHAPTER 16 PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30
16
detail of lead end
F
G
T
P
L
1
15
U
E
A
H
I
J
S
B
C
N
S
M
D
M
K
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
9.85 0.15
0.45 MAX.
0.65 (T.P.)
+0.08
0.24
D
−0.07
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
S30MC-65-5A4-2
198
User's Manual U14801EJ2V0UD
CHAPTER 17 RECOMMENDED SOLDERING CONDITIONS
The µPD789071, 789072, and 789074 should be soldered and mounted under the following recommended
conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 17-1. Surface Mounting Type Soldering Conditions
µPD789071MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD789072MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
µPD789074MC-×××-5A4: 30-pin plastic SSOP (7.62 mm (300))
Recommended Condition
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Time: 30 seconds max.
(at 210°C or higher), Count: Three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
(at 200°C or higher), Count: Three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count:
Once, Preheating temperature: 120°C max. (package surface
temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
−
µPD78F9076MC-5A4: 30-pin plastic SSOP (7.62 mm (300))
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Reflow time: 30 seconds max. (at 210°C or
higher), Number of reflow processes : 2 max., Exposure limit : 3 daysNote
(after that, prebaking is necessary at 125°C for 10 hours)
IR35-103-2
VP15-103-2
WS60-103-1
VPS
Package peak temperature: 215°C, Reflow time: 40 seconds max. (at 200°C or
higher), Number of reflow processes : 2 max., Exposure limit : 3 daysNote
(after that, prebaking is necessary at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C max. , Flow time: 10 seconds max.,
Number of flow processes: 1
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 3 daysNote (after that, prebaking is necessary at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
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User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789074 Subseries.
Figure A-1 shows development tools.
• Compatibility with PC98-NX Series
Unless stated otherwise, products which are supported for IBM PC/ATTM and compatibles can also be used
with the PC98-NX Series. When using the PC98-NX Series, therefore, refer to the explanations for IBM PC/AT
and compatibles.
• Windows
Unless stated otherwise, "Windows" refers to the following operating systems.
• Windows 3.1
• Windows 95, 98, 2000
• Windows NTTM Ver. 4.0
200
User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
·
Software package
Language processing software
Debugging software
·
·
·
·
Assembler package
C compiler package
Device file
·
·
Integrated debugger
System emulator
C compiler source fileNote 1
Control software
·
Project manager
(Windows version only)Note 2
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing tools
Flash programmer
In-circuit emulator
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. The C compiler source file is not included in the software package.
2. The project manager is included in the assembler package and is available only for Windows.
201
User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Various software tools for 78K/0S development are integrated in one package.
The following tools are included.
Software package
RA78K0S, CC78K0S, ID78K0-NS, SM78K0S, various device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µS×××× SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Medium
CD-ROM
PC-9800 series,
IBM PC/AT and compatibles
Japanese Windows
English Windows
Note Also operates under the DOS environment
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object code that can be executed by
microcontroller.
Assembler package
In addition, automatic functions to generate symbol table and optimize branch instructions are also
provided.
Used in combination with a device file (DF789076) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed by
microcontroller.
C compiler package
Used in combination with an assembler package (RA78K0S) and device file (DF789076) (both sold
separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows environment
by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789076Note 1
Device file
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
Part number: µS××××DF789076
CC78K0S-LNote 2
Source file of functions constituting object library included in C compiler package.
C compiler source file
Necessary for changing object library included in C compiler package according to customer's
specifications.
Since this is the source file, its working environment does not depend on any particular operating
system.
Part number: µS××××CC78K0S-L
Notes 1. DF789076 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
202
User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
Host Machine
PC-9800 series,
OS
Supply Media
3.5" 2HD FD
Japanese Windows
English Windows
Japanese Windows
English Windows
HP-UXTM (Rel.10.10)
IBM PC/AT and compatibles
BB13
AB17
BB17
3P17
3K17
CD-ROM
HP9000 series 700TM
SPARCstationTM
SunOSTM (Rel.4.1.1),
SolarisTM (Rel.2.5.1)
µS××××DF789076
µS××××CC78K0S-L
××××
AB13
BB13
3P16
3K13
3K15
Host Machine
OS
Supply Medium
PC-9800 series,
Japanese Windows
English Windows
HP-UX (Rel.10.10)
3.5" 2HD FD
IBM PC/AT and compatibles
HP9000 series 700
SPARCstation
DAT
SunOS (Rel.4.1.1),
Solaris (Rel.2.5.1)
3.5" 2HD FD
1/4" CGMT
A.3 Control Software
Control software provided for an efficient user program development in the Windows
environment. The project manager allows a series of tasks required for user program
development to be performed, including starting the editor, building, and starting the
debugger.
Project manager
<Caution>
The project manager is included in the assembler package (RA78K0S).
It cannot be used in an environment other than Windows.
203
User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
A.4 Flash Memory Writing Tools
Flashpro III
Flash programmer dedicated to microcontrollers incorporating flash memory.
(part number: FL-PR3, PG-FP3)
Flash writer
FA-30MC
Flash memory writing adapter. Used in connection with Flashpro III.
30-pin plastic SSOP (MC-5A4 type)
Flash memory writing adapter
Remark FL-PR3 and FA-30MC are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging hardware and software of application system using the
78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with
an AC adapter, emulation probe, and interface adapter for connecting the host machine.
In-circuit emulator
IE-78K0S-NS-A
In-circuit emulator with enhanced functions of the IE-78K0S-NS. The debug function is further
enhanced by adding a coverage function and enhancing the tracer and timer functions.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from a 100 to 240 VAC outlet.
IE-70000-98-IF-C
Interface adapter
Adapter required when using a PC-9800 series (except notebook type) as the host machine
(C bus supported).
IE-70000-CD-IF-A
PC card interface
PC card and interface cable required when using a notebook type PC as the host machine
(PCMICA socket supported).
IE-70000-PC-IF-C
Interface adapter
Adapter required when using an IBM PC/AT or compatible as the host machine (ISA bus
supported).
IE-70000-PCI-IF-A
Interface adapter
Adapter required when using a personal computer incorporating the PCI bus as the host
machine.
IE-789046-NS-EM1 + NP-K907 Emulation board for emulating the peripheral hardware inherent to the device.
Emulation board
Used in combination with an in-circuit emulator.
NP-36GS
Cable for connecting the in-circuit emulator and target system.
Emulation probe
Used in combination with the NGS-30 when supporting a 30-pin plastic SSOP (MC-5A4 type).
NGS-30
Conversion socket used to connect a target system board designed to allow mounting a 30-
pin plastic SSOP and the NP-36GS.
Conversion socket
Remark NP-36GS, NGS-30, and NP-K907 are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191)
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User's Manual U14801EJ2V0UD
APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
Integrated debugger
It has improved C-compatible debugging functions and can display the results of tracing with the
source program using an integrating window function that associates the source program,
disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789076) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
It can be used to debug the target system at C source level of assembler level while simulating
the operation of the target system on the host machine.
System simulator
Using SM78K0S, the logic and performance of the application can be verified independently of
hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used in combination with a device file (DF789076) (sold separately).
Part number: µS××××SM78K0S
DF789076Note
Device file
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S) (all sold
separately).
Part number: µS××××DF789076
Note DF789076 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
Host Machine
OS
Supply Medium
3.5" 2HD FD
PC-9800 series,
IBM PC/AT and compatibles
Japanese Windows
English Windows
Japanese Windows
English Windows
BB13
AB17
BB17
CD-ROM
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User's Manual U14801EJ2V0UD
APPENDIX B REGISTER INDEX
B.1 Register Name Index (Alphabetic Order)
16-bit capture register 90 (TCP90).........................................................................................................................79
16-bit compare register 90 (CR90).........................................................................................................................79
16-bit timer counter 90 (TM90)...............................................................................................................................79
16-bit timer mode control register 90 (TMC90) ......................................................................................................80
8-bit compare register 80 (CR80)...........................................................................................................................91
8-bit timer counter 80 (TM80).................................................................................................................................91
8-bit timer mode control register 80 (TMC80) ........................................................................................................92
[A]
[B]
Asynchronous serial interface mode register 20 (ASIM20)..........................................................113, 119, 122, 134
Asynchronous serial interface status register 20 (ASIS20)..........................................................................115, 123
Baud rate generator control register 20 (BRGC20)..............................................................................116, 124, 135
Buzzer output control register 90 (BZC90).............................................................................................................82
[E]
[I]
External interrupt mode register 0 (INTM0)..........................................................................................................149
Interrupt mask flag register 0, 1 (MK0, MK1) .......................................................................................................148
Interrupt request flag register 0, 1 (IF0, IF1) ........................................................................................................147
[O]
Oscillation stabilization time selection register (OSTS)........................................................................................159
[P]
Port 0 (P0) ............................................................................................................................................................59
Port 1 (P1) ............................................................................................................................................................60
Port 2 (P2) ............................................................................................................................................................61
Port 3 (P3) ............................................................................................................................................................65
Port mode register 0 (PM0)....................................................................................................................................66
Port mode register 1 (PM1)....................................................................................................................................66
Port mode register 2 (PM2)..............................................................................................................................66, 93
Port mode register 3 (PM3)..............................................................................................................................66, 83
Processor clock control register (PCC) ..................................................................................................................71
Pull-up resistor option register 0 (PU0) ..................................................................................................................67
Pull-up resistor option register B2 (PUB2) .............................................................................................................68
[R]
Receive buffer register 20 (RXB20) .....................................................................................................................111
206
User's Manual U14801EJ2V0UD
APPENDIX B REGISTER INDEX
[S]
[T]
Serial operation mode register 20 (CSIM20)................................................................................112, 119, 121, 133
Transmission shift register 20 (TXS20)................................................................................................................111
[W]
Watchdog timer clock selection register (WDCS) ................................................................................................104
Watchdog timer mode register (WDTM)...............................................................................................................105
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User's Manual U14801EJ2V0UD
APPENDIX B REGISTER INDEX
B.2 Register Symbol Index (Alphabetic Order)
[A]
[B]
[C]
ASIM20:
ASIS20 :
Asynchronous serial interface mode register 20 ......................................................113, 119, 122, 134
Asynchronous serial interface status register 20......................................................................115, 123
BRGC20: Baud rate generator control register 20............................................................................116, 124, 135
BZC90:
Buzzer output control register 90........................................................................................................82
CR80:
8-bit compare register 80....................................................................................................................91
16-bit compare register 90..................................................................................................................79
Serial operation mode register 20 ............................................................................112, 119, 121, 133
CR90:
CSIM20:
[I]
IF0:
Interrupt request flag register 0 ........................................................................................................147
Interrupt request flag register 1 ........................................................................................................147
External interrupt mode register 0 ....................................................................................................149
IF1:
INTM0:
[M]
MK0:
Interrupt mask flag register 0............................................................................................................148
Interrupt mask flag register 1............................................................................................................148
MK1:
[O]
OSTS:
Oscillation stabilization time selection register.................................................................................159
[P]
P0:
Port 0 ...............................................................................................................................................59
Port 1..................................................................................................................................................60
Port 2..................................................................................................................................................61
Port 3..................................................................................................................................................65
Processor clock control register .........................................................................................................71
Port mode register 0...........................................................................................................................66
Port mode register 1...........................................................................................................................66
Port mode register 2.....................................................................................................................66, 93
Port mode register 3.....................................................................................................................66, 83
Pull-up resistor option register 0.........................................................................................................67
Pull-up resistor option register B2 ......................................................................................................68
P1:
P2:
P3:
PCC:
PM0:
PM1:
PM2:
PM3:
PU0:
PUB2:
[R]
[T]
RXB20:
Receive buffer register 20 ................................................................................................................111
TCP90:
TM80:
16-bit capture register 90....................................................................................................................79
8-bit timer counter 80..........................................................................................................................91
16-bit timer counter 90........................................................................................................................79
8-bit timer mode control register 80....................................................................................................92
TM90:
TMC80:
208
User's Manual U14801EJ2V0UD
APPENDIX B REGISTER INDEX
TMC90:
TXS20:
16-bit timer mode control register 90..................................................................................................80
Transmission shift register 20...........................................................................................................111
[W]
WDCS:
WDTM:
Watchdog timer clock selection register...........................................................................................104
Watchdog timer mode register..........................................................................................................105
209
User's Manual U14801EJ2V0UD
APPENDIX C REVISION HISTORY
The following shows the revision history. “Chapter” refers to the chapters in the respective edition.
Edition
Description
Chapter
2nd edition
Change of µPD789071, 789072, 789074, and 78F9076 from
Throughout
under development to development complete.
Modification of description of VPP pin connection
CHAPTER 2 PIN FUNCTION
CHAPTER 6 16-BIT TIMER 90
Modification of Caution on rewriting CR90 in 6.4.1 Operation
as timer interrupt
Addition of description on reading receive data of UART
CHAPTER 9 SERIAL INTERFACE 20
Addition of Note on unused pins in Table 13-2
CHAPTER 13 µPD78F9076
Communication Mode
Addition of Note and Remark to Figures 13-2 Flashpro III
Connection Example in 3-Wire Serial I/O Mode, 13-3
Flashpro III Connection Example in UART Mode, and 13-4
Flashpro III Connection Example in Pseudo 3-Wire Mode
Modification of value of UART in Table 13-4 Setting Example
with PG-FP3
Addition of 13.1.5 On-board pin connections
Addition of electrical specifications
CHAPTER 15 ELECTRICAL
SPECIFICATIONS
Addition of package drawing
CHAPTER 16 PACKAGE DRAWING
Addition of recommended soldering conditions
CHAPTER 17 RECOMMENDED
SOLDERING CONDITIONS
Overall modification of description on development tools
Deletion of Embedded Software
APPENDIX A DEVELOPMENT
TOOLS
210
User's Manual U14801EJ2V0UD
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Please complete this form whenever
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