UPD789834GJ-XXX-UEN [NEC]
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144;
| 型号： | UPD789834GJ-XXX-UEN |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144 时钟 微控制器 ISM频段 外围集成电路 |
| 文件： | 总343页 (文件大小：2466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
User’s Manual
µPD789835, 789835A, 789835B
Subseries
8-Bit Single-Chip Microcontrollers
µPD789832
µPD789833
µPD789834
µPD789835
µPD78F9835
µPD789832A µPD789832B
µPD789833A µPD789833B
µPD789834A µPD789834B
µPD789835A µPD789835B
Document No. U15559EJ2V1UD00 (2nd edition)
Date Published October 2005 N CP(K)
2002
Printed in Japan
[MEMO]
2
User’s Manual U15559EJ2V1UD
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
3
User’s Manual U15559EJ2V1UD
FIP and EEPROM are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
4
User’s Manual U15559EJ2V1UD
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of March, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
5
User’s Manual U15559EJ2V1UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
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Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
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Tel: 408-588-6000
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J05.6
6
User’s Manual U15559EJ2V1UD
INTRODUCTION
Target Readers
This manual is intended for users who wish to understand the functions of the
µPD789835, 789835A, 789835B Subseries and to design and develop application
systems and programs using these microcontrollers.
The target devices are shown as follows:
µPD789835 Subseries:
µPD789832, 789833, 789834, 789835, 78F9835
µPD789835A Subseries: µPD789832A, 789833A, 789834A, 789835A, 78F9835
µPD789835B Subseries: µPD789832B, 789833B, 789834B, 789835B, 78F9835
Purpose
This manual is intended for users to understand the functions described in the
Organization below.
Organization
The µPD789835, 789835A, 789835B Subseries User’s Manual is divided into two
parts: this manual and instructions (common to the 78K/0S Series).
µPD789835, 789835A, 789835B
Subseries
78K/0S Series
Instructions
User’s Manual
User’s Manual
• Pin functions
• CPU function
• Internal block functions
• Interrupt functions
• Instruction set
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
How to Use This Manual
It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To understand the functions in general:
→ Read this manual in the order of the contents. The mark
revised points.
shows major
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable by #pragma sfr directive
in the C compiler.
• When you know a register name and want to confirm its details:
→ Read APPENDIX C REGISTER INDEX.
• To know the 78K/0S Series instruction function in detail:
→ Read 78K/0S Series Instructions User’s Manual (U11047E).
• To know the electrical specifications of the µPD789835, 789835A, 789835B
Subseries:
→ Read CHAPTER 22 ELECTRICAL SPECIFICATIONS.
User’s Manual U15559EJ2V1UD
7
Conventions
Data significance:
Active low representation:
Note:
Higher digits on the left and lower digits on the right
xxx (overscore over pin or signal name)
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numerical representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Generic names in this document indicate the following products.
µPD78983x:
µPD789832, 789833, 789834, 789835
µPD789832A, 789833A, 789834A, 789835A
µPD789832B, 789833B, 789834B, 789835B
µPD78983x, 78983xA, 78983xB
µPD78F9835
µPD78983xA:
µPD78983xB:
Mask ROM version:
Flash memory version:
The oscillation frequency of the system clock is regarded as fX for ceramic/crystal
oscillation, and regarded as fCC for an RC oscillation.
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U11047E
µPD789835, 789835A, 789835B Subseries User’s Manual
78K/0S Series Instructions User’s Manual
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
Document No.
RA78K0S Assembler Package
Operation
U16656E
U14877E
U11623E
U16654E
U14872E
U16768E
U15802E
Language
Structured Assembly Language
Operation
CC78K0S C Compiler
Language
SM78K Series Ver. 2.52 System Simulator
Operation
External Part User Open Interface
Specifications
ID78K0S-NS Ver. 2.52 Integrated Debugger
PM plus Ver. 5.10
Operation
U16584E
U16569E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U15559EJ2V1UD
8
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
IE-78K0S-NS In-Circuit Emulator
Document No.
U13549E
IE-78K0S-NS-A In-Circuit Emulator
U15207E
U16290E
IE-789835-NS-EM1 Emulation Board
Documents Related to Flash Memory Writing
Document Name
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
Document No.
U13502E
U15260E
Other Related Documents
Document Name
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Document No.
X13769X
Note
Quality Grades on NEC Semiconductor Devices
C11531E
C10983E
C11892E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U15559EJ2V1UD
9
CONTENTS
CHAPTER 1 GENERAL...........................................................................................................................25
1.1 Features ......................................................................................................................................25
1.2 Applications................................................................................................................................25
1.3 Ordering Information .................................................................................................................26
1.4 Pin Configuration (Top View)....................................................................................................27
1.5 78K/0S Series Lineup.................................................................................................................30
1.6 Block Diagram ............................................................................................................................33
1.7 Overview of Functions...............................................................................................................34
1.8 Differences Between µPD78983x, µPD78983xA, and µPD78983xB........................................35
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................36
2.1 List of Pin Functions..................................................................................................................36
2.2 Description of Pin Functions ....................................................................................................38
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
P00 to P07 (Port 0)........................................................................................................................38
P10, P11 (Port 1) ..........................................................................................................................38
P20 to P27 (Port 2)........................................................................................................................38
P30 to P37 (Port 3)........................................................................................................................39
P60 to P62 (Port 6)........................................................................................................................39
P80 to P87 (Port 8)........................................................................................................................39
LCD0 to LCD87.............................................................................................................................40
CAP0 to CAP3 ..............................................................................................................................40
VROUT0............................................................................................................................................40
2.2.10 VLC0 to VLC4....................................................................................................................................40
2.2.11 RESET ..........................................................................................................................................40
2.2.12 SEL ...............................................................................................................................................40
2.2.13 X1, X2 ...........................................................................................................................................40
2.2.14 CL1, CL2.......................................................................................................................................40
2.2.15 XT1, XT2.......................................................................................................................................40
2.2.16 VDD ................................................................................................................................................40
2.2.17 VSS ................................................................................................................................................40
2.2.18 VPP (µPD78F9835 only).................................................................................................................41
2.2.19 IC (mask ROM version only) .........................................................................................................41
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................42
CHAPTER 3 CPU ARCHITECTURE......................................................................................................45
3.1 Memory Space............................................................................................................................45
3.1.1
3.1.2
3.1.3
3.1.4
Internal program memory space....................................................................................................50
Internal data memory space..........................................................................................................51
Special function register (SFR) area .............................................................................................51
Data memory addressing ..............................................................................................................52
3.2 Processor Registers ..................................................................................................................57
3.2.1
Control registers............................................................................................................................57
User’s Manual U15559EJ2V1UD
10
3.2.2
3.2.3
General-purpose registers ............................................................................................................ 60
Special function registers (SFRs).................................................................................................. 61
3.3 Instruction Address Addressing..............................................................................................64
3.3.1
3.3.2
3.3.3
3.3.4
Relative addressing....................................................................................................................... 64
Immediate addressing................................................................................................................... 65
Table indirect addressing.............................................................................................................. 66
Register addressing ...................................................................................................................... 66
3.4 Operand Address Addressing..................................................................................................67
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
Direct addressing.......................................................................................................................... 67
Short direct addressing ................................................................................................................. 68
Special function register (SFR) addressing................................................................................... 69
Register addressing ...................................................................................................................... 70
Register indirect addressing.......................................................................................................... 71
Based addressing ......................................................................................................................... 72
Stack addressing .......................................................................................................................... 72
CHAPTER 4 PORT FUNCTIONS...........................................................................................................73
4.1 Port Functions............................................................................................................................73
4.2 Port Configuration .....................................................................................................................74
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Port 0 ............................................................................................................................................ 75
Port 1 ............................................................................................................................................ 76
Port 2 ............................................................................................................................................ 77
Port 3 ............................................................................................................................................ 81
Port 6 ............................................................................................................................................ 82
Port 8 ............................................................................................................................................ 83
4.3 Registers Controlling Port Function........................................................................................84
4.4 Port Function Operation............................................................................................................87
4.4.1
4.4.2
4.4.3
Writing to I/O port.......................................................................................................................... 87
Reading from I/O port ................................................................................................................... 87
Arithmetic operation of I/O port ..................................................................................................... 87
CHAPTER 5 CLOCK GENERATOR......................................................................................................88
5.1 Clock Generator Functions.......................................................................................................88
5.2 Clock Generator Configuration ................................................................................................88
5.3 Registers Controlling Clock Generator...................................................................................90
5.4 System Clock Oscillators..........................................................................................................93
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
Main system clock oscillator (crystal/ceramic oscillation).............................................................. 93
Main system clock oscillator (RC oscillation) ................................................................................ 93
Subsystem clock oscillator............................................................................................................ 94
Example of incorrect resonator connection................................................................................... 95
Divider........................................................................................................................................... 99
When no subsystem clock is used................................................................................................ 99
5.5 Clock Generator Operation.....................................................................................................100
5.6 Changing Setting of System Clock and CPU Clock.............................................................101
5.6.1
Time required for switching between system clock and CPU clock............................................. 101
User’s Manual U15559EJ2V1UD
11
5.6.2
Switching between system clock and CPU clock ........................................................................102
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82 .............................................................104
6.1 8-Bit Timer/Event Counters 80 to 82 Functions....................................................................104
6.2 8-Bit Timer/Event Counters 80 to 82 Configuration .............................................................104
6.3 Registers Controlling 8-Bit Timer/Event Counters 80 to 82 ................................................107
6.4 8-Bit Timer/Event Counters 80 to 82 Operation....................................................................111
6.4.1
6.4.2
6.4.3
Operation as interval timer ..........................................................................................................111
Operation as external event counter (timer 80 only)....................................................................114
Operation as square wave output (timer 82 only)........................................................................115
6.5 Cautions Related to 8-Bit Timer/Event Counters 80 to 82 ...................................................117
CHAPTER 7 8-BIT TIMERS 30, 40.....................................................................................................120
7.1 8-Bit Timers 30, 40 Functions .................................................................................................120
7.2 8-Bit Timers 30, 40 Configuration...........................................................................................121
7.3 Registers Controlling 8-Bit Timers 30, 40..............................................................................126
7.4 8-Bit Timers 30, 40 Operation .................................................................................................131
7.4.1
7.4.2
7.4.3
7.4.4
Operation as 8-bit timer counter..................................................................................................131
Operation as 16-bit timer counter................................................................................................139
Operation as carrier generator ....................................................................................................144
Operation as PWM output (timer 40 only) ...................................................................................148
7.5 Notes on Using 8-Bit Timers 30, 40........................................................................................150
CHAPTER 8 8-BIT REMOTE CONTROL TIMER 50 ........................................................................151
8.1 8-Bit Remote Control Timer 50 Functions.............................................................................151
8.2 8-Bit Remote Control Timer 50 Configuration.......................................................................151
8.3 Registers Controlling 8-Bit Remote Control Timer 50 .........................................................152
8.4 Operation of 8-Bit Remote Control Timer 50.........................................................................153
CHAPTER 9 SOUND GENERATOR...................................................................................................155
9.1 Functions of Sound Generator ...............................................................................................155
9.2 Configuration of Sound Generator.........................................................................................155
9.3 Registers Controlling Sound Generator................................................................................158
9.4 Setting of Sound Generator ....................................................................................................165
9.4.1
Basic operation of sound generator.............................................................................................165
9.5 Sound Generator Output Mode...............................................................................................167
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
General-purpose port mode ........................................................................................................168
Buzzer mode 0............................................................................................................................168
Buzzer mode 1............................................................................................................................169
Buzzer mode 2............................................................................................................................170
Buzzer mode 3............................................................................................................................171
Timing charts in respective buzzer modes ..................................................................................172
CHAPTER 10 WATCH TIMER..............................................................................................................173
User’s Manual U15559EJ2V1UD
12
10.1 Watch Timer Functions ...........................................................................................................173
10.2 Watch Timer Configuration.....................................................................................................174
10.3 Register Controlling Watch Timer..........................................................................................175
10.4 Watch Timer Operation ...........................................................................................................176
10.4.1 Operation as watch timer ............................................................................................................ 176
10.4.2 Operation as interval timer.......................................................................................................... 176
CHAPTER 11 WATCHDOG TIMER.....................................................................................................178
11.1 Watchdog Timer Functions ....................................................................................................178
11.2 Watchdog Timer Configuration..............................................................................................179
11.3 Registers Controlling Watchdog Timer.................................................................................180
11.4 Watchdog Timer Operation.....................................................................................................182
11.4.1 Operation as watchdog timer ...................................................................................................... 182
11.4.2 Operation as interval timer.......................................................................................................... 183
CHAPTER 12 8-BIT A/D CONVERTER (µPD78983xB, 78983xA, 78F9835 ONLY) ....................184
12.1 8-Bit A/D Converter Functions ...............................................................................................184
12.2 8-Bit A/D Converter Configuration.........................................................................................185
12.3 Registers Controlling 8-Bit A/D Converter............................................................................187
12.4 8-Bit A/D Converter Operation................................................................................................189
12.4.1 Basic operation of 8-bit A/D converter......................................................................................... 189
12.4.2 Input voltage and conversion result............................................................................................. 190
12.4.3 Operation mode of 8-bit A/D converter........................................................................................ 192
12.5 Cautions Related to 8-Bit A/D Converter...............................................................................193
CHAPTER 13 SERIAL INTERFACE....................................................................................................196
13.1 Serial Interface Functions.......................................................................................................196
13.2 Serial Interface Configuration ................................................................................................199
13.3 Registers Controlling Serial Interface ...................................................................................201
13.4 Serial Interface Operation.......................................................................................................208
13.4.1 Operation stop mode................................................................................................................... 208
13.4.2 Asynchronous serial interface (UART) mode.............................................................................. 210
13.4.3 3-wire serial I/O mode................................................................................................................. 221
CHAPTER 14 LCD CONTROLLER/DRIVER.......................................................................................224
14.1 Functions of LCD Controller/Driver .......................................................................................224
14.2 Configuration of LCD Controller/Driver.................................................................................224
14.3 Registers Controlling LCD Controller/Driver........................................................................226
14.4 Common and Segment Signals..............................................................................................230
14.5 Setting LCD Controller/Driver.................................................................................................233
14.5.1 Setting to start display................................................................................................................. 233
14.5.2 Setting to turn off display and stop boosting voltage................................................................... 233
14.6 LCD Display Data Memory......................................................................................................234
14.7 Display Modes..........................................................................................................................242
14.7.1 80 × 8 mode (1/8 duty)................................................................................................................ 242
User’s Manual U15559EJ2V1UD
13
14.7.2 80 × 16 mode (1/16 duty) ............................................................................................................244
14.7.3 64 × 32 mode (1/32 duty) ............................................................................................................246
14.7.4 48 × 48 mode (1/48 duty) ............................................................................................................248
14.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2, VLC3, and VLC4...........................................250
CHAPTER 15 MULTIPLIER...................................................................................................................251
15.1 Multiplier Function ...................................................................................................................251
15.2 Multiplier Configuration...........................................................................................................251
15.3 Register Controlling Multiplier ...............................................................................................253
15.4 Multiplier Operation .................................................................................................................254
CHAPTER 16 SWAPPING (SWAP) .....................................................................................................255
16.1 Function of SWAP....................................................................................................................255
16.2 Configuration of SWAP ...........................................................................................................256
16.3 Example of Executing SWAP..................................................................................................256
CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................257
17.1 Interrupt Function Types.........................................................................................................257
17.2 Interrupt Sources and Configuration.....................................................................................257
17.3 Registers Controlling Interrupt Function ..............................................................................261
17.4 Interrupt Servicing Operation .................................................................................................267
17.4.1 Non-maskable interrupt request acknowledgment operation.......................................................267
17.4.2 Maskable interrupt request acknowledgment operation ..............................................................269
17.4.3 Multiple interrupt servicing...........................................................................................................271
17.4.4 Putting interrupt requests on hold................................................................................................272
CHAPTER 18 STANDBY FUNCTION..................................................................................................273
18.1 Standby Function and Configuration.....................................................................................273
18.1.1 Standby function..........................................................................................................................273
18.1.2 Registers controlling standby function.........................................................................................274
18.2 Standby Function Operation...................................................................................................276
18.2.1 HALT mode.................................................................................................................................276
18.2.2 STOP mode ................................................................................................................................279
CHAPTER 19 RESET FUNCTION .......................................................................................................282
CHAPTER 20 µPD78F9835...................................................................................................................286
20.1 Flash Memory Characteristics................................................................................................287
20.1.1 Programming environment..........................................................................................................287
20.1.2 Communication mode .................................................................................................................288
20.1.3 On-board pin processing.............................................................................................................290
20.1.4 Connection on flash memory writing adapter ..............................................................................293
User’s Manual U15559EJ2V1UD
14
CHAPTER 21 INSTRUCTION SET ......................................................................................................294
21.1 Operation ..................................................................................................................................294
21.1.1 Operand identifiers and description methods.............................................................................. 294
21.1.2 Description of “Operation” column............................................................................................... 295
21.1.3 Description of “Flag” column ....................................................................................................... 295
21.2 Operation List...........................................................................................................................296
21.3 Instructions Listed by Addressing Type...............................................................................301
CHAPTER 22 ELECTRICAL SPECIFICATIONS.................................................................................304
CHAPTER 23 PACKAGE DRAWING ..................................................................................................319
CHAPTER 24 APPLICATION CIRCUIT EXAMPLE ...........................................................................320
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................328
A.1 Software Package ....................................................................................................................330
A.2 Language Processing Software .............................................................................................330
A.3 Control Software......................................................................................................................331
A.4 Flash Memory Writing Tools...................................................................................................332
A.5 Debugging Tools (Hardware)..................................................................................................332
A.6 Debugging Tools (Software)...................................................................................................333
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM......................................................334
APPENDIX C REGISTER INDEX.........................................................................................................335
C.1 Register Index (Alphabetic Order of Register Name) ..........................................................335
C.2 Register Index (Alphabetic Order of Register Symbol) .......................................................338
APPENDIX D REVISION HISTORY.....................................................................................................341
D.1 Major Revisions in This Edition .............................................................................................341
User’s Manual U15559EJ2V1UD
15
LIST OF FIGURES (1/6)
Figure No.
Title
Page
2-1
Pin I/O Circuits................................................................................................................................................43
3-1
Memory Map (µPD789832, 789832A, 789832B) ............................................................................................45
Memory Map (µPD789833, 789833A, 789833B) ............................................................................................46
Memory Map (µPD789834, 789834A, 789834B) ............................................................................................47
Memory Map (µPD789835, 789835A, 789835B) ............................................................................................48
Memory Map (µPD78F9835) ..........................................................................................................................49
Data Memory Addressing (µPD789832, 789832A, 789832B).........................................................................52
Data Memory Addressing (µPD789833, 789833A, 789833B).........................................................................53
Data Memory Addressing (µPD789834, 789834A, 789834B).........................................................................54
Data Memory Addressing (µPD789835, 789835A, 789835B).........................................................................55
Data Memory Addressing (µPD78F9835).......................................................................................................56
Program Counter Configuration ......................................................................................................................57
Program Status Word Configuration ...............................................................................................................57
Stack Pointer Configuration ............................................................................................................................59
Data to Be Saved to Stack Memory................................................................................................................59
Data to Be Restored from Stack Memory .......................................................................................................59
General-Purpose Register Configuration ........................................................................................................60
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
4-1
Port Types ......................................................................................................................................................73
Block Diagram of P00 to P07..........................................................................................................................75
Block Diagram of P10 and P11.......................................................................................................................76
Block Diagram of P20 .....................................................................................................................................77
Block Diagram of P21 .....................................................................................................................................78
Block Diagram of P22 to P24 and P26............................................................................................................79
Block Diagram of P25 and P27.......................................................................................................................80
Block Diagram of P30 to P37..........................................................................................................................81
Block Diagram of P60 to P62..........................................................................................................................82
Block Diagram of P80 to P87..........................................................................................................................83
Format of Port Mode Register.........................................................................................................................84
Format of Pull-Up Resistor Option Register 0.................................................................................................85
Format of Pull-Up Resistor Option Register B2...............................................................................................86
Format of Pull-Up Resistor Option Register B3...............................................................................................86
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3
5-4
5-5
Block Diagram of Clock Generator..................................................................................................................89
Format of Processor Clock Control Register...................................................................................................90
Format of Suboscillation Mode Register .........................................................................................................91
Format of Subclock Control Register ..............................................................................................................92
External Circuit of Main System Clock Oscillator (Ceramic/Crystal Oscillation)..............................................93
User’s Manual U15559EJ2V1UD
16
LIST OF FIGURES (2/6)
Figure No.
Title
Page
5-6
External Circuit of Main System Clock Oscillator (RC Oscillation)..................................................................93
External Circuit of Subsystem Clock Oscillator...............................................................................................94
Examples of Incorrect Connection for Ceramic/Crystal Oscillation ................................................................95
Examples of Incorrect Connection for RC Oscillation .....................................................................................97
Switching Between System Clock and CPU Clock (Ceramic/Crystal Oscillation).........................................102
Switching Between System Clock and CPU Clock (RC Oscillation) .............................................................103
5-7
5-8
5-9
5-10
5-11
6-1
Block Diagram of 8-Bit Timer/Event Counter 80 ...........................................................................................105
Block Diagram of 8-Bit Timer 81...................................................................................................................105
Block Diagram of 8-Bit Timer 82...................................................................................................................106
Format of 8-Bit Timer Mode Control Register 80 ..........................................................................................107
Format of 8-Bit Timer Mode Control Register 81 ..........................................................................................108
Format of 8-Bit Timer Mode Control Register 82 ..........................................................................................109
Format of Port Mode Register 2 ...................................................................................................................110
Interval Timer Operation Timing of TM80 and TM81 ....................................................................................113
Interval Timer Operation Timing of TM82 .....................................................................................................113
External Event Counter Operation Timing (with Rising Edge Specified).......................................................114
Square Wave Output Timing ........................................................................................................................116
Case in Which (Maximum) 1.5 Clock Cycle Error Occurs.............................................................................117
Count Operation When Timer Is Started While TI80 at High Level (with Rising Edge Selected)..................118
External Event Counter Operation Timing ....................................................................................................119
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
7-1
Block Diagram of Timer 30 ...........................................................................................................................122
Block Diagram of Timer 40 ...........................................................................................................................123
Block Diagram of Output Controller (Timer 40).............................................................................................124
Format of 8-Bit Timer Mode Control Register 30 ..........................................................................................127
Format of 8-Bit Timer Mode Control Register 40 ..........................................................................................128
Format of Carrier Generator Output Control Register 40..............................................................................129
Format of Port Mode Register 2 ...................................................................................................................130
Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) .................................................133
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H) ..........................133
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH).................................134
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) .......134
Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) .......135
Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for
Timer 30 Count Clock)..................................................................................................................................136
Timing of Square-Wave Output with 8-Bit Resolution...................................................................................138
Timing of Interval Timer Operation with 16-Bit Resolution............................................................................141
Timing of Square-Wave Output with 16-Bit Resolution.................................................................................143
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
User’s Manual U15559EJ2V1UD
17
LIST OF FIGURES (3/6)
Figure No.
Title
Page
7-17
7-18
7-19
7-20
7-21
7-22
Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) ..........................................145
Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) ..........................................146
Timing of Carrier Generator Operation (When CR40 = CRH40 = N) ............................................................147
PWM Output Mode Timing (Basic Operation)...............................................................................................149
PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)........................................................149
Case in Which (Maximum) 1.5 Clock Cycle Error Occurs.............................................................................150
8-1
8-2
8-3
Block Diagram of 8-Bit Remote Control Timer 50 .........................................................................................151
Format of Remote Control Timer Control Register 50...................................................................................152
Pulse Width Measurement Timing ................................................................................................................153
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Block Diagram of Sound Generator ..............................................................................................................156
Format of 8-Bit Timer Mode Control Register SG0 .......................................................................................158
Format of Carrier Generator Output Control Register SG0...........................................................................159
Format of Sound Generator Frequency Setting Register 00.........................................................................159
Format of P3 Function Register ....................................................................................................................164
Timing of Sound Generator Operation..........................................................................................................166
Examples of Output Waveforms in Respective Buzzer Modes .....................................................................172
10-1
10-2
10-3
Block Diagram of Watch Timer .....................................................................................................................173
Format of Watch Timer Mode Control Register.............................................................................................175
Watch Timer/Interval Timer Operation Timing ..............................................................................................177
11-1
11-2
11-3
Block Diagram of Watchdog Timer ...............................................................................................................179
Format of Watchdog Timer Clock Selection Register ...................................................................................180
Format of Watchdog Timer Mode Register ...................................................................................................181
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
Block Diagram of 8-Bit A/D Converter...........................................................................................................185
Format of A/D Converter Mode Register.......................................................................................................187
Format of A/D Input Select Register .............................................................................................................188
Basic Operation of 8-Bit A/D Converter ........................................................................................................190
Relationship Between Analog Input Voltage and A/D Conversion Result .....................................................191
Software-Started A/D Conversion.................................................................................................................192
How to Reduce Current Consumption in Standby Mode...............................................................................193
Conversion Result Readout Timing (When Conversion Result Is Undefined Value).....................................194
Conversion Result Readout Timing (When Conversion Result Is Normal Value) .........................................194
12-10 Analog Input Pin Handling.............................................................................................................................194
12-11 A/D Conversion End Interrupt Request Generation Timing...........................................................................195
User’s Manual U15559EJ2V1UD
18
LIST OF FIGURES (4/6)
Figure No.
Title
Page
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
Block Diagram of Serial Interface (SIO10)....................................................................................................197
Block Diagram of Serial Interface (UART00) ................................................................................................198
Format of Serial Operation Mode Register 10 ..............................................................................................201
Format of Asynchronous Serial Interface Mode Register 00.........................................................................202
Format of Asynchronous Serial Interface Status Register 00 .......................................................................204
Format of Baud Rate Generator Control Register 00....................................................................................205
Permissible Error in Baud Rate Allowing for Sampling Error (Where k = 0)..................................................215
Asynchronous Serial Interface Transmission/Reception Data Format..........................................................216
Asynchronous Serial Interface Transmission Completion Interrupt Timing...................................................218
13-10 Asynchronous Serial Interface Reception Completion Interrupt Timing........................................................219
13-11 Receive Error Timing....................................................................................................................................220
13-12 3-Wire Serial I/O Mode Timing .....................................................................................................................223
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
Block Diagram of LCD Controller/Driver .......................................................................................................225
Format of LCD20 Display Mode Register .....................................................................................................227
Format of LCD20 Clock Control Register .....................................................................................................228
Format of LCD Boost Voltage Level Setting Register 00..............................................................................229
Assignment of LCD Display Data Memory in Each Display Mode ................................................................234
LCD Drive Waveform Examples (1/8 Duty) ..................................................................................................243
LCD Drive Waveform Examples (1/16 Duty) ................................................................................................245
LCD Drive Waveform Examples (1/32 Duty) ................................................................................................247
LCD Drive Waveform Examples (1/48 Duty) ................................................................................................249
14-10 Example of Connecting LCD Driver Pins......................................................................................................250
15-1
15-2
15-3
Block Diagram of Multiplier...........................................................................................................................252
Format of Multiplier Control Register 0 .........................................................................................................253
Multiplier Operation Timing (Example of AAH × D3H) ..................................................................................254
16-1
16-2
Example of Swapping...................................................................................................................................255
SWAP Block Diagram...................................................................................................................................256
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
Basic Configuration of Interrupt Function......................................................................................................259
Format of Interrupt Request Flag Registers..................................................................................................262
Format of Interrupt Mask Flag Registers ......................................................................................................263
Format of External Interrupt Mode Register 0...............................................................................................264
Configuration of Program Status Word.........................................................................................................265
Format of Key Return Mode Register 00 ......................................................................................................266
Block Diagram of Key Return Signal Detector ..............................................................................................266
Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment...........................................268
User’s Manual U15559EJ2V1UD
19
LIST OF FIGURES (5/6)
Figure No.
Title
Page
17-9
Timing of Non-Maskable Interrupt Request Acknowledgment ......................................................................268
17-10 Non-Maskable Interrupt Request Acknowledgment ......................................................................................268
17-11 Interrupt Request Acknowledgment Program Algorithm ...............................................................................269
17-12 Interrupt Request Acknowledgment Timing (Example: MOV A, r) ................................................................270
17-13 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock
Under Execution) ..........................................................................................................................................270
17-14 Example of Multiple Interrupts.......................................................................................................................271
18-1
18-2
18-3
18-4
18-5
18-6
Format of Oscillation Stabilization Time Selection Register..........................................................................274
Format of Power Supply Control Register 0..................................................................................................275
Releasing HALT Mode by Interrupt...............................................................................................................277
Releasing HALT Mode by RESET Input .......................................................................................................278
Releasing STOP Mode by Interrupt ..............................................................................................................280
Releasing STOP Mode by RESET Input.......................................................................................................281
19-1
19-2
19-3
19-4
Block Diagram of Reset Function..................................................................................................................282
Reset Timing by RESET Input ......................................................................................................................283
Reset Timing by Overflow in Watchdog Timer..............................................................................................283
Reset Timing by RESET Input in STOP Mode..............................................................................................283
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
Environment for Writing Program to Flash Memory ......................................................................................287
Communication Mode Selection Format .......................................................................................................288
Example of Connection with Dedicated Flash Programmer..........................................................................289
VPP Pin Connection Example ........................................................................................................................290
Signal Conflict (Input Pin of Serial Interface).................................................................................................291
Abnormal Operation of Other Device............................................................................................................291
Signal Conflict (RESET Pin)..........................................................................................................................292
Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode ........................................293
24-1
24-2
24-3
24-4
24-5
24-6
24-7
Application Circuit Example 1 .......................................................................................................................321
Application Circuit Example 2 .......................................................................................................................322
Application Circuit Example 3 .......................................................................................................................323
Application Circuit Example 4 .......................................................................................................................324
Application Circuit Example 5 .......................................................................................................................325
Application Circuit Example 6 .......................................................................................................................326
Application Circuit Example 7 .......................................................................................................................327
A-1
Development Tools.......................................................................................................................................329
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20
LIST OF FIGURES (6/6)
Figure No.
Title
Page
B-1
B-2
Distance Between In-Circuit Emulator and Conversion Connector...............................................................334
Connection to Target System .......................................................................................................................334
User’s Manual U15559EJ2V1UD
21
LIST OF TABLES (1/3)
Table No.
Title
Page
1-1
2-1
Differences Between µPD78983x, µPD78983xA, and µPD78983xB................................................................35
Types of Pin I/O Circuits and Recommended Connection of Unused Pins.....................................................42
3-1
3-2
3-3
3-4
Internal ROM Capacity....................................................................................................................................50
Vector Table....................................................................................................................................................50
Internal RAM Capacity....................................................................................................................................51
Special Function Registers .............................................................................................................................62
4-1
4-2
4-3
Port Functions.................................................................................................................................................74
Configuration of Port.......................................................................................................................................74
Port Mode Registers and Output Latch Settings When Using Alternate Functions.........................................85
5-1
5-2
5-3
Configuration of Clock Generator....................................................................................................................88
Maximum Time Required for Switching CPU Clock (When Ceramic/Crystal Oscillation Is Selected)...........101
Maximum Time Required for Switching CPU Clock (When RC Oscillation Is Selected) ...............................101
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
Configuration of 8-Bit Timer/Event Counters 80 to 82...................................................................................104
Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz Operation)..................................................111
Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 2.0 MHz Operation) ................................................111
Interval Time of 8-Bit Timer 81 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation)........................................112
Interval Time of 8-Bit Timer 81 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)......................................112
Interval Time of 8-Bit Timer 82 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation)........................................112
Interval Time of 8-Bit Timer 82 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)......................................112
Square Wave Output Range of 8-Bit Timer 82 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation) ...............115
Square Wave Output Range of 8-Bit Timer 82 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)..............115
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
Operation Modes ..........................................................................................................................................120
Configuration of 8-Bit Timers 30, 40 .............................................................................................................121
Interval Time of Timer 30 (at fX = 5.0 MHz Operation)..................................................................................132
Interval Time of Timer 30 (at fCC = 2.0 MHz Operation) ................................................................................132
Interval Time of Timer 40 (at fX = 5.0 MHz Operation)..................................................................................132
Interval Time of Timer 40 (at fCC = 2.0 MHz Operation) ................................................................................132
Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation)..........................................................137
Square-Wave Output Range of Timer 40 (at fCC = 2.0 MHz Operation)........................................................137
Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation)..................................................................140
Interval Time with 16-Bit Resolution (at fCC = 2.0 MHz Operation)................................................................140
Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation) .........................................142
Square-Wave Output Range with 16-Bit Resolution (at fCC = 2.0 MHz Operation) .......................................142
User’s Manual U15559EJ2V1UD
22
LIST OF TABLES (2/3)
Table No.
Title
Page
8-1
Configuration of 8-Bit Remote Control Timer 50...........................................................................................151
9-1
9-2
9-3
Configuration of Sound Generator................................................................................................................155
Supported Buzzer Modes .............................................................................................................................167
Volume Settable in Buzzer Mode 2 (Eight Steps).........................................................................................167
10-1
10-2
10-3
Interval Time of Interval Timer......................................................................................................................174
Configuration of Watch Timer.......................................................................................................................174
Interval Time of Interval Timer......................................................................................................................176
11-1
11-2
11-3
11-4
11-5
11-6
Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................178
Interval Time of Watchdog Timer..................................................................................................................178
Configuration of Watchdog Timer .................................................................................................................179
Inadvertent Program Loop Detection Time or Interval Time of Watchdog Timer ..........................................180
Inadvertent Program Loop Detection Time of Watchdog Timer....................................................................182
Interval Time of Watchdog Timer..................................................................................................................183
12-1
Configuration of 8-Bit A/D Converter ............................................................................................................185
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
Configuration of Serial Interface ...................................................................................................................199
Settings of Serial Interface Operating Mode.................................................................................................203
Example of Relationship Between Main System Clock and Baud Rate (When fX = 5.0 MHz) ......................206
Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.9152 MHz) ................206
Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.1943 MHz) ................207
Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.00 MHz) ....................207
Relationship Between Source Clock of 5-Bit Counter and Value n...............................................................214
Relationship Between Input Clock of Baud Rate Generator and Value k......................................................215
Receive Error Causes...................................................................................................................................220
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
Configuration of LCD Controller/Driver .........................................................................................................224
Frame Frequency (Hz) at 1/48 Duty (48 × 48 Mode) ....................................................................................228
Frame Frequency (Hz) at 1/32 Duty (64 × 32 Mode) ....................................................................................228
Frame Frequency (Hz) at 1/16 Duty (80 × 16 Mode) ....................................................................................229
Frame Frequency (Hz) at 1/8 Duty (80 × 8 Mode) ........................................................................................229
Assignment of LCD0 to LCD95 Pins in Each Display Mode .........................................................................230
Relationship Between LCD Display Data Memory and Segment/Common Output ......................................235
Output Voltage of VLC0 to VLC4 Pins ..............................................................................................................250
16-1
SWAP Configuration.....................................................................................................................................256
User’s Manual U15559EJ2V1UD
23
LIST OF TABLES (3/3)
Table No.
Title
Page
17-1
17-2
17-3
Interrupt Source List......................................................................................................................................258
Flags Corresponding to Interrupt Request Signal Name...............................................................................261
Time from Generation of Maskable Interrupt Request to Servicing...............................................................269
18-1
18-2
18-3
18-4
Operation Statuses in HALT Mode ...............................................................................................................276
Operation After Releasing HALT Mode.........................................................................................................278
Operation Statuses in STOP Mode...............................................................................................................279
Operation After Releasing STOP Mode........................................................................................................281
19-1
Status of Each Hardware After Reset ...........................................................................................................284
20-1
20-2
20-3
Differences Between µPD78F9835 and Mask ROM Versions ......................................................................286
Communication Mode List.............................................................................................................................288
Pin Connection List.......................................................................................................................................289
21-1
Operand Identifiers and Description Methods...............................................................................................294
User’s Manual U15559EJ2V1UD
24
CHAPTER 1 GENERAL
1.1 Features
•
ROM and RAM capacities
Item
Program Memory
(ROM)
Data Memory
Internal High-Speed RAM Internal Low-Speed RAM
1024 bytes 1216 bytes
Part Number
LCD Display RAM
288 bytes × 2
µPD789832
µPD789832A
µPD789832B
24 KB Mask ROM
µPD789833
µPD789833A
µPD789833B
32 KB
µPD789834
µPD789834A
µPD789834B
48 KB
2240 bytes
µPD789835
µPD789835A
µPD789835B
60 KB
µPD78F9835
60 KB Flash memory
•
Ceramic/crystal oscillation (0.4 µs: 5 MHz) or RC oscillation (1.0 µs: 2 MHz) is selectable for the main system
clock oscillator.
•
•
•
I/O ports: 37
Remote controller receive input pin: 1
Timer: 8 channels
•
•
•
8-bit timer: 6 channels
Watch timer: 1 channel
Watchdog timer: 1 channel
•
•
•
•
Sound generator: 10-level volume, 3-octave scale
8-bit resolution A/D converter: 3 channels (µPD78983xA, 78983xB, 78F9835 only)
Serial interface: 1 channel
LCD controller/driver (booster)
•
•
Four display modes selectable (48 × 48, 64 × 32, 80 × 16, 80 × 8)
1/5 bias
•
•
Multiplier: 8 bits × 8 bits = 16 bits
Power supply voltage: VDD = 1.8 to 3.6 V (mask ROM version)
VDD = 3.0 to 3.6 V (flash memory version)
1.2 Applications
LCD games, remote controllers, pagers, etc.
25
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
1.3 Ordering Information
Part Number
Package
Internal ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Flash memory
µPD789832BGJ-×××-UEN
µPD789833BGJ-×××-UEN
µPD789834BGJ-×××-UEN
µPD789835BGJ-×××-UEN
µPD78F9835GJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
Remark ××× indicates ROM code suffix.
The following products are not subject to sales expansion (production is continuing, though). When placing a new
order, specify code B in the above table.
Part Number
Package
Internal ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
µPD789832GJ-×××-UEN
µPD789833GJ-×××-UEN
µPD789834GJ-×××-UEN
µPD789835GJ-×××-UEN
µPD789832AGJ-×××-UEN
µPD789833AGJ-×××-UEN
µPD789834AGJ-×××-UEN
µPD789835AGJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
Remark ××× indicates ROM code suffix.
26
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
(1) 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD789832BGJ-×××-UEN
µPD789833BGJ-×××-UEN
µPD789834BGJ-×××-UEN
µPD789835BGJ-×××-UEN
µPD78F9835BGJ-UEN
µPD789832AGJ-×××-UEN
µPD789833AGJ-×××-UEN
µPD789834AGJ-×××-UEN
µPD789835AGJ-×××-UEN
1
108
107
106
105
104
103
102
101
100
99
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD71
LCD70
LCD69
LCD68
LCD67
LCD66
LCD65
LCD64
LCD63
LCD62
LCD61
LCD60
LCD59
LCD58
LCD57
LCD56
LCD55
LCD54
LCD53
LCD52
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
2
3
4
5
6
P11
7
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
92
91
VLC4
VLC3
VLC2
VLC1
VLC0
90
89
88
87
86
CAP3
CAP2
CAP1
CAP0
IC (VPP
85
84
83
82
)
81
VROUT0
80
XT2
XT1
79
78
V
SS
77
VDD
76
X2Note 1/CL2Note 2
X1Note 1/CL1Note 2
RESET
75
74
73
SEL
Notes 1. When ceramic/crystal oscillation is selected
2. When RC oscillation is selected
Cautions 1. Connect the IC (Internally Connected) pin directly to the VSS pin.
2. Ceramic/crystal oscillation and RC oscillation can be switched by the SEL pin. Connect the
SEL pin to the VSS pin when using ceramic/crystal oscillation, and to the VDD pin when using
RC oscillation.
Remarks 1. The parenthesized values apply to µPD78F9835.
2. The µPD78983xA is not subject to sales expansion (individually supported). The µPD78983xB is
targeted for sales expansion.
27
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
(2) 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD789832GJ-×××-UEN
µPD789833GJ-×××-UEN
µPD789834GJ-×××-UEN
µPD789835GJ-×××-UEN
1
108
107
106
105
104
103
102
101
100
99
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD71
LCD70
LCD69
LCD68
LCD67
LCD66
LCD65
LCD64
LCD63
LCD62
LCD61
LCD60
LCD59
LCD58
LCD57
LCD56
LCD55
LCD54
LCD53
LCD52
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
2
3
4
5
6
P11
7
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
P61
P62
92
91
V
V
V
V
V
LC4
LC3
LC2
LC1
LC0
90
89
88
87
86
CAP3
CAP2
CAP1
CAP0
IC (VPP
85
84
83
82
)
81
VROUT0
80
XT2
XT1
79
78
V
V
SS
77
DD
76
X2Note 1/CL2Note 2
X1Note 1/CL1Note 2
RESET
75
74
73
SEL
Notes 1. When ceramic/crystal oscillation is selected
2. When RC oscillation is selected
Cautions 1. Connect the IC (Internally Connected) pin directly to the VSS pin.
2. Ceramic/crystal oscillation and RC oscillation can be switched by the SEL pin. Connect the
SEL pin to the VSS pin when using ceramic/crystal oscillation, and to the VDD pin when using
RC oscillation.
Remark The µPD78983x is not subject to sales expansion (individually supported). The µPD78983xB is targeted
for sales expansion.
28
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
Pin Identification
ANI0 to ANI2:
CAP0 to CAP3:
CL1, CL2:
Analog input
RIN:
Remote timer input
Receive data
Output of booster
RxD00:
RC oscillator (main system clock)
SEL:
Main system clock selector
Sound generator
Timer input
IC:
Internally connected
SG0 to SG7:
TI80:
INTP0, INTP1:
LCD0 to LCD95
KR00 to KR07:
P00 to P07:
P10, P11:
Interrupt from peripherals
Segment/common signal for LCD
TO40, TO82:
TxD00:
VDD:
Timer output
Key return input
Port 0
Transmit data
Power supply
Port 1
VLC0 to VLC4:
VPP:
Output of booster
Programming power supply
Output of regulator
Ground
P20 to P27:
P30 to P37:
P60 to P62:
P80 to P87:
RESET:
Port 2
Port 3
VROUT0:
VSS:
Port 6
Port 8
X1, X2:
XT1, XT2:
Crystal (main system clock)
Crystal (subsystem clock)
Reset
29
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y Subseries products support SMB.
Small-scale package, general-purpose applications
µ
44-pin
PD789074 with added subsystem clock
µ
PD789046
42/44-pin
On-chip UART and capable of low voltage (1.8 V) operation
µ
PD789026
µ
PD789088
µ
PD789074
µ
PD789062
µ
PD789052
µ
µ
30-pin
30-pin
20-pin
20-pin
PD789074 with enhanced timer and increased ROM, RAM capacity
PD789026 with enhanced timer
µ
RC oscillation version of the PD789052
µ
PD789860 without EEPROM, POC, and LVI
Small-scale package, general-purpose applications and A/D converter
µ
µ
PD789177Y
PD789167Y
µ
µ
µ
µ
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
44-pin
44-pin
30-pin
30-pin
30-pin
30-pin
PD789177
PD789167
PD789134A
PD789124A
PD789114A
PD789104A
µ
µ
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the PD789104A
µ
µ
µ
µ
µ
µ
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
LCD drive
144-pin
88-pin
80-pin
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789835B
UART, 8-bit A/D converter, and dot LCD (Total display output pins: 96)
UART and dot LCD (40 16)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28
PD789830
PD789489
×
×
4)
SIO, 8-bit A/D converter, and resistance division type LCD (28
PD789407A with enhanced A/D converter (10 bits)
×
4)
PD789479
PD789417A
PD789407A
PD789456
PD789446
PD789436
PD789426
PD789316
PD789306
PD789467
80-pin
80-pin
µ
SIO, 8-bit A/D converter, and resistance division type LCD (28
PD789446 with enhanced A/D converter (10 bits)
×
4)
80-pin
64-pin
64-pin
64-pin
64-pin
µ
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (15
×
4)
78K/0S
Series
µ
PD789426 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D converter, and on-chip voltage booster type LCD (5
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24
8-bit A/D converter and on-chip voltage booster type LCD (23
SIO and resistance division type LCD (24 4)
×
4)
64-pin
64-pin
52-pin
52-pin
µ
×
4)
×
4)
µ
×
PD789327
USB
44-pin
44-pin
µ
PD789800
For PC keyboard and on-chip USB function
On-chip inverter controller and UART
Inverter control
µ
PD789842
On-chip bus controller
µ
µ
µ
PD789850A with enhanced functions such as timer and A/D converter
PD789852
44-pin
30-pin
PD789850A
On-chip CAN controller
Keyless entry
30-pin
20-pin
20-pin
µ
µ
µ
PD789862
µ
PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
µ
RC oscillation version of the PD789860
PD789861
PD789860
On-chip POC and key return circuit
Sensor
µ
On-chip analog macro for sensor
PD789864
PD789863
20-pin
20-pin
µ
µ
RC oscillation version of the PD789864
VFD drive
µ
52-pin
64-pin
PD789871
On-chip VFD controller (total display output pins: 25)
Meter control
µ
PD789881
UART and resistance division type LCD (26
× 4)
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
30
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
The major functional differences among the subseries are listed below.
Series for general-purpose applications and LCD drive
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Function
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Subseries Name
Value
Small-scale µPD789046
16 KB
4 to 16 KB
16 to 32 KB 3 ch
1 ch 1 ch
1 ch
1 ch
−
−
1 ch
34 1.8 V
−
package,
(UART: 1 ch)
µPD789026
−
general-
µPD789088
24
14
purpose
µPD789074
µPD789062
2 to 8 KB
4 KB
1 ch
2 ch
applications
−
−
RC oscillation
version
µPD789052
−
−
Small-scale µPD789177
16 to 24 KB 3 ch 1 ch
1 ch
1 ch
−
8 ch
−
8 ch 1 ch
31 1.8 V
20
package,
(UART: 1 ch)
µPD789167
−
4 ch
−
general-
purpose
µPD789134A 2 to 8 KB
1 ch
−
RC oscillation
version
µPD789124A
µPD789114A
µPD789104A
4 ch
−
applications
and A/D
4 ch
−
−
converter
4 ch
Note
LCD drive
µPD789835B 24 to 60 KB 6 ch
–
1 ch
1 ch 3 ch
–
–
1 ch
37
Dot LCD
1.8 V
(UART: 1 ch)
supported
µPD789830
µPD789489
µPD789479
24 KB
1 ch 1 ch
30 2.7 V
32 to 48 KB 3 ch
24 to 48 KB
8 ch 2 ch
45 1.8 V
−
(UART: 1 ch)
8 ch
−
−
µPD789417A 12 to 24 KB
µPD789407A
7 ch 1 ch
43
30
40
23
(UART: 1 ch)
7 ch
−
−
6 ch
–
µPD789456
µPD789446
µPD789436
µPD789426
µPD789316
12 to 16 KB 2 ch
6 ch
–
6 ch
–
6 ch
–
8 to 16 KB
4 to 24 KB
2 ch
RC oscillation
version
(UART: 1 ch)
µPD789306
µPD789467
µPD789327
–
–
1 ch
–
–
18
21
1 ch
Note Flash memory version: 3.0 V
31
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
Series for ASSP
Subseries Name
ROM
Timer
8-Bit 10-Bit
A/D A/D
Serial
I/O
VDD
Remarks
Function
Capacity
Interface
8-Bit 16-Bit Watch WDT
MIN.
Value
USB
µPD789800
µPD789842
µPD789852
8 KB
2 ch
–
−
1 ch
–
–
2 ch
31 4.0 V
30 4.0 V
31 4.0 V
18
−
−
−
(USB: 1 ch)
Inverter
control
8 to 16 KB
3 ch Note 1 1 ch
1 ch 8 ch
−
1 ch
(UART: 1 ch)
On-chip
bus
24 to 32 KB 3 ch
1 ch
−
1 ch
−
4 ch
−
8 ch 3 ch
(UART: 2 ch)
2 ch
controller
µPD789850A 16 KB
1 ch
2 ch
−
−
(UART: 1 ch)
Keyless
entry
µPD789861
4 KB
−
−
1 ch
–
14 1.8 V RC
oscillation
version,
on-chip
EEPROM
µPD789860
µPD789862
On-chip
EEPROM
16 KB
4 KB
1 ch
2 ch
1 ch
22
5
(UART: 1 ch)
Sensor
µPD789864
µPD789863
1 ch Note 2
–
1 ch
–
4 ch
–
1.9 V On-chip
EEPROM
RC
oscillation
version,
on-chip
EEPROM
VFD drive
µPD789871
µPD789881
4 to 8 KB
16 KB
3 ch
2 ch
–
1 ch
–
1 ch
1 ch
–
–
–
–
1 ch
33 2.7 V
–
–
Note 3
Meter
1 ch
1 ch
28
2.7 V
control
(UART: 1 ch)
Notes 1. 10-bit timer: 1 channel
2. 12-bit timer: 1 channel
3. Flash memory version: 3.0 V
32
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
1.6 Block Diagram
Port 0
Port 1
Port 2
Port 3
Port 6
Port 8
P00 to P07
P10, P11
8-bit timer/
event counter 80
TI80/P23
8-bit timer 81
8-bit timer 82
P20 to P27
P30 to P37
P60 to P62
TO82/P25
8-bit
timer 30
Cascaded
16-bit
8-bit
timer
TO40/P27
RIN/P26
timer 40
P80 to P87
78K/0S
ROM
CPU core
8-bit remote
timer 50
LCD0 to LCD87
Dot LCD
controller/driver
LCD88/P80 to
LCD95/P87
SG0/P30 to
SG7/P37
V
LC0 to VLC2
Sound generator
Watch timer
Booster for
Dot LCD
RAM
space
for LCD
data
CAP0 to CAP3
RAM
Regulator for
Dot LCD
V
LC3, VLC4
Watchdog timer
Regulator for
CPU/XT
V
ROUT0
Note
A/D converter
ANI0/P60 to
ANI2/P62
Multiplier
INTP0/P23
INTP1/P24
KR00/P00 to
KR07/P07
SCK10/P20
TxD00/SO10/P21
RxD00/SI10/P22
SCK10/UART00
SWAP
Interrupt control
H/L
RESET
X1/CL1
X2/CL2
XT1
System control
XT2
VDD
VSS
IC
(VPP
SEL
)
Note The A/D converter is provided with the µPD78983xB, 78983xA, and 78F9835 only. It is not provided with
the µPD78983x.
Remarks 1. The internal ROM and RAM capacities vary depending on the product.
2. The parenthesized values apply to µPD78F9835.
33
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
1.7 Overview of Functions
Item
µPD789832
µPD789832A
µPD789832B
µPD789833
µPD789833A
µPD789833B
µPD789834
µPD789834A
µPD789834B
µPD789835
µPD789835A
µPD789835B
µPD78F9835
Internal memory ROM
Mask ROM
24 KB
Flash memory
32 KB
48 KB
60 KB
High-speed RAM
Low-speed RAM
LCD display RAM
1024 bytes
1216 bytes
288 bytes × 2
2240 bytes
Minimum
Ceramic/crystal
oscillation
0.4 µs/1.6 µs (@ 5.0 MHz operation with main system clock)
instruction
execution time
RC oscillation
1.0 µs/4.0 µs (@ 2.0 MHz operation with main system clock)
122 µs (@ 32.768 kHz operation with subsystem clock)
8 bits × 8 registers
General-purpose registers
Instruction set
• 16-bit operation
• Bit manipulation (set, reset, test)
I/O ports
Timers
Total:
37
26
11
• CMOS I/O:
• CMOS input:
• 8-bit timer:
• Watch timer:
• Watchdog timer:
6 channels
1 channel
1 channel
Sound generator
A/D converter
Volume: 10 levels, scale: 3 octaves
µPD78983xB, 78983xA, 78F9835: 8-bit resolution × 3 channels
µPD78983x:
None
Serial interface
Switchable between UART and 3-wire serial I/O modes: 1 channel
LCD controller/driver
• 4 display modes selectable (48 × 48, 64 × 32, 80 × 16, 80 × 8)
• 1/5 bias
Multiplier
SWAP
8 bits × 8 bits = 16 bits
Higher and lower 4 bits of an 8-bit register can be swapped.
Internal: 15, External: 5
Internal: 1
Vectored interrupt
sources
Maskable
Non-maskable
Power supply voltage (VDD)
Operating ambient temperature
Package
1.8 to 3.6 V
3.0 to 3.6 V
TA = –40 to +85°C
144-pin plastic LQFP (fine pitch) (20 × 20)
34
User’s Manual U15559EJ2V1UD
CHAPTER 1 GENERAL
An outline of the timer is shown below.
8-Bit
8-Bit Timer
8-Bit Timer
82
8-Bit Timer
30
8-Bit Timer 8-Bit Remote Watch Timer Watchdog
Timer/Event
Counter 80
81
40
Control
Timer
Timer 50
Operation
mode
Interval timer
1 channel
1 channel
1 channel
–
1 channel
–
1 channel
–
1 channel
–
1 channel 1 channelNote 1 1 channelNote 2
External event
counter
–
–
–
Function
Timer outputs
–
–
–
–
1 output
1 output
–
–
1 output
1 output
–
–
–
–
–
–
Square-wave
outputs
Capture
–
1
–
1
–
1
–
1
–
1
–
3
–
2
–
2
Interrupt
sources
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or interval timer function.
1.8 Differences Between µPD78983x, µPD78983xA, and µPD78983xB
The µPD78983x, µPD78983xA, and µPD78983xB refer to the following products.
µPD78983x.......... µPD789832, 789833, 789834, 789835
µPD78983xA .......µPD789832A, 789833A, 789834A, 789835A ((A) products)
µPD78983xB ....... µPD789832B, 789833B, 789834B, 789835B ((B) products)
The differences between the µPD78983x, µPD78983xA, and µPD78983xB are shown in Table 1-1.
Table 1-1. Differences Between µPD78983x, µPD78983xA, and µPD78983xB
Item
µPD78983x
Mask ROM
None
µPD78983xA
Mask ROM
Provided
−
µPD78983xB
Mask ROM
Provided
ROM
A/D converter
Others
−
Enhanced ESD
countermeasure
Remark For differences with the flash version (µPD78F9835), see Table 20-1 Differences Between
µPD78F9835 and Mask ROM Versions.
35
User’s Manual U15559EJ2V1UD
CHAPTER 2 PIN FUNCTIONS
2.1 List of Pin Functions
(1) Port pins
Pin Name
I/O
Function
After Reset Alternate Function
P00 to P07
I/O
I/O
I/O
Port 0.
Input
Input
Input
KR00 to KR07
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
P10, P11
Port 1.
−
2-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, use of an on-chip pull-up resistor
can be specified by pull-up resistor option register 0 (PU0).
P20
Port 2.
SCK10
8-bit I/O port.
P21
TxD00/SO10
RxD00/SI10
INTP0/TI80
INTP1
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by pull-up
resistor option register B2 (PUB2).
P22
P23
P24
P25
TO82
P26
RIN
P27
TO40
P30 to P37
I/O
Port 3.
Input
SG0 to SG7
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by pull-up
resistor option register B3 (PUB3).
P60 to P62
P80 to P87
Input
Input
Port 6.
Input
ANI0 to ANI2
3-bit input port.
Port 8.
Output
LCD88 to LCD95
8-bit input-only port when used as a general-purpose port.
Output-only pins when used for alternate function (LCD
display).
36
User’s Manual U15559EJ2V1UD
CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
INTP0
I/O
Function
After Reset
Input
Alternate Function
P23/TI80
P24
Input
External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
INTP1
KR00 to KR07
SI10
Input
Input
Key return signal detection
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
P00 to P07
P22/RxD00
P21/TxD00
P20
Serial interface serial data input
SO10
Output Serial interface serial data output
SCK10
I/O
Serial interface serial clock input/output
RxD00
Input
Serial data input for asynchronous serial interface
P22/SI10
P21/SO10
P23/INTP0
P25
TxD00
Output Serial data output for asynchronous serial interface
Input External count clock input to 8-bit timer/event counter 80
Output 8-bit timer 82 output
TI80
TO82
RIN
Input
Input to 8-bit remote control timer 50
P26
TO40
Output 8-bit timer 40 output
Output Frequency output for sound generator
P27
SG0 to SG7
ANI0 to ANI2
LCD0 to LCD87
LCD88 to LCD95
VLC0 to VLC4
CAP0 to CAP3
VROUT0
P30 to P37
P60 to P62
−
Input
A/D converter analog input
Output Segment/common signal output
P80 to P87
−
−
−
−
−
LCD drive voltage
−
−
−
Connection pin for LCD drive capacitor
−
Regulator output for subsystem clock oscillation. Connect to
VSS via a 0.1 µF capacitor.
−
−
SEL
Input
Input to switch ceramic/crystal oscillation or RC oscillation.
Connect to VSS when using ceramic/crystal oscillation, and
connect to VDD when using RC oscillation.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
X1
Input
−
Connecting ceramic/crystal resonator for main system clock
oscillation
X2
CL1
CL2
XT1
XT2
RESET
VDD
VSS
Input
−
Connecting resistor (R) and capacitor (C) for main system clock
oscillation
Input
−
Connecting crystal resonator for subsystem clock oscillation
Input
−
System reset input
Input
−
−
−
−
Positive power supply for ports
Ground potential
−
−
IC
Internally connected. Connect directly to VSS.
−
VPP
Sets flash memory programming mode.
Applies high voltage when a program is written or verified.
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2.2 Description of Pin Functions
2.2.1 P00 to P07 (Port 0)
These pins constitute an 8-bit I/O port. In addition, these pins enable key return signal detection.
Port 0 can be specified in the following operation modes in 1-bit units.
(1) Port mode
These pins constitute an 8-bit I/O port and can be set in the input or output port mode in 1-bit units by port
mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 0 (PU0) in port units.
(2) Control mode
In this mode, P00 to P07 function as key return signal detection pins (KR00 to KR07).
2.2.2 P10, P11 (Port 1)
These pins constitute a 2-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
2.2.3 P20 to P27 (Port 2)
These pins constitute an 8-bit I/O port. In addition, these pins enable serial interface data I/O, clock I/O, external
interrupt input, and timer I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P27 function as an 8-bit I/O port. Port 2 can be set in the input or output port mode in 1-
bit units by port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified by pull-up resistor
option register B2 (PUB2).
(2) Control mode
In this mode, P20 to P27 function as the serial interface data I/O, clock I/O, external interrupt input, and timer
I/O.
(a) SI10, SO10
These are the serial data I/O pins of the serial interface.
(b) SCK10
This is the serial clock I/O pin of the serial interface.
(c) RxD00, TxD00
These are the serial data I/O pins of the asynchronous serial interface.
(d) TI80
This is the external clock input pin for 8-bit timer/event counter 80.
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(e) TO40, TO82
These are the output pins of the 8-bit timer.
(f) RIN
This is the input pin for 8-bit remote control timer 50.
(g) INTP0, INTP1
These are the external interrupt input pins for which valid edges (rising edge, falling edge, or both rising
and falling edges) can be specified.
Caution When using P20 to P27 as serial interface pins, the I/O mode and output latch must be
set according to the functions to be used. For the details of the setting, see Table 13-2
Settings of Serial Interface Operating Mode.
2.2.4 P30 to P37 (Port 3)
These pins constitute an 8-bit I/O port. In addition, they also function as frequency output for sound generator.
Port 3 can be specified in the following operation mode by P3 function register (PF3).
(1) Port mode
In this mode, port 3 functions as an 8-bit I/O port. Port 3 can be set in the input or output port mode in 1-bit
units by port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor
option register B3 (PUB3) in 1-bit units.
(2) Control mode
In this mode, the pins function as frequency output for sound generator (SG0 to SG7).
2.2.5 P60 to P62 (Port 6)
These pins constitute a 3-bit input-only port. In addition, they also function as A/D converter input.
(1) Port mode
In this mode, port 6 functions as a 3-bit input-only port.
(2) Control mode
In this mode, the pins of port 6 function as A/D converter analog inputs (ANI0 to ANI2).
2.2.6 P80 to P87 (Port 8)
These pins constitute an 8-bit input port. In addition, they also function as LCD controller/driver segment signal
output.
Port 8 can be specified in the following operation mode in 8-bit units by LCD display mode register 20 (LCDM20).
(1) Control mode
In this mode, the pins function as LCD controller/driver segment/common signal output (LCD88 to LCD95).
(2) Port mode
In this mode, port 8 functions as an 8-bit input port.
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CHAPTER 2 PIN FUNCTIONS
2.2.7 LCD0 to LCD87
These pins are segment/common signal output pins for the LCD controller/driver.
2.2.8 CAP0 to CAP3
These pins are the capacitor output pins used to drive the LCD. Connect a 0.47 µF capacitor.
2.2.9 VROUT0
This pin is the regulator output pin for subsystem clock oscillation. Connect to VSS via a 0.1 µF capacitor.
2.2.10 VLC0 to VLC4
These pins are the power supply voltage pins used to drive the LCD. Connect a 0.47 µF capacitor.
2.2.11 RESET
This pin inputs an active-low system reset signal.
2.2.12 SEL
This pin is the input pin for switching between ceramic/crystal oscillation and RC oscillation. Connect to VSS when
using ceramic/crystal oscillation, and connect to VDD when using RC oscillation.
2.2.13 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation when ceramic/crystal
oscillation is selected.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
2.2.14 CL1, CL2
These pins are used to connect a resistor (R) and a capacitor (C) for main system clock oscillation when RC
oscillation is selected.
To supply an external clock, input the clock to CL1 and input the inverted signal to CL2.
2.2.15 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
2.2.16 VDD
This is the positive power supply pin.
2.2.17 VSS
This is the ground pin.
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CHAPTER 2 PIN FUNCTIONS
2.2.18 VPP (µPD78F9835 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Perform either of the following.
• Independently connect a 10 kΩ pull-down resistor to VPP.
• Use the jumper on the board to connect VPP directly to the dedicated flash programmer or VSS, in programming
mode or normal operation mode, respectively.
If the wiring between the VPP and VSS pins is long or if external noise is superimposed on the VPP pin, the user
program may not run correctly.
2.2.19 IC (mask ROM version only)
The IC (Internally Connected) pin is used to set the mask ROM versions (µPD789832, 789833, 789834, 789835,
789832A, 789833A, 789834A, 789835A, 789832B, 789833B, 789834B, and 789835B) in the test mode before
shipment. In the normal operation mode, connect this pin directly to the VSS pin with as short a wiring length as
possible.
If a potential difference is generated between the IC pin and VSS pin due to a long wiring length, or an external
noise superimposed on the IC pin, the user program may not run correctly.
• Connect the IC pin directly to the VSS pin.
V
SS IC
Keep short
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the I/O circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
P00/KR00 to P07/KR07
P10, P11
I/O Circuit Type
5-A
I/O
Recommended Connection of Unused Pins
I/O
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P20/SCK10
8-A
5-A
8-A
P21/TxD00/SO10
P22/RxD00/SI10
P23/INTP0/TI80
P24/INTP1
P25/TO82
5-A
8-A
P26/RIN
P27/TO40
5-AA
5-AB
5-A
P30/SG0, P34/SG4
P31/SG1 to P33/SG3,
P35/SG5 to P37/SG7
P60/ANI0 to P62/ANI2
9-C
Input
I/O
Connect directly to VDD or VSS.
P80/LCD88 to
P87/LCD95
17-J
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open.
LCD0 to LCD87
17-K
Output
Input
Leave open.
−
−
SEL
2
−
−
2
−
XT1
Connect to VSS.
Leave open.
−
Input
−
XT2
RESET
IC (mask ROM version)
VPP (µPD78F9835)
Connect directly to VSS.
Independently connect a 10 kΩ pull-down resistor to VPP or connect
directly to VSS.
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Figure 2-1. Pin I/O Circuits (1/2)
Type 2
Type 8-A
VDD
Pull-up
enable
P-ch
IN
VDD
Data
P-ch
Schmitt-triggered input with hysteresis characteristics
IN/OUT
Output
disable
N-ch
V
SS
Type 9-C
Type 5-A
VDD
Pull-up
enable
P-ch
Comparator
P-ch
N-ch
+
IN
–
VDD
VSS
V
REF
Data
P-ch
(Threshold voltage)
IN/OUT
Output
disable
N-ch
Input
enable
V
SS
Input
enable
V
DD
Type 5-AA
Pull-up
enable
P-ch
Output
disable
VDD
V
DD
Data
P-ch
P-ch
IN/OUT
Output
disable
N-ch
V
SS
Input
enable
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (2/2)
Type 5-AB
Type 17-J
V
DD
Input
enable
Pull-up
enable
P-ch
V
LCD0
V
DD
P-ch
N-ch
V
LCD1
Data
P-ch
P-ch
N-ch
IN/OUT
V
LCD2
Output
disable
N-ch
P-ch
N-ch
N-ch
P-ch
V
SS
IN/OUT
SEG/COM
data
Input
enable
P-ch
N-ch
V
LCD3
P-ch
1R
P-ch
N-ch
V
LCD4
N-ch
V
SS
P-ch
N-ch
Type 17-K
2R
4R
8R
V
LCD0
P-ch
V
LCD1
P-ch
N-ch
N-ch
P-ch
N-ch
V
LCD2
P-ch
N-ch
N-ch
P-ch
OUT
SEG/COM
data
Buzzer mode 2
P-ch
N-ch
N-ch
V
LCD3
P-ch
N-ch
V
LCD4
V
SS
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD789835, 789835A, 789835B Subseries can access 64 KB of memory space. Figures 3-1 to 3-5 show the
memory maps.
Figure 3-1. Memory Map (µPD789832, 789832A, 789832B)
FFFFH
Special function registers
(SFRs)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
LCD display RAMNote
288 × 8 bits
F9E0H
F9DFH
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Data memory
space
Internal low-speed RAM
1216 × 8 bits
5FFFH
F400H
F3FFH
Reserved
Program area
6000H
5FFFH
0080H
007FH
CALLT table area
Program area
Internal ROM
24576 × 8 bits
0040H
003FH
Program memory
space
002CH
002BH
Vector table area
0000H
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-2. Memory Map (µPD789833, 789833A, 789833B)
FFFFH
Special function registers
(SFRs)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
LCD display RAMNote
288 × 8 bits
F9E0H
F9DFH
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Data memory
space
Internal low-speed RAM
1216 × 8 bits
7FFFH
F400H
F3FFH
Program area
Reserved
8000H
7FFFH
0080H
007FH
CALLT table area
Program area
0040H
003FH
Internal ROM
32768 × 8 bits
Program memory
space
002CH
002BH
Vector table area
0000H
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-3. Memory Map (µPD789834, 789834A, 789834B)
FFFFH
Special function registers
(SFRs)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
LCD display RAMNote
288 × 8 bits
F9E0H
F9DFH
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Data memory
space
Internal low-speed RAM
1216 × 8 bits
BFFFH
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
Program area
Reserved
C000H
BFFFH
0080H
007FH
CALLT table area
Program area
0040H
003FH
Internal ROM
49152 × 8 bits
Program memory
space
002CH
002BH
Vector table area
0000H
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-4. Memory Map (µPD789835, 789835A, 789835B)
FFFFH
Special function registers
(SFRs)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
LCD display RAMNote
288 × 8 bits
F9E0H
F9DFH
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Data memory
space
Internal low-speed RAM
1216 × 8 bits
EFFFH
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
Program area
0080H
007FH
Program memory
space
CALLT table area
Program area
Internal ROM
61440 × 8 bits
0040H
003FH
002CH
002BH
Vector table area
0000H
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-5. Memory Map (µPD78F9835)
FFFFH
Special function registers
(SFRs)
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
LCD display RAMNote
288 × 8 bits
F9E0H
F9DFH
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Data memory
space
Internal low-speed RAM
1216 × 8 bits
EFFFH
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
Program area
0080H
007FH
Flash memory
61440 × 8 bits
Program memory
space
CALLT table area
Program area
0040H
003FH
002CH
002BH
Vector table area
0000H
0000H
Note Can be used as normal RAM when not being used for LCD display.
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3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The µPD789835, 789835A, 789835B Subseries provide internal ROM (or flash memory) with the following
capacity for each product.
Table 3-1. Internal ROM Capacity
Part Number
Internal ROM
Structure
Mask ROM
Capacity
µPD789832, 789832A, 789832B
µPD789833, 789833A, 789833B
µPD789834, 789834A, 789834B
µPD789835, 789835A, 789835B
µPD78F9835
24576 × 8 bits
32768 × 8 bits
49152 × 8 bits
61440 × 8 bits
61440 × 8 bits
Flash memory
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 44-byte area of addresses 0000H to 002BH is reserved as a vector table area. This area stores program
start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16-
bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an
odd address.
Table 3-2. Vector Table
Vector Table Address
0 0 0 0 H
Interrupt Request
RESET input
Vector Table Address
0 0 1 8 H
Interrupt Request
INTWT
0 0 0 4 H
0 0 0 6 H
0 0 0 8 H
0 0 0 A H
0 0 0 C H
0 0 0 E H
0 0 1 0 H
0 0 1 2 H
0 0 1 4 H
0 0 1 6 H
INTWDT1
INTP0
0 0 1 A H
0 0 1 C H
0 0 1 EH
0 0 2 0 H
0 0 2 2 H
0 0 2 4 H
0 0 2 6 H
0 0 2 8 H
0 0 2 A H
INTWTI
INTTM80
INTTM81
INTTM82
INTTM30
INTTM40
INTTMSG0
INTAD
INTP1
INTCSI10
INTSER00
INTSR00
INTST00
INTTM50
INTTM51
INTTM52
INTKR00
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
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3.1.2 Internal data memory space
The µPD789835, 789835A, 789835B Subseries products incorporate the following RAM.
(1) Internal RAM
The µPD789835, 789835A, 789835B Subseries incorporate the following RAM.
Table 3-3. Internal RAM Capacity
Part Number
Capacity
µPD789832, 789832A, 789832B
µPD789833, 789833A, 789833B
µPD789834, 789834A, 789834B
µPD789835, 789835A, 789835B
µPD78F9835
2240 bytes (high-speed RAM 1024 bytes + low-speed RAM 1216 bytes)
3264 bytes (high-speed RAM 1024 bytes + low-speed RAM 2240 bytes)
The internal high-speed RAM is also used as a stack.
(2) LCD display RAM
LCD display RAM is allocated in the area between F8C0H and FAFFH. The LCD display RAM can also be
used as ordinary RAM.
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H and
FFFFH (see Table 3-4).
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3.1.4 Data memory addressing
The µPD789835, 789835A, 789835B Subseries are provided with a variety of addressing modes to make memory
manipulation as efficient as possible. At the addresses corresponding to data memory area especially, specific
addressing modes that correspond to the particular function an area, such as the special function registers are
available. Figures 3-6 to 3-10 show the data memory addressing modes.
Figure 3-6. Data Memory Addressing (µPD789832, 789832A, 789832B)
FFFFH
Special function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
LCD display RAMNote
Direct addressing
288 × 8 bits
F9E0H
Register indirect addressing
F9DFH
LCD display RAMNote
Based addressing
288 × 8 bits
F8C0H
F8BFH
Internal low-speed RAM
1216 × 8 bits
F400H
F3FFH
Reserved
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-7. Data Memory Addressing (µPD789833, 789833A, 789833B)
FFFFH
Special function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
LCD display RAMNote
Direct addressing
288 × 8 bits
F9E0H
F9DFH
Register indirect addressing
Based addressing
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Internal low-speed RAM
1216 × 8 bits
F400H
F3FFH
Reserved
8000H
7FFFH
Internal ROM
32768 × 8 bits
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-8. Data Memory Addressing (µPD789834, 789834A, 789834B)
FFFFH
Special function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
LCD display RAMNote
Direct addressing
288 × 8 bits
F9E0H
F9DFH
Register indirect addressing
Based addressing
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Internal low-speed RAM
1216 × 8 bits
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
C000H
BFFFH
Reserved
Internal ROM
49152 × 8 bits
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-9. Data Memory Addressing (µPD789835, 789835A, 789835B)
FFFFH
Special function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
LCD display RAMNote
Direct addressing
288 × 8 bits
F9E0H
F9DFH
Register indirect addressing
Based addressing
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Internal low-speed RAM
1216 × 8 bits
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
Internal ROM
61440 × 8 bits
0000H
Note Can be used as normal RAM when not being used for LCD display.
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Figure 3-10. Data Memory Addressing (µPD78F9835)
FFFFH
Special function registers (SFRs)
SFR addressing
256 × 8 bits
FF20H
FF1FH
FF00H
FEFFH
Short direct addressing
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
LCD display RAMNote
Direct addressing
288 × 8 bits
F9E0H
F9DFH
Register indirect addressing
Based addressing
LCD display RAMNote
288 × 8 bits
F8C0H
F8BFH
Internal low-speed RAM
1216 × 8 bits
F400H
F3FFH
Internal low-speed RAM
1024 × 8 bits
F000H
EFFFH
Flash memory
61440 × 8 bits
0000H
Note Can be used as normal RAM when not being used for LCD display.
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3.2 Processor Registers
The µPD789835, 789835A, 789835B Subseries provide the following on-chip processor registers.
3.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Program Counter Configuration
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
The program status word contents are automatically stacked upon interrupt request generation or PUSH
PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets PSW to 02H.
Figure 3-12. Program Status Word Configuration
7
0
IE
Z
0
AC
0
0
1
CY
PSW
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(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgment operations of the CPU.
When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable
interrupt are all disabled.
When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgment enable is
controlled with an interrupt mask flag for various interrupt sources.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-13. Stack Pointer Configuration
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-14. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
instruction
CALL, CALLT
instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Lower
register pairs
SP
PC7 to PC0
Higher
register pairs
SP
SP
PC15 to PC8
SP
SP
SP
SP
Figure 3-15. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower
register pairs
SP
SP
SP + 1
PC7 to PC0
SP
PC7 to PC0
PC15 to PC8
PSW
Higher
register pairs
PC15 to PC8
SP + 1
SP + 1
SP + 2
SP SP + 2
SP SP + 2
SP SP + 3
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3.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL)
or absolute names (R0 to R7 and RP0 to RP3).
Figure 3-16. General-Purpose Register Configuration
(a) Absolute names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Function names
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
The special function registers are allocated in the 256-byte area of FF00H to FFFFH.
Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
The manipulatable bits can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
addressing an address, describe an even address.
Table 3-4 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. The symbols shown in this column are
the reserved words of the assembler, and are defined as an sfr variable by #pragma sfr directive in the C
compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger
is used.
• R/W
Indicates whether the special function register in question can be read or written.
R/W:
R:
Read/write
Read only
Write only
W:
• Bit unit for manipulation
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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Table 3-4. Special Function Registers (1/2)
Address
Special Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation After Reset
1 Bit
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
−
√
√
√
√
−
−
−
−
√
−
−
√
−
−
√
−
−
√
−
−
8 Bits
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16 Bits
FF00H
FF01H
FF02H
FF03H
FF06H
FF08H
FF11H
FF14H
FF15H
FF20H
FF21H
FF22H
FF23H
FF32H
FF33H
FF42H
FF4AH
FF4BH
FF53H
FF54H
FF55H
FF56H
FF57H
FF58H
FF59H
FF5AH
FF5BH
FF5CH
FF5DH
FF5EH
FF5FH
FF60H
FF61H
FF62H
FF63H
FF64H
Port 0
P0
R/W
−
−
−
−
−
−
−
00H
Port 1
P1
Port 2
P2
Port 3
P3
Port 6
P6
R
Undefined
Port 8
P8
A/D conversion result register
16-bit multiplication result store register 0
ADCR
Note 2
√
MUL0Note 1 MUL0L
MUL0H
PM0
Port mode register 0
R/W
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FFH
00H
Port mode register 1
PM1
Port mode register 2
PM2
Port mode register 3
PM3
Pull-up resistor option register B2
Pull-up resistor option register B3
Watchdog timer clock selection register
Watch timer mode control register
Watchdog timer mode register
P3 function register
PUB2
PUB3
WDCS
WTM
WDTM
PF3
Remote control timer control register 50
Remote control timer capture register 50
Remote control timer capture register 51
8-bit compare register 80
TMC50
CP50
R
CP51
CR80
W
R
Undefined
00H
8-bit timer counter 80
TM80
8-bit timer mode control register 80
8-bit compare register 81
TMC80
CR81
R/W
W
Undefined
00H
8-bit timer counter 81
TM81
R
8-bit timer mode control register 81
8-bit compare register 82
TMC81
CR82
R/W
W
Undefined
00H
8-bit timer counter 82
TM82
R
8-bit timer mode control register 82
8-bit compare register 30
TMC82
CR30
R/W
W
Undefined
00H
8-bit timer counter 30
TM30
R
8-bit timer mode control register 30
8-bit compare register 40
TMC30
CR40
R/W
W
Undefined
8-bit H width compare register 40
CRH40
Notes 1. This symbol is for 16-bit access only.
2. 16-bit access is enabled for short direct addressing only.
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Table 3-4. Special Function Registers (2/2)
Address
Special Function Register (SFR) Name
Symbol
R/W Bit Units for Manipulation After Reset
8 Bits 16 Bits
1 Bit
−
√
−
−
−
√
−
−
√
−
−
√
√
√
−
−
−
√
−
−
√
√
−
−
−
−
√
√
√
√
√
√
√
−
√
√
√
√
−
√
FF65H
FF66H
FF67H
FF68H
FF6AH
FF6BH
FF6CH
FF6DH
FF72H
FF74H
8-bit timer counter 40
TM40
R
R/W
W
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
00H
8-bit timer mode control register 40
Carrier generator output control register 40
8-bit compare register SG0
TMC40
TCA40
Undefined
00H
CRSG0
TMSG0
TMCSG0
TCASG0
SGFC00
CSIM10
SIO10
8-bit timer counter SG0
R
8-bit timer mode control register SG0
Carrier generator output control register SG0
Sound generator frequency setting register 00
Serial operation mode register 10
Transmission/reception shift register 10
R/W
W
R/W
W
R
Undefined
00H
FF80H
FF84H
FFA0H
FFA1H
FFA2H
A/D converter mode register
ADM
R/W
A/D input selection register
ADS
Asynchronous serial interface mode register 00
Baud rate generator control register 00
Transmit shift register 00
ASIM00
BRGC00
TXS00
RXB00
ASIS00
SWP0Note
W
R
Undefined
FFH
Receive buffer register 00
FFA3H
FFABH
Asynchronous serial interface status register 00
Swapping function register 0
00H
W
R
Undefined
00H
FFAFH
FFB0H
FFB2H
FFB3H
FFD0H
FFD1H
FFD2H
FFE0H
FFE1H
FFE2H
FFE4H
FFE5H
FFE6H
FFECH
FFF0H
FFF2H
FFF5H
FFF7H
FFFAH
FFFBH
Power supply control register 0
LCD20 display mode register
LCD20 clock control register
LCD boost voltage level setting register 00
Multiplication data register A0
Multiplication data register B0
Multiplier control register 0
PSC0
LCDM20
LCDC20
VLCD00
MRA0
MRB0
MULC0
IF0
R/W
W
Undefined
00H
R/W
Interrupt request flag register 0
Interrupt request flag register 1
Interrupt request flag register 2
Interrupt mask flag register 0
Interrupt mask flag register 1
Interrupt mask flag register 2
External interrupt mode register 0
Suboscillation mode register
Subclock control register
IF1
IF2
MK0
FFH
00H
MK1
MK2
INTM0
SCKM
CSS
Key return mode register 00
KRM00
PU0
Pull-up resistor option register 0
Oscillation stabilization time selection register
Processor clock control register
OSTS
PCC
04H
02H
Note The initial value in read mode differs from that in write mode. For details, see CHAPTER 16 SWAPPING
(SWAP).
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CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series
Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between –128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC is the start address of
the next instruction of
a BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, α indicates all bits 0.
When S = 1, α indicates all bits 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
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CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
7
6
1
5
1
0
0
Instruction code
Effective address
0
ta4-0
15
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
0
7
Memory (Table)
Low Addr.
0
High Addr.
Effective address + 1
15
8
7
0
PC
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated with immediate data in an instruction word is directly addressed.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (Lower)
addr16 (Higher)
Memory
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CHAPTER 3 CPU ARCHITECTURE
3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed
RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and the compare register of the timer counter are mapped in
this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code
1
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
90H (saddr-offset)
50H (Immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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CHAPTER 3 CPU ARCHITECTURE
3.4.3 Special function register (SFR) addressing
[Function]
The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
1
1
0
0
0
0
1
0
1
0
1
0
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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CHAPTER 3 CPU ARCHITECTURE
3.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by a register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specification code
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3.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
7
0
0
DE
D
E
Memory address
specified with
register pair DE.
Addressed memory
contents are
transferred.
7
0
A
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Only the internal high-speed RAM area can be addressed using stack addressing.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The µPD789835, 789835A, 789835B Subseries provide the ports shown in Figure 4-1, enabling various methods
of control. Table 4-1 shows the functions of the ports.
Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more
information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P30
P00
Port 0
Port 1
Port 3
Port 6
P07
P37
P60
P10
P11
P62
P80
P20
Port 2
Port 8
P87
P27
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CHAPTER 4 PORT FUNCTIONS
Table 4-1. Port Functions
Port Name
Port 0
Pin Name
P00 to P07
Function
This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be specified using pull-up
resistor option register 0 (PU0).
Port 1
Port 2
Port 3
P10, P11
This is an I/O port for which input and output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistors can be specified using pull-up
resistor option register 0 (PU0).
P20 to P27
P30 to P37
This is an I/O port for which input and output can be specified in 1-bit units.
On-chip pull-up resistors can be specified using pull-up resistor option register B2
(PUB2).
This is an I/O port for which input and output can be specified in 1-bit units.
On-chip pull-up resistors can be specified using pull-up resistor option register B3
(PUB3).
Port 6
Port 8
P60 to P62
P80 to P87
This is an input port.
This is an input port.
4.2 Port Configuration
The ports include the following hardware.
Table 4-2. Configuration of Port
Item
Configuration
Control registers
Port mode registers (PM0 to PM3)
Pull-up resistor option registers (PU0, PUB2, PUB3)
Total: 37 (CMOS I/O: 26, CMOS input: 11)
Total: 26 (software control: 26)
Ports
Pull-up resistors
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CHAPTER 4 PORT FUNCTIONS
4.2.1 Port 0
This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by
using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can
be connected in 8-bit units by using pull-up resistor option register 0 (PU0).
This port is also used for key return input.
Port 0 is set in the input mode when the RESET signal is input.
Figure 4-2 shows a block diagram of port 0.
Figure 4-2. Block Diagram of P00 to P07
V
DD
WRPU0
PU00
P-ch
RD
WRKRM00
WRPORT
WRPM
KRM00
Output latch
(P00 to P07)
P00/KR00 to
P07/KR07
PM00 to PM07
Alternate
function
KRM00: Key return mode register 00
PU0:
PM:
RD:
Pull-up resistor option register 0
Port mode register
Port 0 read signal
WR:
Port 0 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by
using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can
be connected in 2-bit units by using pull-up resistor option register 0 (PU0).
This port is set in the input mode when the RESET signal is input.
Figure 4-3 shows a block diagram of port 1.
Figure 4-3. Block Diagram of P10 and P11
V
DD
WRPU0
PU01
P-ch
RD
WRPORT
Output latch
(P10, P11)
P10, P11
WRPM
PM10, PM11
PU0:
PM:
RD:
Pull-up resistor option register 0
Port mode register
Port 1 read signal
WR:
Port 1 write signal
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4.2.3 Port 2
This is an 8-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by
using port mode register 2 (PM2). On-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor
option register B2 (PUB2) regardless of the setting of the I/O mode.
The port is also used as a data I/O to and from the serial interface, external interrupt input, and timer I/O.
This port is set in the input mode when the RESET signal is input.
Figures 4-4 to 4-7 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 13-2 Settings of
Serial Interface Operating Mode.
Figure 4-4. Block Diagram of P20
V
DD
WRPUB2
PUB20
P-ch
Alternate
function
RD
WRPORT
WRPM
Output latch
(P20)
P20/SCK10
PM20
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-5. Block Diagram of P21
V
DD
WRPUB2
PUB21
P-ch
RD
WRPORT
Output latch
(P21)
P21/SO10/TxD00
WRPM
PM21
Alternate
function
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-6. Block Diagram of P22 to P24 and P26
VDD
WRPUB2
PUB22 to PUB24,
PUB26
P-ch
Alternate
function
RD
WRPORT
Output latch
(P22 to P24, P26)
P22/SI10/RxD00,
P23/INTP0/TI80,
P24/INTP1,
WRPM
P26/RIN
PM22 to PM24,
PM26
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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Figure 4-7. Block Diagram of P25 and P27
V
DD
WRPUB2
PUB25, PUB27
P-ch
RD
WRPORT
Output latch
(P25, P27)
P25/TO82,
P27/TO40
WRPM
PM25, PM27
Alternate
function
PUB2: Pull-up resistor option register B2
PM:
RD:
WR:
Port mode register
Port 2 read signal
Port 2 write signal
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4.2.4 Port 3
This is an 8-bit I/O port with an output latch. Only the bits specified for the port function by the P3 function register
(PF3) can be used. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3
(PM3). On-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B3 (PUB3)
regardless of the setting of the I/O mode.
This port is also used as a sound generator output.
This port is set in the input mode when the RESET signal is input.
Figure 4-8 shows block diagram of port 3.
Figure 4-8. Block Diagram of P30 to P37
V
DD
WRPU0
PUB30 to PUB37
P-ch
RD
WRPORT
Output latch
(P30 to P37)
WRPM
P30/SG0 to
P37/SG7
PM30 to PM37
Alternate
function
PF3
PF3: P3 function register
PUB3: Pull-up resistor option register B3
PM: Port mode register
RD: Port 3 read signal
WR: Port 3 write signal
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4.2.5 Port 6
This is a 3-bit input-only port.
This port is also used as the analog input of an A/D converter.
Figure 4-9 shows a block diagram of port 6.
Figure 4-9. Block Diagram of P60 to P62
RD
+
P60/ANI0 to P62/ANI2
A/D converter
−
VREF
RD: Port 6 read signal
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4.2.6 Port 8
This is an 8-bit input-only port.
This port is also used for segment output. When used for segment output, P80/LCD88 to P87/LCD95 become
output-only pins.
This port is set in the input mode when the RESET signal is input.
Figure 4-10 shows a block diagram of port 8.
Figure 4-10. Block Diagram of P80 to P87
VDD
RD
VSS
P80/LCD88 to
P87/LCD95
Segment output
LCDM201
LCDM200
LCDM201: Bit 1 of the LCD20 display mode register (LCDM20)
LCDM200: Bit 0 of the LCD20 display mode register (LCDM20)
RD:
Port 8 read signal
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4.3 Registers Controlling Port Function
The ports are controlled by the following two types of registers.
• Port mode registers (PM0 to PM3)
• Pull-up resistor option registers (PU0, PUB2, PUB3)
(1) Port mode registers (PM0 to PM3)
These registers are used to set port input/output in 1-bit units.
The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 4-3.
Caution As Port 2 has an alternate function as external interrupt input, when the port function
output mode is specified and the output level is changed, the interrupt request flag is set.
When the output mode is used, therefore, the interrupt mask flag (PMK0) should be preset
to 1.
Figure 4-11. Format of Port Mode Register
Symbol
PM0
7
6
5
4
3
2
1
0
Address
FF20H
After reset R/W
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFH
FFH
FFH
FFH
R/W
R/W
R/W
R/W
PM1
PM2
PM3
1
1
1
1
1
1
PM11
PM21
PM31
PM10
PM20
PM30
FF21H
FF22H
FF23H
PM27
PM37
PMmn
PM26
PM36
PM25
PM35
PM24
PM34
PM23
PM33
PM22
PM32
Pmn pin I/O mode selection
(m = 0 to 3 n = 0 to 7)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Pin Name
Alternate Function
Name
PM××
P××
I/O
P00 to P07
KR00 to KR07
INTP0
Input
Input
Input
Input
1
1
1
1
0
1
0
×
×
×
×
×
×
0
×
0
×
×
P23
TI80
P24
INTP1
P25
TO82
Output
Input
P26
RIN
P27
TO40
Output
Output
Output
P30 to P37
P80 to P87
SG0 to SG7Note 1
LCD88 to LCD95Note 2
Notes 1. These are set by the P3 function register (PF3) when used as alternate-function pins. For details of
these settings, see Figure 9-5 Format of P3 Function Register.
2. These are set by the LCD20 display mode register (LCDM20) when used as alternate-function pins. For
details of these settings, see Figure 14-2 Format of LCD20 Display Mode Register.
Caution When port 2 is used as a serial interface pin, the I/O latch or output latch must be set according
to its function. For the setting method, see Table 13-2 Settings of Serial Interface Operating
Mode.
Remark ×:
PM××: Port mode register
P××: Port output latch
don’t care
(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor on ports 0 and 1 is used or
not in port units. On the port specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be
internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set
in the output mode regardless of the setting of PU0. This also applies to cases when the pins are used for
alternate functions.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 4-12. Format of Pull-Up Resistor Option Register 0
Symbol
PU0
7
0
6
0
5
0
4
0
3
0
2
0
<1>
<0>
Address After reset
FFF7H 00H
R/W
R/W
PU01
PU00
PU0m
Pm on-chip pull-up resistor selection
(m = 0, 1)
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Caution Be sure to clear bits 2 to 7 to 0.
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(3) Pull-up resistor option register B2 (PUB2)
This register is used to set whether or not to use an on-chip pull-up resistor for P20 to P27. At the pins where
use of a pull-up resistor is specified by PUB2, an on-chip pull-up resistor can be used regardless of the
setting of the I/O mode. This also applies to cases when the pins are used for alternate functions.
PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB2 to 00H.
Figure 4-13. Format of Pull-Up Resistor Option Register B2
Symbol
PUB2
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
FF32H 00H
R/W
R/W
PUB27
PUB26
PUB25
PUB24
PUB23
PUB22
PUB21
PUB20
PUB2n
Selection of On-chip Pull-up Resistor for P2n
(n = 0 to 7)
0
1
On-chip pull-up resistor not connected
On-chip pull-up resistor connected
Caution Clear PUB2n to 0 to use P2n in the output mode or use its alternate output pin function.
Otherwise, a high level will be always output.
(4) Pull-up resistor option register B3 (PUB3)
This register is used to set whether or not to use an on-chip pull-up resistor for P30 to P37. At the pins where
use of a pull-up resistor is specified by PUB3, an on-chip pull-up resistor can be used regardless of the
setting of the I/O mode. This also applies to cases when the pins are used for alternate functions.
PUB3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB3 to 00H.
Figure 4-14. Format of Pull-Up Resistor Option Register B3
Symbol
PUB3
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address After reset
FF33H 00H
R/W
R/W
PUB37
PUB36
PUB35
PUB34
PUB33
PUB32
PUB31
PUB30
PUB3n
Selection of On-chip Pull-up Resistor for P3n
(n = 0 to 7)
0
1
On-chip pull-up resistor not connected
On-chip pull-up resistor connected
Caution Clear PUB3n to 0 to use P3n in the output mode or use its alternate output pin function.
Otherwise, a high level will be always output.
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4.4 Port Function Operation
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
Data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
4.4.2 Reading from I/O port
(1) In output mode
The status of an output latch can be read by using a transfer instruction. The contents of the output latch are
not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
4.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an I/O port, therefore, the contents of the output latch of the
pin that is set in the input mode and not subject to manipulation become undefined.
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5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three types of system clock oscillators are used.
• Main system clock (ceramic/crystal) oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Main system clock (RC) oscillator
This circuit oscillates at 0.4 to 2.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
5.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators
Main system clock oscillator
Subsystem clock oscillator
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Figure 5-1. Block Diagram of Clock Generator
Internal bus
Suboscillation mode register
FRC
SCC
(SCKM)
Subsystem
clock
oscillator
XT1
XT2
8-bit timers 81, 82
Sound generator
Watch timer
fXT
Watchdog timer
LCD controller/driver
1/2
SEL
X1/CL1
X2/CL2
Main system
clock
oscillator
Clock to peripheral
hardware
fX or fCC
Prescaler
f
X
22
f
CC
22
or
fXT
2
Standby
controller
Wait
controller
CPU clock
(fCPU
)
fX or fCC
STOP
CLS CSS0
MCC PCC1
Processor clock
control register (PCC)
Subclock control
register (CSS)
Internal bus
Caution Connect the SEL pin to VSS when these pins are used as the X1 and X2 pins (ceramic/crystal
oscillation (fX)), and to VDD when used as the CL1 and CL2 pins (RC oscillation (fCC)).
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5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following three registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol
PCC
<7>
6
0
5
0
4
0
3
0
2
0
1
0
0
Address After reset
FFFBH 02H
R/W
R/W
MCC
PCC1
MCC
Control of main system clock oscillator operation
0
1
Operation enabled
Operation disabled
CSS0
PCC1
Selection of CPU clock (fCPU)Note
@ fX = 5.0 MHz and fXT = 32.768 kHz operation @ fCC = 2.0 MHz and fXT = 32.768 kHz operation
0
0
1
1
0
1
0
1
fX (0.2 µs)
fX/22 (0.8 µs)
fCC (0.5 µs)
fCC/22 (2.0 µs)
fXT/2 (61 µs)
Note The CPU clock is selected according to a combination of the PCC and CSS flags (See 5.3 (3)
Subclock control register (CSS)).
Cautions 1. Be sure to clear bits 0 and 2 to 6 to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU
clock.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
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The minimum instruction execution time is expressed in units of two CPU clock cycles (fCPU). The following
table shows minimum instruction execution time based on each setting value.
CSS0
PCC1
Minimum instruction execution time
@ fX = 5.0 MHz and fXT = 32.768 kHz operation @ fCC = 2.0 MHz and fXT = 32.768 kHz operation
0
0
1
1
0
1
0
1
0.4 µs
1.6 µs
122 µs
1.0 µs
4.0 µs
(2) Suboscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SCKM to 00H.
Figure 5-3. Format of Suboscillation Mode Register
Symbol
SCKM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address After reset
FFF0H 00H
R/W
R/W
FRC
SCC
FRC
Feedback resistor selectionNote
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
SCC
Control of subsystem clock oscillator operation
0
1
Operation enabled
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the
mid point of the supply voltage. Only when the subclock is not used, the current consumption in
STOP mode can be further reduced by setting FRC = 1.
Caution Be sure to clear bits 2 to 7 to 0.
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(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSS to 00H.
Figure 5-4. Format of Subclock Control Register
Symbol
CSS
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Address After reset
FFF2H 00H
R/W
CLS
CSS0
R/WNote
CLS
0
CPU clock operation status
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
1
CSS0
Selection of the main system or subsystem clock oscillator
Divided output from the main system clock oscillator
Output from the subsystem clock oscillator
0
1
Note Bit 5 is read-only.
Caution Be sure to clear bits 0 to 3, 6, and 7 to 0.
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5.4 System Clock Oscillators
There are two types of system clock oscillators: the main system clock oscillator and the subsystem clock
oscillator.
With the µPD789835, 789835A, 789835B Subseries, the main system clock oscillator can be switched between
ceramic/crystal oscillation and RC oscillation. Switch between ceramic/crystal oscillation and RC oscillation using the
SEL pin. When using ceramic/crystal oscillation, connect the SEL pin to VSS. When using RC oscillation, connect it to
VDD.
5.4.1 Main system clock oscillator (crystal/ceramic oscillation)
This oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2
pins.
Figure 5-5 shows the external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator (Ceramic/Crystal Oscillation)
V
SS
X1
X2
Crystal
or
ceramic resonator
5.4.2 Main system clock oscillator (RC oscillation)
This oscillator is oscillated by the resistor (R) and capacitor (C) (2.0 MHz TYP.) connected across the CL1 and
CL2 pins.
Figure 5-6 shows the external circuit of the main system clock oscillator.
Figure 5-6. External Circuit of Main System Clock Oscillator (RC Oscillation)
CL1
C
R
CL2
VSS
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5.4.3 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
Figure 5-7 shows the external circuit of the subsystem clock oscillator.
Figure 5-7. External Circuit of Subsystem Clock Oscillator
V
SS
XT1
32.768
kHz
XT2
Crystal resonator
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 5-5 to 5-7 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as
a low-amplitude circuit for reducing current consumption.
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5.4.4 Example of incorrect resonator connection
Figure 5-8 shows an example of incorrect connection for ceramic/crystal oscillation and Figure 5-9 shows an
example for RC oscillation.
Figure 5-8. Examples of Incorrect Connection for Ceramic/Crystal Oscillation (1/2)
(a) Too long wiring
(b) Crossed signal line
PORTn
(n = 0 to 3, 6, 8)
VSS
X1
X2
VSS
X1
X2
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD
P
mn
X1
X2
VSS
V
SS
X1
X2
High current
A
B
C
High current
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
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Figure 5-8. Examples of Incorrect Connection for Ceramic/Crystal Oscillation (2/2)
(e) Signal is fetched
X1
X2
VSS
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
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Figure 5-9. Examples of Incorrect Connection for RC Oscillation (1/3)
(a) Too long wiring
• Main system clock
• Subsystem clock
CL1
CL2
VSS
XT1
XT2
V
SS
(b) Crossed signal line
• Main system clock
• Subsystem clock
PORTn
(n = 0 to 3, 6, 8)
PORTn
(n = 0 to 3, 6, 8)
V
SS
CL1
CL2
V
SS
XT1
XT2
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Figure 5-9. Examples of Incorrect Connection for RC Oscillation (2/3)
(c) Wiring near high fluctuating current
• Main system clock
• Subsystem clock
XT2
XT1
VSS
CL1
CL2
V
SS
High current
High current
(d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
• Main system clock
• Subsystem clock
VDD
V
DD
PORTn
(n = 0 to 3)
PORTn
(n = 0 to 3)
XT1
XT2
V
SS
CL1
CL2
V
SS
A
B
C
High current
A
B
High current
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Figure 5-9. Examples of Incorrect Connection for RC Oscillation (3/3)
(e) Signal is fetched
• Main system clock
• Subsystem clock
VSS
XT1
XT2
CL1
CL2
V
SS
5.4.5 Divider
The divider divides the output of the main system clock oscillator (fX or fCC) to generate various clocks.
5.4.6 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
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CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock
• Subsystem clock
fX or fCC
fXT
• CPU clock
fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode of the main system clock is selected when the RESET signal is generated (PCC =
02H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped.
(b) Three types of minimum instruction execution times (for details, see Figure 5-2 Format of Processor
Clock Control Register) can be selected by the PCC, SCKM, and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem
clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122 µs: at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the 8-bit timers 81, 82, sound generator, watch
timer, watchdog timer, and LCD controller/driver. The 8-bit timers 81, 82, sound generator, watch timer,
watchdog timer, and LCD controller/driver can therefore keep running even during standby. The other
hardware stops when the main system clock stops because it runs based on the main system clock
(except for external input clock operations).
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CHAPTER 5 CLOCK GENERATOR
5.6 Changing Setting of System Clock and CPU Clock
5.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Tables 5-2 and 5-3).
Table 5-2. Maximum Time Required for Switching CPU Clock (When Ceramic/Crystal Oscillation Is Selected)
Set Value Before Switching
Set Value After Switching
CSS0
PCC1
CSS0
0
PCC1
0
CSS0
0
PCC1
1
CSS0
1
PCC1
×
0
0
1
×
4 clocks
2 clocks
2fX/fXT clocks
(306 clocks)
2 clocks
2 clocks
fX/2fXT clocks
(76 clocks)
1
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. ×: don’t care
Table 5-3. Maximum Time Required for Switching CPU Clock (When RC Oscillation Is Selected)
Set Value Before Switching
Set Value After Switching
CSS0
PCC1
CSS0
0
PCC1
0
CSS0
0
PCC1
1
CSS0
1
PCC1
×
0
0
1
×
4 clocks
2 clocks
2fCC/fXT clocks
(122 clocks)
2 clocks
2 clocks
fCC/2fXT clocks
(31 clocks)
1
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fCC = 2.0 MHz or fXT = 32.768 kHz.
3. ×: don’t care
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CHAPTER 5 CLOCK GENERATOR
5.6.2 Switching between system clock and CPU clock
(1) When ceramic/crystal oscillation is selected
The following describes switching between the system clock and CPU clock when ceramic/crystal oscillation
is selected for the main system clock.
Figure 5-10. Switching Between System Clock and CPU Clock (Ceramic/Crystal Oscillation)
VDD
RESET
Interrupt request signal
f
X
f
X
f
XT
f
X
System clock
CPU clock
Low-speed
operation
High-speed
operation
High-speed operation
Subsystem clock
operation
Oscillation stabilization time wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6 µs: at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is cleared to 0,
and then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 5 CLOCK GENERATOR
(2) When RC oscillation is selected
The following describes switching between the system clock and CPU clock when RC oscillation is selected
for the main system clock.
Figure 5-11. Switching Between System Clock and CPU Clock (RC Oscillation)
V
DD
RESET
Interrupt request signal
f
CC
f
CC
f
XT
f
CC
System clock
CPU clock
Low-speed
operation
High-speed
operation
High-speed operation
Subsystem clock
operation
µ
Oscillation stabilization time wait (64 s: at 2.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (4.0 µs: at
2.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is cleared to 0,
and then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.1 8-Bit Timer/Event Counters 80 to 82 Functions
The 8-bit timer/event counters (timer 80, timer 81, and timer 82) have the following functions:
• Interval timers (timer 80, timer 81, and timer 82)
• External event counter (timer 80 only)
• Square wave output (timer 82 only)
The µPD789835, 789835A, 789835B Subseries is provided with a channel (timer 80) of an 8-bit timer/event
counter and two channels (timer 81 and timer 82) of an 8-bit timer. When reading the description of timer 81 and timer
82, an 8-bit timer/event counter should be read as referring to an 8-bit timer.
(1) 8-bit interval timer
When the 8-bit timer/event counter is used as an interval timer, it generates an interrupt at any time intervals
set in advance.
(2) External event counter (timer 80 only)
The number of pulses of an externally input signal can be measured.
(3) Square wave output (timer 82 only)
A square wave of any frequency can be output.
6.2 8-Bit Timer/Event Counters 80 to 82 Configuration
8-bit timer/event counters 80 to 82 include the following hardware.
Table 6-1. Configuration of 8-Bit Timer/Event Counters 80 to 82
Item
Timer counters
Configuration
8 bits × 3 (TM80, TM81, and TM82)
Registers
Compare registers: 8 bits × 3 (CR80, CR81, and CR82)
Timer output
Control registers
1 (TO82)
8-bit timer mode control registers 80, 81, and 82 (TMC80, TMC81, and TMC82)
Port mode register 2 (PM2)
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
Figure 6-1. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
8-bit compare register 80
(CR80)
Match
INTTM80
f
CLK/26
CLK/29
8-bit timer counter 80
(TM80)
f
Clear
TI80/P23/INTP0
Selector
2
TCE80 TCL801 TCL800
8-bit timer mode
control register 80 (TMC80)
Internal bus
Remark fCLK: fX or fCC
Figure 6-2. Block Diagram of 8-Bit Timer 81
Internal bus
8-bit compare register 81
(CR81)
Match
INTTM81
f
CLK/24
CLK/28
f
8-bit timer counter 81 (TM81)
Clear
f
XT
Selector
2
TCE81 TCL811 TCL810
8-bit timer mode
control register 81 (TMC81)
Internal bus
Remark
f
CLK: f or fCC
X
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
Figure 6-3. Block Diagram of 8-Bit Timer 82
Internal bus
8-bit compare register 82
(CR82)
P25
output latch
PM25
Match
INTTM82
TO82/P25
f
CLK/23
8-bit timer counter 82
(TM82)
f
CLK/210
F/F
Clear
Selector
fXT
2
TCE82 TCL821 TCL820 TOE82
8-bit timer mode
control register 82 (TMC82)
Internal bus
Remark fCLK: fX or fCC
(1) 8-bit compare register 8n (CR8n)
This is an 8-bit register to compare the value set to CR8n with 8-bit timer counter 8n (TM8n) count value, and
if they match, generates an interrupt request (INTTM8n).
CR8n is set with an 8-bit memory manipulation instruction. The 00H to FFH values can be set.
RESET input makes CR8n undefined.
Caution Be sure to stop the operation of the timer before rewriting CR8n. If CR8n is rewritten while
the timer is operation-enabled, an interrupt request match signal may be generated at the
time of the rewrite.
Remark n = 0 to 2
(2) 8-bit timer counter 8n (TM8n)
This is an 8-bit register to count pulses.
TM8n is read with an 8-bit memory manipulation instruction.
RESET input clears TM8n to 00H.
Remark n = 0 to 2
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.3 Registers Controlling 8-Bit Timer/Event Counters 80 to 82
The following two types of registers are used to control 8-bit timer/event counters 80 to 82.
• 8-bit timer mode control registers 80, 81, and 82 (TMC80, TMC81, and TMC82)
• Port mode register 2 (PM2)
(1) 8-bit timer mode control register 80 (TMC80)
This register enables/stops operation of 8-bit timer counter 80 (TM80) and sets the count clock of TM80.
TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC80 to 00H.
Figure 6-4. Format of 8-Bit Timer Mode Control Register 80
<7>
6
0
5
0
4
0
3
0
2
1
0
0
Symbol
Address
FF59H
After reset
00H
R/W
R/W
TMC80 TCE80
TCL801 TCL800
TCE80
8-bit timer counter 80 operation control
0
1
Operation stopped (TM80 is cleared to 00H)
Operation enabled
TCL801 TCL800
8-bit timer/event counter 80 count clock selection
= 5.0 MHz operation
@fCC = 2.0 MHz operation
@fX
CC/26
CC/29
/26 (
)
0
0
1
1
0
1
0
1
f
X
78.1 kHz
(31.3 kHz)
(3.91 kHz)
f
f
fX
/29 (9.76 kHz)
Rising edge of TI80
Falling edge of TI80
Cautions 1. Be sure to stop the operation of the timer before setting TMC80.
2. Be sure to clear bits 3 to 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. The parenthesized values apply to operation at fX = 5.0 MHz or fCC = 2.0 MHz.
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
(2) 8-bit timer mode control register 81 (TMC81)
TMC81 determines whether to enable or stop operation of 8-bit timer counter 81 (TM81) and specifies the
count clock for 8-bit timer 81.
TMC81 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC81 to 00H.
Figure 6-5. Format of 8-Bit Timer Mode Control Register 81
Symbol <7>
6
0
5
0
4
0
3
0
2
1
0
0
Address
FF5CH
After reset
00H
R/W
R/W
TMC81 TCE81
TCL811 TCL810
TCE81
8-bit timer counter 81 operation control
0
1
Operation stopped (TM81 is cleared to 00H)
Operation enabled
TCL811 TCL810
8-bit timer 81 count clock selection
= 5.0 MHz and fXT = 32.768 kHz operation @fCC = 2.0 MHz and fXT = 32.768 kHz operation
@fX
f
f
CC/24 (125 kHz)
CC/28 (7.81 kHz)
0
0
1
1
0
1
0
1
f
f
f
X
X
/24 (312.5 kHz)
/28 (19.5 kHz)
XT
(32.768 kHz)
Cautions 1. Be sure to stop the operation of the timer before setting TMC81.
2. Be sure to clear bits 3 to 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz, fCC = 2.0 MHz, or fXT = 32.768 kHz.
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
(3) 8-bit timer mode control register 82 (TMC82)
TMC82 determines whether to enable or stop operation of 8-bit timer counter 82 (TM82) and specifies the
count clock for 8-bit timer 82. It also controls the operation of the output controller.
TMC82 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC82 to 00H.
Figure 6-6. Format of 8-Bit Timer Mode Control Register 82
Symbol <7>
6
0
5
0
4
0
3
0
2
1
<0>
Address
FF5FH
After reset
00H
R/W
R/W
TMC82 TCE82
TCL821 TCL820 TOE82
TCE82
8-bit timer counter 82 operation control
0
1
Operation stopped (TM82 is cleared to 00H)
Operation enabled
TCL821 TCL820
8-bit timer 82 count clock selection
= 5.0 MHz and fXT = 32.768 kHz operation @fCC = 2.0 MHz and fXT = 32.768 kHz operation
@fX
fX/23 (625 kHz)
fX/210 (4.88 kHz)
CC/23 (250 kHz)
CC/210 (1.95 kHz)
0
0
1
1
0
1
0
1
f
f
fXT
(32.768 kHz)
TOE82
8-bit timer 82 operation control
0
1
Output disabled (port mode)
Output enabled
Cautions 1. Be sure to stop the operation of the timer before setting TMC82.
2. Be sure to clear bits 3 to 6 to 0.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz, fCC = 2.0 MHz, or fXT = 32.768 kHz.
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
(4) Port mode register 2 (PM2)
This register sets port 2 input/output in 1-bit units.
When using the P23/INTP0/TI80 pin for timer input, set PM23 to 1.
When using the P25/TO82 pin for timer output, clear PM25 and the output latch of P25 to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 6-7. Format of Port Mode Register 2
7
6
5
4
3
2
1
0
Symbol
Address
FF22H
After reset
FFH
R/W
R/W
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
PM2n
P2n pin I/O mode selection (n = 0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.4 8-Bit Timer/Event Counters 80 to 82 Operation
6.4.1 Operation as interval timer
Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare
registers 80, 81, and 82 (CR80, CR81, and CR82) in advance.
To operate 8-bit timer/event counters 80 to 82 as an interval timer, make the settings in the following order.
<1> Set 8-bit timer counter 8n (TM8n) to operation-disabled (TCE8n (bit 7 of 8-bit timer mode control register 8n
(TMC8n)) = 0)
<2> Select the count clock of the 8-bit timer/event counter (see Tables 6-2 to 6-7)
<3> Set the count value to CR8n
<4> Set TM8n to operation-enabled (TCE8n = 1)
When the count value of 8-bit timer counter 8n (TM8n) matches the value set to CR8n, the value of TM8n is
cleared to 00H and TM8n continues counting. At the same time, an interrupt request signal (INTTM8n) is generated.
Tables 6-2 to 6-7 show interval time, and Figures 6-8 and 6-9 show the timing of interval timer operation.
Caution When the setting of the count clock with TMC8n and the setting of TM8n to operation-enable with
an 8-bit memory manipulation instruction are performed at the same time, an error of one clock
or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit
timer/event counter operates as an interval timer, be sure to make the settings in the order
described above.
Remark n = 0 to 2
Table 6-2. Interval Time of 8-Bit Timer/Event Counter 80 (at fX = 5.0 MHz Operation)
TCL801
TCL800
Minimum Interval Time
26/fX (12.8 µs)
Maximum Interval Time
214/fX (3.28 ms)
Resolution
26/fX (12.8 µs)
0
0
1
1
0
1
0
1
29/fX (102 µs)
217/fX (26.2 ms)
29/fX (102 µs)
TI80 input cycle
28 × TI80 input cycle
TI80 input edge cycle
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 6-3. Interval Time of 8-Bit Timer/Event Counter 80 (at fCC = 2.0 MHz Operation)
TCL801
TCL800
Minimum Interval Time
26/fCC (32 µs)
Maximum Interval Time
214/fCC (8.19 ms)
Resolution
26/fCC (32 µs)
0
0
1
1
0
1
0
1
29/fCC (256 µs)
217/fCC (65.5 ms)
29/fCC (256 µs)
TI80 input cycle
28 × TI80 input cycle
TI80 input edge cycle
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
Table 6-4. Interval Time of 8-Bit Timer 81 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation)
TCL811
TCL810
Minimum Interval Time
24/fX (3.2 µs)
Maximum Interval Time
212/fX (819 µs)
Resolution
24/fX (3.2 µs)
0
0
1
1
0
1
0
1
28/fX (51.2 µs)
216/fX (13.1 ms)
28/fXT (7.81 ms)
28/fX (51.2 µs)
1/fXT (30.5 µs)
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fXT: Subsystem clock oscillation frequency
Table 6-5. Interval Time of 8-Bit Timer 81 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)
TCL811
TCL810
Minimum Interval Time
24/fCC (8.0 µs)
Maximum Interval Time
212/fCC (2.05 ms)
Resolution
24/fCC (8.0 µs)
0
0
1
1
0
1
0
1
28/fCC (128 µs)
216/fCC (32.8 ms)
28/fCC (128 µs)
1/fXT (30.5 µs)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Remarks 1. fCC: Main system clock oscillation frequency (RC oscillation)
2. fXT: Subsystem clock oscillation frequency
Table 6-6. Interval Time of 8-Bit Timer 82 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation)
TCL821
TCL820
Minimum Interval Time
23/fX (1.6 µs)
Maximum Interval Time
211/fX (410 µs)
Resolution
23/fX (1.6 µs)
0
0
1
1
0
1
0
1
210/fX (205 µs)
218/fX (52.4 ms)
28/fXT (7.81 ms)
210/fX (205 µs)
1/fXT (30.5 µs)
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fXT: Subsystem clock oscillation frequency
Table 6-7. Interval Time of 8-Bit Timer 82 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)
TCL821
TCL820
Minimum Interval Time
23/fCC (4.0 µs)
Maximum Interval Time
211/fCC (1.02 ms)
Resolution
23/fCC (4.0 µs)
0
0
1
1
0
1
0
1
210/fCC (512 µs)
218/fCC (131 ms)
210/fCC (512 µs)
1/fXT (30.5 µs)
28/fXT (7.81 ms)
1/fXT (30.5 µs)
Remarks 1. fCC: Main system clock oscillation frequency (RC oscillation)
2. fXT: Subsystem clock oscillation frequency
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
Figure 6-8. Interval Timer Operation Timing of TM80 and TM81
t
Count clock
TM8n count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR8n
N
N
N
N
TCE8n
Count starts
INTTM8n
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
Interval time
Remarks 1. Interval time = (N + 1) × t where N = 00H to FFH
2. n = 0, 1
Figure 6-9. Interval Timer Operation Timing of TM82
t
Count clock
TM82 count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR82
N
N
N
N
TCE82
Count start
INTTM82
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
TO82
Interval time
Remark Interval time = (N + 1) × t where N = 00H to FFH
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.4.2 Operation as external event counter (timer 80 only)
The external event counter counts the number of external clock pulses input to the TI80/P23/INTP0 pin by using 8-
bit timer counter 80 (TM80).
To operate 8-bit timer/event counter 80 as an external event counter, make the settings in the following order.
<1> Set P23 to input mode (PM23 = 1)
<2> Set 8-bit timer counter 80 (TM80) to operation-disabled (TCE80 (bit 7 of 8-bit timer mode control register 80
(TMC80)) = 0)
<3> Specify the rising edge/falling edge of TI80 (see Figure 6-4)
<4> Set the count value to CR80
<5> Set TM80 to operation-enabled (TCE80 = 1)
Each time the valid edge specified by bit 1 (TCL800) of TMC80 is input, the value of 8-bit timer counter 80 (TM80)
is incremented.
When the count value of TM80 matches the value set to CR80, the value of TM80 is cleared to 00H and TM80
continues counting. At the same time, an interrupt request signal (INTTM80) is generated.
Figure 6-10 shows the timing of external event counter operation (with rising edge specified).
Caution When the setting of the count clock with TMC80 and the setting of TM80 to operation-enable with
an 8-bit memory manipulation instruction are performed at the same time, an error of one clock
or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit
timer/event counter operates as an external event counter, be sure to make the settings in the
order described above.
Figure 6-10. External Event Counter Operation Timing (with Rising Edge Specified)
TI80 pin input
TM80 count value
CR80
00
01
02
03
04
05
N
N – 1
N
00
01
02
03
TCE80
INTTM80
Remark N = 00H to FFH
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.4.3 Operation as square wave output (timer 82 only)
The 8-bit timer/event counter can generate the output square waves of any frequency at intervals specified by the
count value set to 8-bit compare register 82 (CR82) in advance.
To operate 8-bit timer 82 as square wave output, make the settings in the following order.
<1> Set P25 to output mode (PM25 = 0), and clear the output latch of P25 to 0
<2> Set 8-bit timer counter 82 (TM82) to operation-disabled (TCE82 (bit 7 of 8-bit timer mode control register 82
(TMC82)) = 0)
<3> Set the count clock of 8-bit timer 82 (see Tables 6-8 and 6-9), and set TO82 to output-enabled (TOE82 (bit 0
of TMC82) = 1)
<4> Set the count value to CR82
<5> Set TM82 to operation-enabled (TCE82 = 1)
When the count value of 8-bit timer counter 82 (TM82) matches the value set in CR82, the TO82/P25 pin output
will be inverted, respectively. Through application of this mechanism, square waves of any frequency can be output.
As soon as a match occurred, the TM82 value will be cleared to 00H then resume to count, generating an interrupt
request signal (INTTM82).
Setting 0 to bit 7 in TMC82, that is, TCE82 makes the square-wave output clear to 0.
Tables 6-8 and 6-9 list square wave output range, and Figure 6-11 shows timing of square wave output.
Caution When the setting of the count clock with TMC82 and the setting of TM82 to operation-enable with
an 8-bit memory manipulation instruction are performed at the same time, an error of one clock
or more may occur in the first cycle after the timer is started. Because of this, when the 8-bit
timer/event counter operates as a square-wave output, be sure to make the settings in the order
described above.
Table 6-8. Square Wave Output Range of 8-Bit Timer 82 (at fX = 5.0 MHz and fXT = 32.768 kHz Operation)
TCL821
TCL820
Minimum Pulse Width
23/fX (1.6 µs)
Maximum Pulse Width
211/fX (409 µs)
Resolution
23/fX (1.6 µs)
0
0
1
1
0
1
0
1
210/fX (205 µs)
218/fX (52.4 ms)
28/fXT (7.81 ms)
210/fX (205 µs)
1/fXT (30.5 µs)
1/fXT (30.5 µs)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fXT: Subsystem clock oscillation frequency
Table 6-9. Square Wave Output Range of 8-Bit Timer 82 (at fCC = 2.0 MHz and fXT = 32.768 kHz Operation)
TCL821
TCL820
Minimum Pulse Width
23/fCC (4.0 µs)
Maximum Pulse Width
211/fCC (1.02 ms)
Resolution
23/fCC (4.0 µs)
0
0
1
1
0
1
0
1
210/fCC (512 µs)
218/fCC (131 ms)
28/fXT (7.81 ms)
210/fCC (512 µs)
1/fXT (30.5 µs)
1/fXT (30.5 µs)
Remarks 1. fCC: Main system clock oscillation frequency (RC oscillation)
2. fXT: Subsystem clock oscillation frequency
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
Figure 6-11. Square Wave Output Timing
Count clock
TM82 count value
00
01
N
00
01
N
00
01
N
Clear
Clear
CR82
N
N
N
N
TCE82
Count start
INTTM82
Interrupt acknowledged
Interrupt acknowledged
TO82Note
Note The initial value of TO82 at output enable (TOE82 = 1) becomes low-level.
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
6.5 Cautions Related to 8-Bit Timer/Event Counters 80 to 82
(1) Error on starting timer
An error of up to 1.5 clock cycles may occur from the start of the timer until the match signal is generated.
This is because, if the timer starts while the count clock is at high level, the rising edge may be immediately
detected, and the counter may be incremented (see Figure 6-12).
Figure 6-12. Case in Which (Maximum) 1.5 Clock Cycle Error Occurs
Delay A
Count
pulse
Select clock
TCE8n
8-bit timer
counter 8n (TM8n)
Clear signal
Delay B
Select clock
TCE8n
Clear signal
Count pulse
...
TM8n count value
00H
01H
02H
03H
Delay A
Delay B
Error of up to 1.5 clock cycles occurs if the timer is started while
the selected clock is at high level and if delay A > delay B.
Remark n = 0 to 2
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
(2) Count value if external clock from TI80 pin is selected
If the timer is enabled to operate (TCE80 = 0 → 1) while the TI80 pin is at high level when the rising edge of
the external signal input from the TI80 pin is selected as the count clock, the count value may start from 01H.
This is because the input signal from the TI80 pin and TCE80 signal are internally ANDed, and the rising
edge is input to the timer immediately after TCE80 is set and the counter is incremented. If the rising edge is
input, depending on the timing of delay, after the counter is cleared, the count value is incremented by +1.
Conversely, the count value is not affected (the operation is normal) if the rising edge is input before the
counter is cleared.
For the same reason, the count value may start from 01H if the timer is enabled to operate (TCE80 = 0 → 1)
while the TI80 pin is at low level when the falling edge of the external signal input from the TI80 pin is
selected as the count clock.
Use the timer taking into consideration that the count value has an error of 1 count, or take either of the
following remedial actions A or B.
<Remedy A> Be sure to start the timer while the TI80 pin is at low level when the rising edge is selected.
Be sure to start the timer while the TI80 pin is at high level when the falling edge is selected.
<Remedy B> Save the count value when the timer is started to a control register and, when reading the
count value, subtract the count value saved to the control register from the count value, and
take the difference as the true count value.
Figure 6-13. Count Operation When Timer Is Started While TI80 at High Level (with Rising Edge Selected)
Clear
Increment
TCE8n flag
Rising edge
Counter
detector
TI8n
H
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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 80 TO 82
(3) Setting of 8-bit compare register
8-bit compare registers 80, 81, and 82 (CR80, CR81, and CR82) can be cleared to 00H.
Therefore, one pulse can be counted when timer 80 operates as an event counter.
Figure 6-14. External Event Counter Operation Timing
TI80 input
CR80
TM80 count value
00H
00H
00H
00H
00H
Interrupt request flag
Caution When rewriting CR8n, be sure to stop the timer operation beforehand. If CR8n is rewritten
in the timer operation-enabled state, a match interrupt request signal may occur at the
moment of rewrite.
(4) Notes on STOP mode setting
Before executing the STOP instruction, be sure to stop the timer operation (TCE8n = 0).
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CHAPTER 7 8-BIT TIMERS 30, 40
7.1 8-Bit Timers 30, 40 Functions
The 8-bit timers in the µPD789835, 789835A, 789835B Subseries have 2 channels (timer 30 and timer 40). The
operation modes listed in the following table can be set via mode register settings.
Table 7-1. Operation Modes
Channel
Timer 30
Timer 40
Available
Mode
8-bit timer counter mode
(Discrete mode)
Available
16-bit timer counter mode
(Cascade connection mode)
Available
Available
Carrier generator mode
PWM output mode
Not available
Available
(1) 8-bit timer counter mode (discrete mode)
The following functions can be used in this mode.
• Interval timer with 8-bit resolution
• Square wave output with 8-bit resolution (timer 40 only)
(2) 16-bit timer counter mode (cascade connection mode)
Operation as a 16-bit timer is enabled during cascade connection mode.
The following functions can be used in this mode.
• Interval timer with 16-bit resolution
• Square wave output with 16-bit resolution
(3) Carrier generator mode
The carrier clock generated by timer 40 is output in cycles set by timer 30.
(4) PWM output mode (timer 40 only)
Pulses are output using any duty factor set by timer 40.
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CHAPTER 7 8-BIT TIMERS 30, 40
7.2 8-Bit Timers 30, 40 Configuration
8-bit timers 30 and 40 include the following hardware.
Table 7-2. Configuration of 8-Bit Timers 30, 40
Item
Timer counters
Configuration
8 bits × 2 (TM30, TM40)
Registers
Compare registers: 8 bits × 3 (CR30, CR40, CRH40)
Timer output
Control registers
1 (TO40)
8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 2 (PM2)
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Figure 7-1. Block Diagram of Timer 30
Internal bus
8-bit timer mode control register 30
(TMC30)
TCE30 TCL301 TCL300 TMD300
2
8-bit compare register 30
(CR30)
Decoder
Selector
To Figure 7-2 (G)
Timer 30 match signal
(in carrier generator mode)
(G)
Match
(A)
Bit 7 of TM40
(from Figure 7-2 (A))
OVF
8-bit timer counter 30
(TM30)
f
f
CLK/26
CLK/28
Clear
Timer 40 interrupt request signal
(B)
(C)
(from Figure 7-2 (B))
Carrier clock
(from Figure 7-2 (C))
Internal reset signal
(D)
Selector
From Figure 7-2 (D)
Count operation start signal
(for cascade connection)
Cascade connection mode
INTTM30
(E)
From Figure 7-2 (E)
Timer 40 match signal
(in cascade connection mode)
(F)
To Figure 7-2 (F)
Timer 30 match signal
(in cascade connection mode)
Remark fCLK: fX or fCC
Figure 7-2. Block Diagram of Timer 40
Internal bus
Carrier generator output
control register 40 (TCA40)
8-bit timer mode control
register 40 (TMC40)
8-bit compare
register 40 (CR40)
8-bit H width compare
register 40 (CRH40)
RMC40 NRZB40 NRZ40
TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
2
From Figure 7-1 (G)
Timer counter match signal from timer 30
(in carrier generator mode)
Selector
(G)
Decoder
Output controllerNote
TO40/P27
F/F
Match
3
To Figure 7-1 (C)
Carrier clock
8-bit timer counter 40
(TM40)
f
CLK
(C)
f
CLK/22
OVF
Clear
f
CLK/22
CLK/23
CLK/24
Carrier generator mode
PWM mode
f
To Figure 7-1 (A)
Bit 7 of TM40
(in cascade connection mode)
Reset
f
(A)
Cascade connection mode
Internal reset signal
INTTM40
(D)
To Figure 7-1 (D)
Count operation start signal to timer 30
(in cascade connection mode)
To Figure 7-1 (B)
Timer 40 interrupt request signal
Count clock input
signal to TM30
(E)
To Figure 7-1 (E)
(B)
TM40 timer counter match signal
(in cascade connection mode)
(F)
From Figure 7-1 (F)
TM30 match signal
(in cascade connection mode)
Note See Figure 7-3 for details.
Remark fCLK: fX or fCC
CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-3. Block Diagram of Output Controller (Timer 40)
RMC40
TOE40
NRZ40
P27
output latch
PM27
TO40/P27
F/F
Carrier clock
Carrier generator mode
(1) 8-bit compare register 30 (CR30)
This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer
counter 30 (TM30) and to generate an interrupt request (INTTM30) when a match occurs.
CR30 is set with an 8-bit memory manipulation instruction.
RESET input makes CR30 undefined.
Caution CR30 cannot be used in PWM output mode.
(2) 8-bit compare register 40 (CR40)
This 8-bit register is used to continually compare the value set to CR40 with the count value in 8-bit timer
counter 40 (TM40) and to generate an interrupt request (INTTM40) when a match occurs. When connected
to TM30 via a cascade connection and used as a 16-bit timer, the interrupt request (INTTM40) occurs only
when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40 (INTTM30
does not occur).
During carrier generator mode or PWM output mode, the low-level width of timer output is set.
CR40 is set with an 8-bit memory manipulation instruction.
RESET input makes CR40 undefined.
(3) 8-bit H width compare register 40 (CRH40)
During carrier generator mode or PWM output mode, the high-level width of timer output is set by writing a
value to CRH40.
This register is used to continually compare the value set to CRH40 with the count value in TM40 and to
generate an interrupt request (INTTM40) when a match occurs.
CRH40 is set with an 8-bit memory manipulation instruction.
RESET input makes CRH40 undefined.
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CHAPTER 7 8-BIT TIMERS 30, 40
(4) 8-bit timer counters 30 and 40 (TM30 and TM40)
These are 8-bit registers that are used to count the count pulse.
TM30 and TM40 are read with an 8-bit memory manipulation instruction.
RESET input clears TM30 and TM40 to 00H.
TM30 and TM40 are cleared to 00H under the following conditions.
(a) Discrete mode
(i) TM30
•
•
•
•
After reset
When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0
When a match occurs between TM30 and CR30
When the TM30 count value overflows
(ii) TM40
•
•
•
•
After reset
When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0
When a match occurs between TM40 and CR40
When the TM40 count value overflows
(b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H)
•
•
•
•
After reset
When the TCE40 flag is cleared to 0
When matches occur simultaneously between TM30 and CR30 and between TM40 and CR40
When the TM30 and TM40 count values overflow simultaneously
(c) Carrier generator mode/PWM output mode (TM40 only)
•
•
•
•
•
After reset
When the TCE40 flag is cleared to 0
When a match occurs between TM40 and CR40
When a match occurs between TM40 and CRH40
When the TM40 count value overflows
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CHAPTER 7 8-BIT TIMERS 30, 40
7.3 Registers Controlling 8-Bit Timers 30, 40
8-bit timers 30 and 40 are controlled by the following four registers.
• 8-bit timer mode control register 30 (TMC30)
• 8-bit timer mode control register 40 (TMC40)
• Carrier generator output control register 40 (TCA40)
• Port mode register 2 (PM2)
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CHAPTER 7 8-BIT TIMERS 30, 40
(1) 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the
operation mode setting.
TMC30 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC30 to 00H.
Figure 7-4. Format of 8-Bit Timer Mode Control Register 30
Symbol
<7>
6
0
5
0
4
3
2
0
1
0
0
Address After reset
FF62H 00H
R/W
R/W
TMC30 TCE30
TCL301 TCL300
TMD300
TCE30
Control of TM30 count operationNote 1
0
1
Clears TM30 count value and stops operation
Starts count operation
TCL301 TCL300
Selection of timer 30 count clock
@fX = 5.0 MHz operation @fCC = 2.0 MHz operation
fX/26 (78.1 kHz)
0
0
1
1
0
1
0
1
fCC/26 (31.3 kHz)
fCC/28 (7.81 kHz)
fX/28 (19.5 kHz)
Timer 40 match signal
Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator
mode)
TMD300 TMD401 TMD400
Selection of operation mode for timer 30 and timer 40Note 2
8-bit timer counter mode (discrete mode)
0
1
0
0
0
0
1
1
0
1
1
0
16-bit timer counter mode (cascade connection mode)
Carrier generator mode
Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above
Setting prohibited
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode,
any setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count
clock.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 7 8-BIT TIMERS 30, 40
(2) 8-bit timer mode control register 40 (TMC40)
8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the
operation mode setting.
TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC40 to 00H.
Figure 7-5. Format of 8-Bit Timer Mode Control Register 40
Symbol
<7>
6
0
5
4
3
2
1
<0>
Address After reset
FF69H 00H
R/W
R/W
TMC40 TCE40
TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
TCE40
0
Control of TM40 count operationNote 1
Clears TM40 count value and stops operation (the count value is also cleared for TM30 during cascade
connection mode)
1
Starts count operation (the count operation is also started for TM30 during cascade connection mode)
TCL402 TCL401 TCL400
Selection of timer 40 count clock
@fX = 5.0 MHz operation @fCC = 2.0 MHz operation
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
fX (5.0 MHz)
fCC (2.0 MHz)
fX/22 (1.25 MHz)
fX/2 (2.5 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
Setting prohibited
fCC/22 (500 kHz)
fCC/2 (1.0 MHz)
fCC/22 (500 kHz)
fCC/23 (250 kHz)
fCC/24 (125 kHz)
Other than above
TMD300 TMD401 TMD400
Selection of operation mode for timer 30 and timer 40Note 2
8-bit timer counter mode (discrete mode)
0
1
0
0
0
0
1
1
0
1
1
0
16-bit timer counter mode (cascade connection mode)
Carrier generator mode
Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above
Setting prohibited
TOE40
Control of timer output
0
1
Output disabled (port mode)
Output enabled
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode,
any setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 7 8-BIT TIMERS 30, 40
(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data during carrier generator mode.
TCA40 is set with an 8-bit memory manipulation instruction.
RESET input makes TCA40 undefined.
Figure 7-6. Format of Carrier Generator Output Control Register 40
Symbol
TCA40
7
0
6
0
5
0
4
0
3
0
2
1
0
Address
FF67H
After reset R/W
Undefined
RMC40 NRZB40 NRZ40
W
RMC40
Control of remote control output
0
1
When NRZ40 = 1, a carrier pulse is output to TO40/P27 pin
When NRZ40 = 1, high-level signal is output to TO40/P27 pin
NRZB40 This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge
of the timer 30 match signal. Input the necessary value in NRZB40 in advance by program.
NRZ40
No return zero data
Outputs low-level signal (carrier clock is stopped)
Outputs carrier pulse or high-level signal
0
1
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-
bit memory manipulation instruction to set TCA40.
3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 =
0). The data cannot be overwritten when TOE40 = 1.
4. When enabling the carrier generator operation again after stopping it once, be sure to
set NRZB40 again because the previous value is not retained. In this case, also, a 1-bit
memory manipulation instruction cannot be used. Be sure to use an 8-bit memory
manipulation instruction.
5. To enable an operation in the carrier generator mode, set values to the compare
registers (CR30, CR40, and CRH40) in advance, and input the necessary values to the
NRZB40 and NRZ40 flags before starting the operation. Otherwise, the signal of the
timer match circuit will be undefined and the NRZ40 flag will be undefined.
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CHAPTER 7 8-BIT TIMERS 30, 40
(4) Port mode register 2 (PM2)
This register is used to set the I/O mode of port 2 in 1-bit units.
When using the P27/TO40 pin as a timer output, clear the PM27 and P27 output latch to 0.
PM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 7-7. Format of Port Mode Register 2
Symbol
PM2
7
6
5
4
3
2
1
0
Address
FF22H
After reset
FFH
R/W
R/W
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
PM2n
P2n pin I/O mode
(n = 0 to 7)
0
1
Output mode (output buffer is on)
Input mode (output buffer is off)
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CHAPTER 7 8-BIT TIMERS 30, 40
7.4 8-Bit Timers 30, 40 Operation
7.4.1 Operation as 8-bit timer counter
Timer 30 and timer 40 can independently be used as an 8-bit timer counter.
The following modes can be used for the 8-bit timer counter.
•
•
Interval timer with 8-bit resolution
Square wave output with 8-bit resolution (timer 40 only)
(1) Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register n0 (CRn0).
To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0).
<2> Disable timer output of REM (TOEn0 = 0).
<3> Set a count value in CRn0.
<4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 7-4 and 7-5).
<5> Set the count clock for timer n0 (see Tables 7-3 to 7-6).
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to
00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated.
Tables 7-3 to 7-6 show interval time, and Figures 7-8 to 7-13 show the timing of the interval timer operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark n = 3, 4
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CHAPTER 7 8-BIT TIMERS 30, 40
Table 7-3. Interval Time of Timer 30 (at fX = 5.0 MHz Operation)
TCL301
TCL300
Minimum Interval Time
26/fX (12.8 µs)
Maximum Interval Time
214/fX (3.28 ms)
Resolution
26/fX (12.8 µs)
0
0
1
0
1
0
28/fX (51.2 µs)
216/fX (13.1 ms)
28/fX (51.2 µs)
Input cycle of timer 40 match
signal
Input cycle of timer 40 match
signal × 28
Input cycle of timer 40 match
signal
1
1
Input cycle of timer 40 output
Input cycle of timer 40 output ×
Input cycle of timer 40 output
28
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 7-4. Interval Time of Timer 30 (at fCC = 2.0 MHz Operation)
TCL301
TCL300
Minimum Interval Time
Maximum Interval Time
214/fCC (8.19 ms)
Resolution
26/fCC (32 µs)
28/fCC (128 µs)
26/fCC (32 µs)
28/fCC (128 µs)
0
0
1
0
1
0
216/fCC (32.8 ms)
Input cycle of timer 40 match
signal
Input cycle of timer 40 match
signal × 28
Input cycle of timer 40 match
signal
1
1
Input cycle of timer 40 output
Input cycle of timer 40 output ×
Input cycle of timer 40 output
28
Remark fCC: Main system clock oscillation frequency (RC oscillation)
Table 7-5. Interval Time of Timer 40 (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fX (0.2 µs)
Maximum Interval Time
28/fX (51.2 µs)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
210/fX (205 µs)
28/fX (51.2 µs)
210/fX (205 µs)
211/fX (410 µs)
212/fX (819 µs)
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 7-6. Interval Time of Timer 40 (at fCC = 2.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fCC (0.5 µs)
Maximum Interval Time
Resolution
1/fCC (0.5 µs)
28/fCC (128 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
210/fCC (512 µs)
28/fCC (128 µs)
210/fCC (512 µs)
211/fCC (1.02 ms)
212/fCC (4.10 ms)
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
t
Count clock
TMn0
N
00H 01H
Clear
00H
01H
00H 01H
Clear
00H 01H
Clear
00H
N
N
N
CRn0
TCEn0
Count start
Count stop
INTTMn0
TO40
Interrupt acknowledgment
Interval time
Interrupt acknowledgment
Interval time
Interrupt acknowledgment
Remarks 1. Interval time = (N + 1) × t where N = 00H to FFH
2. n = 3, 4
Figure 7-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H)
Count clock
00H
00H
TMn0
CRn0
TCEn0
Count start
INTTMn0
TO40
Remark n = 3, 4
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
Count clock
01H
00H
01H
00H 01H
Clear
00H 01H
Clear
FFH
00H
FFH
FFH
TMn0
FFH
Clear
FFH
CRn0
TCEn0
Count start
INTTMn0
TO40
Remark n = 3, 4
Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N < M))
Count clock
TMn0
00H
N
N
M
00H
M
00H
01H
00H
01H
N
Clear
Clear
Clear
N
CRn0
M
TCEn0
Count start
INTTMn0
TO40
Interrupt acknowledgment
CRn0 overwritten
Interrupt acknowledgment
Remark n = 3, 4
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-12. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N > M))
Count clock
TMn0
N − 1
M
N
FFH
00H
M
M
00H
N
00H
00H
Clear
Clear
Clear
N
CRn0
M
H
TCEn0
TMn0 overflows
because M < N
INTTMn0
TO40
CRn0 overwritten
Remark n = 3, 4
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
Timer 40
count clock
M
M
M
00H
00H
01H
N
00H
00H
00H
M
TM40
Clear
Clear
Clear
Clear
N
CR40
TCE40
Count start
INTTM40
Input clock to timer 30
(timer 40 match signal)
Y
00H
00H
00H
01H
Y − 1
Y
TM30
CR30
Y
TCE30
INTTM30
TO40
Count start
Remark n = 3, 4
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CHAPTER 7 8-BIT TIMERS 30, 40
(2) Operation as square-wave output with 8-bit resolution (timer 40 only)
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register 40 (CR40).
To operate timer 40 for square-wave output, settings must be made in the following sequence.
<1> Set P27 to output mode (PM27 = 0).
<2> Clear the output latch of P27 to 0.
<3> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0).
<4> Set a count clock for timer 40 and enable output of TO40 (TOE40 = 1).
<5> Set a count value in CR40.
<6> Enable the operation of TM40 (TCE40 = 1).
When the count value of TM40 matches the value set in CR40, the TO40 pin output will be inverted. Through
application of this mechanism, square waves of any frequency can be output. As soon as a match occurs,
TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is
generated.
The square-wave output is cleared to 0 by setting TCE40 to 0.
Tables 7-7 and 7-8 show the square-wave output range, and Figure 7-14 shows the timing of square-wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 7-7. Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fX (0.2 µs)
Maximum Pulse Width
28/fX (51.2 µs)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
210/fX (205 µs)
28/fX (51.2 µs)
210/fX (205 µs)
211/fX (410 µs)
212/fX (819 µs)
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 7-8. Square-Wave Output Range of Timer 40 (at fCC = 2.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fCC (0.5 µs)
Maximum Pulse Width
Resolution
1/fCC (0.5 µs)
28/fCC (128 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
210/fCC (512 µs)
28/fCC (128 µs)
210/fCC (512 µs)
211/fCC (1.02 ms)
212/fCC (4.10 ms)
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-14. Timing of Square-Wave Output with 8-Bit Resolution
t
Count clock
TM40
N
00H 01H
Clear
01H
00H 01H
Clear
00H 01H
Clear
00H
N
N
N
CR40
TCE40
Count start
INTTM40
TO40Note
Interrupt acknowledgment
Interrupt acknowledgment
Interrupt acknowledgment
Square-wave output cycle
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark Square-wave output cycle = 2 (N + 1) × t where N = 00H to FFH
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CHAPTER 7 8-BIT TIMERS 30, 40
7.4.2 Operation as 16-bit timer counter
Timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer
counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls
reset and clear.
The following modes can be used for the 16-bit timer counter.
•
•
Interval timer with 16-bit resolution
Square-wave output with 16-bit resolution
(1) Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0,
TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set the count clock for timer 40 (see Tables 7-5 and 7-6).
<4> Set the operation mode of timer 30 and 8-bit timer 40 to 16-bit timer counter mode (see Figures 7-4
and 7-5).
<5> Set a count value in CR30 and CR40.
<6> Enable the operation of TM30 and TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and
TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal
(INTTM40) is generated (INTTM30 is not generated).
Tables 7-9 and 7-10 show interval time, and Figure 7-15 shows the timing of the interval timer operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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CHAPTER 7 8-BIT TIMERS 30, 40
Table 7-9. Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fX (0.2 µs)
Maximum Interval Time
216/fX (13.1 ms)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
218/fX (52.4 ms)
216/fX (13.1 ms)
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
218/fX (52.4 ms)
219/fX (105 ms)
220/fX (210 ms)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 7-10. Interval Time with 16-Bit Resolution (at fCC = 2.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Interval Time
1/fCC (0.5 µs)
Maximum Interval Time
216/fCC (32.8 ms)
218/fCC (131 ms)
Resolution
1/fCC (0.5 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
216/fCC (32.8 ms)
218/fCC (131 ms)
219/fCC (262 ms)
220/fCC (524 ms)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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Figure 7-15. Timing of Interval Timer Operation with 16-Bit Resolution
t
Count clock
TM40 count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM30 does not match
Cleared because TM30 and TM40 match simultaneously
CR40
N
N
N
N
N
N
N
N
TCE40
Count start
TM30 count pulse
X
X − 1
00H
X
TM30
CR30
00H
X
01H
00H
X − 1
X
X
INTTM40
TO40
Interrupt acknowledgment
Interrupt acknowledgment
Interrupt not generated because
TM30 does not match
Interval time
Remark Interval time = (256X + N + 1) × t where X = 00H to FFH, N = 00H to FFH
CHAPTER 7 8-BIT TIMERS 30, 40
(2) Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and
CR40.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable output of TO40 (TOE40 = 0).
<3> Set a count clock for timer 40.
<4> Set P27 to output mode (PM27 = 0) and clear P27 output latch to 0 and enable TO40 output (TOE40 =
1).
<5> Set count values in CR30 and CR40.
<6> Enable the operation of TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, the TO40 pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting
continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated).
The square-wave output is cleared to 0 by clearing TCE40 to 0.
Tables 7-11 and 7-12 show the square wave output range, and Figure 7-16 shows timing of square wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Table 7-11. Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fX (0.2 µs)
Maximum Pulse Width
216/fX (13.1 ms)
Resolution
1/fX (0.2 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
218/fX (52.4 ms)
216/fX (13.1 ms)
218/fX (52.4 ms)
219/fX (105 ms)
220/fX (210 ms)
22/fX (0.8 µs)
1/fX (0.2 µs)
22/fX (0.8 µs)
23/fX (1.6 µs)
24/fX (3.2 µs)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 7-12. Square-Wave Output Range with 16-Bit Resolution (at fCC = 2.0 MHz Operation)
TCL402 TCL401 TCL400
Minimum Pulse Width
1/fCC (0.5 µs)
Maximum Pulse Width
216/fCC (32.8 ms)
218/fCC (131 ms)
Resolution
1/fCC (0.5 µs)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
22/fCC (2.0 µs)
1/fCC (0.5 µs)
22/fCC (2.0 µs)
23/fCC (4.0 µs)
24/fCC (8.0 µs)
216/fCC (32.8 ms)
218/fCC (131 ms)
219/fCC (262 ms)
220/fCC (524 ms)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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Figure 7-16. Timing of Square-Wave Output with 16-Bit Resolution
t
Count clock
TM40 count value
00H
N
N
7FH 80H
FFH 00H
N
7FH 80H
FFH 00H
00H
7FH 80H
FFH 00H
N
N
00H
Not cleared because TM30 does not match
Cleared because TM30 and TM40 match simultaneously
CR40
N
N
N
N
N
N
N
N
TCE40
Count start
TM30 count pulse
X
X − 1
00H
X
TM30
CR30
00H
X
01H
00H
X − 1
X
X
INTTM40
TO40Note
Interrupt acknowledgment
Interrupt not generated because
TM30 does not match
Interrupt acknowledgment
Square-wave output cycle/2
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark Square-wave output cycle = 2 (256X + N + 1) × t where X = 00H to FFH, N = 00H to FFH
CHAPTER 7 8-BIT TIMERS 30, 40
7.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30.
To operate timer 30 and timer 40 as carrier generators, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR30, CR40, and CRH40.
<4> Set the operation mode of timer 30 and timer 40 to carrier generator mode (see Figures 7-4 and 7-5).
<5> Set the count clock for timer 30 and timer 40.
<6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40
(TCA40)) = 0).
Input the required value to NRZB40 (bit 1 of TCA40) by program.
Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40.
<7> Set P27 to output mode (PM27 = 0) and clear the P27 output latch to 0 and enable TO40 output by setting
TOE40 to 1.
<8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1).
<9> Save the value of NRZB40 to a general-purpose register.
<10> If INTTM30 rises, the value of NRZB40 is transferred to NRZ40. After that, rewrite TCA40 by using an 8-bit
memory manipulation instruction. Input the value to be transferred to NRZ40 next to NRZB40, and input the
value saved in <9> above to NRZ40.
<11> By repeating <9> and <10>, generate the desired carrier signal.
The operation of the carrier generator is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is
generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40.
<5> When NRZ40 is 1, a carrier clock is output from TO40 pin.
Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction.
2. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 = 0).
The data cannot be overwritten when TOE40 = 1.
3. When enabling the carrier generator operation again after stopping it once, be sure to set
NRZB40 again because the previous value is not retained. In this case, also, a 1-bit
memory manipulation instruction cannot be used. Be sure to use an 8-bit memory
manipulation instruction.
4. To enable an operation in the carrier generator mode, set values to the compare registers
(CR30, CR40, and CRH40) in advance, and input the necessary values to the NRZB40 and
NRZ40 flags before starting the operation. Otherwise, the signal of the timer match circuit
will be undefined and the NRZ40 flag will be undefined.
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CHAPTER 7 8-BIT TIMERS 30, 40
Figures 7-17 to 7-19 show the operation timing of the carrier generator.
Figure 7-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
TM40
count clock
TM40
count value
...
...
...
...
...
...
00H
01H
N
00H
N
M
N
00H
00H
00H
N
M
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
Carrier
clock
TM30
count clock
...
...
...
...
X
00H
X
X
01H
00H
01H
X
00H
00H
TM30
CR30
01H
00H 01H
X
TCE30
INTTM30
0
1
0
1
0
NRZB40
NRZ40
0
1
0
1
0
Carrier
clock
TO40
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
TM40
count clock
TM40
count value
...
...
...
...
...
...
...
00H
M
N
00H
M
00H
M
N
00H
M
00H
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
Carrier
clock
TM30
count clock
...
...
...
...
00H
X
X
00H
01H
01H
X
01H
00H
00H
X
00H 01H
TM30
CR30
X
TCE30
INTTM30
0
0
1
0
NRZB40
NRZ40
1
1
0
0
1
0
Carrier
clock
TO40
Remark This figure shows an example where the value of NRZ40 is changed when the carrier clock is at a high
level.
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
TM40
count clock
TM40
count value
...
...
...
...
...
...
00H
N
00H
N
N
N
00H
00H
00H
00H
N
N
Clear
Clear
Clear
Clear
Clear
CR40
N
N
CRH40
TCE40
Count start
INTTM40
Carrier
clock
TM30
count clock
...
...
...
...
X
00H
X
X
01H
00H
01H
X
00H
00H
TM30
CR30
01H
00H 01H
X
TCE30
INTTM30
0
0
1
0
NRZB40
NRZ40
1
1
0
0
1
0
Carrier
clock
TO40
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CHAPTER 7 8-BIT TIMERS 30, 40
7.4.4 Operation as PWM output (timer 40 only)
In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a
high-level width using CRH40.
To operate timer 40 in PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM40 (TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR40 and CRH40.
<4> Set the operation mode of timer 40 to carrier generator mode (see Figure 7-5).
<5> Set the count clock for timer 40.
<6> Set P27 to output mode (PM27 = 0) and clear the P27 output latch to 0 and enable timer output of TO40
(TOE40 = 1).
<7> Enable the operation of TM40 (TCE40 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to
CRH40.
<2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again.
<3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 7-20 and 7-21 show the operation
timing in the PWM output mode.
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CHAPTER 7 8-BIT TIMERS 30, 40
Figure 7-20. PWM Output Mode Timing (Basic Operation)
Count clock
TM40
count value
01H
M
00H
M
00H
N
01H
00H
N
01H
00H
00H
01H
Clear
Clear
Clear
Clear
CR40
N
CRH40
TCE40
M
Count start
INTTM40
TO40Note
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Figure 7-21. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)
Count clock
TM40
count value
N
00H
N
00H
01H
Y
00H
X
M
00H
Clear
00H
X
Clear
Clear
Clear
CR40
N
X
CRH40
TCE40
M
Y
M
Count start
INTTM40
TO40Note
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
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CHAPTER 7 8-BIT TIMERS 30, 40
7.5 Notes on Using 8-Bit Timers 30, 40
(1) Error on starting timer
An error of up to 1.5 clock cycles may occur from the start of the timer until the match signal is generated.
This is because, if the timer starts while the count clock is at high level, the rising edge may be immediately
detected, and the counter may be incremented (see Figure 7-22).
Figure 7-22. Case in Which (Maximum) 1.5 Clock Cycle Error Occurs
Delay A
Count
pulse
8-bit timer counter n0
(TMn0)
Select clock
TCEn0
Clear signal
Delay B
Select clock
TCEn0
Clear signal
Count pulse
...
TMn0 count value
00H
01H
02H
03H
Delay A
Delay B
Error of up to 1.5 clock cycles occurs if the timer is started while
the selected clock is at high level and if delay A > delay B.
Remark n = 3, 4
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CHAPTER 8 8-BIT REMOTE CONTROL TIMER 50
8.1 8-Bit Remote Control Timer 50 Functions
8-bit remote control timer 50 has a pulse width measurement function with a resolution of 8 bits.
Pulse width is measured from a difference in count value when the valid edge has been detected while the timer
operates in the free-running mode.
8.2 8-Bit Remote Control Timer 50 Configuration
8-bit remote control timer 50 includes the following hardware.
Table 8-1. Configuration of 8-Bit Remote Control Timer 50
Item
Timer counter
Register
Configuration
8 bits × 1
Remote control timer capture register: × 2 (CP50 and CP51)
Control register
Remote control timer control register 50 (TMC50)
Figure 8-1. Block Diagram of 8-Bit Remote Control Timer 50
Internal bus
INTTM50
Remote control timer
capture register 50
(CP50)
Noise rejection
Rising edge
detection
RIN/P26
fCLK
f
f
f
CLK/27
CLK/28
CLK/29
8-bit timer counter 50
(TM50)
1/2
INTTM52
INTTM51
Clear
2
Remote control timer
capture register 51
(CP51)
Noise rejection
Falling edge
detection
TCE50 TCL52 TCL51
Remote control timer
control register 50 (TMC50)
Internal bus
Remark fCLK: fX or fCC
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CHAPTER 8 8-BIT REMOTE CONTROL TIMER 50
(1) Remote control timer capture registers (CP50 and CP51)
These 8-bit registers capture the contents of 8-bit timer counter 50 (TM50).
The capture operation is performed in synchronization with the valid edge input to the RIN pin (capture
trigger). The contents of CP50 are retained until the next rising edge of the RIN pin is detected. The
contents of CP51 are retained until the next falling edge of the RIN pin is detected.
CP50 and CP51 are read with an 8-bit memory manipulation instruction.
RESET input clears CP50 and CP51 to 00H.
(2) 8-bit timer counter 50 (TM50)
This 8-bit register counts the count pulse.
RESET input or clearing the TCE50 bit clears TM50 to 00H.
8.3 Registers Controlling 8-Bit Remote Control Timer 50
The following register controls the 8-bit remote control timer.
(1) Remote control timer control register 50 (TMC50)
This register enables or disables the operation of 8-bit timer counter 50 (TM50), and sets the count clock.
TMC50 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC50 to 00H.
Figure 8-2. Format of Remote Control Timer Control Register 50
Symbol
<7>
6
0
5
0
4
0
3
0
2
0
1
0
Address
FF54H
After reset
00H
R/W
R/W
TMC50 TCE50
TCL501 TCL500
TCE50
TM50 count operation control
0
1
Clears counter to 0 and stops operation
Starts count operation
TCL501 TCL500
TM50 count clock selection
@fX = 5.0 MHz operation @fCC = 2.0 MHz operation
0
0
1
1
0
1
0
1
fX/210 (4.88 kHz)
fX/29 (9.77 kHz)
fX/28 (19.5 kHz)
fX/2 (2.5 MHz)
fCC/210 (1.95 kHz)
fCC/29 (3.91 kHz)
fCC/28 (7.81 kHz)
fCC/2 (1.0 MHz)
Cautions 1. Be sure to clear bits 2 to 6 to 0.
2. Be sure to stop the timer operation (TCE50 = 0) before changing the count clock.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 8 8-BIT REMOTE CONTROL TIMER 50
8.4 Operation of 8-Bit Remote Control Timer 50
8-bit remote control timer 50 operates as a pulse width measuring circuit.
The width of a high-level or low-level external pulse input to the RIN pin is measured by operating 8-bit timer
counter 50 (TM50) in the free-running mode.
Noise with short pulse width can be detected since the detection of the valid edge is sampled every 2 cycles of the
count clock selected by TCL500 and TCL501, and the capture operation is not performed until the valid level has been
detected two times. Therefore, the pulse width input to the RIN pin must be 5 or more of the count clock set by
TCL500 and TCL501, regardless of whether the level is high or low. If the pulse width is less than 5 clocks, the valid
edge cannot be detected, and the capture operation is not performed.
The value of timer counter 50 (TM50) being counted is loaded to and retained in the capture registers (CP50 and
CP51) in synchronization with the valid edge of the pulse input to the RIN pin, as shown in Figure 8-3.
Figure 8-3 shows the timing of pulse width measurement.
Figure 8-3. Pulse Width Measurement Timing (1/2)
(1) To measure pulse width in synchronization with rising edge
FFH
FFH
Count value
of TM50
D3
D1
D2
D0
0H
Capture
Capture
Capture
Capture
Count starts
TCE50 = 1
RIN
INTTM50
CP50
00H
D0
t0
D1
D2
D3
INTTM52
t1
Remark t0 = (D1 − D0) × 1/fCOUNT
t1 = (100H − D1 + D2) × 1/fCOUNT
fCOUNT: Count clock frequency set by TCL500 and TCL501
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CHAPTER 8 8-BIT REMOTE CONTROL TIMER 50
Figure 8-3. Pulse Width Measurement Timing (2/2)
(2) Measure pulse width in synchronization with both rising and falling edges
FFH
FFH
Count value
of TM50
D2
D3
D1
D0
0H
Capture Capture Capture
Capture
Count starts
TCE50 = 1
RIN
INTTM50
INTTM51
CP50
00H
00H
D0
D2
CP51
D1
D3
INTTM52
t0
t1
Remark t0 = (D2 − D1) × 1/fCOUNT
t1 = (100H − D2 + D3) × 1/fCOUNT
fCOUNT: Count clock frequency set by TCL500 and TCL501
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CHAPTER 9 SOUND GENERATOR
9.1 Functions of Sound Generator
An interrupt is generated when the value of the compare register matches the value of the timer/counter, and
outputting the carrier clock of the frequency selected at that time is turned ON/OFF. By connecting a buzzer element
to the pin set as a buzzer output pin, the buzzer can therefore be sounded at any frequency.
• Volume: 10 steps
• Scale: 3 octaves (see Figure 9-4)
9.2 Configuration of Sound Generator
Table 9-1. Configuration of Sound Generator
Item
Timer counter
Configuration
8 bits × 1 (TMSG0)
Register
Compare register: 8 bits × 1 (CRSG0)
Control registers
Sound generator frequency setting register 00 (SGFC00)
Carrier generator output control register SG0 (TCASG0)
8-bit timer mode control register SG0 (TMCSG0)
P3 function register (PF3)
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User’s Manual U15559EJ2V1UD
Figure 9-1. Block Diagram of Sound Generator (1/2)
Internal bus
8-bit compare
register SG0 (CRSG0)
Match
Clear
INTTMSG0
(A)
f
CLK/27
fSG
7-bit counter
Output
controller
fXT
Comparator
To (B) in Figure 9-1
Block Diagram of
Sound Generator (2/2)
8-bit timer
counter SG0 (TMSG0)
f
CLK/213
CLK/214
CLK/215
7
f
Clear
f
Selector
2
TPS000
MDL005 MDL004 MDL003 MDL002
RMCSG0
NRZBSG0 NRZSG0
MDL006
MDL001 MDL000
TCESG0 TCLSG01
TCLSG00
Sound generator frequency
setting register 00 (SGFC00)
8-bit timer mode control
register SG0 (TMCSG0)
Carrier generator output
control register SG0 (TCASG0)
Internal bus
Remark fCLK: fX or fCC
Figure 9-1. Block Diagram of Sound Generator (2/2)
Internal bus
P3 function register (PF3)
OE1 OE0 OM2 OM1
SG0/P30
OE3
OE2
OM0
(R30)
SG1/P31
(R31)
SG2/P32
(R32)
SG3/P33
(R33)
(B)
(
(
+
)
From (A) in Figure 9-1 Block
Diagram of Sound Generator (1/2)
-
)
SG4/P34
(R34)
SG5/P35
R30 = R34 = R
R31 = R35 = 2R
R32 = R36 = 4R
R33 = R37 = 8R
3
(R35)
SG6/P36
(R36)
SG7/P37
(R37)
CHAPTER 9 SOUND GENERATOR
(1) 8-bit compare register SG0 (CRSG0)
This 8-bit register is used to continually compare the value set to the CRSG0 with the count value in 8-bit
timer counter SG0 (TMSG0) and to issue an interrupt request (INTTMSG0) when a match occurs.
CRSG0 is set with an 8-bit memory manipulation instruction.
RESET input makes CRSG0 undefined.
(2) 8-bit timer counter SG0 (TMSG0)
This 8-bit register is used to count a count pulse.
TMSG0 is read with an 8-bit memory manipulation instruction.
RESET input clears TMSG0 to 00H.
9.3 Registers Controlling Sound Generator
The following four registers are used to control sound generator.
• 8-bit timer mode control register SG0 (TMCSG0)
• Carrier generator output control register SG0 (TCASG0)
• Sound generator frequency setting register 00 (SGFC00)
• P3 function register (PF3)
(1) 8-bit timer mode control register SG0 (TMCSG0)
This register enables/stops operation of 8-bit timer counter SG0 (TMSG0) and sets the count clock of
TMSG0.
TMCSG0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMCSG0 to 00H.
Figure 9-2. Format of 8-Bit Timer Mode Control Register SG0
Symbol
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address After reset
FF6BH 00H
R/W
R/W
TMCSG0 TCESG0
TCLSG01 TCLSG00
TCESG0
Control of TMSG0 count operation
0
1
TMSG0 count value cleared and operation stopped
Count operation started
TCLSG01 TCLSG00
Selection of TMSG0 count clock
@ fX = 5.0 MHz operation @ fCC = 2.0 MHz operation
fX/213 (610 Hz) fCC/213 (244 Hz)
0
0
1
1
0
1
0
1
fX/214 (305 Hz)
fCC/214 (122 Hz)
fCC/215 (61 Hz)
fX/215 (152 Hz)
Carrier clock specified by SGFC00
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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CHAPTER 9 SOUND GENERATOR
(2) Carrier generator output control register SG0 (TCASG0)
This register is used to set the carrier generator output data.
TCASG0 is set with an 8-bit memory manipulation instruction.
RESET input clears TCASG0 to 00H.
Figure 9-3. Format of Carrier Generator Output Control Register SG0
Symbol
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After reset
R/W
W
TCASG0
RMCSG0 NRZBSG0 NRZSG0 FF6CH
00H
RMCSG0 NRZSG0
Sound output control
Output data
0
0
1
1
0
1
0
1
Sound output enabled
Sound output disabled
Low-level output (carrier output stopped)
Carrier output set by SGFC00 register
Low-level output
High-level output
NRZBSG0 This is the bit that stores the next NRZSG0 data to be output. When a match signal occurs (for a match
between TMSG0 and CRSG0), the data is transferred to NRZSG0.
Caution Be sure to clear bits 3 to 7 to 0.
(3) Sound generator frequency setting register 00 (SGFC00)
This register is used to set a frequency for the sound generator.
SGFC00 is set with an 8-bit memory manipulation instruction.
RESET input clears SGFC00 to 00H.
Figure 9-4. Format of Sound Generator Frequency Setting Register 00 (1/5)
Symbol
7
6
5
4
3
2
1
0
Address After reset
00H
R/W
R/W
SGFC00 TPS000 MDL006 MDL005 MDL004 MDL003 MDL002 MDL001 MDL000 FF6DH
TPS000
Selection of 7-bit counter source clock (fSG)
@ fX = 5.0 MHz and fXT = 32.768 kHz operation
@ fCC = 2.0 MHz and fXT = 32.768 kHz operation
0
1
fXT (32.768 kHz)
fX/27 (39.1 kHz)
fCC/27 (15.6 kHz)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
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CHAPTER 9 SOUND GENERATOR
Figure 9-4. Format of Sound Generator Frequency Setting Register 00 (2/5)
MDL006 MDL005 MDL004 MDL003 MDL002 MDL001 MDL000
Setting of sound generator frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSG
(32.768 kHz)
(16.384 kHz)
(10.923 kHz)
(8.192 kHz)
fSG/2
fSG/3
fSG/4
fSG/5
(6.554 kHz)
fSG/6
(5.461 kHz)
fSG/7
(4.681 kHz)
fSG/8
(4.096 kHz)
fSG/9
(3.641 kHz)
fSG/10
fSG/11
fSG/12
fSG/13
fSG/14
fSG/15
fSG/16
fSG/17
fSG/18
fSG/19
fSG/20
fSG/21
fSG/22
fSG/23
fSG/24
fSG/25
fSG/26
fSG/27
fSG/28
fSG/29
fSG/30
fSG/31
fSG/32
(3.277 kHz)
(2.979 kHz)
(2.731 kHz)
(2.521 kHz)
(2.341 kHz)
(2.185 kHz)
(2.048 kHz) (do)
(1.928 kHz) (si)
(1.820 kHz)
(1.725 kHz) (la)
(1.638 kHz)
(1.560 kHz) (so)
(1.489 kHz)
(1.425 kHz)
(1.365 kHz) (fa)
(1.311 kHz) (mi)
(1.260 kHz)
(1.214 kHz)
(1.170 kHz) (re)
(1.130 kHz)
(1.092 kHz)
(1.057 kHz) (do)
(1.024 kHz)
Remarks 1. fSG: Source clock frequency of 7-bit counter
2. Values in parentheses apply to the case when fSG = fXT (32.768 kHz) is selected.
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CHAPTER 9 SOUND GENERATOR
Figure 9-4. Format of Sound Generator Frequency Setting Register 00 (3/5)
MDL006 MDL005 MDL004 MDL003 MDL002 MDL001 MDL000
Setting of sound generator frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSG/33
fSG/34
fSG/35
fSG/36
fSG/37
fSG/38
fSG/39
fSG/40
fSG/41
fSG/42
fSG/43
fSG/44
fSG/45
fSG/46
fSG/47
fSG/48
fSG/49
fSG/50
fSG/51
fSG/52
fSG/53
fSG/54
fSG/55
fSG/56
fSG/57
fSG/58
fSG/59
fSG/60
fSG/61
fSG/62
fSG/63
fSG/64
(993 Hz)
(964 Hz)
(936 Hz)
(910 Hz)
(886 Hz)
(862 Hz)
(840 Hz)
(819 Hz)
(799 Hz)
(780 Hz)
(762 Hz)
(745 Hz)
(728 Hz)
(712 Hz)
(697 Hz)
(683 Hz)
(669 Hz)
(655 Hz)
(643 Hz)
(630 Hz)
(618 Hz)
(607 Hz)
(596 Hz)
(585 Hz)
(575 Hz)
(565 Hz)
(555 Hz)
(546 Hz)
(537 Hz)
(529 Hz)
(520 Hz)
(512 Hz)
Remarks 1. fSG: Source clock frequency of 7-bit counter
2. Values in parentheses apply to the case when fSG = fXT (32.768 kHz) is selected.
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CHAPTER 9 SOUND GENERATOR
Figure 9-4. Format of Sound Generator Frequency Setting Register 00 (4/5)
MDL006 MDL005 MDL004 MDL003 MDL002 MDL001 MDL000
Setting of sound generator frequency
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSG/65
fSG/66
fSG/67
fSG/68
fSG/69
fSG/70
fSG/71
fSG/72
fSG/73
fSG/74
fSG/75
fSG/76
fSG/77
fSG/78
fSG/79
fSG/80
fSG/81
fSG/82
fSG/83
fSG/84
fSG/85
fSG/86
fSG/87
fSG/88
fSG/89
fSG/90
fSG/91
fSG/92
fSG/93
fSG/94
fSG/95
fSG/96
(504 Hz)
(496 Hz)
(489 Hz)
(482 Hz)
(475 Hz)
(468 Hz)
(462 Hz)
(455 Hz)
(449 Hz)
(443 Hz)
(437 Hz)
(431 Hz)
(426 Hz)
(420 Hz)
(415 Hz)
(410 Hz)
(405 Hz)
(400 Hz)
(395 Hz)
(390 Hz)
(386 Hz)
(381 Hz)
(377 Hz)
(372 Hz)
(368 Hz)
(364 Hz)
(360 Hz)
(356 Hz)
(352 Hz)
(349 Hz)
(345 Hz)
(341 Hz)
Remarks 1. fSG: Source clock frequency of 7-bit counter
2. Values in parentheses apply to the case when fSG = fXT (32.768 kHz) is selected.
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Figure 9-4. Format of Sound Generator Frequency Setting Register 00 (5/5)
MDL006 MDL005 MDL004 MDL003 MDL002 MDL001 MDL000
Setting of sound generator frequency
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSG/97
(338 Hz)
(334 Hz)
(331 Hz)
(328 Hz)
(324 Hz)
(321 Hz)
(318 Hz)
(315 Hz)
(312 Hz)
(309 Hz)
(306 Hz)
(303 Hz)
(300 Hz)
(298 Hz)
(295 Hz)
(293 Hz)
(290 Hz)
(287 Hz)
(285 Hz)
(282 Hz)
(280 Hz)
(278 Hz)
(275 Hz)
(273 Hz)
(271 Hz)
(269 Hz)
(266 Hz)
(264 Hz)
(262 Hz)
(260 Hz)
(258 Hz)
(256 Hz)
fSG/98
fSG/99
fSG/100
fSG/101
fSG/102
fSG/103
fSG/104
fSG/105
fSG/106
fSG/107
fSG/108
fSG/109
fSG/110
fSG/111
fSG/112
fSG/113
fSG/114
fSG/115
fSG/116
fSG/117
fSG/118
fSG/119
fSG/120
fSG/121
fSG/122
fSG/123
fSG/124
fSG/125
fSG/126
fSG/127
fSG/128
Remarks 1. fSG: Source clock frequency of 7-bit counter
2. Values in parentheses apply to the case when fSG = fXT (32.768 kHz) is selected.
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CHAPTER 9 SOUND GENERATOR
(4) P3 function register (PF3)
This register is used to specify a buzzer output pin for the sound generator.
PF3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PF3 to 00H.
Figure 9-5. Format of P3 Function Register
Symbol
PF3
7
6
5
4
3
0
2
1
0
Address After reset
R/W
R/W
OE3
OE2
OE1
OE0
OM2
OM1
OM0
FF53H
00H
OEn
Control of P30/SG0 to P37/SG7 output
0
1
Output of SGn and SGn+4 pins disabled
Output of SGn and SGn+4 pins enabled
OM2
OM1
OM0
Selection of P30/SG0 to P37/SG7 output mode
0
0
0
0
0
1
General-purpose port mode (P30 to P37)
Buzzer mode 0
Pin P30/SG0 is used for buzzer output.
The other pins, P31/SG1 to P37/SG7, are used as ordinary general-purpose port
pins.
0
0
1
1
1
0
0
1
0
Buzzer mode 1
Pins P30/SG0 and P34/SG4 are used for buzzer output.
P34/SG4 outputs the inverted level of P30/SG0.
On-chip resistors are not connected for pins P30/SG0 to P37/SG7.
The other pins, P31/SG1 to P33/SG3 and P35/SG5 to P37/SG7, are used as ordinary
general-purpose port pins.
Buzzer mode 2
Pins P30/SG0 and P34/SG4 are used for buzzer output.
P34/SG4 outputs the inverted level of P30/SG0.
On-chip resistors are connected for pins P30/SG0 to P37/SG7.
The other pins, P31/SG1 to P33/SG3 and P35/SG5 to P37/SG7, are used as ordinary
general-purpose port pins.
Buzzer mode 3
Pins P30/SG0 to P37/SG7 are used for buzzer output.
P34/SG4, P35/SG5, P36/SG6, and P37/SG7 output the inverted level of P30/SG0,
P31/SG1, P32/SG2, and P33/SG3, respectively.
On-chip resistors are not connected for pins P30/SG0 to P37/SG7 (external resistor is
necessary).
Other than above
Setting prohibited
Remarks 1. n: 0 to 3
2. For detailed description of each mode, see 9.5 Sound Generator Output Mode.
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9.4 Setting of Sound Generator
9.4.1 Basic operation of sound generator
This sound generator can produce a sound (buzzer) of various frequencies by external connection of a buzzer
circuit.
• Volume: 10 steps
• Scale: 3 octaves (see Figure 9-4)
To operate as sound generators, settings must be made in the following sequence.
<1> Stop TMSG0 operation (TCESG0 = 0).
<2> Disable output of SG0 to SG7 (OE0 to OE3 = 0).
<3> Set the count value in CRSG0.
<4> Set the output mode of SG0 to SG7 by OM0 to OM2 (see Figure 9-5).
<5> Set the source clock of the carrier clock and the frequency of the sound to be output, by using SGFC00 (see
Figure 9-4).
<6> Set the TMSG0 count clock to carrier clock (TCLSG00 = 1, TCLSG01 = 1) (see Figure 9-2).
<7> Enable sound output (RMCSG0 (bit 2 of carrier generator output control register SG0 (TCASG0)) = 0).
Input the required value to NRZBSG0 (bit 1 of TCASG0) by program.
Input a value to NRZSG0 (bit 0 of TCASG0) before it is reloaded from NRZBSG0.
<8> Set the SGn pin that is used as buzzer output to output mode (PM3n = 0, P3n = 0) and enable SGn output
by OE0 to OE3 (n: 0 to 7).
<9> Enable the TMSG0 operation (TCESG0 = 1).
<10> Save the value of NRZBSG0 to a general-purpose register.
<11> If INTTMSG0 rises, the value of NRZBSG0 is transferred to NRZSG0. After that, rewrite TCASG0 by using
an 8-bit memory manipulation instruction. Input the value to be transferred to NRZSG0 next to NRZBSG0,
and input the value saved in <9> above to NRZSG0.
<12> By repeating <10> and <11>, generate the desired carrier signal.
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The operation of the sound generator is as follows.
<1> The carrier clock of the frequency set by SGFC00 is generated.
<2> When the count value of TMSG0 matches the value set in CRSG0, an interrupt request signal (INTTMSG0)
is generated. The rising edge of this INTTMSG0 serves as a signal to reload data to NRZBSG0, and is
transferred to NRZSG0.
<3> The carrier clock is output from the sound generator pin (SGn) while the value of NRZSG0 is “1”. When it is
“0”, a low level is output from the SGn pin (n: 0 to 7).
SGn
(n: 0 to 7)
Cautions 1. TCASG0 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction.
2. When enabling the sound generator operation again after stopping it once, be sure to set
NRZBSG0 again because the previous value is not retained. In this case, also, a 1-bit
memory manipulation instruction cannot be used. Be sure to use an 8-bit memory
manipulation instruction.
3. To enable an operation of the sound generator, set a value to the compare register (CRSG0)
in advance, and input the necessary values to the NRZBSG0 and NRZSG0 flags before
starting the operation. Otherwise, the signal of the timer match circuit will be undefined and
the NRZSG0 flag will be undefined.
4. Accessing TCASG0 is prohibited when INTTMSG0 (interrupt generated by a match signal) is
output.
5. Accessing TCASG0 is prohibited when the value of 8-bit timer counter SG0 (TMSG0) is 00H.
To access TCASG0 when TMSG0 = 00H, wait for half the cycle of the count clock of TMSG0
before rewriting TCASG0.
Figure 9-6 shows the operation timing of the sound generator.
Figure 9-6. Timing of Sound Generator Operation
SGn
(n: 0 to 7)
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
NRZSG0
0
0
0
0
1
. . . .
1
1
0
1
1
1
0
1
NRZBSG0
0
0
0
INTTMSG0
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CHAPTER 9 SOUND GENERATOR
9.5 Sound Generator Output Mode
This sound generator has five output modes.
Table 9-2 shows the differences among these modes.
Table 9-2. Supported Buzzer Modes
Buzzer Mode Name
General-purpose port mode
Buzzer mode 0
P30/SG0 Pin
P31/SG1 to
P34/SG4 Pin
P35/SG5 to
On-Chip Resistor
for Buzzer Output
P33/SG3 Pins
P37/SG7 Pins
General-
General-
General-
General-
Cannot be used
Cannot be used
Cannot be used
Can be used
purpose port
purpose port
purpose port
purpose port
Buzzer output
Buzzer output
Buzzer output
General-
General-
General-
purpose port
purpose port
purpose port
Buzzer mode 1
General-
Buzzer output
General-
purpose port
purpose port
Buzzer mode 2
General-
Buzzer output
General-
purpose port
purpose port
Buzzer mode 3
Buzzer output Buzzer output Buzzer output Buzzer output
Cannot be used
(external resistor is necessary)
[Volume]
This sound generator can set volume in a total of 10 steps; in buzzer mode 0, buzzer mode 1, and buzzer mode 2
(eight steps). In buzzer mode 3, the volume can be changed to the desired level by the user by changing the
external resistor to be connected.
Table 9-3 shows the volumes settable in buzzer mode 2.
Table 9-3. Volume Settable in Buzzer Mode 2 (Eight Steps)
OE3
OE2
OE1
OE0
Volume in Buzzer Mode 2
(Value Where Volume in Buzzer Mode 1 is “100”)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
0
(output stopped)
(8/12)
67
80
86
89
91
92
93
(8/10)
(6/7)
(8/9)
(10/11)
(12/13)
(14/15)
Remark “Volume” in this table is shown as a ratio of the voltage applied to the buzzer element.
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CHAPTER 9 SOUND GENERATOR
9.5.1 General-purpose port mode
In this mode, the buzzer output is not used.
All the P30/SG0 to P37/SG7 pins are used as ordinary general-purpose port pins.
General-purpose port mode (OM2, OM1, OM0 = 000B)
OE3
OE2
OE1
OE0
P30
P30
P31
P31
P32
P32
P33
P33
P34
P34
P35
P35
P36
P36
P37
P37
×
×
×
×
SG0/P30
.
.
.
.
.
.
.
.
.
.
.
.
SG7/P37
9.5.2 Buzzer mode 0
In this mode, the P30/SG0 pin is used for buzzer output (the buzzer is driven on one side).
The other pins, P31/SG1 to P37/SG7, are used as ordinary general-purpose port pins.
Buzzer mode 0 (OM2, OM1, OM0 = 001B)
OE3
OE2
OE1
OE0
0
P30
P31
P31
P32
P32
P33
P33
P34
P34
P35
P35
P36
P36
P37
P37
×
×
×
Low-level
output
1
Buzzer
output
P31
P32
P33
P34
P35
P36
P37
OE0
(B) in Figure 9-1 (2/2)
SG0/P30
P31
Buzzer
.
.
.
.
.
.
.
.
.
.
P37
Remark The volume is lower than that in buzzer mode 1 because only one side of the buzzer is driven.
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CHAPTER 9 SOUND GENERATOR
9.5.3 Buzzer mode 1
In this mode, the P30/SG0 and P34/SG4 pins are used for buzzer output (the buzzer is driven on both sides).
The other pins, P31/SG1 to P33/SG3 and P35/SG5 to P37/SG7 are used as ordinary general-purpose port pins.
Buzzer mode 1 (OM2, OM1, OM0 = 010B)
OE3
OE2
OE1
OE0
0
P30
P31
P31
P32
P32
P33
P33
P34
P35
P35
P36
P36
P37
P37
×
×
×
Low-level
output
Low-level
output
1
Buzzer
output
P31
P32
P33
Buzzer
output
P35
P36
P37
OE0
(B) in Figure 9-1 (2/2)
SG0/P30
P31
P32
P33
Buzzer
SG4/P34
P35
P36
P37
Remark The volume is greater than that in buzzer mode 0 because both of the sides of the buzzer are driven.
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CHAPTER 9 SOUND GENERATOR
9.5.4 Buzzer mode 2
In this mode, the P30/SG0 and P34/SG4 pins are used for buzzer output (the buzzer is driven on both sides).
The other pins, P31/SG1 to P33/SG3 and P35/SG5 to P37/SG7 pins are used as ordinary general-purpose port
pins.
In this mode, the on-chip resistor can be used. By setting OE1 to OE3 and adjusting the on-chip resistor to be
connected, the volume can be adjusted.
Buzzer mode 2 (OM2, OM1, OM0 = 011B)
OE3
0
OE2
0
OE1
0
OE0
P30
P31
P31
P32
P32
P33
P33
P34
P35
P35
P36
P36
P37
P37
×
Low-level
output
Low-level
output
Other than above
Buzzer
output
P31
P32
P33
Buzzer
output
P35
P36
P37
OE3
OE2
OE1
OE0
On-Chip Resistor Connection to P30 Pin
On-Chip Resistor Connection to P34 Pin
1R
−
2R
−
4R
−
8R
√
1R
−
2R
−
4R
−
8R
√
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
−
−
√
√
−
−
√
√
−
√
−
√
−
√
−
√
−
√
√
√
−
√
√
√
√
−
−
√
√
−
−
√
√
−
√
√
√
−
√
√
√
√
−
√
√
√
−
√
√
√
√
√
√
√
√
√
Remark √: Connected, −: Not connected
SG0/P30
P31
8R
4R
2R
1R
(B) in Figure 9-1 (2/2)
OE1
P32
OE2
OE3
Buzzer
P33
SG4/P34
P35
8R
4R
2R
1R
OE1
P36
OE2
OE3
P37
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CHAPTER 9 SOUND GENERATOR
9.5.5 Buzzer mode 3
In this mode, all the P30/SG0 to P37/SG7 pins are used for buzzer output (the buzzer is driven on both sides).
The P30/SG0 to P37/SG7 pins cannot be used as general-purpose port pins.
In this mode, the on-chip resistor is not used and the user connects external resistors of the desired value to the
P30/SG0 to P37/SG7 pins. By setting OE1 to OE3 and adjusting the external resistor to be connected, the volume
can be adjusted.
Buzzer mode 3 (OM2, OM1, OM0 = 100B)
OE3
OE2
OE1
OE0
External Resistor Connection of P30 to P37 Pins
P30
P31
P32
P33
P34
P35
P36
P37
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
− (all low-level output)
√
−
√
−
√
−
√
−
√
−
√
−
√
−
√
−
√
√
−
−
√
√
−
−
√
√
−
−
√
√
−
−
−
√
√
√
√
−
−
−
−
√
√
√
√
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
−
√
−
√
−
√
−
√
√
−
−
√
√
−
−
√
√
−
−
√
√
−
−
−
√
√
√
√
−
−
−
−
√
√
√
√
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
Remark √: Connected, −: Not connected
External R0
External R1
External R2
(B) in Figure 9-1 (2/2)
SG0/P30
SG1/P31
SG2/P32
OE0
OE1
OE2
OE3
External R3
SG3/P33
Buzzer
External R4
External R5
External R6
External R7
SG4/P34
SG5/P35
SG6/P36
SG7/P37
OE0
OE1
OE2
OE3
Caution Be sure to connect a pull-down resistor before the buzzer element.
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9.5.6 Timing charts in respective buzzer modes
Figure 9-7 shows examples of output waveforms in the respective buzzer modes of the sound generator.
Figure 9-7. Examples of Output Waveforms in Respective Buzzer Modes
Carrier
clock
Sound
generator
output
[Buzzer mode 0]
P30/SG0
[Buzzer mode 1]
P30/SG0
P34/SG4
[Buzzer mode 2]
P30/SG0
P34/SG4
[Buzzer mode 3]
P30/SG0 to
Note
P33/SG3
P34/SG4 to
P37/SG7
Note
Note The waveform in buzzer mode 3 depends on the resistance of the external resistor connected by the user
and the setting of OE0 to OE3.
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CHAPTER 10 WATCH TIMER
10.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 10-1 shows a block diagram of the watch timer.
Figure 10-1. Block Diagram of Watch Timer
Clear
f
CLK/27
5-bit counter
Clear
INTWT
INTWTI
13-bit prescaler
fW
fW
fW
fW
f
W
f
W
f
W
29
28 210 211 212 213
fXT
3
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
Remark fCLK: fX or fCC
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CHAPTER 10 WATCH TIMER
(1) Watch timer
The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz or 2.0 MHz, it cannot be used to
generate a 0.5-second interval. In this case, the subsystem clock, which operates at 32.768
kHz, should be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWTI) at specified intervals.
Table 10-1. Interval Time of Interval Timer
Interval Time
@ fX = 5.0 MHz
Operation
@ fX = 4.19 MHz
Operation
@ fCC = 2.0 MHz
Operation
@ fXT = 32.768 kHz
Operation
28 × 1/fW
6.55 ms
7.81 ms
16.4 ms
7.81 ms
29 × 1/fW
210 × 1/fW
211 × 1/fW
212 × 1/fW
213 × 1/fW
13.1 ms
26.2 ms
52.4 ms
104.9 ms
209.7 ms
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
32.8 ms
65.5 ms
131 ms
262 ms
524 ms
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
Remarks 1. fW: Watch timer clock frequency (fX/27, fCC/27, or fXT)
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
4. fXT: Subsystem clock oscillation frequency
10.2 Watch Timer Configuration
The watch timer includes the following hardware.
Table 10-2. Configuration of Watch Timer
Item
Counter
Configuration
5 bits × 1
Prescaler
13 bits × 1
Control register
Watch timer mode control register (WTM)
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CHAPTER 10 WATCH TIMER
10.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer.
•
Watch timer mode control register (WTM)
WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also
specifies the prescaler interval and how the 5-bit counter is controlled.
WTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WTM to 00H.
Figure 10-2. Format of Watch Timer Mode Control Register
Symbol
WTM
7
6
5
4
3
0
2
0
<1>
<0>
Address After reset
FF4AH 00H
R/W
R/W
WTM7
WTM6
WTM5
WTM4
WTM1
WTM0
WTM7
Watch timer count clock (fW) selection
@fX = 5.0 MHz and fXT = 32.768 kHz operation
fX/27 (39.1 kHz)
@fCC = 2.0 MHz and fXT = 32.768 kHz operation
fCC/27 (15.6 kHz)
0
1
fXT (32.768 kHz)
WTM6
WTM5
WTM4
Prescaler interval selection
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
28/fW
29/fW
210/fW
211/fW
212/fW
213/fW
Other than above
Setting prohibited
WTM1
Control of 5-bit counter operation
0
1
Cleared after stop
Started
WTM0
Watch timer operation
0
1
Operation stopped (both prescaler and timer cleared)
Operation enabled
Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
4. fXT: Subsystem clock oscillation frequency
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CHAPTER 10 WATCH TIMER
10.4 Watch Timer Operation
10.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer that generates 0.5-
second intervals.
The watch timer is used to generate an interrupt request at specified intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By clearing them to 0, the 5-bit counter is cleared and the watch timer stops counting.
When the interval timer also operates at the same time, only the watch timer can be started from 0 seconds by
clearing WTM1 to 0. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer
(INTWT) after a 0-second start because the 13-bit prescaler is not cleared in this case.
10.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 10-3. Interval Time of Interval Timer
Interval Time
@ fX = 5.0 MHz
Operation
@ fX = 4.19 MHz
Operation
@ fCC = 2.0 MHz
Operation
@ fXT = 32.768 kHz
Operation
28 × 1/fW
6.55 ms
7.81 ms
16.4 ms
7.81 ms
29 × 1/fW
210 × 1/fW
211 × 1/fW
212 × 1/fW
213 × 1/fW
13.1 ms
26.2 ms
52.4 ms
104.9 ms
209.7 ms
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
32.8 ms
65.5 ms
131 ms
262 ms
524 ms
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
Remarks 1. fW: Watch timer clock frequency (fX/27, fCC/27, or fXT)
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
4. fXT: Subsystem clock oscillation frequency
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Figure 10-3. Watch Timer/Interval Timer Operation Timing
5-bit counter
0H
Start
Overflow
Overflow
Count clock
/29
fW
Watch timer
interrupt
INTWT
Watch timer interrupt time (0.5 s)
Watch timer interrupt time (0.5 s)
Interval timer
interrupt
INTWTI
Interval
T
timer (T)
Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch
timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first
interrupt request after this setting will not be exactly the same as the watch timer interrupt time
(0.5 s). This is because the 5-bit counter starts counting one cycle after the output of the 13-bit
prescaler. The INTWT signal will be generated at the set time from its second generation.
Remarks 1. fW: Watch timer clock frequency
2. The parenthesized values apply to operation at fW = 32.768 kHz.
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CHAPTER 11 WATCHDOG TIMER
11.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect inadvertent program loop. When the inadvertent program loop is
detected, a non-maskable interrupt or the RESET signal can be generated.
Table 11-1. Inadvertent Program Loop Detection Time of Watchdog Timer
Inadvertent Program Loop
Detection Time
@ fX = 5.0 MHz Operation
@ fCC = 2.0 MHz Operation
@ fXT = 32.768 kHz Operation
213 × 1/fW
214 × 1/fW
210 ms
419 ms
524 ms
1.05 s
250 ms
500 ms
Remarks 1. fW: fX/27, fCC/27, or fXT
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
4. fXT: Subsystem clock oscillation frequency
(2) Interval timer
The interval timer generates an interrupt at any preset intervals.
Table 11-2. Interval Time of Watchdog Timer
Interval Time
@ fX = 5.0 MHz Operation
210 ms
419 ms
@ fCC = 2.0 MHz Operation
524 ms
1.05 s
@ fXT = 32.768 kHz Operation
213 × 1/fW
214 × 1/fW
250 ms
500 ms
Remarks 1. fW: fX/27, fCC/27, or fXT
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
4. fXT: Subsystem clock oscillation frequency
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11.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 11-3. Configuration of Watchdog Timer
Item
Configuration
Watchdog timer clock selection register (WDCS)
Control registers
Watchdog timer mode register (WDTM)
Figure 11-1. Block Diagram of Watchdog Timer
Internal bus
WDTMK1
INTWDT1
WDTIF1
Maskable
interrupt request
f
CLK/27
f
W
W
/26
/27
fW
7-bit counter
Clear
Prescaler
RESET
fXT
f
INTWDT0
Non-maskable
interrupt request
WDTM4 WDTM3
RUN
WDCS2 WDCS1
Watchdog timer clock selection
register (WDCS)
Watchdog timer mode register
(WDTM)
Internal bus
Remark fCLK: fX or fCC
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11.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock selection register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input clears WDCS to 00H.
Figure 11-2. Format of Watchdog Timer Clock Selection Register
Symbol
WDCS
7
0
6
0
5
0
4
0
3
0
2
1
0
0
Address After reset
FF42H 00H
R/W
R/W
WDCS2 WDCS1
WDCS2 WDCS1
Selection of count clock
@ fX = 5.0 MHz and fXT = 32.768 kHz operation @ fCC = 2.0 MHz and fXT = 32.768 kHz operation
fX/213 (610 Hz)
fX/214 (305 Hz)
fXT/26 (512 Hz)
fXT/27 (256 Hz)
fCC/213 (244 Hz)
fCC/214 (122 Hz)
0
0
1
1
0
1
0
1
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
Table 11-4. Inadvertent Program Loop Detection Time or Interval Time of Watchdog Timer
WDCS2 WDCS1
Inadvertent Program Loop Detection Time or Interval Time
@ fX = 5.0 MHz and fXT = 32.768 kHz Operation @ fCC = 2.0 MHz and fXT = 32.768 kHz Operation
220/fX (210 ms)
221/fX (419 ms)
213/fXT (250 ms)
214/fXT (500 ms)
220/fCC (524 ms)
221/fCC (1.05 s)
0
0
1
1
0
1
0
1
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
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(2) Watchdog timer mode register (WDTM)
This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 11-3. Format of Watchdog Timer Mode Register
Symbol
WDTM
<7>
6
0
5
0
4
3
2
0
1
0
0
0
Address After reset
FF4BH 00H
R/W
R/W
RUN
WDTM4 WDTM3
RUN
Selection of operation of watchdog timerNote 1
0
1
Stops counting
Clears counter and starts counting
WDTM4 WDTM3
Selection of operation mode of watchdog timerNote 2
0
0
1
1
0
1
0
1
Operation stopped
Interval timer mode (when overflow occurs, a maskable interrupt occurs)Note 3
Watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs)
Watchdog timer mode 2 (when overflow occurs, reset operation starts)
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is
started, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up
to 0.8% shorter than the time set by the watchdog timer clock selection register (WDCS).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that the WDTIF1 (bit 0
of interrupt request flag register 0 (IF0)) is cleared to 0. While WDTIF1 is 1, a non-
maskable interrupt is generated upon write completion if watchdog timer mode 1 or 2 is
selected.
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11.4 Watchdog Timer Operation
11.4.1 Operation as watchdog timer
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 1
and 2 (WDCS1 and WDCS2) of the watchdog timer clock selection register (WDCS). By setting bit 7 (RUN) of WDTM
to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after
the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If
RUN is not set to 1, and the inadvertent program loop detection time is exceeded, the system is reset or a non-
maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Cautions 1. The actual inadvertent program loop detection time may be up to 0.8% shorter than the set
time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
In this case, therefore, the watchdog timer stops operation even though the main system
clock is oscillating.
Table 11-5. Inadvertent Program Loop Detection Time of Watchdog Timer
WDCS2 WDCS1
Inadvertent Program Loop Detection Time
@ fX = 5.0 MHz and fXT = 32.768 kHz Operation @ fCC = 2.0 MHz and fXT = 32.768 kHz Operation
220/fX (210 ms)
221/fX (419 ms)
213/fXT (250 ms)
214/fXT (500 ms)
220/fCC (524 ms)
221/fCC (1.05 s)
0
0
1
1
0
1
0
1
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
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11.4.2 Operation as interval timer
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time
intervals specified by a preset count value.
Select a count clock (or interval time) by setting bits 1 and 2 (WDCS1 and WDCS2) of the watchdog timer clock
selection register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of
WDTM) is set to 1.
In the interval timer mode, the interrupt mask flag (WDTMK1) is valid, and a maskable interrupt (INTWDT1) can be
generated. The priority of INTWDT1 is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 11-6. Interval Time of Watchdog Timer
WDCS2 WDCS1
Interval Time
@ fX = 5.0 MHz and fXT = 32.768 kHz Operation @ fCC = 2.0 MHz and fXT = 32.768 kHz Operation
220/fX (210 ms)
221/fX (419 ms)
213/fXT (250 ms)
214/fXT (500 ms)
220/fCC (524 ms)
221/fCC (1.05 s)
0
0
1
1
0
1
0
1
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
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CHAPTER 12 8-BIT A/D CONVERTER (µPD78983xB, 78983xA, 78F9835 ONLY)
Caution The A/D converter is provided only for the µPD78983xB, 78983xA, and 78F9835.
It cannot be used with the µPD78983x.
12.1 8-Bit A/D Converter Functions
The 8-bit A/D converter converts input analog voltages into digital signals with an 8-bit resolution. It can control up
to three analog input channels (ANI0 to ANI2).
A/D conversion can be started only by software.
One of analog inputs ANI0 to ANI2 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD) being issued each time an A/D conversion is completed.
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12.2 8-Bit A/D Converter Configuration
The 8-bit A/D converter consists of the following hardware.
Table 12-1. Configuration of 8-Bit A/D Converter
Item
Analog input
Register
Configuration
3 channels (ANI0 to ANI2)
Successive approximation register (SAR)
A/D conversion result register (ADCR)
Control register
A/D converter mode register (ADM)
A/D input select register (ADS)
Figure 12-1. Block Diagram of 8-Bit A/D Converter
Series resistor string
V
DD
P-ch
Sample & hold circuit
ANI0/P60
ANI1/P61
ANI2/P62
Voltage comparator
V
SS
V
SS
Successive
approximation
register (SAR)
Controller
INTAD
A/D conversion result
register (ADCR)
2
ADS1 ADS0
ADCS FR2 FR1 FR0
A/D input select
register (ADS)
A/D converter mode
register (ADM)
Internal bus
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the series resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to the A/D conversion result register (ADCR).
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(2) A/D conversion result register (ADCR)
ADCR holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into ADCR, which is an 8-bit register that holds the
result of A/D conversion.
ADCR is read with an 8-bit memory manipulation instruction.
RESET input makes ADCR undefined.
(3) Sample & hold circuit
The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the series resistor string.
(5) Series resistor string
The series resistor string is configured between VDD and VSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI2 pins
Pins ANI0 to ANI2 are analog input pins for the three-channel A/D converter. They are used to receive the
analog signals to be A/D converted.
Caution Do not supply pins ANI0 to ANI2 with voltages that fall outside the rated range. If a voltage
equal to or greater than VDD or equal to or less than VSS (even if within the absolute
maximum rating) is supplied to any of these pins, the conversion value for the
corresponding channel will be undefined. Furthermore, the conversion values for the other
channels may also be affected.
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12.3 Registers Controlling 8-Bit A/D Converter
The following two registers are used to control the 8-bit A/D converter.
• A/D converter mode register (ADM)
• A/D input select register (ADS)
(1) A/D converter mode register (ADM)
ADM specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADM to 00H.
Figure 12-2. Format of A/D Converter Mode Register
Symbol <7>
ADM ADCS
6
0
5
4
3
2
0
1
0
0
0
Address
FF80H
After reset
00H
R/W
R/W
FR2 FR1 FR0
ADCS
A/D conversion control
0
1
Conversion stopped
Conversion enabled
A/D conversion time selectionNote
FR2 FR1 FR0
@f
X
= 5.0 MHz operation
s)
@fCC = 2.0 MHz operation
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
288/f
240/f
192/f
144/f
120/f
X
X
X
X
X
(57.6
µ
288/fCC
240/fCC
192/fCC
144/fCC
120/fCC
96/fCC
(144
µs)
(48
µ
s)
µ
(120 s)
µ
(38.4
(28.8
s)
s)
(96
µ
s)
µ
(72 s)
µ
(24
µ
s)
µ
(60 s)
96/f
X
(19.2 s)
(48 s)
µ
µ
Other than above
Setting prohibited
Note The specifications of FR2, FR1, and FR0 must be such that the A/D conversion time is at least 14 µs.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS) is set is undefined.
2. The result of conversion performed after ADCS is cleared may be undefined (see 12.5
(5) Timing that makes the A/D conversion result undefined for details).
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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(2) A/D input select register (ADS)
ADS specifies the port used to input the analog voltages to be converted to a digital signal.
ADS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADS to 00H.
Figure 12-3. Format of A/D Input Select Register
Symbol
ADS
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address
FF84H
After reset
00H
R/W
R/W
ADS1 ADS0
Analog input channel specification
ADS1 ADS0
0
0
1
1
0
1
0
1
ANI0
ANI1
ANI2
Setting prohibited
Caution Be sure to clear bits 2 to 7 to 0.
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12.4 8-Bit A/D Converter Operation
12.4.1 Basic operation of 8-bit A/D converter
<1> Select a channel for A/D conversion, using the A/D input select register (ADS).
<2> The voltage supplied to the selected analog input channel is sampled using the sample and hold circuit.
<3> After sampling continues for a certain period of time, the sample and hold circuit is put on hold to keep the
input analog voltage until A/D conversion is completed.
<4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap at the tap
selector is set to half of VDD.
<5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator.
If the analog input voltage is higher than half of VDD, the MSB of the SAR is left set. If it is lower than half of
VDD, the MSB is reset.
<6> Bit 6 of the SAR is set automatically, and comparison shifts to the next stage. The next voltage tap of the
series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows:
• Bit 7 = 1: Three quarters of VDD
• Bit 7 = 0: One quarter of VDD
The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of
comparison.
• Analog input voltage ≥ tap voltage: Bit 6 = 1
• Analog input voltage < tap voltage: Bit 6 = 0
<7> Comparison is repeated until bit 0 of the SAR is reached.
<8> When comparison is completed for all of the 8 bits, a significant digital result is left in the SAR. This value is
sent to and latched in the A/D conversion result register (ADCR). At the same time, it is possible to generate
an A/D conversion end interrupt request (INTAD).
Cautions 1. The first A/D conversion value immediately following the start of A/D conversion may
be undefined.
2. When the A/D converter enters the standby mode, it stops operating.
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Figure 12-4. Basic Operation of 8-Bit A/D Converter
Conversion
time
Sampling
time
A/D converter
operation
Sampling
Undefined
A/D conversion
C0H
or 40H
Conversion
result
SAR
ADCR
INTAD
80H
Conversion
result
A/D conversion continues until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
If an attempt is made to write to ADM or the A/D input select register (ADS) during A/D conversion, the A/D
conversion operation is initialized. In this case, A/D conversion is restarted from the beginning, if the ADCS is set (1).
RESET makes the A/D conversion result register (ADCR) undefined.
12.4.2 Input voltage and conversion result
The relationship between the analog input voltage at the analog input pins (ANI0 to ANI2) and the A/D conversion
result (A/D conversion result register (ADCR)) is represented by:
VIN
ADCR = INT (
or
× 256 + 0.5)
VDD
VDD
VDD
(ADCR − 0.5) ×
≤ VIN < (ADCR + 0.5) ×
256
256
INT( ): Function that returns the integer part of a parenthesized value
VIN:
Analog input voltage
VDD pin voltage
VDD:
ADCR: Value in the A/D conversion result register (ADCR)
Figure 12-5 shows the relationship between the analog input voltage and the A/D conversion result.
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Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253
A/D conversion
result (ADCR)
3
2
1
0
1
1
3
2
5
3
507 254 509 255 511
512 256 512 256 512
1
512 256 512 256 512 256
Input voltage/VDD
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12.4.3 Operation mode of 8-bit A/D converter
The 8-bit A/D converter is initially in the select mode. In this mode, the A/D input select register (ADS) is used to
select an analog input channel from ANI0 to ANI2 for A/D conversion.
A/D conversion can be started only by software, that is, by setting the A/D converter mode register (ADM).
The A/D conversion result is saved to the A/D conversion result register (ADCR). At the same time, an interrupt
request signal (INTAD) is generated.
• Software-started A/D conversion
Setting bit 7 (ADCS) of the A/D converter mode register (ADM) triggers A/D conversion for a voltage applied to
the analog input pin specified in the A/D input select register (ADS). Upon completion of A/D conversion, the
conversion result is saved to the A/D conversion result register (ADCR). At the same time, an interrupt request
signal (INTAD) is generated. Once A/D conversion is activated, and completed, another session of A/D
conversion is started. A/D conversion is repeated until new data is written to the ADM. If data where ADCS is 1
is written to ADM again during A/D conversion, the current session of A/D conversion is discontinued, and a
new session of A/D conversion begins for the new data. If data where ADCS is 0 is written to ADM again during
A/D conversion, A/D conversion is stopped immediately.
Figure 12-6. Software-Started A/D Conversion
Rewriting ADM
ADCS = 1
Rewriting ADM
ADCS = 1
ADCS = 0
A/D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion is
discontinued;
no conversion
Stop
result is preserved.
ADCR
INTAD
ANIn
ANIn
ANIm
Remarks 1. n = 0 to 2
2. m = 0 to 2
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12.5 Cautions Related to 8-Bit A/D Converter
(1) Current consumption in the standby mode
When the A/D converter enters the standby mode, it stops operating. Stopping conversion (bit 7 (ADCS) of
the A/D converter mode register (ADM) = 0) can reduce the current consumption.
Figure 12-7 shows how to reduce the current consumption in the standby mode.
Figure 12-7. How to Reduce Current Consumption in Standby Mode
VDD
ADCS
P-ch
Series resistor string
VSS
(2) Input range for the ANI0 to ANI2 pins
Be sure to keep the input voltage at ANI0 to ANI2 within the rated value. If a voltage equal to or greater than
VDD or equal to or less than VSS (even within the absolute maximum rating) is input to a conversion channel,
the conversion output of the channel becomes undefined. This may also affect the conversion output of the
other channels.
(3) Conflict
<1> Conflict between writing to the A/D conversion result register (ADCR) at the end of conversion and
reading from ADCR
Reading from ADCR takes precedence. After reading, the new conversion result is written to ADCR.
<2> Conflict between writing to ADCR at the end of conversion and writing to the A/D converter mode register
(ADM) or the A/D input select register (ADS)
Writing to ADM or ADS takes precedence. A request to write to ADCR is ignored. No A/D conversion
end interrupt request signal (INTAD) is generated.
(4) Conversion results immediately following start of A/D conversion
The first A/D conversion value immediately following the start of A/D conversion may be undefined. Be sure
to poll the A/D conversion end interrupt request (INTAD) and perform processing such as discarding the first
conversion result.
(5) Timing that makes the A/D conversion result undefined
If the timing of the end of A/D conversion and the timing at which the A/D converter stops operating conflict,
the A/D conversion value may be undefined. Because of this, be sure to read out the A/D conversion result
while the A/D converter is operating. Furthermore, when reading out an A/D conversion result after A/D
conversion has stopped, be sure to have done so by the time the next conversion result is complete.
The conversion result readout timing is shown in Figures 12-8 and 12-9.
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Figure 12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value)
A/D conversion end
A/D conversion end
ADCR
INTAD
ADCS
Normal conversion result
Undefined value
Normal conversion result read out
A/D operation stopped
Undefined
value read out
Figure 12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value)
A/D conversion end
Normal conversion result
ADCR
INTAD
ADCS
A/D operation stopped
Normal conversion
result read out
(6) Noise prevention
To maintain a resolution of 8 bits, be careful of noise at the VDD and ANI0 to ANI2 pins. The higher the output
impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external
capacitor to the relevant pins as shown in Figure 12-10.
Figure 12-10. Analog Input Pin Handling
If noise equal to or greater than VDD or equal to or
less than VSS is likely to come to the VDD pin, clamp
the voltage at the pin by attaching a diode with a
small V (0.3 V or lower).
F
V
DD
ANI0 to ANI2
C = 100 to 1000 pF
V
SS
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(7) ANI0 to ANI2
The analog input pins (ANI0 to ANI2) are alternate-function pins. They are also used as port pins (P60 to
P62).
If any of ANI0 to ANI2 has been selected for A/D conversion, do not execute input instructions for the ports;
otherwise the conversion resolution may become lower.
If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise
may occur which prevents an A/D conversion result from being attained as expected. Avoid applying a digital
pulse to pins adjacent to the analog input pins during A/D conversion.
(8) Input impedance of the ANI0 to ANI2 pins
This A/D converter charges the internal sampling capacitor for about 1/10 of the conversion time, and
performs sampling.
Therefore at times other than sampling, only the leak current is output. During sampling, the current for
charging the capacitor is also output, so the input impedance fluctuates and has no meaning.
However, to ensure adequate sampling, it is recommended that the output impedance of the analog input
source be set to below 10 kΩ, or a 100 pF capacitor be connected to the ANI0 to ANI2 pins (see Figure 12-
10).
(9) Interrupt request flag (ADIF)
Changing the contents of the A/D converter mode register (ADM) does not clear the interrupt request flag
(ADIF).
If the voltage at the analog input pins is changed during A/D conversion, therefore, the A/D conversion result
and the conversion end interrupt request flag may reflect the previous analog input just before writing to the
ADM occurs. In this case, ADIF may appear to be set if it is read-accessed just after ADM is write-accessed,
even when A/D conversion has not been completed for the new analog input.
In addition, when A/D conversion is restarted, ADIF must be cleared beforehand.
Figure 12-11. A/D Conversion End Interrupt Request Generation Timing
Rewriting ADM
(to begin conversion
for ANIn)
Rewriting ADM
(to begin conversion
for ANIm)
ADIF has been set, but conversion
for ANIm has not been completed.
A/D conversion
ANIn
ANIn
ANIm
ANIm
ANIn
ANIn
ANIm
ANIm
ADCR
INTAD
Remarks 1. n = 0 to 2
2. m = 0 to 2
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13.1 Serial Interface Functions
The serial interface has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out. It enables a reduction in the power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by dividing the clock input to the ASCK pin.
(3) 3-wire serial I/O mode (MSB/LSB-first switchable)
In this mode, 8-bit data transfer is carried out with three lines, one for the serial clock (SCK10) and two for
serial data (SI10, SO10).
The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing the data transfer
processing time.
It is possible to switch the first bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing
connection to devices with either bit first.
The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL
Series, 78K Series, and 17K Series that include a conventional clocked serial interface.
Figures 13-1 and 13-2 show the block diagrams of the serial interface.
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Figure 13-1. Block Diagram of Serial Interface (SIO10)
Internal bus
Serial operation mode register 10
(CSIM10)
CSIE10 TPS100
DIR10 CSCK10
Transmit/receive shift
register 10 (SIO10)
SI10/P22/RxD00
SO10/P21/TxD00
Output latch
(P21)
PM21
Interrupt request
generator
Serial clock counter
INTCSI10
SCK10/P20
F/F
Clock controller
PM20
Output latch
(P20)
f
f
X
X
/22
/23
CHAPTER 13 SERIAL INTERFACE
Figure 13-2. Block Diagram of Serial Interface (UART00)
Internal bus
Receive buffer
register 00
(RXB00)
PS001 PS000 CL00 SL00
TXE00 RXE00
ISRM00
Asynchronous serial interface
mode register 00 (ASIM00)
Asynchronous serial interface
status register 00 (ASIS00)
Transmit shift
register 00
(TXS00)
RxD00/
SI10/P22
Receive shift
register 00
(RXS00)
PE00
OVE00
FE00
Reception
controller
(parity check)
INTSER00
INTSR00
Transmission
controller
INTST00
(parity addition)
TxD00/
SO10/P21
Baud rate
generator
CLK/22 to fCLK/29
5-bit prescaler
f
4
3
PM21
Output latch
(P21)
MDL003
TPS001 TPS000
MDL001
TPS002
MDL002
MDL000
Baud rate generator control
register 00 (BRGC00)
Internal bus
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13.2 Serial Interface Configuration
The serial interface has the following hardware configuration.
Table 13-1. Configuration of Serial Interface
Item
Configuration
Registers
Transmit/receive shift register 10 (SIO10)
Transmit shift register 00 (TXS00)
Receive shift register 00 (RXS00)
Receive buffer register 00 (RXB00)
Control registers
Serial operation mode register 10 (CSIM10)
Asynchronous serial interface mode register 00 (ASIM00)
Asynchronous serial interface status register 00 (ASIS00)
Baud rate generator control register 00 (BRGC00)
(1) Transmit/receive shift register 10 (SIO10)
This is an 8-bit register used for parallel-to-serial conversion and to perform serial data transmission/reception
in synchronization with the serial clock in the 3-wire serial I/O mode.
SIO10 is set with an 8-bit memory manipulation instruction.
RESET input makes SIO10 undefined.
(2) Transmit shift register 00 (TXS00)
This register is used to specify the data to be transmitted in the UART mode. Data written to TXS00 is
transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS00 are transferred as the transmit
data. The transmit operation is started by writing data to TXS00.
TXS00 is written to with an 8-bit memory manipulation instruction. It cannot be read.
RESET input sets TXS00 to FFH.
Caution During a transmit operation, do not write to TXS00.
TXS00 and receive buffer register 00 (RXB00) are allocated to the same address, and when
reading is performed, RXB00 values are read.
(3) Receive shift register 00 (RXS00)
This register is used to convert serial data input to the RxD pin into parallel data in the UART mode. Each time
one byte of data is received, it is transferred to receive buffer register 00 (RXB00).
RXS00 cannot be manipulated directly by program.
(4) Receive buffer register 00 (RXB00)
This register is used to hold received data in the UART mode. Each time one byte of data is received, a new
byte of data is transferred from receive shift register 00 (RXS00).
If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB00, and the MSB of
RXB00 always becomes 0.
RXB00 can be read with an 8-bit memory manipulation instruction. It cannot be written to.
RESET input makes RXB00 undefined.
Caution RXB00 and transmit shift register 00 (TXS00) are allocated to the same address, and when
writing is performed, the values are written to TXS00.
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(5) Transmit controller
This controller controls transmit operations by adding a start bit, parity bit, and stop bit to data written to
transmit shift register 00 (TXS00), according to the data set to asynchronous serial interface mode register 00
(ASIM00).
(6) Receive controller
This controller controls receive operations according to the data set to asynchronous serial interface mode
register 00 (ASIM00). It also performs parity error check, etc., during receive operations, and when an error is
detected, it sets the value to asynchronous serial interface status register 00 (ASIS00) depending on the
nature of the error.
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13.3 Registers Controlling Serial Interface
The following four registers are used to control the serial interface.
• Serial operation mode register 10 (CSIM10)
• Asynchronous serial interface mode register 00 (ASIM00)
• Asynchronous serial interface status register 00 (ASIS00)
• Baud rate generator control register 00 (BRGC00)
(1) Serial operation mode register 10 (CSIM10)
This register is set when using the serial interface in the 3-wire serial I/O mode.
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Figure 13-3. Format of Serial Operation Mode Register 10
<7>
6
0
5
0
4
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM10 CSIE10
TPS100
DIR10 CSCK10
CSIE10
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
TPS100
Count clock selection when internal clock is selected
@ fCC = 2.0 MHz operation
(500 kHz)
@ fX = 5.0 MHz operation
fX/22
fX/23
fCC/22
fCC/23
(1.25 MHz)
(625 kHz)
0
1
(250 kHz)
DIR10
First bit specification
SIO10 clock selection
MSB
LSB
0
1
CSCK10
0
1
Clock input to SCK10 pin from external
Internal clock selected by TPS100
Cautions 1. Be sure to clear bits 0, 3, 5, and 6 to 0.
2. Clear CSIM10 to 00H in the UART mode.
3. When the clock input from an external source is selected in the 3-wire serial I/O mode, select
the input mode by setting bit 0 of port mode register 2 (PM2) to 1.
4. Switching operation modes must be performed after the serial transmit/receive operation has
been stopped.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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(2) Asynchronous serial interface mode register 00 (ASIM00)
This register is set when using the serial interface in the asynchronous serial interface mode.
ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM00 to 00H.
Figure 13-4. Format of Asynchronous Serial Interface Mode Register 00
Symbol <7> <6>
5
4
3
2
1
0
0
Address
FFA0H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00 ISRM00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
PS001 PS000
Parity bit specification
0
0
0
1
No parity
0 parity always added at transmission
Parity check is not performed at reception (no parity error is generated)
Odd parity
Even parity
1
1
0
1
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmit data stop bit length specification
0
1
1 bit
2 bits
ISRM00
Reception completion interrupt control at error occurrence
0
1
A reception completion interrupt request is generated when an error occurs.
A reception completion interrupt request is not generated when an error occurs.
Cautions 1. Be sure to clear bit 0 to 0.
2. Clear ASIM00 to 00H in the 3-wire serial I/O mode.
3. Switching operation modes must be performed after the serial transmit/receive operation has
been stopped.
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Table 13-2. Settings of Serial Interface Operating Mode
(1) Operation stop mode
ASIM00
CSIM10
PM22 P22 PM21 P21 PM20 P20 First Shift
P22/SI10/RxD00 P21/SO10/TxD00 P20/SCK10
Clock
Pin Function
Pin Function
Pin Function
Bit
CSCK10
TXE00 RXE00 CSIE10 DIR10
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
0
0
0
×
×
×
×
×
×
×
×
−
−
P22
P21
P20
Other than above
Setting prohibited
(2) Asynchronous serial interface mode
P22
First
Bit
ASIM00
CSIM10
PM22
PM21 P21 PM20 P20
Shift
Clock
P22/SI10/RxD00 P21/SO10/TxD00 P20/SCK10
Pin Function
Pin Function
Pin Function
TXE00 RXE00 CSIE10 DIR10 CSCK10
Note 1
Note 1
Note 1
Note 1
×
×
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
×
×
0
0
LSB
P22
TxD00
(CMOS output)
P20
Internal
clock
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
1
1
×
×
×
×
RxD00
P21
×
×
×
×
0
0
TxD0
(CMOS output)
Other than above
Setting prohibited
(3) 3-wire serial I/O mode
P22
First
Bit
ASIM00
CSIM10
PM22
PM21 P21 PM20 P20
Shift
Clock
P22/SI10/RxD00 P21/SO10/TxD00 P20/SCK10
Pin Function
Pin Function
Pin Function
TXE00 RXE00 CSIE10 DIR10 CSCK10
Note 2
0
0
1
0
0
1
0
1
1Note 2
×
0
1
1
0
1
0
×
1
×
1
MSB External SI10 Note 2
clock
SO10
(CMOS output)
SCK10 input
Internal
clock
SCK10 output
SCK10 input
SCK10 output
1
1
LSB External
clock
Internal
clock
Other than above
Setting prohibited
Notes 1. Can be used as port function.
2. If used only for transmission, can be used as P22 (CMOS I/O).
Remark ×: don’t care
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(3) Asynchronous serial interface status register 00 (ASIS00)
This register is used to display the type of receive error, if it occurs while asynchronous serial interface mode is
set.
ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS00 to 00H.
Figure 13-5. Format of Asynchronous Serial Interface Status Register 00
Symbol
ASIS00
7
0
6
5
4
3
2
1
0
Address After reset
R/W
R
0
0
0
0
PE00
FE00
OVE00
FFA3H 00H
PE00
Parity error flag
0
1
Parity error not generated
Parity error generated (when specified parity of transmit data does not match receive data parity)
FE00
Framing error flag
Framing error not generated
0
1
Framing error generatedNote 1 (when stop bit is not detected)
OVE00
Overrun error flag
0
1
Overrun error not generated
Overrun error generatedNote 2
(when the next receive operation is completed before the data is read from the receive buffer register)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface
mode register 00 (ASIM00), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not, an overrun
error will occur every time data is received.
Caution Be sure to clear bits 3 to 7 to 0.
(4) Baud rate generator control register 00 (BRGC00)
This register is used to specify the serial clock for the serial interface.
BRGC00 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC00 to 00H.
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Figure 13-6. Format of Baud Rate Generator Control Register 00
Symbol
7
0
6
5
4
3
2
1
0
Address After reset
R/W
R/W
BRGC00
TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000
FFA1H
00H
TPS002 TPS001 TPS000
Selection of 5-bit counter source clock (fSCK)
@ fX = 5.0 MHz operation
@ fCC = 2.0 MHz operation
n
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2 (2.5 MHz)
fCC/2 (1.0 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fCC/22 (500 kHz)
fCC/23 (250 kHz)
fCC/24 (125 kHz)
fCC/25 (62.5 kHz)
fCC/26 (31.3 kHz)
fCC/27 (15.6 kHz)
fCC/28 (7.81 kHz)
MDL003 MDL002 MDL001 MDL000
Selection of baud rate generator input clock
k
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
−
Setting prohibited
Cautions 1. Be sure to clear bit 7 to 0.
2. When writing to BRGC00 is performed during a communication operation, the output of
the baud rate generator is disrupted and communications cannot be performed normally.
Be sure not to write to BRGC00 during a communication operation.
Remarks 1. fX:
Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fSCK: Source clock of 5-bit counter
4. n:
5. k:
Value determined by the setting of TPS000 to TPS002 (1 ≤ n ≤ 8)
Value determined by the setting of MDL000 to MDL003 (0 ≤ k ≤ 14)
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The baud rate transmit/receive clock to be generated is a divided main system clock signal.
(a) Generation of UART baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by dividing the main system clock. The baud rate generated
from the main system clock is estimated by using the following expression.
fCLK
2n+2 × (k + 16)
[Baud rate] =
[Hz]
fCLK: Main system clock oscillation frequency (fX or fCC)
n:
k:
Value in Figure 13-6 determined by the settings of TPS000 to TPS002 (0 ≤ n ≤ 7)
Value in Figure 13-6 determined by the setting of MDL000 to MDL003 (0 ≤ k ≤ 14)
Table 13-3. Example of Relationship Between Main System Clock and Baud Rate (When fX = 5.0 MHz)
Baud Rate (bps)
BRGC00 Set Value
n
k
Error (%)
fX = 5.0 MHz
1.73
600
70H
60H
50H
40H
30H
20H
14H
10H
00H
7
6
5
4
3
2
1
1
0
0
0
0
0
0
0
4
0
0
1200
2400
4800
9600
19200
31250
38400
76800
0.00
1.73
Table 13-4. Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.9152 MHz)
Baud Rate (bps)
BRGC00 Set Value
n
k
Error (%)
fX = 4.9152 MHz
0.00
600
70H
60H
50H
40H
30H
20H
14H
10H
00H
7
6
5
4
3
2
1
1
0
0
0
0
0
0
0
4
0
0
1200
2400
4800
9600
19200
31250
38400
76800
−1.73
0.00
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Table 13-5. Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.1943 MHz)
Baud Rate (bps)
BRGC00 Set Value
n
k
Error (%)
fX = 4.1943 MHz
1.13
300
7BH
6BH
5BH
4BH
3BH
2BH
1BH
11H
0BH
7
6
5
4
3
2
1
1
0
11
11
11
11
11
11
11
1
600
1200
2400
4800
9600
19200
31250
38400
−1.33
11
1.13
Table 13-6. Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.00 MHz)
Baud Rate (bps)
BRGC00 Set Value
n
k
Error (%)
fX = 4.00 MHz
0.16
300
7AH
6AH
5AH
4AH
3AH
2AH
1AH
10H
0AH
7
6
5
4
3
2
1
1
0
10
10
10
10
10
10
10
0
600
1200
2400
4800
9600
19200
31250
38400
0.00
0.16
10
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13.4 Serial Interface Operation
The serial interface provides the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
13.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed, enabling a reduction in the power consumption.
The P20/SCK10, P21/SO10/TxD00, and P22/SI10/RxD00 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 10 (CSIM10) and asynchronous serial interface
mode register 00 (ASIM00).
(a) Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM00 to 00H.
<7>
6
0
5
0
4
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM10 CSIE10
TPS100
DIR10 CSCK10
CSIE10
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
Caution Be sure to clear bits 0, 3, 5, and 6 to 0.
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM00 to 00H.
Symbol <7> <6>
5
4
3
2
1
0
0
Address
FFA0H
After reset
00H
R/W
R/W
ASIM00 TXE00 RXE00 PS001 PS000 CL00 SL00 ISRM00
TXE00
Transmit operation control
0
1
Transmit operation stopped
Transmit operation enabled
RXE00
Receive operation control
0
1
Receive operation stopped
Receive operation enabled
Caution Be sure to clear bit 0 to 0.
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13.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received enabling full-duplex communications.
This device incorporates a UART-dedicated baud rate generator, allowing communication at a wide range of baud
rates.
The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI
standard.
(1) Register setting
UART mode is set by serial operation mode register 10 (CSIM10), asynchronous serial interface mode register
00 (ASIM00), asynchronous serial interface status register 00 (ASIS00), and baud rate generator control
register 00 (BRGC00).
(a) Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Clear CSIM10 to 00H in the UART mode.
<7>
6
0
5
0
4
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM10 CSIE10
TPS100
DIR10 CSCK10
CSIE10
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
TPS100
Count clock selection when internal clock is selected
@ fCC = 2.0 MHz operation
@ f = 5.0 MHz operation
X
/22
/23
(500 kHz)
(250 kHz)
f
f
CC/22
CC/23
(1.25 MHz)
(625 kHz)
f
f
X
X
0
1
DIR10
Start bit specification
MSB
LSB
0
1
CSCK10
SIO10 clock selection
0
1
Clock input to SCK10 pin from external
Internal clock selected by TPS100
Cautions 1. Be sure to clear bits 0, 3, 5, and 6 to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation has been stopped.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM00 to 00H.
Caution When using the serial interface function (UART mode), clear the related output latches
to 0, and the port mode registers (PM××) as follows.
• For reception
Set P22 (RxD00) to input mode (PM22 = 1).
• For transmission
Set P21 (TxD00) to output mode (PM21 = 0).
• For transmission and reception
Set P22 and P21 to input and output mode, respectively.
Symbol
<7>
<6>
5
4
3
2
1
0
0
Address After reset
FFA0H 00H
R/W
R/W
ASIM00 TXE00
RXE00
PS001
PS000
CL00
SL00
ISRM00
TXE00
RXE00
Operation mode
Function of RxD00/SI10/P22 pin Function of TxD00/SO10/P21 pin
0
0
1
0
1
0
Operation disabled
Port function (P22)
Serial function (RxD00)
Port function (P22)
Port function (P21)
UART mode (reception only)
UART mode (transmission
only)
Serial function (TxD00)
1
1
UART mode (transmission
and reception)
Serial function (RxD00)
Parity bit specification
PS001
PS000
0
0
0
1
No parity
At transmission, the parity bit is fixed to 0.
At reception, a parity check is not made; no parity error is reported.
1
1
0
1
Odd parity
Even parity
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmission data stop bit length specification
0
1
1 bit
2 bits
ISRM00
Reception completion interrupt control at error occurrence
0
1
A reception completion interrupt request is generated when an error occurs.
A reception completion interrupt request is not generated when an error occurs.
Cautions 1. Be sure to clear bit 0 to 0.
2. Switch the operation mode after stopping serial transmission/reception.
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(c) Asynchronous serial interface status register 00 (ASIS00)
ASIS00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS00 to 00H.
Symbol
ASIS00
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After reset
FFA3H 00H
R/W
R
PE00
FE00
OVE00
PE00
Parity error flag
0
1
Parity error not generated
Parity error generated (when specified parity of transmit data does not match receive data parity)
FE00
Framing error flag
Framing error not generated
0
1
Framing error generatedNote 1 (when stop bit is not detected)
OVE00
Overrun error flag
0
1
Overrun error not generated
Overrun error generatedNote 2
(when the next receive operation is completed before the data is read from the receive buffer register)
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL00) of asynchronous serial interface
mode register 00 (ASIM00), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 00 (RXB00) when an overrun error occurs. If not, an overrun
error will occur every time data is received.
Caution Be sure to clear bits 3 to 7 to 0.
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(d) Baud rate generator control register 00 (BRGC00)
BRGC00 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC00 to 00H.
Symbol
7
0
6
5
4
3
2
1
0
Address After reset
R/W
R/W
BRGC00
TPS002 TPS001 TPS000 MDL003 MDL002 MDL001 MDL000
FFA1H
00H
TPS002 TPS001 TPS000
Selection of 5-bit counter source clock (fSCK)
@ fX = 5.0 MHz operation
@ fCC = 2.0 MHz operation
n
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2 (2.5 MHz)
fCC/2 (1.0 MHz)
fX/22 (1.25 MHz)
fX/23 (625 kHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fCC/22 (500 kHz)
fCC/23 (250 kHz)
fCC/24 (125 kHz)
fCC/25 (62.5 kHz)
fCC/26 (31.3 kHz)
fCC/27 (15.6 kHz)
fCC/28 (7.81 kHz)
MDL003 MDL002 MDL001 MDL000
Selection of baud rate generator input clock
k
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
−
Setting prohibited
Cautions 1. Be sure to clear bit 7 to 0.
2. When writing to BRGC00 is performed during a communication operation, the output of
the baud rate generator is disrupted and communications cannot be performed normally.
Be sure not to write to BRGC00 during a communication operation.
Remarks 1. fX:
Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fSCK: Source clock of 5-bit counter
4. n:
5. k:
Value determined by the setting of TPS000 to TPS002 (1 ≤ n ≤ 8)
Value determined by the setting of MDL000 to MDL003 (0 ≤ k ≤ 14)
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The baud rate transmit/receive clock to be generated is a divided main system clock signal.
•
Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by dividing the main system clock. The baud rate generated from
the main system clock is estimated by using the following expression.
fCLK
2n + 2 (k + 16)
[Baud rate] =
[Hz]
fCLK: fX or fCC
fX:
Main system clock oscillation frequency (ceramic/crystal oscillation)
fCC: Main system clock oscillation frequency (RC oscillation)
Table 13-7 shows the relationship between the source clock of the 5-bit counter assigned to bits 4 to 6
(TPS000 to TPS002) of BRGC00 and value n, while Table 13-8 shows that between the input clock of the
baud rate generator and value k.
Table 13-7. Relationship Between Source Clock of 5-Bit Counter and Value n
TPS002
TPS001
TPS000
5-Bit Counter Source Clock Selection
n
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fCLK/2
fCLK/22
fCLK/23
fCLK/24
fCLK/25
fCLK/26
fCLK/27
fCLK/28
Remarks 1. fCLK: fX or fCC
2. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. fCC: Main system clock oscillation frequency (RC oscillation)
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Table 13-8. Relationship Between Input Clock of Baud Rate Generator and Value k
MDL003 MDL002 MDL001 MDL000
Selection of Baud Rate Generator Input Clock
k
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fSCK/16
fSCK/17
fSCK/18
fSCK/19
fSCK/20
fSCK/21
fSCK/22
fSCK/23
fSCK/24
fSCK/25
fSCK/26
fSCK/27
fSCK/28
fSCK/29
fSCK/30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
−
Setting prohibited
Remark fSCK: Source clock of 5-bit counter
Permissible error range of baud rate
•
The permissible error range of the baud rate is dependent upon the number of bits of one frame and the
division ratio of the counter [1/(16 + k)].
Figure 13-7. Permissible Error in Baud Rate Allowing for Sampling Error (Where k = 0)
Ideal sampling
point
32T
64T
256T
320T
352T
288T
336T
304T
P
Basic timing
(clock cycle T)
START
D7
D0
STOP
15.5T
STOP
High-speed clock that can
be received normally
(clock cycle T’)
START
START
D0
P
D7
Sampling error
0.5T
15.5T
304.5T
60.9T
30.45T
33.55T
Low-speed clock that can
be received normally
(clock cycle T”)
P
STOP
335.5T
D0
D7
67.1T
301.95T
Remark T: Source clock cycle of 5-bit counter
15.5
320
Permissible error range of baud rate (where k = 0) =
× 100 = 4.8438 (%)
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(2) Communication operation
(a) Data format
The transmission/reception data format is as shown in Figure 13-8.
Figure 13-8. Asynchronous Serial Interface Transmission/Reception Data Format
One data frame
Start
bit
Parity
bit
Stop bit
D0
D1
D3
D2
D4
D7
D5
D6
Character bit
One data frame consists of the following bits.
•
•
•
•
Start bit:
1 bit
Character bits: 7 bits/8 bits
Parity bits:
Stop bit(s):
Even parity/odd parity/0 parity/no parity
1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each
data frame is carried out using asynchronous serial interface mode register 00 (ASIM00).
When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always “0”.
The serial transfer rate is selected by means of ASIM00 and baud rate generator control register 00
(BRGC00).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of asynchronous serial interface status register 00 (ASIS00).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same parity bit is
used on the transmitting side and the receiving side. With even parity and odd parity, a 1-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• Transmission
The transmission operation is controlled so that the number of bits with a value of “1” in the
transmission data including parity bit is even. The parity bit value should be as follows.
The number of bits with a value of “1” is an odd number in transmission data:
1
The number of bits with a value of “1” is an even number in transmission data: 0
• Reception
The number of bits with a value of “1” in the reception data including parity bit is counted, and if the
number is odd, a parity error is generated.
(ii) Odd parity
• Transmission
As opposed to even parity, the transmission operation is controlled so that the number of bits with
a value of “1” in the transmission data including parity bit is odd. The parity bit value should be as
follows.
The number of bits with a value of “1” is an odd number in transmission data:
0
The number of bits with a value of “1” is an even number in transmission data: 1
• Reception
The number of bits with a value of “1” in the reception data including parity bit is counted, and if the
number is even, a parity error is generated.
(iii) 0 parity
When transmitting, the parity bit is set to “0” irrespective of the transmission data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated,
irrespective of whether the parity bit is set to “0” or “1”.
(iv) No parity
A parity bit is not added to the transmission data. At reception, data is received assuming that
there is no parity bit. Since there is no parity bit, a parity error is not generated.
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(c) Transmission
A transmit operation is enabled by setting bit 7 (TXE00) of asynchronous serial interface mode register
00 (ASIM00) to 1 and is started by writing transmit data to transmission shift register 00 (TXS00). The
start bit, parity bit, and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS00 is shifted out, and when TXS00 is empty, a
transmission completion interrupt request (INTST00) is generated.
The transmission completion interrupt timing is shown in Figure 13-9.
Figure 13-9. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(i) Stop bit length: 1
STOP
TxD00 (Output)
INTST00
D0
D1
D2
D6
D7
Parity
START
(ii) Stop bit length: 2
D0
D1
D2
D6
D7
Parity
TxD00 (Output)
INTST00
STOP
START
Caution Do not overwrite asynchronous serial interface mode register 00 (ASIM00) during a
transmit operation. If the ASIM00 register is overwritten during transmission,
subsequent transmission may not be performed (the normal state is restored by RESET
input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt request (INTST00) or the interrupt request flag
(STIF00) set by INTST00.
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(d) Reception
When bit 6 (RXE00) of asynchronous serial interface mode register 00 (ASIM00) is set to 1, a receive
operation is enabled and sampling of the RxD00 pin input is performed.
RxD00 pin input sampling is performed using the serial clock specified by BRGC00.
When the RxD00 pin input becomes low, the 5-bit counter of the baud rate generator starts counting,
and when half the time determined by the specified baud rate has passed, the data sampling start
timing signal is output. If the RxD00 pin input sampled again as a result of this start timing signal is low,
it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is
performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception
of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to receive
buffer register 00 (RXB00), and a reception completion interrupt request (INTSR00) is generated.
Even if an error occurs, the receive data in which the error occurred is still transferred to RXB00. If bit 1
(ISRM00) of ASIM00 is cleared to 0 when an error occurs, INTSR00 is generated (see Figure 13-11). If
the ISRM00 bit is set to 1, INTSR00 is not generated.
If the RXE00 bit is cleared to 0 during the receive operation, the receive operation is stopped
immediately. In this case, the contents of RXB00 and ASIS00 are not changed, and INTSR00 and
INTSER00 are not generated.
Figure 13-10 shows the asynchronous serial interface reception completion interrupt timing.
Figure 13-10. Asynchronous Serial Interface Reception Completion Interrupt Timing
STOP
D0
D1
D2
D6
D7
Parity
RxD00 (Input)
INTSR00
START
Caution Be sure to read reception buffer register 00 (RXB00) even if a receive error occurs. If
RXB00 is not read, an overrun error will be generated when the next data is received,
and the receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. If the error flag in asynchronous serial interface status register 00 (ASIS00) is set to 1 as a result
of data reception, a reception error interrupt request (INTSER00) is generated. The reception error
interrupt occurs before the reception completion interrupt request (INTSR00). Receive error causes are
shown in Table 13-9.
It is possible to determine what kind of error occurred during reception by reading the contents of
ASIS00 in the reception error interrupt servicing (INTSER00) (see Table 13-9 and Figure 13-11).
The contents of ASIS00 are cleared to 0 by reading receive buffer register 00 (RXB00) or receiving the
next data (if there is an error in the next data, the corresponding error flag is set).
Table 13-9. Receive Error Causes
Receive Error
Parity error
Cause
Parity specification at transmission and reception data parity do not match
Stop bit not detected
ASIS00 Value
04H
Framing error
Overrun error
02H
Reception of next data is completed before data is read from receive buffer
register 00
01H
Figure 13-11. Receive Error Timing
STOP
RxD00 (Input)
START D0
D1
D2
D6
D7
Parity
INTSR00Note
INTSER00
(Framing error or overrun
error occurs)
INTSER00
(Parity error occurs)
Note If the receive error occurs when the ISRM00 bit is set to 1, INTSR00 is not generated.
Cautions 1. The contents of asynchronous serial interface status register 00 (ASIS00) are
cleared to 0 by reading receive buffer register 00 (RXB00) or receiving the next data.
To ascertain the error contents, read ASIS00 before reading RXB00.
2. Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If
RXB00 is not read, an overrun error will be generated when the next data is
received, and the receive error state will continue indefinitely.
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13.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., that incorporate
a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series.
Communication is performed using three lines: the serial clock (SCK10), serial output (SO10), and serial input
(SI10) lines.
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 10 (CSIM10), asynchronous
serial interface mode register 00 (ASIM00), and baud rate generator control register 00 (BRGC00).
(a) Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
<7>
6
0
5
0
4
3
0
2
1
0
0
Address
FF72H
After reset
00H
R/W
R/W
Symbol
CSIM10 CSIE10
TPS100
DIR10 CSCK10
CSIE10
Operation control in 3-wire serial I/O mode
0
1
Operation stopped
Operation enabled
TPS100
Count clock selection when internal clock is selected
@ fCC = 2.0 MHz operation
@ f = 5.0 MHz operation
X
/22
/23
(500 kHz)
(250 kHz)
f
f
CC/22
CC/23
(1.25 MHz)
(625 kHz)
f
f
X
X
0
1
DIR10
First bit specification
MSB
LSB
0
1
CSCK10
SIO10 clock selection
0
1
Input clock to SCK10 pin from external
Internal clock selected by TPS100
Cautions 1. Be sure to clear bits 0, 3, 5, and 6 to 0.
2. When the clock input from an external source is selected in the 3-wire serial I/O mode,
select the input mode by setting bit 0 of port mode register 2 (PM2) to 1.
3. Switching operation modes must be performed after the serial transmit/receive operation
has been stopped.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
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(b) Asynchronous serial interface mode register 00 (ASIM00)
ASIM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM00 to 00H.
Clear ASIM00 to 00H in the 3-wire serial I/O mode.
Symbol
<7>
<6>
5
4
3
2
1
0
0
Address After reset
FFA0H 00H
R/W
R/W
ASIM00 TXE00
RXE00
PS001
PS000
CL00
SL00
ISRM00
TXE00
RXE00
Operation mode
Function of RxD00/P22 pin
Port function (P22)
Function of TxD00/P21 pin
Port function (P21)
0
0
1
0
1
0
Operation stopped
UART mode (reception only)
Serial function (RxD00)
Port function (P22)
UART mode (transmission
only)
Serial function (TxD00)
1
1
UART mode (transmission
and reception)
Serial function (RxD00)
Parity bit specification
PS001
PS000
0
0
0
1
No parity
At transmission, the parity bit is fixed to 0.
At reception, a parity check is not made; no parity error is reported.
1
1
0
1
Odd parity
Even parity
CL00
Character length specification
0
1
7 bits
8 bits
SL00
Transmission data stop bit length specification
0
1
1 bit
2 bits
ISRM00
Reception completion interrupt control at error occurrence
0
1
A reception completion interrupt request is generated when an error occurs.
A reception completion interrupt request is not generated when an error occurs.
Cautions 1. Be sure to clear bit 0 to 0.
2. Switch the operation mode after stopping serial transmission/reception.
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
transmitted/received in 1-bit units in synchronization with the serial clock.
Data is
Transmit/receive shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the
serial clock (SCK10). Then transmit data is held in the SO10 latch and output from the SO10 pin. Also,
receive data input to the SI10 pin is latched in input bits of SIO10 on the rise of SCK10.
At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal
(INTCSI10) is generated.
Figure 13-12. 3-Wire Serial I/O Mode Timing
SCK10
SI10
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO10
INTCSI10
End of transfer
Transfer start at the falling edge of SCK10
Cautions 1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the data
cannot be transmitted or received.
2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and then
serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or received.
3. Once data has been written to SIO10 with the serial clock selected (CSCK10 = 0), overwriting
the data does not update the contents of SIO10.
4. When CSIM10 is operated during data transmission/reception, data cannot be transmitted or
received normally.
5. When SIO10 is operated during data transmission/reception, the data cannot be transmitted
or received normally.
(3) Transfer start
Serial transfer is started by setting transfer data to transmit/receive shift register 10 (SIO10) when the following
two conditions are satisfied.
•
•
Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1
Internal serial clock is stopped or SCK10 is a high level after 8-bit serial transfer.
An end of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI10).
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.1 Functions of LCD Controller/Driver
The LCD controller/driver has the following functions.
(1) Enables automatic output of segment signals and common signals by automatically reading from display data
memory.
(2) Four types of display modes can be selected:
•
•
•
•
1/8 duty (1/5 bias) (80 segments × 8 commons)
1/16 duty (1/5 bias) (80 segments × 16 commons)
1/32 duty (1/5 bias) (64 segments × 32 commons)
1/48 duty (1/5 bias) (48 segments × 48 commons)
(3) Any of four frame frequency settings can be selected for each display mode.
(4) Operation using the subsystem clock is also supported.
(5) Booster is incorporated.
14.2 Configuration of LCD Controller/Driver
The LCD controller/driver includes the following hardware.
Table 14-1. Configuration of LCD Controller/Driver
Item
Display outputs
Control registers
Configuration
Segment/common signals: 96 (LCD0 to LCD95)
LCD20 display mode register (LCDM20)
LCD20 clock control register (LCDC20)
LCD boost voltage level setting register (VLCD00)
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Figure 14-1. Block Diagram of LCD Controller/Driver
Internal bus
Display data memoryNote
• • • • • • • •
LCD20 clock control
register (LCDC20)
LCD20 display mode
register (LCDM20)
F××H
F××H
LCDC201
LCDON201
VAON20
LIPS20
LCDM201
LCDM200
LCDC200
2
LCDON200
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LCD boost
voltage level
setting register
00 (VLCD00)
2
Segment
selector
VLCD003
VLCD001
VLCD000
VLCD002
3 2 1 0
Selector
3 2 1 0
Selector
• • • • • • • •
...........
f
f
f
CLK/26
CLK/27
CLK/28
LCD
clock
generator
f
LCD
Prescaler
LCDCL
Timing
controller
f
XT
...........
2
2
• • • • • • • •
...........
4
...........
...........
Segment voltage
controller
Segment
driver
Segment
driver
Common voltage
controller
Common driver
• • • • •
LCD driving voltage controller
• • • • • • • •
Voltage regulator
• • • • • • • •
LCD47
V
LC2
V
LC1
V
LC0
LCD0
LCD48
V
LC4
V
LC3
CAP0
CAP1 CAP2
LCD95/P87
CAP3
Note The display area changes depending on the LCD display mode.
For details, see Figure 14-2 Format of LCD20 Display Mode Register.
CHAPTER 14 LCD CONTROLLER/DRIVER
14.3 Registers Controlling LCD Controller/Driver
The following three registers are used to control the LCD controller/driver.
•
•
•
LCD20 display mode register (LCDM20)
LCD20 clock control register (LCDC20)
LCD boost voltage level setting register 00 (VLCD00)
(1) LCD20 display mode register (LCDM20)
This register is used to set the display operation enabled/disabled status, booster enabled/stopped status, the
segment/common pin output, and the display mode.
LCDM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM20 to 00H.
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-2. Format of LCD20 Display Mode Register
Symbol
7
6
5
4
3
2
1
0
Address After reset
R/W
R/W
LCDM20 LCDON201 LCDON200 VAON20 LIPS20
0
0
LCDM201 LCDM200 FFB0H 00H
LCDON201 LCDON200
LCD display enable/disable
0
0
1
1
0
1
0
1
Display is OFF (all segment outputs are non-select signals)
Display is ON (pattern A)Note 1
Setting prohibited
Display is ON (pattern B)Note 1
VAON20
Booster operation enable/stopNote 2
0
1
Booster operation stop
Booster operation enable
LIPS20
Segment pin/common pin output controlNote 2
0
1
Output ground level to segment pin/common pin
Output non-selection level to segment pin and LCD waveform to common pin
LCDM201 LCDM200
Selection of LCD controller/driver display mode
1/5 bias
0
0
1
1
0
1
0
1
48 × 48 mode (1/48 duty)
64 × 32 mode (1/32 duty)
80 × 16 mode (1/16 duty)
80 × 8 mode (1/8 duty)Note 3
Notes 1. In pattern A, the RAM area is displayed between F8C0H and F9DFH, and in pattern B, between
F9E0H and FAFFH. For the memory map, see CHAPTER 3 CPU ARCHITECTURE.
2. When an LCD display is not needed, clear VAON20 and LIPS20 to 0 to reduce power consumption.
3. P80/LCD88 to P87/LCD95 are used as general-purpose input ports.
Cautions 1. Be sure to clear bits 2 and 3 to 0.
2. Observe the following sequence when manipulating VAON20.
A. To stop boosting the voltage by turning OFF the display
1) Turn off the display by clearing LCDON200 = 0 and LCDON201 = 0.
2) Disable output of all the segment buffers and common buffers by clearing LIPS20 =
0.
3) Stop boosting the voltage by clearing VAON20 = 0.
B. To stop boosting the voltage with the display ON
This setting is prohibited. Be sure to stop boosting the voltage after turning off the
display.
C. To turn on the display while boosting the voltage is stopped
1) Start boosting the voltage by setting VAON20 = 1 and wait for about 500 ms.
2) Place all the segment buffers and common buffers in non-display output status by
setting LIPS20 = 1.
3) Turn on the display by setting LCDON200 = 1.
To display pattern A, clear LCDON201 = 0. To display pattern B, set LCDON201 = 1.
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CHAPTER 14 LCD CONTROLLER/DRIVER
(2) LCD20 clock control register (LCDC20)
This register is used to set the LCD source clock and frame frequency.
LCDC20 is set with an 8-bit memory manipulation instruction.
RESET input clears LCDC20 to 00H.
Figure 14-3. Format of LCD20 Clock Control Register
Symbol
7
0
6
0
5
4
3
2
1
0
Address After reset
R/W
R/W
LCDC20
0
0
0
0
LCDC201 LCDC200 FFB2H 00H
LCDC201 LCDC200
Selection of LCD source clock (fLCD)
@ fX = 5.0 MHz and fXT = 32.768 kHz operation @ fCC = 2.0 MHz and fXT = 32.768 kHz operation
fX/26 (78.1 kHz)
fX/27 (39.1 kHz)
fX/28 (19.5 kHz)
fXT (32.768 kHz)
fCC/26 (31.3 kHz)
fCC/27 (15.6 kHz)
fCC/28 (7.81 kHz)
0
0
1
1
0
1
0
1
Caution Be sure to clear bits 2 to 7 to 0.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. fXT: Subsystem clock oscillation frequency
The frame frequency is determined by the duty factor in the display mode and the LCD source clock (fLCD).
Tables 14-2 to 14-5 show the frame frequency in each display mode.
Table 14-2. Frame Frequency (Hz) at 1/48 Duty (48 × 48 Mode)
LCDM201 LCDM200 LCDC201 LCDC200
LCD Source Clock
Frequency (fLCD)
Frame Frequency
@ fX = 4.19 MHz Operation @ fX = 5.0 MHz Operation
fX/26
0
0
0
0
1
1
0
1
0
1
42.7 Hz
21.3 Hz
10.7 Hz
21.3 Hz
50.9 Hz
25.4 Hz
12.8 Hz
fX/27
fX/28
fXT (32.768 kHz)
Table 14-3. Frame Frequency (Hz) at 1/32 Duty (64 × 32 Mode)
LCDM201 LCDM200 LCDC201 LCDC200
LCD Source Clock
Frequency (fLCD)
Frame Frequency
@ fX = 4.19 MHz Operation @ fX = 5.0 MHz Operation
fX/26
0
1
0
0
1
1
0
1
0
1
64 Hz
32 Hz
16 Hz
32 Hz
76.3 Hz
38.1 Hz
19.1 Hz
fX/27
fX/28
fXT (32.768 kHz)
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-4. Frame Frequency (Hz) at 1/16 Duty (80 × 16 Mode)
LCDM201 LCDM200 LCDC201 LCDC200
LCD Source Clock
Frequency (fLCD)
Frame Frequency
@ fX = 4.19 MHz Operation @ fX = 5.0 MHz Operation
fX/26
fX/27
fX/28
1
0
0
0
1
1
0
1
0
1
128 Hz
64 Hz
32 Hz
64 Hz
152.6 Hz
76.3 Hz
38.1 Hz
fXT (32.768 kHz)
Table 14-5. Frame Frequency (Hz) at 1/8 Duty (80 × 8 Mode)
LCDM201 LCDM200 LCDC201 LCDC200
LCD Source Clock
Frequency (fLCD)
Frame Frequency
@ fX = 4.19 MHz Operation @ fX = 5.0 MHz Operation
fX/26
fX/27
fX/28
1
1
0
0
1
1
0
1
0
1
256 Hz
128 Hz
64 Hz
305.2 Hz
152.6 Hz
76.3 Hz
fXT (32.768 kHz)
128 Hz
(3) LCD boost voltage level setting register 00 (VLCD00)
This register is used to set the voltage level of the LCD controller/driver booster.
VLCD00 is set with an 8-bit memory manipulation instruction.
RESET input clears VLCD00 to 00H.
Figure 14-4. Format of LCD Boost Voltage Level Setting Register 00
Symbol
7
0
6
0
5
4
3
2
1
0
Address After reset
R/W
R/W
VLCD00
0
0
VLCD003 VLCD002 VLCD001 VLCD000 FFB3H 00H
VLCD003 VLCD002 VLCD001 VLCD000 Voltage level selection for LCD display
VLC0 voltage (TYP.) (V)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Voltage level 0 (light)
Voltage level 1
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Voltage level 2
Voltage level 3
Voltage level 4
Voltage level 5
Voltage level 6
Voltage level 7 (medium)
Voltage level 8
Voltage level 9
Voltage level 10
Voltage level 11
Voltage level 12
Voltage level 13
Voltage level 14
Voltage level 15 (dark)
Remark The above values are when no external LCD load is connected.
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.4 Common and Segment Signals
The LCD0 to LCD95 pins serve as common signal and segment signals. The assignment of the LCD pins differs
depending on the display mode.
Table 14-6 shows the assignment of the LCD0 to LCD95 pins in each display mode.
Table 14-6. Assignment of LCD0 to LCD95 Pins in Each Display Mode (1/3)
Pin No. Pin Name
LCD Display Mode
48×48 Mode
64×32 Mode
80×16 Mode
80×8Mode
(LCDM200, 201 = 00B)
(LCDM200, 201 = 10B)
(LCDM200, 201 = 01B)
(LCDM200, 201 = 11B)
1
LCD71
LCD70
LCD69
LCD68
LCD67
LCD66
LCD65
LCD64
LCD63
LCD62
LCD61
LCD60
LCD59
LCD58
LCD57
LCD56
LCD55
LCD54
LCD53
LCD52
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
S39
S55
S63
2
S38
S54
S62
3
S37
S53
S61
4
S36
S52
S60
5
S35
S51
S59
6
S34
S50
S58
7
S33
S49
S57
8
S32
S48
S56
9
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
S47
S55
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
S46
S54
S45
S53
S44
S52
S43
S51
S42
S50
S41
S49
S40
S48
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
S39
S47
S46
S45
S44
S43
S42
S41
S40
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
S39
COM8
COM7
COM6
S38
S38
COM5
S37
S37
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-6. Assignment of LCD0 to LCD95 Pins in Each Display Mode (2/3)
Pin No. Pin Name
LCD Display Mode
48×48 Mode
64×32 Mode
80×16 Mode
80×8 Mode
(LCDM200, 201 = 00B)
(LCDM200, 201 = 10B)
(LCDM200, 201 = 01B)
(LCDM200, 201 = 11B)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
121
122
123
124
125
LCD36
LCD35
LCD34
LCD33
LCD32
LCD31
LCD30
LCD29
LCD28
LCD27
LCD26
LCD25
LCD24
LCD23
LCD22
LCD21
LCD20
LCD19
LCD18
LCD17
LCD16
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
LCD9
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
S23
COM4
COM3
COM2
COM1
COM0
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
LCD8
S8
S8
S8
S8
LCD7
S7
S7
S7
S7
LCD6
S6
S6
S6
S6
LCD5
S5
S5
S5
S5
LCD4
S4
S4
S4
S4
LCD3
S3
S3
S3
S3
LCD2
S2
S2
S2
S2
LCD1
S1
S1
S1
S1
LCD0
S0
S0
S0
S0
LCD95
LCD94
LCD93
LCD92
LCD91
S47
S63
S62
S61
S60
S59
S79
S78
S77
S76
S75
P87
P86
P85
P84
P83
S46
S45
S44
S43
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-6. Assignment of LCD0 to LCD95 Pins in Each Display Mode (3/3)
Pin No. Pin Name
LCD Display Mode
48×48 Mode
64×32 Mode
80×16 Mode
80×8 Mode
(LCDM200, 201 = 00B)
(LCDM200, 201 = 10B)
(LCDM200, 201 = 01B)
(LCDM200, 201 = 11B)
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
LCD90
LCD89
LCD88
LCD87
LCD86
LCD85
LCD84
LCD83
LCD82
LCD81
LCD80
LCD79
LCD78
LCD77
LCD76
LCD75
LCD74
LCD73
LCD72
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
P82
P81
P80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.5 Setting LCD Controller/Driver
Set the LCD controller/driver as follows.
Note that, before changing the LCD clock or boost voltage level, be sure to turn off the display and stop boosting
the voltage.
14.5.1 Setting to start display
<1> Input initial data to the LCD display data memories (F8C0H to F9DFH, F9E0H to FAFFH).
<2> Select the LCD source clock by using the LCD20 clock control register (LCDC20).
<3> Select a boost voltage level by using LCD boost voltage level setting register 00 (VLCD00).
<4> Enable boosting voltage by setting bit 5 of LCD display mode register 20 (LCDM20) (VAON20 = 1).
<5> Wait for 500 ms or more after setting VAON20.
<6> Output the non-selected potential by setting bit 4 of LCDM20 (LIPS20 = 1).
<7> Turn on the display by using bits 6 and 7 (LCDON200 and LCDON201) of LCDM20, and start producing the
output corresponding to each data memory.
14.5.2 Setting to turn off display and stop boosting voltage
<1> Turn off the display by clearing bits 6 and 7 (LCDON200 = 0 and LCDON201 = 0) of LCDM0.
<2> Disable output of all the segment buffers and common buffers by clearing bit 4 (LIPS20 = 0) of LCDM0.
<3> Stop boosting voltage by clearing bit 5 (VAON20 = 0) of LCDM0.
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.6 LCD Display Data Memory
The LCD display data memory is mapped at F8C0H to F9DFH (pattern A) and F9E0H to FAFFH (pattern B). When
the LCD display data memory is not used for LCD display, it can be used as a normal RAM.
Figure 14-5 shows the assignment of the LCD display data memory in each display mode, and Table 14-7 shows
the relationship between the LCD display data memory and segment/common output.
Figure 14-5. Assignment of LCD Display Data Memory in Each Display Mode
FFFFH
Special function registers
(SFRs)
FF00H
FEFFH
Internal high-speed RAM
FB00H
FAFFH
FAE0H
FADFH
FA80H
FA7FH
Pattern B
FA30H
FA2FH
48 × 48 64 × 32 80 × 16 80 × 8
F9E0H
F9DFH
F9C0H
F9BFH
F960H
F95FH
Pattern A
F910H
F90FH
48 × 48 64 × 32 80 × 16 80 × 8
F8C0H
F8BFH
Internal low-speed RAM
Reserved
Mask ROM/
flash memory
0000H
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (1/7)
(i) Display mode: 48 × 48 mode, address: Pattern A (F8C0H to F9DFH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S47
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F8C0H
S0
F8C6H
S1
F8CDH
S2
F8D3H
S3
• • •
• • •
F9DAH
S47
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F8C1H
F8C7H
F8CEH
F8D4H
• • •
F9DBH
•
•
•
•
S0
S1
S2
S3
• • •
S47
b0
b1
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
b2
b3
b4
b5
b6
b7
Address
F8C5H
F8CCH
F8D2H
F8D8H
• • •
F9DFH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (2/7)
(ii) Display mode: 48 × 48 mode, address: Pattern B (F9E0H to FAFFH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S47
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F9E0H
S0
F9E6H
S1
F9EDH
S2
F9F3H
S3
• • •
• • •
FAFAH
S47
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F9E1H
F9E7H
F9EEH
F9F4H
• • •
FAFBH
•
•
•
•
S0
S1
S2
S3
• • •
S47
b0
b1
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
b2
b3
b4
b5
b6
b7
Address
F9E5H
F9ECH
F9F2H
F9F8H
• • •
FAFFH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (3/7)
(iii) Display mode: 64 × 32 mode, address: Pattern A (F8C0H to F9BFH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S63
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F8C0H
S0
F8C4H
S1
F8C8H
S2
F8CCH
S3
• • •
• • •
F9BCH
S63
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F8C1H
F8C5H
F8C9H
F8CDH
• • •
F9BDH
•
•
•
•
S0
S1
S2
S3
• • •
S63
b0
b1
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
b2
b3
b4
b5
b6
b7
Address
F8C3H
F8C7H
F8CBH
F8CFH
• • •
F9BFH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (4/7)
(iv) Display mode: 64 × 32 mode, address: Pattern B (F9E0H to FADFH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S63
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F9E0H
S0
F9E4H
S1
F9E8H
S2
F9ECH
S3
• • •
• • •
FADCH
S63
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F9E1H
F9E5H
F9E9H
F9EDH
• • •
FADDH
•
•
•
•
S0
S1
S2
S3
• • •
S63
b0
b1
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
b2
b3
b4
b5
b6
b7
Address
F9E3H
F9E7H
F9EBH
F9EFH
• • •
FADFH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (5/7)
(v) Display mode: 80 × 16 mode, address: Pattern A (F8C0H to F95FH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S79
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F8C0H
S0
F8C2H
S1
F8C4H
S2
F8C6H
S3
• • •
• • •
F95EH
S79
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F8C1H
F8C3H
F8C5H
F8C7H
• • •
F95FH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (6/7)
(vi) Display mode: 80 × 16 mode, address: Pattern B (F9E0H to FA7FH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S79
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F9E0H
S0
F9E2H
S1
F9E4H
S2
F9E6H
S3
• • •
• • •
FA7EH
S79
b0
b1
COM8
COM9
b2
COM10
COM11
COM12
COM13
COM14
COM15
b3
b4
b5
b6
b7
Address
F9E1H
F9E3H
F9E5H
F9E7H
• • •
FA7FH
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CHAPTER 14 LCD CONTROLLER/DRIVER
Table 14-7. Relationship Between LCD Display Data Memory and Segment/Common Output (7/7)
(vii) Display mode: 80 × 8 mode, address: Pattern A (F8C0H to F90FH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S79
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F8C0H
F8C1H
F8C2H
F8C3H
• • •
F90FH
(viii) Display mode: 80 × 8 mode, address: Pattern B (F9E0H to FA2FH)
Bit
Segment Pin
Common Pin
S0
S1
S2
S3
• • •
S79
b0
b1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
b2
b3
b4
b5
b6
b7
Address
F9E0H
F9E1H
F9E2H
F9E3H
• • •
FA2FH
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.7 Display Modes
14.7.1 80 × 8 mode (1/8 duty)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
G G G G G G G G G G G G G G G
G G G G G G G G G G G G G G G G G
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
0
1
2
3
4
5 6 7 8 9 10 11 12 13 14
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-6. LCD Drive Waveform Examples (1/8 Duty)
<Display example>
1 frame
0
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
COM1
COM2
V
SS
VLC0
VLC1
VLC2
VLC3
VLC4
S
E
S
E
S
E
S
E
S
E
G G G G G
0
1 2 3 4
V
SS
VLC0
VLC1
VLC2
VLC3
VLC4
VSS
•
•
•
•
•
•
•
•
•
•
•
•
VLC0
VLC1
VLC2
VLC3
VLC4
COM7
VSS
VLC0
VLC1
VLC2
VLC3
VLC4
SEG0
VSS
VLC0
VLC1
VLC2
VLC3
VLC4
SEG1
VSS
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.7.2 80 × 16 mode (1/16 duty)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-7. LCD Drive Waveform Examples (1/16 Duty)
<Display example>
1 frame
0
1
2
3
4
• • • 14 15 0
1 2 3 4 • • • 14 15
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM0
COM1
COM2
V
SS
VLC0
VLC1
VLC2
VLC3
VLC4
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
S
E
S
E
S
E
S
E
S
E
G G G G G
0
1 2 3 4
V
SS
•
•
•
•
•
•
•
•
•
•
•
•
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM15
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
SEG0
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
SEG1
V
SS
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CHAPTER 14 LCD CONTROLLER/DRIVER
14.7.3 64 × 32 mode (1/32 duty)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
G G G G G G G G G G G G G G G G
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
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CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-8. LCD Drive Waveform Examples (1/32 Duty)
<Display example>
1 frame
0
1
2
3
4
• • • 30 31 0
1 2 3 4 • • • 30 31
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM0
COM1
COM2
COM0
COM1
COM2
COM3
COM4
V
SS
COM5
COM6
VLC0
VLC1
VLC2
VLC3
VLC4
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
V
SS
•
•
•
•
•
•
•
•
•
•
•
•
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM31
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
S
E
S
E
S
E
S
E
S
E
SEG0
G G G G G
0
1 2 3 4
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
SEG1
V
SS
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User’s Manual U15559EJ2V1UD
CHAPTER 14 LCD CONTROLLER/DRIVER
14.7.4 48 × 48 mode (1/48 duty)
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
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User’s Manual U15559EJ2V1UD
CHAPTER 14 LCD CONTROLLER/DRIVER
Figure 14-9. LCD Drive Waveform Examples (1/48 Duty)
<Display example>
1 frame
0
1
2
3
4
• • • 46 47 0
1 2 3 4 • • • 46 47
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM0
COM1
COM2
COM0
COM1
COM2
COM3
COM4
V
SS
COM5
COM6
VLC0
VLC1
VLC2
VLC3
VLC4
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
V
SS
•
•
•
•
•
•
•
•
•
•
•
•
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
COM47
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
SEG0
V
SS
V
V
V
V
V
LC0
LC1
LC2
LC3
LC4
SEG1
V
SS
S
E
S
E
S
E
S
E
S
E
G G G G G
0
1 2 3 4
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User’s Manual U15559EJ2V1UD
CHAPTER 14 LCD CONTROLLER/DRIVER
14.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2, VLC3, and VLC4
The µPD789835, 789835A, and 789835B Subseries each have an on-chip booster (which increases the voltage
only five-fold) to supply power for driving the LCD.
The internal LCD reference voltage is output from VLC4. The VLC3 pin outputs a voltage two times that of VLC4. The
VLC2 pin outputs a voltage three times that of VLC4. The VLC1 pin outputs a voltage four times, and the VLC0 pin outputs
a voltage five times that of VLC4.
An LCD display voltage (VLC0) can be selected by using LCD boost voltage level setting register 00 (VLCD00).
The µPD789835, 789835A, and 789835B Subseries require an external capacitor (recommended capacitance:
0.47 µF) because they use a capacitance division system to generate the power to drive the LCD.
Table 14-8. Output Voltage of VLC0 to VLC4 Pins
Power Supply Pin for Driving LCD
Pin Voltage
Example: When VLCD00 = 08H
4.5 V
VLC0
5VLC4
4VLC4
3VLC4
2VLC4
VLC4
VLC1
3.6 V
2.7 V
1.8 V
0.9 V
VLC2
VLC3
VLC4 (LCD reference voltage)
Cautions 1. Do not leave the VLC0 to VLC4 pins open when using the LCD function. For a connection
example, see Figure 14-10.
2. The LCD driving power supply can always supply a constant voltage, regardless of changes
in VDD, because it is separated from the power supply of the device.
Figure 14-10. Example of Connecting LCD Driver Pins
VLC0
VLC1
VLC2
VLC3
VLC4
C4
C5
C6
C7
C8
CAP0
CAP1
CAP2
CAP3
C1
C2
C3
µ
C1 = C2 = C3 = C4 = C5 = C6 = C7 = C8 = 0.47
External pin
F
Remark Use a capacitor with as little leakage as possible.
Use non-polarity capacitors as C1 to C3.
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User’s Manual U15559EJ2V1UD
CHAPTER 15 MULTIPLIER
15.1 Multiplier Function
The multiplier has the following function.
• Calculation of 8 bits × 8 bits = 16 bits
15.2 Multiplier Configuration
(1) 16-bit multiplication result storage register 0 (MUL0)
This register stores the 16-bit result of multiplication.
This register holds the result of multiplication after 16 CPU clocks have elapsed.
MUL0 is set with a 16-bit memory manipulation instruction.
RESET input makes MUL0 undefined.
Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can
also be manipulated with an 8-bit memory manipulation instruction. When using an 8-bit
memory manipulation instruction, however, access the register by means of direct
addressing.
(2) Multiplication data registers A and B (MRA0 and MRB0)
These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0.
MRA0 and MRB0 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input makes MRA0 and MRB0 undefined.
Figure 15-1 shows the block diagram of the multiplier.
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User’s Manual U15559EJ2V1UD
CHAPTER 15 MULTIPLIER
Figure 15-1. Block Diagram of Multiplier
Internal bus
Multiplication data
register A (MRA0)
Multiplication data
register B (MRB0)
Counter value
CPU clock
Selector
3-bit counter
Start Clear
3
16-bit
adder
16-bit multiplication result
storage register 0 (master) (MUL0)
16-bit multiplication result
storage register 0 (slave)
Reset
MULST0
Multiplier control
register 0 (MULC0)
Internal bus
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User’s Manual U15559EJ2V1UD
CHAPTER 15 MULTIPLIER
15.3 Register Controlling Multiplier
The multiplier is controlled by the following register.
• Multiplier control register 0 (MULC0)
(1) Multiplier control register 0 (MULC0)
MULC0 indicates the operating status of the multiplier after operation, as well as controls the multiplier.
MULC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears MULC0 to 00H.
Figure 15-2. Format of Multiplier Control Register 0
Symbol
MULC0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FFD2H
After reset
00H
R/W
R/W
MULST0
MULST0
Multiplier operation start control bit
Operating status of multiplier
Operation stops
Operation in progress
0
1
Stops operation after resetting counter to 0.
Enables operation
Caution Be sure to clear bits 1 to 7 to 0.
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User’s Manual U15559EJ2V1UD
CHAPTER 15 MULTIPLIER
15.4 Multiplier Operation
The multiplier of the µPD789835, 789835A, 789835B Subseries can execute the calculation of 8 bits × 8 bits = 16
bits. Figure 15-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.
<1> Counting is started by setting MULST0.
<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value
is incremented by one.
<3> If MULST0 is cleared when the counter value is 111B, the operation is stopped. At this time, MUL0 holds the
data.
<4> While MULST0 is low, the counter and slave are cleared.
Figure 15-3. Multiplier Operation Timing (Example of AAH × D3H)
CPU clock
MRA0
MRB0
AA
D3
MULST0
Counter
000B
001B 010B 011B 100B 101B 110B 111B
0154 0000 0000 0AA0 0000 2A80 5500
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
00AA 01FE 01FE 01FE 0C9E 0C9E 371E
000B
00AA
00AA
Selector output
MUL0
(Master)
8C1E
0000
0000
(Slave)
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User’s Manual U15559EJ2V1UD
CHAPTER 16 SWAPPING (SWAP)
16.1 Function of SWAP
The µPD789835, 789835A, and 789835B Subseries can swap the contents of the higher 4 bits of byte data with
the contents of the lower 4 bits by using swapping function register 0 (SWP0). As a result, conversion equivalent to
four times of shift operation can be performed with fewer instructions. Figure 16-1 shows an example of swapping
execution.
Figure 16-1. Example of Swapping
7
6
3
2
5
4
1
0
During write
SWAP00
SWAP07 SWAP06 SWAP05
SWAP02 SWAP01
SWAP04 SWAP03
7
6
3
2
SWAP06
5
4
1
0
SWAP03
SWAP02
SWAP07
SWAP00
During read
SWAP01
SWAP05 SWAP04
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CHAPTER 16 SWAPPING (SWAP)
16.2 Configuration of SWAP
SWAP consists of the following hardware.
Table 16-1. SWAP Configuration
Item
Configuration
Register
Swapping function register 0 (SWP0)
Figure 16-2. SWAP Block Diagram
SWAP04 to SWAP07
SWAP00 to SWAP03
Internal bus (L)
Internal bus (H)
(1) Swapping function register 0 (SWP0)
By writing data to SWP0 and subsequently reading it back, the contents of the higher four bits and the lower
four bits can be swapped.
SWP0 is set with an 8-bit memory manipulation instruction.
In write mode, RESET input makes SWP0 undefined.
In read mode, RESET input clears SWP0 to 00H.
16.3 Example of Executing SWAP
An example where four shift operations are used to swap the contents of the higher bits with those of the lower bits,
and an example where SWAP is used are shown below. By using the SWAP function, the contents of the higher bits
and those of the lower bits can be swapped with fewer instruction clocks.
<Example of shifting byte data four times>
MOV A, #byte
ROR A, 1
ROR A, 1
ROR A, 1
ROR A, 1
;
;
;
;
;
← 6 clocks
← 2 clocks
← 2 clocks
← 2 clocks
← 2 clocks
Total: 14 clocks
Total: 10 clocks
<Example of using SWAP>
MOV SWP0, #byte
MOV A, SWP0
;
;
← 6 clocks
← 4 clocks
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CHAPTER 17 INTERRUPT FUNCTIONS
17.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2) Maskable interrupt
This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 17-1.
A standby release signal is generated.
5 external and 15 internal interrupt sources are incorporated as maskable interrupts.
17.2 Interrupt Sources and Configuration
A total of 21 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table 17-1).
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Table 17-1. Interrupt Source List
Interrupt
Type
PriorityNote 1
Interrupt Source
Trigger
Internal/
External
Vector
Table
Basic
Configuration
TypeNote 2
Name
Address
Non-
–
0
INTWDT0
Watchdog timer overflow (with watchdog timer
mode 1 selected)
Internal
0002H
(A)
(B)
(C)
maskable
Maskable
INTWDT1
Watchdog timer overflow (with interval timer mode
selected)
0004H
1
2
3
INTP0
Pin input edge detection
External
Internal
0006H
0008H
000AH
INTP1
INTCSI10
End of 3-wire serial I/O (SIO10) transmission/
reception
(B)
4
INTSER00
Occurrence of asynchronous serial interface
(UART00) receive error
000CH
5
6
INTSR00
INTST00
INTTM50
INTTM51
INTTM52
INTWT
End of UART00 reception
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
End of UART00 transmission
RIN pin input rising edge detection
RIN pin input falling edge detection
8-bit remote control timer 50 overflow signal
Watch timer interrupt
7
External
Internal
(D)
(B)
8
9
10
11
12
INTWTI
Watch timer interval timer interrupt
INTTM80
Generation of match signal of 8-bit timer/event
counter 80
13
14
15
16
17
18
19
INTTM81
INTTM82
INTTM30
INTTM40
Generation of match signal of 8-bit timer 81
Generation of match signal of 8-bit timer 82
Generation of match signal of 8-bit timer 30
Generation of match signal of 8-bit timer 40
001EH
0020H
0022H
0024H
0026H
0028H
002AH
INTTMSG0 Generation of match signal of 8-bit timer SG0
INTAD
A/D conversion completion signal
Key return signal detection
INTKR00
External
(C)
Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same
time. 0 is the highest priority and 19 is the lowest.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
Remark There are two interrupt sources for the watchdog timer: a non-maskable interrupt (INTWDT0) and a
maskable interrupt (internal) (INTWDT1). Either one (but not both) should be selected for actual use.
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Figure 17-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generator
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
IE
MK
Vector table
address generator
Interrupt request
IF
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, KRM00
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
INTP0:
External interrupt mode register 0
KRM00: Key return mode register 00
IF:
Interrupt request flag
Interrupt enable flag
Interrupt mask flag
IE:
MK:
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(D) External maskable interrupt (INTTM50, INTTM51)
Internal bus
MK
IE
Vector table
address generator
Interrupt
request
Edge
detector
IF
Standby
release signal
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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CHAPTER 17 INTERRUPT FUNCTIONS
17.3 Registers Controlling Interrupt Function
The following five types of registers are used to control the interrupt functions.
• Interrupt request flag registers 0 to 2 (IF0 to IF2)
• Interrupt mask flag registers 0 to 2 (MK0 to MK2)
• External interrupt mode register 0 (INTM0)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 17-2 lists the interrupt request flag and interrupt mask flag names corresponding to the interrupt requests.
Table 17-2. Flags Corresponding to Interrupt Request Signal Name
Interrupt Request Signal Name
INTWDT1
Interrupt Request Flag
Interrupt Mask Flag
WDTIF1
PIF0
WDTMK1
PMK0
INTP0
INTP1
PIF1
PMK1
INTCSI10
INTSER00
INTSR00
INTST00
INTWT
CSIIF10
SERIF00
SRIF00
STIF00
WTIF
CSIMK10
SERMK00
SRMK00
STMK00
WTMK
INTWTI
WTIIF
WTIMK
INTTM50
INTTM51
INTTM52
INTTM80
INTTM81
INTTM82
INTTM30
INTTM40
INTTMSG0
INTAD
TMIF50
TMIF51
TMIF52
TMIF80
TMIF81
TMIF82
TMIF30
TMIF40
TMMK50
TMMK51
TMMK52
TMMK80
TMMK81
TMMK82
TMMK30
TMMK40
TMMKSG0
ADMK
TMIFSG0
ADIF
INTKR00
KRIF00
KRMK00
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(1) Interrupt request flag registers 0 to 2 (IF0 to IF2)
An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an
instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal
is input, or when an instruction is executed.
IF0 to IF2 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 to IF2 to 00H.
Figure 17-2. Format of Interrupt Request Flag Registers
Symbol
IF0
<7>
TMIF50
<7>
<6>
STIF00
<6>
<5>
<4>
<3>
<2>
PIF1
<2>
<1>
PIF0
<1>
<0>
WDTIF1
<0>
Address After reset
R/W
R/W
SRIF00 SERIF00 CSIIF10
FFE0H
FFE1H
FFE2H
00H
00H
00H
<5>
<4>
<3>
WTIIF
<3>
IF1
IF2
TMIF30
7
TMIF82
6
TMIF81
TMIF80
WTIF
<2>
TMIF52
<1>
TMIF51
<0>
R/W
R/W
5
0
4
0
0
0
KRIF00
ADIF
TMIFSG0 TMIF40
××IF×
Interrupt request flag
0
1
Interrupt request signal not generated
Interrupt request signal generated, interrupt request status entered
Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as an interval
timer. If watchdog timer mode 1 or 2 is used, clear the WDTIF flag to 0.
2. Since port 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the corresponding interrupt mask flag should be set to 1 before
using the output mode.
3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared
before entering the interrupt routine.
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(2) Interrupt mask flag registers 0 to 2 (MK0 to MK2)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing.
MK0 to MK2 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 to MK2 to FFH.
Figure 17-3. Format of Interrupt Mask Flag Registers
Symbol
MK0 TMMK50 STMK00 SRMK00 SERMK00 CSIMK10 PMK1
<7> <6> <5> <4> <3> <2>
MK1 TMMK30 TMMK82 TMMK81 TMMK80 WTIMK WTMK TMMK52 TMMK51 FFE5H
<2> <1> <0>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
PMK0 WDTMK1 FFE4H
<1> <0>
<0>
Address After reset
R/W
R/W
FFH
FFH
FFH
R/W
R/W
7
1
6
1
5
1
4
1
<3>
MK2
KRMK00
ADMK TMMKSG0 TMMK40 FFE6H
××MK×
Interrupt servicing control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Cautions 1. If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 or
2, its value becomes undefined.
2. Since port 2 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the corresponding interrupt mask flag should be set to 1 before
using the output mode.
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(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 and INTP1.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 17-4. Format of External Interrupt Mode Register 0
Symbol
INTM0
7
0
6
0
5
4
3
2
1
0
0
0
Address After reset
FFECH 00H
R/W
R/W
ES11
ES10
ES01
ES00
ES11
ES10
Selection of INTP1 valid edge
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES01
ES00
Selection of INTP0 valid edge
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Cautions 1. Be sure to clear bits 0, 1, 6, and 7 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag to
1 to disable interrupts.
Afterward, clear the interrupt request flag to 0, then clear the interrupt mask flag to 0 to
enable interrupts.
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(4) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped in the PSW.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved
into a stack, and the IE flag is reset to 0.
RESET input sets the PSW to 02H.
Figure 17-5. Configuration of Program Status Word
After reset
02H
7
6
Z
5
0
4
3
0
2
0
1
1
0
Symbol
PSW
IE
AC
CY
Used when normal instruction is executed
IE
0
Interrupt acknowledgment enabled/disabled
Disabled
Enabled
1
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(5) Key return mode register 00 (KRM00)
This register sets the pin that is used to detect the key return signal (falling edge of port 0).
KRM00 is set with an 8-bit memory manipulation instruction.
RESET input clears KRM00 to 00H.
Figure 17-6. Format of Key Return Mode Register 00
Symbol
7
6
5
4
3
0
2
0
1
0
0
Address After reset
FFF5H 00H
R/W
R/W
KRM00 KRM007 KRM006 KRM005 KRM004
KRM000
KRM000
Control of key return signal detection (P00 to P03)
0
1
Key return signal not detected
Key return signal detected (P00 to P03 falling edge detection)
KRM00n
Control of key return signal detection (P0n)
0
1
Key return signal not detected
Key return signal detected (P0n falling edge detection)
Remark n = 4 to 7
Cautions 1. Be sure to clear bits 1 to 3 to 0.
2. Before setting KRM00, set (1) bit 7 (KRMK00) of MK0 to disable interrupts. After KRM00
is set, clear (0) KRMK00 after clearing (0) bit 7 (KRIF00) of IF0 to enable interrupts.
3. On-chip pull-up resistors are automatically connected in the input mode to the pins
specified for key return signal detection (P00 to P07). Although these resistors are
disconnected when the mode changes to output, key return signal detection continues
unchanged.
4. A key return signal cannot be detected while any one of the pins specified for key return
detection is low level even when a falling edge occurs at another pin.
Figure 17-7. Block Diagram of Key Return Signal Detector
Key return mode register 00
(KRM00)
P00/KR00
P01/KR01
P02/KR02
P03/KR03
Falling edge detector
KRMK00
INTKR00
P04/KR04
P05/KR05
P06/KR06
P07/KR07
Standby release
signal
Note For selecting the pin to be used as the falling edge input.
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17.4 Interrupt Servicing Operation
17.4.1 Non-maskable interrupt request acknowledgment operation
A non-maskable interrupt request is acknowledged unconditionally even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When a non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 17-8 shows the flow from non-maskable interrupt request generation to acknowledgment, Figure 17-9 shows
the timing of non-maskable interrupt acknowledgment, and Figure 17-10 shows the acknowledgment operation when
multiple non-maskable interrupts are generated.
Caution During non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; otherwise, the service program will be interrupted and the new non-maskable
interrupt request will be acknowledged.
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Figure 17-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment
Start
WDTM4 = 1
No
(watchdog timer mode
is selected)
Interval timer
Yes
No
No
WDT
overflows
Yes
WDTM3 = 0
(non-maskable interrupt
is selected)
Reset processing
Yes
Interrupt request is generated
Interrupt servicing starts
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 17-9. Timing of Non-Maskable Interrupt Request Acknowledgment
Saving PSW and PC, and
jump to interrupt servicing
CPU processing
WDTIF
Instruction
Instruction
Interrupt servicing program
Figure 17-10. Non-Maskable Interrupt Request Acknowledgment
Main routine
First interrupt servicing
NMI request
(second)
NMI request
(first)
Second interrupt servicing
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17.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 17-3.
See Figures 17-12 and 17-13 for the timing of interrupt request acknowledgment.
Table 17-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time
Maximum TimeNote
19 clocks
9 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
the BT or BF instruction.
1
Remark 1 clock:
(fCPU: CPU clock)
fCPU
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
A pending interrupt is acknowledged when the status in which it can be acknowledged is set.
Figure 17-11 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and
execution branches.
To return from interrupt servicing, use the RETI instruction.
Figure 17-11. Interrupt Request Acknowledgment Program Algorithm
Start
No
xxIF = 1?
Yes (Interrupt request generated)
No
xxMK = 0?
Yes
Interrupt request pending
Interrupt request pending
No
IE = 1?
Yes
Vectored interrupt
servicing
xxIF: Interrupt request flag
xxMK: Interrupt mask flag
IE:
Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
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Figure 17-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
8 clocks
Clock
Saving PSW and PC, and
jump to interrupt servicing
MOV A, r
Interrupt servicing program
CPU
Interrupt
If the interrupt request has generated an interrupt request flag (xxIF) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 17-12 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 17-13. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
8 clocks
Clock
Interrupt servicing
program
Saving PSW and PC, and
jump to interrupt servicing
NOP
MOV A, r
CPU
Interrupt
If the interrupt request flag (xxIF) is generated in the final clock of the instruction, interrupt request acknowledgment
processing will begin after execution of the next instruction is complete.
Figure 17-13 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be serviced after execution of MOV A, r, which follows NOP, is
complete.
Caution When interrupt request flag registers 0 to 2 (IF0 to IF2) or interrupt mask flag registers 0 to 2
(MK0 to MK2) are being accessed, interrupt requests will be held pending.
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17.4.3 Multiple interrupt servicing
Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced,
can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the
order of the priority assigned to each interrupt request in advance (see Table 17-1).
Figure 17-14. Example of Multiple Interrupts
Example 1. Acknowledging multiple interrupts
INTxx servicing
INTyy servicing
Main servicing
IE = 0
IE = 0
EI
EI
INTxx
INTyy
RETI
RETI
The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are
performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is
enabled.
Example 2. Multiple interrupts are not performed because interrupts are disabled
INTxx servicing
INTyy servicing
Main servicing
EI
IE = 0
INTyy is held pending
INTyy
RETI
INTxx
IE = 0
RETI
Because interrupt requests are disabled (the EI instruction has not been issued) in interrupt INTxx servicing, the
interrupt request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and is
acknowledged after INTxx servicing is completed.
IE = 0: Interrupt requests disabled
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17.4.4 Putting interrupt requests on hold
If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type
of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed.
These instructions (interrupt request pending instructions) are as follows.
• Instructions that manipulate interrupt request flag registers 0 to 2 (IF0 to IF2)
• Instructions that manipulate interrupt mask flag registers 0 to 2 (MK0 to MK2)
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CHAPTER 18 STANDBY FUNCTION
18.1 Standby Function and Configuration
18.1.1 Standby function
The standby function is used to reduce the power consumption of the system and can be effected in the following
two modes.
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption
as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this
mode.
The data memory can be retained at a low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining
the contents of the data memory at an extremely low current.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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18.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time selection register (OSTS) (only when ceramic/crystal oscillation is selected)
• Power supply control register 0 (PSC0)
(1) Oscillation stabilization time selection register (OSTS) (only when ceramic/crystal oscillation is
selected)
The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled
with the oscillation stabilization time selection register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H.
Note that the time required for oscillation to stabilize after RESET input is 215/fX, and does not depend on
OSTS.
Caution When RC oscillation is selected, the oscillation stabilization time cannot be selected using
OSTS.
In the case of RC oscillation, the oscillation stabilization time is fixed to 27/fCC.
Figure 18-1. Format of Oscillation Stabilization Time Selection Register
Symbol
OSTS
7
0
6
0
5
0
4
0
3
0
2
1
0
Address After reset
FFFAH 04H
R/W
R/W
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
0
0
1
0
1
0
0
0
0
212/fX (819 µs)
215/fX (6.55 ms)
217/fX (26.2 ms)
Setting prohibited
Other than above
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of whether STOP
mode is released by RESET input or by interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. The parenthesized values apply to operation at fX = 5.0 MHz.
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(2) Power supply control register 0 (PSC0)
This register is used to switch the power supply to the subsystem clock oscillator. By setting the power supply
of the subsystem clock oscillator to VROUT0, the power consumption can be reduced.
PSC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PSC0 to 00H.
Figure 18-2. Format of Power Supply Control Register 0
Symbol
PSC0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
<0>
Address
FFAFH
After reset
00H
R/W
R/W
PSC00
PSC00
Selection of power supply to subsystem clock oscillator
0
1
VDD
VROUT0 (1.4 V TYP.)
Caution Be sure to clear bits 1 to 7 to 0.
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18.2 Standby Function Operation
18.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation statuses in the HALT mode are shown in the following table.
Table 18-1. Operation Statuses in HALT Mode
Item
Operation Status in HALT Mode Set While Main Operation Status in HALT Mode Set While
System Clock Is Operating Subsystem Clock Is Operating
Subsystem Clock
Operating
Subsystem Clock
Stopped
Main System Clock
Operating
Main System Clock
Stopped
Main system clock
CPU
Oscillation enabled
Operation stopped
Oscillation stopped
Port (output latch)
Status prior to setting HALT mode is retained
8-bit timer/event counter 80 Operation enabled
Operation enabledNote 1
Operation enabledNote 3
Operation enabledNote 3
Operation stopped
8-bit timer 81
8-bit timer 82
8-bit timer 30
8-bit timer 40
Operation enabled
Operation enabled
Operation enabled
Operation enabledNote 2
Operation enabledNote 2
Operation enabled
Operation enabled
8-bit remote control timer 50 Operation stopped
Sound generator
Watch timer
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation stopped
Operation enabled
Operation enabledNote 4
Operation enabledNote 2
Operation enabledNote 2
Operation enabledNote 2
Operation enabled
Operation enabled
Operation enabled
Operation enabledNote 3
Operation enabledNote 3
Operation enabledNote 3
Operation enabledNote 1
Operation stopped
Watchdog timer
Serial interface
SIO
UART
A/D converter
LCD controller/driver
External interrupt
Operation enabledNote 2
Operation enabled
Operation enabledNote 3
Notes 1. Operation is enabled only when an external clock has been selected.
2. Operation is enabled when the main system clock has been selected.
3. Operation is enabled when the subsystem clock has been selected.
4. Non-masked maskable interrupt
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(2) Releasing HALT mode
The HALT mode can be released by the following three sources.
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to
be acknowledged, vectored interrupt servicing is performed. If interrupts are disabled, the instruction at
the next address is executed.
Figure 18-3. Releasing HALT Mode by Interrupt
HALT
instruction
Wait
Wait
Standby
release signal
Operation
mode
HALT mode
Operation mode
Oscillation
Clock
Remarks 1. The broken line indicates the case where the interrupt request that has released the
standby mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is performed:
9 to 10 clocks
• When vectored interrupt servicing is not performed: 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether interrupts are enabled or disabled, and vectored
interrupt servicing is performed.
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(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address in
the same manner as the ordinary reset operation, and program execution is started.
Figure 18-4. Releasing HALT Mode by RESET Input
HALT
instruction
WaitNote
RESET
signal
Oscillation
Reset
period
stabilization
wait status
Operation
mode
Operation
mode
HALT mode
Oscillation
Oscillation
stops
Oscillation
Clock
Note The wait time differs depending on the main system clock selected.
When ceramic/crystal oscillation is selected: 215/fX (6.55 ms)
When RC oscillation is selected:
27/fCC (64 µs)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. The parenthesized values apply to operation at fX = 5.0 MHz or fCC = 2.0 MHz.
Table 18-2. Operation After Releasing HALT Mode
Releasing Source
MK××
IE
0
Operation
Executes next address instruction
Executes interrupt servicing
Retains HALT mode
Maskable interrupt request
0
0
1
1
×
Non-maskable interrupt request
RESET input
−
×
Executes interrupt servicing
Reset processing
-−-
−
×: don’t care
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18.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby mode
is released as soon as it is set if there is an interrupt source whose interrupt request flag is
set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode
is set immediately after the STOP instruction has been executed, the wait time set by the
oscillation stabilization time selection register (OSTS) elapses, and then an operation mode
is set.
The operation statuses in the STOP mode are shown in the following table.
Table 18-3. Operation Statuses in STOP Mode
Item
Operation Status in STOP Mode
Subsystem Clock Operating Subsystem Clock Stopped
Oscillation stopped
Operation stopped
Main system clock
CPU
Port (output latch)
8-bit timer/event counter 80
8-bit timer 81
Status prior to setting STOP mode is retained
Operation enabledNote 1
Operation enabledNote 2
Operation stopped
8-bit timer 82
Operation enabledNote 2
Operation stopped
8-bit timer 30
Operation stopped
8-bit timer 40
8-bit remote control timer 50
Sound generator
Watch timer
Operation stopped
Operation enabledNote 2
Operation enabledNote 2
Operation enabledNote 2
Operation enabledNote 1
Operation stopped
Operation stopped
Operation stopped
Operation stopped
Watchdog timer
Serial interface
SIO
UART
A/D converter
Operation stopped
LCD controller/driver
External interrupt
Operation enabledNote 2
Operation enabledNote 3
Operation stopped
Notes 1. Operation is enabled only when an external clock has been selected.
2. Operation is enabled when the subsystem clock has been selected.
3. Non-masked maskable interrupt
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(2) Releasing STOP mode
The STOP mode can be released by the following two sources.
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are
enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization
time has elapsed. If interrupts are disabled, the instruction at the next address is executed.
Figure 18-5. Releasing STOP Mode by Interrupt
STOP
instruction
WaitNote
Standby
release signal
Oscillation stabilization
Operation
mode
Operation
mode
wait status
STOP mode
Oscillation
stops
Oscillation
Oscillation
Clock
Note The wait time differs depending on the main system clock selected.
When ceramic/crystal oscillation is selected: Can be selected by OSTS register (for details, see Figure
18-1 Format of Oscillation Stabilization Time
Selection Register)
When RC oscillation is selected:
Fixed at 27/fCC
Remark The broken line indicates the case where the interrupt request that has released the standby mode is
acknowledged.
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CHAPTER 18 STANDBY FUNCTION
(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 18-6. Releasing STOP Mode by RESET Input
STOP
instruction
WaitNote
RESET
signal
Oscillation
stabilization
wait status
Operation
mode
Reset
period
Operation
mode
STOP mode
Oscillation
Oscillation
stops
Oscillation
Clock
Note The wait time differs depending on the main system clock selected.
When ceramic/crystal oscillation is selected: 215/fX (6.55 ms)
When RC oscillation is selected:
27/fCC (64 µs)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
3. The parenthesized values apply to operation at fX = 5.0 MHz or fCC = 2.0 MHz.
Table 18-4. Operation After Releasing STOP Mode
Releasing Source
MK××
IE
0
Operation
Executes next address instruction
Executes interrupt servicing
Retains STOP mode
Maskable interrupt request
0
0
1
−
1
×
RESET input
−
Reset processing
×: don’t care
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CHAPTER 19 RESET FUNCTION
There are two ways to issue a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop time detection
Figure 19-1. Block Diagram of Reset Function
RESET
Reset controller
Reset signal
Over-
flow
Count clock
Watchdog timer
Stop
Interrupt function
(1) External reset input via RESET pin
Program execution starts at the address written to 0000H and 0001H after the RESET signal is input.
When a low level is input to the RESET pin, a reset is triggered and all hardware is set to the status shown in
Table 19-1. Each pin has high impedance during reset input or during the oscillation stabilization time
immediately after a reset is released.
When a high level is input to the RESET pin, the reset is released and program execution is started after the
oscillation stabilization time has elapsed.
(2) Internal reset by watchdog timer program loop time detection
There are no functional differences between external and internal resets, since in both cases program
execution starts at the address written to 0000H and 0001H after the RESET signal is input.
When the watchdog timer overflows, a reset is triggered and all hardware is set to the status shown in Table
19-1. Each pin has high impedance during reset input or during the oscillation stabilization time immediately
after a reset is released.
The reset is automatically released after a reset, and program execution is started after the oscillation
stabilization time has elapsed.
Cautions 1. For an external reset, input a low level for at least 10 µs to the RESET pin.
2. When the STOP mode is released by reset, the STOP mode contents are retained during
reset input. However, the port pins are set to high impedance.
3. The oscillation stabilization time for ceramic/crystal oscillation after a reset is released
differs from that for RC oscillation.
Ceramic/crystal oscillation: 215/fX
RC oscillation:
27/fCC
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Figure 19-2. Reset Timing by RESET Input
X1, CL1
RESET
Oscillation
During normal
operation
Reset period
stabilization
Normal operation
(reset processing)
(oscillation stops)
time wait
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
Figure 19-3. Reset Timing by Overflow in Watchdog Timer
X1, CL1
Oscillation
stabilization
time wait
Reset period
(oscillation
continues)
During normal
operation
Normal operation
(reset processing)
Overflow in
watchdog timer
Internal
reset signal
Hi-Z
Port pin
Figure 19-4. Reset Timing by RESET Input in STOP Mode
X1, CL1
RESET
STOP instruction execution
Oscillation
During normal
operation
Stop status
Reset period
Normal operation
(reset processing)
stabilization
time wait
(oscillation stops)
(oscillation stops)
Internal
reset signal
Delay
Delay
Hi-Z
Port pin
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CHAPTER 19 RESET FUNCTION
Table 19-1. Status of Each Hardware After Reset (1/2)
Hardware
Status After Reset
Program counter (PC)Note 1
Contents of reset vector
table (0000H, 0001H) are
set
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
Data memory
UndefinedNote 2
UndefinedNote 2
00H
General-purpose registers
Ports (P0 to P3) (output latch)
Port mode registers (PM0 to PM3)
FFH
Pull-up resistor option registers (PU0, PUB2, PUB3)
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
00H
02H
00H
Subclock control register (CSS)
00H
Oscillation stabilization time selection register (OSTS)
Power supply control register 0 (PSC0)
04H
00H
8-bit timer
Timer counters (TM30, TM40, TM80 to TM82)
00H
Compare registers (CR30, CR40, CRH40, CR80 to CR82)
Mode control registers (TMC30, TMC40, TMC80 to TMC82)
Carrier generator output control register (TCA40)
Timer counter (TM50)
Undefined
00H
Undefined
00H
8-bit remote control timer
Sound generator
Capture register (CP50, CP51)
00H
Control register (TMC50)
00H
Timer counter (TMSG0)
00H
Compare register (CRSG0)
Undefined
00H
Frequency setting register (SGFC00)
Carrier generator output control register (TCASG0)
Mode control register (TMCSG0)
00H
00H
P3 function register (PF3)
00H
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined.
For all other hardware, the status during reset input and oscillation stabilization time wait remains
unchanged after reset.
2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.
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Table 19-1. Status of Each Hardware After Reset (2/2)
Hardware
Status After Reset
Watch timer
Mode control register (WTM)
00H
00H
00H
00H
Watchdog timer
Clock selection register (WDCS)
Mode register (WDTM)
Serial interface
Mode register (CSIM10)
Transmit/receive shift register (SIO10)
Transmit shift register (TXS00)
Undefined
Undefined
FFH
Receive buffer register (RXB00)
Asynchronous serial interface mode register (ASIM00)
Asynchronous serial interface status register (ASIS00)
Baud rate generator control register (BRGC00)
Conversion result register (ADCR)
Mode register (ADM)
00H
00H
00H
A/D converter
LCD controller/driver
Multiplier
Undefined
00H
Input selection register (ADS)
00H
Display mode register (LCDM20)
Clock control register (LCDC20)
Boost voltage level setting register (VLCD00)
Multiplication result storage register (MUL0)
Data registers (MRA0, MRB0)
00H
00H
00H
Undefined
Undefined
00H
Control register (MULC0)
SWAP
Swap function register (SWP0)
Note
Interrupt
Request flag registers (IF0 to IF2)
Mask flag registers (MK0 to MK2)
External interrupt mode register (INTM0)
Key return mode register (KRM00)
00H
FFH
00H
00H
Note The status after reset in read mode differs from that in write mode. For details, see CHAPTER 16
SWAPPING (SWAP).
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CHAPTER 20 µPD78F9835
The µPD78F9835 is available as the flash memory version of the µPD789835, 789835A, 789835B Subseries.
The µPD78F9835 is a version with the internal ROM of the µPD78983x, 78983xA, 78983xB, replaced with flash
memory. The differences between the µPD78F9835 and the mask ROM versions are shown in Table 20-1.
Table 20-1. Differences Between µPD78F9835 and Mask ROM Versions
Item
Flash Memory
Version
Mask ROM Version
µPD78F9835
µPD789832
µPD789832A
µPD789832B
µPD789833
µPD789833A
µPD789833B
µPD789834
µPD789834A
µPD789834B
µPD789835
µPD789835A
µPD789835B
Internal
memory
ROM
60 KB
24 KB
32 KB
48 KB
60 KB
(flash memory)
High-speed RAM 1024 bytes
Low-speed RAM 2240 bytes
LCD display RAM 288 bytes × 2
1216 bytes
2240 bytes
A/D converter
Provided
µPD78983xB, 78983xA: Provided
µPD78983x:
Not provided
IC0 pin
Not provided
Provided
Provided
VPP pin
Not provided
1.8 to 3.6 V
Supply voltage (VDD)
Electrical specifications
3.0 to 3.6 V
See CHAPTER 22 ELECTRICAL SPECIFICATIONS.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
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20.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the
target system (on-board). A flash memory writing adapter (program adapter), which is a target board used exclusively
for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd.
(TEL +81-45-475-4191).
Programming using flash memory has the following advantages.
•
•
•
Software can be modified after the microcontroller is solder-mounted on the target system
Distinguishing software facilities low-quantity, varied model production
Easy data adjustment when starting mass production
20.1.1 Programming environment
The following shows the environment required for µPD78F9835 flash memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between
the host machine and flash programmer is performed via RS-232C/USB (Rev.1.1).
For details, refer the manual for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 20-1. Environment for Writing Program to Flash Memory
VPP
V
DD
SS
RS-232C
USB
V
RESET
Dedicated flash programmer
PD78F9835
µ
3-wire serial I/O
Host machine
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CHAPTER 20 µPD78F9835
20.1.2 Communication mode
Use the communication mode shown in Table 20-2 to perform communication between the dedicated flash
programmer and µPD78F9835.
Table 20-2. Communication Mode List
Communication
Mode
TYPE SettingNote 1
CPU CLOCK
Pins Used
Number of
VPP Pulses
COMM PORT
SIO Clock
Multiple Rate
In Flashpro
On Target
Board
3-wire serial I/O SIO ch-0
100 Hz to 1.25 1, 2, 4, 5
MHzNote 3
1 to 5 MHzNote 2 1.0
SI10/P22
0
(3 wired, sync.) MHzNote 2
SO10/P21
SCK10/P20
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,
PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).
2. The possible setting range differs depending on the voltage. For details, see CHAPTER 22
ELECTRICAL SPECIFICATIONS.
3. Only 2 MHz or 4 MHz is selectable with Flashpro III.
Caution Be sure to select the communication mode according to the number of VPP pulses shown in
Table 20-2.
Figure 20-2. Communication Mode Selection Format
7.8 V
VPP
VDD
1
2
n
VSS
VPP pulses
V
DD
RESET
V
SS
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Figure 20-3. Example of Connection with Dedicated Flash Programmer
Dedicated flash programmer
PD78F9835
µ
VPP1
VDD
V
PP
DD
V
RESET
SCK
RESET
P20/SCK10
P22/SI10
P21/SO10
X1
SO
SI
CLKNote
GND
VSS, SEL
Note Connect this pin when the system clock is supplied by the dedicated flash programmer. If an oscillator is
already connected to the X1 pin, the CLK pin does not need to be connected.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. Before using the power supply connected to the VDD pin, supply
voltage before starting programming.
If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the
µPD78F9835. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 20-3. Pin Connection List
Signal Name
VPP1
I/O
−
Pin Function
Pin Name
3-Wire Serial I/O
Output
I/O
Write voltage
VPP
VDD
VPP2
VDD
GND
CLK
RESET
SI
−
−
×
Note
VDD voltage generation/voltage monitoring
−
Ground
VSS, SEL
X1
Output
Output
Input
Clock output
Reset signal
Reception signal
Transmit signal
Transfer clock
−
{
RESET
P21/SO10
P22/SI10
P20/SCK10
−
SO
Output
Output
SCK
HS
−
×
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
{: If the signal is supplied on the target board, pin need not be connected.
×: Pin need not be connected.
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20.1.3 On-board pin processing
When performing programming on the target system, provide a connector on the target system to connect the
dedicated flash programmer.
An on-board function that allows switching between normal operation mode and flash memory programming mode
may be required in some cases.
<VPP pin>
In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 7.8
V (TYP.) is supplied to the VPP pin, so perform the following.
(1) Connect a pull-down resistor (RVPP = 10 kΩ) to the VPP pin.
(2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND.
A VPP pin connection example is shown below.
Figure 20-4. VPP Pin Connection Example
PD78F9835
µ
Connection pin of dedicated flash programmer
VPP
Pull-down resistor (RVPP
)
<Serial interface pin>
The following shows the pins used by the serial interface.
Serial Interface
Pins Used
SCK10/P20, SO10/P21, SI10/P22
3-wire serial I/O
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device
on-board, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken
with such connections.
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CHAPTER 20 µPD78F9835
(1) Signal conflict
If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to
another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device
or set the other device to the output high impedance status.
Figure 20-5. Signal Conflict (Input Pin of Serial Interface)
µ
PD78F9835
Connection pin of
dedicated flash
programmer
Signal conflict
Input pin
Other device
Output pin
In the flash memory programming mode, the signal output by another
device and the signal sent by the dedicated flash programmer conflict,
therefore, isolate the signal of the other device.
(2) Abnormal operation of other device
If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is
connected to another device (input), a signal is output to the device, and this may cause an abnormal
operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the
input signals to the other device are ignored.
Figure 20-6. Abnormal Operation of Other Device
µ
PD78F9835
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
µ
If the signal output by the PD78F9835 affects another device in the flash
memory programming mode, isolate the signals of the other device.
PD78F9835
µ
Connection pin of
dedicated flash
programmer
Pin
Other device
Input pin
If the signal output by the dedicated flash programmer affects another
device in the flash memory programming mode, isolate the signals of the
other device.
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CHAPTER 20 µPD78F9835
<RESET pin>
If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal
generator.
If the reset signal is input from the user system in the flash memory programming mode, a normal programming
operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash
programmer.
Figure 20-7. Signal Conflict (RESET Pin)
µ
PD78F9835
Connection pin of
dedicated flash
programmer
Signal conflict
RESET
Reset signal generator
Output pin
The signal output by the reset signal generator and the signal output from
the dedicated flash programmer conflict in the flash memory programming
mode, so isolate the signal of the reset signal generator.
<Port pins>
When the µPD78F9835 enters the flash memory programming mode, all the pins other than those that
communicate in flash memory programming are in the same status as immediately after reset.
If the external device does not recognize initial statuses such as the output high impedance status, therefore,
connect the external device to VDD or VSS via a resistor.
<Oscillator>
When using the on-board clock, connect X1 and X2 as required in the normal operation mode.
When using the clock output of the flash programmer, connect it directly to the X1 pin, disconnecting the main
oscillator on-board, and leave the X2 pin open. Operation of subclocks conforms that in the normal operation
mode.
<Power supply>
When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND of
the flash programmer, respectively.
When using the on-board power supply, connect it as required in the normal operation mode. Because the flash
programmer monitors the voltage, however, VDD of the flash programmer must be connected.
<Other pins>
Connect the SEL pin to VSS.
Process the other pins (LCD0 to LCD87, VLC0 to VLC4, VROUT0, and CAP0 to CAP3) in the same manner as in the
normal operation mode.
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20.1.4 Connection on flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 20-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode
VDD (3.0 to 3.6 V)
GND
1
108
107
106
105
104
103
102
101
100
99
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
92
µ
PD78F9835
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
VDD
VDD2 (LVDD)
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 21 INSTRUCTION SET
This chapter lists the instruction set of the µPD789835, 789835A, 789835B Subseries. For details of the operation
and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual
(U11047E).
21.1 Operation
21.1.1 Operand identifiers and description methods
Operands are described in the “Operands” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $, and [ ] symbols.
For the operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 21-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or label
saddrp
FE20H to FF1FH Immediate data or label (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or label (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 3-4 Special Function Registers for symbols of special function registers.
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CHAPTER 21 INSTRUCTION SET
21.1.2 Description of “Operation” column
A:
A register; 8-bit accumulator
X register
X:
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS:
( ):
Flag indicating non-maskable interrupt servicing in progress
Memory contents indicated by address or register contents in parenthesis
Higher 8 bits and lower 8 bits of 16-bit register
Logical product (AND)
XH, XL:
∧:
∨:
Logical sum (OR)
V:
Exclusive logical sum (exclusive OR)
Inverted data
−
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
21.1.3 Description of “Flag” column
(Blank): Unchanged
0:
1:
x:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
R:
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21.2 Operation List
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z
AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
x
x
x
x
x
x
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL+byte]
[HL+byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A, [HL]
A, [HL+byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z
AC CY
MOVW
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rp
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
Note
Note
Note
rp, AX
rp ← AX
XCHW
ADD
AX, rp
AX ↔ rp
A, #byte
saddr, #byte
A, r
A, CY ← A + byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
ADDC
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, [HL+byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, [HL+byte]
A, CY ← A − (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
SUBC
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A − byte − CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A ∧ byte
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
A ← A ∧ (addr16)
A ← A ∧ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∧ (HL + byte)
A ← A ∨ byte
OR
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A ← A ∨ (HL + byte)
A ← A V byte
XOR
(saddr) ← (saddr) V byte
A ← A V r
A, saddr
A, !addr16
A, [HL]
A ← A V (saddr)
A ← A V (addr16)
A ← A V (HL)
A, [HL+byte]
A ← A V (HL + byte)
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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CHAPTER 21 INSTRUCTION SET
Mnemonic
Operands
Byte
Clock
Operation
Flag
Z
x
x
x
x
x
x
x
x
x
x
x
x
x
x
AC CY
CMP
A, #byte
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
A − byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
saddr, #byte
A, r
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
ADDW
SUBW
CMPW
INC
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r − 1
DEC
saddr
rp
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
sfr.bit ← 1
x
x
x
x
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
PSW.bit ← 1
x
x
x
x
x
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
x
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
x
CY
CY ← 0
CY
CY ← CY
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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Mnemonic
Operands
Byte
Clock
Operation
Flag
Z
AC CY
CALL
!addr16
[addr5]
3
1
6
8
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH
POP
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
PSW
4
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$saddr16
$saddr16
$saddr16
$saddr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable interrupt)
IE ← 0 (Disable interrupt)
Set HALT mode
DI
HALT
STOP
Set STOP mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
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21.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte
A
r
sfr
saddr !addr16 PSW
[DE]
[HL]
[HL+byte] $addr16
1
None
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV
XCHNote XCH
ADD
MOV
XCH
ADD
MOV
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
A
ROL
RORC
ROLC
ADDC
SUB
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
XOR
CMP
AND
AND
OR
AND
OR
AND
OR
AND
OR
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV
MOV
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL+byte]
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
SP
MOVW
MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
$addr16
None
1st Operand
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX
!addr16
[addr5]
$addr16
Basic Instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound Instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
−0.3 to +4.6
−0.3 to +8.1
−0.3 to VDD + 0.3Note 2
−0.3 to VDD + 0.3Note 2
−0.3 to +6.5
−10
Unit
V
Power supply voltage
VDD
VPP
VI1
µPD78F9835 only, Note 1
V
Input voltage
V
Output voltage
VO1
VO2
IOH
Other than below
V
LCD0 to LCD95, CAP0 to CAP3, VLC0 to VLC4
V
Output current, high
1 pin
mA
mA
mA
mA
mA
°C
°C
°C
°C
TO40
−24
Total for all pins
1 pin
−30
Output current, low
IOL
TA
30
Total for all pins
During normal operation
During flash memory programming
Mask ROM version
µPD78F9835
90
Operating ambient temperature
Storage temperature
−40 to +85
10 to 40
Tstg
−65 to +150
−40 to +125
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the
flash memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (3.0 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (3.0 V) of the operating
voltage range of VDD (see b in the figure below).
3.0 V
V
DD
0 V
a
b
VPP
3.0 V
0 V
2. Must be 4.6 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Main System Clock Oscillator Characteristics
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V, (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Resonator Recommended Circuit
Parameter
Conditions
MIN.
1.0
TYP.
MAX.
5.0
4
Unit
MHz
ms
Ceramic
Oscillation frequency (fX)Note 1
IC X1
X2
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage
range MIN.
C1
C2
IC X1
X2
Crystal
Oscillation frequencyNote 1
1.0
0.4
5.0
10
MHz
ms
resonator
Oscillation stabilization
timeNote 2
C1
C2
CL1
CL2
RC
Oscillation frequency (fCC)
2.0
10
MHz
resonator
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage
range MIN.
µs
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS
.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Recommended Oscillator Constant
Ceramic resonator (TA = −40 to +85°C) (Mask ROM Version)
Manufacturer
Part Number
Frequency Recommended Circuit Oscillation Voltage
Remark
(MHz)
Constant (pF)
Range (VDD)
C1
100
−
C2
100
−
MIN.
1.8
MAX.
3.6
Murata Mfg.
Co., Ltd.
(Standard
products)
CSBLA1M00J58-B0Note
CSTCR4M00G53-R0
CSTLS4M00G53-B0
CSTCR5M00G53-R0
CSTLS5M00G53-B0
1.0
4.0
Rd = 2.2 kΩ
On-chip capacitor
version
5.0
Note A limiting resistor (Rd = 2.2 kΩ) is required when the CSBLA1M00J58-B0 (1.0 MHz) of Murata Mfg. Co.,
Ltd. is used as the ceramic resonator (see the figure below). A limiting resistor is not necessary when
other recommended resonators are used.
X1
X2
CSBLA1M00J58-B0
Rd
C2
C1
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the
actual application, apply to the resonator manufacturer for evaluation on the implementation
circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use
the µPD78983x so that the internal operating conditions are within the specifications of the DC
and AC characteristics.
Remark For the resonator selection and oscillator constant of the flash memory version, customers are required
to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Subsystem Clock Oscillator Characteristics
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Resonator Recommended Circuit
Parameter
Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
IC XT1 XT2
Crystal
Oscillation frequency
(fXT)Note 1
32.768
R
resonator
Oscillation stabilization
timeNote 2
10
s
C3
C4
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS
.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
DC Characteristics (1/3)
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
10
Unit
mA
mA
mA
Output current, low
IOL
1 pin
All pins
80
P30/SG0, P34/SG4 (when OE3 = 1, OE2 = 0,
buzzer mode 2 is selected) OE1 = 0, OE0 = X
3.4
1.9
VOL = VDD
OE3 = 0, OE2 = 1,
mA
mA
mA
OE1 = 0, OE0 = X
OE3 = 0, OE2 = 0,
OE1 = 1, OE0 = X
1.1
OE3 = 0, OE2 = 0,
OE1 = 0, OE0 = X
0.38
Output current, high
IOH
1 pin
−1
mA
mA
TO40/P27
VOH = 1.0 V,
VDD = 3.0 V
−6
−15
−24
All pins
−15
mA
mA
P30/SG0, P34/SG4 (when OE3 = 1, OE2 = 0,
buzzer mode 2 is selected) OE1 = 0, OE0 = X
−3.0
−1.5
−0.75
0
VOH = VSS
OE3 = 0, OE2 = 1,
mA
mA
mA
OE1 = 0, OE0 = X
OE3 = 0, OE2 = 0,
OE1 = 1, OE0 = X
OE3 = 0, OE2 = 0,
OE1 = 0, OE0 = X
0
0
Input voltage, high
VIH1
VIH2
P00 to P07, P10, P11, P21, VDD = 2.7 to 3.6 V
0.7VDD
0.9VDD
VDD
VDD
V
V
P25, P27, P30 to P37, P60
VDD = 1.8 to 2.7 V
to P62, P80 to P87
RESET, P20, P22 to P24,
P26
VDD = 2.7 to 3.6 V
VDD = 1.8 to 2.7 V
0.8VDD
0.9VDD
VDD − 0.1
VOH − 0.1
0
VDD
VDD
V
V
V
V
V
V
VIH3
VIH4
VIL1
X1 (CL1), X2 (CL2)
XT1, XT2
VDD
VOH
Input voltage, low
P00 to P07, P10, P11, P21, VDD = 2.7 to 3.6 V
0.3VDD
0.1VDD
P25, P27, P30 to P37, P60
VDD = 1.8 to 2.7 V
0
to P62, P80 to P87
VIL2
RESET, P20, P22 to P24,
P26
VDD = 2.7 to 3.6 V
VDD = 1.8 to 2.7 V
0
0
0
0
0.2VDD
0.1VDD
0.1
V
V
V
V
VIL3
X1 (CL1), X2 (CL2)
XT1, XT2
VIL4
0.1
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
DC Characteristics (2/3)
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Output voltage, high
VOH
IOH = −1 mA
VDD − 1.0
P00 to P07, P10, P11, P20 to P27, P30 to P37
VOH2
P30/SG0, P34/SG4 (when OE3 = 1, OE2 = 0,
buzzer mode 2 is selected) OE1 = 0, OE0 = X
2.7
2.4
2.0
0.0
V
V
VDD = 3.0 V
OE3 = 0, OE2 = 1,
OE1 = 0, OE0 = X
OE3 = 0, OE2 = 0,
OE1 = 1, OE0 = X
V
OE3 = 0, OE2 = 0,
OE1 = 0, OE0 = X
V
Output voltage, low
VOL
ILIH1
IOL = 10 mA
1.0
3
V
P00 to P07, P10, P11, P20 to P27, P30 to P37
VIN = VDD
Other than X1
(CL1), X2 (CL2),
XT1, XT2
µA
Input leakage current,
high
ILIH2
ILIH3
ILIL1
X1 (CL1), X2 (CL2)
XT1, XT2
20
3
µA
µA
µA
VIN = VOH
VIN = 0 V
Other than X1
−3
Input leakage current,
low
(CL1), X2 (CL2)
ILIL2
X1 (CL1), X2 (CL2)
−20
µA
µA
Output leakage current, ILOH
high
VOUT = VDD
VOUT = 0 V
3
Output leakage current, ILOL
low
−3
µA
VROUT0
PSC0 = 00H, After reset, After STOP mode
PSC0 = 01H
VDD
1.4
V
V
Regulator voltage
Software pull-up
resistor
R1
VIN = 0 V
P00 to P07, P10,
P11, P20 to P27,
P30 to P37
50
100
200
kΩ
Remarks 1. Unless otherwise specified, the characteristics of alternate-function pins are the same as those of
port pins.
2. Pin names enclosed in parentheses are for RC oscillation.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
DC Characteristics (3/3)
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
5.0 MHz crystal oscillation
MIN.
TYP. MAX.
Unit
mA
mA
mA
mA
mA
Power supply currentNote 1
(mask ROM version)
IDD1
PCC = 00H
PCC = 02H
PCC = 00H
PCC = 02H
1.5
1.1
1.5
1.1
0.5
3
2
operation mode (SEL = L)
1.2 MHz RC oscillation
3
operation mode (SEL = H)
2
IDD2
5.0 MHz crystal oscillation
HALT mode (SEL = L)
1.5
1.2 MHz RC oscillation HALT
mode (SEL = H)
0.5
1.5
mA
IDD3
32.768 kHz suboscillation
operation modeNote 2
VAON20 = 1
VAON20 = 0
VAON20 = 1
VAON20 = 0
15
10
12
8
40
35
36
24
10
5.0
4.2
5.0
4.2
18
16
18
16
12
µA
µA
32.768 kHz suboscillation
HALT modeNote 2
µA
µA
IDD4
STOP modeNote 3
1
µA
IDD5
5.0 MHz crystal oscillation
A/D operation mode
PCC = 00H
PCC = 02H
PCC = 00H
PCC = 02H
PCC = 00H
PCC = 02H
PCC = 00H
PCC = 02H
2.5
2.1
2.5
2.1
10
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
1.2 MHz RC oscillation A/D
operation mode
Power supply currentNote 1
IDD1
5.0 MHz crystal oscillation
operation mode (SEL = L)
(µPD78F9835)
1.2 MHz RC oscillation
10
8
operation mode (SEL = H)
IDD2
5.0 MHz crystal oscillation
HALT mode (SEL = L)
6
1.2 MHz RC oscillation HALT
mode (SEL = H)
6
12
mA
IDD3
32.768 kHz suboscillation
operation modeNote 2
VAON20 = 1
VAON20 = 0
VAON20 = 1
VAON20 = 0
7
7
12
12
6
mA
mA
mA
mA
µA
32.768 kHz suboscillation
HALT modeNote 2
3
3
6
IDD4
STOP modeNote 3
1
10
20
18
20
18
IDD5
5.0 MHz crystal oscillation
A/D operation mode
PCC = 00H
PCC = 02H
PCC = 00H
PCC = 02H
11
9
mA
mA
mA
mA
1.2 MHz RC oscillation A/D
operation mode
11
9
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. When the main system clock is stopped.
3. When the subsystem clock is stopped.
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
AC Characteristics
(1) Basic operation
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (mask ROM version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
Ceramic/
crystal
MIN.
0.4
TYP.
MAX.
8.0
Unit
µs
Cycle time (minimum
instruction execution
time)
TCY
Operating
with main
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
1.6
8.0
µs
system clock oscillation
RC
VDD = 2.0 to 3.6 V
VDD = 1.8 to 3.6 V
1.0
1.6
114
0
20
20
125
4
µs
µs
oscillation
Operating with subsystem clock
122
µs
TI80 input frequency
fTI
MHz
µs
TI80 input high-/low-
level width
tTIH,
0.1
tTIL
Interrupt input high-
/low-level width
tINTH,
INTP0, INTP1
KR00 to KR07
10
10
10
µs
µs
µs
tINTL
Key return input low-
level width
tKRL
tRSL
RESET low-level width
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
TCY vs. VDD (Main system clock: ceramic/crystal oscillation)
µ
(b) PD78F9835
(a) Mask ROM version
60
60
20
10
20
10
µ
µ
Guaranteed
operation
range
Guaranteed
operation
range
2.0
1.6
2.0
1.0
1.0
0.5
0.4
0.5
0.4
0.1
0.1
1
2
3
4
5
6
1
2
3
4
5
6
2.7
Supply voltage VDD (V)
Supply voltage VDD (V)
TCY vs. VDD (Main system clock: RC oscillation)
µ
(b) PD78F9835
(a) Mask ROM version
60
60
20
10
20
10
Guaranteed
operation
range
µ
µ
Guaranteed
operation
range
2.0
1.6
2.0
1.0
1.0
0.5
0.4
0.5
0.4
0.1
0.1
1
2
3
4
5
6
1
2
3
4
5
6
Supply voltage VDD (V)
Supply voltage VDD (V)
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
(2) Serial interface (UART00)
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (mask ROM version), VDD = 3.0 to 3.6 V (µPD78F9835))
Dedicated baud rate generator output
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
When fX = 5.0 MHz selected
78125
(3) Serial interface (SIO10)
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (mask ROM version), VDD = 3.0 to 3.6 V (µPD78F9835))
(a) 3-wire serial I/O mode (internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK10 cycle time
tKCY1
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
800
3200
SCK10 high-/low-level
width
tKH1,
tKCY1/2 – 50
tKL1
tKCY1/2 – 150
SI10 setup time
tSIK1
tKSI1
150
500
400
600
0
(to SCK10↑)
SI10 hold time
(from SCK10↑)
SO10 output delay time tKSO1
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 3.6 V
250
from SCK10↓
VDD = 1.8 to 3.6 V
0
1000
Note R and C are the load resistance and load capacitance of the SO10 output line.
(b) 3-wire serial I/O mode (external clock input)
Parameter
Symbol
Conditions
MIN.
800
3200
400
1600
100
150
400
600
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK10 cycle time
tKCY2
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
VDD = 2.7 to 3.6 V
VDD = 1.8 to 3.6 V
SCK10 high-/low-level
width
tKH2,
tKL2
SI10 setup time
tSIK2
tKSI2
(to SCK10↑)
SI10 hold time
(from SCK10↑)
SO10 output delay time tKSO2
R = 1 kΩ, C = 100 pFNote VDD = 2.7 to 3.6 V
300
from SCK10↓
VDD = 1.8 to 3.6 V
0
1000
Note R and C are the load resistance and load capacitance of the SO10 output line.
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
AC Timing Test Points (Excluding X1 and XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/f
X
t
XL
t
XH
V
IH3 (MIN.)
X1 (CL1) input
V
IL3 (MAX.)
1/fXT
t
XTL
t
XTH
V
IH4 (MIN.)
XT1 input
VIL4 (MAX.)
TI80 Timing
1/fTI
tTIL
t
TIH
TI80
Interrupt Input Timing
tINTL
tINTH
INTP0, INTP1
Key Return Input Timing
tKRL
KR00 to KR07
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
RESET Input Timing
tRSL
RESET
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK10
SI10
t
SIKm
t
KSIm
Input data
t
KSOm
Output data
SO10
Remark m = 1, 2
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User’s Manual U15559EJ2V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS
LCD Characteristics
(TA = −40 to +85°C, VDD = 2.4 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
MIN.
0
TYP.
MAX.
0.2
Unit
V
LCD output voltage
differential (common)
VODC
IO = 5 µA
IO = 5 µA
LCD output voltage
differential (segment)
VODS
tB
0
0.2
V
Boost voltage set time
LCD voltage
C = 0.47 µF, after VAON20 is set
VLCD00 = 00H
VLCD00 = 01H
VLCD00 = 02H
VLCD00 = 03H
VLCD00 = 04H
VLCD00 = 05H
VLCD00 = 06H
VLCD00 = 07H
VLCD00 = 08H
VLCD00 = 09H
VLCD00 = 0AH
VLCD00 = 0BH
VLCD00 = 0CH
VLCD00 = 0DH
VLCD00 = 0EH
VLCD00 = 0FH
500
ms
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note
VLC0
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
VLC1
VLC2
VLC3
VLC4
VODS
4/5 VLC0
3/5 VLC0
2/5 VLC0
1/5 VLC0
VLC0
Segment output voltage
Common signal output
Output level = VLC0
Output level = VLC2
Output level = VLC3
Output level = VLC0
Output level = VLC1
Output level = VLC4
3/5 VLC0
2/5 VLC0
VLC0
VODC
4/5 VLC0
1/5 VLC0
Note The above voltage is the value when no external LCD load is connected.
8-Bit A/D Converter Characteristics (µPD78983xB, 78983xA, 78F9835 Only)
(TA = −40 to +85°C, 2.2 V ≤ VDD ≤ 3.6 V (µPD78983xB, 78983xA), 3.0 V ≤ VDD ≤ 3.6 V (µPD78F9835))
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
Overall errorNote
1.5
LSB
µs
Conversion time
Analog input voltage
tCONV
VIAN
14
0
VDD
V
Note Excludes quantization error ( 1/2 LSB).
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User’s Manual U15559EJ2V1UD
CHAPTER 22 ELECTRICAL SPECIFICATIONS
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C, VDD = 1.8 to 3.6 V (Mask ROM Version), VDD = 3.0 to 3.6 V (µPD78F9835))
Parameter
Symbol
Conditions
MIN.
1.8
TYP.
MAX.
3.6
Unit
V
Data retention power
supply voltage
VDDDR
Release signal set time
tSREL
0
µs
215/fX
Oscillation stabilization
wait timeNote 1
tWAIT
Release by RESET
Release by interrupt
Ceramic/crystal
s
oscillation
27/fCC
RC oscillation
s
s
Ceramic/crystal
oscillation
Note 2
27/fCC
RC oscillation
s
Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time selection register (OSTS). For details, see 18.1.2 Registers controlling standby
function.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. fCC: Main system clock oscillation frequency (RC oscillation)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
V
DDDR
tSREL
STOP instruction execution
RESET
tWAIT
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
V
DDDR
t
SREL
STOP instruction execution
Standby release signal
(interrupt request)
t
WAIT
Flash Memory Writing and Erasing Characteristics (TA = 10 to 40°C, VDD = 3.0 to 3.6 V) (µPD78F9835 Only)
Parameter
Write/erase operating frequency
SCK cycle time
Symbol
fX
Conditions
3.0 V ≤ VDD ≤ 3.6 V
MIN.
1
TYP.
MAX.
5
Unit
MHz
ns
tkcy
500
Write current (VDD pin)Note
IDDW
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
21
mA
Write current (VPP pin)Note
Erase current (VDD pin)Note
IPPW
IDDE
When VPP supply voltage = VPP1
50
21
mA
mA
When VPP supply voltage = VPP1
(at 5.0 MHz operation)
Erase current (VPP pin)Note
Total erase time
IPPE
tera
When VPP supply voltage = VPP1
100
20
mA
s
Number of overwrites
Erase and write is considered as 1
cycle
20
Times
VPP supply voltage
VPP0
During normal operation
0
0.2VDD
8.1
V
V
VPP1
During flash memory programming
7.5
7.8
Note Excludes current flowing through ports (including on-chip pull-up resistors)
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User’s Manual U15559EJ2V1UD
CHAPTER 23 PACKAGE DRAWING
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
M
G
H
J
I
K
P
S
L
S
N
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
20.0 0.2
22.0 0.2
1.25
G
H
1.25
0.22 0.05
I
0.08
J
0.5 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.4
0.10 0.05
+4°
3°
R
S
−3°
1.5 0.1
S144GJ-50-UEN
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User’s Manual U15559EJ2V1UD
CHAPTER 24 APPLICATION CIRCUIT EXAMPLE
Caution The information shown in this chapter is for explaining an application circuit example. The user
shall assume all risk if this information is used when designing user’s own system.
Application circuit example 1
• Dot LCD panel (64 × 32)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used (buzzer mode 1 or 2).
• TO82 for lighting LED
• Key matrix of P00 to P07, and P10, P11, P35, and P36
• Infrared remote control signal transmission by TO40
• Thermistor sensor using ANI0 and P37
• External interface by UART
Application circuit example 2
Application circuit example 3
Application circuit example 4
• Dot LCD panel (64 × 32)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used (buzzer mode 1 or 2).
• Key matrix of P00 to P07, and P10, P11, P25, and P26
• External interface by UART
• Dot LCD panel (64 × 32)
• Main clock: RC oscillation (SEL pin: HIGH)
• Buzzer port (P3x) is used (buzzer mode 1 or 2).
• Key matrix of P00 to P07, and P10, P11, P25, and P26
• External interface by UART
• Dot LCD panel (64 × 32)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used (buzzer mode 1 or 2).
• TO82 for lighting LED
• Key matrix of P00 to P07, and P10, P11, P35, and P36
• Thermistor sensor using ANI0 and P37
• External interface by UART
• Remote control signal learning by remote controller amplifier and P26/RIN
Application circuit example 5
Application circuit example 6
Application circuit example 7
• Dot LCD panel (80 × 8)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used by using external resistor (buzzer mode 3).
• Key matrix of P00 to P07, and P10, P11, P25, and P26
• External interface by UART and P8
• Dot LCD panel (80 × 16)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used by using external resistor (buzzer mode 3).
• Key matrix of P00 to P07, and P10, P11, P25, and P26
• External interface by UART
• Dot LCD panel (48 × 48)
• Main clock: Ceramic or crystal (SEL pin: LOW)
• Buzzer port (P3x) is used by using external resistor (buzzer mode 3).
• Key matrix of P00 to P07, and P10, P11, P25, and P26
• External interface by UART
320
User’s Manual U15559EJ2V1UD
Figure 24-1. Application Circuit Example 1
Connector
In this example:
1) Dot LCD panel (64 × 32)
2) Main clock: Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used (buzzer mode 1 or 2).
4) TO82 for lighting LED
5) Key matrix of P00 to P07, and P10, P11, P35, and P36
6) Infrared remote control signal transmission by TO40
7) Thermistor sensor using ANI0 and P37
8) External interface by UART
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
COM
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
V
V
V
V
V
LC4
LC3
LC2
LC1
LC0
90
LCD53
LCD52
20
89
µ
PD789835A
µ
0.47 F × 5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
µ
×
0.47
F
3
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (64 × 32)
Figure 24-2. Application Circuit Example 2
Connector
In this example:
1) Dot LCD panel (64 × 32)
2) Main clock: Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used (buzzer mode 1 or 2).
4) Key matrix of P00 to P07, and P10, P11, P25, and P26
5) External interface by UART
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
COM
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
V
V
V
V
V
LC4
LC3
LC2
LC1
LC0
90
LCD53
LCD52
20
89
µ
PD789835A
0.47 F × 5
µ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
µ
×
0.47
F
3
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (64 × 32)
Figure 24-3. Application Circuit Example 3
Connector
In this example:
1) Dot LCD panel (64 × 32)
2) Main clock: RC oscillation (SEL pin: HIGH)
3) Buzzer port (P3x) is used (buzzer mode 1 or 2).
4) Key matrix of P00 to P07, and P10, P11, P25, and P26
5) External interface by UART
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
COM
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
VLC4
VLC3
VLC2
VLC1
VLC0
90
LCD53
LCD52
20
89
µ
PD789835A
µ
0.47 F × 5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
0.47
×
µ
F
3
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (64 × 32)
Figure 24-4. Application Circuit Example 4
Connector
In this example:
AMP
1) Dot LCD panel (64 × 32)
2) Main clock: Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used (buzzer mode 1 or 2).
4) TO82 for lighting LED
5) Key matrix of P00 to P07, and P10, P11, P35, and P36
6) Thermistor sensor using ANI0 and P37
7) External interface by UART
8) Remote control signal learning by remote controller
amplifier and P26/RIN
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
COM
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
VLC4
VLC3
VLC2
VLC1
VLC0
90
LCD53
LCD52
20
89
µPD789835A
µ
0.47 F × 5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
0.47
×
µ
F
3
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (64 × 32)
Figure 24-5. Application Circuit Example 5
Connector
In this example:
1) Dot LCD panel (80 × 8)
2) Main clock:
Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used by using external
resistor (buzzer mode 3).
4) Key matrix of P00 to P07, and P10, P11, P25, and P26
5) External interface by UART and P8
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
V
V
V
V
V
LC4
LC3
LC2
LC1
LC0
90
LCD53
LCD52
20
89
0.47
µ
F
5
PD789835A
µ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
×
87
86
CAP3
CAP2
CAP1
CAP0
COM
85
0.47
×
F
3
µ
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (80 × 8)
Figure 24-6. Application Circuit Example 6
Connector
In this example:
1) Dot LCD panel (80 × 16)
2) Main clock:
Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used by using external
resistor (buzzer mode 3).
4) Key matrix of P00 to P07, and P10, P11, P25, and P26
5) External interface by UART
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
LCD70
3
LCD69
4
LCD68
5
SEG
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
V
V
V
V
V
LC4
LC3
LC2
LC1
LC0
90
LCD53
LCD52
20
89
PD789835A
0.47 F × 5
µ
µ
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
0.47
×
F
3
µ
84
83
82
COM
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
SEG
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
Dot LCD panel (80 × 16)
Figure 24-7. Application Circuit Example 7
Connector
In this example:
1) Dot LCD panel (48 × 48)
2) Main clock:
Ceramic or crystal (SEL pin: LOW)
3) Buzzer port (P3x) is used by using external
resistor (buzzer mode 3).
4) Key matrix of P00 to P07, and P10, P11, P25, and P26
5) External interface by UART
1
108
107
106
105
104
103
102
101
100
99
LCD71
2
P04/KR04
P05/KR05
P06/KR06
P07/KR07
P10
SEG
LCD70
3
LCD69
4
LCD68
5
LCD67
6
LCD66
7
P11
LCD65
8
P30/SG0
P31/SG1
P32/SG2
P33/SG3
P34/SG4
P35/SG5
P36/SG6
P37/SG7
P60/ANI0
P61/ANI1
P62/ANI2
LCD64
9
LCD63
10
LCD62
11
98
LCD61
12
97
LCD60
13
96
LCD59
14
95
LCD58
15
94
LCD57
16
93
LCD56
17
92
LCD55
18
91
LCD54
19
VLC4
VLC3
VLC2
VLC1
VLC0
90
LCD53
LCD52
20
89
µ
PD789835A
µ
0.47 F × 5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
88
LCD51
LCD50
LCD49
LCD48
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
87
86
CAP3
CAP2
CAP1
CAP0
85
0.47
×
µ
F
3
COM
84
83
82
IC (VPP
)
81
V
ROUT0
80
XT2
XT1
79
78
V
SS
77
V
DD
76
X2
X1
75
74
1.5 V
× 2
RESET
SEL
73
SEG
Dot LCD panel (48 × 48)
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD789835, 789835A,
789835B Subseries. Figure A-1 shows the development tools.
• Support of PC98-NX Series
Unless specified otherwise, products supported by IBM PC/AT™ compatibles can be used in the PC98-NX
Series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles.
• WindowsTM
Unless specified otherwise, “Windows” indicates the following operating systems.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Version 4.0
• Windows XP
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User’s Manual U15559EJ2V1UD
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tools
Software package
• Software package
Language processing software
Software for debugging
• Assembler package
• C compiler package
• Device file
• Integrated debugger
• System simulator
• C compiler source fileNote 1
Control software
• Project manager
(Windows version only)Note 2
Host machine
(PC or EWS)
Interface adapter
Power supply unit
Flash memory writing tools
Flash programmer
In-circuit emulator
Emulation board
Flash memory
writing adapter
Flash memory
Emulation probe
Conversion socket or
conversion adapter
Target system
Notes 1. The C compiler source file is not included in the software package.
2. The project manager is included in the assembler package.
The project manager is used only for Windows.
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User’s Manual U15559EJ2V1UD
APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0S
Various software tools for 78K/0S Series development are integrated into one package.
The following tools are included.
Software package
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files
Part number: µS××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µS××××SP78K0S
××××
AB17
BB17
Host Machine
OS
Supply Medium
CD-ROM
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
A.2 Language Processing Software
RA78K0S
Program that converts program written in mnemonic into object codes that can be executed
by microcontroller.
Assembler package
In addition, automatic functions to generate symbol tables and optimize branch instructions
are also provided.
Used in combination with a device file (DF789835) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××RA78K0S
CC78K0S
Program that converts program written in C language into object codes that can be executed
by microcontroller.
C compiler package
Used in combination with an assembler package (RA78K0S) and device file (DF789835)
(bothsold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
Part number: µS××××CC78K0S
DF789835Note 1
Device file
File containing the information specific to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (sold
separately).
Part number: µS××××DF789835
CC78K0S-LNote 2
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
C library source file
Part number: µS××××CC78K0S-L
Notes 1. DF789835 is a file that can be used commonly with the RA78K0S, CC78K0S, ID78K0S-NS, and
SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
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User’s Manual U15559EJ2V1UD
APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µS××××RA78K0S
µS××××CC78K0S
××××
AB13
BB13
AB17
BB17
3P17
3K17
Host Machine
OS
Supply Medium
3.5" 2HD FD
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
Japanese Windows
English Windows
HP-UX™ (Rel.10.10)
CD-ROM
HP9000 series 700™
SPARCstation™
SunOS™ (Rel.4.1.4),
Solaris™ (Rel.2.5.1)
µS××××DF789835
µS××××CC78K0S-L
××××
Host Machine
OS
Supply Medium
AB13
BB13
3P16
3K13
3K15
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
HP-UX (Rel.10.10)
3.5" 2HD FD
HP9000 series 700
SPARCstation
DAT
SunOS (Rel.4.1.4),
Solaris (Rel.2.5.1)
3.5" 2HD FD
1/4" CGMT
A.3 Control Software
PM plus
Control software designed so that the user program can be efficiently developed in the
Windows environment. A series of jobs for user program development including starting the
editor, building, and starting the debugger, can be executed on the PM plus.
<Caution>
Project manager
The PM plus is included in the assembler package (RA78K0S).
It cannot be used in an environment other than Windows.
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User’s Manual U15559EJ2V1UD
APPENDIX A DEVELOPMENT TOOLS
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-144GJ-UEN
Adapter for writing to flash memory and connected to Flashpro III or to Flashpro IV.
FA-144GJ-UEN: for 144-pin plastic LQFP (GJ-UEN type)
Flash memory writing adapter
Remark The FL-PR3, FL-PR4, and FA-144GJ-UEN are products made by Naito Densei Machida Mfg. Co., Ltd.
(TEL +81-45-475-4191).
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator for debugging hardware and software of application system using 78K/0S
Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter,
emulation probe, and interface adapter for connecting the host machine.
In-circuit emulator
IE-78K0S-NS-A
IE-78K0S-NS with added coverage function and enhanced the debug function, enhancing the
tracer and timer functions.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using PC-9800 series PC (except notebook type) as host machine
(C bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using notebook PC as host machine (PCMCIA
socket supported)
IE-70000-PC-IF-C
Interface adapter
Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus
supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using personal computer incorporating PCI bus as host machine
IE-789835-NS-EM1
Emulation board
Board for emulating peripheral hardware specific to device. Used in combination with in-
circuit emulator.
SWEX-144SD-1
Emulation probe
Probe for connecting in-circuit emulator and target system.
Used in combination with NQPACK144SD and YQSOCKET144SDF.
NQPACK144SD
Conversion connector to connect SWEX-144SD-1 and target system board on which 144-pin
plastic LQFP (GJ-UEN type) can be mounted
Conversion connector
YQSOCKET144SDF
Conversion socket
Conversion socket to connect SWEX-144SD-1 and target system board on which 144-pin
plastic LQFP (GJ-UEN type) can be mounted
Remark The SWEX-144SD-1, NQPACK144SD, and YQSOCKET144SDF are products made by TOKYO
ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
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User’s Manual U15559EJ2V1UD
APPENDIX A DEVELOPMENT TOOLS
A.6 Debugging Tools (Software)
ID78K0S-NS
Debugger supporting in-circuit emulators for the 78K/0S Series: IE-78K0S-NS and IE-
78K0S-NS-A. The ID78K0S-NS is Windows-based software.
Integrated debugger
This program enhances the debugging functions for C language. Therefore, it can display
the trace results corresponding to the source program by using the window integration
function that links the source program, disassembled display, and memory display with the
trace results.
Use this program in combination with a device file (DF789835) (sold separately).
Part number: µS××××ID78K0S-NS
SM78K0S
System simulator for the 78K/0S Series. The SM78K0S is Windows-based software.
C-source-level or assembler level debugging is possible while simulating the operation of the
target system on the host machine. Using the SM78K0S enables logical and performance
verification of an application independently of the hardware development. This enhances
development efficiency and improves software quality.
System simulator
Use this program in combination with a device file (DF789835) (sold separately).
Part number: µS××××SM78K0S
DF789835Note
Device file
File containing information specific to the device.
Use this file in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (sold
separately).
Part number: µS××××DF789835
Note DF789835 is a file that can be used commonly with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µS××××ID78K0S-NS
µS××××SM78K0S
××××
AB13
BB13
AB17
BB17
Host Machine
OS
Supply Medium
3.5" 2HD FD
PC-9800 series, IBM PC/AT
compatibles
Japanese Windows
English Windows
Japanese Windows
English Windows
CD-ROM
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User’s Manual U15559EJ2V1UD
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
Figures B-1 and B-2 show the conditions when connecting the emulation probe to the conversion connector.
Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a
system.
SWEX-144SD-1, NQPACK144SD, and YQPACK144SD described in this appendix are products of TOKYO
ELETECH CORPORATION.
Figure B-1. Distance Between In-Circuit Emulator and Conversion Connector
In-circuit emulator
IE-78K0-NS or IE-78K0-NS-A
Target system
Emulation board
IE-789835-NS-EM1
CN2 CN3
335 8 mm
CN1
Emulation probe
SWEX-144SD-1
Conversion connector
NQPACK144SD +
YQPACK144SD
FG Cable
(Supplied)
Figure B-2. Connection to Target System
Emulation board
IE-789835-NS-EM1
Emulation probe
SWEX-144SD-1
Conversion
connector
18.5 mm
NQPACK144SD+
YQPACK144SD
29 mm
29 mm
47.5 mm
55.5 mm
Target system
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
C.1 Register Index (Alphabetic Order of Register Name)
[A]
A/D conversion result register (ADCR)........................................................................................................................186
A/D converter mode register (ADM)............................................................................................................................187
A/D input select register (ADS) ...................................................................................................................................188
Asynchronous serial interface mode register 00 (ASIM00) .........................................................................................202
Asynchronous serial interface status register 00 (ASIS00) .........................................................................................204
[B]
Baud rate generator control register 00 (BRGC00).....................................................................................................204
[C]
Carrier generator output control register 40 (TCA40)..................................................................................................129
Carrier generator output control register SG0 (TCASG0) ...........................................................................................159
[E]
8-bit compare register 30 (CR30)................................................................................................................................124
8-bit compare register 40 (CR40)................................................................................................................................124
8-bit compare register 80 (CR80)................................................................................................................................106
8-bit compare register 81 (CR81)................................................................................................................................106
8-bit compare register 82 (CR82)................................................................................................................................106
8-bit compare register SG0 (CRSG0) .........................................................................................................................158
8-bit H width compare register 40 (CRH40) ................................................................................................................124
8-bit timer counter 30 (TM30)......................................................................................................................................125
8-bit timer counter 40 (TM40)......................................................................................................................................125
8-bit timer counter 80 (TM80)......................................................................................................................................106
8-bit timer counter 81 (TM81)......................................................................................................................................106
8-bit timer counter 82 (TM82)......................................................................................................................................106
8-bit timer counter SG0 (TMSG0) ...............................................................................................................................158
8-bit timer mode control register 30 (TMC30) .............................................................................................................127
8-bit timer mode control register 40 (TMC40) .............................................................................................................128
8-bit timer mode control register 80 (TMC80) .............................................................................................................107
8-bit timer mode control register 81 (TMC81) .............................................................................................................108
8-bit timer mode control register 82 (TMC82) .............................................................................................................109
8-bit timer mode control register SG0 (TMCSG0).......................................................................................................158
External interrupt mode register 0 (INTM0).................................................................................................................264
[I]
Interrupt mask flag register 0 (MK0)............................................................................................................................263
Interrupt mask flag register 1 (MK1)............................................................................................................................263
Interrupt mask flag register 2 (MK2)............................................................................................................................263
Interrupt request flag register 0 (IF0) ..........................................................................................................................262
Interrupt request flag register 1 (IF1) ..........................................................................................................................262
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
Interrupt request flag register 2 (IF2)...........................................................................................................................262
[K]
Key return mode register 00 (KRM00).........................................................................................................................266
[L]
LCD boost voltage level setting register 00 (VLCD00) ................................................................................................229
LCD20 clock control register (LCDC20) ......................................................................................................................228
LCD20 display mode register (LCDM20).....................................................................................................................226
[M]
Multiplication data register A0 (MRA0)........................................................................................................................251
Multiplication data register B0 (MRB0)........................................................................................................................251
Multiplier control register 0 (MULC0)...........................................................................................................................253
[O]
Oscillation stabilization time selection register (OSTS) ...............................................................................................274
[P]
P3 function register (PF3) ...........................................................................................................................................164
Port 0 (P0).....................................................................................................................................................................75
Port 1 (P1).....................................................................................................................................................................76
Port 2 (P2).....................................................................................................................................................................77
Port 3 (P3).....................................................................................................................................................................81
Port 6 (P6).....................................................................................................................................................................82
Port 8 (P8).....................................................................................................................................................................83
Port mode register 0 (PM0)...........................................................................................................................................84
Port mode register 1 (PM1)...........................................................................................................................................84
Port mode register 2 (PM2)...........................................................................................................................84, 110, 130
Port mode register 3 (PM3)...........................................................................................................................................84
Power supply control register 0 (PSC0) ......................................................................................................................275
Processor clock control register (PCC) .........................................................................................................................90
Pull-up resistor option register 0 (PU0) .........................................................................................................................85
Pull-up resistor option register B2 (PUB2).....................................................................................................................86
Pull-up resistor option register B3 (PUB3).....................................................................................................................86
[R]
Receive buffer register 00 (RXB00).............................................................................................................................199
Remote control timer capture register 50 (CP50)........................................................................................................152
Remote control timer capture register 51 (CP51)........................................................................................................152
Remote control timer control register 50 (TMC50) ......................................................................................................152
[S]
Serial operation mode register 10 (CSIM10)...............................................................................................................201
16-bit multiplication result storage register 0H (MUL0H).............................................................................................251
16-bit multiplication result storage register 0L (MUL0L) ..............................................................................................251
Sound generator frequency setting register 00 (SGFC00) ..........................................................................................159
Subclock control register (CSS) ....................................................................................................................................92
Suboscillation mode register (SCKM)............................................................................................................................91
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
Swapping function register 0 (SWP0) .........................................................................................................................256
[T]
Transmit shift register 00 (TXS00) ..............................................................................................................................199
Transmit/receive shift register 10 (SIO10)...................................................................................................................199
[W]
Watch timer mode control register (WTM) ..................................................................................................................175
Watchdog timer clock selection register (WDCS) .......................................................................................................180
Watchdog timer mode register (WDTM) .....................................................................................................................181
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
C.2 Register Index (Alphabetic Order of Register Symbol)
[A]
ADCR:
ADM:
A/D conversion result register...............................................................................................................186
A/D converter mode register.................................................................................................................187
A/D input select register........................................................................................................................188
Asynchronous serial interface mode register 00...................................................................................202
Asynchronous serial interface status register 00 ..................................................................................204
ADS:
ASIM00:
ASIS00:
[B]
BRGC00:
[C]
Baud rate generator control register 00 ................................................................................................204
CP50:
CP51:
CR30:
CR40:
CR80:
CR81:
CR82:
CRH40:
CRSG0:
CSIM10:
CSS:
Remote control timer capture register 50..............................................................................................152
Remote control timer capture register 51..............................................................................................152
8-bit compare register 30......................................................................................................................124
8-bit compare register 40......................................................................................................................124
8-bit compare register 80......................................................................................................................106
8-bit compare register 81......................................................................................................................106
8-bit compare register 82......................................................................................................................106
8-bit H width compare register 40.........................................................................................................124
8-bit compare register SG0...................................................................................................................158
Serial operation mode register 10.........................................................................................................201
Subclock control register ........................................................................................................................92
[I]
IF0:
Interrupt request flag register 0.............................................................................................................262
Interrupt request flag register 1.............................................................................................................262
Interrupt request flag register 2.............................................................................................................262
External interrupt mode register 0.........................................................................................................264
IF1:
IF2:
INTM0:
[K]
KRM00:
[L]
Key return mode register 00 .................................................................................................................266
LCDC20:
LCDM20:
LCD20 clock control register.................................................................................................................228
LCD20 display mode register................................................................................................................226
[M]
MK0:
Interrupt mask flag register 0................................................................................................................263
Interrupt mask flag register 1................................................................................................................263
Interrupt mask flag register 2................................................................................................................263
Multiplication data register A0...............................................................................................................251
Multiplication data register B0...............................................................................................................251
16-bit multiplication result storage register 0H......................................................................................251
16-bit multiplication result storage register 0L.......................................................................................251
Multiplier control register 0....................................................................................................................253
MK1:
MK2:
MRA0:
MRB0:
MUL0H:
MUL0L:
MULC0:
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
[O]
OSTS:
[P]
Oscillation stabilization time selection register......................................................................................274
P0:
Port 0......................................................................................................................................................75
Port 1......................................................................................................................................................76
Port 2......................................................................................................................................................77
Port 3......................................................................................................................................................81
Port 6......................................................................................................................................................82
Port 8......................................................................................................................................................83
Processor clock control register..............................................................................................................90
P3 function register...............................................................................................................................164
Port mode register 0...............................................................................................................................84
Port mode register 1...............................................................................................................................84
Port mode register 2...............................................................................................................84, 110, 130
Port mode register 3...............................................................................................................................84
Power supply control register 0 ............................................................................................................275
Pull-up resistor option register 0.............................................................................................................85
Pull-up resistor option register B2...........................................................................................................86
Pull-up resistor option register B3...........................................................................................................86
P1:
P2:
P3:
P6:
P8:
PCC:
PF3:
PM0:
PM1:
PM2:
PM3:
PSC0:
PU0:
PUB2:
PUB3:
[R]
RXB00:
[S]
Receive buffer register 00 ....................................................................................................................199
SCKM:
SGFC00:
SIO10:
SWP0:
Suboscillation mode register...................................................................................................................91
Sound generator frequency setting register 00.....................................................................................159
Transmit/receive shift register 10..........................................................................................................199
Swapping function register 0 ................................................................................................................256
[T]
TCA40:
TCASG0:
TM30:
Carrier generator output control register 40..........................................................................................129
Carrier generator output control register SG0.......................................................................................159
8-bit timer counter 30............................................................................................................................125
8-bit timer counter 40............................................................................................................................125
8-bit timer counter 80............................................................................................................................106
8-bit timer counter 81............................................................................................................................106
8-bit timer counter 82............................................................................................................................106
8-bit timer mode control register 30......................................................................................................127
8-bit timer mode control register 40......................................................................................................128
Remote control timer control register 50...............................................................................................152
8-bit timer mode control register 80......................................................................................................107
8-bit timer mode control register 81......................................................................................................108
8-bit timer mode control register 82......................................................................................................109
8-bit timer mode control register SG0...................................................................................................158
8-bit timer counter SG0 ........................................................................................................................158
Transmit shift register 00......................................................................................................................199
TM40:
TM80:
TM81:
TM82:
TMC30:
TMC40:
TMC50:
TMC80:
TMC81:
TMC82:
TMCSG0:
TMSG0:
TXS00:
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User’s Manual U15559EJ2V1UD
APPENDIX C REGISTER INDEX
[V]
VLCD00:
[W]
LCD boost voltage level setting register 00...........................................................................................229
WDCS:
WDTM:
WTM:
Watchdog timer clock selection register ...............................................................................................180
Watchdog timer mode register..............................................................................................................181
Watch timer mode control register........................................................................................................175
340
User’s Manual U15559EJ2V1UD
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition
(1/3)
Page
Description
Addition of products in µPD789835B, 789835A Subseries
Total revision of CHAPTER 1 GENERAL
Throughout
pp. 25 to 35
pp. 36, 38, 39, Change so that pull-up resistors of ports 2 and 3 can be used regardless of the I/O modes.
74, 77, 81, 86
2.1 List of Pin Functions
2.2.3 P20 to P27 (Port 2)
2.2.4 P30 to P37 (Port 3)
Table 4-1 Port Functions
4.2.3 Port 2
4.2.4 Port 3
4.3 (3) Pull-up resistor option register B2 (PUB2)
4.3 (4) Pull-up resistor option register B3 (PUB3)
p. 40
2.2.8 CAP0 to CAP3
2.2.10 VLC0 to VLC4
• Correction of capacitance
p. 41
p. 44
p. 63
Addition of description to 2.2.18 VPP (µPD78F9835 only)
Modification of Type 5-AB in Figure 2-1 Pin I/O Circuits
Modification of value after reset of carrier generator output control register 40 (TCA40) in Table 3-4 Special
Function Registers
pp. 75, 77 to
81
Modification of the following figures
Figure 4-2 Block Diagram of P00 to P07
Figure 4-4 Block Diagram of P20
Figure 4-5 Block Diagram of P21
Figure 4-6 Block Diagram of P22 to P24 and P26
Figure 4-7 Block Diagram of P25 and P27
Figure 4-8 Block Diagram of P30 to P37
p. 86
4.3 (3) Pull-up resistor option register B2 (PUB2)
4.3 (4) Pull-up resistor option register B3 (PUB3)
• Change so that pull-up resistors of ports 2 and 3 can be used regardless of I/O modes
• Addition of Caution when output is used
pp. 93, 94
5.4.1 Main system clock oscillator (crystal/ceramic oscillation)
5.4.2 Main system clock oscillator (RC oscillation)
5.4.3 Subsystem clock oscillator
• Deletion of description of external clock
pp. 117 to 119 Modification of 6.5 Cautions Related to 8-Bit Timer/Event Counters 80 to 82
pp. 122 to 124 Modification of the following figures
Figure 7-1 Block Diagram of Timer 30
Figure 7-2 Block Diagram of Timer 40
Figure 7-3 Block Diagram of Output Controller (Timer 40)
p. 124
p. 128
Addition of descriptions to 7.2 (2) 8-bit compare register 40 (CR40) and (3) 8-bit H width compare register
40 (CRH40)
Modification of Figure 7-5 Format of 8-Bit Timer Mode Control Register 40
341
User’s Manual U15559EJ2V1UD
APPENDIX D REVISION HISTORY
(2/3)
Page
p. 129
Description
Modification of Figure 7-6 Format of Carrier Generator Output Control Register 40
Addition of description and Caution to 7.4.3 Operation as carrier generator
p. 144
p. 145
Modification of Figure 7-17 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
Modification of Figure 7-18 Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
Modification of 7.5 Notes on Using 8-Bit Timers 30, 40
p. 146
p. 150
p. 155
Revision of 9.1 Functions of Sound Generator
p. 159
Modification of Figure 9-3 Format of Carrier Generator Output Control Register SG0
Modification of Figure 9-5 Format of P3 Function Register
p. 164
pp. 165, 166
Addition of 9.4 Setting of Sound Generator
pp. 167 to 172 Addition of 9.5 Sound Generator Output Mode
p. 173
p. 174
p. 176
p. 177
p. 184
p. 197
p. 198
p. 201
p. 203
p. 205
Modification of Figure 10-1 Block Diagram of Watch Timer
Modification of interrupt request name in 10.1 (2) Interval timer
Modification of value of maximum error in 10.4.1 Operation as watch timer
Modification of Figure 10-3 Watch Timer/Interval Timer Operation Timing
Addition of Caution to CHAPTER 12 8-BIT A/D CONVERTER (µPD78983xB, 78983xA, 78F9835 ONLY)
Modification of Figure 13-1 Block Diagram of Serial Interface (SIO10)
Modification of Figure 13-2 Block Diagram of Serial Interface (UART00)
Addition of Caution to Figure 13-3 Format of Serial Operation Mode Register 10
Modification of Table 13-2 Settings of Serial Interface Operating Mode
Modification of Figure 13-6 Format of Baud Rate Generator Control Register 00
pp. 206, 207,
214
Modification of the following tables
Table 13-3 Example of Relationship Between Main System Clock and Baud Rate (When fX = 5.0 MHz)
Table 13-4 Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.9152 MHz)
Table 13-5 Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.1943 MHz)
Table 13-6 Example of Relationship Between Main System Clock and Baud Rate (When fX = 4.00 MHz)
Table 13-7 Relationship Between Source Clock of 5-Bit Counter and Value n
pp. 225, 227,
229
Modification of the following figures
Figure 14-1 Block Diagram of LCD Controller/Driver
Figure 14-2 Format of LCD20 Display Mode Register
Figure 14-4 Format of LCD Boost Voltage Level Setting Register 00
pp. 228, 229
Addition of the following tables
Table 14-2 Frame Frequency (Hz) at 1/48 Duty (48 × 48 Mode)
Table 14-3 Frame Frequency (Hz) at 1/32 Duty (64 × 32 Mode)
Table 14-4 Frame Frequency (Hz) at 1/16 Duty (80 × 16 Mode)
Table 14-5 Frame Frequency (Hz) at 1/8 Duty (80 × 8 Mode)
p. 233
p. 250
p. 255
p. 256
p. 266
Revision of 14.5 Setting LCD Controller/Driver
Addition of 14.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2, VLC3, and VLC4
Revision of 16.1 Function of SWAP
Addition of 16.3 Example of Executing SWAP
17.3 (5) Key return mode register 00 (KRM00)
• Change so that only 8-bit memory manipulation instruction can be used
• Deletion of reserved word definition of 0-bit and 4-bit to 7-bit names
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APPENDIX D REVISION HISTORY
(3/3)
Page
p. 284
Description
Modification of value after reset of carrier generator output control register 40 (TCA40) in Table 19-1 Status of
Each Hardware After Reset
p. 286
Addition of description of A/D converter to Table 20-1 Differences Between µPD78F9835 and Mask ROM
Versions
p. 288
Modification of Table 20-2 Communication Mode List
pp. 288, 290
Figure 20-2 Communication Mode Selection Format
20.1.3 On-board pin processing
• Modification of write voltage to 7.8 V
pp. 304 to 318 CHAPTER 22 ELECTRICAL SPECIFICATIONS
• Modification of target specification to official specification
• Addition of Note to Absolute Maximum Ratings
• Deletion of description of external clock from Main System Clock Oscillator Characteristics
• Addition of recommended oscillator constants of mask ROM versions
• Deletion of description of external clock from Subsystem Clock Oscillator Characteristics
• Modification of specification of supply current in DC Characteristics
• Modification of specification of cycle time (minimum instruction execution time) in AC Characteristics
• Modification of specification of transfer rate of serial interface (UART00)
• Modification of specification of LCD Characteristics
• Modification of specification of Flash Memory Writing and Erasing Characteristics
pp. 320 to 327 Addition of CHAPTER 24 APPLICATION CIRCUIT EXAMPLE
pp. 328 to 333 Updating of APPENDIX A DEVELOPMENT TOOLS
p. 334
Addition of APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
pp. 341 to 343 Addition of APPENDIX D REVISION HISTORY
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User’s Manual U15559EJ2V1UD
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