UPD78C11AL [NEC]

8-BIT SINGLE-CHIP MICROCOMPUTER WITH A/D CONVERTER; 带A / D转换器8位单片机


型号：	UPD78C11AL
厂家：	NEC
描述：	8-BIT SINGLE-CHIP MICROCOMPUTER WITH A/D CONVERTER 带A / D转换器8位单片机转换器微控制器和处理器外围集成电路装置输入元件计算机时钟
文件：	总66页 (文件大小：3241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD78C10A, 78C11A, 78C12A

8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)

DESCRIPTION

The µPD78C11A is a CMOS 8-bit microprocessor which can integrate 16-bit ALU, ROM, RAM, an A/D converter,

a multi-function timer/event counter, and a general-purpose serial interface into a single chip, then expand the

memory (ROM/RAM) up to 60K bytes externally. The µPD78C10A is a ROM-less product of the µPD78C11A, and can

directly address the external memory up to 64k bytes. The µPD78C12A is a product which has more built-in ROM

capacity than the µPD78C11A, and its memory (ROM/RAM) can be externally extended up to 56K bytes. The

µPD78C10A, µPD78C11A, and µPD78C12A operated at low power consumption, because they have a CMOS

construction. Also, they can hold data with low power consumption by using standby function.

On-chip PROM products, µPD78CP14 and µPD78CP18 which are ideal for evaluation or preproduction use during

system development, early start-up and short-run multiple-device production of application sets, are available.

FEATURES

• Abundant 159 types of instructions : 87AD series instruction set, multiplication/division instructions,

16-bit operation instructions

• Instruction cycle : 0.8 µs (at 15 MHz operation)

• On-chip ROM : 4096W × 8 (µPD78C11A), 8192W × 8 (µPD78C12A)

Non (µPD78C10A)

• On-chip RAM : 256W × 8

• High-precision 8-bit A/D converter : 8 analog inputs

• General-purpose serial interface : Asynchronous, synchronous, I/O interface mode

• Multi-function 16-bit timer/event counter

• Two 8-bit timers

• I/O lines : 32 (µPD78C10A), 44 (µPD78C11A, 78C12A)

• Interrupt function (external - 3, internal - 8) : Non-maskable interrupt × 1, maskable interrupt × 10

• Standby function : HALT mode, hardware/software STOP mode

• Zero-cross detection function : (2 inputs)

• On-chip pull-up resistor (port A, B, C: µPD78C11A, 78C12A only) by mask option

Caution The µPD78C10A does not hava a mask option.

The information in this document is subject to change without notice.

Document No. IC-2678C

The mark ★ shows major revised points.

(O. D. No. IC-7769E)

Date Published February 1995 P

Printed in Japan

1990

µPD78C10A,78C11A,78C12A

ORDERING INFORMATION

Ordering Code

Package

On-Chip ROM

µPD78C10ACW

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14 × 20 mm)

64-pin plastic QUIP

68-pin plastic QFJ ( 950 mil)

64-pin plastic shirink DIP (750 mil)

64-pin plastic QFP (14 × 20 mm)

64-pin plastic QUIP

64-pin plastic QUIP straight

68-pin plastic QFJ ( 950 mil)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14 × 20 mm)

64-pin plastic QUIP

None

µPD78C10AGF-3BE

µPD78C10AGQ-36

µPD78C10AL

µPD78C11ACW-×××

µPD78C11AGF-×××-3BE

µPD78C11AGQ-×××-36

µPD78C11AGQ-×××-37

µPD78C11AL-×××

µPD78C12ACW-×××

µPD78C12AGF-×××-3BE

µPD78C12AGQ-×××-36

µPD78C12AGQ-×××-37

µPD78C12AL-×××

Mask ROM

64-pin plastic QUIP straight

68-pin plastic QFJ ( 950 mil)

µPD78C10A,78C11A,78C12A

PIN CONFIGURATION (TOP VIEW)

•

For µPD78C10ACW, µPD78C10AGQ-36, µPD78C11ACW-×××, µPD78C11AGQ-×××-36/37, µPD78C12ACW-×××,

µPD78C12AGQ-×××-36/37.

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

VDD

STOP

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

ALE

PC0/T

PC1/R

PC2/SCK

PC3/INT2

PC4/TO

PC5/CI

PC6/CO0

PC7/CO1

NMI

AVDD

AREF

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

AV^SS

INT1

MODE1

RESET

MODE0

•

For µPD78C10AGF-3BE, µPD78C11AGF-×××-3BE, µPD78C12AGF-×××-3BE

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PD3

PD4

PD5

PD6

PD7

STOP

V^DD

AN4

AN3

AN2

AN1

AN0

AV^SS

VSS

PA0

PA1

PA2

PA3

PA4

PA5

MODE0

RESET

MODE1

INT1

10 11 12 13 14 15 16 17 18 19

µPD78C10A,78C11A,78C12A

•

For µPD78C10AL, µPD78C11AL-×××, µPD78C12AL-×××

68 67 66 65 64 63 62 61

PD1

PD0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

ALE

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0/T

PC1/R

PC2/SCK

PC3/INT2

AV^DD

PC4/TO

PC5/CI

PC6/CO0

AREF

AN7

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

OSC

PF7-0/

AB15-8

LATCH

INC/DEC

12/

PC0/TXD

SERIAL I/O

PC1/RXD

PC2/SCK

MAIN

G.R

PD7-0/

AD7-0

NMI

INT1

EA'

PROGRAM*1

MEMORY

INT.

CONTROL

DATA

ALT

G.R

MEMORY

(256-BYTE)

PC7-0*2

PB7-0*2

PA7-0*2

BUFFER

8/16

PC3/INT2/TI

PC4/TO

TIMER

INTERNAL DATA BUS

PC5/CI

PC6/CO0

PC7/CO1

LATCH

TIMER/

EVENT COUNTER

LATCH

PSW

INST.REG

AN7-0

A/D

CONVERTER

VAREF

INST.

DECODER

ALU

(8/16)

AVDD

AVSS

READ/WRITE

CONTROL

SYSTEM

CONTROL

STAND BY

CONTROL

1. It depends on a product type.

The µPD78C11A has 4K bytes, and the µPD78C12A has 8K

bytes.

ALE MODE1 MODE0 RESET

STOP

VDD

VSS

The µPD78C10A does not incorporate a program memory.

2. An on-chip pull-up resistor is available by mask option

(µPD78C11A, 78C12A only).

µPD78C10A,78C11A,78C12A

CONTENTS

1. PIN FUNCTIONS .....................................................................................................................................

1.1 LIST OF PIN FUNCTION ................................................................................................................................

1.2 PIN INPUT/OUTPUT CIRCUITS ....................................................................................................................

1.3 PIN MASK OPTIONS ...................................................................................................................................... 14

1.4 RECOMMENDED CONNECTION OF UNUSED PINS.................................................................................. 14

2. DIFFERENCES BETWEEN µPD78C10A AND µPD78C11A, 78C12A................................................... 15

3. RESET OPERATIONS ............................................................................................................................. 17

4. INSTRUCTION SET................................................................................................................................. 20

4.1 IDENTIFIER/DESCRIPTION OF OPERAND................................................................................................... 20

4.2 SYMBOL DESCRIPTION OF OPERATION CODE......................................................................................... 21

4.3 INSTRUCTION EXECUTION TIME ................................................................................................................ 22

5. LIST OF MODE REGISTERS .................................................................................................................. 34

6. ELECTRICAL SPECIFICATIONS ............................................................................................................. 35

7. CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 47

8. DIFFERENCES IN 87AD SERIES PRODUCTS ...................................................................................... 50

9. PACKAGE INFORMATION ..................................................................................................................... 54

10. RECOMMENDED SOLDERING CONDITIONS...................................................................................... 60

APPENDIX DEVELOPMENT TOOLS ............................................................................................................ 62

µPD78C10A,78C11A,78C12A

1. PIN FUNCTIONS

1.1 LIST OF PIN FUNCTION (1/2)

Pin Name

I/O

Function

PA7 to PA0

(Port A)

Input/Output

8-bit input-output port, which can specify input/output bit-wise.

Transmit Data

PB7 to PB0

(Port B)

Input-output/

Output

PC0/T^XD

PC1/RxD

Output pin for serial data.

Receive Data

Input pin for serial data.

Input-output/

Input

Serial Clock

Input-output pin for serial clock.

It becomes output clock for the internal

Input-output/

Input-output

PC2/SCK

clock use, and input for the external.

Interrupt Request/Timer Input

Maskable interrut input pin of the edge

trigger(fallingedge),oranexternalclock

input pin for a timer. Also, it can be used

as a zero-cross detection pin for AC

Input-output/

Input/Input

Port C

PC3/INT2/TI

8-bit input-output port,

which can specify input/ output bit-wise.

input.

Timer Output

Squarewavedefiningonecycleofinternal

clock or timer counter time as half cycle

is output.

Input-output/

Output

PC4/TO

PC5/CI

Counter Input

External pulse input pin to timer/event

counter.

Input-output/

Input

Counter Output 0, 1

Programmablerectanglewaveoutputby

timer/event counter.

PC6/CO0

PC7/CO1

Input-output/

Output

Port D

Address/Data Bus

When external memory is used, it be-

comes multiplexed address/data bus.

Input-output/

Input-output

PD7 to PD0/

AD7 to AD0

8-bit input-output port, which can specify

input-output in byte units (µPD78C11A).

Address Bus

When external memory is used, it be-

comes address bus.

Port F

Input-output/

Output

PF7 to PF0/

AB15 to AB8

8-bit input-output port, which can specify

input-output bit-wise.

Strobe signal which is output for write operation of external memory. It becomes high in

any cycle other than the data write machine cycle of external memory. When RESET signal

is either low or in the hardware STOP mode, this signal becomes output high-impedance.

Output

(Write Strobe)

Strobe signal which is output for read operation of external memory. It becomes high in any

cycle other than the read machine cycle of external memory. When RESET signal is either

low or in the hardware STOP mode, this signal becomes output high-impedance.

(Read Strobe)

ALE

(AddressLatch

Enable)

Strobe signal to latch externally the lower address information which is output to PD7 to

PD0 pins to access external memory. When RESET signal is either low or in the hardware

STOP mode, this signal becomes output high-impedance.

µPD78C10A,78C11A,78C12A

1.1 LIST OF PIN FUNCTION (2/2)

Pin Name

I/O

Function

µPD78C11A and 78C12A sets MODE0 pin to “0” (low level), and MODE1 pin to “1” (high

level*)

µPD78C10A allows you to set MODE0, MODE1 pins to select 4K, 16K, or 64K bytes for the

size of the memory which is installed externally.

MODE0

MODE1

(Mode)

Input-output

MODE0

MODE1

External Memory

4K bytes

16K bytes

64K bytes

Also, when each of MODE0 and MODE1 pins is set to “1”*, it is synchronized to ALE to output

a control signal.

NMI

(Non-Maskable

Interrupt)

Input

Non-maskable interrupt input pin of the edge trigger (falling edge)

INT1

(Interrupt

Request)

A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a

zero-cross detection pin for AC input.

Input

8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling

edge) input.

AN7 to AN0

(AnalogInput)

V^AREF

(Reference

Voltage)

A common pin serving both as a standard voltage input pin for A/D converter and as a

control pin for A/D converter operation.

Input

AVDD

(Analog VDD)

Power supply pin for A/D converter.

GND pin for A/D converter.

AV^SS

(Analog VSS)

Crystal connection pins for system clock oscillation. X1 should be input when a clock is

supplied from outside. Input the clock of the reverse phase of X1 to X2.

X1, X2

(Crystal)

★

RESET

(Reset)

Input

Low-level active system reset input.

STOP

(Stop)

Control signal input pin in hardware STOP mode. The oscillation stops when a clock is

supplied from outside.

V^DD

Positive power supply pin.

GND pin.

VSS

Pull-up. Pull-up resister R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC is ns unit).

Remarks The µPD78C11A and µPD78C12A are pull-up resistor incorporation specifiable by mask option at ports

A, B and C.

µPD78C10A,78C11A,78C12A

1.2 PIN INPUT/OUTPUT CIRCUITS

Tables 1-1 and 1-2, and figures (1) to (15) show input- output circuits of each pin in a partially simplified form.

Table 1-1 Pin Type No. (µPD78C10A)

Pin Name

RESET

Type No.

PA7 to PA0

PB7 to PB0

PC1 to PC0

PC2/SCK

PC3/INT2

PC7 to PC4

PD7 to PD0

PF7 to PF0

NMI

ALE

STOP

MODE0

MODE1

AN3 to AN0

AN7 to AN4

V^AREF

INT1

Table 1-2 Pin Type No. (µPD78C11A and 78C12A)

Pin Name

Type No.

Pin Name

RESET

Type No.

PA7 to PA0

PB7 to PB0

PC1 to PC0

PC2/SCK

PC3/INT2

PC7 to PC4

PD7 to PD0

PF7 to PF0

NMI

5-A

8-A

10-A

5-A

ALE

STOP

MODE0

MODE1

AN3 to AN0

AN7 to AN4

V^AREF

INT1

µPD78C10A,78C11A,78C12A

(1) Type 1

V_DD

P-

N-

(2) Type 2

(3) Type 4

V_DD

output data

P-ch

OUT

N-ch

output disable

(4) Type 4-A

V_DD

output data

P-ch

OUT

output disable

N-ch

µPD78C10A,78C11A,78C12A

(5) Type 5

(6) Type 5-A

(7) Type 7

output data

IN/OUT

Type4

Type1

output disable

output data

IN/OUT

Type4-A

Type1

output disable

AV_DD

P-ch

N-ch

AV_DD

Sampling

AV_SS

Reference Voltage

AVSS

(From Voltage Tap of Series Resistance String)

(8) Type 8

output data

output disable

Type5

Type2

IN/OUT

MCC

µPD78C10A,78C11A,78C12A

(9) Type 8-A

output data

output disable

Type5-A

Type2

IN/OUT

MCC

(10) Type 9

self bias

enable

Type1

data

(11) Type 10

output data

output disable

Type5

IN/OUT

self bias

enable

Type9

MCC

µPD78C10A,78C11A,78C12A

(12) Type 10-A

output data

output disable

Type5-A

Type9

IN/OUT

self bias

enable

MCC

(13) Type 11

IN/OUT

output data

N-ch

Type1

(14) Type 12

Type7

Type2

Edge Detector

(15) Type 13

Type1

STOP Mode

AV_SS

µPD78C10A,78C11A,78C12A

1.3 PIN MASK OPTIONS

µPD78C11A and 78C12A has the following mask options, which can be selected bit-wise according to the

application.

Pin Name

PA7 to PA0

Mask Options

➀

➁

Pull-up resistor incorporated

Pull-up resistor not incorporated

PB7 to PB0

PC7 to PC0

Cautions 1. Zero-cross function can not be operated normally if pull-up resistor is incorporated

in PC3.

2. µPD78C10A has no mask option.

1.4 RECOMMENDED CONNECTION OF UNUSED PINS

Recommended Connection

PA7 to PA0

PB7 to PB0

PC7 to PC0

PD7 to PD0

PF7 to PF0

Connect to VSS or VDD via resistor

Leave open

ALE

STOP

Connect to VDD

Connect to VSS or VDD

Connect to VDD

INT1, NMI

AV^DD

AVAREF

Connect to VSS

AVSS

Connect to AVSS or AVDD

AN7 to AN0

µPD78C10A,78C11A,78C12A

2. DIFFERENCES BETWEEN µPD78C10A AND µPD78C11A, 78C12A

The difference between the µPD78C10A and µPD78C11A, 78C12A is whether or not there is an on-chip mask

programmable ROM. The memory map differs accordingly as described below.

(1) µPD78C10A

Since the µPD78C10A does not have an on-chip ROM, all memory, except the on-chip RAM area (addresses FF00H

to FFFFH) can be installed outside. The size of this external memory can be selected from among 4K bytes (0000H

to 0FFFH), 16K bytes (0000H to 3FFFH), and 64K bytes (0000H to FEFFH) by MODE0 and MODE1 pin setting as shown

in the following table and Fig. 2-1.

Control Pin

Operation Mode

External Memory

On-Chip RAM

MODE1 MODE0

4K bytes access

16K bytes access

64K bytes access

4K bytes (address 0000H to 0FFFH)

16K bytes (address 0000H to 3FFFH)

64K bytes (address 0000H to FEFFH)

Address FF00H to FFFFH

External memory is accessed by using PD7 to PD0 (multiplexed address/data bus), PF7 to PF0 (address bus), and

the RD, WR, and ALE signals. When 4K-byte or 16K-byte external memory is accessed PF7 to PF0 not used as address

lines can be used as general purpose input/output ports.

The size of external memory can be specified by MODE0 and MODE1 pin setting. Preset each bit of MEMORY

MAPPING reisters MM2, MM1, and MM0 to "0".

(2) µPD78C11A and 78C12A

The µPD78C11A has an on-chip mask programmable ROM at addresses 0000H to 0FFFH and RAM at addresses

FF00H to FFFFH. Externally, memory can be extended up to 60K bytes (addresses 1000H to FEFFH) in steps. The

µPD78C12A has an on-chip mask programmable ROM at address 0000H to 1FFFH and RAM at address FF00H to

FFFFH. Externally, memory can be extended up to 56K bytes (address 2000H to FEFFH) in steps. The size of the

external extension memory can be selected from among no external memory, 256 bytes, 4K bytes, 16K bytes, and

56K/60K bytes* by MEMORY MAPPING register setting. External memory can be accessed by using PD7 to PD0

(multiplexed address/data bus), PF7 to PF0 (address bus), and the RD, WR, and ALE signals. Programs and data

can be stored in external memory. PF7 to PF0 become address lines corresponding to the size of external memory.

The remaining pins can be used as general purpose input/output ports.

PF7

Port

AB15

PF6

Port

AB14

PF5

Port

PF4

Port

PF3

Port

PF2

Port

PF1

Port

AB9

PF0

Port

AB8

External Memory

Maximam 256 bytes

Maximum 4K bytes

Port

AB11

AB10

AB13

AB12

Maximum 16K bytes

Maximum 56K/60K bytes*

µPD78C11A: 60K bytes, µPD78C12A: 56K bytes

µPD78C10A,78C11A,78C12A

Fig. 2-1 µPD78C10A Memory Map

4K Bytes Access

16K Bytes Access

64K Bytes Access

0000H

0FFFH

External

Memory

External

Memory

External

Memory

Not Used

3FFFH

Not Used

FF00H

FFFFH

On-Chip RAM

MODE0 = 0

MODE1 = 0

MODE0 = 1

MODE1 = 0

MODE0 = 1

MODE1 = 1

µPD78C10A,78C11A,78C12A

3. RESET OPERATIONS

When RESET Input becomes low, the system reset is activated to create the following status.

• INTERRUPT ENABLE F/F is reset and interrupt is disabled.

• All the interrupt mask registers are set (1) and interrupt is masked.

• An interrupt request flag is reset (0) and hold interrupt is eliminated.

• Each bit of PSW is reset (0).

• 0000H is loaded into the program counter (PC).

• The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the MODE

CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the

ports (A, B, C, D, and F) become input port (output high-impedance).

• All the test flags but SB flag are reset (0).

• A timer mode register is set to FFH, and TIMER F/F is reset.

• The mode register (ETMM, EOM) of a timer/event counter is reset (0).

• The serial mode high register(SMH) of serial interface is reset (0), while the serial mode low register (SML) is

set to 48H.

• The A/D channel mode register of the A/D converter is reset (0).

• WR, RD, ALE signals become high-impedance.

• The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1).

• The internal timing generator is initialized.

• Data memory and the following register contents are undefined:

Stack pointer (SP)

Expansion accumulator (EA, EA’), accumulator (A, A’)

General register (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)

Output latch of each port

TIMER REG0, 1 (TM0, TM1)

TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1)

RAE bit of MEMORY MAPPING register

SB flag of test flag

When RESET input becomes high, the reset status is released. Then, execution of the program is started from

0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if necessary.

Table 3-1 shows the state of each hardware after reset.

Table 3-2 shows the state of each pin after reset.

µPD78C10A,78C11A,78C12A

Table 3-1 State of Each Hardware after Reset

State after Reset

Hardware

Power-on reset

Previous contents held.

Undefined

Write address data

Writing

by CPU

Reset input

during normal

operation

Internal data

memory

Address data other than the aboove

Operation other than writing by CPU

Previous contents held.

Reset input in standby mode

Expansion accumulator (EA, EA')

Accumulator (A, A')

Undefined

General register (B, C, D, E, H, L, B', C', D', E', H', L')

Working register vector register (V, V')

Program counter (PC)

0000H

Stack pointer (SP)

Undefined

Mode register (MA, MB, MC, MF)

FFH

Port

MCC register

00H

MM register (bits MM0 to MM2)

Output latch of each port

INTERRUPT ENABLE F/F

Undefined

Interrupt

Request flag

Mask register

FFH

Test flag (except SB flag)

Power-on reset

Standby flag (SB)

Standby mode

Previous contents held.

Contents immediately before

RESET input held

Reset input during normal operation

Timer mode register (TMM)

FFH

Timer

Timer F/F

Timer register (TM0, TM1)

Undefined

Timer/event counter mode register (ETMM)

Timer/event counter output mode register (EOM)

00H

Timer/event counter Timer/event counter register (ETM0, ETM1)

Timer/event counter capture register (ECPT)

Timer/event counter (ECNT)

Undefined

Serial mode high register (SMH)

Serial interface

00H

Serial mode low register (SML)

48H

A/D channel mode register (ANM)

MM register (MM3; RAE bit)

00H

Undefined

Zero cross mode register (ZC1, ZC2 bits)

µPD78C10A,78C11A,78C12A

Table 3-2 State of Each Pin after Reset

State after Reset

High-impedance

ALE

All ports (PA, PB, PC, PD, PF)

µPD78C10A,78C11A,78C12A

4. INSTRUCTION SET

4.1 IDENTIFIER/DESCRIPTION OF OPERAND

Identifier

Description

V, A, B, C, D, E, H, L

EAH, EAL, B, C, D, E, H, L

A, B, C

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF,

TXB, TM0, TM1, ZCM

sr1

sr2

sr3

sr4

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM

ETM0, ETM1

ECNT, ECPT

SP, B, D, H

V, B, D, H, EA

SP, B, D, H, EA

B, D, H

rp1

rp2

rp3

rpa

B, D, H, D+, H+, D–, H–

rpa1

rpa2

rpa3

B, D, H

B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte

D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte

8 bit immediate data

word

byte

bit

16 bit immediate data

8 bit immediate data

3 bit immediate data

CY, HC, Z

irf

NMI*, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB

NMI can also be described as FNMI.

Remarks

1. sr to sr4 (special register)

2. rp to rp3 (register pair)

4. f (flag)

CARRY

PORT A

ETMM

EOM

TIMER/EVENT

STACK POINTER

HALF CARRY

ZERO

PORT B

COUNTER MODE

TIMER/EVENT

PORT C

PORT D

COUNTER OUTPUT

MODE

5. irf (interrupt flag)

PORT F

MCC

MODE A

ANM

CR0

A/D CHANNEL MODE

A/D CONVERSION

RESULT 0 to 3

EXTENDED

ACCUMULATOR

NMI

FT0

FT1

NMI INPUT

INTFT0

MODE B

MODE C

INTFT1

3. rpa to rpa3 (rp addressing)

MODE CONTROL C

MODE F

CR3

TXB

RXB

SMH

SML

MKH

MKL

ZCM

INTF1

BUFFER

D+

H+

D–

H–

D++

H++

D + byte

H + A

H + B

H + EA

H + byte

(BC)

(DE)

(HL)

(DE)+

(HL)+

(DE)–

(HL)–

(DE)++

(HL)++

(DE + byte)

(HL + A)

(HL + B)

(HL + EA)

(HL + byte)

INTF2

TM0

TM1

TMM

ETM0

MEMORY MAPPING

TIMER REG0

TIMER REG1

TIMER MODE

TIMER/EVENT

COUNTER REG0

TIMER/EVENT

COUNTER REG1

TIMER/EVENT

COUNTER UPCOUNTER

TIMER/EVENT

COUNTER CAPTURE

FE0

FE1

FEIN

FAD

FSR

FST

INTFE0

SERIAL MODE High

SERIAL MODE Low

MASK High

INTFE1

INTFEIN

INTFAD

MASK Low

INTFSR

ZERO CROSS MODE

INTFST

ETM1

ECNT

ECPT

ERROR

OVERFLOW

ANALOG INPUT 4 to 7

AN4

AN7

STANDBY

µPD78C10A,78C11A,78C12A

4.2 SYMBOL DESCRIPTION OF OPERATION CODE

rpa

R¹

R⁰

reg

T²

T¹

T⁰

reg

A³A²A¹A⁰

addressing

EAH

EAL

(BC)

rpa1

(DE)

(HL)

rpa

(DE)+

(HL)+

(DE)-

rpa2

(HL)-

(DE + byte)

(HL + A)

(HL + B)

(HL + EA)

(HL + byte)

S5 S4 S3 S2 S1 S0

Special-reg

rpa3

C³C²C¹C⁰

sr1

sr2

MKH

MKL

ANM

SMH

SML

EOM

ETMM

TMM

MCC

addressing

(DE)

(HL)

(DE)++

(HL)++

(DE + byte)

(HL + A)

(HL + B)

(HL + EA)

(HL + byte)

TXB

RXB

TM0

TM1

CR0

CR1

CR2

CR3

ZCM

irf

I⁴

INTF

NMI

FT0

FT1

FE0

FE1

FEIN

FAD

FSR

FST

sr3

sr4

special-reg

ETM0

ETM1

ECNT

ECPT

AN4

AN5

AN6

AN7

rp1

P²

reg-pair

Q1 Q0

reg-pair

flag

rp2

rp3

µPD78C10A,78C11A,78C12A

4.3 INSTRUCTION EXECUTION TIME

1 state shown here is composed of 3 clock cycles. When a clock cycle of 15 MHz is used, the execution time should

be 200 ns (= 3 × 1/15µs). In this case, the 4-state instruction which is the minimum execution time should be execution

time of 0.8 µs.

Operation Code

Skip

Condition

Mnemonic

Operand

State

Operation

r1, A

0 0 0 1 1 T²T1 T0

r1 ← A

A ← r1

sr ← A

A ← sr1

A, r1

sr, A

A, sr1

0 0 0 0 1 T2 T1 T0

0 1 0 0 1 1 0 1 1 1 S5 S4 S3 S2 S1 S0

0 1 0 0 1 1 0 0 1 1 S5 S4 S3 S2 S1 S0

0 1 1 1 0 0 0 0 0 1 1 0 1 R2 R1 R0

MOV

r, word

word, r

r, byte

Low Adrs

High Adrs

r ← (word)

(word) ← r

r ← byte

0 1 1 1 1 R2 R1 R0

Data

0 1 1 1 0 0 0 0

0 1 1 0 1 R²R1 R0

MVI

Data

sr2 ← byte

sr2, byte

0 1 1 0 0 1 0 0 S³0 0 0 0 S2 S1 S0

wa, byte

rpa1, byte

Offset

Data

(V. wa) ← byte

(rpa1) ← byte

(V. wa) ← A

A ← (V. wa)

(rpa2) ← A

MVIW

MVIX

STAW

LDAW

STAX

LDAX

EXX

0 1 1 1 0 0 0 1

0 1 0 0 1 0 A¹A0

0 1 1 0 0 0 1 1

Offset

Data*1

0 0 0 0 0 0 0 1

A³0 1 1 1 A2 A1 A0

A3 0 1 0 1 A2 A1 A0

rpa2

7/13*3

rpa2

A ← (rpa2)

7/13*3

B ↔ B', C ↔ C', D ↔ D'

E ↔ E', H ↔ H', L ↔ L'

0 0 0 1 0 0 0 1

0 0 0 1 0 0 0 0

0 1 0 1 0 0 0 0

V, A ↔ V', A', EA ↔ EA'

EXA

H, L ↔ H', L'

EXH

(DE)⁺← (HL)⁺, C ← C – 1

End if borrow

BLOCK

0 0 1 1 0 0 0 1

1 0 1 1 0 1 P¹P0

(C + 1)

rp3^L← EAL, rp3H ← EAH

rp3, EA

EA, rp3

DMOV

EAL ← rp3^L, EAH ← rp3H

1 0 1 0 0 1 P1 P0

Note 1. Instruction Group

2. 16-bit data transfer instructions

Operation Code

Skip

Condition

Mnemonic

DMOV

Operand

sr3, EA

State

Operation

0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 U0

1 1 0 0 0 0 0 V0

sr3 ← EA

EA ← sr4

EA, sr4

word

(word) ← C, (word + 1) ← B

(word) ← E, (word + 1) ← D

(word) ← L, (word + 1) ← H

(word) ← SP^L, (word + 1) ← SPH

(rpa3) ← EAL, (rpa3 + 1) ← EAH

C ← (word), B ← (word + 1)

E ← (word), D ← (word + 1)

SBCD

SDED

0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0

0 0 1 0 1 1 1 0

Low Adrs

High Adrs

word

rpa3

0 0 1 1 1 1 1 0

0 0 0 0 1 1 1 0

SHLD

SSPD

STEAX

LBCD

Data*2

0 1 0 0 1 0 0 0 1 0 0 1 C3 C2 C1 C0

0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1

14/20

word

Low Adrs

High Adrs

word

rpa3

rp1

LDED

LHLD

LSPD

LDEAX

PUSH

POP

0 0 1 0 1 1 1 1

0 0 1 1 1 1 1 1

0 0 0 0 1 1 1 1

L ← (word), H ← (word + 1)

SP^L← (word), SPH ← (word + 1)

EAL ← (rpa3), EAH ← (rpa3 + 1)

1 0 0 0 C3 C2 C1 C0

Data*2

0 1 0 0 1 0 0 0

1 0 1 1 0 Q²Q1 Q0

1 0 1 0 0 Q2 Q1 Q0

14/20

(SP – 1) ← rp1^H, (SP – 2) ← rp1L

SP ← SP – 2

rp1^L← (SP), rp1H ← (SP + 1)

SP ← SP + 2

rp1

Low Byte

High Byte

rp2 ← word

LXI

rp2, word

0 P2 P1 P0 0 1 0 0

C ← (PC + 3 + A)

B ← (PC + 3 + A + 1)

TABLE

0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0

0 1 1 0 0 0 0 0 1 1 0 0 0 R2 R1 R0

A ← A + r

A, r

ADD

ADC

r, A

A, r

0 1 0 0

1 1 0 1

r ← r + A

A ← A + r + CY

r ← r + A + CY

r, A

0 1 0 1

Note 1. Instruction Group

2. 8-bit operation instructions (register)

Operation Code

Skip

Condition

Mnemonic

ADDNC

Operand

State

Operation

No Carry

A, r

r, A

A, r

r, A

0 1 1 0 0 0 0 0 1 0 1 0 0 R2 R1 R0

A ← A + r

r ← r + A

A ←A – r

r ← r – A

0 0 1 0

1 1 1 0

0 1 1 0

SUB

A ← A – r – CY

r ← r – A – CY

A ← A – r

A, r

r, A

A, r

r, A

1 1 1 1

0 1 1 1

1 0 1 1

0 0 1 1

SBB

Borrow

SUBNB

ANA

r ← r – A

A ← A

r ← r

A, r

r, A

A, r

r, A

A, r

r, A

1 0 0 0 1 R²R1 R0

0 0 0 0

1 0 0 1

A ← A

r ← r

ORA

XRA

GTA

0 0 0 1

1 0 0 1 0 R²R1 R0

0 0 0 1

A ← A

r ← r

Borrow

A, r

r, A

A, r

1 0 1 0 1 R²R1 R0

0 0 1 0

A – r – 1

r – A – 1

A – r

1 0 1 1

Borrow

LTA

r, A

A, r

0 0 1 1

1 1 1 0

r – A

A – r

Borrow

No Zero

NEA

r, A

0 1 1 0

r – A

Note Instruction Group

Operation Code

Skip

Condition

Mnemonic

EQA

Operand

State

Operation

Zero

A, r

r, A

A, r

0 1 1 0 0 0 0 0 1 1 1 1 1 R2 R1 R0

A – r

r – A

0 1 1 1

1 1 0 0

1 1 0 1

Zero

ONA

No Zero

Zero

OFFA

rpa

0 1 1 1 0 0 0 0 1 1 0 0 0 A2 A1 A0

A ← A + (rpa)

ADDX

ADCX

1 1 0 1

1 0 1 0

1 1 1 0

A ← A + (rpa) + CY

A ← A + (rpa)

ADDNCX

SUBX

No Carry

A ← A – (rpa)

A ← A – (rpa) – CY

rpa

1 1 1 1

SBBX

Borrow

A ← A – (rpa)

A ← A (rpa)

A – (rpa) – 1

A – (rpa)

SUBNBX

ANAX

ORAX

XRAX

GTAX

1 0 1 1

1 0 0 0 1 A²A1 A0

1 0 0 1

1 0 0 1 0 A2 A1 A0

1 0 1 0 1 A2 A1 A0

Borrow

LTAX

NEAX

EQAX

rpa

1 0 1 1

1 1 1 0

1 1 1 1

Borrow

No Zero

Zero

rpa

A – (rpa)

ONAX

1 1 0 0

1 1 0 1

(rpa)

No Zero

Zero

OFFAX

Note Instruction Group

Operation Code

Data

Skip

Condition

Mnemonic

Operand

A, byte

State

Operation

0 1 0 0 0 1 1 0

A ← A + byte

r ← r + byte

ADI

r, byte

0 1 1 1 0 1 0 0 0 1 0 0 0 R2 R1 R0

Data

sr2, byte

A, byte

0 1 1 0

S³1 0 0 0 S2 S1 S0

Data

sr2 ← sr2 + byte

0 1 0 1 0 1 1 0

A ← A + byte + CY

r, byte

0 1 1 1 0 1 0 0 0 1 0 1 0 R2 R1 R0

r ← r + byte + CY

sr2 ← sr2 + byte + CY

A ← A + byte

ACI

Data

S³1 0 1 0 S2 S1 S0

Data

sr2, byte

A, byte

r, byte

0 1 1 0

0 0 1 0 0 1 1 0

0 1 1 1 0 1 0 0

No Carry

r ← r + byte

ADINC

SUI

0 0 1 0 0 R2 R1 R0

sr2, byte

A, byte

r, byte

sr2 ← sr2 + byte

A ← A – byte

0 1 1 0

S3 0 1 0 0 S2 S1 S0

Data

No Carry

0 1 1 0 0 1 1 0

0 1 1 1 0 1 0 0 0 1 1 0 0 R2 R1 R0

Data

r ← r – byte

sr2 ← sr2 – byte

A ← A – byte – CY

r ← r – byte – CY

sr2, byte

A, byte

r, byte

0 1 1 0

S3 1 1 0 0 S2 S1 S0

Data

0 1 1 1 0 1 1 0

0 1 1 1 0 1 0 0

SBI

0 1 1 1 0 R²R1 R0

sr2, byte

A, byte

r, byte

S3 1 1 1 0 S2 S1 S0

Data

0 1 1 0

sr2 ← sr2 – byte – CY

A ← A – byte

Borrow

0 0 1 1 0 1 1 0

r ← r – byte

0 1 1 1 0 1 0 0 0 0 1 1 0 R²R1 R0

SUINB

ANI

Borrow

sr2, byte

A, byte

0 1 1 0

sr2 ← sr2 – byte

A ← A byte

S3 0 1 1 0 S2 S1 S0

Data

0 0 0 0 0 1 1 1

r ← r byte

0 1 1 1 0 1 0 0

r, byte

0 0 0 0 1 R2 R1 R0

Note Instruction Group

Operation Code

0 1 1 0 0 1 0 0 S3 0 0 0 1 S2 S1 S0

Skip

Condition

Mnemonic

ANI

Operand

sr2, byte

State

Operation

sr2 ← sr2 byte

Data

A, byte

r, byte

0 0 0 1 0 1 1 1

Data

A ← A byte

r ← r byte

0 1 1 1 0 1 0 0 0 0 0 1 1 R2 R1 R0

Data

ORI

XRI

sr2, byte

0 1 1 0

S3 0 0 1 1 S2 S1 S0

sr2 ← sr2 byte

A, byte

r, byte

0 0 0 1 0 1 1 0

0 1 1 1 0 1 0 0

0 1 1 0

Data

A ← A byte

r ← r byte

sr2 ← sr2 byte

A – byte– 1

0 0 0 1 0 R²R1 R0

S³0 0 1 0 S2 S1 S0

Data

sr2, byte

A, byte

Borrow

0 0 1 0 0 1 1 1

Borrow

r – byte – 1

sr2 – byte – 1

A – byte

r, byte

0 1 1 1 0 1 0 0

0 1 1 0

GTI

LTI

0 0 1 0 1 R2 R1 R0

S3 0 1 0 1 S2 S1 S0

Data

sr2, byte

A, byte

0 0 1 1 0 1 1 1

0 1 1 1 0 1 0 0

0 1 1 0

Borrow

No Zero

Zero

r – byte

r, byte

0 0 1 1 1 R2 R1 R0

S3 0 1 1 1 S2 S1 S0

Data

sr2, byte

A, byte

sr2 – byte

A – byte

0 1 1 0 0 1 1 1

0 1 1 1 0 1 0 0

0 1 1 0

NEI

EQI

0 1 1 0 1 R2 R1 R0

S3 1 1 0 1 S2 S1 S0

Data

r, byte

r – byte

sr2 – byte

A – byte

sr2, byte

A, byte

0 1 1 1 0 1 1 1

r, byte

0 1 1 1 0 1 0 0 0 1 1 1 1 R2 R1 R0

0 1 1 0 S3 1 1 1 1 S2 S1 S0

r – byte

Zero

sr2, byte

sr2 – byte

Note Instruction Group

Operation Code

Data

Skip

Condition

Mnemonic

Operand

A, byte

State

Operation

0 1 0 0 0 1 1 1

byte

No Zero

Zero

ONI

r, byte

0 1 1 1 0 1 0 0 0 1 0 0 1 R2 R1 R0

Data

sr2, byte

A, byte

0 1 1 0

S³1 0 0 1 S2 S1 S0

Data

sr2 byte

0 1 0 1 0 1 1 1

byte

r, byte

sr2, byte

0 1 1 1 0 1 0 0 0 1 0 1 1 R2 R1 R0

S³1 0 1 1 S2 S1 S0

0 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0

1 1 0 1

OFFI

Data

Zero

0 1 1 0

sr2 byte

ADDW

ADCW

offset

A ← A +(V. wa)

A ← A + (V. wa) + CY

A ← A + (V. wa)

A ← A – (V. wa)

A ← A – (V. wa) – CY

A ← A – (V. wa)

A ← A (V. wa)

ADDNCW

SUBW

1 0 1 0

No Carry

1 1 1 0

SBBW

1 1 1 1

Borrow

1 0 1 1

SUBNBW

ANAW

1 0 0 0 1 0 0 0

1 0 0 1

ORAW

XRAW

GTAW

LTAW

1 0 0 1 0 0 0 0

1 0 1 0 1 0 0 0

1 0 1 1

A ← A (V. wa)

Borrow

A – (V. wa) – 1

A – (V. wa)

Borrow

NEAW

EQAW

A – (V. wa)

No Zero

Zero

1 1 1 0

1 1 1 1

(V. wa)

ONAW

1 1 0 0

No Zero

Note Instruction Group

Operation Code

0 1 1 1 0 1 0 0 1 1 0 1 1 0 0 0

Skip

Condition

Mnemonic

OFFAW

Operand

State

Operation

Offset

(V. wa)

Zero

ANIW

ORIW

GTIW

wa, byte

0 0 0 0 0 1 0 1

0 0 0 1

(V. wa) ← (V. wa) byte

(V. wa) – byte – 1

Offset

Data

Borrow

0 0 1 0

wa, byte

(V. wa) – byte

(V. wa) byte

LTIW

NEIW

EQIW

ONIW

0 0 1 1

0 1 1 0

0 1 1 1

0 1 0 0

Borrow

No Zero

Zero

No Zero

Zero

wa, byte

EA, r2

0 1 0 1

(V. wa) byte

EA ← EA + r2

OFFIW

EADD

0 1 0 0 0 0 R1 R0

1 1 0 0 0 1 P1 P0

1 1 0 1

0 1 1 1 0 0 0 0

0 1 0 0

EA, rp3

EA, r2

DADD

DADC

EA ← EA + rp3

EA ← EA + rp3 +CY

EA ← EA + rp3

EA ← EA – r2

No Carry

DADDNC

ESUB

1 0 1 0

0 0 0 0

0 1 0 0

0 1 1 0 0 0 R1 R0

1 1 1 0 0 1 P1 P0

1 1 1 1

EA, rp3

DSUB

EA ← EA – rp3

DSBB

EA ← EA – rp3 – CY

EA ← EA – rp3

Borrow

1 0 1 1

DSUBNB

DAN

DOR

EA, rp3

1 0 0 0 1 1 P1 P0

1 0 0 1

EA ← EA rp3

1 0 0 1 0 1 P1 P0

DXR

EA, rp3

Note Instruction Group

Operation Code

Skip

Condition

Mnemonic

Operand

State

Operation

Borrow

EA, rp3

0 1 1 1 0 1 0 0 1 0 1 0 1 1 P1 P0

EA – rp3 – 1

EA – rp3

DGT

DLT

DNE

DEQ

EA, rp3

1 0 1 1

1 1 1 0

1 1 1 1

Borrow

No Zero

Zero

EA – rp3

EA, rp3

1 1 0 0

1 1 0 1

EA rp3

DON

DOFF

MUL

DIV

No Zero

Zero

EA rp3

0 1 0 0 1 0 0 0

EA ← A × r2

0 0 1 0 1 1 R1 R0

0 0 1 1

EA ← EA ÷ r2, r2 ← Remainder

r2 ← r2 + 1

INR

Carry

0 1 0 0 0 0 R1 R0

0 0 1 0 0 0 0 0

0 0 P1 P0 0 0 1 0

1 0 1 0 1 0 0 0

0 1 0 1 0 0 R1 R0

0 0 1 1 0 0 0 0

(V. wa) ← (V. wa) + 1

rp ← rp + 1

Offset

INRW

INX

EA ← EA + 1

r2 ← r2 – 1

Borrow

DCR

(V. wa) ← (V. wa) – 1

DCRW

Offset

0 0 P¹P0 0 0 1 1

1 0 1 0 1 0 0 1

0 1 1 0 0 0 0 1

0 1 0 0 1 0 0 0

rp ← rp – 1

DCX

DAA

EA ← EA – 1

Decimal Adjust Accumulator

STC

CLC

0 0 1 0 1 0 1 1

0 0 1 0 1 0 1 0

CY ← 1

CY ← 0

A ← A + 1

0 0 1 1 1 0 1 0

NEGA

Note 1. Instruction Group

2. Multiplication/division instructions

3. Other operation instructions

Operation Code

0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 0

Skip

Condition

Mnemonic

Operand

State

Operation

Rotate Left Digit

Rotate Right Digit

r2^{m + 1}← r2 , r2 ← CY, CY ← r2

, r2 ← CY, CY ← r2

, r2 ← 0, CY ← r2

, EA ← CY, CY ← EA15

, EA15 ← CY, CY ← EA

, EA ← 0, CY ← EA15

, EA15 ← 0, CY ← EA

RLD

RRD

RLL

RLR

1 0 0 1

0 1 R

0 0 R

r2m – 1 ← r2

0 0 1 0 0 1 R

r2m + 1 ← r2

r2m – 1 ← r2

r2m + 1 ← r2

r2m – 1 ← r2

SLL

SLR

0 0 R

SLLC

SLRC

0 0 0 0 0 1 R

0 0 R

Carry

EAn + 1 ← EA

DRLL

DRLR

DSLL

DSLR

1 0 1 1 0 1 0 0

0 0 0 0

EAn – 1 ← EA

1 0 1 0 0 1 0 0

0 0 0 0

EA^{n + 1}← EA

EAn – 1 ← EA

PC ← word

word

0 1 0 1 0 1 0 0

0 0 1 0 0 0 0 1

Low Adrs

High Adrs

JMP

PCH

← B, PC ← C

jdisp 1

word

1 1

PC ← PC + 1 + jdisp 1

jdisp

0 1 0 0 1 1 1

PC ← PC + 2 + jdisp

PC ← EA

JRE

JEA

0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0

(SP – 1) ← (PC + 3)

PC ← word, SP ← SP – 2

(SP – 1) ← (PC + 2) , (SP – 2) ← (PC + 2)

PC ← B, PC ← C, SP ← SP – 2

(SP – 1) ← (PC + 2) , (SP – 2) ← (PC + 2)

, (SP – 2) ← (PC + 3)

Low Adrs

CALL

CALB

word

High Adrs

0 1 0 0 0 0 0 0

0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1

CALF

0 1 1 1 1

PC15 – 11 ← 00001, PC10 – 0 ← fa, SP ← SP – 2

Note Instruction Group

Operation Code

Skip

Condition

Mnemonic

Operand

word

State

Operation

(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L

PCL←(128+2ta),PCH←(129+2ta),SP←SP–2

1 0 0

CALT

SOFTI

RET

(SP – 1) ←PSW, (SP – 2)← (PC + 1)H, (SP – 3)

← (PC + 1)^L, PC ← 0060H, SP ← SP – 3

0 1 1 1 0 0 1 0

1 0 1 1 1 0 0 0

1 0 0 1

PCL ← (SP), PCH ← (SP + 1)

SP ←SP + 2

Uncondi-

tional skip

PC^L← (SP), PCH ← (SP + 1), SP ← SP +2

PC ← PC + n

PC^L← (SP), PCH ← (SP + 1)

PSW ← (SP + 2), SP ← SP + 3

RETS

0 1 1 0 0 0 1 0

0 1 0 1 1 B2 B1 B0

0 1 0 0 1 0 0 0

RETI

(V. wa)bit

= 1

Offset

0 0 0 0 1 F²F1 F0

0 0 0 1

BIT

bit, wa

Skip if (V. wa) bit = 1

Skip if f = 1

f = 1

Skip if f = 0

SKN

f = 0

Skip if irf = 1, then reset irf

SKIT

SKNIT

NOP

irf

0 1 0 I⁴I3 I2 I1 I0

0 1 1 I4 I3 I2 I1 I0

irf = 1

irf = 0

Skip if irf = 0

Reset irf, if irf = 1

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0

1 0 1 1 1 0 1 0

No Operation

Enable Interrupt

Disable Interrupt

Set Halt Mode

HLT

0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1

0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1

STOP

Set Stop Mode

* 1. Data is B2 if rpa2 = D + byte, H + byte.

2. Data is B3 if rpa3 = D + byte, H + byte.

3. In the State item, a figure is in the right side of slash if rpa2 and rpa3 are D + byte, H + A, H + B, H + EA, H + byte.

Remarks The idle state when each instruction is skipped is different from the execution state as shown below.

1-byte instruction

2-byte instruction (with *)

2-byte instruction

Instruction Group

Call instructions

4 states

7 states

8 states

3-byte instruction (with *)

3-byte instruction

10 states

11 states

14 states

4-byte instruction

Note 1.

µPD78C10A,78C11A,78C12A

5. LIST OF MODE REGISTERS

Read/

Write

Name of Mode Registers

Function

MODE A register

MODE B register

Specifies bit-wise the input/output of the port A.

Specifies bit-wise the input/output of the port B.

MODE CONTROL

C register

MCC

Specifies bit-wise the port/control mode of the port C.

MODE C register

Specifies bit-wise the input/output of the port C which is in port mode.

Specifies the port/extension mode of port D and port F.

MEMORY MAPPING

MODE F register

Specifies bit-wise the input/output of the port F which is in port mode.

Specifies operating mode of timer.

TMM

Timer mode register

R/W

Timer/event counter

mode register

ETMM

EOM

Specifies the operating mode of timer/event counter.

Control the output level of CO0 and CO1.

Timer/event counter

output mode register

R/W

SML

SMH

MKL

MKH

Serial mode register

Specifies the operating mode of serial interface.

Specifies the enable/disable of the interrupt request.

R/W

Interrupt mask register

R/W

A/D channel mode

ANM

ZCM

R/W

Specifies the operating mode of A/D converter.

Zero-cross mode

Specifies the operation of zero-cross detector circuit.

µPD78C10A,78C11A,78C12A

6. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

PARAMETER

SYMBOL

V^DD

TEST CONDITIONS

RATING

–0.5 to +7.0

AVSS to VDD +0.5

–0.5 to +0.5

–0.5 to VDD +0.5

4.0

UNIT

Power supply voltage

AVDD

AVSS

Input voltage

Output voltage

All output pins

Output current low

Output current high

IOL

IOH

Total of all output pins

All output pins

100

–2.0

Total of all output pins

–50

A/D converter reference

input voltage

–0.5 to AVDD +0.3

–40 to +85

VAREF

Operating ambient

temperature

T^A

°C

Storage temperature

T^stg

–65 to +150

°C

★

Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of

the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit

of the value at which the product can be used without physical damages. Be sure not to exceed or fall

below this value when using the product.

µPD78C10A,78C11A,78C12A

OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V,

V^DD–0.8 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)

RESONATOR

RECOMMENDED CIRCUIT

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

MHz

A/D converter not

used

Ceramic*1

crystal

Oscillator frequency (fXX)

resonator*2

A/D converter used

5.8

MHz

A/D converter not

used

X1 input frequency (fX)

A/D converter used

5.8

MHz

External

clock

X1 rise time,

fall time (tr, tf)

HCMOS

Inverter

X1 input high, low

level width (t ^H, t L)

250

Cautions 1. Place oscillator circuit as close as possible to X1, X2 pins.

2. Ensure that no other signal lines pass through the shadow area.

1. The ceramic oscillators and external capacitance given in the following

table are recommended.

RECOMMENDED CONSTANTS

MAKER

PRODUCT NAME

CSA7.37MT

C2[pF]

C1[pF]

On-chip

CST7.37MTW

CSA12.0MT

CST12.0MTW

CSA15.00MX001

FCR8.0MC

On-chip

Murata Mfg. Co., Ltd

On-chip

FCR10.0MC

On-chip

TDK Corp.

On-chip

FCR12.0OMC

FCR15.0MC

2. When a crystal oscillator is used, the following external capacitance is

recommended.

C1 = C2 = 10 pF

µPD78C10A,78C11A,78C12A

CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)

PARAMETER

Input capacitance

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

C^I

C^IO

f^C= 1 MHz

Unmeasured pins returned to 0 V

Output capacitance

Input-output capacitance

µPD78C10A,78C11A,78C12A

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

0.8

UNIT

All except RESET, STOP, NMI,

SCK, INT1, TI, AN4 to AN7

VIL1

Input voltage low

RESET, STOP, NMI, SCK, INT1,

TI, AN4 to AN7

VIL2

V1IH

0.2 VDD

VDD

All except RESET, STOP, NMI,

SCK, INT1, TI, AN4 to AN7, X1, X2

2.2

Input voltage

high

RESET, STOP, NMI, SCK, INT1,

TI, AN4 to AN7, X1, X2

0.8 VDD

VDD

VIH2

VOL

Output voltage low

IOL = 2.0 mA

0.45

VDD

–1.0

IOH = –1.0 mA

Output voltage

high

VOH

VDD

–0.5

IOH = –100 µA

Input current

INT1*1, TI(PC3)*2 ; 0 V ≤ VI ≤ VDD

±200

±10

µA

All except INT1, TI (PC3),

0 V ≤ VI ≤ VDD

Input leakage

current

ILI

µA

Output leakage

current

ILO

0 V ≤ VO ≤ VDD

±10

AIDD1

AI^DD2

IDD1

Operating mode fXX = 15 MHz

STOP mode

0.5

1.3

µA

AV^DDpower

supply current

Operating mode fXX = 15 MHz

HALT mode fXX = 15 MHz

VDD power

supply current

I^DD2

Data retention

voltage

Hardware/software STOP mode

2.5

VDDDR

IDDDR

Hardware/software*3

V^DDDR= 2.5 V

µA

Data retention

current

STOP mode

VDDDR = 5 V ±10%

3.5 V ≤ VDD ≤ 5.5 V,

VI = 0 V

Pull-up resistor*4

Ports A, B and C

kΩ

Caution For a detailed description of the hardware STOP mode, refer to the 87AD Series mPD78C18 User's

Manual.

1. If self-bias should be generated by ZCM register.

2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register.

3. If self-bias is not generated.

4. µPD78C11A and 78C12A only.

µPD78C10A,78C11A,78C12A

AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V)

Read/write Operation:

PARAMETER

SYMBOL

tCYC

t^AL

TEST CONDITIONS

MIN.

MAX.

250

UNIT

X1 input cycle time

Address setup time (to ALE ↓ )

Address hold time (from ALE ↓ )

RD ↓ delay time from address

Address float time from RD ↓

Data input time from address

Data input time from ALE ↓

Data input time from RD ↓

RD ↓ delay time from ALE ↓

Data hold time (from RD ↑ )

ALE ↑ delay time from RD ↑

tLA

fXX = 15 MHz, CL = 100 pF

tAR

100

tAFR

tAD

CL = 100 pF

250

135

120

t^LDR

tRD

fXX = 15 MHz, CL = 100 pF

tLR

tRDH

t^RL

CL = 100 pF

fXX = 15 MHz, CL = 100 pF

In Data Read

fXX = 15 MHz, CL = 100 pF

215

415

RD low level width

tRR

In OP Code Fetch

f^XX= 15 MHz, CL = 100 pF

ALE high level width

tLL

t^ML

tLM

tIL

fXX = 15 MHz, CL = 100 pF

M1 setup time (to ALE ↓ )

M1 hold time (from ALE ↓ )

IO/M setup time (to ALE ↓ )

IO/M hold time (from ALE ↓ )

WR ↓ delay time from address

Data output time from ALE ↓

Data output time from WR ↓

WR ↓ delay time from ALE ↓

Data setup time (to WR ↑ )

Data hold time (from WR ↑ )

ALE ↑ delay time from WR ↑

WR low level width

fXX = 15 MHz

t^LI

tAW

tLDW

tWD

tLW

tDW

tWDH

tWL

tWW

100

fXX = 15 MHz, CL = 100 pF

CL = 100 pF

180

100

165

fXX = 15 MHz, CL = 100 pF

215

µPD78C10A,78C11A,78C12A

Serial Operation :

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

800

400

1.6

MAX.

UNIT

µs

SCK input

SCK cycle time

tCYK

SCK output

SCK input

335

160

700

335

160

700

SCK low level width

SCK high level width

tKKL

SCK output

SCK input

tKKH

SCK output

R^XD setup time (to SCK ↑ )

R^XD hold time (from SCK ↑ )

TXD delay time from SCK ↓

tRXK

tKRX

tKTX

210

1. If clock rate is × 1 in asynchronous mode, synchronous mode, or I/O interface mode.

2. If clock rate is × 16 or × 64 in asynchronous mode.

Remarks The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF.

Zero-Cross Characteristics :

PARAMETER

Zero-cross detection input

Zero-cross accuracy

SYMBOL

V^ZX

TEST CONDITIONS

MIN.

MAX.

1.8

UNIT

VACP-P

AC combination

60 Hz sine wave

AZX

±135

Zero-cross detection input

frequency

fZX

0.05

kHz

Other Operation :

PARAMETER

SYMBOL

tTIH, tTIL

tCI1H, tCI1L

tCI2H,tCI2L

tNIH, tNIL

tI1H, tI1L

TEST CONDITIONS

MIN.

MAX.

UNIT

tCYC

µs

TI high, low level width

Event count mode

CI high, low level width

Pulse width test mode

NMI high, low level width

INT1 high, low level width

INT2 high, low level width

AN4 to AN7, low level width

RESET high, low level width

tCYC

µs

tI2H, tI2L

tANH, tANL

tRSH, tRSL

µPD78C10A,78C11A,78C12A

A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5.0 V ±10 %, VSS = AVSS = 0 V,

VDD –0.5 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)

PARAMETER

Resolution

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Bits

3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns

4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns

±0.8%

±0.6%

FSR

Absolute accuracy*

T^A= –10 to +70 °C,

4.0 V ≤ V^AREF≤ AVDD, 66 ns ≤ tCYC ≤ 170 ns

±0.4%

FSR

66 ns ≤ tCYC ≤ 110 ns

576

432

tCYC

Conversion time

tCONV

tSAMP

110 ns ≤ tCYC ≤ 170 ns

66 ns ≤ tCYC ≤ 110 ns

Sampling time

110 ns ≤ tCYC ≤ 170 ns

Analog input voltage

VIAN

AN0 to AN7 (including unused pins)

–0.3

VAREF +0.3

Analog input

impedance

R^AN

MΩ

★

Reference voltage

VAREF current

V^AREF

I^AREF1

IAREF2

AI^DD1

AIDD2

3.4

AVDD

3.0

1.5

1.3

Operating mode

STOP mode

1.5

0.7

0.5

µA

Operating mode fXX = 15 MHz

STOP mode

AVDD power supply

current

Quantization error (±1/2 LSB) is not included.

AC Timing Test Point

V^DD– 1.0 V

2.2 V

0.8 V

2.2 V

0.8 V

Test Points

0.45 V

µPD78C10A,78C11A,78C12A

tCYC-Dependent AC Characteristics Expression

PARAMETER

EXPRESSION

MIN./MAX.

MIN.

UNIT

tAL

tLA

tAR

tAD

t^LDR

tRD

tLR

tRL

2T – 100

T – 30

MIN.

3T – 100

7T – 220

5T – 200

4T – 150

T – 50

MIN.

MAX.

MIN.

2T – 50

MIN.

4T – 50 (In data read)

tRR

MIN.

7T – 50 (In OP code fetch)

t^LL

2T – 40

MIN.

MAX.

MIN.

tML

t^LM

tIL

2T – 100

T – 30

2T – 100

tLI

T – 30

t^AW

tLDW

t^LW

tDW

tWDH

t^WL

tWW

3T – 100

T + 110

T – 50

4T – 100

2T – 70

2T – 50

4T – 50

12T (SCK input)*1/6T (SCK input)*2

24T (SCK output)

tCYK

tKKL

tKKH

MIN.

5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2

12T – 100 (SCK output)

5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2

12T – 100 (SCK output)

1. If clock rate is ×1, in asynchronous mode, synchronous mode, or I/O interface mode.

2. If clock rate is 16 × 64, in asynchronous mode.

Cautions 1. T = tCYC = 1/fXX

2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX).

µPD78C10A,78C11A,78C12A

Timing Waveform

Read operation

tCYC

PF7 - 0

PD7 - 0

ALE

Address (Upper)

tAD

Address (Lower)

Read Data

tLDR

t^RDH

tRL

tLL

tLA

tAFR

tAL

tRD

tRR

tLR

tAR

tML

tIL

tLM

tLI

MODE1

(M1)*1

MODE0

(IO/M)*2

1. When MODE1 pin is pulled up, M1 signal is output to MODE1 pin in the 1st OP code fetch cycle.

2. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register read cycle.

Write operation

PF7 - 0

PD7 - 0

ALE

Address (Upper)

tLDW

Write Data

Address (Lower)

tDW

tWDH

tWL

tLL

tLA

tWD

tWW

tAL

tLW

tLI

tAW

tIL

MODE0

(IO/M)*3

3. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register write cycle.

µPD78C10A,78C11A,78C12A

Serial Operation

tCYK

tKKL

tKKH

SCK

tKTX

T^XD

RXD

tRXK

tKRX

Timer Input Timing

tTIH

tTIL

Timer/Event Counter Input Timing

Event Counter Mode

tCI1H

tCI1L

Pulse Width Test Mode

tCI2H

tCI2L

µPD78C10A,78C11A,78C12A

Interrupt Input Timing

tNIH

tI1L

tI2H

tNIL

tI1H

tI2L

NMI

INT1

INT2

Reset Input Timing

tRSH

tRSL

RESET

0.8 VDD

0.2 VDD

External Clock Timing

Φ H

0.8 VDD

0.8 V

tΦ H

tCYC

µPD78C10A,78C11A,78C12A

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

(TA = –40 to +85 °C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

2.5

TYP.

MAX.

5.5

UNIT

Data retention power

supply voltage

VDDDR

VDDDR = 2.5 V

µA

µs

Data retention power

supply current

I^DDDR

V^DDDR= 5 V ±10%

★

VDD rise/fall time

tRVD, tFVD

tSSTVD

200

STOP setup time

(to VDD)

12T +0.5

µs

STOP hold time

(from V^DD)

tHVDST

12T +0.5

Data Retention Timing

90 %

10 %

V^DD

VDDDR

t^FVD

tRVD

tHVDST

tSSTVD

VIH2

VIL2

STOP

µPD78C10A,78C11A,78C12A

7. CHARACTERISTIC CURVES (REFERENCE VALUES)

IDD1, IDD2 vs VDD

= 25 ˚C, fXX = 15 MHz)

IDD1 (TYP.)

IDD2 (TYP.)

4.5

5.0

5.5

Power Supply Voltage V^DD[V]

IDD1, IDD2 vs fXX

(TA

= 25 ˚C, VDD = 5 V)

DD1 (TYP.)

DD2 (TYP.)

Oscillator Frequency f^XX[MHz]

µPD78C10A,78C11A,78C12A

IOL vs VOL

(TA

= 25 ˚C, VDD = 5 V)

2.5

2.0

1.5

TYP.

1.0

0.5

0.1

0.2

0.3

0.4

0.5

Output Voltage Low V^OL[V]

IOH vs VOH

(TA = 25 ˚C, VDD = 5 V)

–1.5

–1.0

–0.5

TYP.

0.1

0.2

0.3

0.4

0.5

Power Supply Voltage – Output Voltage High V^DD– VOH [V]

µPD78C10A,78C11A,78C12A

IDDDR vs VDDDR

(TA = 25 ˚C)

TYP.

Data Retention Power Supply Voltage V^DDDR[V]

µPD78C10A,78C11A,78C12A

8. DIFFERENCES IN 87AD SERIES PRODUCTS (1/2)

Product Name

µPD7810H, 7811H

µPD78C10, 78C11*1

µPD7810, 7811*1

Item

159 kinds (STOP instruction

added)

Number of instructions

158 kinds

ROM less (µPD7810)

ROM less (µPD7810H)

4K × 8 bits (µPD7811H)

ROM less (µPD78C10)

4K × 8 bits (µPD78C11)

On-chip ROM

4K × 8 bits (µPD7811)

On-chip RAM

256 × 8 bits

Nnmber of special registers

Operating frequency

Power supply voltage

Operating temperature range

28 (ZCM register added)

4 to 10 MHz

4 to 15 MHz*2

5 V ±10 %

10 to 12 MHz

5 V ±5 %

4 to 15 MHz

5 V ±10 %

–40 to +85 °C

–10 to +70 °C

Three kinds: HALT mode,

software STOP mode, and

hardware STOP mode. All

data of on-chip RAM are

held by low power supply

voltage (2.5V) in software/

hardware STOP mode.

Thirty-two bytes of the on-chip RAM 256 bytes of data

are held by low power supply voltage (3.2 V)

Standby function

Number of HALT instruction state

CPU operation

HALT

M3 T2 cycle repeated

High level

Stop

mode

ALE

Low level

Zero crossing detector self-bias

control

Self-bias control possible (by

ZCM register specification)

Self-bias control impossible

By clock sampling

NMI, RESET noise elimination

method

By analog delay

Operation stop possible

(VAREF pin operation)

Operation stop impossible

A/D converter operation control

0.4% (T^A= –10 to +70 °C,

VAREF = 4.0V to AVDD)

A/D converter absolute accuracy

(Unit: FSR)

0.4% (TA = –10 to +50 °C)

0.6% (TA = –40 to +85 °C,

0.4% (TA = –10 to +70 °C)*3

0.6% (TA = –40 to +85 °C)

V^AREF= 4.0V to AVDD)

0.8% (TA = –40 to +85 °C

VAREF = 3.4V to AVDD)

3.4 V to AVDD

VAREF voltage range

Analog input voltage range

AICC/AIDD1

AVCC to 0.5V to AVCC

0V to VAREF

6 mA Typ.

—

0.5 mA Typ.

10 µA Typ.

1.5 mA Typ.

0.7 mA Typ.

AIDD2

IAREF/IAREF1

IAREF2

0.5 mA Typ.

2.0 mA Typ.

—

* 1. µPD7810, 7811, 78C10 and 78C11 are maintenance products.

2. K, E, P masks apply from 4 MHz to 12 MHz.

3. The µPD7810HG and 7811HG G masks, µPD7810HCW and 7811HCW K masks apply TA = 0 to +70 °C.

µPD78C10A,78C11A,78C12A

µPD78C10A, 78C11A,

µPD78CP14

µPD78CP18

78C12A

159 kinds (STOP instruction added)

ROM less (µPD78C10A)

4K × 8 bits (µPD78C11A)

8K × 8 bits (µPD78C12A)

32K × 8 bits (PROM)

1024 × 8 bits

16K × 8 bits (PROM)

256 × 8 bits

28 (ZCM register added)

6 to 15 MHz

4 to 15 MHz

5 V ±10 %

5 V ±5 %

–40 to +85 °C

Three kinds: Halt mode, software STOP mode, and hardware STOP mode. All data of

on-chip RAM are held by low power supply voltage (2.5 V) in software/hardware STOP

mode.

STOP

Low level

Self-bias control possible

(by ZCM register specification)

By analog delay

Operation stop impossible (V^AREFpin operation)

0.4% (TA = –10 to +70 °C, VAREF = 4.0 V to AVDD)

0.6% (TA = –40 to +85 °C, VAREF = 4.0 V to AVDD)

0.8% (T^A= –40 to +85 °C, VAREF = 3.4 V to AVDD)

3.4V to AVDD

–0.3 V to VAREF + 0.3 V

0V to VAREF

0.5mA Typ.

10 µA Typ.

1.5 mA Typ.

0.7 mA Typ.

–0.3 V to VAREF + 0.3 V

µPD78C10A,78C11A,78C12A

DIFFERENCES IN 87AD SERIES PRODUCTS (2/2)

Product Name

µPD7810H, 7811H

µPD78C10, 78C11*1

µPD7810, 7811*1

Item

RD/WR

ALE

High level

Output

Operation

High-impedance

during RESET

Zero is output at the pin specified by the address bus.

Other pins are high impedance.

PD/PF*4

On-chip pull-up register

(Mask option)

Impossible

NMOS

Device configuration

CMOS

3.2 mA (–10 to +70°C) MAX.

3.2 mA MAX.

3.5 mA (–40 to +85°C) MAX.

50 µA MAX.

Standby current

(VDD = 5 V ±10 %)

203.2 mA (–10 to +70°C) MAX.

203.2 mA MAX.

223.5 mA (–40 to +85°C) MAX.

Current consumption

25 mA MAX.

Cycle time input

20T

SCK

Low level width

10T + 80

10T – 80

T + 110

(Unit: ns)

High level width

TLDW

TWD

TDW

Bus

timing

(Unit: ns)

100

4T – 100

★

Hardware STOP mode restrictions

—

Yes

Asyncronous mode restrictions

during external SCK input.

64-pin plastic shrink DIP

64-pin plastic QUIP

straight*8

64-pin plastic QUIP

64-pin plastic QFP

(14 × 20 mm, 2.05 mm

thickness)

64-pin plastic shrink DIP

64-pin plastic QUIP straight*7

Package

64-pin plastic QUIP

64-pin plastic QFP

(14 × 20 mm, 2.70 mm

thickness)

68-pin plastic QFJ

Pin connection*10

VCC (64-pin), VDD (63-pin)

VDD (64-pin), STOP (63-pin)

* 1. µPD7810, 7811, 78C10 and 78C11 are maintenance products.

4. For µPD7810, 7810H, 78C10 and 78C10A.

(Unit : ns)

For the asyncronous mode with clock For the asyncronous mode with clock

rate x1, syncronous mode, and I/O

interface mode

rate ×16 and ×64

Cycle time input

SCK Low level width

High level width

12T

5T + 5

2.5T + 5

Remarks T = tCYC = 1/fxx

µPD78C10A,78C11A,78C12A

µPD78C10A, 78C11A,

µPD78CP14

µPD78CP18

78C12A

High-impedance

Only µPD78C11A, 78C12A

Impossible

possible (ports A, B, C)

CMOS

50 µA MAX.

1 mA MAX.

50 µA MAX.

(VDD = 5 V ±10 %)

(VDD = 5 V ±5 %)

(VDD = 5 V ±10 %)

25 mA MAX.

35 mA MAX.

32 mA MAX.

T + 130

140

T + 110

110

4T – 140

4T – 100

★

Yes*6

64-pin plastic shrink DIP

64-pin plastic QUIP

64-pin plastic QFP (14 × 20

mm, 2.70 mm thickness)

68-pin plastic QFJ

64-pin plastic shrink DIP

64-pin plastic QUIP

64-pin plastic shrink DIP

64-pinplasticQUIPstraight*9

64-pin plastic QUIP

64-pin plastic QFP (14 × 20

mm, 2.70 mm thickness)

64-pin ceramic shrink DIP

with window

64-pin ceramic shrink DIP

with window

64-pin plastic QFP (14 × 20

mm, 2.70 mm thickness)

68-pin plastic QFJ

64-pin ceramic QUIP with

window

64-pin ceramic WQFN

VDD (64-pin), STOP (63-pin)

6. K mask products only

7. µPD7811, 7811H only

8. µPD78C11, only

9. µPD78C11A, 78C12A only

10. Items in the parentheses are the pin numbers for the 64-pin plastic shrink DIP, 64-pin plastic QUIP straight

and 64-pin plastic QUIP.

Caution Since the oscillator characteristics, I/O level, and some internal operation timing are different, be careful

when studying direct replacement of the mPD78C10A, 78C11A, 78C12A and µPD7810, 7811, 7810H,

7811H, 78C10, 78C11.

µPD78C10A,78C11A,78C12A

9. PACKAGE INFORMATION

64 PIN PLASTIC SHRINK DIP (750 mil)

NOTE

ITEM MILLIMETERS

INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

58.68 MAX.

1.78 MAX.

1.778 (T.P.)

2.311 MAX.

0.070 MAX.

0.070 (T.P.)

2) Item "K" to center of leads when formed parallel.

+0.004

0.020

0.50±0.10

–0.005

0.9 MIN.

3.2±0.3

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.51 MIN.

4.31 MAX.

5.08 MAX.

19.05 (T.P.)

17.0

+0.004

0.010

+0.10

0.25

–0.003

–0.05

0.17

0.007

0~15°

P64C-70-750A,C-1

µPD78C10A,78C11A,78C12A

64PIN PLASTIC QFP (14 × 20) (UNIT: mm)

detail of lead end

P64GF-100-3B8,3BE,3BR-1

NOTE

ITEM

MILLIMETERS

INCHES

Each lead centerline is located within 0.20

mm (0.008 inch) of its true position (T.P.) at

maximum material condition.

23.6 0.4

20.0 0.2

14.0 0.2

17.6 0.4

1.0

0.929 0.016

+0.009

0.795

–0.008

+0.009

0.551

–0.008

0.693 0.016

0.039

1.0

0.039

+0.004

0.40 0.10

0.20

0.016

–0.005

0.008

1.0 (T.P.)

1.8 0.2

0.039 (T.P.)

+0.008

0.071

–0.009

+0.009

0.031

0.8 0.2

–0.008

+0.10

+0.004

0.15

0.006

–0.05

–0.003

0.12

0.005

2.7

0.106

0.1 0.1

3.0 MAX.

0.004 0.004

0.119 MAX.

µPD78C10A,78C11A,78C12A

ES 64PIN CERAMIC QFP (REFERENCE DRAWING) (UNIT: mm)

Cautions 1. The metal cap is connected to

pin 26 and is V^SS(GND) level.

2. The bottom leads are tilted.

3. Since cutting of the end of the

leads is no process-controlled,

the lead length is unspecified.

µPD78C10A,78C11A,78C12A

68PIN PLASTIC QFJ ( 950 mil) (UNIT: mm)

P68L-50A1-2

NOTE

ITEM

MILLIMETERS

25.2 0.2

24.20

INCHES

Each lead centerline is located within 0.12

mm (0.005 inch) of its true position (T.P.) at

maximum material condition.

0.992 0.008

0.953

24.20

0.953

25.2 0.2

1.94 0.15

0.6

0.992 0.008

+0.007

0.076

–0.006

0.024

+0.009

4.4 0.2

2.8 0.2

0.9 MIN.

3.4

0.173

–0.008

+0.009

0.110

–0.008

0.035 MIN.

0.134

1.27 (T.P.)

0.40 1.0

0.12

0.050 (T.P.)

+0.004

0.016

–0.005

0.005

+0.009

23.12 0.20

0.15

0.910

–0.008

0.006

R 0.8

R 0.031

+0.10

+0.004

0.20

0.008

–0.05

–0.002

µPD78C10A, 78C11A, 78C12A

★

10. RECOMMENDED SOLDERING CONDITIONS

The µPD78C10A, 78C11A, and 78C12A should be soldered and mounted under the conditions recommended in

the table below.

For detail of recommended soldering conditions, refer to the information document "Semiconductor Device

Mounting Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended below, contact our sales personnel.

Table 10-1 Surface Mounting Type Soldering Conditions

(1)µPD78C10AGF-3BE

: 64-pin plastic QFP (14 × 20 mm)

µPD78C11AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm)

µPD78C12AGF-×××-3BE : 64-pin plastic QFP (14 × 20 mm)

Recommended

Soldering Method

Infrared reflow

Soldering Conditions

Condition Symbol

IR35-00-2

Package peak temperature : 235 °C, Duration : 30 sec. max. (210

°C min.), Number of times : 2 max.

(1) Start the second reflow after the device temperature by the first

reflow returns to normal.

(2) Fluxwashingbythewaterafterthefirstreflowshouldbeavoided.

Package peak temperature : 215 °C, Duration : 40 sec. max. (200

°C min.), Number of times : 2 max.

VPS

VP15-00-2

WS60-00-1

(1) Start the second reflow after the device temperature by the first

reflow returns to normal.

(2) Fluxwashingbythewaterafterthefirstreflowshouldbeavoided.

Solder bath temperature : 260 °C max., Duration : 10 sec. max.,

Number of times : 1

Pre-heating temperature : 120 °C max. (package surface tempera-

ture)

Wave soldering

Pin part heating

Pin temperature : 300 °C max.,

Duration: 3 sec. max. (per device side)

Caution

Do not use two or more soldering methods in combination (except the pin part heating method).

(2)µPD78C10AL

µPD78C11AL-×××

µPD78C12AL-×××

68-pin plastic QFJ ( 950 mil)

Recommended

Soldering Conditions

Soldering Method

Infrared reflow

Condition Symbol

Package peak temperature : 230 °C, Duration : 30 sec. max.

(210 °C min.), Number of times : 1

IR30-00-1

VP15-00-1

Package peak temperature : 215 °C, Duration : 40 sec. max.

(200 °C min.), Number of times : 1

VPS

Pin part heating

Pin temperature : 300 °C max., Duration : 3 sec. max. (per device

side)

Caution

Do not use two or more soldering methods in combination (except the pin part heating method).

µPD78C10A, 78C11A, 78C12A

Table 10-2 Inserted Type Soldering Conditions

(1) µPD78C10ACW

µPD78C11ACW-×××

µPD78C12ACW-×××

µPD78C10AGQ-36

: 64-pin plastic shrink DIP (750 mil)

: 64-pin plastic QUIP

µPD78C11AGQ-×××-36 : 64-pin plastic QUIP

µPD78C12AGQ-×××-36 : 64-pin plastic QUIP

Soldering Method

Wave soldering

Soldering Conditions

Solder bath temperature: 260 °C max.

(pin only)

Duration: 10 sec. max.

Pin temperature: 300 °C max.

Pin part heating

Duration: 3 sec. max. (per pin)

Caution

Ensure that the application of wave soldering is limited to

the pins and no solder touches the main unit directly.

(2)µPD78C11AGQ-×××-37 : 64-pin plastic QUIP straight

µPD78C12AGQ-×××-37 : 64-pin plastic QUIP straight

Soldering Method

Pin part heating

Soldering Conditions

Pin temperature: 300 °C max.

Duration: 3 sec. max. (per pin)

µPD78C10A,78C11A,78C12A

APPENDIX DEVELOPMENT TOOLS

★

The following development tools are available to develop a system which uses 87AD series products.

Language Processor

This is a program which converts a program written in mnemonic to an object code that micro-

computer execution is possible.

Besides, it contains a function to automatically create a symbol/table, and optimize a branch

instruction.

Host Machine

PC-9800 series

IBM PC/AT^TM

Ordering Code (Product Name)

µS5A13RA87

Supply Medium

3.5-inch 2HD

87AD series

relocatable assembler

(RA87)

MS-DOS^TM

Ver. 2.11

5-inch 2HD

µS5A10RA87

Ver. 5.00A*

PC DOS^TM

(Ver. 3.1)

3.5-inch 2HC

5-inch 2HC

µS7B13RA87

µS7B10RA87

PROM Write Tools

With an provided board and an optional programmer adapter connected, this PROM programmer

can manipulate from a stand-alone or host machine to perform programming on single-chip

microcomputer which incorporates PROM.

PG-1500

It is also capable of programming a typical PROM ranging from 256K to 4M bits.

PA-78CP14CW/

GF/GQ/KB/L

PROM programmer adapter for µPD78CP14/78CP18. Used by connecting to PG-1500.

PA-78CP14CW

PA-78CP14GF

PA-78CP14GQ

PA-78CP14KB

PA-78CP14L

For µPD78CP14CW, 78CP14DW, 78CP18CW, 78CP18DW

For µPD78CP14GF-3BE, 78CP18GF-3BE

For µPD78CP14G-36, 78CP14R, 78CP18GQ-36

For µPD78CP14KB, 78CP18KB

For µPD78CP14L

Connected PG-1500 to a host machine by using serial and parallel interface, to control the PG-

1500 on a host machine.

Host Machine

PC-9800 series

Ordering Code (Product Name)

Supply Medium

3.5-inch 2HD

5-inch 2HD

PG-1500

MS-DOS

Ver. 2.11

µS5A13PG1500

µS5A10PG1500

controller

Ver. 5.00A*

PC DOS

IBM PC/AT

5-inch 2HC

µS7B10PG1500

(Ver. 3.1)

* Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.

Remarks Operation of assemblers and the PG-1500 controller are guaranteed only on the host machines and

operating systems quoted above.

µPD78C10A,78C11A,78C12A

Debugging tools

An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for 87AD series. The following table

shows its system configuration.

The IE-78C11-M is an in-circuit emulator which works with 87AD series.

Only the IE-78C11-M should be used for a plastic QUIP package, while it should be used with a

IE-78C11-M

conversion socket for a plastic shrink DIP package.

It can be connected to a host machine to perform efficient debugging.

Conversion sockets for plastic shrink DIP.

EV-9001-64

Used in combination with the IE-78C11-M.

64-pin LCC socket. Can be used as a substitute for 64-pin plastic QFP products with window in

EV-9200G-64

combination with the µPD78CP14KB/78CP18KB.

Connects the IE-78C11-M to host machine by using the RS-232-C, then controls the IE-78C11-M

on host machine.

Ordering Code (Product Name)

µS5A13IE78C11

Host Machine

PC-9800 series

IBM PC/AT

Supply Medium

3.5-inch 2HD

IE-78C11-M

control program

(IE controller)

MS-DOS

Ver. 2.11

5-inch 2HD

5-inch 2HC

µS5A10IE78C11

Ver. 3.30D

PC DOS

µS7B10IE78C11

(Ver. 3.1)

Remarks Operation of the IE controller is guaranteed only on the host machine and operating systems quoted

above.

µPD78C10A,78C11A,78C12A

[MEMO]

µPD78C10A,78C11A,78C12A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V^DDor GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused

pins must be judged device by device and related specifications governing the

devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immedi-

ately after power-on for devices having reset function.

µPD78C10A,78C11A,78C12A

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products

may be prohibited without governmental license. To export or re-export some or all of these products from a country other

than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The customer must judge : µPD78C11ACW-×××, 78C11AGF-×××-3BE, 78C11AGQ-×××-36, 78C11AGQ-×××-37,

the need for license

µPD78C11AL-×××, 78C12ACW-×××, 78C12AGF-×××-3BE, 78C12AGQ-×××-36,

µPD78C12AGQ-×××-37, 78C12AL-×××

License not needed :

µPD78C10ACW, 78C10AGF-3BE, 78C10AGQ-36, 78C10AL

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents,

copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on

a customer designated “quality assurance program“ for a specific application. The recommended applications

of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each

device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact NEC Sales Representative in advance.

Anti-radioactive design is not implemented in this product.

M4 94.11

MS-DOS is a trademark of Microsoft Corporation.

PC/AT and PC DOS are trademarks of IBM Corporation.

UPD78C11AL [NEC]

相关型号：

UPD78C11AL(A)-XXX

UPD78C11AL-XXX

UPD78C11CW

UPD78C11CW-XXX

UPD78C11G

UPD78C11G-1B

UPD78C11G-36

UPD78C11G-XXX-1B

UPD78C11G-XXX-36

UPD78C11GF

UPD78C11GF-XXX-3BE

UPD78C11L