UPD78F0103HMC(A1)-5A4-A

User’s Manual

78K0/KB1+

8-Bit Single-Chip Microcontrollers

µPD78F0101H

µPD78F0102H

µPD78F0103H

µPD78F0101H(A)

µPD78F0102H(A)

µPD78F0103H(A)

µPD78F0101H(A1)

µPD78F0102H(A1)

µPD78F0103H(A1)

Document No. U16846EJ3V0UD00 (3rd edition)

Date Published April 2006 NS CP(K)

2003

Printed in Japan

[MEMO]

User’s Manual U16846EJ3V0UD

2

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

V

IH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

User’s Manual U16846EJ3V0UD

3

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

User’s Manual U16846EJ3V0UD

4

Caution: This product uses SuperFlash^®technology licensed from Silicon Storage Technology, inc.

•

The information in this document is current as of March, 2006. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or

data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all

products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

User’s Manual U16846EJ3V0UD

5

INTRODUCTION

Readers

This manual is intended for user engineers who wish to understand the functions of the

78K0/KB1+ and design and develop application systems and programs for these

devices.

The target products are as follows.

78K0/KB1+: µPD78F0101H, 78F0102H, 78F0103H, 78F0101H(A), 78F0102H(A),

78F0103H(A), 78F0101H(A1), 78F0102H(A1), 78F0103H(A1)

Purpose

This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization

The 78K0/KB1+ manual is separated into two parts: this manual and the instructions

edition (common to the 78K/0 Series).

78K0/KB1+

User’s Manual

(This Manual)

78K/0 Series

User’s Manual

Instructions

• Pin functions

• CPU functions

• Internal block functions

• Interrupts

• Instruction set

• Explanation of each instruction

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• When using this manual as the manual for (A) grade products and (A1) grade

products:

→ Only the quality grade differs between standard products and (A), (A1) grade

products. Read the part number as follows.

• µPD780101H → µPD780101H(A), 780101H(A1)

• µPD780102H → µPD780102H(A), 780102H(A1)

• µPD780103H → µPD780103H(A), 780103H(A1)

• To gain a general understanding of functions:

→ Read this manual in the order of the CONTENTS. The mark <R> shows major

revised points. The revised points can be easily searched by copying an "<R>" in

the PDF file and specifying it in the "Find what:" field.

• How to interpret the register format:

→ For a bit number enclosed in brackets, the bit name is defined as a reserved word

in the RA78K0, and is defined as an sfr variable by #pragma sfr directive in the

CC78K0.

• To check the details of a register when you know the register name:

→ Refer to APPENDIX C REGISTER INDEX.

• To know details of the 78K/0 Series instructions:

→ Refer to the separate document 78K/0 Series Instructions User’s Manual

(U12326E).

6

User’s Manual U16846EJ3V0UD

Conventions

Data significance:

Higher digits on the left and lower digits on the right

Active low representations: ××× (overscore over pin and signal name)

Note:

Footnote for item marked with Note in the text

Caution:

Remark:

Information requiring particular attention

Supplementary information

...

Numerical representations: Binary

Decimal

×××× or ××××B

××××

...

Hexadecimal

××××H

Differences Between 78K0/KB1+ and 78K0/KB1

Series Name

78K0/KB1+

78K0/KB1

Item

Mask ROM version

None

Available

Flash

Power supply

Single power supply

Available

Two power supplies

memory

version

Self-programming function

Option byte

None

Internal oscillator can be stopped/cannot

be stopped selectable

Power-on clear function

2.1 V 0.1 V (fixed)

2.85 V 0.15 V or 3.5 V 0.2 V selectable

Minimum instruction execution time

0.125 µs (at 16 MHz operation)

0.166 µs (at 12 MHz operation)

Other Documents

Document Name

SEMICONDUCTOR SELECTION GUIDE − Products and Packages −

Semiconductor Device Mount Manual

Document No.

X13769X

Note

Quality Grades on NEC Semiconductor Devices

C11531E

C10983E

C11892E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

8

User’s Manual U16846EJ3V0UD

CONTENTS

CHAPTER 1 OUTLINE ............................................................................................................................ 15

1.1 Features ...................................................................................................................................... 15

1.2 Applications................................................................................................................................ 16

1.3 Ordering Information................................................................................................................. 16

1.4 Pin Configuration (Top View).................................................................................................... 17

1.5 Kx1 Series Lineup...................................................................................................................... 18

1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup ..............................................................................................18

1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup.....................................................................................21

1.6 Block Diagram............................................................................................................................ 24

1.7 Outline of Functions.................................................................................................................. 25

CHAPTER 2 PIN FUNCTIONS............................................................................................................... 27

2.1 Pin Function List........................................................................................................................ 27

2.2 Description of Pin Functions.................................................................................................... 29

2.2.1 P00 to P03 (port 0)...........................................................................................................................29

2.2.2 P10 to P17 (port 1)...........................................................................................................................29

2.2.3 P20 to P23 (port 2)...........................................................................................................................30

2.2.4 P30 to P33 (port 3)...........................................................................................................................30

2.2.5 P120 (port 12) ..................................................................................................................................30

2.2.6 P130 (port 13) ..................................................................................................................................31

2.2.7 AVREF ...............................................................................................................................................31

2.2.8 AVSS .................................................................................................................................................31

2.2.9 RESET.............................................................................................................................................31

2.2.10 X1 and X2 ........................................................................................................................................31

2.2.11 CL1 and CL2....................................................................................................................................31

2.2.12 VDD ...................................................................................................................................................31

2.2.13 VSS ...................................................................................................................................................31

2.2.14 FLMD0 and FLMD1..........................................................................................................................31

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 32

CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 34

3.1 Memory Space............................................................................................................................ 34

3.1.1 Internal program memory space ......................................................................................................38

3.1.2 Internal data memory space.............................................................................................................39

3.1.3 Special function register (SFR) area ................................................................................................39

3.1.4 Data memory addressing.................................................................................................................40

3.2 Processor Registers.................................................................................................................. 43

3.2.1 Control registers...............................................................................................................................43

3.2.2 General-purpose registers ...............................................................................................................47

3.2.3 Special function registers (SFRs).....................................................................................................48

3.3 Instruction Address Addressing .............................................................................................. 52

3.3.1 Relative addressing..........................................................................................................................52

3.3.2 Immediate addressing......................................................................................................................53

3.3.3 Table indirect addressing.................................................................................................................54

3.3.4 Register addressing .........................................................................................................................54

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User’s Manual U16846EJ3V0UD

3.4 Operand Address Addressing .................................................................................................. 55

3.4.1 Implied addressing .......................................................................................................................... 55

3.4.2 Register addressing ........................................................................................................................ 56

3.4.3 Direct addressing ............................................................................................................................ 57

3.4.4 Short direct addressing ................................................................................................................... 58

3.4.5 Special function register (SFR) addressing ..................................................................................... 59

3.4.6 Register indirect addressing............................................................................................................ 60

3.4.7 Based addressing............................................................................................................................ 61

3.4.8 Based indexed addressing .............................................................................................................. 62

3.4.9 Stack addressing............................................................................................................................. 63

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 64

4.1 Port Functions............................................................................................................................ 64

4.2 Port Configuration...................................................................................................................... 65

4.2.1 Port 0............................................................................................................................................... 66

4.2.2 Port 1............................................................................................................................................... 69

4.2.3 Port 2............................................................................................................................................... 74

4.2.4 Port 3............................................................................................................................................... 75

4.2.5 Port 12............................................................................................................................................. 76

4.2.6 Port 13............................................................................................................................................. 77

4.3 Registers Controlling Port Function ........................................................................................ 77

4.4 Port Function Operations.......................................................................................................... 81

4.4.1 Writing to I/O port ............................................................................................................................ 81

4.4.2 Reading from I/O port...................................................................................................................... 81

4.4.3 Operations on I/O port..................................................................................................................... 81

CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 82

5.1 Functions of Clock Generator................................................................................................... 82

5.2 Configuration of Clock Generator ............................................................................................ 82

5.3 Registers Controlling Clock Generator.................................................................................... 84

5.4 System Clock Oscillator............................................................................................................ 90

5.4.1 High-speed system clock oscillator ................................................................................................. 90

5.4.2 Internal oscillator ............................................................................................................................. 94

5.4.3 Prescaler ......................................................................................................................................... 94

5.5 Clock Generator Operation ....................................................................................................... 94

5.6 Time Required to Switch Between Internal Oscillation Clock and

High-Speed System Clock......................................................................................................... 99

5.7 Time Required for CPU Clock Switchover............................................................................... 99

5.8 Clock Switching Flowchart and Register Setting ................................................................. 100

5.8.1 Switching from internal oscillation clock to high-speed system clock .............................................100

5.8.2 Switching from high-speed system clock to internal oscillation clock .............................................101

5.8.3 Register settings.............................................................................................................................102

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00........................................................................... 103

6.1 Functions of 16-Bit Timer/Event Counter 00......................................................................... 103

6.2 Configuration of 16-Bit Timer/Event Counter 00................................................................... 104

6.3 Registers Controlling 16-Bit Timer/Event Counter 00.......................................................... 108

6.4 Operation of 16-Bit Timer/Event Counter 00 ......................................................................... 114

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User’s Manual U16846EJ3V0UD

6.4.1 Interval timer operation ..................................................................................................................114

6.4.2 PPG output operations...................................................................................................................117

6.4.3 Pulse width measurement operations ............................................................................................120

6.4.4 External event counter operation ...................................................................................................128

6.4.5 Square-wave output operation.......................................................................................................131

6.4.6 One-shot pulse output operation....................................................................................................133

6.5 Cautions for 16-Bit Timer/Event Counter 00 ......................................................................... 138

CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50............................................................................. 141

7.1 Functions of 8-Bit Timer/Event Counter 50........................................................................... 141

7.2 Configuration of 8-Bit Timer/Event Counter 50 .................................................................... 142

7.3 Registers Controlling 8-Bit Timer/Event Counter 50............................................................ 144

7.4 Operations of 8-Bit Timer/Event Counter 50......................................................................... 147

7.4.1 Operation as interval timer.............................................................................................................147

7.4.2 Operation as external event counter ..............................................................................................149

7.4.3 Operation as square-wave output ..................................................................................................150

7.4.4 Operation as PWM output..............................................................................................................151

7.5 Cautions for 8-Bit Timer/Event Counter 50 ........................................................................... 153

CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 154

8.1 Functions of 8-Bit Timers H0 and H1..................................................................................... 154

8.2 Configuration of 8-Bit Timers H0 and H1 .............................................................................. 154

8.3 Registers Controlling 8-Bit Timers H0 and H1...................................................................... 158

8.4 Operation of 8-Bit Timers H0 and H1..................................................................................... 162

8.4.1 Operation as interval timer/square-wave output.............................................................................162

8.4.2 Operation as PWM output mode....................................................................................................165

CHAPTER 9 WATCHDOG TIMER....................................................................................................... 171

9.1 Functions of Watchdog Timer ................................................................................................ 171

9.2 Configuration of Watchdog Timer.......................................................................................... 173

9.3 Registers Controlling Watchdog Timer................................................................................. 173

9.4 Operation of Watchdog Timer ................................................................................................ 176

9.4.1 Watchdog timer operation when “Internal oscillator cannot be stopped”

is selected by option byte...............................................................................................................176

9.4.2 Watchdog timer operation when “Internal oscillator can be stopped by software”

is selected by option byte...............................................................................................................177

9.4.3 Watchdog timer operation in STOP mode (when “Internal oscillator can be stopped by software”

is selected by option byte)..............................................................................................................178

9.4.4 Watchdog timer operation in HALT mode (when “Internal oscillator can be stopped by software”

is selected by option byte)..............................................................................................................180

CHAPTER 10 A/D CONVERTER......................................................................................................... 181

10.1 Function of A/D Converter ...................................................................................................... 181

10.2 Configuration of A/D Converter.............................................................................................. 182

10.3 Registers Used in A/D Converter ........................................................................................... 184

10.4 A/D Converter Operations....................................................................................................... 188

10.4.1 Basic operations of A/D converter..................................................................................................188

10.4.2 Input voltage and conversion results..............................................................................................190

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User’s Manual U16846EJ3V0UD

10.4.3 A/D converter operation mode........................................................................................................191

10.5 How to Read A/D Converter Characteristics Table............................................................... 194

10.6 Cautions for A/D Converter..................................................................................................... 196

CHAPTER 11 SERIAL INTERFACE UART0 (µPD78F0102H AND 78F0103H ONLY)..................... 201

11.1 Functions of Serial Interface UART0...................................................................................... 201

11.2 Configuration of Serial Interface UART0 ............................................................................... 202

11.3 Registers Controlling Serial Interface UART0....................................................................... 205

11.4 Operation of Serial Interface UART0...................................................................................... 210

11.4.1 Operation stop mode......................................................................................................................210

11.4.2 Asynchronous serial interface (UART) mode .................................................................................211

11.4.3 Dedicated baud rate generator.......................................................................................................217

CHAPTER 12 SERIAL INTERFACE UART6 ...................................................................................... 222

12.1 Functions of Serial Interface UART6...................................................................................... 222

12.2 Configuration of Serial Interface UART6 ............................................................................... 226

12.3 Registers Controlling Serial Interface UART6....................................................................... 229

12.4 Operation of Serial Interface UART6...................................................................................... 239

12.4.1 Operation stop mode......................................................................................................................239

12.4.2 Asynchronous serial interface (UART) mode .................................................................................240

12.4.3 Dedicated baud rate generator.......................................................................................................254

CHAPTER 13 SERIAL INTERFACE CSI10 ........................................................................................ 261

13.1 Functions of Serial Interface CSI10........................................................................................ 261

13.2 Configuration of Serial Interface CSI10 ................................................................................. 261

13.3 Registers Controlling Serial Interface CSI10......................................................................... 263

13.4 Operation of Serial Interface CSI10........................................................................................ 266

13.4.1 Operation stop mode......................................................................................................................266

13.4.2 3-wire serial I/O mode ....................................................................................................................267

CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................ 275

14.1 Interrupt Function Types......................................................................................................... 275

14.2 Interrupt Sources and Configuration ..................................................................................... 275

14.3 Registers Controlling Interrupt Function............................................................................... 278

14.4 Interrupt Servicing Operations ............................................................................................... 284

14.4.1 Maskable interrupt request acknowledgment .................................................................................284

14.4.2 Software interrupt request acknowledgment ..................................................................................286

14.4.3 Multiple interrupt servicing..............................................................................................................287

14.4.4 Interrupt request hold .....................................................................................................................290

CHAPTER 15 STANDBY FUNCTION .................................................................................................. 291

15.1 Standby Function and Configuration..................................................................................... 291

15.1.1 Standby function.............................................................................................................................291

15.1.2 Registers controlling standby function............................................................................................293

15.2 Standby Function Operation................................................................................................... 295

15.2.1 HALT mode ....................................................................................................................................295

15.2.2 STOP mode....................................................................................................................................298

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User’s Manual U16846EJ3V0UD

CHAPTER 16 RESET FUNCTION ....................................................................................................... 302

16.1 Register for Confirming Reset Source .................................................................................. 308

CHAPTER 17 CLOCK MONITOR........................................................................................................ 309

17.1 Functions of Clock Monitor .................................................................................................... 309

17.2 Configuration of Clock Monitor.............................................................................................. 309

17.3 Register Controlling Clock Monitor ....................................................................................... 310

17.4 Operation of Clock Monitor..................................................................................................... 311

CHAPTER 18 POWER-ON-CLEAR CIRCUIT ..................................................................................... 316

18.1 Functions of Power-on-Clear Circuit ..................................................................................... 316

18.2 Configuration of Power-on-Clear Circuit............................................................................... 317

18.3 Operation of Power-on-Clear Circuit ..................................................................................... 317

18.4 Cautions for Power-on-Clear Circuit...................................................................................... 318

CHAPTER 19 LOW-VOLTAGE DETECTOR....................................................................................... 320

19.1 Functions of Low-Voltage Detector ....................................................................................... 320

19.2 Configuration of Low-Voltage Detector................................................................................. 320

19.3 Registers Controlling Low-Voltage Detector ........................................................................ 321

19.4 Operation of Low-Voltage Detector........................................................................................ 323

19.5 Cautions for Low-Voltage Detector........................................................................................ 327

CHAPTER 20 OPTION BYTE............................................................................................................... 330

20.1 Functions of Option Bytes...................................................................................................... 330

20.2 Format of Option Byte............................................................................................................. 330

CHAPTER 21 FLASH MEMORY........................................................................................................... 332

21.1 Internal Memory Size Switching Register ............................................................................. 333

21.2 Writing with Flash Programmer.............................................................................................. 334

21.3 Programming Environment..................................................................................................... 338

21.4 Communication Mode ............................................................................................................. 338

21.5 Connection of Pins on Board ................................................................................................. 341

21.5.1 FLMD0 pin .....................................................................................................................................341

21.5.2 FLMD1 pin .....................................................................................................................................341

21.5.3 Serial interface pins........................................................................................................................342

21.5.4 RESET pin .....................................................................................................................................344

21.5.5 Port pins.........................................................................................................................................344

21.5.6 Other signal pins ............................................................................................................................344

21.5.7 Power supply..................................................................................................................................344

21.6 Programming Method.............................................................................................................. 345

21.6.1 Controlling flash memory ...............................................................................................................345

21.6.2 Flash memory programming mode ................................................................................................345

21.6.3 Selecting communication mode .....................................................................................................346

21.6.4 Communication commands............................................................................................................347

21.7 Flash Memory Programming by Self-Writing........................................................................ 348

21.7.1 Registers used for self-programming function................................................................................349

21.8 Boot Swap Function ................................................................................................................ 353

21.8.1 Outline of boot swap function.........................................................................................................353

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User’s Manual U16846EJ3V0UD

21.8.2 Memory map and boot area ...........................................................................................................354

CHAPTER 22 INSTRUCTION SET....................................................................................................... 357

22.1 Conventions Used in Operation List...................................................................................... 357

22.1.1 Operand identifiers and specification methods...............................................................................357

22.1.2 Description of operation column.....................................................................................................358

22.1.3 Description of flag operation column ..............................................................................................358

22.2 Operation List........................................................................................................................... 359

22.3 Instructions Listed by Addressing Type................................................................................ 367

CHAPTER 23 ELECTRICAL SPECIFICATIONS

(STANDARD PRODUCTS, (A) GRADE PRODUCTS) ........................................................................ 370

CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................ 384

CHAPTER 25 PACKAGE DRAWING................................................................................................... 397

CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS........................................................... 398

CHAPTER 27 CAUTIONS FOR WAIT................................................................................................. 399

27.1 Cautions for Wait...................................................................................................................... 399

27.2 Peripheral Hardware That Generates Wait ............................................................................ 400

27.3 Example of Wait Occurrence .................................................................................................. 401

APPENDIX A DEVELOPMENT TOOLS............................................................................................... 402

A.1 Software Package..................................................................................................................... 405

A.2 Language Processing Software.............................................................................................. 406

A.3 Control Software ...................................................................................................................... 407

A.4 Flash Memory Writing Tools................................................................................................... 407

A.5 Debugging Tools (Hardware).................................................................................................. 408

A.5.1 When using in-circuit emulator QB-78K0KX1H ..............................................................................408

A.5.2 When using on-chip debug emulator QB-78K0MINI.......................................................................409

A.6 Debugging Tools (Software) ................................................................................................... 410

APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 411

APPENDIX C REGISTER INDEX ......................................................................................................... 412

C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 412

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 415

APPENDIX D LIST OF CAUTIONS..................................................................................................... 418

APPENDIX E REVISION HISTORY...................................................................................................... 435

E.1 Major Revisions in This Edition.............................................................................................. 435

E.2 Revision History up to Previous Edition................................................................................ 436

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User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.1 Features

{ Minimum instruction execution time can be changed from high speed (0.125 µs: @ 16 MHz operation with high-

speed system clock) to low-speed (2.0 µs: @ 16 MHz operation with high-speed system clock)

{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)

{ ROM, RAM capacities

Part Number

Program Memory

(ROM)

Data Memory

(Internal High-Speed RAM)

Item

µPD78F0101H

µPD78F0102H

µPD78F0103H

Flash memory

8 KB^Note

512 bytes

768 bytes

16 KB^Note

24 KB^Note

Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal

memory size switching register (IMS).

{ On-chip single-power-supply flash memory

{ Self-programming (with boot swap function)

{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)

{ Short startup is possible via the CPU default start using the internal oscillator

{ On-chip clock monitor function using the internal oscillator

{ On-chip watchdog timer (operable with internal oscillation clock)

{ I/O ports: 22

{ Timer: 5 channels

{ Serial interface: 2 channels

UART (LIN (Local Interconnect Network)-bus supported): 1 channel

CSI1/UART^{Note 1}

:

1 channel (µPD78F0101H only, CSI1: 1 channel)

{ 10-bit resolution A/D converter: 4 channels

{ Supply voltage:

<R>

• Standard products and (A) grade products:

V^DD= 2.5 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 V^{Note 2}

• (A1) grade products:

)

V^DD= 2.7 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 V^{Note 3}

{ Operating ambient temperature:

• Standard products and (A) grade products: T^A= −40 to +85°C

• (A1) grade products: T^A= −40 to +110°C

Notes 1. Select either of the functions of these alternate-function pins.

2. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the

power-on-clear (POC) circuit is 2.1 V 0.1 V.

<R>

3. Use the product in a voltage range of 2.25 to 5.5 V because the detection voltage (V^POC) of the

power-on-clear (POC) circuit is 2.0 V to 2.25 V.

15

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.2 Applications

{ Automotive equipment

•

System control for body electricals (power windows, keyless entry reception, etc.)

Sub-microcontrollers for control

{ Home audio, car audio

{ AV equipment

{ PC peripheral equipment (keyboards, etc.)

{ Household electrical appliances

•

Outdoor air conditioner units

Microwave ovens, electric rice cookers

{ Industrial equipment

•

Pumps

Vending machines

FA (Factory Automation)

<R>

1.3 Ordering Information

•

Flash memory version

Part Number

Package

Quality Grade

Standard

Special

µPD78F0101HMC-5A4

30-pin plastic SSOP (7.62 mm (300))

µPD78F0102HMC-5A4

µPD78F0103HMC-5A4

µPD78F0101HMC-5A4-A

µPD78F0102HMC-5A4-A

µPD78F0103HMC-5A4-A

µPD78F0101HMC(A)-5A4

µPD78F0102HMC(A)-5A4

µPD78F0103HMC(A)-5A4

µPD78F0101HMC(A)-5A4-A

µPD78F0102HMC(A)-5A4-A

µPD78F0103HMC(A)-5A4-A

µPD78F0101HMC(A1)-5A4

µPD78F0102HMC(A1)-5A4

µPD78F0103HMC(A1)-5A4

µPD78F0101HMC(A1)-5A4-A

µPD78F0102HMC(A1)-5A4-A

µPD78F0103HMC(A1)-5A4-A

Special

Remark Products that have the part numbers suffixed by "-A" are lead-free products.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

16

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.4 Pin Configuration (Top View)

•

30-pin plastic SSOP (7.62 mm (300))

P33/INTP4

P32/INTP3

P31/INTP2

P30/INTP1

FLMD0

1

P120/INTP0

AVSS

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

2

3

AVREF

4

P20/ANI0

5

P21/ANI1

V

SS

6

P22/ANI2

V

DD

7

P23/ANI3

X1[CL1]

X2[CL2]

8

P130

9

P17/TI50/TO50/FLMD1

P16/TOH1/INTP5

P15/TOH0

P14/RxD6

P13/TxD6

RESET

10

11

12

13

14

15

P03

P02

P01/TI010/TO00

P00/TI000

P10/SCK10/TxD0^Note

P12/SO10

P11/SI10/RxD0^Note

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

Caution Connect the AV^SSpin to VSS.

Remark Items in brackets are the pin names when external RC oscillation is used.

Pin Identification

ANI0 to ANI3:

AV^REF:

Analog input

Analog reference voltage RxD0^Note, RxD6:

RC oscillator SCK10:

RESET:

Reset

Receive data

CL1, CL2:

Serial clock input/output

Serial data input

Serial data output

Timer input

FLMD0, FLMD1: Flash programming mode SI10:

INTP0 to INTP5: External interrupt input

SO10:

P00 to P03:

P10 to P17:

P20 to P23:

P30 to P33:

P120:

Port 0

Port 1

Port 2

Port 3

Port 12

Port 13

TI000, TI010, TI50:

TO00, TO50, TOH0, TOH1: Timer output

TxD0^Note, TxD6:

Transmit data

V^DD:

Power supply

V^SS:

Ground

P130:

X1, X2:

Crystal oscillator (High-speed system clock)

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

17

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.5 Kx1 Series Lineup

1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup

•

30-pin SSOP (7.62 mm 0.65 mm pitch)

78K0/KB1

78K0/KB1+

µ

PD78F0103

µ

PD780103

µ

PD78F0103H

Mask ROM: 24 KB,

RAM: 768 B

Single-power-supply flash memory: 24 KB,

RAM: 768 B

Two-power-supply

flash memory: 24 KB,

RAM: 768 B

µ

PD78F0102H

PD780102

µ

Mask ROM: 16 KB,

RAM: 768 B

Single-power-supply flash memory: 16 KB,

RAM: 768 B

PD780101

µ

PD78F0101H

µ

Mask ROM: 8 KB,

RAM: 512 B

Single-power-supply flash memory: 8 KB,

RAM: 512 B

•

44-pin LQFP (10

78K0/KC1

×

10 mm 0.8 mm pitch)

78K0/KC1+

Note

PD78F0114

µ

PD780114

µ

PD78F0114H/HD

µ

Two-power-supply

flash memory: 32 KB,

RAM: 1 KB

Mask ROM: 32 KB,

RAM: 1 KB

Single-power-supply flash memory: 32 KB,

RAM: 1 KB

µ

PD780113

PD78F0113H

µ

Mask ROM: 24 KB,

RAM: 1 KB

Single-power-supply flash memory: 24 KB,

RAM: 1 KB

µ

PD780112

PD78F0112H

µ

Mask ROM: 16 KB,

RAM: 512 B

Single-power-supply flash memory: 16 KB,

RAM: 512 B

PD780111

µ

Mask ROM: 8 KB,

RAM: 512 B

•

52-pin LQFP (10

78K0/KD1

×

10 mm 0.65 mm pitch)

78K0/KD1+

PD78F0124

µ

PD780124

µ

PD78F0124H/HD^Note

µ

Mask ROM: 32 KB,

RAM: 1 KB

Single-power-supply flash memory: 32 KB,

RAM: 1 KB

Two-power-supply

flash memory: 32 KB,

RAM: 1 KB

µ

PD780123

µ

PD78F0123H

Mask ROM: 24 KB,

RAM: 1 KB

Single-power-supply flash memory: 24 KB,

RAM: 1 KB

µ

PD780122

µ

PD78F0122H

Mask ROM: 16 KB,

RAM: 512 B

Single-power-supply flash memory: 16 KB,

RAM: 512 B

PD780121

µ

Mask ROM: 8 KB,

RAM: 512 B

•

64-pin LQFP, TQFP (10

78K0/KE1

×

10 mm 0.5 mm pitch, 12

×

12 mm 0.65 mm pitch, 14

78K0/KE1+

PD78F0138H/HD^Note

× 14 mm 0.8 mm pitch)

µ

PD780138

µ

PD78F0138

Mask ROM: 60 KB,

RAM: 2 KB

Single-power-supply flash memory: 60 KB,

RAM: 2 KB

Two-power-supply

flash memory: 60 KB,

RAM: 2 KB

µ

PD780136

µPD78F0136H

Mask ROM: 48 KB,

RAM: 2 KB

Single-power-supply flash memory: 48 KB,

RAM: 2 KB

µ

PD78F0134

µ

PD780134

µ

PD78F0134H

Two-power-supply

flash memory: 32 KB,

RAM: 1 KB

Mask ROM: 32 KB,

RAM: 1 KB

Single-power-supply flash memory: 32 KB,

RAM: 1 KB

µ

PD780133

µPD78F0133H

Mask ROM: 24 KB,

RAM: 1 KB

Single-power-supply flash memory: 24 KB,

RAM: 1 KB

µ

PD780132

PD78F0132H

µ

Mask ROM: 16 KB,

RAM: 512 B

Single-power-supply flash memory: 16 KB,

RAM: 512 B

µ

PD780131

Mask ROM: 8 KB,

RAM: 512 B

•

80-pin TQFP, QFP (12

78K0/KF1

×

12 mm 0.5 mm pitch, 14

×

14 mm 0.65 mm pitch)

78K0/KF1+

Note

µ

PD78F0148H/HD

PD78F0148

PD780148

µ

Two-power-supply

flash memory: 60 KB,

RAM: 2 KB

Mask ROM: 60 KB,

RAM: 2 KB

Single-power-supply flash memory: 60 KB,

RAM: 2 KB

µ

PD780146

Mask ROM: 48 KB,

RAM: 2 KB

µ

PD780144

Mask ROM: 32 KB,

RAM: 1 KB

PD780143

µ

Mask ROM: 24 KB,

RAM: 1 KB

Note Product with on-chip debug function

18

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

The list of functions in the 78K0/Kx1 is shown below.

Part Number

78K0/KB1

78K0/KC1

78K0/KD1

52 pins

78K0/KE1

64 pins

78K0/KF1

80 pins

Item

Number of pins

30 pins

44 pins

Internal Mask ROM

8

16/

24

−

8/ 24/

16 32

−

8/ 24/

16 32

−

8/ 24/

16 32

−

48/

60

−

24/ 48/

32 60

−

memory

(KB)

Flash memory

RAM

−

24

−

32

−

32

−

32

−

60

−

60

0.5

0.75

0.5

1

0.5

1

0.5

1

2

1

2

Power supply voltage

V

DD = 2.5 to 5.5 V^{Notes 1, 2}

Minimum instruction execution time 0.166 µs (when 12 MHz, VDD = <Connect REGC pin to V^DD>

4.0 to 5.5 V)

0.2 µs (when 10 MHz, VDD =

3.5 to 5.5 V)

0.166 µs (when 12 MHz, VDD = 4.0 to 5.5 V)

0.2 µs (when 10 MHz, VDD = 3.5 to 5.5 V)

0.238 µs (when 8.38 MHz, VDD = 3.0 to 5.5 V)

0.238 µs (when 8.38 MHz, VDD 0.4 µs (when 5 MHz, VDD = 2.5 to 5.5 V)

= 3.0 to 5.5 V)

0.4 µs (when 5 MHz, VDD = 2.5

to 5.5 V)

Clock

Port

X1 input

2 to 12 MHz

Sub

−

32.768 kHz

240 kHz (TYP.)

26

Internal oscillation

CMOS I/O

17

4

19

38

54

CMOS input

CMOS output

N-ch open-drain I/O

16 bits (TM0)

8 bits (TM5)

8 bits (TMH)

For watch

8

1

−

1 ch

−

4

Timer

1 ch

2 ch

1 ch

2 ch

1 ch

2 ch

1 ch

WDT

3-wire CSI^{Note 3}

Serial

1 ch

2 ch

interface

Automatic transmit/

receive 3-wire CSI

−

1 ch

UART^{Note 3}

−

1 ch

UART supporting LIN-bus

10-bit A/D converter

Interrupt External

Internal

4 ch

6

8 ch

7

8

9

11

12

15

16

19

8 ch

17

20

Key return input

−

4 ch

Reset

RESET pin

POC

Provided

2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option)

LVI

2.85 V/3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software)

Clock monitor

WDT

Provided

Clock output/buzzer output

−

Clock output

only

Provided

Multiplier/divider

−

16 bits × 16 bits, 32 bits ÷ 16 bits

ROM correction

−

Provided

−

Standby function

HALT/STOP mode

Operating ambient temperature

Standard and special (A) grade products: −40 to +85°C

Special (A1) grade products: −40 to +110°C (mask ROM version),

−40 to +105°C (flash memory version)

Special (A2) grade products: −40 to +125°C (mask ROM version)

Notes 1. If the POC circuit detection voltage (VPOC) is used with 2.85 V 0.15 V, then use the products in the voltage

range of 3.0 to 5.5 V.

2. If the POC circuit detection voltage (V^POC) is used with 3.5 V 0.2 V, then use the products in the voltage

range of 3.7 to 5.5 V.

3. Select either of the functions of these alternate-function pins.

19

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

The list of functions in the 78K0/Kx1+ is shown below.

Part Number

78K0/KB1+

78K0/KC1+

78K0/KD1+

52 pins

78K0/KE1+

78K0/KF1+

Item

Number of pins

30 pins

44 pins

64 pins

24/32

80 pins

60

Internal Flash memory

memory

8

16/24

0.75

16

0.5

24/32

1

16

24/32

16

48/60

2

RAM

(KB)

0.5

1

0.5

1

2

Power supply voltage

V )

DD = 2.5 to 5.5 V (with internal oscillation clock or subclock: VDD = 2.0 to 5.5 V^{Note 1}

Minimum instruction execution time

0.125 µs (when 16 MHz, VDD = 4.0 to 5.5 V), 0.2 µs (when 10 MHz, VDD = 3.5 to 5.5 V),

0.238 µs (when 8.38 MHz, VDD = 3.0 to 5.5 V), 0.4 µs (when 5 MHz, VDD = 2.5 to 5.5 V)

Clock

Ports

Timer

Crystal/ceramic

2 to 16 MHz

RC

3 to 4 MHz

−

Sub

−

32.768 kHz

240 kHz (TYP.)

26

Internal oscillation

CMOS I/O

17

4

19

38

54

CMOS input

CMOS output

N-ch open-drain I/O

16 bits (TM0)

8 bits (TM5)

8 bits (TMH)

For watch

8

1

−

1 ch

−

4

1 ch

2 ch

1 ch

2 ch

1 ch

WDT

3-wire CSI^{Note 2}

Serial

1 ch

interface

Automatic transmit/

receive 3-wire CSI

−

1 ch

UART^{Note 2}

−

1 ch

UART supporting LIN-bus

10-bit A/D converter

Interrupts External

Internal

4 ch

6

8 ch

7

8

9

11

12

15

16

19

8 ch

20

Key return input

−

4 ch

Reset

RESET pin

POC

Provided

2.1 V 0.1 V (detection voltage is fixed)

LVI

2.35 V/2.6 V/2.85 V/3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V

(selectable by software)

Clock monitor

WDT

Provided

Clock output/buzzer output

−

Clock output

only

Provided

External bus interface

Multiplier/divider

−

Provided

16 bits × 16 bits, 32 bits ÷ 16 bits

Provided

−

ROM correction

−

Self-programming function

Provided

Product with on-chip debug

function

µPD78F0114HD, 78F0124HD, 78F0138HD, 78F0148HD

Standby function

HALT/STOP mode

Operating ambient temperature

TA = −40 to +85°C

Notes 1. Because the POC circuit detection voltage (VPOC) is 2.1 V 0.1 V, use the products in the voltage range of

2.2 to 5.5 V.

2. Select either of the functions of these alternate-function pins.

20

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup

•

64-pin plastic LQFP (10

64-pin plastic TQFP (12

×

10 mm, 0.5 mm pitch)

12 mm, 0.65 mm pitch)

V850ES/KE1

V850ES/KE1+

µ

PD703302Y

µ

PD70F3207HY

µ

PD703207Y

PD703207

µ

PD70F3302Y

PD703302

µ

PD70F3302

µ

PD70F3207H

Mask ROM: 128 KB,

RAM: 4 KB

Mask ROM: 128 KB,

RAM: 4 KB

Single-power flash: 128 KB,

RAM: 4 KB

Single-power flash: 128 KB,

RAM: 4 KB

•

80-pin plastic TQFP (12

×

12 mm, 0.5 mm pitch)

80-pin plastic QFP (14

× 14 mm, 0.65 mm pitch)

V850ES/KF1

V850ES/KF1+

µ

PD70F3211HY

PD703211Y

PD703211

µ

PD70F3308Y

µPD703308Y

PD703308

µ

PD70F3211H

µ

PD70F3308

µ

Single-power flash: 256 KB,

RAM: 12 KB

Mask ROM: 256 KB,

RAM: 12 KB

Single-power flash: 256 KB,

RAM: 12 KB

Mask ROM: 256 KB,

RAM: 12 KB

µ

PD703210Y

PD70F3210HY

µ

PD70F3306Y

PD70F3306

µ

PD70F3210H

µ

PD703210

µ

Single-power flash: 128 KB,

RAM: 6 KB

Mask ROM: 128 KB,

RAM: 6 KB

Single-power flash: 128 KB,

RAM: 6 KB

µ

PD70F3210Y

µ

PD703209Y

PD703209

µ

PD70F3210

µ

Mask ROM: 96 KB,

RAM: 4 KB

Two-power flash: 128 KB,

RAM: 6 KB

µ

PD703208Y

µ

PD703208

Mask ROM: 64 KB,

RAM: 4 KB

•

100-pin plastic LQFP (14

×

14 mm, 0.5 mm pitch)

100-pin plastic QFP (14

× 20 mm, 0.65 mm pitch)

V850ES/KG1

V850ES/KG1+

µ

PD70F3215HY

µ

PD703215Y

PD703215

µ

PD70F3313Y

PD70F3313

PD703313Y

µ

PD70F3215H

µ

µPD703313

Single-power flash: 256 KB,

RAM: 16 KB

Mask ROM: 256 KB,

RAM: 16 KB

Single-power flash: 256 KB,

RAM: 16 KB

Mask ROM: 256 KB,

RAM: 16 KB

µ

PD70F3214HY

PD703214Y

PD70F3311Y

µ

PD70F3214H

µ

PD703214

µ

PD70F3311

Single-power flash: 128 KB,

RAM: 6 KB

Mask ROM: 128 KB,

RAM: 6 KB

Single-power flash: 128 KB,

RAM: 6 KB

µ

PD703213Y

µ

PD70F3214Y

µ

PD70F3214

PD703213

µ

Mask ROM: 96 KB,

RAM: 4 KB

Two-power flash: 128 KB,

RAM: 6 KB

µ

PD703212Y

PD703212

µ

Mask ROM: 64 KB,

RAM: 4 KB

•

144-pin plastic LQFP (20

V850ES/KJ1

× 20 mm, 0.5 mm pitch)

V850ES/KJ1+

µ

PD70F3318Y

PD70F3318

µ

PD70F3218HY

µ

PD70F3218H

Single-power flash: 256 KB,

RAM: 16 KB

Single-power flash: 256 KB,

RAM: 16 KB

µ

PD70F3217HY

µ

PD703217Y

µ

PD70F3316Y

µ

PD70F3217H

µ

PD703217

PD70F3316

µ

Single-power flash: 128 KB,

RAM: 6 KB

Mask ROM: 128 KB,

RAM: 6 KB

Single-power flash: 128 KB,

RAM: 6 KB

µ

PD70F3217Y

PD703216Y

µ

PD70F3217

µ

PD703216

Two-power flash: 128 KB,

RAM: 6 KB

Mask ROM: 96 KB,

RAM: 6 KB

21

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

The list of functions in the V850ES/Kx1 is shown below.

Product Name

Number of pins

V850ES/KE1

64 pins

V850ES/KF1

80 pins

V850ES/KG1

100 pins

V850ES/KJ1

144 pins

−

Internal

memory

(KB)

Mask ROM

128

−

64/ 128

−

256

−

64/ 128

96

−

256

−

96/

−

96

−

128

Flash memory

RAM

−

128

−

128

−

256

−

128

−

256

−

128

6

256

16

4

6

12

4

6

16

Supply voltage

2.7 to 5.5 V

Minimum instruction execution time

50 ns @20 MHz

2 to 10 MHz

32.768 kHz

−

Clock

X1 input

Sub

Internal oscillator

CMOS input

CMOS I/O

N-ch open-drain I/O

16-bit (TMP)

16-bit (TM0)

8-bit (TM5)

8-bit (TMH)

Interval timer

Watch

Port

8

41 (4)^{Note 1}

2

8

16

106 (12)^{Note 1}

6

57 (6)^{Note 1}

72 (8)^{Note 1}

2

4

Timer

1 ch

2 ch

1 ch

−

1 ch

−

1 ch

−

1 ch

2 ch

4 ch

2 ch

6 ch

2 ch

1 ch

WDT1

1 ch

WDT2

1 ch

RTO

6 bits × 1 ch

2 ch

6 bits × 1 ch

2 ch

6 bits × 2 ch

3 ch

Serial

CSI

2 ch

interface

Automatic transmit/receive

3-wire CSI

−

1 ch

2 ch

UART

2 ch

−

2 ch

−

3 ch

−

UART supporting LIN-bus

I²C^{Note 2}

−

1 ch

3 MB

22 bits

2 ch

External

bus

Address space

Address bus

Mode

−

128 KB

16 bits

15 MB

24 bits

−

Multiplex only

Multiplex/separate

DMA controller

10-bit A/D converter

8-bit D/A converter

Interrupt External

Internal

−

8 ch

−

8 ch

−

16 ch

2 ch

8

8 ch

2 ch

8

25/26^{Note 2}

28/29^{Note 2}

30/31^{Note 2}

33/34^{Note 2}

38/40^{Note 2}

41/43^{Note 2}

Key return input

8 ch

Reset

RESET pin

Provided

None

POC

LVI

None

Clock monitor

WDT1

WDT2

None

Provided

4

ROM correction

Regulator

None

Provided

HALT/IDLE/STOP/sub-IDLE mode

= −40 to +85°C

Standby function

Operating ambient temperature

TA

Notes 1. The number of channels in parentheses indicates the number of pins for which the N-ch open drain

output can be selected by software.

2. Only in products with an I²C bus (Y products). For the product name, refer to each user’s manual.

22

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

The list of functions in the V850ES/Kx1+ is shown below.

Product Name

Number of pins

V850ES/KE1+

64 pins

V850ES/KF1+

V850ES/KG1+

V850ES/KJ1+

144 pins

80 pins

256

−

100 pins

Internal

memory

(KB)

Mask ROM

Flash memory

RAM

128

−

128

6

−

128

6

256

−

128

256

128

6

256

16

4

12

16

Supply voltage

2.7 to 5.5 V

Minimum instruction execution time

50 ns @20 MHz

2 to 10 MHz

Clock

X1 input

Sub

32.768 kHz

Internal oscillator

CMOS input

CMOS I/O

N-ch open-drain I/O

16-bit (TMP)

16-bit (TM0)

8-bit (TM5)

8-bit (TMH)

Interval timer

Watch

240 kHz (TYP.)

Port

8

41 (4)^{Note 1}

2

8

57 (6)^{Note 1}

2

8

72 (8)^{Note 1}

4

16

106 (12)^{Note 1}

6

Timer

1 ch

2 ch

1 ch

2 ch

4 ch

6 ch

2 ch

1 ch

WDT1

1 ch

WDT2

1 ch

RTO

6 bits × 1 ch

2 ch

6 bits × 1 ch

2 ch

6 bits × 2 ch

3 ch

Serial

CSI

2 ch

interface

Automatic transmit/receive

3-wire CSI

−

1 ch

2 ch

UART

1 ch

2 ch

1 ch

2 ch

1 ch

UART supporting LIN-bus

I²C^{Note 2}

1 ch

2 ch

External

bus

Address space

Address bus

Mode

−

128 KB

16 bits

3 MB

22 bits

15 MB

24 bits

−

Multiplex only

Multiplex/separate

DMA controller

10-bit A/D converter

8-bit D/A converter

Interrupt External

Internal

−

8 ch

−

8 ch

−

4 ch

8 ch

4 ch

16 ch

2 ch

9

26/27^{Note 2}

29/30^{Note 2}

41/42^{Note 2}

46/48^{Note 2}

Key return input

8 ch

Reset

RESET pin

Provided

2.7 V or less fixed

POC

LVI

3.1 V/3.3 V 0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software)

Clock monitor

WDT1

WDT2

Provided (monitor by internal oscillator)

Provided

ROM correction

4

None

Regulator

None

Provided

HALT/IDLE/STOP/sub-IDLE mode

= −40 to +85°C

Standby function

Operating ambient temperature

TA

Notes 1. The number of channels in parentheses indicates the number of pins for which the N-ch open drain

output can be selected by software.

2. Only in products with an I²C bus (Y products). For the product name, refer to each user’s manual.

23

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

1.6 Block Diagram

TO00/TI010/P01

TI000/P00

16-bit timer/

event counter 00

4

8

4

Port 0

Port 1

P00 to P03

P10 to P17

P20 to P23

P30 to P33

P120

8-bit timer H0

8-bit timer H1

TOH0/P15

TOH1/P16

Port 2

Port 3

Port 12

78K/0

Flash

CPU

8-bit timer/

event counter 50

TI50/TO50/P17

memory

core

Port 13

P130

Watchdog timer

Clock monitor

RxD0^Note/P11

TxD0^Note/P10

Serial interface

UART0^Note

Power-on-clear/

low voltage

indicator

POC/LVI

control

Internal

high-speed

RAM

RxD6/P14

TxD6/P13

Serial interface

UART6

Reset control

SI10/P11

SO10/P12

SCK10/P10

Serial interface

CSI10

Internal

Oscillator

ANI0/P20 to

4

RESET

X1[CL1]

X2[CL2]

ANI3/P23

System control

A/D converter

AVREF

AVSS

INTP0/P120

Interrupt control

INTP1/P30 to

4

INTP4/P33

VDD

V

SS FLMD0,

FLMD1

Note µPD78F0102H and 78F0103H only.

Remark Items in brackets are the pin names when external RC oscillation is used.

24

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CHAPTER 1 OUTLINE

1.7 Outline of Functions

(1/2)

Item

µPD78F0101H

µPD78F0102H

µPD78F0103H

Internal memory Flash memory

(self-programming

8 KB

16 KB

24 KB

supported)

High-speed RAM

Memory space

512 bytes

64 KB

768 bytes

<R>

High-speed Crystal/

Standard

2 to 16 MHz: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V,

system

ceramic/

external

clock

products and 2 to 8.38 MHz: VDD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.5 to 5.5 V

clock

(A) grade

products

(oscillation

frequency)

oscillation

(A1) grade

products

2 to 16 MHz: VDD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V,

2 to 8.38 MHz: VDD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V

External RC/external

clock oscillation

3 to 4 MHz: VDD = 2.7 to 5.5 V

Internal oscillation clock

(oscillation frequency)

Internal oscillation (240 kHz (TYP.): VDD = 2.0 to 5.5 V^{Notes 2, 3}

)

General-purpose registers

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.125 µs/0.25 µs/0.5 µs/1.0 µs/2.0 µs (high-speed system clock: @ fXP = 16 MHz operation)

8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.)

(internal oscillation clock: @ f^R= 240 kHz (TYP.) operation)

Instruction set

I/O ports

• 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc.

Total:

22

CMOS I/O

17

4

CMOS input

CMOS output

1

Timers

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 1 channel

• 8-bit timer:

2 channels

1 channel

• Watchdog timer:

Timer outputs

A/D converter

4 (PWM: 3)

10-bit resolution × 4 channels

Serial interface

• UART mode supporting LIN-bus:

1 channel

• 3-wire serial I/O mode/UART mode^{Note 1}: 1 channel

(µPD78F0101H only, 3-wire serial I/O mode: 1 channel)

Vectored

Internal

External

11

12

interrupt sources

6

Reset

• Reset using RESET pin

• Internal reset by watchdog timer

• Internal reset by clock monitor

• Internal reset by power-on-clear

• Internal reset by low-voltage detector

Notes 1. Select either of the functions of these alternate-function pins.

2. Use the standard products and (A) grade products in a voltage range of 2.2 to 5.5 V because the

detection voltage (V^POC) of the power-on-clear (POC) circuit is 2.1 V 0.1 V.

<R>

3. Use the (A1) grade products in a voltage range of 2.25 to 5.5 V because the detection voltage (V^POC) of

the power-on-clear (POC) circuit is 2.0 to 2.25 V.

25

User’s Manual U16846EJ3V0UD

CHAPTER 1 OUTLINE

(2/2)

Item

<R> Supply voltage

µPD78F0101H

µPD78F0102H

µPD78F0103H

• Standard products and (A) grade products:

V^DD= 2.5 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 V^{Note 1}

)

• (A1) grade products:

V^DD= 2.7 to 5.5 V (with internal oscillation clock: VDD = 2.0 to 5.5 V^{Note 2}

Operating ambient temperature

Package

• Standard products and (A) grade products : TA = −40 to +85°C

<R>

• (A1) grade products :

T^A= −40 to +110°C

• 30-pin plastic SSOP (7.62 mm (300))

Notes 1. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is 2.1 V 0.1 V.

2. Use the product in a voltage range of 2.25 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.0 to 2.25 V.

An outline of the timer is shown below.

16-Bit Timer/Event

Counter 00

8-Bit Timer/Event

Counter 50

8-Bit Timers H0 and H1

Watchdog Timer

TMH0

TMH1

Operation Interval timer

mode

1 channel

−

1 channel

−

External event counter

1 channel

−

Watchdog timer

Timer output

−

1 channel

Function

1 output

−

1 output

−

PPG output

−

PWM output

1 output

Pulse width measurement

Square-wave output

Interrupt source

2 inputs

1 output

2

−

1 output

1

−

1 output

1

−

1 output

1

26

User’s Manual U16846EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

There are two types of pin I/O buffer power supplies: AV^REFand VDD. The relationship between these power

supplies and the pins is shown below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply

AVREF

Corresponding Pins

P20 to P23

Pins other than P20 to P23

VDD

(1) Port pins

Pin Name

I/O

Function

After Reset Alternate Function

P00

P01

P02

P03

I/O

Port 0.

4-bit I/O port.

Input

TI000

TI010/TO00

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

−

P10

Port 1.

Input

SCK10/TxD0^Note

SI10/RxD0^Note

SO10

8-bit I/O port.

P11

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P12

P13

TxD6

P14

RxD6

P15

TOH0

P16

TOH1/INTP5

TI50/TO50/FLMD1

ANI0 to ANI3

P17

P20 to P23

Input

I/O

Port 2.

Input

4-bit input-only port.

P30 to P33

Port 3.

INTP1 to INTP4

4-bit I/O port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P120

I/O

Port 12.

Input

INTP0

1-bit I/O port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P130

Output

Port 13.

Output

−

1-bit output-only port.

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

27

User’s Manual U16846EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

I/O

Input

Function

After Reset Alternate Function

INTP0

External interrupt request input for which the valid edge (rising Input

edge, falling edge, or both rising and falling edges) can be

specified

P120

INTP1 to INTP4

INTP5

P30 to P33

P16/TOH1

P11/RxD0^Note

P12

SI10

Input

Serial data input to serial interface

Input

SO10

Output

I/O

Serial data output from serial interface

Clock input/output for serial interface

Serial data input to asynchronous serial interface

SCK10

RxD0^Note

RxD6

P10/TxD0^Note

P11/SI10

P14

Input

TxD0^Note

Output

Input

Serial data output from asynchronous serial interface

Input

P10/SCK10

P13

TxD6

TI000

External count clock input to 16-bit timer/event counter 00

Capture trigger input to capture registers (CR000, CR010) of

16-bit timer/event counter 00

P00

TI010

Capture trigger input to capture register (CR000) of 16-bit

timer/event counter 00

P01/TO00

TO00

Output

Input

16-bit timer/event counter 00 output

External count clock input to 8-bit timer/event counter 50

8-bit timer/event counter 50 output

8-bit timer H0 output

Input

P01/TI010

P17/TO50/FLMD1

P17/TI50/FLMD1

P15

TI50

TO50

Output

TOH0

TOH1

8-bit timer H1 output

P16/INTP5

P20 to P23

−

ANI0 to ANI3

AVREF

Input

A/D converter analog input

Input

A/D converter reference voltage input and positive power

supply for port 2

−

AVSS

−

A/D converter ground potential. Make the same potential as

V^SS.

−

RESET

X1[CL1]

X2[CL2]

VDD

Input

System reset input

−

Input

Connecting resonator for high-speed system clock

[RC connection for high-speed system clock]

−

Positive power supply

−

VSS

Ground potential

−

FLMD0

FLMD1

Flash memory programming mode setting.

−

Input

P17/TI50/TO50

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

Remark Items in brackets are the pin names when external RC oscillation is used.

28

User’s Manual U16846EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P03 (port 0)

P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode

register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

(2) Control mode

P00 to P03 function as timer I/O.

(a) TI000

This is the pins for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a

capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.

(b) TI010

This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event

counter 00.

(c) TO00

This is a timer output pin.

2.2.2 P10 to P17 (port 1)

P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial

interface data I/O, clock I/O, and timer I/O, and flash memory programming mode setting.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode

register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).

(2) Control mode

P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O, and flash

memory programming mode setting.

(a) SI10

This is a serial data input pin of the serial interface.

(b) SO10

This is a serial data output pin of the serial interface.

(c) SCK10

This is a serial clock I/O pin of the serial interface.

(d) RxD0^Note, RxD6

These are the serial data input pins of the asynchronous serial interface.

29

User’s Manual U16846EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

(e) TxD0^Note, TxD6

These are serial data output pins of the asynchronous serial interface.

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

(f) TI50

This is the pin for inputting an external count clock to 8-bit timer/event counter 50.

(g) TO50, TOH0, and TOH1

These are timer output pins.

(h) INTP5

This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising

and falling edges) can be specified.

(i) FLMD1

This pin sets the flash memory programming mode.

2.2.3 P20 to P23 (port 2)

P20 to P23 function as a 4-bit input-only port. These pins also function as pins for A/D converter analog input.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P20 to P23 function as a 4-bit input-only port.

(2) Control mode

P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input

pins, see (5) ANI0/P20 to ANI3/P23 in 10.6 Cautions for A/D Converter.

2.2.4 P30 to P33 (port 3)

P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode

register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).

(2) Control mode

P30 to P33 function as external interrupt request input pins (INTP1 to INTP4) for which the valid edge (rising

edge, falling edge, or both rising and falling edges) can be specified.

2.2.5 P120 (port 12)

P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P120 functions as a 1-bit I/O port. P120 can be set to input or output in 1-bit units using port mode register 12

(PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).

30

User’s Manual U16846EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Control mode

P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling

edge, or both rising and falling edges) can be specified.

2.2.6 P130 (port 13)

P130 functions as a 1-bit output-only port.

2.2.7 AV^REF

This is the A/D converter reference voltage input pin.

When A/D converter is not used, connect this pin directly to V^DD.

2.2.8 AV^SS

This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with

the same potential as the V^SSpin.

2.2.9 RESET

This is the active-low system reset input pin.

2.2.10 X1 and X2

These are the pins for connecting a resonator for high-speed system clock oscillation.

When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.

2.2.11 CL1 and CL2

These are the pins for connecting a resistor (R) and capacitor (C) for high-speed system clock oscillation.

When supplying an external clock, input a signal to the CL1 pin and input the inverse signal to the CL2 pin.

2.2.12 V^DD

This is the positive power supply pin.

2.2.13 V^SS

This is the ground potential pin.

2.2.14 FLMD0 and FLMD1

These pins set the flash memory programming mode.

Connect FLMD0 to V^SSin the normal operation mode (FLMD1 is not used in the normal operation mode).

Always connect FLMD0 and FLMD1 to the flash programmer in the flash memory programming mode.

31

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-2 shows the types of pin I/O circuit and the recommended connections of unused pins.

Refer to Figure 2-1 for the configuration of the I/O circuits of each type.

Table 2-2. Pin I/O Circuit Types

Pin Name

P00/TI000

I/O Circuit Type

8-A

I/O

Recommended Connection of Unused Pins

I/O

Input: Independently connect to V^DDor VSS via a resistor.

Output: Leave open.

P01/TI010/TO00

P02

P03

P10/SCK10/TxD0^Note

P11/SI10/RxD0^Note

P12/SO10

5-A

P13/TxD6

P14/RxD6

8-A

5-A

8-A

P15/TOH0

P16/TOH1/INTP5

P17/TI50/TO50/FLMD1

P20/ANI0 to P23/ANI3

P30/INTP1 to P33/INTP4

P120/INTP0

P130

9-C

8-A

Input

I/O

Connect to VDD or VSS.

Input: Independently connect to V^DDor VSS via a resistor.

Output: Leave open.

3-C

2

Output

Input

−

Leave open.

RESET

Connect to VDD.

AVREF

−

Connect directly to VDD.

Connect directly to VSS.

Connect to VSS.

AVSS

FLMD0

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

32

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuit List

Type 2

Type 8-A

V

DD

Pull-up

enable

P-ch

IN

V

DD

Data

P-ch

IN/OUT

Schmitt-triggered input with hysteresis characteristics

Output

disable

N-ch

Type 3-C

Type 9-C

V

DD

Comparator

+

P-ch

N-ch

IN

P-ch

–

AV^SS

Data

OUT

V

REF

(threshold voltage)

N-ch

Input

enable

Type 5-A

VDD

Pull-up

enable

P-ch

V

DD

Data

P-ch

IN/OUT

Output

disable

N-ch

Input

enable

33

User’s Manual U16846EJ3V0UD

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the 78K0/KB1+ can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps.

Caution Regardless of the internal memory capacity, the initial values of internal memory size switching

register (IMS) of all products in the 78K0/KB1+ are fixed (IMS = CFH). Therefore, set the value

corresponding to each product as indicated below. In addition, set the following values to the

internal memory size switching register (IMS) when using the 78K0/KB1+ to evaluate the program

of a mask ROM version of the 78K0/KB1.

Table 3-1. Internal Memory Size Switching Register (IMS) Set Value

Flash Memory Version

(78K0/KB1+)

Target Mask ROM Version

(78K0/KB1)

Internal Memory Size

Switching Register (IMS)

µPD78F0101H

µPD78F0102H

µPD78F0103H

µPD780101

µPD780102

µPD780103

42H

04H

06H

34

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CHAPTER 3 CPU ARCHITECTURE

<R>

Figure 3-1. Memory Map (µPD78F0101H)

F FFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

1FFFH

FFFH

1

Program area

Internal high-speed RAM

1 0 8 5H

1 0 8 4H

512 × 8 bits

Option byte area^Note

5 × 8 bits

1 0 8 0H

1 0 7FH

Boot cluster 1

FD0 0H

FCFF

H

Program area

Data memory

space

1 0 0 0H

0FFFH

CALLF entry area

2048 × 8 bits

0 8 0 0H

Reserved

0

7FFH

Program area

1915 × 8 bits

0 0 8 5H

Option byte area^Note

0

0 8 4H

Boot cluster 0

5 × 8 bits

0 0 8 0H

0 0 7FH

2 0 0 0

1FFF

H

CALLT table area

64 × 8 bits

0 0 4 0H

0 0 3FH

Flash memory

Program

8192 × 8 bits

memory space

Vector table area

64 × 8 bits

0 0 0 0

H

Note When boot swap is not used: Set the option bytes to 0080H to 0084H.

When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.

35

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CHAPTER 3 CPU ARCHITECTURE

<R>

Figure 3-2. Memory Map (µPD78F0102H)

F FFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

3FFFH

Program area

1FFFH

1 0 8 5H

1 0 8 4H

Internal high-speed RAM

Option byte area^Note

768 × 8 bits

5 × 8 bits

1 0 8 0H

1 0 7FH

Boot cluster 1

FC0 0H

Program area

FBFF

H

Data memory

space

1 0 0 0H

0FFFH

CALLF entry area

2048 × 8 bits

0 8 0 0H

0

7FFH

Reserved

Program area

1915 × 8 bits

0 0 8 5H

Option byte area^Note

0

0 8 4H

Boot cluster 0

5 × 8 bits

0 0 8 0H

0 0 7FH

4 0 0 0

3FFF

H

CALLT table area

64 × 8 bits

0 0 4 0H

0 0 3FH

Program

memory space

Flash memory

16384 × 8 bits

Vector table area

64 × 8 bits

0

0 0 0H

0 0 0 0

H

Note When boot swap is not used: Set the option bytes to 0080H to 0084H.

When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.

36

User’s Manual U16846EJ3V0UD

CHAPTER 3 CPU ARCHITECTURE

<R>

Figure 3-3. Memory Map (µPD78F0103H)

FFFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

5

FFFH

Program area

1FFFH

1 0 8 5H

1 0 8 4H

Internal high-speed RAM

Option byte area^Note

768 × 8 bits

5 × 8 bits

1 0 8 0H

1 0 7FH

Boot cluster 1

FC0 0H

Program area

FBFF

H

Data memory

space

1 0 0 0H

0FFFH

CALLF entry area

2048 × 8 bits

0 8 0 0

H

0

7FFH

Reserved

Program area

1915 × 8 bits

0 0 8 5H

Option byte area^Note

0

0 8 4H

Boot cluster 0

5 × 8 bits

0 0 8 0H

0 0 7FH

6 0 0 0

5FFF

H

CALLT table area

64 × 8 bits

0 0 4 0H

0 0 3FH

Program

memory space

Flash memory

24576 × 8 bits

Vector table area

64 × 8 bits

0 0 0 0H

0 0 0 0

H

Note When boot swap is not used: Set the option bytes to 0080H to 0084H.

When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores the program and table data. Normally, it is addressed with the program

counter (PC).

78K0/KB1+ products incorporate internal ROM (flash memory), as shown below.

Table 3-2. Internal ROM Capacity

Part Number

Internal ROM

Structure

Flash memory

Capacity

µPD78F0101H

8192 × 8 bits (0000H to 1FFFH)

16384 × 8 bits (0000H to 3FFFH)

24576 × 8 bits (0000H to 5FFFH)

µPD78F0102H

µPD78F0103H

The internal program memory space is divided into the following areas.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch

upon reset signal input or generation of each interrupt request are stored in the vector table area.

Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd

addresses.

Table 3-3. Vector Table

Vector Table Address

0000H

Interrupt Source

Vector Table Address

0016H

Interrupt Source

INTST6

RESET input, POC, LVI

clock monitor, WDT

0018H

INTCSI10/INTST0^Note

INTTMH1

INTTMH0

INTTM50

INTTM000

INTTM010

INTAD

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

INTLVI

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTSRE6

INTSR6

001AH

001CH

001EH

0020H

0022H

0024H

0026H

INTSR0^Note

003EH

BRK

Note Available only in the µPD78F0102H and 78F0103H.

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) Option byte area

The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 20 OPTION BYTE for details.

(4) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

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3.1.2 Internal data memory space

78K0/KB1+ products incorporate the following internal high-speed RAM.

Table 3-4. Internal High-Speed RAM Capacity

Part Number

µPD78F0101H

Internal High-Speed RAM

512 × 8 bits (FD00H to FEFFH)

768 × 8 bits (FC00H to FEFFH)

µPD78F0102H

µPD78F0103H

The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit

registers per bank.

This area cannot be used as a program area in which instructions are written and executed.

The internal high-speed RAM can also be used as a stack memory.

3.1.3 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to

Table 3-5 Special Function Register List in 3.2.3 Special function registers (SFRs)).

Caution Do not access addresses to which SFRs are not assigned.

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3.1.4 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of

the register or memory relevant to the execution of instructions.

Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the

78K0/KB1+, based on operability and other considerations. For areas containing data memory in particular, special

addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are

available for use. Figures 3-4 to 3-6 show the correspondence between data memory and addressing. For details of

each addressing mode, refer to 3.4 Operand Address Addressing.

Figure 3-4. Correspondence Between Data Memory and Addressing (µPD78F0101H)

FFFFH

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF2 0H

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

512 × 8 bits

FE2 0H

FE1F

H

FD0 0H

FCFF

H

Direct addressing

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

2 0 0 0

1FFF

H

Flash memory

8192 × 8 bits

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Correspondence Between Data Memory and Addressing (µPD78F0102H)

FFFFH

FF2 0H

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

FE2 0H

FE1F

H

Direct addressing

FC0 0H

FBFF

H

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

4 0 0 0

3FFF

H

Flash memory

16384 × 8 bits

0 0 0 0

H

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Figure 3-6. Correspondence Between Data Memory and Addressing (µPD78F0103H)

FFFFH

FF2 0H

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

FE2 0H

FE1F

H

Direct addressing

FC0 0H

FBFF

H

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

6 0 0 0

5FFF

H

Flash memory

24576 × 8 bits

0 0 0 0

H

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3.2 Processor Registers

78K0/KB1+ products incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist of a

program counter (PC), a program status word (PSW) and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be

fetched. When a branch instruction is executed, immediate data and register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Format of Program Counter

15

0

PC

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are reset upon execution of the RETB, RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-8. Format of Program Status Word

7

0

PSW

IE

Z

RBS1

AC

RBS0

0

ISP

CY

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgment operations of the CPU.

When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all disabled.

When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment enable is

controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a

priority specification flag.

The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI

instruction execution.

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(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Register bank select flags (RBS0 and RBS1)

These are 2-bit flags to select one of the four register banks.

In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction

execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other

cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-

level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L) (refer

to 14.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) can not be acknowledged. Actual

request acknowledgment is controlled by the interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores on overflow or underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM

area can be set as the stack area.

Figure 3-9. Format of Stack Pointer

15

0

SP

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from

the stack memory.

Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before use.

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Figure 3-10. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

Register pair upper

Register pair lower

(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

PC15-PC8

PC7-PC0

(c) Interrupt, BRK instructions (when SP = FEE0H)

FEE0H

FEDFH

FEDEH

FEDDH

SP

PSW

PC15-PC8

PC7-PC0

FEDDH

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Figure 3-11. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

Register pair upper

Register pair lower

(b) RET instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

PC15-PC8

PC7-PC0

(c) RETI, RETB instructions (when SP = FEDDH)

FEE0H

FEDFH

FEDEH

FEDDH

SP

PSW

PC15-PC8

PC7-PC0

FEDDH

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3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The

general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register

(AX, BC, DE, and HL).

These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and

absolute names (R0 to R7 and RP0 to RP3).

Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of

the 4-register bank configuration, an efficient program can be created by switching between a register for normal

processing and a register for interrupts for each bank.

Figure 3-12. Configuration of General-Purpose Registers

(a) Absolute name

16-bit processing

RP3

8-bit processing

R7

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

R6

R5

R4

R3

R2

R1

R0

RP2

RP1

RP0

FEF0H

FEE8H

FEE0H

15

0

7

0

(b) Function name

16-bit processing

8-bit processing

H

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

HL

DE

BC

AX

L

D

E

B

C

A

X

FEF0H

FEE8H

FEE0H

15

0

7

0

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3.2.3 Special function registers (SFRs)

Unlike a general-purpose register, each special function register has a special function.

SFRs are allocated to the FF00H to FFFFH area.

Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit

manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.

Each manipulation bit unit can be specified as follows.

•

1-bit manipulation

Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can also be specified with an address.

8-bit manipulation

Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can also be specified with an address.

16-bit manipulation

Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).

When specifying an address, describe an even address.

Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.

•

Symbol

Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined

as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-NS,

ID78K0, or SM78K0, symbols can be written as an instruction operand.

R/W

•

Indicates whether the corresponding special function register can be read or written.

R/W: Read/write enable

R:

Read only

W: Write only

•

Manipulatable bit units

Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.

After reset

Indicates each register status upon RESET input.

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Table 3-5. Special Function Register List (1/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

16 Bits

FF00H

FF01H

FF02H

FF03H

FF08H

FF09H

FF0AH

FF0BH

FF0CH

FF0DH

FF0FH

FF10H

FF11H

FF12H

FF13H

FF14H

FF15H

FF16H

FF17H

FF18H

FF19H

FF1AH

FF1BH

FF20H

FF21H

FF23H

FF28H

FF29H

FF2AH

FF2BH

FF2CH

FF30H

FF31H

FF33H

FF3CH

FF48H

FF49H

FF4FH

Port register 0

P0

P1

P2

P3

R/W

R

√

−

√

−

√

00H

Port register 1

Port register 2

Undefined

00H

Port register 3

R/W

R

A/D conversion result register

ADCR

Undefined

Receive buffer register 6

Transmit buffer register 6

Port register 12

RXB6

TXB6

P12

R

R/W

R

−

√

−

√

−

√

FFH

00H

Port register 13

P13

00H

Serial I/O shift register 10

16-bit timer counter 00

SIO10

TM00

00H

R

0000H

16-bit timer capture/compare register 000

16-bit timer capture/compare register 010

CR000

CR010

R/W

−

√

0000H

8-bit timer counter 50

TM50

CR50

CMP00

CMP10

CMP01

CMP11

PM0

R

−

√

−

√

−

00H

FFH

00H

FFH

00H

8-bit timer compare register 50

8-bit timer H compare register 00

8-bit timer H compare register 10

8-bit timer H compare register 01

8-bit timer H compare register 11

Port mode register 0

R/W

Port mode register 1

PM1

Port mode register 3

PM3

A/D converter mode register

ADM

ADS

Analog input channel specification register

Power-fail comparison mode register

Power-fail comparison threshold register

Port mode register 12

PFM

PFT

PM12

PU0

Pull-up resistor option register 0

Pull-up resistor option register 1

Pull-up resistor option register 3

Pull-up resistor option register 12

External interrupt rising edge enable register

External interrupt falling edge enable register

Input switch control register

PU1

PU3

PU12

EGP

EGN

ISC

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Table 3-5. Special Function Register List (2/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

16 Bits

FF50H

FF53H

FF55H

Asynchronous serial interface operation mode

register 6

ASIM6

R/W

R

√

−

√

−

01H

00H

Asynchronous serial interface reception error

status register 6

ASIS6

ASIF6

√

Asynchronous serial interface transmission

status register 6

R

FF56H

FF57H

FF58H

FF69H

FF6AH

FF6BH

FF6CH

FF70H

Clock selection register 6

CKSR6

BRGC6

ASICL6

TMHMD0

TCL50

R/W

−

√

−

√

−

00H

FFH

16H

00H

01H

Baud rate generator control register 6

Asynchronous serial interface control register 6

8-bit timer H mode register 0

Timer clock selection register 50

8-bit timer mode control register 50

8-bit timer H mode register 1

TMC50

TMHMD1

ASIM0

Asynchronous serial interface operation mode

register 0^{Note 1}

FF71H

FF72H

FF73H

Baud rate generator control register 0^{Note 1}

Receive buffer register 0^{Note 1}

BRGC0

RXB0

R/W

R

−

√

−

1FH

FFH

00H

Asynchronous serial interface reception error

status register 0^{Note 1}

ASIS0

R

FF74H

FF80H

FF81H

FF84H

FF98H

FF99H

FFA0H

FFA1H

FFA2H

FFA3H

Transmit shift register 0^{Note 1}

Serial operation mode register 10

Serial clock selection register 10

Transmit buffer register 10

TXS0

W

−

√

−

√

−

FFH

00H

CSIM10

CSIC10

SOTB10

WDTM

WDTE

RCM

R/W

R

00H

Undefined

67H

Watchdog timer mode register

Watchdog timer enable register

Internal oscillation mode register

Main clock mode register

9AH

00H

MCM

00H

Main OSC control register

MOC

00H

Oscillation stabilization time counter status

register

OSTC

00H

FFA4H

FFA9H

FFACH

FFBAH

FFBBH

Oscillation stabilization time select register

Clock monitor mode register

OSTS

CLM

R/W

R

−

√

−

√

−

05H

00H

Reset control flag register

RESF

TMC00

PRM00

00H^{Note 2}

16-bit timer mode control register 00

Prescaler mode register 00

R/W

00H

Notes 1. µPD78F0102H and 78F0103H only.

2. This value varies depending on the reset source.

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Table 3-5. Special Function Register List (3/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

16 Bits

FFBCH

FFBDH

FFBEH

FFBFH

FFC0H

FFC2H

FFC4H

FFE0H

FFE1H

FFE2H

FFE4H

FFE5H

FFE6H

FFE8H

FFE9H

FFEAH

FFF0H

FFFBH

Capture/compare control register 00

16-bit timer output control register 00

Low-voltage detection register

CRC00

R/W

√

−

√

−

√

−

√

00H

TOC00

LVIM

R/W

00H

Low-voltage detection level selection register

Flash protect command register

Flash status register

LVIS

R/W

00H

PFCMD

PFS

W

Undefined

00H

R/W

Flash programming mode control register

Interrupt request flag register 0L

Interrupt request flag register 0H

Interrupt request flag register 1L

Interrupt mask flag register 0L

FLPMC

IF0

R/W

0XH^{Note 1}

IF0L R/W

IF0H R/W

R/W

00H

IF1L

−

√

00H

MK0 MK0L R/W

MK0H R/W

FFH

Interrupt mask flag register 0H

FFH

Interrupt mask flag register 1L

MK1L

R/W

−

√

FFH

Priority specification flag register 0L

Priority specification flag register 0H

Priority specification flag register 1L

Internal memory size switching register^{Note 2}

Processor clock control register

PR0 PR0L R/W

PR0H R/W

FFH

PR1L

IMS

R/W

−

FFH

CFH

00H

PCC

Notes 1. Differs depending on the operation mode.

• User mode: 08H

• On-board mode: 0CH

2. The default value of IMS is fixed (IMS = CFH) in all products in the 78K0/KB1+ regardless of the internal

memory capacity. Therefore, set the following value to each product. In addition, set the following values

to the internal memory size switching register (IMS) when using the 78K0/KB1+ to evaluate the program

of a mask ROM version of the 78K0/KB1.

Flash Memory Version

(78K0/KB1+)

Target Mask ROM Version

(78K0/KB1)

Internal Memory Size

Switching Register (IMS)

µPD78F0101H

µPD78F0102H

µPD78F0103H

µPD780101

µPD780102

µPD780103

42H

04H

06H

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3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each

byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is

executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by

the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.

In other words, relative addressing consists of relative branching from the start address of the following

instruction to the −128 to +127 range.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

PC indicates the start address

of the instruction after the BR instruction.

...

PC

+

8

7

6

S

α

jdisp8

15

0

PC

When S = 0, all bits of

When S = 1, all bits of

α

are 0.

are 1.

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3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.

CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11

instruction is branched to the 0800H to 0FFFH area.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

7

0

CALL or BR

Low Addr.

High Addr.

15

8 7

0

PC

In the case of CALLF !addr11 instruction

7

6

4

3

0

fa^10–8

CALLF

fa^7–0

15

11 10

1

8 7

0

PC

0

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the

immediate data of an operation code are transferred to the program counter (PC) and branched.

This function is carried out when the CALLT [addr5] instruction is executed.

This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to

the entire memory space.

[Illustration]

7

6

1

5

1

0

1

Operation code

1

ta4–0

15

8

0

7

0

6

1

5

1

0

Effective address

0

7

Memory (Table)

Low Addr.

0

High Addr.

Effective address+1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.4.1 Implied addressing

[Function]

The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically

(implicitly) addressed.

Of the 78K0/KB1+ instruction words, the following instructions employ implied addressing.

Instruction

MULU

Register to Be Specified by Implied Addressing

A register for multiplicand and AX register for product storage

AX register for dividend and quotient storage

DIVUW

ADJBA/ADJBS

ROR4/ROL4

A register for storage of numeric values that become decimal correction targets

A register for storage of digit data that undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format is

necessary.

[Description example]

In the case of MULU X

With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,

the A and AX registers are specified by implied addressing.

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Register addressing

[Function]

The general-purpose register to be specified is accessed as an operand with the register bank select flags

(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier

Description

X, A, C, B, E, D, L, H

AX, BC, DE, HL

r

rp

‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; when selecting C register as r

Operation code

0

1

0

1

0

Register specify code

INCW DE; when selecting DE register pair as rp

Operation code

1

0

1

0

Register specify code

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3.4.3 Direct addressing

[Function]

The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an

operand address.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OP code

00H

FEH

[Illustration]

7

0

OP code

addr16 (lower)

addr16 (upper)

Memory

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3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers

(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.

Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter

are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to

1FH, bit 8 is set to 1. Refer to the [Illustration].

[Operand format]

Identifier

saddr

Description

Immediate data that indicate label or FE20H to FF1FH

Immediate data that indicate label or FE20H to FF1FH (even address only)

saddrp

[Description example]

MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)

Operation code

1

0

1

0

1

0

1

0

OP code

30H (saddr-offset)

[Illustration]

7

0

OP code

saddr-offset

Short direct memory

15

1

8 7

0

Effective address

1

α

When 8-bit immediate data is 20H to FFH, α = 0

When 8-bit immediate data is 00H to 1FH, α = 1

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3.4.5 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

sfrp

16-bit manipulatable special function register name (even address

only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code

1

0

1

0

1

0

1

0

1

0

OP code

20H (sfr-offset)

[Illustration]

7

0

OP code

sfr-offset

SFR

15

1

8 7

0

Effective address

1

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3.4.6 Register indirect addressing

[Function]

Register pair contents specified by a register pair specify code in an instruction word and by a register bank

select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be

carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

Operation code

1

0

1

0

1

[Illustration]

16

8

7

0

DE

D

E

The memory address

specified with the

register pair DE

Memory

The contents of the memory

addressed are transferred.

7

0

A

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3.4.7 Based addressing

[Function]

8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in

the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address

the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from

the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL + byte]

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

Operation code

1

0

1

0

1

0

1

0

1

0

[Illustration]

16

8

7

0

HL

H

L

+10

Memory

The contents of the memory

addressed are transferred.

7

0

A

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3.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to the contents of the base register, that

is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the

sum is used to address the memory. Addition is performed by expanding the B or C register contents as a

positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the

memory spaces.

[Operand format]

Identifier

Description

−

[HL + B], [HL + C]

[Description example]

In the case of MOV A, [HL + B] (selecting B register)

Operation code

1

0

1

0

1

0

1

[Illustration]

16

8

7

0

HL

H

L

+

7

0

B

Memory

The contents of the memory

addressed are transferred.

7

0

A

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3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call and return

instructions are executed or the register is saved/reset upon generation of an interrupt request.

With stack addressing, only the internal high-speed RAM area can be accessed.

[Description example]

In the case of PUSH DE (saving DE register)

Operation code

1

0

1

0

1

0

1

[Illustration]

7

Memory

0

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

D

E

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

There are two types of pin I/O buffer power supplies: AV^REFand VDD. The relationship between these power

supplies and the pins is shown below.

Table 4-1. Pin I/O Buffer Power Supplies

Power Supply

AVREF

Corresponding Pins

P20 to P23

Pins other than P20 to P23

VDD

78K0/KB1+ products are provided with the ports shown in Figure 4-1, which enable variety of control operations.

The functions of each port are shown in Table 4-2.

In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the

alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

P00

P20

Port 2

Port 3

Port 0

P03

P10

P23

P30

P33

Port 1

Port 12

Port 13

P120

P130

P17

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Table 4-2. Port Functions

Pin Name

I/O

Function

After Reset Alternate Function

P00

P01

P02

P03

I/O

Port 0.

Input

TI000

4-bit I/O port.

TI010/TO00

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

−

P10

P11

P12

P13

P14

P15

P16

P17

Port 1.

Input

SCK10/TxD0^Note

SI10/RxD0^Note

SO10

8-bit I/O port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

TxD6

RxD6

TOH0

TOH1/INTP5

TI50/TO50/

FLMD1

P20 to P23

P30 to P33

Input

I/O

Port 2.

Input

ANI0 to ANI3

4-bit input-only port.

Port 3.

INTP1 to INTP4

4-bit I/O port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P120

P130

I/O

Port 12.

Input

INTP0

1-bit I/O port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

Output

Port 13.

Output

−

1-bit output-only port.

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

4.2 Port Configuration

A port includes the following hardware.

Table 4-3. Port Configuration

Item

Control registers

Configuration

Port mode register (PM0, PM1, PM3, PM12)

Port register (P0 to P3, P12, P13)

Pull-up resistor option register (PU0, PU1, PU3, PU12)

Port

Total: 22 (CMOS I/O: 17, CMOS input: 4, CMOS output: 1)

Total: 17 (software control only)

Pull-up resistors

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4.2.1 Port 0

Port 0 is a 4-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units

using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up

resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).

This port can also be used for timer I/O.

RESET input sets port 0 to input mode.

Figures 4-2 to 4-4 show block diagrams of port 0.

Figure 4-2. Block Diagram of P00

V

DD

WR^PU

PU0

PU00

P-ch

Alternate function

RD

WR^PORT

Output latch

(P00)

P00/TI000

WRPM

PM0

PM00

PU0:

PM0:

RD:

Pull-up resistor option register 0

Port mode register 0

Read signal

WR××: Write signal

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Figure 4-3. Block Diagram of P01

VDD

WR^PU

PU0

PU01

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P01)

P01/TI010/TO00

WRPM

PM0

PM01

Alternate

function

PU0:

PM0:

RD:

Pull-up resistor option register 0

Port mode register 0

Read signal

WR××: Write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-4. Block Diagram of P02 and P03

V

DD

WRPU

PU0

PU02, PU03

P-ch

RD

WR^PORT

Output latch

(P02, P03)

P02, P03

WRPM

PM0

PM02, PM03

PU0:

PM0:

RD:

Pull-up resistor option register 0

Port mode register 0

Read signal

WR××: Write signal

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4.2.2 Port 1

Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units

using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up

resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).

This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O, and

flash memory programming mode setting.

RESET input sets port 1 to input mode.

Figures 4-5 to 4-9 show block diagrams of port 1.

Caution To use P10/SCK10 (/TxD0^Note), P11/SI10 (/RxD0^Note), and P12/SO10 as general-purpose ports, set

serial operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the

default status (00H).

<R>

Figure 4-5. Block Diagram of P10

VDD

WR^PU

PU1

PU10

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P10)

P10/SCK10 (/TxD0^Note

)

WRPM

PM1

PM10

Alternate

function

Note Available only in the µPD78F0102H and 78F0103H.

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

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Figure 4-6. Block Diagram of P11 and P14

VDD

WR^PU

PU1

PU11, PU14

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P11, P14)

P11/SI10 (/RxD0^Note),

P14/RxD6

WRPM

PM1

PM11, PM14

Note Available only in the µPD78F0102H and 78F0103H.

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

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Figure 4-7. Block Diagram of P12 and P15

VDD

WR^PU

PU1

PU12, PU15

P-ch

RD

WR^PORT

Output latch

(P12, P15)

P12/SO10,

P15/TOH0

WRPM

PM1

PM12, PM15

Alternate

function

PU1:

Pull-up resistor option register 1

Port mode register 1

Read signal

PM1:

RD:

WR××: Write signal

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Figure 4-8. Block Diagram of P13

V

DD

WR^PU

PU1

PU13

P-ch

RD

WR^PORT

Output latch

(P13)

P13/TxD6

WRPM

PM1

PM13

Alternate

function

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

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Figure 4-9. Block Diagram of P16 and P17

V

DD

WR^PU

PU1

PU16, PU17

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P16, P17)

P16/TOH1/INTP5,

P17/TI50/TO50/FLMD1

WRPM

PM1

PM16, PM17

Alternate

function

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

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4.2.3 Port 2

Port 2 is a 4-bit input-only port.

This port can also be used for A/D converter analog input.

Figure 4-10 shows a block diagram of port 2.

Figure 4-10. Block Diagram of P20 to P23

RD

A/D converter

P20/ANI0 to P23/ANI3

RD:

Read signal

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4.2.4 Port 3

Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units

using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up

resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).

This port can also be used for external interrupt request input.

RESET input sets port 3 to input mode.

Figure 4-11 shows a block diagram of port 3.

Figure 4-11. Block Diagram of P30 to P33

VDD

WR^PU

PU3

PU30 to PU33

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P30 to P33)

P30/INTP1 to

P33/INTP4

WRPM

PM3

PM30 to PM33

PU3:

PM3:

RD:

Pull-up resistor option register 3

Port mode register 3

Read signal

WR××: Write signal

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4.2.5 Port 12

Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units

using port mode register 12 (PM12). When the P120 pin is used as an input port, use of an on-chip pull-up resistor

can be specified by pull-up resistor option register 12 (PU12).

This port can also be used for external interrupt request input.

RESET input sets port 12 to input mode.

Figure 4-12 shows a block diagram of port 12.

Figure 4-12. Block Diagram of P120

V

DD

WR^PU

PU12

PU120

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P120)

P120/INTP0

WRPM

PM12

PM120

PU12: Pull-up resistor option register 12

PM12: Port mode register 12

RD:

Read signal

WR××: Write signal

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4.2.6 Port 13

Port 13 is a 1-bit output-only port.

Figure 4-13 shows a block diagram of port 13.

Figure 4-13. Block Diagram of P130

RD

WR^PORT

Output latch

(P130)

P130

RD:

Read signal

WR××: Write signal

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

4.3 Registers Controlling Port Function

Port functions are controlled by the following three types of registers.

•

Port mode registers (PM0, PM1, PM3, PM12)

Port registers (P0 to P3, P12, P13)

Pull-up resistor option registers (PU0, PU1, PU3, PU12)

(1) Port mode registers (PM0, PM1, PM3, and PM12)

These registers specify input or output mode for the port in 1-bit units.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table

4-4.

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Figure 4-14. Format of Port Mode Register

Symbol

PM0

7

1

6

1

5

1

4

1

3

2

1

0

Address After reset R/W

PM03

PM02

PM01

PM00

FF20H

FF21H

FF23H

FF2CH

FFH

R/W

PM1

PM3

PM17

PM16

PM15

PM14

PM13

PM33

1

PM12

PM32

1

PM11

PM31

1

PM10

PM30

1

PM12

PM120

PMmn

Pmn pin I/O mode selection

(m = 0, 1, 3, 12; n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

Table 4-4. Settings of Port Mode Register and Output Latch When Alternate Function Is Used

Pin Name

Alternate Function

Name

PM××

P××

I/O

P00

P01

TI000

TI010

TO00

SCK10

Input

1

0

1

0

1

0

1

0

1

0

1

×

0

×

1

×

0

1

×

0

×

0

×

Output

Input

P10

P11

Output

Input

TxD0^Note

SI10

RxD0^Note

Input

P12

P13

P14

P15

P16

SO10

Output

Input

TxD6

RxD6

TOH0

Output

Input

TOH1

INTP5

TI50

P17

Input

TO50

Output

Input

P30 to P33

P120

INTP1 to INTP4

INTP0

Input

Note TxD0 and RxD0 are available only in the µPD78F0102H and 78F0103H.

Remark ×: Don’t care

PM××: Port mode register

P××: Port output latch

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(2) Port registers (P0 to P3, P12, P13)

These registers write the data that is output from the chip when data is output from a port.

If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output

latch is read.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H (but P2 is undefined).

Figure 4-15. Format of Port Register

Symbol

P0

7

0

6

0

5

0

4

0

3

2

1

0

Address

FF00H

After reset

R/W

P03

P02

P01

P00

00H (output latch) R/W

7

6

5

4

3

2

1

0

P1

P2

P17

P16

P15

P14

P13

P12

P11

P10

FF01H

FF02H

FF03H

FF0CH

FF0DH

00H (output latch) R/W

7

0

6

0

5

0

4

0

3

2

1

0

P23

P22

P21

P20

Undefined

R

7

0

6

0

5

0

4

0

3

2

1

0

P3

P33

P32

P31

P30

00H (output latch) R/W

7

0

6

0

5

0

4

0

3

0

2

0

1

0

P12

P13

P120

7

0

6

0

5

0

4

0

3

0

2

0

1

0

P130

Pmn

m = 0 to 3, 12, 13; n = 0 to 7

Output data control (in output mode) Input data read (in input mode)

Input low level

Input high level

0

1

Output 0

Output 1

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(3) Pull-up resistor option registers (PU0, PU1, PU3, and PU12)

These registers specify whether the on-chip pull-up resistors of P00 to P03, P10 to P17, P30 to P33, or P120 is to

be used or not. An on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the

pins to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistor cannot be

connected for bits set to output mode and bits used as alternate-function output pins, regardless of the settings of

PU0, PU1, PU3 and PU12.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H.

Figure 4-16. Format of Pull-up Resistor Option Register

Symbol

PU0

7

6

5

4

3

PU03

3

2

PU02

2

1

PU01

1

0

PU00

0

Address After reset R/W

0

FF30H

FF31H

FF33H

FF3CH

00H

R/W

7

6

5

4

PU1

PU3

PU17

PU16

PU15

PU14

PU13

3

PU12

2

PU11

1

PU10

0

7

0

7

0

6

0

6

0

5

0

5

0

4

0

4

0

PU33

3

PU32

2

PU31

1

PU30

0

PU12

0

PU120

PUmn

Pmn pin on-chip pull-up resistor selection

(m = 0, 1, 3, 12; n = 0 to 7)

0

1

On-chip pull-up resistor not connected

On-chip pull-up resistor connected

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4.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the

port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the

output latch contents for pins specified as input are undefined, even for bits other than the

manipulated bit.

4.4.1 Writing to I/O port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The data of the output latch is cleared by reset.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does

not change.

Once data is written to the output latch, it is retained until data is written to the output latch again.

4.4.2 Reading from I/O port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

4.4.3 Operations on I/O port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output

latch contents are output from the pins.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The data of the output latch is cleared by reset.

(2) Input mode

The pin level is read and an operation is performed on its contents. The result of the operation is written to the

output latch, but since the output buffer is off, the pin status does not change.

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5.1 Functions of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.

The following two system clock oscillators are available.

•

High-speed system clock oscillator

The following two high-speed system clock oscillators are available.

• Crystal/ceramic oscillator: Oscillates a clock of fXP = 2 to 16 MHz

• External RC oscillator:

Oscillates a clock of fXP = 3 to 4 MHz

High-speed system clock oscillation can be selected using the option byte. Refer to CHAPTER 20 OPTION

BYTE for details.

The high-speed system clock oscillator can be stopped by executing the STOP instruction or setting the main

OSC control register (MOC).

•

Internal oscillator

The internal oscillator oscillates a clock of f^R= 240 kHz (TYP.). Oscillation can be stopped by setting the

internal oscillation mode register (RCM) when “Can be stopped by software” is set by the option byte and the

high-speed system clock is used as the CPU clock.

Remarks 1. f^XP: High-speed system clock oscillation frequency

2. f^R: Internal oscillation clock frequency

5.2 Configuration of Clock Generator

The clock generator includes the following hardware.

Table 5-1. Configuration of Clock Generator

Item

Configuration

Control registers

Processor clock control register (PCC)

Internal oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

Oscillator

High-speed system clock oscillator

Internal oscillator

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Figure 5-1. Block Diagram of Clock Generator

Internal bus

Oscillation

Main clock

Processor clock

control register

(PCC)

Main OSC

control register

(MOC)

stabilization time

mode register

select register

(MCM)

(OSTS)

OSTS2 OSTS1 OSTS0

3

PCC2 PCC1 PCC0

MCS MCM0

MSTOP

STOP

Control

signal

Oscillation stabilization

time counter

Controller

Oscillation

stabilization

time counter

status register

(OSTC)

C

P

U

CPU

clock

MOST MOST MOST MOST MOST

(f^CPU

)

11

13

14

15

16

High-speed

system clock

oscillator

X1[CL1]

X2[CL2]

Crystal/ceramic

oscillator^Note

3

f

X

fXP

Prescaler

Operation

clock switch

External RC

oscillator^Note

f

2

X

f

X

f

X

f

X

2²2³2⁴

f

CPU

Internal

oscillator

f

R

Prescaler

Clock to peripheral

hardware

Option byte (LSROSC)

1: Cannot be stopped

0. Can be stopped

Prescaler

8-bit timer H1,

watchdog timer

RSTOP

Internal oscillation mode

register (RCM)

Internal bus

Note Select one of these as the high-speed system clock oscillator by the option byte.

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5.3 Registers Controlling Clock Generator

The following six registers are used to control the clock generator.

•

Processor clock control register (PCC)

Internal oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

(1) Processor clock control register (PCC)

This register sets the division ratio of the CPU clock.

PCC can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-2. Format of Processor Clock Control Register (PCC)

Address: FFFBH After reset: 00H R/W

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

1

0

PCC2

PCC1

PCC0

PCC2

PCC1

PCC0

CPU clock selection (fCPU)

MCM0 = 0

MCM0 = 1

0

1

0

1

0

1

0

fX

fR

fXP

0

fX/2

fX/2²

fX/2³

fX/2⁴

fR/2^Note

fXP/2

1

Setting prohibited

fXP/2²

fXP/2³

fXP/2⁴

1

0

Other than above

Setting prohibited

Note Setting is prohibited for the (A1) grade products.

Caution Be sure to clear bits 3 to 7 to 0.

<R>

Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)

2. f^X: Main system clock oscillation frequency (high-speed system clock oscillation frequency or

internal oscillation clock frequency)

3. f^R: Internal oscillation clock frequency

4. f^XP: High-speed system clock oscillation frequency

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The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KB1+. Therefore, the

relationship between the CPU clock (f^CPU) and minimum instruction execution time is as shown in the Table 5-2.

Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

CPU Clock (fCPU)

Minimum Instruction Execution Time: 2/fCPU

High-Speed System Clock^{Note 1}Internal Oscillation Clock^{Note 1}

At 10 MHz Operation^{Note 2}At 16 MHz Operation^{Note 2}

0.2 µs 0.125 µs

At 240 kHz (TYP.) Operation

8.3 µs (TYP.)

fX

fX/2

fX/2²

fX/2³

fX/2⁴

0.4 µs

0.8 µs

1.6 µs

3.2 µs

0.25 µs

0.5 µs

1.0 µs

2.0 µs

16.6 µs (TYP.)^{Note 3}

Setting prohibited

Notes 1. The main clock mode register (MCM) is used to set the CPU clock (high-speed system clock/internal

oscillation clock) (see Figure 5-4).

2. When crystal/ceramic oscillation is used

<R>

3. Setting is prohibited for the (A1) grade products.

(2) Internal oscillation mode register (RCM)

This register sets the operation mode of the internal oscillator.

This register is valid when “Can be stopped by software” is set for the internal oscillator by the option byte, and

the high-speed system clock is input to the CPU clock. If “Cannot be stopped” is selected for the internal

oscillator by the option byte, settings for this register are invalid.

RCM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-3. Format of Internal Oscillation Mode Register (RCM)

Address: FFA0H After reset: 00H R/W

Symbol

RCM

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

RSTOP

Internal oscillator oscillating/stopped

0

1

Internal oscillator oscillating

Internal oscillator stopped

Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting

RSTOP.

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(3) Main clock mode register (MCM)

This register sets the CPU clock (high-speed system clock/internal oscillation clock).

MCM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-4. Format of Main Clock Mode Register (MCM)

Address: FFA1H After reset: 00H R/W^Note

Symbol

MCM

7

0

6

0

5

0

4

0

3

0

2

0

<1>

<0>

MCS

MCM0

MCS

CPU clock status

0

1

Operates with internal oscillation clock

Operates with high-speed system clock

MCM0

Selection of clock supplied to CPU

0

1

Internal oscillation clock

High-speed system clock

Note Bit 1 is read-only.

Caution When the internal oscillation clock is selected as the clock to be supplied to the

CPU, the divided clock of the internal oscillator output (f^X) is supplied to the

peripheral hardware (fX = 240 kHz (TYP.)).

Operation of the peripheral hardware with the internal oscillation clock cannot be

guaranteed. Therefore, when the internal oscillation clock is selected as the clock

supplied to the CPU, do not use peripheral hardware. In addition, stop the

peripheral hardware before switching the clock supplied to the CPU from the high-

speed system clock to the internal oscillation clock. Note, however, that the

following peripheral hardware can be used when the CPU operates on the internal

oscillation clock.

• Watchdog timer

• Clock monitor

• 8-bit timer H1 when f^R/2⁷is selected as the count clock

• Peripheral hardware with an external clock selected as the clock source

(Except when the external count clock of TM00 is selected (TI000 valid edge))

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(4) Main OSC control register (MOC)

This register selects the operation mode of the high-speed system clock.

This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the

internal oscillation clock. Therefore, this register is valid only when the CPU is operating with the internal

oscillation clock.

MOC can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-5. Format of Main OSC Control Register (MOC)

Address: FFA2H After reset: 00H R/W

Symbol

MOC

<7>

6

0

5

0

4

0

3

0

2

0

1

0

MSTOP

Control of high-speed system clock oscillator operation

0

1

High-speed system clock oscillator operating

High-speed system clock oscillator stopped

Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting

MSTOP.

(5) Oscillation stabilization time counter status register (OSTC)

This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal

oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be

checked.

OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.

When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,

MSTOP = 1 clear OSTC to 00H.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock

can be switched without reading the OSTC value.

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Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)

Address: FFA3H After reset: 00H

R

Symbol

OSTC

7

0

6

0

5

0

4

3

2

1

0

MOST11

MOST13

MOST14

MOST15

MOST16

MOST11

MOST13

MOST14

MOST15

MOST16

Oscillation stabilization time status

fXP = 10 MHz fXP = 16 MHz

1

0

1

0

1

0

1

0

1

2¹¹/fXP min. 204.8 µs min. 128 µs min.

2¹³/fXP min. 819.2 µs min. 512 µs min.

2¹⁴/fXP min. 1.64 ms min. 1.02 ms min.

2¹⁵/fXP min. 3.27 ms min. 2.04 ms min.

2¹⁶/fXP min. 6.55 ms min. 4.09 ms min.

Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and

remain 1.

2. If the STOP mode is entered and then released while the internal oscillation

clock is being used as the CPU clock, set the oscillation stabilization time as

follows.

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The oscillation stabilization time counter counts up to the oscillation

stabilization time set by OSTS. Note, therefore, that only the status up to the

oscillation stabilization time set by OSTS is set to OSTC after STOP mode is

released.

3. The wait time when STOP mode is released does not include the time after STOP

mode release until clock oscillation starts (“a” below) regardless of whether

STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remark fXP: High-speed system clock oscillation frequency

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(6) Oscillation stabilization time select register (OSTS)

This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP

mode is released.

The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected

as the CPU clock. After STOP mode is released with the internal oscillation clock selected as the CPU clock, the

oscillation stabilization time must be confirmed by OSTC.

OSTS can be set by an 8-bit memory manipulation instruction.

RESET input sets OSTS to 05H.

Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFA4H After reset: 05H R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

1

0

OSTS2

OSTS1

OSTS0

OSTS2

OSTS1

OSTS0

Oscillation stabilization time selection

fXP = 10 MHz fXP = 16 MHz

204.8 µs 128 µs

0

1

0

1

0

1

0

1

2¹¹/fXP

1

2¹³/fXP

819.2 µs

1.64 ms

3.27 ms

6.55 ms

512 µs

1

2¹⁴/fXP

1.02 ms

2.04 ms

4.09 ms

0

2¹⁵/fXP

0

2¹⁶/fXP

Other than above

Setting prohibited

Cautions 1. To set the STOP mode when the high-speed system clock is used as the CPU

clock, set OSTS before executing a STOP instruction.

2. Execute the OSTS setting after confirming that the oscillation stabilization time

has elapsed as expected in OSTC.

3. If the STOP mode is entered and then released while the internal oscillation

clock is being used as the CPU clock, set the oscillation stabilization time as

follows.

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The oscillation stabilization time counter counts up to the oscillation

stabilization time set by OSTS. Note, therefore, that only the status up to the

oscillation stabilization time set by OSTS is set to OSTC after STOP mode is

released.

4. The wait time when STOP mode is released does not include the time after STOP

mode release until clock oscillation starts (“a” below) regardless of whether

STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remark f^XP: High-speed system clock oscillation frequency

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5.4 System Clock Oscillator

5.4.1 High-speed system clock oscillator

The following two high-speed system clock oscillators are available.

• Crystal/ceramic oscillator: Oscillates a clock of f^XP= 2 to 16 MHz

• External RC oscillator:

Oscillates a clock of f^XP= 3 to 4 MHz

High-speed system clock oscillation can be selected using the option byte. Refer to CHAPTER 20 OPTION BYTE

for details.

(1) Crystal/ceramic oscillator

The crystal/ceramic oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2

pins.

An external clock can be input to the crystal/ceramic oscillator. In this case, input the clock signal to the X1 pin

and input the inverse signal to the X2 pin.

Figure 5-8 shows the external circuit of the crystal/ceramic oscillator.

Figure 5-8. External Circuit of Crystal/Ceramic Oscillator

(a) Crystal, ceramic oscillation

(b) External clock

V

SS

X1

External

clock

X1

X2

Crystal resonator or

ceramic resonator

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in the Figure 5-8 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Figure 5-9 shows examples of incorrect resonator connection.

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Figure 5-9. Examples of Incorrect Resonator Connection

(a) Too long wiring

(b) Crossed signal line

PORT

X2

VSS

X1

X2

V

SS

X1

(c) Wiring near high alternating current

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

V

DD

Pmn

X2

V

SS

X1

X2

V

SS

X1

A

B

C

High current

(e) Signals are fetched

VSS

X1

X2

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(2) External RC oscillator

The external RC oscillator is oscillated by the resistor (R) and capacitor (C) connected across the CL1 and CL2

pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the

inverted signal to the CL2 pin.

Figure 5-10 shows the external circuit of the external RC oscillator.

Figure 5-10. External Circuit of External RC Oscillator

(a) RC oscillation

(b) External clock

External

clock

CL1

V

CL1

SS

C

R

CL2

Caution When using the external RC oscillator, wire as follows in the area enclosed by the broken lines

in Figure 5-10 to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

Figure 5-11 shows an example of incorrect connections for RC oscillation.

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Figure 5-11. Example of Incorrect Connection for RC Oscillation

(a) Too long wiring

(b) Crossed signal line

PORT

CL2

VSS

CL1

CL2

V

SS

CL1

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of oscillator

(potential at points A and B fluctuates)

VDD

PORT

CL2

VSS

CL1

CL2

V

SS

CL1

High current

A

B

High current

(e) Signal is fetched

VSS

CL1

CL2

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5.4.2 Internal oscillator

An internal oscillator is incorporated in the 78K0/KB1+.

“Can be stopped by software” or “Cannot be stopped” can be selected by the option byte. The internal oscillator

always oscillates the internal oscillation clock after RESET release (240 kHz (TYP.)).

5.4.3 Prescaler

The prescaler generates various clocks by dividing the high-speed system clock oscillator output when the high-

speed system clock is selected as the clock to be supplied to the CPU.

Caution When the internal oscillation clock is selected as the clock supplied to the CPU, the prescaler

generates various clocks by dividing the internal oscillator output (f^X= 240 kHz (TYP.)).

5.5 Clock Generator Operation

The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby

mode.

•

High-speed system clock f^XP

Internal oscillation clock f^R

CPU clock f^CPU

Clock to peripheral hardware

The CPU starts operation when the internal oscillator starts outputting after reset release in the 78K0/KB1+, thus

enabling the following.

(1) Enhancement of security function

When the high-speed system clock is set as the CPU clock by the default setting, the device cannot operate if the

high-speed system clock is damaged or badly connected and therefore does not operate after reset is released.

However, the start clock of the CPU is the internal oscillation clock, so the device can be started by the internal

oscillation clock after reset release by the clock monitor (detection of high-speed system clock stop).

Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a

reset source by software or performing safety processing when there is a malfunction.

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(2) Improvement of performance

Because the CPU can be started without waiting for the high-speed system clock oscillation stabilization time, the

total performance can be improved.

A timing diagram of the CPU default start using the internal oscillator is shown in Figure 5-12.

Figure 5-12. Timing Diagram of CPU Default Start Using Internal Oscillator

High-speed

system clock (f^XP

)

Internal oscillation

clock (f

R

)

RESET

Switched by software

CPU clock

Internal oscillation clock

High-speed system clock

Operation

stopped: 17/f

R

High-speed system clock oscillation stabilization time:

Note

2¹¹/fXP to 2¹⁶/fXP

Note Check using the oscillation stabilization time counter status register (OSTC). Waiting for the oscillation

stabilization time is not required when the external RC oscillation clock is selected as the high-speed

system clock by the option byte. Therefore, the CPU clock can be switched without reading the OSTC

value.

(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the internal

oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the

internal oscillation clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks).

During the RESET period, oscillation of the high-speed system clock and the internal oscillation clock is

stopped.

(b) After RESET release, the CPU clock can be switched from the internal oscillation clock to the high-speed

system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed system clock

oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time using the

oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The CPU clock

status can be checked using bit 1 (MCS) of MCM.

(c) The internal oscillator can be set to stopped/oscillating using the internal oscillation mode register (RCM)

when “Can be stopped by software” is selected for the internal oscillator by the option byte, if the high-speed

system clock is used as the CPU clock. Make sure that MCS is 1 at this time.

(d) When the internal oscillation clock is used as the CPU clock, the high-speed system clock can be set to

stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.

(e) Select the high-speed system clock oscillation stabilization time (2¹¹/fXP, 2¹³/fXP, 2¹⁴/fXP, 2¹⁵/fXP, 2¹⁶/fXP) using

the oscillation stabilization time select register (OSTS) when releasing STOP mode while the high-speed

system clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is

released and the internal oscillation clock is being used as the CPU clock, check the high-speed system

clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC).

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A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation

clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown

in Tables 5-3 and 5-4, respectively.

Figure 5-13. Status Transition Diagram (1/2)

(1) When “Internal oscillator can be stopped by software” is selected by option byte

HALT^{Note 4}

HALT instruction

Interrupt

HALT

instruction

Interrupt

HALT

instruction

HALT

Interrupt

instruction

Status 4

CPU clock: f^XP

XP: Oscillating

: Oscillation stopped

MSTOP = 1^{Note 3}

Status 3

CPU clock: f^XP

XP: Oscillating

Status 1

CPU clock: f

XP: Oscillation stopped

RSTOP = 0

MCM0 = 0

Status 2

R

CPU clock: f

XP: Oscillating

: Oscillating

R

f

R

RSTOP = 1^{Note 1}

MCM0 = 1^{Note 2}

MSTOP = 0

STOP

R

: Oscillating

f : Oscillating

R

Interrupt

instruction

STOP

Interrupt

STOP

instruction

Interrupt

STOP

instruction

STOP^{Note 4}

Reset release

Reset^{Note 5}

Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register

(MCM) is 1.

2. Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed

system clock oscillation stabilization time status using the oscillation stabilization time counter status

register (OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

3. When shifting from status 2 to status 1, make sure that MCS is 0.

4. When “Internal oscillator can be stopped by software” is selected by the option byte, the watchdog

timer stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog

timer. However, oscillation of the internal oscillator does not stop even in the HALT and STOP

modes if RSTOP = 0.

5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)

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Figure 5-13. Status Transition Diagram (2/2)

(2) When “Internal oscillator cannot be stopped” is selected by option byte

HALT

instruction

Interrupt

HALT instruction

Interrupt

HALT

instruction

Status 3

CPU clock: f^XP

XP: Oscillating

: Oscillating

Status 1

CPU clock: f

fXP: Oscillation stopped

Status 2

CPU clock: f

XP: Oscillating

: Oscillating

MCM0 = 0

MSTOP = 1^{Note 2}

R

f

MCM0 = 1^{Note 1}

MSTOP = 0

R

f : Oscillating

R

STOP

instruction

Interrupt

STOP

instruction

Interrupt

instruction

STOP^{Note 3}

Reset release

Reset^{Note 4}

Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed

system clock oscillation stabilization time status using the oscillation stabilization time counter status

register (OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

2. When shifting from status 2 to status 1, make sure that MCS is 0.

3. The watchdog timer operates using the internal oscillation clock even in STOP mode if “Internal

oscillator cannot be stopped” is selected by the option byte. Internal oscillation clock division can be

selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1

interrupt request before watchdog timer overflow. If this processing is not performed, an internal

reset signal is generated at watchdog timer overflow after STOP instruction execution.

4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)

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Table 5-3. Relationship Between Operation Clocks in Each Operation Status

Status

High-Speed System Clock

Oscillator

Internal Oscillator

CPU Clock

After

Prescaler Clock Supplied to

Peripherals

Release

Note 1

Note 2

MCM0 = 0

MCM0 = 1

Operation

Mode

MSTOP = 0 MSTOP = 1

Stopped

RSTOP = 0 RSTOP = 1

Reset

Stopped

Internal

Stopped

oscillation

STOP

HALT

Oscillating

Stopped

Note 3

Note 4

Oscillating

Stopped

Internal

High-speed

oscillation

system clock

Notes 1. When “Cannot be stopped” is selected for the internal oscillator by the option byte.

2. When “Can be stopped by software” is selected for the internal oscillator by the option byte.

3. Operates using the CPU clock at STOP instruction execution.

4. Operates using the CPU clock at HALT instruction execution.

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal oscillator

by the option byte.

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

RSTOP: Bit 0 of the internal oscillation mode register (RCM)

MCM0: Bit 0 of the main clock mode register (MCM)

Table 5-4. Oscillation Control Flags and Clock Oscillation Status

High-Speed System Clock Oscillator

Stopped

Internal Oscillator

Oscillating

MSTOP = 1 RSTOP = 0

RSTOP = 1

Setting prohibited

Oscillating

MSTOP = 0 RSTOP = 0

RSTOP = 1

Oscillating

Stopped

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal

oscillator by the option byte.

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

RSTOP: Bit 0 of the internal oscillation mode register (RCM)

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5.6 Time Required to Switch Between Internal Oscillation Clock and High-Speed System Clock

Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the internal oscillation clock and

high-speed system clock.

In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions

are executed using the pre-switch over clock after switching MCM0 (see Table 5-5).

Bit 1 (MCS) of MCM is used to judge that operation is performed using either the internal oscillation clock or high-

speed system clock.

To stop the original clock after changing the clock, wait for the number of clocks shown in Table 5-5.

Table 5-5. Time Required to Switch Between Internal Oscillation Clock and High-Speed System Clock

PCC

Time Required for Switching

PCC2

PCC1

PCC0

High-Speed System Clock →

Internal Oscillation Clock

fXP/fR + 1 clock

fXP/2fR + 1 clock ^Note

Internal Oscillation Clock →

High-Speed System Clock

0

1

2 clocks

2 clocks ^Note

<R>

Note Setting is prohibited for the (A1) grade products.

Caution To calculate the maximum time, set f^R= 120 kHz.

Remarks 1. PCC: Processor clock control register

2. f^XP: High-speed system clock oscillation frequency

3. f^R: Internal oscillation clock frequency

4. The maximum time is the number of clocks of the CPU clock before switching.

5.7 Time Required for CPU Clock Switchover

The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC).

The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on

the pre-switchover clock for several instructions (see Table 5-6).

Table 5-6. Maximum Time Required for CPU Clock Switchover

Set Value Before

Switchover

Set Value After Switchover

PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16 clocks

8 clocks

16 clocks

8 clocks

4 clocks

16 clocks

8 clocks

4 clocks

2 clocks

8 clocks

4 clocks

2 clocks

1 clock

4 clocks

2 clocks

1 clock

2 clocks

1 clock

Caution Setting the following values is prohibited when the CPU operates on the internal oscillation clock.

• PCC2, PCC1, PCC0 = 0, 1, 0

• PCC2, PCC1, PCC0 = 0, 1, 1

• PCC2, PCC1, PCC0 = 1, 0, 0

Remark The maximum time is the number of clocks of the CPU clock before switching.

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5.8 Clock Switching Flowchart and Register Setting

5.8.1 Switching from internal oscillation clock to high-speed system clock

Figure 5-14. Switching from Internal Oscillation Clock to High-Speed System Clock (Flowchart)

After reset release

PCC = 00H

RCM = 00H

MCM = 00H

MOC = 00H

OSTC = 00H

OSTS = 05H^Note

; fCPU = f

R

; Internal oscillation

Register initial

; Internal oscillation clock operation

; High-speed system clock oscillation

; Oscillation stabilization time status register

; Oscillation stabilization time f^XP/2¹⁶

value after reset

Each processing

OSTC check^Note

; High-speed system clock oscillation

stabilization time status check

High-speed system

clock oscillation stabilization

time has not elapsed

Internal oscillation

clock operation

High-speed system clock oscillation stabilization time

has elapsed

PCC setting

Internal oscillation

clock operation

(dividing set PCC)

MCM.0 ← 1

MCM.1 (MCS) is changed from 0 to 1

High-speed system clock operation

High-speed system

clock operation

Note Check the oscillation stabilization wait time of the high-speed system clock oscillator after reset release

using the OSTC register and then switch to the high-speed system clock operation after the oscillation

stabilization wait time has elapsed. Waiting for the oscillation stabilization time is not required when the

external RC oscillation clock is selected as the high-speed system clock by the option byte. Therefore, the

CPU clock can be switched without reading the OSTC value. The OSTS register setting is valid only after

STOP mode is released by interrupt during high-speed system clock operation.

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5.8.2 Switching from high-speed system clock to internal oscillation clock

Figure 5-15. Switching from High-Speed System Clock to Internal Oscillation Clock (Flowchart)

Register setting

in high-speed system

clock operation

; High-speed system clock operation

MCM = 03H

Yes: RSTOP = 1

RCM.0^Note

(RSTOP) = 1?

High-speed system

clock operation

; Internal oscillator oscillating?

No: RSTOP = 0

RSTOP = 0

MCM.0 ← 0

; Internal oscillator oscillating

MCM.1 (MCS) is changed from 1 to 0

Internal oscillation

clock operation

Internal oscillation clock operation

Note Required only when “can be stopped by software” is selected for the internal oscillator by the option byte.

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5.8.3 Register settings

The table below shows the statuses of the setting flags and status flags when each mode is set.

Table 5-7. Clock and Register Settings

fCPU

Mode

Setting Flag

MOC Register

MSTOP

Status Flag

MCM Register

RCM Register

RSTOP^{Note 1}

0

MCM Register

MCM0

1

MCS

1

High-speed system

clock^{Note 2}

Internal oscillation

clock oscillating

0

Internal oscillation

clock stopped

1

0

1

0

1

0

Internal oscillation

clock

High-speed system

clock oscillating

High-speed system

clock stopped

Notes 1. This is valid only when “can be stopped by software” is selected for the internal oscillator by the option

byte.

2. Do not set MSTOP to 1 during high-speed system clock operation (oscillation of high-speed system

clock is not stopped even when MSTOP = 1).

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6.1 Functions of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 has the following functions.

• Interval timer

• PPG output

• Pulse width measurement

• External event counter

• Square-wave output

• One-shot pulse output

(1) Interval timer

16-bit timer/event counter 00 generates an interrupt request at the preset time interval.

(2) PPG output

16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set

freely.

(3) Pulse width measurement

16-bit timer/event counter 00 can measure the pulse width of an externally input signal.

(4) External event counter

16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.

(5) Square-wave output

16-bit timer/event counter 00 can output a square wave with any selected frequency.

(6) One-shot pulse output

16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely.

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6.2 Configuration of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 includes the following hardware.

Table 6-1. Configuration of 16-Bit Timer/Event Counter 00

Item

Timer counter

Configuration

16 bits (TM00)

Register

16-bit timer capture/compare register: 16 bits (CR000, CR010)

Timer input

Timer output

Control registers

TI000, TI010

TO00, output controller

16-bit timer mode control register 00 (TMC00)

Capture/compare control register 00 (CRC00)

16-bit timer output control register 00 (TOC00)

Prescaler mode register 00 (PRM00)

Port mode register 0 (PM0)

Port register 0 (P0)

Figure 6-1 shows the block diagram.

Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00

Internal bus

Capture/compare control

register 00 (CRC00)

CRC002CRC001 CRC000

To CR010

INTTM000

16-bit timer capture/compare

register 000 (CR000)

Noise

elimi-

nator

TI010/TO00/P01

Match

f

X

f

X

/2²

/2⁸

16-bit timer counter 00

(TM00)

fX

Clear

Output

TO00/TI010/

P01

controller

Match

Noise

elimi-

nator

2

fX

Output latch

(P01)

PM01

Noise

elimi-

nator

16-bit timer capture/compare

register 010 (CR010)

TI000/P00

INTTM010

CRC002

PRM001

TMC003 TMC002 TMC001OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

PRM000

16-bit timer output

control register 00

(TOC00)

16-bit timer mode

control register 00

(TMC00)

Prescaler mode

register 00 (PRM00)

Internal bus

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(1) 16-bit timer counter 00 (TM00)

TM00 is a 16-bit read-only register that counts count pulses.

The counter is incremented in synchronization with the rising edge of the input clock.

Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)

Address: FF10H, FF11H

Symbol

After reset: 0000H

FF11H

R

FF10H

TM00

The count value is reset to 0000H in the following cases.

<1> At RESET input

<2> If TMC003 and TMC002 are cleared

<3> If the valid edge of the TI000 pin is input in the mode in which clear & start occurs when inputting the valid

edge of the TI000 pin

<4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000

<5> If OSPT00 is set to 1 in one-shot pulse output mode

(2) 16-bit timer capture/compare register 000 (CR000)

CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is

used as a capture register or as a compare register is set by bit 0 (CR000) of capture/compare control register 00

(CRC00).

CR000 can be set by a 16-bit memory manipulation instruction.

RESET input clears CR000 to 0000H.

Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)

Address: FF12H, FF13H

Symbol

After reset: 0000H

FF13H

R/W

FF12H

CR000

•

When CR000 is used as a compare register

The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an

interrupt request (INTTM000) is generated if they match. The set value is held until CR000 is rewritten.

When CR000 is used as a capture register

It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or

TI010 pin valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2).

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Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)

CR000 Capture Trigger

TI000 Pin Valid Edge

ES001

ES000

Falling edge

Rising edge

0

1

0

1

Rising edge

Falling edge

No capture operation

Both rising and falling edges

(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)

CR000 Capture Trigger

TI010 Pin Valid Edge

ES101

ES100

Falling edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.

2. ES001, ES000:

Bits 5 and 4 of prescaler mode register 00 (PRM00)

Bits 7 and 6 of prescaler mode register 00 (PRM00)

ES101, ES100:

CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)

Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match

of TM00 and CR000.

2. If CR000 is set to 0000H in the free-running mode and in the clear mode using the valid edge

of the TI000 pin, an interrupt request (INTTM000) is generated when the value of CR000

changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover, INTTM000 is

generated after a match of TM00 and CR000 is detected, a valid edge of the TI010 pin is

detected, and the timer is cleared by a one-shot trigger.

3. When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00).

When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.

4. When CR000 is used as a capture register, read data is undefined if the register read time

and capture trigger input conflict (the capture data itself is the correct value).

If timer count stop and capture trigger input conflict, the captured data is undefined.

5. Do not rewrite CR000 during TM00 operation.

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(3) 16-bit timer capture/compare register 010 (CR010)

CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is

used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00

(CRC00).

CR010 can be set by a 16-bit memory manipulation instruction.

RESET input clears CR010 to 0000H.

Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)

Address: FF14H, FF15H

Symbol

After reset: 0000H

FF15H

R/W

FF14H

CR010

•

When CR010 is used as a compare register

The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and

an interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten.

When CR010 is used as a capture register

It is possible to select the valid edge of the TI000 pin as the capture trigger. The valid edge of the TI000 pin is

set by prescaler mode register 00 (PRM00) (see Table 6-3).

Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)

CR010 Capture Trigger

TI000 Pin Valid Edge

ES001

ES000

Falling edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited.

2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)

CRC002: Bit 2 of capture/compare control register 00 (CRC00)

Cautions 1. If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when the value of

CR010 changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover,

INTTM010 is generated after a match of TM00 and CR010 is detected, a valid edge of the

TI000 pin is detected, and the timer is cleared by a one-shot trigger.

2. When CR010 is used as a capture register, read data is undefined if the register read time

and capture trigger input conflict (the capture data itself is the correct value).

If count stop input and capture trigger input conflict, the captured data is undefined.

3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.

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6.3 Registers Controlling 16-Bit Timer/Event Counter 00

The following six registers are used to control 16-bit timer/event counter 00.

• 16-bit timer mode control register 00 (TMC00)

• Capture/compare control register 00 (CRC00)

• 16-bit timer output control register 00 (TOC00)

• Prescaler mode register 00 (PRM00)

• Port mode register 0 (PM0)

• Port register 0 (P0)

(1) 16-bit timer mode control register 00 (TMC00)

This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output

timing, and detects an overflow.

TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC00 to 00H.

Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to

values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and TMC003 to 0, 0 to

stop operation.

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Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)

Address FFBAH

After reset: 00H

R/W

3

Symbol

TMC00

7

0

6

0

5

0

4

0

2

1

<0>

TMC003 TMC002 TMC001 OVF00

TMC003 TMC002 TMC001

Operating mode and clear

mode selection

TO00 inversion timing

selection

Interrupt request

generation

0

1

0

1

0

Operation stop

No change

Not generated

(TM00 cleared to 0)

Free-running mode

Match between TM00 and

CR000 or match between

TM00 and CR010

<When used as compare

register>

Generated on match

between TM00 and CR000,

or match between TM00

and CR010

0

1

Match between TM00 and

CR000, match between

TM00 and CR010 or TI000

pin valid edge

<When used as capture

register>

1

0

1

0

1

0

Clear & start occurs on TI000

pin valid edge

−

Generated by inputting

CR000 capture trigger

Clear & start occurs on match Match between TM00 and

between TM00 and CR000

CR000 or match between

TM00 and CR010

1

Match between TM00 and

CR000, match between

TM00 and CR010 or TI000

pin valid edge

OVF00

16-bit timer counter 00 (TM00) overflow detection

0

1

Overflow not detected

Overflow detected

Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.

2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).

3. If any of the following modes: the mode in which clear & start occurs on match between

TM00 and CR000, the mode in which clear & start occurs at the valid edge of the TI000 pin or

free-running mode is selected, when the set value of CR000 is FFFFH and the TM00 value

changes from FFFFH to 0000H, the OVF00 flag is set to 1.

Remark TO00: 16-bit timer/event counter 00 output pin

TI000: 16-bit timer/event counter 00 input pin

TM00: 16-bit timer counter 00

CR000: 16-bit timer capture/compare register 000

CR010: 16-bit timer capture/compare register 010

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(2) Capture/compare control register 00 (CRC00)

This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010).

CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CRC00 to 00H.

Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)

Address: FFBCH After reset: 00H R/W

Symbol

CRC00

7

0

6

0

5

0

4

0

3

0

2

1

0

CRC002

CRC001

CRC000

CRC002

CR010 operating mode selection

0

1

Operates as compare register

Operates as capture register

CRC001

CR000 capture trigger selection

0

1

Captures on valid edge of TI010 pin

Captures on valid edge of TI000 pin by reverse phase^Note

CRC000

CR000 operating mode selection

Operates as compare register

0

1

Operates as capture register

Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of

the TI000 pin.

Cautions 1. Timer operation must be stopped before setting CRC00.

2. When the mode in which clear & start occurs on a match between TM00 and CR000 is

selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified

as a capture register.

3. To ensure that the capture operation is performed properly, the capture trigger requires a

pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00).

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(3) 16-bit timer output control register 00 (TOC00)

This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the timer

output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output,

enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.

TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TOC00 to 00H.

Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)

Address: FFBDH After reset: 00H R/W

Symbol

TOC00

7

0

<6>

<5>

4

<3>

<2>

1

<0>

OSPT00

OSPE00

TOC004

LVS00

LVR00

TOC001

TOE00

OSPT00

One-shot pulse output trigger control via software

0

1

No one-shot pulse output trigger

One-shot pulse output trigger

OSPE00

One-shot pulse output operation control

0

1

Successive pulse output mode

One-shot pulse output mode^Note

TOC004

Timer output F/F control using match of CR010 and TM00

0

1

Disables inversion operation

Enables inversion operation

LVS00

LVR00

Timer output F/F status setting

0

1

0

1

0

1

No change

Timer output F/F reset (0)

Timer output F/F set (1)

Setting prohibited

TOC001

Timer output F/F control using match of CR000 and TM00

0

1

Disables inversion operation

Enables inversion operation

TOE00

Timer output control

0

1

Disables output (output fixed to level 0)

Enables output

Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match

between the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow

does not occur.

Cautions 1. Timer operation must be stopped before setting other than TOC004.

2. LVS00 and LVR00 are 0 when they are read.

3. OSPT00 is automatically cleared after data is set, so 0 is read.

4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.

5. A write interval of two cycles or more of the count clock selected by prescaler mode register

00 (PRM00) is required to write to OSPT00 successively.

6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously.

7. Do not make settings <1> and <2> below simultaneously. In addition, follow the setting

procedure shown below.

<1> Setting of TOC001, TOC004, TOE00, and OSPE00: Setting of timer output operation

<2> Setting of LVS00 and LVR00:

Setting of timer output F/F

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(4) Prescaler mode register 00 (PRM00)

This register is used to set the 16-bit timer counter 00 (TM00) count clock and the valid edges of the TI000 and

TI010 pin input.

PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PRM00 to 00H.

Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)

Address: FFBBH After reset: 00H R/W

Symbol

PRM00

7

6

5

4

3

0

2

0

1

0

ES101

ES100

ES001

ES000

PRM001

PRM000

ES101

ES100

TI010 pin valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES001

ES000

TI000 pin valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

PRM001

PRM000

Count clock selection^{Note 1}

0

1

0

1

0

1

fX (10 MHz)

fX/2²(2.5 MHz)

fX/2⁸(39.06 kHz)

TI000 pin valid edge^{Note 2}

Notes 1. Be sure to set the count clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Count clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Count clock ≤ 8.38 MHz

• V^DD= 2.7 to 3.3 V: Count clock ≤ 5 MHz

<R>

• VDD = 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)

2. The external clock requires a pulse two cycles longer than the internal clock (f^X).

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Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not

guaranteed. When an external clock is used and when the internal oscillation clock is

selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not

guaranteed, either, because the internal oscillation clock is supplied as the sampling clock to

eliminate noise.

2. Always set data to PRM00 after stopping the timer operation.

3. If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start

mode using the valid edge of the TI000 pin and the capture trigger.

4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is

immediately detected after the rising edge or both the rising and falling edges are set as the

valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00

(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when re-

enabling operation after the operation has been stopped, the rising edge is not detected if the

TI000 or TI010 pin is high level.

5. When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00).

When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. TI000, TI010: 16-bit timer/event counter 00 input pin

3. Figures in parentheses are for operation with f^X= 10 MHz.

(5) Port mode register 0 (PM0)

This register sets port 0 input/output in 1-bit units.

When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latch of P01 to 0.

Set PM01 to 1 when using the P01/TO00/TI010 pin as a timer input pin. The output latch of P01 at this time may

be 0 or 1.

PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM0 to FFH.

Figure 6-9. Format of Port Mode Register 0 (PM0)

Address: FF20H After reset: FFH R/W

Symbol

PM0

7

1

6

1

5

1

4

1

3

2

1

0

PM03 PM02 PM01 PM00

PM0n

P0n pin I/O mode selection (n = 0 to 3)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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6.4 Operation of 16-Bit Timer/Event Counter 00

6.4.1 Interval timer operation

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-10 allows operation as an interval timer.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-10 for the set value).

<2> Set any value to the CR000 register.

<3> Set the count clock by using the PRM000 register.

<4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).

Caution Do not rewrite CR000 during TM00 operation.

Remark For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register

000 (CR000) as the interval.

When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with

the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.

The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of

prescaler mode register 00 (PRM00).

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Figure 6-10. Control Register Settings for Interval Timer Operation

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0/1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

0

PRM001 PRM000

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the

description of the respective control registers for details.

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Figure 6-11. Interval Timer Configuration Diagram

16-bit timer capture/compare

register 000 (CR000)

INTTM000

fX

f

X

/2²

/2⁸

16-bit timer counter 00

(TM00)

OVF00^Note

fX

Noise

eliminator

TI000/P00

Clear

circuit

fX

Note OVF00 is set to 1 only when CR000 is set to FFFFH.

Figure 6-12. Timing of Interval Timer Operation

t

Count clock

TM00 count value

0000H

0001H

N

0000H 0001H

N

0000H 0001H

N

Timer operation enabled

N

Clear

N

CR000

INTTM000

Interrupt acknowledged

Remark Interval time = (N + 1) × t

N = 0001H to FFFFH (settable range)

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6.4.2 PPG output operations

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-13 for the set value).

<2> Set any value to the CR000 register as the cycle.

<3> Set any value to the CR010 register as the duty factor.

<4> Set the TOC00 register (see Figure 6-13 for the set value).

<5> Set the count clock by using the PRM00 register.

<6> Set the TMC00 register to start the operation (see Figure 6-13 for the set value).

Caution To change the value of the duty factor (the value of the CR010 register) during operation, see

Caution 2 in Figure 6-15 PPG Output Operation Timing.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle

that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer

capture/compare register 000 (CR000), respectively.

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Figure 6-13. Control Register Settings for PPG Output Operation

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

×

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output on match between TM00 and CR000

Specifies initial value of TO00 output F/F (setting “11” is prohibited.)

Inverts output on match between TM00 and CR010

Disables one-shot pulse output

(d) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

PRM001 PRM000

0

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Cautions 1. Values in the following range should be set in CR000 and CR010:

0000H ≤ CR010 < CR000 ≤ FFFFH

2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of

(CR010 setting value + 1)/(CR000 setting value + 1).

Remark ×: Don’t care

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Figure 6-14. Configuration of PPG Output

16-bit timer capture/compare

register 000 (CR000)

fX

f

X

/2²

/2⁸

Clear

circuit

16-bit timer counter 00

(TM00)

fX

Noise

eliminator

TI000/P00

TO00/TI010/P01

fX

16-bit timer capture/compare

register 010 (CR010)

Figure 6-15. PPG Output Operation Timing

t

Count clock

TM00 count value

0000H 0001H

M − 1

M

0000H 0001H

N

N − 1

N

Clear

CR000 capture value

CR010 capture value

TO00

N

M

Pulse width: (M + 1) × t

1 cycle: (N + 1) × t

Cautions 1. Do not rewrite CR000 during TM00 operation.

2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation

using the following procedure.

<1> Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0)

<2> Disable the INTTM010 interrupt (TMMK010 = 1)

<3> Rewrite CR010

<4> Wait for 1 cycle of the TM00 count clock

<5> Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1)

<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)

<7> Enable the INTTM010 interrupt (TMMK010 = 0)

Remark 0000H ≤ M < N ≤ FFFFH

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6.4.3 Pulse width measurement operations

It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer

counter 00 (TM00).

There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by

restarting the timer in synchronization with the edge of the signal input to the TI000 pin.

When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate

the necessary pulse width. Clear the overflow flag after checking it.

The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by

prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating

noise with a short pulse width.

Figure 6-16. CR010 Capture Operation with Rising Edge Specified

Count clock

TM00

N − 3

N − 2

N − 1

N

N + 1

TI000

Rising edge detection

N

CR010

INTTM010

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set the TMC00 register to start the operation (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).

Caution To use two capture registers, set the TI000 and TI010 pins.

Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 14 INTERRUPT

FUNCTIONS.

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(1) Pulse width measurement with free-running counter and one capture register

When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode

register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare

register 010 (CR010) and an external interrupt request signal (INTTM010) is set.

Specify both the rising and falling edges of the TI000 pin by using bits 4 and 5 (ES000 and ES001) of PRM00.

Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed

when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register (When TI000 and CR010 Are Used)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0/1

0

CR000 used as compare register

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter

f

X

/2²

/2⁸

16-bit timer counter 00

(TM00)

f

X

OVF00

16-bit timer capture/compare

register 010 (CR010)

TI000

INTTM010

Internal bus

Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter

and One Capture Register (with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2

D3

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

D0

D1

D2

D3

Note

(D3 – D2) × t

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

Note Clear OVF00 by software.

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(2) Measurement of two pulse widths with free-running counter

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure

the pulse widths of the two signals input to the TI000 pin and the TI010 pin.

When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to

the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt

request signal (INTTM010) is set.

Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value

of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal

(INTTM000) is set.

Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000

and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00.

Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is

only performed when the valid level of the TI000 pin or TI010 pin is detected twice, thus eliminating noise with a

short pulse width.

Figure 6-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0

1

CR000 used as capture register

Captures valid edge of TI010 pin to CR000

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

3

0

2

0

PRM001 PRM000

PRM00

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1 D2 + 2

D3

TM00 count value

TI000 pin input

D0

D1

D2

CR010 capture value

INTTM010

TI010 pin input

CR000 capture value

INTTM000

D1

D2 + 1

Note

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

(D3 – D2) × t

(10000H – D1 + (D2 + 1)) × t

Note Clear OVF00 by software.

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(3) Pulse width measurement with free-running counter and two capture registers

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width

of the signal input to the TI000 pin.

When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00

(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010

(CR010) and an interrupt request signal (INTTM010) is set.

Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into

16-bit timer capture/compare register 000 (CR000).

Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is

only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse

width.

Figure 6-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers (with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

CR000 used as capture register

Captures to CR000 at inverse edge

to valid edge of TI000.

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter

and Two Capture Registers (with Rising Edge Specified)

t

Count clock

TM00 count value

TI000 pin input

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1

D3

CR010 capture value

CR000 capture value

INTTM010

D0

D2

D1

D3

Note

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

(D3 – D2) × t

Note Clear OVF00 by software.

(4) Pulse width measurement by means of restart

When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken

into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000

pin is measured by clearing TM00 and restarting the count operation.

Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode

register 00 (PRM00).

Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a

capture operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise

with a short pulse width.

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Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart

(with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

0/1

0

Clears and starts at valid edge of TI000 pin.

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

1

CR000 used as capture register

Captures to CR000 at inverse edge to valid edge of TI000.

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Figure 6-25. Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified)

t

Count clock

0000H 0001H

D0 0000H 0001H D1

D2 0000H 0001H

TM00 count value

TI000 pin input

CR010 capture value

D0

D2

D1

CR000 capture value

INTTM010

D1 × t

D2 × t

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6.4.4 External event counter operation

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-26 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set any value to the CR000 register (0000H cannot be set).

<4> Set the TMC00 register to start the operation (see Figure 6-26 for the set value).

Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer

counter 00 (TM00).

TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.

When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is

cleared to 0 and the interrupt request signal (INTTM000) is generated.

Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out).

Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of

prescaler mode register 00 (PRM00).

Sampling is performed using the internal clock (f^X) and an operation is only performed when the valid level of the

TI000 pin is detected twice, thus eliminating noise with a short pulse width.

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Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0/1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

Selects external clock.

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.

See the description of the respective control registers for details.

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Figure 6-27. Configuration Diagram of External Event Counter

Internal bus

16-bit timer capture/compare

register 000 (CR000)

Match

Clear

INTTM000

OVF00^Note

Noise eliminator

fX

16-bit timer counter 00 (TM00)

Valid edge of TI000 pin

Note OVF00 is set to 1 only when CR000 is set to FFFFH.

Figure 6-28. External Event Counter Operation Timing (with Rising Edge Specified)

TI000 pin input

TM00 count value

CR000

0000H 0001H 0002H 0003H 0004H 0005H

N − 1

N

0000H 0001H 0002H 0003H

N

INTTM000

Caution When reading the external event counter count value, TM00 should be read.

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6.4.5 Square-wave output operation

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figure 6-29 for the set value).

<3> Set the TOC00 register (see Figure 6-29 for the set value).

<4> Set any value to the CR000 register (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figure 6-29 for the set value).

Caution Do not rewrite CR000 during TM00 operation.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

A square wave with any selected frequency can be output at intervals determined by the count value preset to 16-

bit timer capture/compare register 000 (CR000).

The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 +1 by setting

bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave

with any selected frequency to be output.

Figure 6-29. Control Register Settings in Square-Wave Output Mode (1/2)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

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Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2)

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

0/1

1

Enables TO00 output.

Inverts output on match between TM00 and CR000.

Specifies initial value of TO00 output F/F (setting “11” is prohibited).

Does not invert output on match between TM00 and CR010.

Disables one-shot pulse output.

(d) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

0

PRM001 PRM000

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the

description of the respective control registers for details.

Figure 6-30. Square-Wave Output Operation Timing

Count clock

TM00 count value

CR000

0000H 0001H 0002H

N − 1

N

0000H 0001H 0002H

N − 1

N

0000H

N

INTTM000

TO00 pin output

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.4.6 One-shot pulse output operation

16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external

trigger (TI000 pin input).

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figures 6-31 and 6-33 for the set value).

<3> Set the TOC00 register (see Figures 6-31 and 6-33 for the set value).

<4> Set any value to the CR000 and CR010 registers (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figures 6-31 and 6-33 for the set value).

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 14

INTERRUPT FUNCTIONS.

(1) One-shot pulse output with software trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-31, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.

By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes

active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the

output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000

(CR000)^Note

.

Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00

register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

Cautions 1. Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the one-

shot pulse again, wait until the current one-shot pulse output is completed.

2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software

trigger, do not change the level of the TI000 pin or its alternate-function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even

at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a

pulse at an undesired timing.

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Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

0/1

0

CR000 as compare register

CR010 as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

OSPT00 OSPE00 TOC004 LVS00

LVR00 TOC001 TOE00

0/1

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output upon match

between TM00 and CR000

Specifies initial value of

TO00 output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010

Sets one-shot pulse output mode

Set to 1 for output

(d) Prescaler mode register 00 (PRM00)

ES101

0/1

ES100

0/1

ES001

0/1

ES000

0/1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock.

Setting invalid

(setting “10” is prohibited.)

Setting invalid

(setting “10” is prohibited.)

Caution Do not set 0000H to the CR000 and CR010 registers.

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Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger

Set TMC00 to 04H

(TM00 count starts)

Count clock

TM00 count

CR010 set value

CR000 set value

0000H 0001H

N

N + 1 0000H

N – 1

N

M – 1

M

M + 1 M + 2

N

M

OSPT00

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002 bits are set to a

value other than 00 (operation stop mode).

Remark N < M

(2) One-shot pulse output with external trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-33, and by using the valid edge of the TI000 pin as an external trigger.

The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES001) of prescaler mode register 00

(PRM00). The rising, falling, or both the rising and falling edges can be specified.

When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the

output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010).

After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register

000 (CR000)^Note

.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

Caution Even if the external trigger is generated again while the one-shot pulse is being output, it is

ignored.

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Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger

(with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts at

valid edge of TI000 pin

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

0/1

CRC00

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

OSPT00 OSPE00 TOC004 LVS00

LVR00 TOC001 TOE00

0/1

7

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output upon match

between TM00 and CR000

Specifies initial value of

TO00 output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010

Sets one-shot pulse output mode

(d) Prescaler mode register 00 (PRM00)

ES101

0/1

ES100

0/1

ES001

0

ES000

1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock

(setting “11” is prohibited).

Specifies the rising edge

for pulse width detection.

Setting invalid

(setting “10” is prohibited.)

Caution Do not set the CR000 and CR010 registers to 0000H.

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Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)

When TMC00 is set to 08H

(TM00 count starts)

t

Count clock

TM00 count value

CR010 set value

CR000 set value

0000H 0001H

0000H

N

N + 1 N + 2

M − 2 M − 1

M

M + 1 M + 2

N

M

TI000 pin input

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003 bits are set to a

value other than 00 (operation stop mode).

Remark N < M

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.5 Cautions for 16-Bit Timer/Event Counter 00

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.

Figure 6-35. Start Timing of 16-Bit Timer Counter 00 (TM00)

Count clock

0000H

0001H

0002H

0003H

0004H

TM00 count value

Timer start

(2) 16-bit timer capture/compare register 000 setting

In the mode in which clear & start occurs on a match between TM00 and CR000, set 16-bit timer

capture/compare register 000 (CR000) to other than 0000H. This means a 1-pulse count operation cannot be

performed when 16-bit timer/event counter 00 is used as an external event counter.

(3) Capture register data retention timing

The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) are not guaranteed after

16-bit timer/event counter 00 has been stopped.

(4) Valid edge setting

Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control

register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4

and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).

(5) Re-triggering one-shot pulse

(a) One-shot pulse output by software

When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again

until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a

match with the CR010 register, occurs.

(b) One-shot pulse output with external trigger

If the external trigger occurs again while a one-shot pulse is output, it is ignored.

(c) One-shot pulse output function

When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change

the level of the TI000 pin or its alternate function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the

TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.

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(6) Operation of OVF00 flag

<1> The OVF00 flag is also set to 1 in the following case.

When of the following modes: the mode in which clear & start occurs on a match between TM00 and

CR000, the mode in which clear & start occurs at the TI000 pin valid edge, or the free-running mode, is

selected

↓

CR000 is set to FFFFH

↓

TM00 is counted up from FFFFH to 0000H.

Figure 6-36. Operation Timing of OVF00 Flag

Count clock

CR000

TM00

FFFFH

FFFEH

FFFFH

0000H

0001H

OVF00

INTTM000

<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the

occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.

(7) Conflicting operations

When the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture trigger input

(CR000/CR010 used as capture register) conflict, the priority is given to the capture trigger input. The data read

from CR000/CR010 is undefined.

Figure 6-37. Capture Register Data Retention Timing

Count clock

TM00 count value

Edge input

N

N + 1

N + 2

M

M + 1

M + 2

INTTM010

Capture read signal

CR010 capture value

X

N + 2

M + 1

Capture

Capture, but

read value is

not guaranteed

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(8) Timer operation

<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare

register 010 (CR010).

<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins

are not acknowledged.

<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between

the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not

occur.

(9) Capture operation

<1> If the TI000 pin valid edge is specified as the count clock, a capture operation by the capture register

specified as the trigger for TI000 is not possible.

<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than

the count clock selected by prescaler mode register 00 (PRM00).

<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input

(INTTM000/INTTM010), however, is generated at the rise of the next count clock.

(10) Compare operation

A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has

been input.

(11) Edge detection

<1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising

and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter

00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful

therefore when pulling up the TI000 or TI010 pin. However, when re-enabling operation after the operation

has been stopped, the rising edge is not detected if the TI000 or TI010 pin is high level.

<2> The sampling clock used to eliminate noise differs when the TI000 pin valid edge is used as the count clock

and when it is used as a capture trigger. In the former case, the count clock is f^X, and in the latter case the

count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only after

a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width.

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50

7.1 Functions of 8-Bit Timer/Event Counter 50

8-bit timer/event counter 50 has the following functions.

•

Interval timer

External event counter

Square-wave output

PWM output

Figure 7-1 shows the block diagram of 8-bit timer/event counter 50.

Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50

Internal bus

8-bit timer compare

register 50 (CR50)

Selector

Note 1

INTTM50

TI50/TO50/

FLMD1/P17

To TMH0

To UART0

To UART6

Match

f

X

f /2

X

S

INV

f

X

/2²

Q

8-bit timer

counter 50 (TM50)

/2⁶

/2⁸

OVF

TO50/TI50/

FLMD1/P17

R

f

X

/2¹³

Clear

Note 2

Output latch

(P17)

PM17

S

R

Invert

level

3

Selector

TCE50 TMC506 LVS50 LVR50 TMC501 TOE50

TCL502 TCL501 TCL500

8-bit timer mode control

register 50 (TMC50)

Timer clock selection

register 50 (TCL50)

Internal bus

Notes 1. Timer output F/F

2. PWM output F/F

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7.2 Configuration of 8-Bit Timer/Event Counter 50

8-bit timer/event counter 50 includes the following hardware.

Table 7-1. Configuration of 8-Bit Timer/Event Counter 50

Item

Timer register

Register

Configuration

8-bit timer counter 50 (TM50)

8-bit timer compare register 50 (CR50)

Timer input

Timer output

Control registers

TI50

TO50

Timer clock selection register 50 (TCL50)

8-bit timer mode control register 50 (TMC50)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) 8-bit timer counter 50 (TM50)

TM50 is an 8-bit register that counts the count pulses and is read-only.

The counter is incremented is synchronization with the rising edge of the count clock.

Figure 7-2. Format of 8-Bit Timer Counter 50 (TM50)

Address: FF16H

After reset: 00H

R

Symbol

TM50

In the following situations, the count value is cleared to 00H.

<1> RESET input

<2> When TCE50 is cleared

<3> When TM50 and CR50 match in clear & start mode if this mode was entered upon a match of TM50 and

CR50 values.

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(2) 8-bit timer compare register 50 (CR50)

CR50 can be read and written by an 8-bit memory manipulation instruction.

Except in PWM mode, the value set in CR50 is constantly compared with the 8-bit timer counter 50 (TM50) count

value, and an interrupt request (INTTM50) is generated if they match.

In PWM mode, when the TO50 pin becomes high level due to a TM50 overflow and the values of TM50 and

CR50 match, the TO50 pin becomes inactive.

The value of CR50 can be set within 00H to FFH.

RESET input clears this register to 00H.

Figure 7-3. Format of 8-Bit Timer Compare Register 50 (CR50)

Address: FF17H

After reset: 00H

R/W

Symbol

CR50

Cautions 1. In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not write

other values to CR50 during operation.

2. In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock

selected by TCL50) or more.

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7.3 Registers Controlling 8-Bit Timer/Event Counter 50

The following four registers are used to control 8-bit timer/event counter 50.

•

Timer four selection register 50 (TCL50)

8-bit timer mode control register 50 (TMC50)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Timer clock selection register 50 (TCL50)

This register sets the count clock of 8-bit timer/event counter 50 and the valid edge of the TI50 pin input.

TCL50 can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 7-4. Format of Timer Clock Selection Register 50 (TCL50)

Address: FF6AH After reset: 00H R/W

Symbol

TCL50

7

0

6

0

5

0

4

0

3

0

2

1

0

TCL502

TCL501

TCL500

TCL502

TCL501

TCL500

Count clock selection^Note

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TI50 pin falling edge

TI50 pin rising edge

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2⁶(156.25 kHz)

fX/2⁸(39.06 kHz)

fX/2¹³(1.22 kHz)

Note Be sure to set the count clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Count clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Count clock ≤ 8.38 MHz

• VDD = 2.7 to 3.3 V: Count clock ≤ 5 MHz

• V^DD= 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)

<R>

Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not

guaranteed.

2. When rewriting TCL50 to other than the same data, stop the timer operation beforehand.

3. Be sure to set bits 3 to 7 to 0.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses apply to operation at f^X= 10 MHz.

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(2) 8-bit timer mode control register 50 (TMC50)

TMC50 is a register that performs the following five types of settings.

<1> 8-bit timer counter 50 (TM50) count operation control

<2> 8-bit timer counter 50 (TM50) operating mode selection

<3> Timer output F/F (flip-flop) status setting

<4> Active level selection in timer F/F control or PWM (free-running) mode

<5> Timer output control

TMC50 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 7-5 shows the TMC50 format.

Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50)

Address: FF6BH

Symbol

After reset: 00H R/W^Note

<7>

6

5

0

4

0

<3>

<2>

1

<0>

TMC50

TCE50

TMC506

LVS50

LVR50

TMC501

TOE50

TCE50

TM50 count operation control

0

1

After clearing to 0, count operation disabled (counter stopped)

Count operation start

TMC506

TM50 operating mode selection

Clear & start mode by match between TM50 and CR50

PWM (free-running) mode

0

1

LVS50

LVR50

Timer output F/F status setting

0

1

0

1

0

1

No change

Timer output F/F reset (0)

Timer output F/F set (1)

Setting prohibited

TMC501

In other modes (TMC506 = 0)

Timer F/F control

In PWM mode (TMC506 = 1)

Active level selection

0

1

Inversion operation disabled

Inversion operation enabled

Active high

Active low

TOE50

Timer output control

0

1

Output disabled (TM50 outputs the low level)

Output enabled

Note Bits 2 and 3 are write-only.

(Refer to Cautions and Remarks on the next page.)

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Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode.

2. Do not make settings <1> to <4> below simultaneously. In addition, follow the setting

procedure shown below.

<1> Setting of TMC501 and TMC506:

Setting of operation mode

Enabling timer output

<2> Setting of TOE50 if enabling output:

<3> Setting of LVS50 and LVR50 (see Caution 1): Setting of timer output F/F

<4> Setting of TCE50

3. Stop operation before rewriting TMC506.

Remarks 1. In PWM mode, PWM output is made inactive by setting TCE50 to 0.

2. If LVS50 and LVR50 are read, 0 is read.

3. The values of the TMC506, LVS50, LVR50, TMC501, and TOE50 bits are reflected at the TO50 pin

regardless of the value of TCE50.

(3) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using the P17/TO50/TI50/FLMD1 pin for timer output, set PM17 and the output latches of P17 to 0.

Set PM17 to 1 when using the P17/TO50/TI50/FLMD1 pin as a timer input pin. The output latch of P17 at this

time may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 7-6. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

6

5

4

3

2

1

0

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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7.4 Operations of 8-Bit Timer/Event Counter 50

7.4.1 Operation as interval timer

8-bit timer/event counter 50 operates as an interval timer that generates interrupt requests repeatedly at intervals

of the count value preset to 8-bit timer compare register 50 (CR50).

When the count value of 8-bit timer counter 50 (TM50) matches the value set to CR50, counting continues with the

TM50 value cleared to 0 and an interrupt request signal (INTTM50) is generated.

The count clock of TM50 can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50

(TCL50).

Setting

<1> Set the registers.

•

TCL50: Select the count clock.

CR50: Compare value

TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50.

(TMC50 = 0000×××0B × = Don’t care)

<2> After TCE50 = 1 is set, the count operation starts.

<3> If the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H).

<4> INTTM50 is generated repeatedly at the same interval.

Set TCE50 to 0 to stop the count operation.

Caution Do not write other values to CR50 during operation.

Figure 7-7. Interval Timer Operation Timing (1/2)

(a) Basic operation

t

Count clock

TM50 count value

CR50

00H 01H

Count start

N

00H 01H

N

00H 01H

N

Clear

N

TCE50

INTTM50

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time

Remark Interval time = (N + 1) × t

N = 01H to FEH

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Figure 7-7. Interval Timer Operation Timing (2/2)

(b) When CR50 = 00H

t

Count clock

TM50 00H

CR50

00H 00H

TCE50

INTTM50

Interval time

(c) When CR50 = FFH

t

Count clock

TM50

01H

FEH FFH 00H

FFH

FEH FFH 00H

FFH

CR50

FFH

TCE50

INTTM50

Interrupt acknowledged

Interval time

Interrupt

acknowledged

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7.4.2 Operation as external event counter

The external event counter counts the number of external clock pulses to be input to the TI50 pin by 8-bit timer

counter 50 (TM50).

TM50 is incremented each time the valid edge specified by timer clock selection register 50 (TCL50) is input.

Either the rising or falling edge can be selected.

When the TM50 count value matches the value of 8-bit timer compare register 50 (CR50), TM50 is cleared to 0

and an interrupt request signal (INTTM50) is generated.

Whenever the TM50 count value matches the value of CR50, INTTM50 is generated.

Setting

<1> Set each register.

•

Set port mode register 1 (PM17) to 1.

TCL50: Select TI50 pin edge.

TI50 pin falling edge → TCL50 = 00H

TI50 pin rising edge → TCL50 = 01H

•

CR50: Compare value

TMC50: Stop the count operation, select clear & start mode entered on match of TM50 and CR50,

disable the timer F/F inversion operation, disable timer output.

(TMC50 = 0000××00B × = Don’t care)

<2> When TCE50 = 1 is set, the number of pulses input from the TI50 pin is counted.

<3> When the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H).

<4> After these settings, INTTM50 is generated each time the values of TM50 and CR50 match.

Figure 7-8. External Event Counter Operation Timing (with Rising Edge Specified)

TI50

Count start

TM50 count value

CR50

00H 01H 02H 03H 04H 05H

N–1

N

00H 01H 02H 03H

N

INTTM50

N = 00H to FFH

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50

7.4.3 Operation as square-wave output

A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer

compare register 50 (CR50).

The TO50 pin output status is inverted at intervals determined by the count value preset to CR50 by setting bit 0

(TOE50) of 8-bit timer mode control register 50 (TMC50) to 1. This enables a square wave with any selected

frequency to be output (duty = 50%).

Setting

<1> Set each register.

•

Set the port output latch (P17) and port mode register 1 (PM17) to 0.

TCL50: Select the count clock.

CR50: Compare value

TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50.

LVS50 LVR50

Timer Output F/F Status Setting

High-level output

Low-level output

1

0

1

Timer output F/F inversion enabled

Timer output enabled

(TMC50 = 00001011B or 00000111B)

<2> After TCE50 = 1 is set, the count operation starts.

<3> The timer output F/F is inverted by a match of TM50 and CR50. After INTTM50 is generated, TM50 is

cleared to 00H.

<4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from

TO50.

The frequency is as follows.

Frequency = 1/2t (N + 1)

(N: 00H to FFH)

Caution Do not write other values to CR50 during operation.

Figure 7-9. Square-Wave Output Operation Timing

t

Count clock

TM50 count value

00H 01H 02H

Count start

N − 1

N

00H 01H 02H

N − 1

N

00H

CR50

N

TO50^Note

Note The initial value of TO50 output can be set by bits 2 and 3 (LVR50, LVS50) of 8-bit timer mode control

register 50 (TMC50).

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CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50

7.4.4 Operation as PWM output

8-bit timer/event counter 50 operates as a PWM output when bit 6 (TMC506) of 8-bit timer mode control register 50

(TMC50) is set to 1.

The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50).

Set the active level width of the PWM pulse to CR50; the active level can be selected with bit 1 of TMC50

(TMC501).

The count clock can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50 (TCL50).

PWM output can be enabled/disabled with bit 0 of TMC50 (TOE50).

Caution In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected by

TCL50) or more.

(1) PWM output basic operation

Setting

<1> Set each register.

•

Set the port output latch (P17) and port mode register 1 (PM17) to 0.

TCL50: Select the count clock.

CR50: Compare value

TMC50: Stop the count operation, select PWM mode.

The timer output F/F is not changed, timer output is enabled.

TMC501

Active Level Selection

0

1

Active-high

Active-low

(TMC50 = 01000001B or 01000011B)

<2> The count operation starts when TCE50 = 1.

Set TCE50 to 0 to stop the count operation.

PWM output operation

<1> PWM output (output from TO50) outputs an inactive level until an overflow occurs.

<2> When an overflow occurs, the active level is output.

The active level is output until CR50 matches the count value of 8-bit timer counter 50 (TM50).

<3> After the CR50 matches the count value, the inactive level is output until an overflow occurs again.

<4> Operations <2> and <3> are repeated until the count operation stops.

<5> When the count operation is stopped with TCE50 = 0, PWM output becomes inactive.

For details of timing, see Figures 7-10 and 7-11.

The cycle, active-level width, and duty are as follows.

•

Cycle = 2⁸t

Active-level width = Nt

Duty = N/2⁸

(N = 00H to FFH)

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Figure 7-10. PWM Output Operation Timing

(a) Basic operation (active level = H)

t

Count clock

TM50

00H 01H

N

FFH 00H 01H 02H

N

N+1

FFH 00H 01H 02H

M

00H

CR50

TCE50

INTTM50

TO50

<1>

<5>

<2> Active level

<3> Inactive level

Active level

(b) CR50 = 00H

t

Count clock

TM50 00H 01H

FFH 00H 01H 02H

N

N+1 N+2

FFH 00H 01H 02H

M 00H

00H

CR50

TCE50

INTTM50

TO50

L

Inactive level

(c) CR50 = FFH

t

Count clock

TM50

M

00H

00H 01H

FFH 00H 01H 02H

N

N+1 N+2

FFH 00H 01H 02H

CR50

FFH

TCE50

INTTM50

TO50

Active level

Inactive level

Active level

Remark <1> to <3> and <5> in Figure 7-10 (a) correspond to <1> to <3> and <5> in PWM output operation in

7.4.4 (1) PWM output basic operation.

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(2) Operation with CR50 changed

Figure 7-11. Timing of Operation with CR50 Changed

(a) CR50 value is changed from N to M before clock rising edge of FFH

→ Value is transferred to CR50 at overflow immediately after change.

t

Count clock

TM50

CR50

N

N + 1 N + 2

FFH 00H 01H 02H

M

M + 1 M + 2

FFH 00H 01H 02H

M M + 1 M + 2

N

M

TCE50

H

INTTM50

TO50

<2>

<1> CR50 change (N → M)

(b) CR50 value is changed from N to M after clock rising edge of FFH

→ Value is transferred to CR50 at second overflow.

t

Count clock

TM50

N

N + 1 N + 2

FFH 00H 01H 02H

N

N + 1 N + 2

FFH 00H 01H 02H

M M+1 M+2

CR50

N

M

TCE50

H

INTTM50

TO50

<2>

<1> CR50 change (N → M)

Caution When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from the

actual value (read value: M, actual value of CR50: N).

7.5 Cautions for 8-Bit Timer/Event Counter 50

(1) Timer start error

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 8-bit timer counter 50 (TM50) is started asynchronously to the count clock.

Figure 7-12. 8-Bit Timer Counter 50 Start Timing

Count clock

TM50 count value

00H

Timer start

01H

02H

03H

04H

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CHAPTER 8 8-BIT TIMERS H0 AND H1

8.1 Functions of 8-Bit Timers H0 and H1

8-bit timers H0 and H1 have the following functions.

•

Interval timer

PWM output mode

Square-wave output

8.2 Configuration of 8-Bit Timers H0 and H1

8-bit timers H0 and H1 include the following hardware.

Table 8-1. Configuration of 8-Bit Timers H0 and H1

Item

Timer register

Registers

Configuration

8-bit timer counter Hn

8-bit timer H compare register 0n (CMP0n)

8-bit timer H compare register 1n (CMP1n)

Timer outputs

TOHn

Control registers

8-bit timer H mode register n (TMHMDn)

Port mode register 1 (PM1)

Port register 1 (P1)

Remark n = 0, 1

Figures 8-1 and 8-2 show the block diagrams.

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(1) 8-bit timer H compare register 0n (CMP0n)

This register can be read/written by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n)

Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H R/W

Symbol

7

5

3

2

1

0

6

4

CMP0n

(n = 0, 1)

Caution CMP0n cannot be rewritten during timer count operation.

(2) 8-bit timer H compare register 1n (CMP1n)

This register can be read/written by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)

Address: FF19H (CMP10), FF1BH (CMP11) After reset: 00H R/W

Symbol

7

5

3

2

1

0

6

4

CMP1n

(n = 0, 1)

CMP1n can be rewritten during timer count operation.

If the CMP1n value is rewritten during timer operation, transfer is performed at the timing at which the count value

and CMP1n value match. If the transfer timing and writing from CPU to CMP1n conflict, transfer is not performed.

Caution In the PWM output mode be sure to set CMP1n when starting the timer count operation (TMHEn =

1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting

the same value to CMP1n).

Remark n = 0, 1

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8.3 Registers Controlling 8-Bit Timers H0 and H1

The following three registers are used to control 8-bit timers H0 and H1.

• 8-bit timer H mode register n (TMHMDn)

• Port mode register 1 (PM1)

• Port register 1 (P1)

(1) 8-bit timer H mode register n (TMHMDn)

This register controls the mode of timer H.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Remark n = 0, 1

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Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)

Address: FF69H After reset: 00H R/W

Symbol

<7>

5

3

2

<1>

<0>

6

4

TMHMD0

TMHE0 CKS02

CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0

TMHE0

Timer operation enable

0

1

Stops timer count operation (counter is cleared to 0)

Enables timer count operation (count operation started by inputting clock)

CKS02

CKS01

CKS00

Count clock (f^CNT) selection^{Note 1}

(10 MHz)

0

1

0

1

0

1

0

1

0

1

f

X

/2

(5 MHz)

/2²

/2⁶

(2.5 MHz)

(156.25 kHz)

/2¹⁰(9.77 kHz)

TM50 output^{Note 2}

Setting prohibited

Other than above

TMMD01 TMMD00

Timer operation mode

0

1

0

Interval timer mode

PWM output mode

Other than above Setting prohibited

TOLEV0

Timer output level control (in default mode)

0

1

Low level

High level

TOEN0

Timer output control

0

1

Disables output

Enables output

Notes 1. Be sure to set the count clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Count clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Count clock ≤ 8.38 MHz

• V^DD= 2.7 to 3.3 V: Count clock ≤ 5 MHz

• VDD = 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)

2. Note the following points when selecting the TM50 output as the count clock.

• PWM mode (TMC506 = 1)

<R>

Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty

= 50%.

• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)

Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion

operation (TMC501 = 1).

It is not necessary to enable the TO50 pin as a timer output pin in any mode.

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Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer H0 is not guaranteed.

2. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.

3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when

starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped

(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses apply to operation at fX = 10 MHz

3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)

TMC501: Bit 1 of TMC50

Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)

Address: FF6CH After reset: 00H R/W

Symbol

<7>

5

3

2

<1>

<0>

6

4

TMHMD1

TMHE1 CKS12

CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

TMHE1

Timer operation enable

0

1

Stops timer count operation (counter is cleared to 0)

Enables timer count operation (count operation started by inputting clock)

CKS12

CKS11

CKS10

Count clock (f^CNT) selection^Note

(10 MHz)

0

1

0

1

0

1

0

1

0

1

f

X

/2²

/2⁴

/2⁶

(2.5 MHz)

(625 kHz)

(156.25 kHz)

/2¹²(2.44 kHz)

/2⁷

(1.88 kHz (TYP.))

R

Other than above

Setting prohibited

TMMD11 TMMD10

Timer operation mode

0

1

0

Interval timer mode

PWM output mode

Setting prohibited

Other than above

TOLEV1

Timer output level control (in default mode)

0

1

Low level

High level

TOEN1

Timer output control

0

1

Disables output

Enables output

Note Be sure to set the count clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Count clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Count clock ≤ 8.38 MHz

• V^DD= 2.7 to 3.3 V: Count clock ≤ 5 MHz

<R>

• V^DD= 2.5 to 2.7 V: Count clock ≤ 2.5 MHz (standard products, (A) grade products only)

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Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer H1 is not guaranteed (except

when CKS12, CKS11, CKS10 = 1, 0, 1 (f^R/2⁷)).

2. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.

3. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when

starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped

(TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).

Remarks 1. fX: High-speed system clock oscillation frequency

2. f^R: Internal oscillation clock frequency

3. Figures in parentheses apply to operation at f^X= 10 MHz, fR = 240 kHz (TYP.).

(2) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output

latches of P15 and P16 to 0.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 8-7. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

6

5

4

3

2

1

0

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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8.4 Operation of 8-Bit Timers H0 and H1

8.4.1 Operation as interval timer/square-wave output

When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is

generated and 8-bit timer counter Hn is cleared to 00H.

Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the

CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.

By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)

is output from TOHn.

(1) Usage

Generates the INTTMHn signal repeatedly at the same interval.

<1> Set each register.

Figure 8-8. Register Setting During Interval Timer/Square-Wave Output Operation

(i) Setting timer H mode register n (TMHMDn)

TMHEn

0

CKSn2 CKSn1

0/1 0/1

CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn

0/1 0/1 0/1

TMHMDn

0

Timer output setting

Timer output level inversion setting

Interval timer mode setting

Count clock (f^CNT) selection

Count operation stopped

(ii) CMP0n register setting

Compare value (N)

•

<2> Count operation starts when TMHEn = 1.

<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated

and 8-bit timer counter Hn is cleared to 00H.

Interval time = (N +1)/f^CNT

<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set

TMHEn to 0.

Remark n = 0, 1

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(2) Timing chart

The timing of the interval timer/square-wave output operation is shown below.

Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (1/2)

(a) Basic operation

Count clock

Count start

00H

01H

N

00H

Clear

01H

N

00H 01H 00H

Clear

8-bit timer counter Hn

CMP0n

TMHEn

INTTMHn

TOHn

Interval time

<1>

<2>

Level inversion,

<3>

<2>

Level inversion,

match interrupt occurrence,

8-bit timer counter Hn clear

match interrupt occurrence,

8-bit timer counter Hn clear

<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than

1 clock after the operation is enabled.

<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn

is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.

<3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn

operation. If these are inactive from the first, the level is retained.

Remark n = 0, 1

N = 01H to FEH

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Figure 8-9. Timing of Interval Timer/Square-Wave Output Operation (2/2)

(b) Operation when CMP0n = FFH

Count clock

Count start

00H

01H

FEH

FFH

00H

FEH

FFH

8-bit timer counter Hn

Clear

FFH

CMP0n

TMHEn

INTTMHn

TOHn

Interval time

(c) Operation when CMP0n = 00H

Count clock

Count start

00H

8-bit timer counter Hn

CMP0n

TMHEn

INTTMHn

TOHn

Interval time

Remark n = 0, 1

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8.4.2 Operation as PWM output mode

In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.

8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register

during timer operation is prohibited.

8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register

during timer operation is possible.

The operation in PWM output mode is as follows.

TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the

CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn

and the CMP1n register match.

(1) Usage

In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.

<1> Set each register.

Figure 8-10. Register Setting in PWM Output Mode

(i) Setting timer H mode register n (TMHMDn)

TMHEn

0

CKSn2 CKSn1

0/1 0/1

CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn

0/1 0/1

TMHMDn

1

0

1

Timer output enabled

Timer output level inversion setting

PWM output mode selection

Count clock (f^CNT) selection

Count operation stopped

(ii) Setting CMP0n register

• Compare value (N): Cycle setting

(iii) Setting CMP1n register

• Compare value (M): Duty setting

Remarks 1. n = 0, 1

2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH

<2> The count operation starts when TMHEn = 1.

<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.

When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared,

an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time,

the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the

CMP1n register.

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<4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the

compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the

CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not

generated.

<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.

<6> To stop the count operation, set TMHEn = 0.

If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock

frequency is f^CNT, the PWM pulse output cycle and duty are as follows.

PWM pulse output cycle = (N + 1)/f^CNT

Duty = Active width : Total width of PWM = (M + 1) : (N + 1)

Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0

bits of the TMHMDn register) are required to transfer the CMP1n register value after

rewriting the register.

2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after

the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the

same value to the CMP1n register).

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(2) Timing chart

The operation timing in PWM output mode is shown below.

Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are

within the following range.

00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH

Remark n = 0, 1

Figure 8-11. Operation Timing in PWM Output Mode (1/4)

(a) Basic operation

Count clock

00H 01H

A5H 00H 01H 02H

A5H 00H

8-bit timer counter Hn

A5H

01H

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

<4>

<2>

<3>

<1>

TOHn

(TOLEVn = 1)

<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one

count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0).

<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted,

the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.

<3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is

returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.

<4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.

Remark n = 0, 1

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Figure 8-11. Operation Timing in PWM Output Mode (2/4)

(b) Operation when CMP0n = FFH, CMP1n = 00H

Count clock

8-bit timer counter Hn

00H 01H

FFH 00H 01H 02H

FFH 00H

FFH

00H

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

(c) Operation when CMP0n = FFH, CMP1n = FEH

Count clock

00H 01H

FEH FFH 00H 01H

FEH FFH 00H

8-bit timer counter Hn

FFH

FEH

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

Remark n = 0, 1

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Figure 8-11. Operation Timing in PWM Output Mode (3/4)

(d) Operation when CMP0n = 01H, CMP1n = 00H

Count clock

00H 01H 00H 01H 00H

00H 01H 00H 01H

8-bit timer counter Hn

CMP0n

01H

00H

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

Remark n = 0, 1

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Figure 8-11. Operation Timing in PWM Output Mode (4/4)

(e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H)

Count clock

8-bit timer counter Hn

00H 01H 02H

A5H 00H 01H 02H 03H

A5H 00H

A5H

03H

CMP0n

CMP1n

01H

01H (03H)

<2>'

<2>

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

<3>

<4>

<6>

<1>

<5>

<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count

clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).

<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous

to the count clock.

<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn

is cleared, the TOHn output becomes active, and the INTTMHn signal is output.

<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the

values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to

the CMP1n register and the CMP1n register value is changed (<2>’).

However, three count clocks or more are required from when the CMP1n register value is changed to when

the value is transferred to the register. If a match signal is generated within three count clocks, the changed

value cannot be transferred to the register.

<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output

becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.

<6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.

Remark n = 0, 1

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CHAPTER 9 WATCHDOG TIMER

9.1 Functions of Watchdog Timer

The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset

signal is generated.

When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.

For details of RESF, see CHAPTER 16 RESET FUNCTION.

Table 9-1. Loop Detection Time of Watchdog Timer

Loop Detection Time

During Internal Oscillation Clock Operation During High-Speed System Clock Operation

2¹¹/fR (4.27 ms)

2¹²/fR (8.53 ms)

2¹³/fR (17.07 ms)

2¹⁴/fR (34.13 ms)

2¹⁵/fR (68.27 ms)

2¹⁶/fR (136.53 ms)

2¹⁷/fR (273.07 ms)

2¹⁸/fR (546.13 ms)

2¹³/fXP (819.2 µs)

2¹⁴/fXP (1.64 ms)

2¹⁵/fXP (3.28 ms)

2¹⁶/fXP (6.55 ms)

2¹⁷/fXP (13.11 ms)

2¹⁸/fXP (26.21 ms)

2¹⁹/fXP (52.43 ms)

2²⁰/fXP (104.86 ms)

Remarks 1. fR: Internal oscillation clock frequency

2. f^XP: High-speed system clock oscillation frequency

3. Figures in parentheses apply to operation at f^R= 480 kHz (MAX.), fXP = 10 MHz

The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the internal

oscillator as shown in Table 9-2.

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Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode

Option Byte

Internal Oscillator Cannot Be Stopped Internal Oscillator Can Be Stopped by

Software

Note 1

Watchdog timer clock

source

Fixed to f^R

.

• Selectable by software (f^XP, fR or

stopped)

• When reset is released: f^R

Operation after reset

Operation mode selection

Features

Operation starts with the maximum

interval (2¹⁸/fR).

Operation starts with maximum

interval (2¹⁸/fR).

The interval can be changed only

once.

The clock selection/interval can be

changed only once.

The watchdog timer cannot be

stopped.

The watchdog timer can be stopped in

standby mode^{Note 2}

.

Notes 1. As long as power is being supplied, the internal oscillator cannot be stopped (except in the reset

period).

2. The conditions under which clock supply to the watchdog timer is stopped differ depending on

the clock source of the watchdog timer.

<1> If the clock source is f^XP, clock supply to the watchdog timer is stopped under the following

conditions.

• When f^XPis stopped

• In HALT/STOP mode

• During oscillation stabilization time

<2> If the clock source is f^R, clock supply to the watchdog timer is stopped under the following

conditions.

• If the CPU clock is f^XPand if fR is stopped by software before execution of the STOP

instruction

• In HALT/STOP mode

Remarks 1. f^R: Internal oscillation clock frequency

2. f^XP: High-speed system clock oscillation frequency

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9.2 Configuration of Watchdog Timer

The watchdog timer includes the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item

Configuration

Control registers

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

Figure 9-1. Block Diagram of Watchdog Timer

2¹¹/f

2¹⁸/f

R

to

f

/2²

R

Clock

input

controller

Output

controller

16-bit

counter

Internal reset signal

Selector

f

XP/2⁴

or

2¹³/fXP to

2²⁰/fXP

2

3

Clear

Option byte

(to set “Internal oscillator

cannot be stopped” or

“Internal oscillator can be

stopped by software”)

0

1

WDCS4 WDCS3 WDCS2 WDCS1 WDCS0

Watchdog timer enable

register (WDTE)

Watchdog timer mode

register (WDTM)

Internal bus

9.3 Registers Controlling Watchdog Timer

The watchdog timer is controlled by the following two registers.

•

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

(1) Watchdog timer mode register (WDTM)

This register sets the overflow time and operation clock of the watchdog timer.

This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be

written only once after reset is released.

RESET input sets this register to 67H.

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Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)

Address: FF98H After reset: 67H R/W

7

0

6

1

5

1

4

3

2

1

0

Symbol

WDTM

WDCS4

WDCS3

WDCS2

WDCS1

WDCS0

WDCS4^{Note 1}WDCS3^{Note 1}

Operation clock selection

0

1

0

1

×

Internal oscillation clock (fR)

High-speed system clock (fXP)

Watchdog timer operation stopped

WDCS2^{Note 2}WDCS1^{Note 2}WDCS0^{Note 2}

Overflow time setting

During internal oscillation clock During high-speed system clock

operation operation

2¹¹/fR (4.27 ms) 2¹³/fXP (819.2 µs)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2¹²/fR (8.53 ms)

2¹⁴/fXP (1.64 ms)

2¹⁵/fXP (3.28 ms)

2¹⁶/fXP (6.55 ms)

2¹⁷/fXP (13.11 ms)

2¹⁸/fXP (26.21 ms)

2¹⁹/fXP (52.43 ms)

2²⁰/fXP (104.86 ms)

2¹³/fR (17.07 ms)

2¹⁴/fR (34.13 ms)

2¹⁵/fR (68.27 ms)

2¹⁶/fR (136.53 ms)

2¹⁷/fR (273.07 ms)

2¹⁸/fR (546.13 ms)

Notes 1. If “Internal oscillator cannot be stopped” is specified by the option byte, this cannot be set.

The internal oscillation clock will be selected no matter what value is written.

2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).

Cautions 1. If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Internal oscillator cannot be

stopped” is selected by the option byte, other values are ignored).

3. After reset is released, WDTM can be written only once by an 8-bit memory

manipulation instruction. If writing is attempted a second time, an internal reset

signal is generated. If the source clock to the watchdog timer is stopped, however,

an internal reset signal is generated when the source clock to the watchdog timer

resumes operation.

4. WDTM cannot be set by a 1-bit memory manipulation instruction.

5. If “Internal oscillator can be stopped by software” is selected by the option byte and

the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not

resume operation even if WDCS4 is cleared to 0. In addition, the internal reset signal

is not generated.

Remarks 1. f^R: Internal oscillation clock frequency

2. f^XP: High-speed system clock oscillation frequency

3. ×: Don’t care

4. Figures in parentheses apply to operation at f^R= 480 kHz (MAX.), fXP = 10 MHz

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(2) Watchdog timer enable register (WDTE)

Writing ACH to WDTE clears the watchdog timer counter and starts counting again.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 9AH.

Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)

Address: FF99H After reset: 9AH R/W

7

6

5

4

3

2

1

0

Symbol

WDTE

Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If

the source clock to the watchdog timer is stopped, however, an internal reset signal

is generated when the source clock to the watchdog timer resumes operation.

2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset

signal is generated. If the source clock to the watchdog timer is stopped, however,

an internal reset signal is generated when the source clock to the watchdog timer

resumes operation.

3. The value read from WDTE is 9AH (this differs from the written value (ACH)).

The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog

timer is shown below.

Table 9-4. Relationship Between Watchdog Timer Operation and

Internal Reset Signal Generated by Watchdog Timer

Watchdog Timer

Operation

“Internal Oscillator

Cannot Be Stopped by

Software” Is Selected

by Option Byte

“Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte

Watchdog Timer Is

Operating

Watchdog Timer Stopped

WDCS4 Is Set to 1

Source Clock to

Internal

Reset Signal

Generation Cause

Watchdog Timer Is

Stopped

(Watchdog Timer Is

Always Operating)

Watchdog timer

overflows

Internal reset signal is

generated.

Internal reset signal is

generated.

−

Write to WDTM for the

second time

Internal reset signal is

generated.

Internal reset signal is

generated.

Internal reset signal is

not generated and the

watchdog timer does

not resume operation.

Internal reset signal is

generated when the

source clock to the

watchdog timer

resumes operation.

Write other than “ACH”

to WDTE

Internal reset signal is

generated.

Internal reset signal is

generated.

Internal reset signal is

not generated.

Internal reset signal is

generated when the

source clock to the

watchdog timer

Access WDTE by 1-bit

memory manipulation

instruction

resumes operation.

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9.4 Operation of Watchdog Timer

9.4.1 Watchdog timer operation when “Internal oscillator cannot be stopped” is selected by option byte

The operation clock of watchdog timer is fixed to the internal oscillation clock.

After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of

the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Internal oscillation clock

Cycle: 2¹⁸/fR (546.13 ms: At operation with fR = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2}

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

.

•

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. The operation clock (internal oscillation clock) cannot be changed. If any value is written to bits 3 and

4 (WDCS3, WDCS4) of WDTM, it is ignored.

2. As soon as WDTM is written, the counter of the watchdog timer is cleared.

Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP

instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation clock can

be selected as the count source, so after STOP instruction execution, clear the watchdog timer

using the interrupt request of TMH1 before the watchdog timer overflows. If this processing is

not performed, an internal reset signal is generated when the watchdog timer overflows after

STOP instruction execution.

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9.4.2 Watchdog timer operation when “Internal oscillator can be stopped by software” is selected by option

byte

The operation clock of the watchdog timer can be selected as either the internal oscillation clock or the high-speed

system clock.

After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of

the watchdog timer mode register (WDTM) = 1, 1, 1) of the internal oscillation clock.

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Internal oscillation clock

Cycle: 2¹⁸/fR (546.13 ms: At operation with fR = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2, 3}

.

•

Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).

Internal oscillation clock (f^R)

High-speed system clock (f^XP)

Watchdog timer operation stopped

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

•

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.

2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. These bits must not be set to other values.

3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal

reset signal is not generated even if the following processing is performed.

•

WDTM is written a second time.

A 1-bit memory manipulation instruction is executed to WDTE.

A value other than ACH is written to WDTE.

Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.

After HALT/STOP mode is released, counting is started again using the operation clock of the

watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter

is not cleared to 0 but holds its value.

For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer

operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.

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9.4.3 Watchdog timer operation in STOP mode (when “Internal oscillator can be stopped by software” is

selected by option byte)

The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed

system clock or internal oscillation clock is being used.

(1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f^XP) when

the STOP instruction is executed

When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,

counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)

and then counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: High-Speed System Clock)

Normal

operation

Oscillation stabilization time

CPU operation

STOP

Normal operation

f

XP

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

f

R

Watchdog timer

Operating

Operation stopped

Operating

(2) When the CPU clock is the high-speed system clock (f^XP) and the watchdog timer operation clock is the

internal oscillation clock (f^R) when the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-5. Operation in STOP Mode

(CPU Clock: High-Speed System Clock, WDT Operation Clock: Internal Oscillation Clock)

Normal

operation

Oscillation stabilization time

Normal operation

CPU operation

STOP

fXP

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

fR

Watchdog timer

Operating Operation stopped

Operating

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(3) When the CPU clock is the internal oscillation clock (fR) and the watchdog timer operation clock is the

high-speed system clock (f^XP) when the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started

using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds

its value.

<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.

<2> The CPU clock is switched to the high-speed system clock (f^XP).

Figure 9-6. Operation in STOP Mode

(CPU Clock: Internal Oscillation Clock, WDT Operation Clock: High-Speed System Clock)

<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time

select register (OSTS) has elapsed

Normal operation

(internal oscillation

STOP

Clock supply stopped

clock)

Normal operation (internal oscillation clock)

CPU operation

fXP

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

f^R

17 clocks

Watchdog timer

Operating

Operation stopped

Operating

<2> Timing when counting is started after the CPU clock is switched to the high-speed system clock (fXP)

Normal operation (internal oscillation clock)

CPU clock

Note

fR → fXP

Normal operation

(internal oscillation

clock)

Normal operation

Clock supply

stopped

STOP

(high-speed system clock)

CPU operation

f

XP

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

fR

17 clocks

Watchdog timer

Operating

Operation stopped

Operating

Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register

(OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be switched

without reading the OSTC value.

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(4) When CPU clock and watchdog timer operation clock are the internal oscillation clocks (fR) during STOP

instruction execution

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Internal Oscillation Clock)

Normal operation

(internal oscillation

STOP

Clock supply stopped

clock)

Normal operation (internal oscillation clock)

CPU operation

f

XP

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

f

R

17 clocks

Operating

Watchdog timer

Operating

Operation stopped

9.4.4 Watchdog timer operation in HALT mode (when “Internal oscillator can be stopped by software” is

selected by option byte)

The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the

high-speed system clock (f^XP) or internal oscillation clock (fR), or whether the operation clock of the watchdog timer is

the high-speed system clock (f^XP) or internal oscillation clock (fR). After HALT mode is released, counting is started

again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but

holds its value.

Figure 9-8. Operation in HALT Mode

Normal operation

HALT

Normal operation

CPU operation

f

XP

f

R

Watchdog timer

Operating Operation stopped

Operating

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CHAPTER 10 A/D CONVERTER

10.1 Function of A/D Converter

The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to

ANI3) with a resolution of 10 bits.

The A/D converter has the following two functions.

(1) 10-bit resolution A/D conversion

10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to

ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.

(2) Power-fail detection function

This function is to detect a voltage drop in a battery. The values of the A/D conversion result (ADCR register

value) and power-fail comparison threshold register (PFT) are compared. INTAD is generated only when a

comparative condition has been matched.

Figure 10-1. Block Diagram of A/D Converter

AVREF

ADCS bit

ANI0/P20

Sample & hold circuit

ANI1/P21

ANI2/P22

ANI3/P23

Voltage comparator

AVSS

Successive

approximation

register (SAR)

AVSS

INTAD

Controller

Comparator

A/D conversion result

register (ADCR)

Power-fail comparison

threshold register (PFT)

2

ADS1 ADS0

ADCS

FR2

FR1

FR0

ADCE

PFEN PFCM

Power-fail comparison

mode register (PFM)

Analog input channel

specification register

(ADS)

A/D converter mode

register (ADM)

Internal bus

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10.2 Configuration of A/D Converter

The A/D converter includes the following hardware.

Table 10-1. Registers of A/D Converter Used on Software

Item

Registers

Configuration

A/D conversion result register (ADCR)

A/D converter mode register (ADM)

Analog input channel specification register (ADS)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

(1) ANI0 to ANI3 pins

These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into

digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification

register (ADS) can be used as input port pins.

(2) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D

conversion is started, and holds the sampled analog input voltage value during A/D conversion.

(3) Series resistor string

The series resistor string is connected between AV^REFand AVSS, and generates a voltage to be compared with

the analog input signal.

<R>

Figure 10-2. Circuit Configuration of Series Resistor String

AV^REF

P-ch

ADCS

ADCE

Series resistor string

Reference voltage

generator

AV^SS

(4) Voltage comparator

The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor

string.

(5) Successive approximation register (SAR)

This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the

result, starting from the most significant bit (MSB).

When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D

conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).

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(6) A/D conversion result register (ADCR)

The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each

time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits

(the lower 6 bits are fixed to 0).

(7) Controller

When A/D conversion has been completed or when the power-fail detection function is used, this controller

compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison

threshold register (PFT). It generates the interrupt INTAD only if a specified comparison condition is satisfied as

a result.

(8) AV^REFpin

This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential

as that of the V^DDpin even when the A/D converter is not used.

The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AVREF and

AV^SS.

(9) AV^SSpin

This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the V^SS

pin even when the A/D converter is not used.

(10) A/D converter mode register (ADM)

This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the

conversion operation.

(11) Analog input channel specification register (ADS)

This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.

(12) Power-fail comparison mode register (PFM)

This register is used to set the power-fail monitor mode.

(13) Power-fail comparison threshold register (PFT)

This register is used to set the threshold value that is to be compared with the value of the A/D conversion result

register (ADCR).

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10.3 Registers Used in A/D Converter

The A/D converter uses the following five registers.

•

A/D converter mode register (ADM)

Analog input channel specification register (ADS)

A/D conversion result register (ADCR)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

(1) A/D converter mode register (ADM)

This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.

ADM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-3. Format of A/D Converter Mode Register (ADM)

Address: FF28H After reset: 00H R/W

Symbol

<7>

6

0

5

4

3

2

0

1

0

<0>

ADM ADCS

FR2

FR1

FR0

ADCE

ADCS

A/D conversion operation control

0

1

Stops conversion operation

Enables conversion operation

Conversion time selection^{Note 1}

FR2

FR1

FR0

fX

= 10 MHz

fX

= 16 MHz

fX

= 2 MHz

fX = 8.38 MHz

288/f

240/f

192/f

144/f

120/f

X

144

120

96

72

60

48

µ

s

0

1

0

1

0

1

0

1

0

1

0

34.3

µ

s

µ

28.8

µ

s 18

s

µ

28.6

22.9

17.2

14.3

24.0 s 15

µ

s

µ

19.2

14.4

µ

s

12

µ

s

s 9

µ

s

µ

7.5 s

12.0

9.6

µ

s

96/f

X

µ

11.5 s

µ

s

µ

6 s

Other than above

Setting prohibited

ADCE

Boost reference voltage generator operation control^{Note 2}

Stops operation of reference voltage generator

0

1

Enables operation of reference voltage generator

<R>

Notes 1. Set so that the A/D conversion time is as follows.

• Standard products, (A) grade products: 14 µs or longer but less than 100 µs

• (A1) grade products: 14 µs or longer but less than 60 µs

2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that

generates the reference voltage for boosting is controlled by ADCE, and it takes 14 µs from operation

start to operation stabilization. Therefore, when ADCS is set to 1 after 14 µs or more has elapsed from

the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result.

Remark f^X: High-speed system clock oscillation frequency

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Table 10-2. Settings of ADCS and ADCE

ADCS

ADCE

A/D Conversion Operation

0

1

0

1

0

1

Stop status (DC power consumption path does not exist)

Conversion waiting mode (only reference voltage generator consumes power)

Conversion mode (reference voltage generator operation stopped^Note

Conversion mode (reference voltage generator operates)

)

Note Data of first conversion cannot be used.

Figure 10-4. Timing Chart When Boost Reference Voltage Generator Is Used

Boost reference voltage generator: operating

ADCE

Boost reference voltage

Conversion

operation

Conversion

waiting

Conversion

operation

Conversion stopped

ADCS

Note

Note The time from the rising of the ADCE bit to the falling of the ADCS bit must be 14 µs or longer to stabilize

the reference voltage.

Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the

identical data.

2. For the sampling time of the A/D converter and the A/D conversion start delay time, see (11)

in 10.6 Cautions for A/D Converter.

3. If data is written to ADM, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS

FOR WAIT.

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(2) Analog input channel specification register (ADS)

This register specifies the analog voltage input port to be A/D converted.

ADS can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-5. Format of Analog Input Channel Specification Register (ADS)

Address: FF29H After reset: 00H R/W

Symbol

ADS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADS1

ADS0

ADS1

ADS0

Analog input channel specification

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

Cautions 1. Be sure to clear bits 2 to 7 of ADS to 0.

2. If data is written to ADS, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

(3) A/D conversion result register (ADCR)

This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time

A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in

ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion

result, and FF08H indicates the lower 2 bits of the conversion result.

ADCR can be read by a 16-bit memory manipulation instruction.

RESET input makes ADCR undefined.

Figure 10-6. Format of A/D Conversion Result Register (ADCR)

Address: FF08H, FF09H After reset: Undefined

FF09H

R

FF08H

Symbol

ADCR

0

Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel

specification register (ADS), the contents of ADCR may become undefined. Read the

conversion result following conversion completion before writing to ADM and ADS. Using

timing other than the above may cause an incorrect conversion result to be read.

2. If data is read from ADCR, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

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(4) Power-fail comparison mode register (PFM)

The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the

ADCR register) and the value of the power-fail comparison threshold value register (PFT).

PFM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-7. Format of Power-Fail Comparison Mode Register (PFM)

Address: FF2AH After reset: 00H R/W

Symbol

<7>

<6>

5

0

4

0

3

0

2

0

1

0

PFM PFEN

PFCM

PFEN

Power-fail comparison enable

0

1

Stops power-fail comparison (used as a normal A/D converter)

Enables power-fail comparison (used for power-fail detection)

PFCM

Power-fail comparison mode selection

Interrupt request signal (INTAD) generation

Higher 8 bits of

ADCR ≥ PFT

0

1

Higher 8 bits of

ADCR < PFT

No INTAD generation

Higher 8 bits of

ADCR ≥ PFT

Higher 8 bits of

ADCR < PFT

INTAD generation

Caution If data is written to PFM, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS

FOR WAIT.

(5) Power-fail comparison threshold register (PFT)

The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the

values with the A/D conversion result.

8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result.

PFT can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-8. Format of Power-Fail Comparison Threshold Register (PFT)

Address: FF2BH After reset: 00H R/W

Symbol

7

6

5

4

3

2

1

0

PFT PFT7

PFT6

PFT5

PFT4

PFT3

PFT2

PFT1

PFT0

Caution If data is written to PFT, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS

FOR WAIT.

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10.4 A/D Converter Operations

10.4.1 Basic operations of A/D converter

<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).

<2> Set ADCE to 1 and wait for 14 µs or longer.

<3> Set ADCS to 1 and start the conversion operation.

(<4> to <10> are operations performed by hardware.)

<4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.

<5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the

input analog voltage is held until the A/D conversion operation has ended.

<6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to

(1/2) AV^REFby the tap selector.

<7> The voltage difference between the series resistor string voltage tap and analog input is compared by the

voltage comparator. If the analog input is greater than (1/2) AV^REF, the MSB of SAR remains set to 1. If the

analog input is smaller than (1/2) AV^REF, the MSB is reset to 0.

<8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series

resistor string voltage tap is selected according to the preset value of bit 9, as described below.

•

Bit 9 = 1: (3/4) AV^REF

Bit 9 = 0: (1/4) AV^REF

The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.

•

Analog input voltage ≥ Voltage tap: Bit 8 = 1

Analog input voltage < Voltage tap: Bit 8 = 0

<9> Comparison is continued in this way up to bit 0 of SAR.

<10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result

value is transferred to the A/D conversion result register (ADCR) and then latched.

At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.

<11> Repeat steps <4> to <10>, until ADCS is cleared to 0.

To stop the A/D converter, clear ADCS to 0.

To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the

status of ADCE = 0, however, start from <2>.

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Figure 10-9. Basic Operation of A/D Converter

Conversion time

Sampling time

Sampling

A/D converter

operation

A/D conversion

Conversion

result

Undefined

SAR

Conversion

result

ADCR

INTAD

A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)

is reset (0) by software.

If any of ADM, the analog input channel specification register (ADS), power-fail comparison mode register (PFM),

or power-fail comparison threshold register (PFT) is written during an A/D conversion operation, the conversion

operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning.

RESET input makes the A/D conversion result register (ADCR) undefined.

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10.4.2 Input voltage and conversion results

The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical

A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression.

VAIN

SAR = INT (

× 1024 + 0.5)

AV^REF

ADCR = SAR × 64

or

AVREF

(ADCR − 0.5) ×

≤ V^AIN< (ADCR + 0.5) ×

1024

where, INT( ): Function which returns integer part of value in parentheses

V^AIN: Analog input voltage

AV^REF: AVREF pin voltage

ADCR: A/D conversion result register (ADCR) value

SAR:

Successive approximation register

Figure 10-10 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 10-10. Relationship Between Analog Input Voltage and A/D Conversion Result

SAR

ADCR

1023

FFC0H

1022

FF80H

FF40H

00C0H

0080H

0040H

0000H

1021

A/D conversion result

3

2

1

0

1

3

2

5

3

2043 1022 2045 1023 2047

2048 1024 2048 1024 2048

1

2048 1024 2048 1024 2048 1024

Input voltage/AV_REF

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10.4.3 A/D converter operation mode

The operation mode of the A/D converter is the select mode. One analog input channel is selected from ANI0 to

ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.

In addition, the following two functions can be selected by setting bit 7 (PFEN) of the power-fail comparison mode

register (PFM).

•

Normal 10-bit A/D converter (PFEN = 0)

Power-fail detection function (PFEN = 1)

(1) A/D conversion operation (when PFEN = 0)

By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail

comparison mode register (PFM) to 0, A/D conversion of the voltage applied to the analog input pin specified by

the analog input channel specification register (ADS) is started.

When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result

register (ADCR), and an interrupt request signal (INTAD) is generated. Once the next A/D conversion has started

and when one A/D conversion has been completed, the A/D conversion operation after that is immediately started.

The A/D conversion operations are repeated until new data is written to ADS.

If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register

(PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and

restarted from the beginning.

If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the

conversion result is undefined.

Figure 10-11. A/D Conversion Operation

Rewriting ADM

ADCS = 1

Rewriting ADS

ANIn

ADCS = 0

A/D conversion

ANIn

ANIm

Conversion is stopped

Conversion result is not retained

Stopped

ANIn

ANIm

ADCR

INTAD

(PFEN = 0)

Remarks 1. n = 0 to 3

2. m = 0 to 3

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(2) Power-fail detection function (when PFEN = 1)

By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail

comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin

specified by the analog input channel specification register (ADS) is started.

When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion

result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an

interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM.

<1> When PFEN = 1 and PFCM = 0

The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only

generated when the higher 8 bits of ADCR ≥ PFT.

<2> When PFEN = 1 and PFCM = 1

The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only

generated when the higher 8 bits of ADCR < PFT.

Figure 10-12. Power-Fail Detection (When PFEN = 1 and PFCM = 0)

A/D conversion

ANIn

80H

ANIn

7FH

ANIn

80H

Higher 8 bits

of ADCR

PFT

80H

INTAD

(PFEN = 1)

Note

First conversion

Condition match

Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is

replaced by the next conversion result.

Remark n = 0 to 3

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The setting methods are described below.

When used as A/D conversion operation

•

<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.

<2> Select the channel and conversion time using bits 1 and 0 (ADS1 and ADS0) of the analog input channel

specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

<3> Set bit 7 (ADCS) of ADM to 1 and start the A/D conversion operation.

<4> An interrupt request signal (INTAD) is generated.

<5> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<6> Change the channel using bits 1 and 0 (ADS1 and ADS0) of ADS and start the A/D conversion operation.

<7> An interrupt request signal (INTAD) is generated.

<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<9> Clear ADCS to 0.

<10> Clear ADCE to 0.

Cautions 1. Make sure the period of <1> to <3> is 14 µs or more.

2. It is no problem if the order of <1> and <2> is reversed.

3. <1> can be omitted. However, do not use the first conversion result after <3> in this case.

4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.

•

When used as power-fail detection function

<1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM) to 1.

<2> Set power-fail comparison condition using bit 6 (PFCM) of PFM.

<3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.

<4> Select the channel and conversion time using bits 1 and 0 (ADS1 and ADS0) of the analog input channel

specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

<5> Set a threshold value to the power-fail comparison threshold register (PFT).

<6> Set bit 7 (ADCS) of ADM to 1.

<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<8> The higher 8 bits of ADCR and PFT are compared and an interrupt request signal (INTAD) is generated

if the conditions match.

<9> Change the channel using bits 1 and 0 (ADS1 and ADS0) of ADS.

<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<11> The higher 8 bits of ADCR and the power-fail comparison threshold register (PFT) are compared and an

interrupt request signal (INTAD) is generated if the conditions match.

<12> Clear ADCS to 0.

<13> Clear ADCE to 0.

Cautions 1. Make sure the period of <3> to <6> is 14 µs or more.

2. It is no problem if the order of <3>, <4>, and <5> is changed.

3. <3> must not be omitted if the power-fail function is used.

4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.

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10.5 How to Read A/D Converter Characteristics Table

Here, special terms unique to the A/D converter are explained.

(1) Resolution

This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input

voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the

full scale is expressed by %FSR (Full Scale Range).

1LSB is as follows when the resolution is 10 bits.

1LSB = 1/2¹⁰= 1/1024

= 0.098%FSR

Accuracy has no relation to resolution, but is determined by overall error.

(2) Overall error

This shows the maximum error value between the actual measured value and the theoretical value.

Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of

these express the overall error.

Note that the quantization error is not included in the overall error in the characteristics table.

(3) Quantization error

When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an

analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot

be avoided.

Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral

linearity error, and differential linearity error in the characteristics table.

Figure 10-13. Overall Error

Figure 10-14. Quantization Error

……

1

……

1

Ideal line

Overall

error

Quantization error

1/2LSB

……

0

……

0

AV^REF

0

AVREF

Analog input

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(4) Zero-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (1/2LSB) when the digital output changes from 0......000 to 0......001.

If the actual measurement value is greater than the theoretical value, it shows the difference between the actual

measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output

changes from 0……001 to 0……010.

(5) Full-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.

(6) Integral linearity error

This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It

expresses the maximum value of the difference between the actual measurement value and the ideal straight line

when the zero-scale error and full-scale error are 0.

(7) Differential linearity error

While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value

and the ideal value.

Figure 10-15. Zero-Scale Error

Figure 10-16. Full-Scale Error

111

Full-scale error

Ideal line

011

111

110

010

001

101

000

Ideal line

Zero-scale error

000

0

AVREF–3 AVREF–2 AVREF–1 AVREF

0

1

2

3

AV^REF

Analog input (LSB)

Figure 10-17. Integral Linearity Error

Figure 10-18. Differential Linearity Error

……

1

……

1

Ideal 1LSB width

Ideal line

Differential

linearity error

Integral linearity

error

……

0 0

……

0

AVREF

0

Analog input

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(8) Conversion time

This expresses the time since sampling has been started until digital output is obtained.

The sampling time is included in the conversion time in the characteristics table.

(9) Sampling time

This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.

Sampling

time

Conversion time

10.6 Cautions for A/D Converter

(1) Operating current in standby mode

The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by

clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 (see Figure 10-2).

<R>

(2) Input range of ANI0 to ANI3

Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV^REFor higher and AVSS or lower

(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that

channel becomes undefined. In addition, the converted values of the other channels may also be affected.

(3) Conflicting operations

<1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end

of conversion

ADCR read has priority. After the read operation, the new conversion result is written to ADCR.

<2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel

specification register (ADS) write upon the end of conversion

ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal

(INTAD) generated.

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(4) Noise countermeasures

To maintain the 10-bit resolution, attention must be paid to noise input to the AV^REFand ANI0 to ANI3 pins.

Because the effect increases in proportion to the output impedance of the analog input source, it is recommended

that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise.

Figure 10-19. Analog Input Pin Connection

If there is a possibility that noise equal to or higher than AV^REFor

equal to or lower than AV^SSmay enter, clamp with a diode with a

small V value (0.3 V or lower).

F

Reference

voltage

input

AV^REF

ANI0 to ANI3

C = 100 to 1,000 pF

AVSS

VSS

(5) ANI0/P20 to ANI3/P23

<1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).

When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while

conversion is in progress; otherwise the conversion resolution may be degraded.

<2> If a digital pulse is applied to the pins adjacent to the pins currently being used for A/D conversion, the

expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a

pulse to the pins adjacent to the pin undergoing A/D conversion.

(6) Input impedance of ANI0 to ANI3 pins

In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth

of the conversion time.

Since only the leakage current flows other than during sampling and the current for charging the capacitor also

flows during sampling, the input impedance fluctuates and has no meaning.

To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input

source 10 kΩ or lower, or connect a capacitor of around 100 pF to the ANI0 to ANI3 pins (see Figure 10-19).

(7) AV^REFpin input impedance

A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins.

Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to

the series resistor string between the AV^REFand AVSS pins, resulting in a large reference voltage error.

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(8) Interrupt request flag (ADIF)

The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is

changed.

Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the

pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,

when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-

change analog input has not finished.

When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.

Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation

ADS rewrite

(start of ANIn conversion)

ADS rewrite

(start of ANIm conversion)

ADIF is set but ANIm conversion

has not finished.

A/D conversion

ANIn

ANIm

ANIn

ANIm

ADCR

ADIF

ANIn

ANIm

Remarks 1. n = 0 to 3

2. m = 0 to 3

(9) Conversion results just after A/D conversion start

The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the

ADCS bit is set to 1 within 14 µs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =

0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first

conversion result.

(10) A/D conversion result register (ADCR) read operation

When a write operation is performed to the A/D converter mode register (ADM) and analog input channel

specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following

conversion completion before writing to ADM and ADS. Using a timing other than the above may cause an

incorrect conversion result to be read.

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(11) A/D converter sampling time and A/D conversion start delay time

The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM). A

delay time exists until actual sampling is started after A/D converter operation is enabled.

When using a set in which the A/D conversion time must be strictly observed, care is required regarding the

contents shown in Figure 10-21 and Table 10-3.

Figure 10-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay

ADCS ← 1 or ADS rewrite

ADCS

Sampling timing

INTAD

Wait

A/D

Sampling

time

Sampling

time

period conversion

start delay

time

Conversion time

Table 10-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)

FR2

FR1

FR0

Conversion Time

Sampling Time

A/D Conversion Start Delay Time^Note

MIN.

MAX.

0

1

0

1

0

1

0

1

0

1

0

288/fX

240/fX

192/fX

144/fX

120/fX

96/fX

40/fX

32/fX

28/fX

24/fX

16/fX

14/fX

12/fX

36/fX

32/fX

28/fX

18/fX

16/fX

14/fX

32/fX

24/fX

20/fX

16/fX

12/fX

Other than above

Setting prohibited

−

Note The A/D conversion start delay time is the time after the wait period. For the wait function, see CHAPTER 27

CAUTIONS FOR WAIT.

Remark f^X: High-speed system oscillation frequency

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CHAPTER 10 A/D CONVERTER

(12) Internal equivalent circuit

The equivalent circuit of the analog input block is shown below.

Figure 10-22. Internal Equivalent Circuit of ANIn Pin

R1

R2

ANIn

C1

C2

C3

Table 10-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)

AVREF

2.7 V

4.5 V

R1

R2

C1

C2

C3

12 kΩ

4 kΩ

8 kΩ

8 pF

3 pF

0.6 pF

2.7 kΩ

1.4 pF

Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values.

2. n = 0 to 3

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CHAPTER 11 SERIAL INTERFACE UART0 (µPD78F0102H AND 78F0103H ONLY)

11.1 Functions of Serial Interface UART0

Serial interface UART0 has the following two modes.

(1) Operation stop mode

This mode is used when serial communication is not executed and can enable a reduction in the power

consumption.

For details, see 11.4.1 Operation stop mode.

(2) Asynchronous serial interface (UART) mode

The functions of this mode are outlined below.

For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate

generator.

•

Two-pin configuration T^XD0: Transmit data output pin

R^XD0: Receive data input pin

•

Length of communication data can be selected from 7 or 8 bits.

Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set

Transmission and reception can be performed independently.

Four operating clock inputs selectable

Fixed to LSB-first communication

Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The T^XD0 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.

2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start

communication.

3. TXE0 and RXE0 are synchronized by the base clock (f^XCLK0) set by BRGC0. To enable

transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock

after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base

clock, the transmission circuit or reception circuit may not be initialized.

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11.2 Configuration of Serial Interface UART0

Serial interface UART0 includes the following hardware.

Table 11-1. Configuration of Serial Interface UART0

Item

Registers

Configuration

Receive buffer register 0 (RXB0)

Receive shift register 0 (RXS0)

Transmit shift register 0 (TXS0)

Control registers

Asynchronous serial interface operation mode register 0 (ASIM0)

Asynchronous serial interface reception error status register 0 (ASIS0)

Baud rate generator control register 0 (BRGC0)

Port mode register 1 (PM1)

Port register 1 (P1)

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(1) Receive buffer register 0 (RXB0)

This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).

Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift

register 0 (RXS0).

If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is

always 0.

If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.

RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.

RESET input or POWER0 = 0 sets this register to FFH.

(2) Receive shift register 0 (RXS0)

This register converts the serial data input to the R^XD0 pin into parallel data.

RXS0 cannot be directly manipulated by a program.

(3) Transmit shift register 0 (TXS0)

This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is

transmitted from the T^XD0 pin.

TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.

RESET input, POWER0 = 0, or TXE0 = 0 sets this register to FFH.

Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal

(INTST0) is generated.

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11.3 Registers Controlling Serial Interface UART0

Serial interface UART0 is controlled by the following five registers.

•

Asynchronous serial interface operation mode register 0 (ASIM0)

Asynchronous serial interface reception error status register 0 (ASIS0)

Baud rate generator control register 0 (BRGC0)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Asynchronous serial interface operation mode register 0 (ASIM0)

This 8-bit register controls the serial communication operations of serial interface UART0.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)

Address: FF70H After reset: 01H R/W

Symbol

ASIM0

<7>

<6>

<5>

4

3

2

1

0

1

POWER0

TXE0

RXE0

PS01

PS00

CL0

SL0

POWER0

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

Enables operation of the internal operation clock.

.

1

TXE0

Enables/disables transmission

0

1

Disables transmission (synchronously resets the transmission circuit).

Enables transmission.

RXE0

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Enables reception.

0

1

Notes 1. The input from the R^XD0 pin is fixed to high level when POWER0 = 0.

2. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),

and receive buffer register 0 (RXB0) are reset.

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Figure 11-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)

PS01

PS00

Transmission operation

Does not output parity bit.

Reception operation

Reception without parity

0

1

0

1

0

1

Outputs 0 parity.

Reception as 0 parity^Note

Judges as odd parity.

Judges as even parity.

Outputs odd parity.

Outputs even parity.

CL0

0

Specifies character length of transmit/receive data

Character length of data = 7 bits

Character length of data = 8 bits

1

SL0

0

Specifies number of stop bits of transmit data

Number of stop bits = 1

Number of stop bits = 2

1

Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial

interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.

Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0,

and then clear POWER0 to 0.

2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0,

and then clear POWER0 to 0.

3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If

POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.

4. TXE0 and RXE0 are synchronized by the base clock (f^XCLK0) set by BRGC0. To enable

transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after

TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,

the transmission circuit or reception circuit may not be initialized.

5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.

6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with

“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.

7. Be sure to set bit 0 to 1.

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(2) Asynchronous serial interface reception error status register 0 (ASIS0)

This register indicates an error status on completion of reception by serial interface UART0. It includes three

error flag bits (PE0, FE0, OVE0).

This register is read-only by an 8-bit memory manipulation instruction.

RESET input, bit 7 (POWER0) = 0, or bit 5 (RXE0) of ASIM0 = 0 clears this register to 00H. 00H is read when

this register is read.

Figure 11-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)

Address: FF73H After reset: 00H R

Symbol

ASIS0

7

0

6

0

5

0

4

0

3

0

2

1

0

PE0

FE0

OVE0

PE0

0

Status flag indicating parity error

If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.

1

If the parity of transmit data does not match the parity bit on completion of reception.

FE0

0

Status flag indicating framing error

If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.

If the stop bit is not detected on completion of reception.

1

OVE0

Status flag indicating overrun error

0

1

If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.

If receive data is set to the RXB0 register and the next reception operation is completed before the

data is read.

Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of

asynchronous serial interface operation mode register 0 (ASIM0).

2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of

stop bits.

3. If an overrun error occurs, the next receive data is not written to receive buffer register 0

(RXB0) but discarded.

4. If data is read from ASIS0, a wait cycle is generated. For details, see CHAPTER 27 CAUTIONS

FOR WAIT.

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(3) Baud rate generator control register 0 (BRGC0)

This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.

BRGC0 can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 1FH.

Figure 11-4. Format of Baud Rate Generator Control Register 0 (BRGC0)

Address: FF71H After reset: 1FH R/W

Symbol

BRGC0

7

6

5

0

4

3

2

1

0

TPS01

TPS00

MDL04

MDL03

MDL02

MDL01

MDL00

TPS01

TPS00

Base clock (fXCLK0) selection^{Note 1}

0

1

0

1

0

1

TM50 output^{Note 2}

fX/2 (5 MHz)

fX/2³(1.25 MHz)

fX/2⁵(312.5 kHz)

MDL04

MDL03

MDL02

MDL01

MDL00

k

Selection of 5-bit counter

output clock

0

1

×

0

×

0

1

×

0

1

0

×

8

Setting prohibited

fXCLK0/8

9

fXCLK0/9

10

fXCLK0/10

•

1

0

1

0

1

0

1

0

1

0

1

26

27

28

29

30

31

fXCLK0/26

fXCLK0/27

fXCLK0/28

fXCLK0/29

fXCLK0/30

fXCLK0/31

Notes 1. Be sure to set the base clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Base clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Base clock ≤ 8.38 MHz

• V^DD= 2.7 to 3.3 V: Base clock ≤ 5 MHz

<R>

• V^DD= 2.5 to 2.7 V: Base clock ≤ 2.5 MHz (standard products, (A) grade products only)

2. Note the following points when selecting the TM50 output as the base clock.

• PWM mode (TMC506 = 1)

Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty

= 50%.

• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)

Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion

operation (TMC501 = 1).

It is not necessary to enable the TO50 pin as a timer output pin in any mode.

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Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the base clock is

the internal oscillation clock, the operation of serial interface UART0 is not guaranteed.

2. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the

MDL04 to MDL00 bits.

3. The baud rate value is the output clock of the 5-bit counter divided by 2.

Remarks 1. f^XCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits

2. fX: High-speed system clock oscillation frequency

3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)

4. ×: Don’t care

5. Figures in parentheses apply to operation at f^X= 10 MHz

6. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)

TMC501: Bit 1 of TMC50

(4) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of

P10 to 1.

Set PM11 to 1 when using the P11/RxD0/SI10 pin as a serial interface data input pin. The output latch of P11 at

this time may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 11-5. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

6

5

4

3

2

1

0

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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11.4 Operation of Serial Interface UART0

Serial interface UART0 has the following two modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

11.4.1 Operation stop mode

In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the

pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0,

TXE0, and RXE0) of ASIM0 to 0.

(1) Register used

The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).

ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Address: FF70H After reset: 01H R/W

Symbol

ASIM0

<7>

<6>

<5>

4

3

2

1

0

1

POWER0

TXE0

RXE0

PS01

PS00

CL0

SL0

POWER0

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

.

TXE0

0

Enables/disables transmission

Disables transmission (synchronously resets the transmission circuit).

RXE0

0

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Notes 1. The input from the R^XD0 pin is fixed to high level when POWER0 = 0.

2. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),

and receive buffer register 0 (RXB0) are reset.

Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.

To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1.

Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 4

PORT FUNCTIONS.

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11.4.2 Asynchronous serial interface (UART) mode

In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed.

A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of

baud rates.

(1) Registers used

• Asynchronous serial interface operation mode register 0 (ASIM0)

• Asynchronous serial interface reception error status register 0 (ASIS0)

• Baud rate generator control register 0 (BRGC0)

• Port mode register 1 (PM1)

• Port register 1 (P1)

The basic procedure of setting an operation in the UART mode is as follows.

<1> Set the BRGC0 register (see Figure 11-4).

<2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 11-2).

<3> Set bit 7 (POWER0) of the ASIM0 register to 1.

<4> Set bit 6 (TXE0) of the ASIM0 register to 1. → Transmission is enabled.

Set bit 5 (RXE0) of the ASIM0 register to 1. → Reception is enabled.

<5> Write data to the TXS0 register. → Data transmission is started.

Caution Take relationship with the other party of communication when setting the port mode register

and port register.

The relationship between the register settings and pins is shown below.

Table 11-2. Relationship Between Register Settings and Pins

POWER0 TXE0

RXE0

PM10

P10

PM11

P11

UART0

Pin Function

TxD0/SCK10/P10

Operation

RxD0/SI10/P11

SI10/P11

RxD0

Note

0

1

0

1

0

1

0

1

×

Stop

SCK10/P10

TxD0

Note

×

1

×

Reception

Transmission

Note

0

1

×

SI10/P11

RxD0

1

×

Transmission/

reception

TxD0

Note Can be set as port function.

Remark ×:

don’t care

POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)

TXE0:

RXE0:

PM1×:

P1×:

Bit 6 of ASIM0

Bit 5 of ASIM0

Port mode register

Port output latch

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(2) Communication operation

(a) Format and waveform example of normal transmit/receive data

Figures 11-6 and 11-7 show the format and waveform example of the normal transmit/receive data.

Figure 11-6. Format of Normal UART Transmit/Receive Data

1 data frame

Start

bit

Parity

bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop bit

Character bits

One data frame consists of the following bits.

• Start bit ... 1 bit

• Character bits ... 7 or 8 bits (LSB first)

• Parity bit ... Even parity, odd parity, 0 parity, or no parity

• Stop bit ... 1 or 2 bits

The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial

interface operation mode register 0 (ASIM0).

Figure 11-7. Example of Normal UART Transmit/Receive Data Waveform

1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

Parity

Stop

3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

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(b) Parity types and operation

The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used

on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error

can be detected. With zero parity and no parity, an error cannot be detected.

(i) Even parity

• Transmission

Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.

The value of the parity bit is as follows.

If transmit data has an odd number of bits that are “1”:

1

If transmit data has an even number of bits that are “1”: 0

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a

parity error occurs.

(ii) Odd parity

• Transmission

Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that

are “1” is odd.

If transmit data has an odd number of bits that are “1”:

0

If transmit data has an even number of bits that are “1”: 1

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a

parity error occurs.

(iii) 0 parity

The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.

The parity bit is not detected when the data is received. Therefore, a parity error does not occur

regardless of whether the parity bit is “0” or “1”.

(iv) No parity

No parity bit is appended to the transmit data.

Reception is performed assuming that there is no parity bit when data is received. Because there is no

parity bit, a parity error does not occur.

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(c) Transmission

The T^XD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode

register 0 (ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled.

Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity

bit, and stop bit are automatically appended to the data.

When transmission is started, the start bit is output from the T^XD0 pin, followed by the rest of the data in

order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are

appended and a transmission completion interrupt request (INTST0) is generated.

Transmission is stopped until the data to be transmitted next is written to TXS0.

Figure 11-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt

occurs as soon as the last stop bit has been output.

Caution After transmit data is written to TXS0, do not write the next transmit data before the

transmission completion interrupt signal (INTST0) is generated.

Figure 11-8. Transmission Completion Interrupt Request Timing

1. Stop bit length: 1

Parity

TXD0 (output)

Start

D0

D1

D2

D6

D7

Stop

INTST0

2. Stop bit length: 2

TXD0 (output)

Start

D0

D1

D2

D6

D7

Parity

Stop

INTST0

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(d) Reception

Reception is enabled and the R^XD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial

interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.

The 5-bit counter of the baud rate generator starts counting when the falling edge of the R^XD0 pin input is

detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the

R^XD0 pin input is sampled again ( in Figure 11-9). If the RXD0 pin is low level at this time, it is recognized

as a start bit.

When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift

register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion

interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an

overrun error (OVE0) occurs, however, the receive data is not written to RXB0.

Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception

position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception.

Figure 11-9. Reception Completion Interrupt Request Timing

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

RX

D0 (input)

INTSR0

RXB0

Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

2. Reception is always performed with the “number of stop bits = 1”. The second stop bit

is ignored.

3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0)

before reading RXB0.

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(e) Reception error

Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error

flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data

reception, a reception error interrupt request (INTSR0) is generated.

Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception

error interrupt servicing (INTSR0) (see Figure 11-3).

The contents of ASIS0 are reset to 0 when ASIS0 is read.

Table 11-3. Cause of Reception Error

Reception Error

Parity error

Cause

The parity specified for transmission does not match the parity of the

receive data.

Framing error

Overrun error

Stop bit is not detected.

Reception of the next data is completed before data is read from

receive buffer register 0 (RXB0).

(f) Noise filter of receive data

The R^XD0 signal is sampled using the base clock output by the prescaler block.

If two sampled values are the same, the output of the match detector changes, and the data is sampled as

input data.

Because the circuit is configured as shown in Figure 11-10, the internal processing of the reception operation

is delayed by two clocks from the external signal status.

Figure 11-10. Noise Filter Circuit

Base clock

Internal signal A

R

X

D0/SI10/P11

Internal signal B

In

Q

In

Q

LD_EN

Match detector

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CHAPTER 11 SERIAL INTERFACE UART0 (µPD78F0102H AND 78F0103H ONLY)

11.4.3 Dedicated baud rate generator

The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and

generates a serial clock for transmission/reception of UART0.

Separate 5-bit counters are provided for transmission and reception.

(1) Configuration of baud rate generator

•

Base clock

The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is

supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0

(ASIM0) is 1. This clock is called the base clock and its frequency is called f^XCLK0. The base clock is fixed

to low level when POWER0 = 0.

Transmission counter

This counter stops, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface

operation mode register 0 (ASIM0) is 0.

It starts counting when POWER0 = 1 and TXE0 = 1.

The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).

Reception counter

This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial

interface operation mode register 0 (ASIM0) is 0.

It starts counting when the start bit has been detected.

The counter stops operation after one frame has been received, until the next start bit is detected.

Figure 11-11. Configuration of Baud Rate Generator

POWER0

Baud rate generator

fX/2

POWER0, TXE0 (or RXE0)

fX

/2³

Selector

5-bit counter

fXCLK0

fX

/2⁵

8-bit timer/

event counter

50 output

Match detector

Baud rate

1/2

BRGC0: TPS01, TPS00

BRGC0: MDL04 to MDL00

Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)

TXE0:

Bit 6 of ASIM0

RXE0:

BRGC0:

Bit 5 of ASIM0

Baud rate generator control register 0

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(2) Generation of serial clock

A serial clock can be generated by using baud rate generator control register 0 (BRGC0).

Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.

Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.

(a) Baud rate

The baud rate can be calculated by the following expression.

f^XCLK0

• Baud rate =

[bps]

2 × k

f^XCLK0:

Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register

Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)

k:

(b) Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Cautions 1. Keep the baud rate error during transmission to within the permissible error range at

the reception destination.

2. Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz

Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16)

Target baud rate = 76,800 bps

Baud rate = 2.5 M/(2 × 16)

= 2,500,000/(2 × 16) = 78125 [bps]

Error = (78,125/76,800 − 1) × 100

= 1.725 [%]

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(3) Example of setting baud rate

Table 11-4. Set Data of Baud Rate Generator

Baud Rate

[bps]

fX = 10.0 MHz

fX = 8.38 MHz

fX = 4.19 MHz

TPS01,

TPS00

k

Calculated ERR[%] TPS01,

k

Calculated ERR[%] TPS01,

k

Calculated ERR[%]

Value

TPS00

Value

TPS00

Value

2425

4676

9699

10475

18705

−

2400

4800

−

3

2

1

−

3

2

1

−

3

2

−

2

1

−

27

14

27

25

14

−

1.03

−2.58

1.03

0.72

−2.58

−

27

14

13

27

17

14

27

18

14

9

4850

1.03

9600

16

15

8

9766

1.73

0.16

1.73

0

9353

−2.58

−3.15

1.03

10400

19200

31250

38400

76800

115200

153600

230400

10417

19531

31250

39063

78125

113636

156250

227273

10072

19398

30809

38796

77593

116389

149643

232778

20

16

8

−1.41

−2.58

1.03

1.73

−1.36

1.73

−1.36

27

14

9

38796

74821

116389

−

1.03

−2.58

1.03

−

22

16

11

1.03

−2.58

1.03

−

Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock

(f^XCLK0))

k:

Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)

High-speed system clock oscillation frequency

Baud rate error

f^X:

ERR:

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(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 11-12. Permissible Baud Rate Range During Reception

Latch timing

Data frame length

Start bit

Bit 0

FL

Bit 1

Bit 7

Parity bit

Stop bit

of UART0

1 data frame (11 × FL)

Minimum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmin

Maximum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmax

As shown in Figure 11-12, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

1

FL = (Brate)⁻

Brate: Baud rate of UART0

k:

Set value of BRGC0

1-bit data length

FL:

Margin of latch timing: 2 clocks

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21k + 2

2k

k − 2

2k

Minimum permissible data frame length: FLmin = 11 × FL −

× FL =

FL

Therefore, the maximum receivable baud rate at the transmission destination is as follows.

22k

1

BRmax = (FLmin/11)⁻

=

Brate

21k + 2

Similarly, the maximum permissible data frame length can be calculated as follows.

10

11

k + 2

21k − 2

2 × k

× FLmax = 11 × FL −

× FL =

FL

2 × k

21k − 2

20k

FLmax =

FL × 11

Therefore, the minimum receivable baud rate at the transmission destination is as follows.

20k

1

BRmin = (FLmax/11)⁻

=

Brate

21k − 2

The permissible baud rate error between UART0 and the transmission destination can be calculated from the

above minimum and maximum baud rate expressions, as follows.

Table 11-5. Maximum/Minimum Permissible Baud Rate Error

Division Ratio (k)

Maximum Permissible Baud Rate Error

Minimum Permissible Baud Rate Error

8

+3.53%

+4.14%

+4.34%

+4.44%

−3.61%

−4.19%

−4.38%

−4.47%

16

24

31

Remarks 1. The permissible reception error depends on the number of bits in one frame, input clock

frequency, and division ratio (k). The higher the input clock frequency and the higher the division

ratio (k), the higher the permissible reception error.

2. k: Set value of BRGC0

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CHAPTER 12 SERIAL INTERFACE UART6

12.1 Functions of Serial Interface UART6

Serial interface UART6 has the following two modes.

(1) Operation stop mode

This mode is used when serial communication is not executed and can enable a reduction in the power

consumption.

For details, see 12.4.1 Operation stop mode.

(2) Asynchronous serial interface (UART) mode

This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.

For details, see 12.4.2 Asynchronous serial interface (UART) mode and 12.4.3 Dedicated baud rate

generator.

•

Two-pin configuration T^XD6: Transmit data output pin

R^XD6: Receive data input pin

•

Data length of communication data can be selected from 7 or 8 bits.

Dedicated internal 8-bit baud rate generator allowing any baud rate to be set

Transmission and reception can be performed independently.

Twelve operating clock inputs selectable

MSB- or LSB-first communication selectable

Inverted transmission operation

Synchronous break field transmission from 13 to 20 bits selectable

More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided).

Cautions 1. The T^XD6 output inversion function inverts only the transmission side and not the reception

side. To use this function, the reception side must be ready for reception of inverted data.

2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The T^XD6 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.

3. If data is continuously transmitted, the communication timing from the stop bit to the next

start bit is extended two operating clocks of the macro. However, this does not affect the

result of communication because the reception side initializes the timing when it has

detected a start bit. Do not use the continuous transmission function if the interface is

incorporated in LIN.

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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication

protocol intended to aid the cost reduction of an automotive network.

LIN communication is single-master communication, and up to 15 slaves can be connected to one

master.

The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the

LIN master via the LIN network.

Normally, the LIN master is connected to a network such as CAN (Controller Area Network).

In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that

complies with ISO9141.

In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and

corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave

is 15% or less.

Figures 12-1 and 12-2 outline the transmission and reception operations of LIN.

Figure 12-1. LIN Transmission Operation

Wakeup

signal frame

Synchronous

break field

Synchronous

field

Identifier

field

Data field

Data field Checksum

field

Sleep

bus

13-bit^{Note 2}SBF

transmission

55H

Data

8 bits^{Note 1}

transmission transmissiontransmissiontransmissiontransmission

TX6

Note 3

INTST6

Notes 1. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.

2. The synchronous break field is output by hardware. The output width is the bit length set by bits 4 to 2

(SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 12.4.2 (2) (h) SBF

transmission).

3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.

Remark The interval between each field is controlled by software.

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Figure 12-2. LIN Reception Operation

Wakeup

signal frame

Synchronous

break field

Synchronous Identifier Data field Data field Checksum

field

Sleep

bus

SF

reception

ID

Data

reception reception reception reception^{Note 5}

13 bits^{Note 2}

SBF

reception

RX6

Disable

Enable

Note 3

Reception interrupt

(INTSR6)

Note 1

Edge detection

(INTP0)

Note 4

Enable

Capture timer

Disable

Notes 1. The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception

mode.

2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or

more has been detected, it is assumed that SBF reception has been completed correctly, and an

interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is

assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF

reception mode is restored.

3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception

completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed,

and error detection processing of UART communication and data transfer of the shift register and

RXB6 is not performed. The shift register holds the reset value FFH.

4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF

reception, and then re-set baud rate generator control register 6 (BRGC6).

5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6

after reception of the checksum field and to set the SBF reception mode again.

To perform a LIN receive operation, use a configuration like the one shown in Figure 12-3.

The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt

(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external

event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.

The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit

timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.

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Figure 12-3. Port Configuration for LIN Reception Operation

Selector

P14/RxD6

P120/INTP0

P00/TI000

RXD6 input

Port mode

(PM14)

Output latch

(P14)

Selector

INTP0 input

Port mode

(PM120)

Port input

switch control

(ISC0)

Output latch

(P120)

<ISC0>

0: Select INTP0 (P120)

1: Select RxD6 (P14)

Selector

TI000 input

Port mode

(PM00)

Port input

switch control

(ISC1)

Output latch

(P00)

<ISC1>

0: Select TI000 (P00)

1: Select RxD6 (P14)

Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 12-11)

The peripheral functions used in the LIN communication operation are shown below.

• External interrupt (INTP0); wakeup signal detection

Use: Detects the wakeup signal edges and detects start of communication.

• 16-bit timer/event counter 00 (TI000); baud rate error detection

Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the

sync field (SF) length and divides it by the number of bits.

• Serial interface UART6

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12.2 Configuration of Serial Interface UART6

Serial interface UART6 includes the following hardware.

Table 12-1. Configuration of Serial Interface UART6

Item

Registers

Configuration

Receive buffer register 6 (RXB6)

Receive shift register 6 (RXS6)

Transmit buffer register 6 (TXB6)

Transmit shift register 6 (TXS6)

Control registers

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 1 (PM1)

Port register 1 (P1)

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(1) Receive buffer register 6 (RXB6)

This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).

Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift

register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.

•

In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.

In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.

If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.

RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.

RESET input sets this register to FFH.

(2) Receive shift register 6 (RXS6)

This register converts the serial data input to the R^XD6 pin into parallel data.

RXS6 cannot be directly manipulated by a program.

(3) Transmit buffer register 6 (TXB6)

This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.

This register can be read or written by an 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission

status register 6 (ASIF6) is 1.

2. Do not refresh (write the same value to) TXB6 by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation

mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).

(4) Transmit shift register 6 (TXS6)

This register transmits the data transferred from TXB6 from the T^XD6 pin as serial data. Data is transferred from

TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one

frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the T^XD6

pin at the falling edge of the base clock.

TXS6 cannot be directly manipulated by a program.

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12.3 Registers Controlling Serial Interface UART6

Serial interface UART6 is controlled by the following nine registers.

•

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Asynchronous serial interface operation mode register 6 (ASIM6)

This 8-bit register controls the serial communication operations of serial interface UART6.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)

Address: FF50H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

Enables operation of the internal operation clock

.

1^{Note 3}

TXE6

Enables/disables transmission

0

1

Disables transmission (synchronously resets the transmission circuit).

Enables transmission

Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when

POWER6 = 0.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the

POWER6 bit.

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Figure 12-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)

RXE6

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Enables reception

0

1

PS61

PS60

Transmission operation

Does not output parity bit.

Reception operation

Reception without parity

0

1

0

1

0

1

Outputs 0 parity.

Reception as 0 parity^Note

Judges as odd parity.

Judges as even parity.

Outputs odd parity.

Outputs even parity.

CL6

0

Specifies character length of transmit/receive data

Character length of data = 7 bits

Character length of data = 8 bits

1

SL6

0

Specifies number of stop bits of transmit data

Number of stop bits = 1

Number of stop bits = 2

1

ISRM6

Enables/disables occurrence of reception completion interrupt in case of error

“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).

“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).

0

1

Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial

interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.

Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0

and then clear POWER6 to 0.

2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0

and then clear POWER6 to 0.

3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If

POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.

4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.

5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.

6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the

number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.

7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.

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(2) Asynchronous serial interface reception error status register 6 (ASIS6)

This register indicates an error status on completion of reception by serial interface UART6. It includes three

error flag bits (PE6, FE6, OVE6).

This register is read-only by an 8-bit memory manipulation instruction.

RESET input, bit 7 (POWER6) = 0, or bit 5 (RXE6) of ASIM6 = 0 clears this register to 00H. 00H is read when

this register is read.

Figure 12-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)

Address: FF53H After reset: 00H R

Symbol

ASIS6

7

0

6

0

5

0

4

0

3

0

2

1

0

PE6

FE6

OVE6

PE6

0

Status flag indicating parity error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

1

If the parity of transmit data does not match the parity bit on completion of reception

FE6

0

Status flag indicating framing error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If the stop bit is not detected on completion of reception

1

OVE6

Status flag indicating overrun error

0

1

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If receive data is set to the RXB6 register and the next reception operation is completed before the

data is read.

Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of

asynchronous serial interface operation mode register 6 (ASIM6).

2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop

bits.

3. If an overrun error occurs, the next receive data is not written to receive buffer register 6

(RXB6) but discarded.

4. If data is read from ASIS6, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

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(3) Asynchronous serial interface transmission status register 6 (ASIF6)

This register indicates the status of transmission by serial interface UART6. It includes two status flag bits

(TXBF6 and TXSF6).

Transmission can be continued without disruption even during an interrupt period, by writing the next data to the

TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.

This register is read-only by an 8-bit memory manipulation instruction.

RESET input, bit 7 (POWER6) = 0, or bit 6 (TXE6) of ASIM6 = 0 clears this register to 00H.

Figure 12-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)

Address: FF55H After reset: 00H R

Symbol

ASIF6

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TXBF6

TXSF6

TXBF6

Transmit buffer data flag

0

1

If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)

If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)

TXSF6

0

Transmit shift register data flag

If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6

(TXB6) after completion of transfer

1

If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)

Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

2. To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

transmit data cannot be guaranteed.

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(4) Clock selection register 6 (CKSR6)

This register selects the base clock of serial interface UART6.

CKSR6 can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 12-8. Format of Clock Selection Register 6 (CKSR6)

Address: FF56H After reset: 00H R/W

Symbol

CKSR6

7

0

6

0

5

0

4

0

3

2

1

0

TPS63

TPS62

TPS61

TPS60

TPS63

TPS62

TPS61

TPS60

Base clock (fXCLK6) selection^{Note 1}

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

fX/2⁶(156.25 kHz)

fX/2⁷(78.13 kHz)

fX/2⁸(39.06 kHz)

fX/2⁹(19.53 kHz)

fX/2¹⁰(9.77 kHz)

TM50 output^{Note 2}

Setting prohibited

Other than above

Notes 1. Be sure to set the base clock so that the following condition is satisfied.

• V^DD= 4.0 to 5.5 V: Base clock ≤ 10 MHz

• V^DD= 3.3 to 4.0 V: Base clock ≤ 8.38 MHz

• V^DD= 2.7 to 3.3 V: Base clock ≤ 5 MHz

<R>

• VDD = 2.5 to 2.7 V: Base clock ≤ 2.5 MHz (standard products, (A) grade products only)

2. Note the following points when selecting the TM50 output as a base clock.

• PWM mode (TMC506 = 1)

Start the operation of 8-bit timer/event counter 50 first and then set the base clock to make the duty

= 50%.

• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)

Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion

operation (TMC501 = 1).

It is not necessary to enable the TO50 pin as a timer output pin in any mode.

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Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the base clock is

the internal oscillation clock, the operation of serial interface UART6 is not guaranteed.

2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.

Remarks 1. Figures in parentheses are for operation with f^X= 10 MHz

2. f^X: High-speed system clock oscillation frequency

3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)

TMC501: Bit 1 of TMC50

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(5) Baud rate generator control register 6 (BRGC6)

This register sets the division value of the 8-bit counter of serial interface UART6.

BRGC6 can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 12-9. Format of Baud Rate Generator Control Register 6 (BRGC6)

Address: FF57H After reset: FFH R/W

Symbol

BRGC6

7

6

5

4

3

2

1

0

MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60

k

Output clock selection of

8-bit counter

0

1

×

0

×

0

1

×

0

1

0

×

8

Setting prohibited

fXCLK6/8

9

fXCLK6/9

10

fXCLK6/10

•

1

0

1

0

1

0

1

252 fXCLK6/252

253 fXCLK6/253

254 fXCLK6/254

255 fXCLK6/255

Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the

MDL67 to MDL60 bits.

2. The baud rate value is the output clock of the 8-bit counter divided by 2.

Remarks 1. f^XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register

2. k:

3. ×:

Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)

Don’t care

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(6) Asynchronous serial interface control register 6 (ASICL6)

This register controls the serial communication operations of serial interface UART6.

ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 16H.

Caution ASICL6 can be refreshed (the same value is written) by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5

(RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh operation

because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is completed (when an

interrupt signal is generated).

Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)

Address: FF58H After reset: 16H R/W^Note

Symbol

ASICL6

<7>

<6>

5

4

3

2

1

0

SBRF6

SBRT6

SBTT6

SBL62

SBL61

SBL60

DIR6

TXDLV6

SBRF6

SBF reception status flag

0

1

If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly

SBF reception in progress

SBRT6

SBF reception trigger

0

1

−

SBF reception trigger

SBTT6

SBF transmission trigger

0

1

−

SBF transmission trigger

Note Bit 7 is read-only.

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Figure 12-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)

SBL62

SBL61

SBL60

SBF transmission output width control

SBF is output with 13-bit length.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SBF is output with 14-bit length.

SBF is output with 15-bit length.

SBF is output with 16-bit length.

SBF is output with 17-bit length.

SBF is output with 18-bit length.

SBF is output with 19-bit length.

SBF is output with 20-bit length.

DIR6

First-bit specification

0

1

MSB

LSB

TXDLV6

Enables/disables inverting TXD6 output

0

1

Normal output of TXD6

Inverted output of TXD6

Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode. The status

of the SBRF6 flag is held (1).

2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.

3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF

reception has been correctly completed.

4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =

1.

5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of

SBF transmission.

6. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.

7. When using the 78K0/KB1+ to evaluate the program of a mask ROM version of the 78K0/KB1,

set the SBTT6, SBL62, SBL61, and SBL60 bits to 0, 1, 0, 1, respectively.

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(7) Input switch control register (ISC)

The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN

(Local Interconnect Network) reception. The input source is switched by setting ISC.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 12-11. Format of Input Switch Control Register (ISC)

Address: FF4FH After reset: 00H R/W

Symbol

ISC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ISC1

ISC0

ISC1

TI000 input source selection

0

1

TI000 (P00)

RxD6 (P14)

ISC0

INTP0 input source selection

0

1

INTP0 (P120)

RxD6 (P14)

(8) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using the P13/TxD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1.

Set PM14 to 1 when using the P14/RxD6 pin as a serial interface data input pin. The output latch of P14 at this

time may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 12-12. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

6

5

4

3

2

1

0

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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12.4 Operation of Serial Interface UART6

Serial interface UART6 has the following two modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

12.4.1 Operation stop mode

In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In

addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and

5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.

(1) Register used

The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).

ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Address: FF50H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

.

TXE6

0

Enables/disables transmission

Disables transmission operation (synchronously resets the transmission circuit).

RXE6

0

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Notes 1. The output of the T^XD6 pin goes high and the input from the RXD6 pin is fixed to high level when

POWER6 = 0.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.

To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.

Remark To use the RxD6/P14 and TxD6/P13 pins as general-purpose port pins, see CHAPTER 4 PORT

FUNCTIONS.

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12.4.2 Asynchronous serial interface (UART) mode

In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be

performed.

A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of

baud rates.

(1) Registers used

• Asynchronous serial interface operation mode register 6 (ASIM6)

• Asynchronous serial interface reception error status register 6 (ASIS6)

• Asynchronous serial interface transmission status register 6 (ASIF6)

• Clock selection register 6 (CKSR6)

• Baud rate generator control register 6 (BRGC6)

• Asynchronous serial interface control register 6 (ASICL6)

• Input switch control register (ISC)

• Port mode register 1 (PM1)

• Port register 1 (P1)

The basic procedure of setting an operation in the UART mode is as follows.

<1> Set the CKSR6 register (see Figure 12-8).

<2> Set the BRGC6 register (see Figure 12-9).

<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 12-5).

<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 12-10).

<5> Set bit 7 (POWER6) of the ASIM6 register to 1.

<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.

Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.

<7> Write data to transmit buffer register 6 (TXB6). → Data transmission is started.

Caution Take relationship with the other party of communication when setting the port mode register

and port register.

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The relationship between the register settings and pins is shown below.

Table 12-2. Relationship Between Register Settings and Pins

POWER6 TXE6

RXE6

PM13

P13

PM14

P14

UART6

Pin Function

TxD6/P13

Operation

RxD6/P14

P14

Note

0

1

0

1

0

1

0

1

×

Stop

P13

Note

×

1

×

Reception

Transmission

RxD6

P14

Note

0

1

×

TxD6

1

×

Transmission/

reception

RxD6

Note Can be set as port function.

Remark ×:

don’t care

POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

RXE6:

PM1×:

P1×:

Bit 6 of ASIM6

Bit 5 of ASIM6

Port mode register

Port output latch

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(2) Communication operation

(a) Format and waveform example of normal transmit/receive data

Figures 12-13 and 12-14 show the format and waveform example of the normal transmit/receive data.

Figure 12-13. Format of Normal UART Transmit/Receive Data

1. LSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop bit

Character bits

2. MSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D7

D6

D5

D4

D3

D2

D1

D0

Stop bit

Character bits

One data frame consists of the following bits.

• Start bit ... 1 bit

• Character bits ... 7 or 8 bits

• Parity bit ... Even parity, odd parity, 0 parity, or no parity

• Stop bit ... 1 or 2 bits

The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial

interface operation mode register 6 (ASIM6).

Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial

interface control register 6 (ASICL6).

Whether the T^XD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.

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Figure 12-14. Example of Normal UART Transmit/Receive Data Waveform

1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, T^XD6 pin

inverted output

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

Parity

Stop

5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

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(b) Parity types and operation

The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used

on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error

can be detected. With zero parity and no parity, an error cannot be detected.

Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.

(i) Even parity

• Transmission

Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.

The value of the parity bit is as follows.

If transmit data has an odd number of bits that are “1”:

1

If transmit data has an even number of bits that are “1”: 0

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a

parity error occurs.

(ii) Odd parity

• Transmission

Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that

are “1” is odd.

If transmit data has an odd number of bits that are “1”:

0

If transmit data has an even number of bits that are “1”: 1

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a

parity error occurs.

(iii) 0 parity

The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.

The parity bit is not detected when the data is received. Therefore, a parity error does not occur

regardless of whether the parity bit is “0” or “1”.

(iv) No parity

No parity bit is appended to the transmit data.

Reception is performed assuming that there is no parity bit when data is received. Because there is no

parity bit, a parity error does not occur.

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(c) Normal transmission

The T^XD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode

register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.

Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity

bit, and stop bit are automatically appended to the data.

When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,

the data is sequentially output from TXS6 to the T^XD6 pin. When transmission is completed, the parity bit

and stop bit set by ASIM6 are added and a transmission completion interrupt request (INTST6) is generated.

Transmission is stopped until the data to be transmitted next is written to TXB6.

Figure 12-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt

occurs as soon as the last stop bit has been output.

Figure 12-15. Normal Transmission Completion Interrupt Request Timing

1. Stop bit length: 1

Parity

TX

D6 (output)

INTST6

Start

D0

D1

D2

D6

D7

Stop

2. Stop bit length: 2

TXD6 (output)

Start

D0

D1

D2

D6

D7

Parity

Stop

INTST6

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(d) Continuous transmission

The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6

(TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after

transmission of one data frame, data can be continuously transmitted and an efficient communication rate

can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait

for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface

transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred.

To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and

whether the TXB6 register can be written, and then write the data.

Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from “10” to “11”, and to “01”

during continuous transmission. To check the status, therefore, do not use a

combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag

when executing continuous transmission.

2. When the device is incorporated in a LIN, the continuous transmission function cannot

be used. Make sure that asynchronous serial interface transmission status register 6

(ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6).

TXBF6

Writing to TXB6 Register

0

1

Writing enabled

Writing disabled

Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

The communication status can be checked using the TXSF6 flag.

TXSF6

Transmission Status

0

1

Transmission is completed.

Transmission is in progress.

Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure

to check that the TXSF6 flag is “0” after generation of the transmission completion

interrupt, and then execute initialization. If initialization is executed while the TXSF6

flag is “1”, the transmit data cannot be guaranteed.

2. During continuous transmission, an overrun error may occur, which means that the

next transmission was completed before execution of INTST6 interrupt servicing after

transmission of one data frame. An overrun error can be detected by developing a

program that can count the number of transmit data and by referencing the TXSF6 flag.

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Figure 12-16 shows an example of the continuous transmission processing flow.

Figure 12-16. Example of Continuous Transmission Processing Flow

Set registers.

Write TXB6.

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXBF6 = 0?

Yes

Write TXB6.

Transmission

completion interrupt

occurs?

No

Yes

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXSF6 = 0?

Yes

Completion of

transmission processing

Remark TXB6: Transmit buffer register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)

TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)

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Figure 12-17 shows the timing of starting continuous transmission, and Figure 12-18 shows the timing of

ending continuous transmission.

Figure 12-17. Timing of Starting Continuous Transmission

Start

T

X

D6

Data (1)

Parity Stop

Data (2)

Parity

Stop

INTST6

TXB6

FF

Data (1)

Data (2)

Data (3)

TXS6

Data (1)

Data (2)

Data (3)

TXBF6

TXSF6

Note

Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether

writing is enabled using only the TXBF6 bit.

Remark T^XD6:

TXD6 pin (output)

INTST6: Interrupt request signal

TXB6:

TXS6:

Transmit buffer register 6

Transmit shift register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6

TXSF6: Bit 0 of ASIF6

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Figure 12-18. Timing of Ending Continuous Transmission

Start

TX

D6

Data (n)

Parity

Stop

Data (n − 1) Parity

Stop

INTST6

TXB6

Data (n − 1)

Data (n)

TXS6

FF

Data (n − 1)

Data (n)

TXBF6

TXSF6

POWER6 or TXE6

Remark T^XD6:

INTST6:

TXD6 pin (output)

Interrupt request signal

Transmit buffer register 6

Transmit shift register 6

TXB6:

TXS6:

ASIF6:

TXBF6:

TXSF6:

Asynchronous serial interface transmission status register 6

Bit 1 of ASIF6

Bit 0 of ASIF6

POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

Bit 6 of asynchronous serial interface operation mode register 6 (ASIM6)

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(e) Normal reception

Reception is enabled and the R^XD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial

interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.

The 8-bit counter of the baud rate generator starts counting when the falling edge of the R^XD6 pin input is

detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the

R^XD6 pin input is sampled again ( in Figure 12-19). If the RXD6 pin is low level at this time, it is recognized

as a start bit.

When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift

register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt

(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun

error (OVE6) occurs, however, the receive data is not written to RXB6.

Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception

position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception.

Figure 12-19. Reception Completion Interrupt Request Timing

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

RX

D6 (input)

INTSR6

RXB6

Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

2. Reception is always performed with the “number of stop bits = 1”. The second stop bit

is ignored.

3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)

before reading RXB6.

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(f) Reception error

Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error

flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data

reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.

Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception

error interrupt servicing (INTSR6/INTSRE6) (see Figure 12-6).

The contents of ASIS6 are reset to 0 when ASIS6 is read.

Table 12-3. Cause of Reception Error

Reception Error

Parity error

Cause

The parity specified for transmission does not match the parity of the receive data.

Stop bit is not detected.

Framing error

Overrun error

Reception of the next data is completed before data is read from receive buffer register 6 (RXB6).

The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt

(INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0.

Figure 12-20. Reception Error Interrupt

1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are

separated)

(a) No error during reception

(b) Error during reception

INTSR6

INTSRE6

2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)

(a) No error during reception

(b) Error during reception

INTSR6

INTSRE6

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(g) Noise filter of receive data

The RxD6 signal is sampled with the base clock output by the prescaler block.

If two sampled values are the same, the output of the match detector changes, and the data is sampled as

input data.

Because the circuit is configured as shown in Figure 12-21, the internal processing of the reception operation

is delayed by two clocks from the external signal status.

Figure 12-21. Noise Filter Circuit

Base clock

Internal signal A

R

X

D6/P14

Internal signal B

In

Q

In

Q

LD_EN

Match detector

(h) SBF transmission

When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is

used for transmission. For the transmission operation of LIN, see Figure 12-1 LIN Transmission

Operation.

The T^XD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface mode register 6

(ASIM6) is set to 1. Transmission is enabled when bit 6 (TXE6) of ASIM6 is set to 1 next time, and SBF

transmission operation is started when bit 5 (SBTT6) of asynchronous serial interface control register 6

(ASICL6) is set to 1.

After transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of

ASICL6) are output. When SBF is complete, a transmission completion interrupt request (INTST6) is issued,

and SBTT6 is automatically cleared. After SBF transmission is completed, the normal transmission mode is

restored.

SBF transmission is stopped until the data to be transmitted next is written to transmit buffer register 6

(TXB6) or SBTT6 is set to 1.

Figure 12-22. SBF Transmission

1

2

3

4

5

6

7

8

9

10

11

12

13 Stop

TXD6

INTST6

SBTT6

Remark T^XD6:

TXD6 pin (output)

INTST6: Transmission completion interrupt request

SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)

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(i) SBF reception

When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is

used for reception. For the reception operation of LIN, see Figure 12-2 LIN Reception Operation.

Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6

(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)

of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,

the R^XD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable

status.

When the start bit has been detected, reception is started, and serial data is sequentially stored in receive

shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or

more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the

SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as

OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is

suppressed, and error detection processing of UART communication is not performed. In addition, data

transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and

the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error

processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the

SBRF6 and SBRT6 bits are not cleared.

Figure 12-23. SBF Reception

1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)

1

2

3

4

5

6

7

8

9

10

11

RXD6

SBRT6

/SBRF6

INTSR6

2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)

1

2

3

4

5

6

7

8

9

10

RXD6

SBRT6

/SBRF6

INTSR6

“0”

Remark RXD6:

RXD6 pin (input)

SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)

SBRF6: Bit 7 of ASICL6

INTSR6: Reception completion interrupt request

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12.4.3 Dedicated baud rate generator

The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and

generates a serial clock for transmission/reception of UART6.

Separate 8-bit counters are provided for transmission and reception.

(1) Configuration of baud rate generator

•

Base clock

The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to

each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is 1.

This clock is called the base clock and its frequency is called f^XCLK6. The base clock is fixed to low level

when POWER6 = 0.

Transmission counter

This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface

operation mode register 6 (ASIM6) is 0.

It starts counting when POWER6 = 1 and TXE6 = 1.

The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).

If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been

completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues

counting until POWER6 or TXE6 is cleared to 0.

•

Reception counter

This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial

interface operation mode register 6 (ASIM6) is 0.

It starts counting when the start bit has been detected.

The counter stops operation after one frame has been received, until the next start bit is detected.

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Figure 12-24. Configuration of Baud Rate Generator

POWER6

fX

fX/2

Baud rate generator

f^X/2²

fX/2³

fX/2⁴

fX/2⁵

fX/2⁶

fX/2⁷

fX/2⁸

fX/2⁹

POWER6, TXE6 (or RXE6)

Selector

8-bit counter

fXCLK6

fX/2¹⁰

8-bit timer/

Match detector

Baud rate

1/2

event counter

50 output

CKSR6: TPS63 to TPS60

BRGC6: MDL67 to MDL60

Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

Bit 6 of ASIM6

RXE6:

Bit 5 of ASIM6

CKSR6:

BRGC6:

Clock selection register 6

Baud rate generator control register 6

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(2) Generation of serial clock

A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control

register 6 (BRGC6).

Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.

Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.

(a) Baud rate

The baud rate can be calculated by the following expression.

f^XCLK6

• Baud rate =

[bps]

2 × k

f^XCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register

k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)

(b) Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Cautions 1. Keep the baud rate error during transmission to within the permissible error range at

the reception destination.

2. Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Example: Frequency of base clock = 10 MHz = 10,000,000 Hz

Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)

Target baud rate = 153600 bps

Baud rate = 10 M/(2 × 33)

= 10000000/(2 × 33) = 151515 [bps]

Error = (151515/153600 − 1) × 100

= −1.357 [%]

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(3) Example of setting baud rate

Table 12-4. Set Data of Baud Rate Generator

Baud Rate

[bps]

fX = 10.0 MHz

fX = 8.38 MHz

fX = 4.19 MHz

TPS63 to

TPS60

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%]

Value

TPS60

6H

5H

4H

3H

2H

1H

0H

Value

TPS60

5H

4H

3H

2H

1H

0H

Value

600

1200

6H

5H

4H

3H

2H

1H

0H

130

120

130

80

601

1202

0.16

0.00

0.16

0.94

−1.36

109

101

109

134

109

55

601

0.11

0.28

0.11

0.06

0.11

−0.80

1.03

109

101

109

67

601

0.11

−0.28

0.11

0.06

−0.80

1.03

−2.58

1.03

1201

2400

2404

2403

4800

4808

4805

9600

9615

9610

10400

19200

31250

38400

76800

115200

153600

230400

10417

19231

31250

38462

76923

116279

151515

227272

10371

19220

31268

38440

76182

116389

155185

232778

10475

19220

31268

38090

77593

116389

149643

232778

130

65

55

27

43

36

18

33

27

14

22

18

9

Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))

k:

Value set by MDL67 to MDL60 bits of baud rate generator control register 6

(BRGC6) (k = 8, 9, 10, ..., 255)

f^X:

High-speed system clock oscillation frequency

Baud rate error

ERR:

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(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 12-25. Permissible Baud Rate Range During Reception

Latch timing

Data frame length

Start bit

Bit 0

FL

Bit 1

Bit 7

Parity bit

Stop bit

of UART6

1 data frame (11 × FL)

Minimum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmin

Maximum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmax

As shown in Figure 12-25, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

1

FL = (Brate)⁻

Brate: Baud rate of UART6

k:

Set value of BRGC6

1-bit data length

FL:

Margin of latch timing: 2 clocks

21k + 2

2k

k − 2

2k

Minimum permissible data frame length: FLmin = 11 × FL −

× FL =

FL

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Therefore, the maximum receivable baud rate at the transmission destination is as follows.

22k

1

BRmax = (FLmin/11)⁻

=

Brate

21k + 2

Similarly, the maximum permissible data frame length can be calculated as follows.

10

11

k + 2

21k − 2

2 × k

× FLmax = 11 × FL −

× FL =

FL

2 × k

21k − 2

20k

FLmax =

FL × 11

Therefore, the minimum receivable baud rate at the transmission destination is as follows.

20k

1

BRmin = (FLmax/11)⁻

=

Brate

21k − 2

The permissible baud rate error between UART6 and the transmission destination can be calculated from the

above minimum and maximum baud rate expressions, as follows.

Table 12-5. Maximum/Minimum Permissible Baud Rate Error

Division Ratio (k)

Maximum Permissible Baud Rate Error

Minimum Permissible Baud Rate Error

8

+3.53%

+4.26%

+4.56%

+4.66%

+4.72%

−3.61%

−4.31%

−4.58%

−4.67%

−4.73%

20

50

100

255

Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock

frequency, and division ratio (k). The higher the input clock frequency and the higher the division

ratio (k), the higher the permissible error.

2. k: Set value of BRGC6

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(5) Data frame length during continuous transmission

When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by

two clocks of base clock from the normal value. However, the result of communication is not affected because

the timing is initialized on the reception side when the start bit is detected.

Figure 12-26. Data Frame Length During Continuous Transmission

Start bit of

1 data frame

second byte

Bit 0

FL

Bit 1

FL

Bit 7

FL

Bit 0

FL

Start bit

FL

Start bit

FL

Parity bit

FL

Stop bit

FLstp

Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following

expression is satisfied.

FLstp = FL + 2/f^XCLK6

Therefore, the data frame length during continuous transmission is:

Data frame length = 11 × FL + 2/f^XCLK6

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CHAPTER 13 SERIAL INTERFACE CSI10

13.1 Functions of Serial Interface CSI10

Serial interface CSI10 has the following two modes.

•

Operation stop mode

3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial communication is not performed and can enable a reduction in the power

consumption.

For details, see 13.4.1 Operation stop mode.

(2) 3-wire serial I/O mode (MSB/LSB-first selectable)

This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data

lines (SI10 and SO10).

The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission

and reception can be simultaneously executed.

In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can

be connected to any device.

The 3-wire serial I/O mode can be used connecting peripheral ICs and display controllers with a clocked serial

interface.

For details, see 13.4.2 3-wire serial I/O mode.

13.2 Configuration of Serial Interface CSI10

Serial interface CSI10 includes the following hardware.

Table 13-1. Configuration of Serial Interface CSI10

Item

Configuration

Registers

Transmit buffer register 10 (SOTB10)

Serial I/O shift register 10 (SIO10)

Control registers

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Port mode register 1 (PM1)

Port register 1 (P1)

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Figure 13-1. Block Diagram of Serial Interface CSI10

Internal bus

8

Serial I/O shift

register 10 (SIO10)

Transmit buffer

register 10 (SOTB10)

Output

selector

SI10/P11(/RxD0^Note

)

SO10/P12

Output latch

(P12)

PM12

Transmit data

controller

Output latch

Transmit controller

f^X/2

fX/2²

fX/2³

fX/2⁴

Clock start/stop controller &

clock phase controller

INTCSI10

fX/2⁵

fX/2⁶

fX/2⁷

SCK10/P10

(/TxD0^Note

)

Note µPD78F0102H and 78F0103H only.

(1) Transmit buffer register 10 (SOTB10)

This register sets the transmit data.

Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial

operation mode register 10 (CSIM10) are 1.

The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and

output to the serial output pin (SO10).

SOTB10 can be written or read by an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication).

(2) Serial I/O shift register 10 (SIO10)

This is an 8-bit register that converts data from parallel data into serial data and vice versa.

This register can be read by an 8-bit memory manipulation instruction.

Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10)

is 0.

During reception, the data is read from the serial input pin (SI10) to SIO10.

RESET input clears this register to 00H.

Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).

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13.3 Registers Controlling Serial Interface CSI10

Serial interface CSI10 is controlled by the following four registers.

•

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Serial operation mode register 10 (CSIM10)

CSIM10 is used to select the operation mode and enable or disable operation.

CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 13-2. Format of Serial Operation Mode Register 10 (CSIM10)

Address: FF80H After reset: 00H R/W^{Note 1}

Symbol

CSIM10

<7>

6

5

0

4

3

0

2

0

1

0

CSIE10

TRMD10

DIR10

CSOT10

CSIE10

Operation control in 3-wire serial I/O mode

0

1

Disables operation^{Note 2}and asynchronously resets the internal circuit^{Note 3}

Enables operation

.

TRMD10^{Note 4}

Transmit/receive mode control

Receive mode (transmission disabled).

Transmit/receive mode

0^{Note 5}

1

DIR10^{Note 6}

First bit specification

0

1

MSB

LSB

CSOT10

Communication status flag

Communication is stopped.

0

1

Communication is in progress.

Notes 1. Bit 0 is a read-only bit.

2. To use P10/SCK10(/TxD0^{Note 7}), P11/SI10(/RxD0^{Note 7}), and P12/SO10 as general-purpose ports, set

<R>

CSIM10 in the default status (00H).

3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.

4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).

5. The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read

from SIO10.

6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).

7. µPD78F0102H and 78F0103H only.

Caution Be sure to clear bit 5 to 0.

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CHAPTER 13 SERIAL INTERFACE CSI10

(2) Serial clock selection register 10 (CSIC10)

This register specifies the timing of the data transmission/reception and sets the serial clock.

CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 13-3. Format of Serial Clock Selection Register 10 (CSIC10)

Address: FF81H After reset: 00H R/W

Symbol

CSIC10

7

0

6

0

5

0

4

3

2

1

0

CKP10

DAP10

CKS102

CKS101

CKS100

CKP10

0

DAP10

0

Specification of data transmission/reception timing

SCK10

Type

1

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

0

1

0

1

2

3

4

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

CKS102

CKS101

CKS100

CSI10 serial clock selection^Note

Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX/2 (5 MHz)

Master mode

Slave mode

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

fX/2⁶(156.25 kHz)

fX/2⁷(78.13 kHz)

External clock input to SCK10

Note Set the serial clock to satisfy the following conditions.

• V^DD= 4.0 to 5.5 V: Serial clock ≤ 5 MHz

• V^DD= 3.3 to 4.0 V: Serial clock ≤ 4.19 MHz

• V^DD= 2.7 to 3.3 V: Serial clock ≤ 2.5 MHz

<R>

• V^DD= 2.5 to 2.7 V: Serial clock ≤ 1.25 MHz (standard products, (A) grade products only)

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Cautions 1. When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of

the internal oscillator is divided and supplied as the serial clock. At this time, the operation

of serial interface CSI10 is not guaranteed.

2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).

<R>

3. To use P10/SCK10(/TxD0^Note), P11/SI10(/RxD0^Note), and P12/SO10 as general-purpose ports, set

CSIC10 in the default status (00H).

4. The phase type of the data clock is type 1 after reset.

Note µPD78F0102H and 78F0103H only.

Remarks 1. Figures in parentheses are for operation with f^X= 10 MHz

2. fX: High-speed system clock oscillation frequency

(3) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using P10/SCK10(/TxD0^Note) as the clock output pin of the serial interface, clear PM10 to 0 and set the

output latch of P10 to 1.

When using P12/SO10 as the data output pin of the serial interface, clear PM12 and the output latches of P12 to

0.

When using P10/SCK10(/TxD0^Note) as the clock input pins of the serial interface, and P11/SI10(/RxD0^Note) as the

data input pins, set PM10 and PM11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Note µPD78F0102H and 78F0103H only.

Figure 13-4. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

6

5

4

3

2

1

0

PM17

PM16

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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13.4 Operation of Serial Interface CSI10

Serial interface CSI10 can be used in the following two modes.

•

Operation stop mode

3-wire serial I/O mode

13.4.1 Operation stop mode

Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition,

the P10/SCK10(/T^XD0^Note), P11/SI10(/RXD0^Note), and P12/SO10 pins can be used as ordinary I/O port pins in this mode.

Note µPD78F0102H and 78F0103H only.

(1) Register used

The operation stop mode is set by serial operation mode register 10 (CSIM10).

To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0.

(a) Serial operation mode register 10 (CSIM10)

CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM10 to 00H.

Address: FF80H After reset: 00H R/W

Symbol

CSIM10

<7>

6

5

0

4

3

0

2

0

1

0

CSIE10

TRMD10

DIR10

CSOT10

CSIE10

0

Operation control in 3-wire serial I/O mode

Disables operation^{Note 1}and asynchronously resets the internal circuit^{Note 2}

.

Notes 1. To use P10/SCK10(/TxD0^{Note 3}), P11/SI10(/RxD0^{Note 3}), and P12/SO10 as general-purpose ports,

set CSIM10 in the default status (00H).

<R>

2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.

3. µPD78F0102H and 78F0103H only.

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13.4.2 3-wire serial I/O mode

The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked

serial interface.

In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and

serial input (SI10) lines.

(1) Registers used

• Serial operation mode register 10 (CSIM10)

• Serial clock selection register 10 (CSIC10)

• Port mode register 1 (PM1)

• Port register 1 (P1)

The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.

<1> Set the CSIC10 register (see Figure 13-3).

<2> Set bits 4 and 6 (DIR10 and TRMD10) of the CSIM10 register (see Figure 13-2).

<3> Set bit 7 (CSIE10) of the CSIM10 register to 1. → Transmission/reception is enabled.

<4> Write data to transmit buffer register 10 (SOTB10). → Data transmission/reception is started.

Read data from serial I/O shift register 10 (SIO10). → Data reception is started.

Caution Take relationship with the other party of communication when setting the port mode

register and port register.

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The relationship between the register settings and pins is shown below.

Table 13-2. Relationship Between Register Settings and Pins

CSIE10

PM11

P11

PM12

P12

PM10

P10

CSI10

Pin Function

TRMD10

Operation

P11/SI10

(/RxD0^{Note 4}

P12/SO10 P10/SCK10

)

(/TxD0^{Note 4}

)

Note 1

0

1

×

0

1

×

Stop

P11

P12

P10

Note2

(/RxD0^{Note 4}

)

(/TxD0^Note4

)

Note 1

1

×

1

×

Slave

reception^{Note 3}

SI10

SCK10

(input)^{Note 3}

Note 1

×

0

Slave

P11

SO10

SCK10

(input)^{Note 3}

transmission^{Note 3}(/RxD0^{Note 4}

)

1

×

Slave

SI10

SCK10

(input)^{Note 3}

transmission/

reception^{Note 3}

Note 1

1

0

1

×

0

1

Master

SI10

P12

SCK10

(output)

reception

Note 1

×

0

Master

P11

(/RxD0^{Note 4}

)

SO10

SCK10

(output)

transmission

1

×

Master

transmission/

reception

SI10

SCK10

(output)

Notes 1. Can be set as port function.

2. To use P10/SCK10(/TxD0^{Note 4}) as port pins, clear CKP10 to 0.

3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1.

4. µPD78F0102H and 78F0103H only.

Remark ×:

don’t care

CSIE10:

TRMD10:

CKP10:

Bit 7 of serial operation mode register 10 (CSIM10)

Bit 6 of CSIM10

Bit 4 of serial clock selection register 10 (CSIC10)

CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10

PM1×:

P1×:

Port mode register

Port output latch

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(2) Communication operation

In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or

received in synchronization with the serial clock.

Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1.

Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition,

data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0.

Reception is started when data is read from serial I/O shift register 10 (SIO10).

After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data

has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared

to 0. Then the next communication is enabled.

Caution Do not access the control register and data register when CSOT10 = 1 (during serial

communication).

Figure 13-5. Timing in 3-Wire Serial I/O Mode (1/2)

(1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)

SCK10

Read/write trigger

SOTB10

SIO10

55H (communication data)

ABH

56H

ADH

5AH

B5H

6AH

D5H AAH

CSOT10

INTCSI10

CSIIF10

SI10 (receive AAH)

SO10

55H is written to SOTB10.

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Figure 13-5. Timing in 3-Wire Serial I/O Mode (2/2)

(2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)

SCK10

Read/write trigger

SOTB10

SIO10

55H (communication data)

ABH

56H

ADH

5AH

B5H

6AH

D5H

AAH

CSOT10

INTCSI10

CSIIF10

SI10 (input AAH)

SO10

55H is written to SOTB10.

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Figure 13-6. Timing of Clock/Data Phase

(a) Type 1; CKP10 = 0, DAP10 = 0

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(b) Type 2; CKP10 = 0, DAP10 = 1

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(c) Type 3; CKP10 = 1, DAP10 = 0

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(d) Type 4; CKP10 = 1, DAP10 = 1

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

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CHAPTER 13 SERIAL INTERFACE CSI10

(3) Timing of output to SO10 pin (first bit)

When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin.

The output operation of the first bit at this time is described below.

Figure 13-7. Output Operation of First Bit

(1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0)

SCK10

Writing to SOTB10 or

reading from SIO10

SOTB10

SIO10

Output latch

First bit

2nd bit

SO10

The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10,

and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the

SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of

the receive data is stored in the SIO10 register via the SI10 pin.

The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising)

edge of SCK10, and the data is output from the SO10 pin.

(2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1)

SCK10

Writing to SOTB10 or

reading from SIO10

SOTB10

SIO10

Output latch

First bit

2nd bit

3rd bit

SO10

The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10

register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the

value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and

shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.

The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling)

edge of SCK10, and the data is output from the SO10 pin.

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(4) Output value of SO10 pin (last bit)

After communication has been completed, the SO10 pin holds the output value of the last bit.

Figure 13-8. Output Value of SO10 Pin (Last Bit)

(1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0)

SCK10

Writing to SOTB10 or

reading from SIO10

( ← Next request is issued.)

SOTB10

SIO10

Output latch

Last bit

SO10

(2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1)

SCK10

Writing to SOTB10 or

reading from SIO10

( ← Next request is issued.)

SOTB10

SIO10

Output latch

SO10

Last bit

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CHAPTER 13 SERIAL INTERFACE CSI10

(5) SO10 output

The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is

cleared to 0.

Table 13-3. SO10 Output Status

TRMD10

TRMD10 = 0^{Note 2}

TRMD10 = 1

DAP10

DIR10

SO10 Output^{Note 1}

Outputs low level^{Note 2}

−

.

DAP10 = 0

Value of SO10 latch

(low-level output)

DAP10 = 1

DIR10 = 0

DIR10 = 1

Value of bit 7 of SOTB10

Value of bit 0 of SOTB10

Notes 1. The actual output of the SO10/P12 pin is determined according to PM12 and P12, as well as the

SO10 output.

2. Status after reset

Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.

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CHAPTER 14 INTERRUPT FUNCTIONS

14.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Maskable interrupts

These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group

and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L).

Multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts. If two or more

interrupts with the same priority are simultaneously generated, each interrupt is serviced according to its

predetermined priority (see Table 14-1).

A standby release signal is generated and the STOP mode and HALT mode are released by maskable interrupts.

Six external interrupt requests and 12 internal interrupt requests are provided as maskable interrupts.

(2) Software interrupt

This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts

are disabled. The software interrupt does not undergo interrupt priority control.

14.2 Interrupt Sources and Configuration

A total of 19 interrupt sources exist for maskable and software interrupts. In addition, maximum total of 5 reset

sources are also provided (see Table 14-1).

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Table 14-1. Interrupt Source List

Interrupt

Type

Default

Interrupt Source

Trigger

Internal/

External

Vector

Table

Basic

Priority^{Note 1}

Configuration

Type^{Note 2}

Name

INTLVI

Address

Maskable

0

1

Low-voltage detection^{Note 3}

Pin input edge detection

Internal

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

(A)

(B)

INTP0

External

2

INTP1

3

INTP2

4

INTP3

5

INTP4

6

INTP5

7

INTSRE6

INTSR6

INTST6

UART6 reception error generation

End of UART6 reception

Internal

(A)

8

9

End of UART6 transmission

10

INTCSI10/ End of CSI10 communication/end of UART0

INTST0^{Note 4}transmission

11

12

13

14

15

INTTMH1

INTTMH0

INTTM50

Match between TMH1 and CMP01

(when compare register is specified)

001AH

001CH

001EH

0020H

0022H

Match between TMH0 and CMP00

(when compare register is specified)

Match between TM50 and CR50

(when compare register is specified)

INTTM000 Match between TM00 and CR000

(when compare register is specified)

INTTM010 Match between TM00 and CR010

(when compare register is specified)

16

17

INTAD

End of A/D conversion

0024H

0026H

INTSR0^{Note 4}End of UART0 reception or reception error

generation

Software

Reset

−

BRK

BRK instruction execution

Reset input

−

003EH

0000H

(C)

RESET

POC

LVI

−

Power-on-clear

Low-voltage detection^{Note 5}

Clock

High-speed system clock stop detection

monitor

WDT

WDT overflow

Notes 1. The default priority is the priority applicable when two or more maskable interrupt are generated

simultaneously. 0 is the highest priority, and 17 is the lowest.

2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 14-1.

3. When bit 1 (LVIMD) = 0 is selected for the low-voltage detection register (LVIM).

4. The interrupt sources INTST0 and INTSR0 are available only in the µPD78F0102H and 78F0103H.

5. When LVIMD = 1 is selected.

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Figure 14-1. Basic Configuration of Interrupt Function

(A) Internal maskable interrupt

Internal bus

IE

MK

PR

ISP

Vector table

address generator

Priority controller

Interrupt

request

IF

Standby release signal

(B) External maskable interrupt (INTP0 to INTP5)

Internal bus

External interrupt edge

enable register

(EGP, EGN)

MK

IE

PR

ISP

Vector table

address generator

Priority controller

Interrupt

request

Edge

detector

IF

Standby release signal

(C) Software interrupt

Internal bus

Interrupt

request

Vector table

address generator

Priority controller

IF:

IE:

Interrupt request flag

Interrupt enable flag

ISP: In-service priority flag

MK:

PR:

Interrupt mask flag

Priority specification flag

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14.3 Registers Controlling Interrupt Function

The following 6 types of registers are used to control the interrupt functions.

•

Interrupt request flag register (IF0L, IF0H, IF1L)

Interrupt mask flag register (MK0L, MK0H, MK1L)

Priority specification flag register (PR0L, PR0H, PR1L)

External interrupt rising edge enable register (EGP)

External interrupt falling edge enable register (EGN)

Program status word (PSW)

Table 14-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding

to interrupt request sources.

Table 14-2. Flags Corresponding to Interrupt Request Sources

Interrupt

Request

Interrupt Request Flag

Register

IF0L

Interrupt Mask Flag

Register

MK0L

Priority Specification Flag

Register

INTLVI

LVIIF

LVIMK

LVIPR

PR0L

INTP0

PIF0

PMK0

PPR0

INTP1

PIF1

PMK1

PPR1

INTP2

PIF2

PMK2

PPR2

INTP3

PIF3

PMK3

PPR3

INTP4

PIF4

PMK4

PPR4

INTP5

PIF5

PMK5

PPR5

INTSRE6

INTSR6

INTST6

INTST0^{Note 1}

INTCSI10

INTTMH1

INTTMH0

INTTM50

INTTM000

INTTM010

INTAD

SREIF6

SRIF6

SREMK6

SRMK6

STMK6

SREPR6

SRPR6

IF0H

MK0H

PR0H

STIF6

STPR6

DUALIF0^{Note 2}

CSIIF10^{Note 3}

TMIFH1

TMIFH0

TMIF50

TMIF000

TMIF010

ADIF

DUALMK0^{Note 4}

CSIMK10^{Note 3}

TMMKH1

TMMKH0

TMMK50

TMMK000

TMMK010

ADMK

DUALPR0^{Note 4}

CSIPR10^{Note 3}

TMPRH1

TMPRH0

TMPR50

TMPR000

TMPR010

ADPR

IF1L

MK1L

PR1L

INTSR0^{Note 1}

SRIF0^{Note 1}

SRMK0^{Note 1}

SRPR0^{Note 1}

Notes 1. µPD78F0102H and 78F0103H only.

2. Flag name in the µPD78F0102H and 78F0103H. If either of the two types of interrupt sources is

generated, these flags are set (1).

3. Flag name in the µPD78F0101H

4. These are the flag names in the µPD78F0102H and 78F0103H. These flags support two types of

interrupt sources.

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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)

The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is

executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or

upon application of RESET input.

When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt

routine is entered.

IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are

combined to form 16-bit register IF0, they are read with a 16-bit memory manipulation instruction.

RESET input sets these registers to 00H.

Figure 14-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L)

Address: FFE0H After reset: 00H R/W

Symbol

IF0L

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

SREIF6

PIF5

PIF4

PIF3

PIF2

PIF1

PIF0

LVIIF

Address: FFE1H After reset: 00H R/W

Symbol

IF0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMIF010

TMIF000

TMIF50

TMIFH0

TMIFH1 DUALIF0^{Note 1}

STIF6

SRIF6

Address: FFE2H After reset: 00H R/W

Symbol

IF1L

7

0

6

0

5

0

4

0

3

0

2

0

<1>

<0>

SRIF0^{Note 2}

ADIF

XXIFX

Interrupt request flag

0

1

No interrupt request signal is generated

Interrupt request is generated, interrupt request status

Notes 1. This is CSIIF10 in the µPD78F0101H.

2. µPD78F0102H and 78F0103H only.

Cautions 1. Be sure to set bits 2 to 7 of IF1L to 0.

2. When operating a timer, serial interface, or A/D converter after standby release, operate it

once after clearing the interrupt request flag. An interrupt request flag may be set by noise.

3. Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the

interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and

“_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly

instructions after compilation must be 1-bit memory manipulation instructions (CLR1).

If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C language, for

example, it is converted to the following three assembly instructions after compilation:

mov

and

a, IF0L

a, #0FEH

IF0L, a

mov

In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request flag of

another bit of the identical interrupt request flag register (IF0L) is set to 1, it is cleared to 0

by “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory

manipulation instruction in C language.

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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)

The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.

MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are

combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Figure 14-3. Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L)

Address: FFE4H After reset: FFH R/W

Symbol

MK0L

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

SREMK6

PMK5

PMK4

PMK3

PMK2

PMK1

PMK0

LVIMK

Address: FFE5H After reset: FFH R/W

Symbol

MK0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMMK010 TMMK000

TMMK50

TMMKH0

TMMKH1 DUALMK0^{Note 1}STMK6

SRMK6

Address: FFE6H After reset: FFH R/W

Symbol

MK1L

7

1

6

1

5

1

4

1

3

1

2

1

<1>

<0>

SRMK0^{Note 2}

ADMK

XXMKX

Interrupt servicing control

0

1

Interrupt servicing enabled

Interrupt servicing disabled

Notes 1. This is CSIMK10 in the µPD78F0101H.

2. µPD78F0102H and 78F0103H only.

Caution Be sure to set bits 2 to 7 of MK1L to 1.

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(3) Priority specification flag registers (PR0L, PR0H, PR1L)

The priority specification flag registers are used to set the corresponding maskable interrupt priority order.

PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are

combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Figure 14-4. Format of Priority Specification Flag Register (PR0L, PR0H, PR1L)

Address: FFE8H After reset: FFH R/W

Symbol

PR0L

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

SREPR6

PPR5

PPR4

PPR3

PPR2

PPR1

PPR0

LVIPR

Address: FFE9H After reset: FFH R/W

Symbol

PR0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMPR010 TMPR000

TMPR50

TMPRH0

TMPRH1 DUALPR0^Note1

STPR6

SRPR6

Address: FFEAH After reset: FFH R/W

Symbol

PR1L

7

1

6

1

5

1

4

1

3

1

2

1

<1>

<0>

SRPR0^{Note 2}

ADPR

XXPRX

Priority level selection

0

1

High priority level

Low priority level

Notes 1. This is CSIPRI0 in the µPD78F0101H.

2. µPD78F0102H and 78F0103H only.

Caution Be sure to set bits 2 to 7 of PR1L to 1.

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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)

These registers specify the valid edge for INTP0 to INTP5.

EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H.

Figure 14-5. Format of External Interrupt Rising Edge Enable Register (EGP)

and External Interrupt Falling Edge Enable Register (EGN)

Address: FF48H After reset: 00H R/W

Symbol

EGP

7

0

6

0

5

4

3

2

1

0

EGP5

EGP4

EGP3

EGP2

EGP1

EGP0

Address: FF49H After reset: 00H R/W

Symbol

EGN

7

0

6

0

5

4

3

2

1

0

EGN5

EGN4

EGN3

EGN2

EGN1

EGN0

EGPn

EGNn

INTPn pin valid edge selection (n = 0 to 5)

0

1

0

1

0

1

Edge detection disabled

Falling edge

Rising edge

Both rising and falling edges

Table 14-3 shows the ports corresponding to EGPn and EGNn.

Table 14-3. Ports Corresponding to EGPn and EGNn

Detection Enable Register

Edge Detection Port

Interrupt Request Signal

INTP0

EGP0

EGP1

EGP2

EGP3

EGP4

EGP5

EGN0

EGN1

EGN2

EGN3

EGN4

EGN5

P120

P30

P31

P32

P33

P16

INTP1

INTP2

INTP3

INTP4

INTP5

Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when

the external interrupt function is switched to the port function.

Remark n = 0 to 5

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(5) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for an

interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple

interrupt servicing are mapped to the PSW.

Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated

instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,

the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt

request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are

transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.

They are restored from the stack with the RETI, RETB, and POP PSW instructions.

RESET input sets PSW to 02H.

Figure 14-6. Format of Program Status Word

After reset

02H

<7> <6> <5> <4> <3>

PSW IE RBS1 AC RBS0

2

0

<1>

ISP

0

Z

CY

Used when normal instruction is executed

ISP

Priority of interrupt currently being serviced

0

High-priority interrupt servicing (low-priority

interrupt disabled)

Interrupt request not acknowledged, or low-

priority interrupt servicing (all maskable

interrupts enabled)

1

IE

0

Interrupt request acknowledgment enable/disable

Disabled

Enabled

1

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CHAPTER 14 INTERRUPT FUNCTIONS

14.4 Interrupt Servicing Operations

14.4.1 Maskable interrupt request acknowledgment

A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask

(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if

interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is

not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).

The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table

14-4 below.

For the interrupt request acknowledgment timing, see Figures 14-8 and 14-9.

Table 14-4. Time from Generation of Maskable Interrupt Request Until Servicing

Minimum Time

7 clocks

8 clocks

Maximum Time^Note

32 clocks

33 clocks

When ××PR = 0

When ××PR = 1

Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.

Remark 1 clock: 1/f^CPU(fCPU: CPU clock)

If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level

specified in the priority specification flag is acknowledged first. If two or more interrupt requests have the same

priority level, the request with the highest default priority is acknowledged first.

An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.

Figure 14-7 shows the interrupt request acknowledgment algorithm.

If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then

PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged

interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the

PC and branched.

Restoring from an interrupt is possible by using the RETI instruction.

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Figure 14-7. Interrupt Request Acknowledgment Processing Algorithm

Start

No

××IF = 1?

Yes (interrupt request generation)

No

××MK = 0?

Yes

Interrupt request held pending

Yes (High priority)

××PR = 0?

No (Low priority)

Any high-priority

Yes

Any high-priority

interrupt request among those

simultaneously generated

with ××PR = 0?

Yes

interrupt request among

those simultaneously generated

with ××PR = 0?

Interrupt request held pending

No

Interrupt request held pending

Yes

No

IE = 1?

Yes

Any high-priority

interrupt request among

those simultaneously

generated?

Interrupt request held pending

No

IE = 1?

Yes

Vectored interrupt servicing

Interrupt request held pending

No

ISP = 1?

Yes

Interrupt request held pending

Vectored interrupt servicing

××IF: Interrupt request flag

××MK: Interrupt mask flag

××PR: Priority specification flag

IE:

Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)

ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt

servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)

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Figure 14-8. Interrupt Request Acknowledgment Timing (Minimum Time)

6 clocks

PSW and PC saved,

jump to interrupt

servicing

Interrupt servicing

program

CPU processing

Instruction

××IF

(××PR = 1)

8 clocks

××IF

(××PR = 0)

7 clocks

Remark 1 clock: 1/fCPU (fCPU: CPU clock)

Figure 14-9. Interrupt Request Acknowledgment Timing (Maximum Time)

25 clocks

6 clocks

PSW and PC saved,

jump to interrupt

servicing

Interrupt servicing

program

CPU processing

Instruction

Divide instruction

××IF

(××PR = 1)

33 clocks

××IF

(××PR = 0)

32 clocks

Remark 1 clock: 1/fCPU (fCPU: CPU clock)

14.4.2 Software interrupt request acknowledgment

A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled.

If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program

status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,

003FH) are loaded into the PC and branched.

Restoring from a software interrupt is possible by using the RETB instruction.

Caution Do not use the RETI instruction for restoring from the software interrupt.

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14.4.3 Multiple interrupt servicing

Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.

Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected

(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).

Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during

interrupt servicing to enable interrupt acknowledgment.

Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to

interrupt priority control. Two types of priority control are available: default priority control and programmable priority

control. Programmable priority control is used for multiple interrupt servicing.

In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt

currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority

lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged

for multiple interrupt servicing.

Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have

a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is

acknowledged following execution of at least one main processing instruction execution.

Table 14-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 14-10

shows multiple interrupt servicing examples.

Table 14-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing

During Interrupt Servicing

Multiple Interrupt Request

Maskable Interrupt Request

PR = 0 PR = 1

Software

Interrupt

Request

Interrupt Being Serviced

IE = 1

IE = 0

IE = 1

IE = 0

Maskable interrupt

ISP = 0

ISP = 1

×

Software interrupt

Remarks 1. : Multiple interrupt servicing enabled

2. ×: Multiple interrupt servicing disabled

3. The ISP and IE are flags contained in the PSW.

ISP = 0: An interrupt with higher priority is being serviced.

ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower

priority is being serviced.

IE = 0: Interrupt request acknowledgment is disabled.

IE = 1: Interrupt request acknowledgment is enabled.

4. PR is a flag contained in PR0L, PR0H, and PR1L.

PR = 0: Higher priority level

PR = 1: Lower priority level

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Figure 14-10. Examples of Multiple Interrupt Servicing (1/2)

Example 1. Multiple interrupt servicing occurs twice

Main processing

INTxx servicing

INTyy servicing

INTzz servicing

IE = 0

EI

INTxx

(PR = 1)

INTyy

(PR = 0)

INTzz

(PR = 0)

RETI

IE = 1

RETI

IE = 1

During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple

interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be

issued to enable interrupt request acknowledgment.

Example 2. Multiple interrupt servicing does not occur due to priority control

Main processing

INTxx servicing

INTyy servicing

EI

IE = 0

INTyy

EI

INTxx

(PR = 0)

(PR = 1)

RETI

IE = 1

1 instruction execution

IE = 0

RETI

IE = 1

Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower

than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,

and is acknowledged following execution of one main processing instruction.

PR = 0: Higher priority level

PR = 1: Lower priority level

IE = 0: Interrupt request acknowledgment disabled

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Figure 14-10. Examples of Multiple Interrupt Servicing (2/2)

Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled

Main processing

INTxx servicing INTyy servicing

IE = 0

EI

INTyy

(PR = 0)

INTxx

RETI

(PR = 0)

IE = 1

IE = 0

1 instruction execution

RETI

IE = 1

Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt

request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request

is held pending, and is acknowledged following execution of one main processing instruction.

PR = 0: Higher priority level

IE = 0: Interrupt request acknowledgment disabled

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CHAPTER 14 INTERRUPT FUNCTIONS

14.4.4 Interrupt request hold

There are instructions where, even if an interrupt request is issued for them while another instruction is being

executed, request acknowledgment is held pending until the end of execution of the next instruction. These

instructions (interrupt request hold instructions) are listed below.

•

MOV PSW, #byte

MOV A, PSW

MOV PSW, A

MOV1 PSW. bit, CY

MOV1 CY, PSW. bit

AND1 CY, PSW. bit

OR1 CY, PSW. bit

XOR1 CY, PSW. bit

SET1 PSW. bit

CLR1 PSW. bit

RETB

RETI

PUSH PSW

POP PSW

BT PSW. bit, $addr16

BF PSW. bit, $addr16

BTCLR PSW. bit, $addr16

EI

DI

Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers

Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,

the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared

to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK

instruction, the interrupt request is not acknowledged.

Figure 14-11 shows the timing at which interrupt requests are held pending.

Figure 14-11. Interrupt Request Hold

PSW and PC saved, jump Interrupt servicing

CPU processing

Instruction N

Instruction M

to interrupt servicing

program

××IF

Remarks 1. Instruction N: Interrupt request hold instruction

2. Instruction M: Instruction other than interrupt request hold instruction

3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).

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CHAPTER 15 STANDBY FUNCTION

15.1 Standby Function and Configuration

15.1.1 Standby function

Table 15-1. Relationship Between Operation Clocks in Each Operation Status

Status

High-Speed System

Clock Oscillator

Internal Oscillator

CPU Clock

After

Prescaler Clock Supplied to

Peripherals

Release

MSTOP = 0 MSTOP = 1

Note 1

Note 2

RSTOP = 0 RSTOP = 1

MCM0 = 0

MCM0 = 1

Operation

Mode

Reset

Stopped

Internal

Stopped

oscillation

STOP

HALT

Oscillating

Stopped

Note 3

Note 4

Oscillating Stopped

Internal

High-speed

oscillation

system clock

Notes 1. When “Cannot be stopped” is selected for the internal oscillator by the option byte.

2. When “Can be stopped by software” is selected for the internal oscillator by the option byte.

3. Operates using the CPU clock at STOP instruction execution.

4. Operates using the CPU clock at HALT instruction execution.

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal oscillator

by the option byte.

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

RSTOP: Bit 0 of the internal oscillation mode register (RCM)

MCM0: Bit 0 of the main clock mode register (MCM)

The standby function is designed to reduce the operating current consumption of the system. The following two

modes are available.

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(1) HALT mode

HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. If

the high-speed system clock and internal oscillator are operating before the HALT mode is set, oscillation of the

high-speed system clock and internal oscillation clock continues. In this mode, operating current is not decreased

as much as in the STOP mode. However, the HALT mode is effective for restarting operation immediately upon

interrupt request generation and carrying out intermittent operations.

(2) STOP mode

STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator

stops, stopping the whole system, thereby considerably reducing the CPU operating current.

Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.

However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is

released, select the HALT mode if it is necessary to start processing immediately upon interrupt request

generation.

In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is

set are held. The I/O port output latches and output buffer statuses are also held.

Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before

executing STOP instruction.

2. The following sequence is recommended for operating current reduction of the A/D converter

when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D

converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute

the HALT or STOP instruction.

3. If the internal oscillator is operating before the STOP mode is set, oscillation of the internal

oscillation clock cannot be stopped in the STOP mode. However, when the internal

oscillation clock is used as the CPU clock, CPU operation is stopped for 17/f^R(s) after STOP

mode is released.

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15.1.2 Registers controlling standby function

The standby function is controlled by the following two registers.

•

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.

(1) Oscillation stabilization time counter status register (OSTC)

This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal

oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be

checked.

OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.

When a reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, or

MSTOP (bit 7 of MOC register) = 1 clears OSTC to 00H.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock

can be switched without reading the OSTC value.

Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)

Address: FFA3H After reset: 00H

R

Symbol

OSTC

7

0

6

0

5

0

4

3

2

1

0

MOST11

MOST13

MOST14

MOST15

MOST16

MOST11

MOST13

MOST14

MOST15

MOST16

Oscillation stabilization time status

fXP = 10 MHz fXP = 16 MHz

1

0

1

0

1

0

1

0

1

2¹¹/fXP min. 204.8 µs min. 128 µs min.

2¹³/fXP min. 819.2 µs min. 512 µs min.

2¹⁴/fXP min. 1.64 ms min. 1.02 ms min.

2¹⁵/fXP min. 3.27 ms min. 2.04 ms min.

2¹⁶/fXP min. 6.55 ms min. 4.09 ms min.

Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and

remain 1.

2. If the STOP mode is entered and then released while the internal oscillation

clock is being used as the CPU clock, set the oscillation stabilization time as

follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The oscillation stabilization time counter counts only during the oscillation

stabilization time set by OSTS. Therefore, note that only the statuses during the

oscillation stabilization time set by OSTS are set to OSTC after STOP mode has

been released.

3. The wait time when STOP mode is released does not include the time after

STOP mode release until clock oscillation starts (“a” below) regardless of

whether STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remark f^XP: High-speed system clock oscillation frequency

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(2) Oscillation stabilization time select register (OSTS)

This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP

mode is released. The wait time set by OSTS is valid only after STOP mode is released when the high-speed

system clock is selected as the CPU clock. After STOP mode is released when the internal oscillation clock is

selected, check the oscillation stabilization time using OSTC.

OSTS can be set by an 8-bit memory manipulation instruction.

RESET input sets OSTS to 05H.

Figure 15-2. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFA4H After reset: 05H R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

1

0

OSTS2

OSTS1

OSTS0

OSTS2

OSTS1

OSTS0

Oscillation stabilization time selection

f^XP= 10 MHz fXP = 16 MHz

204.8 µs 128 µs

0

1

0

1

0

1

0

1

2¹¹/fXP

1

2¹³/fXP

819.2 µs

1.64 ms

3.27 ms

6.55 ms

512 µs

1

2¹⁴/fXP

1.02 ms

2.04 ms

4.09 ms

0

2¹⁵/fXP

0

2¹⁶/fXP

Other than above

Setting prohibited

Cautions 1. To set the STOP mode when the high-speed system clock is used as the CPU

clock, set OSTS before executing a STOP instruction.

2. Execute the OSTS setting after confirming that the oscillation stabilization time

has elapsed as expected in the OSTC.

3. If the STOP mode is entered and then released while the internal oscillation

clock is being used as the CPU clock, set the oscillation stabilization time as

follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The oscillation stabilization time counter counts only during the oscillation

stabilization time set by OSTS. Therefore, note that only the statuses during the

oscillation stabilization time set by OSTS are set to OSTC after STOP mode has

been released.

4. The wait time when STOP mode is released does not include the time after

STOP mode release until clock oscillation starts (“a” below) regardless of

whether STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remark f^XP: High-speed system clock oscillation frequency

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CHAPTER 15 STANDBY FUNCTION

15.2 Standby Function Operation

15.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction. HALT mode can be set when the CPU clock before

the setting was the high-speed system clock or internal oscillation clock.

The operating statuses in the HALT mode are shown below.

Table 15-2. Operating Statuses in HALT Mode

When HALT Instruction Is Executed While

CPU Is Operating Using High-Speed

System Clock

When HALT Instruction Is Executed While

CPU Is Operating on Internal Oscillation

Clock

HALT Mode Setting

When Internal

Oscillation Clock

Continues

When Internal

Oscillation Clock

Stopped^{Note 1}

High-Speed System High-Speed System

Item

Clock Oscillation

Continues

Clock Oscillation

Stopped

System clock

CPU

Clock supply to the CPU is stopped

Operation stopped

Port (output latch)

Holds the status before HALT mode was set

Operable

16-bit timer/event counter 00

8-bit timer/event counter 50

Operation not guaranteed

Operable

Operation not guaranteed when count

clock other than TI50 is selected

8-bit timer H0

Operable

Operation not guaranteed when count

clock other than TM50 output is selected

during 8-bit timer/event counter 50

operation

8-bit timer H1

Operable

Operation not guaranteed when count

clock other than f^R/2⁷is selected

Watchdog

timer

Internal oscillator

cannot be stopped^{Note 2}

Operable

−

Operable

Internal oscillator can Operation stopped

be stopped^{Note 2}

A/D converter

Serial interface

Operable

UART0^{Note 3}Operable

Operation not guaranteed

Operation not guaranteed when serial

clock other than TM50 output is selected

during 8-bit timer/event counter 50

operation

UART6

Operable

CSI10

Operation not guaranteed when serial

clock other than external SCK10 is

selected

Clock monitor

Operable

Operation stopped

Operable

Operation stopped

Power-on-clear function

Low-voltage detection function

External interrupt

Notes 1. When “Stopped by software” is selected for the internal oscillator by the option byte and the internal

oscillator is stopped by software (for the option byte, see CHAPTER 20 OPTION BYTE).

2. “Internal oscillator cannot be stopped” or “Internal oscillator can be stopped by software” can be selected

by the option byte.

3. µPD78F0102H and 78F0103H only.

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(2) HALT mode release

The HALT mode can be released by the following two sources.

(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the HALT mode is released. If interrupt

acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is

disabled, the next address instruction is executed.

Figure 15-3. HALT Mode Release by Interrupt Request Generation

Interrupt

request

HALT

instruction

Wait

Standby

release signal

Operating mode

HALT mode

Operating mode

Status of CPU

Oscillation

High-speed system clock

or internal oscillation clock

Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby

mode is acknowledged.

2. The wait time is as follows:

• When vectored interrupt servicing is carried out:

8 or 9 clocks

• When vectored interrupt servicing is not carried out: 2 or 3 clocks

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(b) Release by RESET input

When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset

operation, the program is executed after branching to the reset vector address.

Figure 15-4. HALT Mode Release by RESET Input

(1) When high-speed system clock is used as CPU clock

HALT

instruction

RESET signal

Operation

stopped

Reset

period

Status of CPU

Operating mode

(High-speed

system clock)

HALT mode

Oscillates

Operating mode

(17/f )

R

(Internal oscillation clock)

Oscillation

stopped

Oscillates

High-speed system clock

Oscillation stabilization time

Note

(2¹¹/fXP to 2¹⁶/fXP

)

Note Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

(2) When internal oscillation clock is used as CPU clock

HALT

instruction

RESET signal

Reset Operation

Operating mode

Status of CPU

HALT mode

Oscillates

Operating mode

period

stopped

(Internal oscillation

clock)

(17/f

R

)

(Internal oscillation clock)

Oscillation

stopped

Oscillates

Internal oscillation

clock

Remarks 1. f^XP: High-speed system clock oscillation frequency

2. f^R: Internal oscillation clock frequency

Table 15-3. Operation in Response to Interrupt Request in HALT Mode

Release Source

MK××

PR××

IE

0

1

0

×

1

×

ISP

×

Operation

Maskable interrupt request

0

1

−

0

1

×

−

Next address instruction execution

Interrupt servicing execution

Next address instruction execution

×

1

0

1

Interrupt servicing execution

HALT mode held

×

RESET input

×

Reset processing

×: Don’t care

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15.2.2 STOP mode

(1) STOP mode setting and operating statuses

The STOP mode is set by executing the STOP instruction. It can be set when the CPU clock before the setting

was the high-speed system clock or internal oscillation clock.

Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt

source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is

immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after

execution of the STOP instruction and the system returns to the operating mode as soon as the

wait time set using the oscillation stabilization time select register (OSTS) has elapsed.

The operating statuses in the STOP mode are shown below.

Table 15-4. Operating Statuses in STOP Mode

When STOP Instruction Is Executed While

CPU Is Operating Using High-Speed System

Clock

When STOP Instruction Is Executed

While CPU Is Operating on Internal

Oscillation Clock

HALT Mode Setting

When Internal

Oscillation Clock

Continues

When Internal

Oscillation Clock

Stopped^{Note 1}

Item

System clock

Only high-speed system clock oscillator oscillation is stopped. Clock supply to the CPU

is stopped.

CPU

Operation stopped

Port (output latch)

Holds the status before STOP mode was set

Operation stopped

16-bit timer/event counter 00

8-bit timer/event counter 50

8-bit timer H0

Operable only when TI50 is selected as count clock

Operable when TM50 output is selected as count clock during 8-bit timer/event counter

50 operation

8-bit timer H1

Operable^{Note 2}

Operation stopped

Operable^{Note 2}

Watchdog

timer

Internal oscillator

cannot be stopped^{Note 3}

Operable

−

Operable

Internal oscillator can Operation stopped

be stopped^{Note 3}

A/D converter

Serial interface

Operation stopped

UART0^{Note 4}Operable only when TM50 output is selected as count clock during 8-bit timer/event

counter 50 operation

UART6

CSI10

Operable only when external SCK10 is selected as serial clock

Clock monitor

Operation stopped

Operable

Power-on-clear function

Low-voltage detection function

External interrupt

Operable

Notes 1. When “Stopped by software” is selected for the internal oscillator by the option byte and the internal

oscillator is stopped by software (for the option byte, see CHAPTER 20 OPTION BYTE).

2. Operable only when f^R/2⁷is selected as count clock.

3. “Internal oscillator cannot be stopped” or “Internal oscillator can be stopped by software” can be selected

by the option byte.

4. µPD78F0102H and 78F0103H only.

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(2) STOP mode release

Figure 15-5. Operation Timing When STOP Mode Is Released

STOP mode release

STOP mode

High-speed system

clock

Internal oscillation

clock

High-speed system

clock is selected as

CPU clock when STOP

instruction is executed

HALT status

(oscillation stabilization time set by OSTS)

High-speed system clock

Internal oscillation

clock is selected as

CPU clock when

STOP instruction

is executed

Internal oscillation

clock

Operation stopped

Clock switched

by software

(17/f )

R

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The STOP mode can be released by the following two sources.

(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation

stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried

out. If interrupt acknowledgment is disabled, the next address instruction is executed.

Figure 15-6. STOP Mode Release by Interrupt Request Generation

(1) When high-speed system clock is used as CPU clock

Interrupt

Wait

request

STOP

instruction

(set by OSTS)

Standby release signal

Status of CPU

Oscillation stabilization

wait status

Operating mode

STOP mode

Oscillation stopped

(High-speed

(High-speed system clock)

system clock)

Oscillates

High-speed system clock

Oscillation stabilization time (set by OSTS)

(2) When internal oscillation clock is used as CPU clock

Interrupt

request

STOP

instruction

Standby release signal

Operation

stopped

Operating mode

STOP mode

Status of CPU

(Internal oscillation

clock)

(Internal oscillation clock)

(17/f )

R

Oscillates

Internal oscillation clock

Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby

mode is acknowledged.

2. f^R: Internal oscillation clock frequency

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CHAPTER 15 STANDBY FUNCTION

(b) Release by RESET input

When the RESET signal is input, STOP mode is released and a reset operation is performed after the

oscillation stabilization time has elapsed.

Figure 15-7. STOP Mode Release by RESET Input

(1) When high-speed system clock is used as CPU clock

STOP

instruction

RESET signal

Reset

period

Operation

stopped

Status of CPU

Operating mode

STOP mode

Operating mode

(High-speed

system clock)

Oscillates

(17/f

R

)

(Internal oscillation clock)

Oscillation

stopped

Oscillation stopped

Oscillates

High-speed system clock

Note

Oscillation stabilization time (2¹¹/fXP to 2¹⁶/fXP

)

Note Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

(2) When internal oscillation clock is used as CPU clock

STOP

instruction

RESET signal

Reset

period

Operation

stopped

Status of CPU

Operating mode

STOP mode

Oscillates

Operating mode

(17/f

R

)

(Internal oscillation clock)

(Internal oscillation

clock)

Oscillation

stopped

Oscillates

Internal oscillation clock

Remarks 1. f^XP: High-speed system clock oscillation frequency

2. fR: Internal oscillation clock frequency

Table 15-5. Operation in Response to Interrupt Request in STOP Mode

Release Source

MK××

PR××

IE

0

1

0

×

1

×

ISP

×

Operation

Maskable interrupt request

0

1

−

0

1

×

−

Next address instruction execution

Interrupt servicing execution

Next address instruction execution

×

1

0

1

Interrupt servicing execution

STOP mode held

×

RESET input

×

Reset processing

×: Don't care

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The following five operations are available to generate a reset signal.

(1) External reset input via RESET pin

(2) Internal reset by watchdog timer program loop detection

(3) Internal reset by clock monitor high-speed system clock oscillation stop detection

(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit

(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)

External and internal resets have no functional differences. In both cases, program execution starts at the address

at 0000H and 0001H when the reset signal is input.

A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, high-speed system

clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of

hardware is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the

oscillation stabilization time just after reset release, except for P130, which is low-level output.

When a high level is input to the RESET pin, the reset is released and program execution starts using the internal

oscillation clock after the CPU clock operation has stopped for 17/f^R(s). A reset generated by the watchdog timer and

clock monitor sources is automatically released after the reset, and program execution starts using the internal

oscillation clock after the CPU clock operation has stopped for 17/f^R(s) (see Figures 16-2 to 16-4). Reset by POC

and LVI circuit power supply detection is automatically released when V^DD> VPOC or VDD > VLVI after the reset, and

program execution starts using the internal oscillation clock after the CPU clock operation has stopped for 17/f^R(s)

(see CHAPTER 18 POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. During reset input, the high-speed system clock and the internal oscillation clock stop

oscillating.

3. When the STOP mode is released by a reset, the STOP mode contents are held during reset

input. However, the port pins become high-impedance, except for P130, which is set to low-

level output.

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Figure 16-2. Timing of Reset by RESET Input

Internal oscillation

clock

High-speed

system clock

Operation stop

Normal operation (reset processing,

internal oscillation clock)

Reset period

(Oscillation stop)

CPU clock

RESET

Normal operation

(17/f )

R

Internal

reset signal

Delay

Port pin

Hi-Z

(except P130)

Note

Port pin (P130)

Note Set P130 to high-level output by software.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

Figure 16-3. Timing of Reset Due to Watchdog Timer Overflow

Internal oscillation

clock

High-speed

system clock

Operation stop

Reset period

(Oscillation stop)

Normal operation (reset processing,

internal oscillation clock)

CPU clock

Normal operation

(17/f )

R

Watchdog timer

overflow

Internal

reset signal

Hi-Z

Port pin

(except P130)

Note

Port pin (P130)

Note Set P130 to high-level output by software.

Caution A watchdog timer internal reset resets the watchdog timer.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after

reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

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Figure 16-4. Timing of Reset in STOP Mode by RESET Input

Internal oscillation

clock

High-speed

system clock

STOP instruction execution

Operation stop

Normal

operation

Normal operation (reset processing,

internal oscillation clock)

Reset period

(Oscillation stop)

Stop status

CPU clock

RESET

(17/f )

R

(Oscillation stop)

Internal

reset signal

Delay

Hi-Z

Port pin

(except P130)

Port pin (P130)

Note

Note Set P130 to high-level output by software.

Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately

after reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 18

POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR.

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Table 16-1. Hardware Statuses After Reset Acknowledgment (1/2)

Hardware

Status After Reset

Acknowledgment^{Note 1}

Program counter (PC)

Stack pointer (SP)

The contents of the

reset vector table

(0000H, 0001H) are

set.

Undefined

02H

Undefined^{Note 2}

Program status word (PSW)

RAM

Data memory

General-purpose registers

Port registers (P0 to P3, P12, P13) (output latches)

00H (undefined only

for P2)

Port mode registers (PM0, PM1, PM3, PM12)

Pull-up resistor option registers (PU0, PU1, PU3, PU12)

Input switch control register (ISC)

FFH

00H

CFH

0CH

00H

05H

00H

0000H

00H

Internal memory size switching register (IMS)

Internal expansion RAM size switching register (IXS)

Processor clock control register (PCC)

Internal oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time select register (OSTS)

Oscillation stabilization time counter status register (OSTC)

16-bit timer/event counter 00

Timer counter 00 (TM00)

Capture/compare registers 000, 010 (CR000, CR010)

Mode control register 00 (TMC00)

Prescaler mode register 00 (PRM00)

Capture/compare control register 00 (CRC00)

Timer output control register 00 (TOC00)

Timer counter 50 (TM50)

8-bit timer/event counter 50

Compare register 50 (CR50)

Timer clock selection register 50 (TCL50)

Mode control register 50 (TMC50)

8-bit timer/event counters H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H

Mode registers (TMHMD0, TMHMD1)

Mode register (WDTM)

00H

Watchdog timer

A/D converter

67H

Enable register (WDTE)

9AH

Conversion result register (ADCR)

Mode register (ADM)

Undefined

00H

Analog input channel specification register (ADS)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

00H

Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses

become undefined. All other hardware statuses remain unchanged after reset.

2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.

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Table 16-1. Hardware Statuses After Reset Acknowledgment (2/2)

Hardware

Status After Reset

Acknowledgment

Serial interface UART0^{Note 1}

Serial interface UART6

Receive buffer register 0 (RXB0)

FFH

Transmit shift register 0 (TXS0)

FFH

01H

1FH

FFH

01H

00H

Asynchronous serial interface operation mode register 0 (ASIM0)

Baud rate generator control register 0 (BRGC0)

Receive buffer register 6 (RXB6)

Transmit buffer register 6 (TXB6)

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6

(ASIS6)

Asynchronous serial interface transmission error status register 6

(ASIF6)

00H

Clock selection register 6 (CKSR6)

00H

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Transmit buffer register 10 (SOTB10)

FFH

16H

Serial interface CSI10

Undefined

00H

Serial I/O shift register 10 (SIO10)

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Mode register (CLM)

00H

Clock monitor

00H

Reset function

Reset control flag register (RESF)

00H^{Note 2}

00H

Low-voltage detector

Low-voltage detection register (LVIM)

Low-voltage detection level selection register (LVIS)

Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)

Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)

Interrupt

FFH

Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) FFH

External interrupt rising edge enable register (EGP)

External interrupt falling edge enable register (EGN)

Flash protect command register (PFCMD)

Flash status register (PFS)

00H

Flash memory

Undefined

00H

Flash programming mode control register (FLPMC)

0XH^{Note 3}

Notes 1. µPD78F0102H and 78F0103H only.

2. These values vary depending on the reset source.

Reset Source

RESET Input

Reset by POC

Cleared (00H)

Reset by WDT

Cleared (00H)

Reset by CLM

Cleared (00H)

Reset by LVI

Register

RESF

LVIM

See Table 16-2.

Cleared (00H)

Held

LVIS

3. Differs depending on the operation mode.

• User mode: 08H

• On-board mode: 0CH

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CHAPTER 16 RESET FUNCTION

16.1 Register for Confirming Reset Source

Many internal reset generation sources exist in the 78K0/KB1+. The reset control flag register (RESF) is used to

store which source has generated the reset request.

RESF can be read by an 8-bit memory manipulation instruction.

RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.

Figure 16-5. Format of Reset Control Flag Register (RESF)

Address: FFACH After reset: 00H^Note

R

Symbol

RESF

7

0

6

0

5

0

4

3

0

2

0

1

0

WDTRF

CLMRF

LVIRF

WDTRF

Internal reset request by watchdog timer (WDT)

0

1

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

CLMRF

Internal reset request by clock monitor (CLM)

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

0

1

LVIRF

Internal reset request by low-voltage detector (LVI)

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

0

1

Note The value after reset varies depending on the reset source.

Caution Do not read data via a 1-bit memory manipulation instruction.

The status of RESF when a reset request is generated is shown in Table 16-2.

Table 16-2. RESF Status When Reset Request Is Generated

Reset Source

RESET input

Reset by POC

Reset by WDT

Reset by CLM

Reset by LVI

Flag

WDTRF

CLMRF

LVIRF

Cleared (0)

Set (1)

Held

Set (1)

Held

Set (1)

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CHAPTER 17 CLOCK MONITOR

17.1 Functions of Clock Monitor

The clock monitor samples the high-speed system clock using the internal oscillator, and generates an internal

reset signal when the high-speed system clock is stopped.

When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set

to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION.

The clock monitor automatically stops under the following conditions.

• Reset is released and during the oscillation stabilization time

• In STOP mode and during the oscillation stabilization time

• When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation

stabilization time

• When the internal oscillation clock is stopped

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

17.2 Configuration of Clock Monitor

The clock monitor includes the following hardware.

Table 17-1. Configuration of Clock Monitor

Item

Configuration

Control register

Clock monitor mode register (CLM)

Figure 17-1. Block Diagram of Clock Monitor

Internal bus

Clock monitor

mode register (CLM)

CLME

High-speed system clock oscillation

control signal (MSTOP)

Operation mode

controller

High-speed system

clock oscillation

monitor circuit

Internal reset

signal

High-speed system clock oscillation

stabilization status (OSTC overflow)

High-speed system clock

Internal oscillation clock

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

OSTC: Oscillation stabilization time counter status register (OSTC)

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CHAPTER 17 CLOCK MONITOR

17.3 Register Controlling Clock Monitor

The clock monitor is controlled by the clock monitor mode register (CLM).

(1) Clock monitor mode register (CLM)

This register sets the operation mode of the clock monitor.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 17-2. Format of Clock Monitor Mode Register (CLM)

Address: FFA9H After reset: 00H R/W

Symbol

CLM

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

CLME

Enables/disables clock monitor operation

CLME

0

1

Disables clock monitor operation

Enables clock monitor operation

Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal

reset signal.

2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)

of the reset control flag register (RESF) is set to 1.

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CHAPTER 17 CLOCK MONITOR

17.4 Operation of Clock Monitor

This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows.

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).

< Monitor stop condition>

• Reset is released and during the oscillation stabilization time

• In STOP mode and during the oscillation stabilization time

• When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation

stabilization time

• When the internal oscillation clock is stopped

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

Table 17-2. Operation Status of Clock Monitor (When CLME = 1)

CPU Operation Clock Operation Mode High-Speed System Clock Internal Oscillation Clock

Status Status

Clock Monitor Status

High-speed system

clock

STOP mode

Stopped

Oscillating

Stopped

Stopped^Note

Oscillating

Stopped^Note

Oscillating

Stopped^Note

RESET input

Normal operation Oscillating

Operating

Stopped

mode

HALT mode

Internal oscillation

clock

STOP mode

RESET input

Stopped

Oscillating

Stopped

Normal operation Oscillating

Operating

Stopped

mode

Stopped

HALT mode

Note The internal oscillation clock is stopped only when the “Internal oscillator can be stopped by software” is

selected by the option byte. If “Internal oscillator cannot be stopped” is selected, the internal oscillation

clock cannot be stopped.

The clock monitor timing is as shown in Figure 17-3.

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Figure 17-3. Timing of Clock Monitor (1/4)

(1) When internal reset is executed by oscillation stop of high-speed system clock

4 clocks of internal oscillation clock

High-speed

system clock

Internal oscillation clock

Internal reset signal

CLME

CLMRF

(2) Clock monitor status after RESET input

(CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time)

Clock supply

stopped

Normal

operation

Normal operation (internal oscillation clock)

CPU operation

Reset

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

Internal oscillation clock

RESET

Oscillation

stopped

17 clocks

Set to 1 by software

CLME

Clock monitor status

Monitoring

Monitoring stopped

Monitoring

Waiting for end

of oscillation

stabilization time

RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor

operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register

is 05H (2¹⁶/fXP)) of the high-speed system clock, monitoring is not performed until the oscillation stabilization time of

the high-speed system clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock

can be switched without reading the OSTC value. However, the clock monitor starts operation

after the oscillation stabilization time (OSTS register reset value = 05H (2¹⁶/fXP)) has elapsed.

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Figure 17-3. Timing of Clock Monitor (2/4)

(3) Clock monitor status after RESET input

(CLME = 1 is set after RESET input and at the end of high-speed system clock oscillation stabilization time)

Normal

operation

Clock supply

stopped

CPU operation

Reset

Normal operation (internal oscillation clock)

High-speed

system clock

Oscillation stabilization time

Internal oscillation clock

RESET

17 clocks

Set to 1 by software

Monitoring

CLME

Clock monitor status

Monitoring

Monitoring stopped

RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor

operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS

register is 05H (2¹⁶/fXP)) of the high-speed system clock, monitoring is started.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock

can be switched without reading the OSTC value. However, the clock monitor starts operation

after the oscillation stabilization time (OSTS register reset value = 05H (2¹⁶/fXP)) has elapsed.

(4) Clock monitor status after STOP mode is released

(CLME = 1 is set when CPU clock operates on high-speed system clock and before entering STOP mode)

Normal

operation

Normal operation

Oscillation stabilization time

CPU operation

STOP

High-speed system

clock (CPU clock)

Oscillation

stopped

Oscillation stabilization time

(time set by OSTS register)

Internal oscillation clock

CLME

Clock monitor status

Monitoring

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring

automatically starts at the end of the high-speed system clock oscillation stabilization time. Monitoring is stopped in

STOP mode and during the oscillation stabilization time.

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Figure 17-3. Timing of Clock Monitor (3/4)

(5) Clock monitor status after STOP mode is released

(CLME = 1 is set when CPU clock operates on internal oscillation clock and before entering STOP mode)

Clock supply

stopped

Normal

operation

Normal operation

STOP

CPU operation

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

(time set by OSTS register)

Internal oscillation clock

(CPU clock)

17 clocks

CLME

Clock monitor status

Monitoring

stopped

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring

automatically starts at the end of the high-speed system clock oscillation stabilization time. Monitoring is stopped in

STOP mode and during the oscillation stabilization time.

(6) Clock monitor status after high-speed system clock oscillation is stopped by software

CPU operation

Normal operation (internal oscillation clock)

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

(time set by OSTS register)

Internal oscillation clock

MSTOP

CLME

Clock monitor status

Monitoring

stopped

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the high-

speed system clock is stopped, monitoring automatically starts at the end of the high-speed system clock oscillation

stabilization time. Monitoring is stopped when oscillation of the high-speed system clock is stopped and during the

oscillation stabilization time.

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Figure 17-3. Timing of Clock Monitor (4/4)

(7) Clock monitor status after internal oscillation clock is stopped by software

Normal operation (high-speed system clock)

CPU operation

High-speed

system clock

Internal oscillation clock

RSTOP^Note

Oscillation stopped

CLME

Clock monitor status

Monitoring

stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the internal

oscillation clock is stopped, monitoring automatically starts after the internal oscillation clock is stopped. Monitoring is

stopped when oscillation of the internal oscillation clock is stopped.

Note If it is specified by the option byte that the internal oscillator cannot be stopped, the setting of bit 0 (RSTOP)

of the internal oscillation mode register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS)

of the main clock mode register (MCM) is 1.

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.1 Functions of Power-on-Clear Circuit

The power-on-clear circuit (POC) has the following functions.

•

Generates internal reset signal at power on.

Compares supply voltage (V^DD) and detection voltage (VPOC), and generates internal reset signal when VDD <

V^POC.

Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register

(RESF) is cleared to 00H.

2. The supply voltage is V^DD= 2.0 to 5.5 V when the internal oscillation clock is used, but be

sure to use the standard products and (A) grade products in a voltage range of 2.2 to 5.5 V

because the detection voltage (V^POC) of the POC circuit is 2.1 V 0.1 V.

<R>

3. The supply voltage is V^DD= 2.0 to 5.5 V when the internal oscillation clock is used, but be

sure to use the (A1) grade products in a voltage range of 2.25 to 5.5 V because the detection

voltage (V^POC) of the POC circuit is 2.0 to 2.25 V.

Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that

indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset

signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor.

RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT,

LVI, or the clock monitor.

For details of the RESF, see CHAPTER 16 RESET FUNCTION.

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.2 Configuration of Power-on-Clear Circuit

A block diagram of the power-on-clear circuit is shown in Figure 18-1.

Figure 18-1. Block Diagram of Power-on-Clear Circuit

V

DD

V

DD

+

Internal reset signal

−

Reference

voltage

source

18.3 Operation of Power-on-Clear Circuit

In the power-on-clear circuit, the supply voltage (V^DD) and detection voltage (VPOC) are compared, and when VDD <

VPOC, an internal reset signal is generated.

Figure 18-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit

Supply voltage (V^DD

)

POC detection voltage

(V^POC

)

Time

Internal reset signal

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.4 Cautions for Power-on-Clear Circuit

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection

voltage (V^POC), the system may be repeatedly reset and released from the reset status. In this case, the time from

release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports.

Figure 18-3. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage

; The internal oscillation clock is set as the CPU clock when

the reset signal is generated

Reset

Checking cause

of reset^{Note 2}

; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)

can be identified by the RESF register.

Power-on-clear

; 8-bit timer H1 can operate with the internal oscillation clock.

Start timer

(set to 50 ms)

Source: f

R

(480 kHz (MAX.))/2⁷× compare value 200 = 53 ms

(fR: internal oscillation clock frequency)

Check stabilization

of oscillation

; Check the stabilization of oscillation of the high-speed system clock by using

the OSTC register^{Note 3}

Note 1

.

; Change the CPU clock from the internal oscillation clock

to the high-speed system clock.

Change CPU clock

No

50 ms has passed?

(TMIFH1 = 1?)

; TMIFH1 = 1: Interrupt request is generated.

Yes

Initialization

processing

; Initialization of ports

Notes 1. If reset is generated again during this period, initialization processing is not started.

2. A flowchart is shown on the next page.

3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

Figure 18-3. Example of Software Processing After Release of Reset (2/2)

• Checking reset cause

Check reset cause

Yes

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

CLMRF of RESF

register = 1?

No

Reset processing by

clock monitor

LVIRF of RESF

register = 1?

No

Reset processing by

low-voltage detector

Power-on-clear/external

reset generated

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.1 Functions of Low-Voltage Detector

The low-voltage detector (LVI) has following functions.

•

Compares supply voltage (V^DD) and detection voltage (VLVI), and generates an internal interrupt signal or

internal reset signal when VDD < VLVI.

•

Detection levels (nine levels) of supply voltage can be changed by software.

Interrupt or reset function can be selected by software.

Operable in STOP mode.

When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if

reset occurs. For details of RESF, see CHAPTER 16 RESET FUNCTION.

19.2 Configuration of Low-Voltage Detector

A block diagram of the low-voltage detector is shown below.

Figure 19-1. Block Diagram of Low-Voltage Detector

VDD

N-ch

Internal reset signal

+

−

INTLVI

Reference

voltage

source

4

LVIF

LVIMD

LVION

LVIS3 LVIS2 LVIS1 LVIS0

Low-voltage detection level

Low-voltage detection register

(LVIM)

selection register (LVIS)

Internal bus

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.3 Registers Controlling Low-Voltage Detector

The low-voltage detector is controlled by the following registers.

•

Low-voltage detection register (LVIM)

Low-voltage detection level selection register (LVIS)

(1) Low-voltage detection register (LVIM)

This register sets low-voltage detection and the operation mode.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

A reset other than LVI clears LVIM to 00H.

Figure 19-2. Format of Low-Voltage Detection Register (LVIM)

Address: FFBEH After reset: 00H R/W^{Note 1}

<7>

6

0

5

0

4

3

0

2

0

<1>

<0>

Symbol

LVIM

LVION

0^{Note 2}

LVIMD

LVIF

LVION^{Notes 3, 4}

Enables low-voltage detection operation

0

1

Disables operation

Enables operation

LVIMD^{Note 3}

Low-voltage detection operation mode selection

Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)

0

1

Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)

LVIF^{Note 5}

Low-voltage detection flag

Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is disabled

Supply voltage (VDD) < detection voltage (VLVI)

0

1

Notes 1. Bit 0 is read-only.

2. Bit 4 may be 0 or 1. This bit corresponds to the LVIE bit in the 78K0/KB1.

3. LVION and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are

not cleared to 0 in the case of an LVI reset.

4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use

software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is

confirmed at LVIF.

5. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and

LVIMD = 0.

Caution To stop LVI, follow either of the procedures below.

• When using 8-bit manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

(2) Low-voltage detection level selection register (LVIS)

This register selects the low-voltage detection level.

This register can be set by an 8-bit memory manipulation instruction.

RESET input clears LVIS to 00H.

Figure 19-3. Format of Low-Voltage Detection Level Selection Register (LVIS)

Address: FFBFH After reset: 00H R/W

7

0

6

0

5

0

4

0

3

2

1

0

Symbol

LVIS

LVIS3

LVIS2

LVIS1

LVIS0

LVIS3

LVIS2

LVIS1

LVIS0

Detection level^Note

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VLVI0 (4.3 V 0.2 V)

VLVI1 (4.1 V 0.2 V)

VLVI2 (3.9 V 0.2 V)

VLVI3 (3.7 V 0.2 V)

VLVI4 (3.5 V 0.2 V)

VLVI5 (3.3 V 0.15 V)

VLVI6 (3.1 V 0.15 V)

VLVI7 (2.85 V 0.15 V)

VLVI8 (2.6 V 0.1 V)^Note

VLVI9 (2.35 V 0.1 V)^Note

Setting prohibited

Other than above

<R>

Note Do not set VLVI8 or VLVI9 when using the standard products and (A) grade products to evaluate the

program of a mask ROM version of the 78K0/KB1 or when using the (A1) grade products.

Cautions 1. Be sure to clear bits 4 to 7 to 0.

2. Clear all port pins after the supply voltage (V^DD) exceeds the preset detection

voltage (V^LVI) after POC release in the (A1) grade products.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.4 Operation of Low-Voltage Detector

The low-voltage detector can be used in the following two modes.

•

Used as reset

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an internal reset signal when

V^DD< VLVI.

Used as interrupt

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)

when V^DD< VLVI.

The operation is set as follows.

(1) When used as reset

•

When starting operation

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Confirm that “supply voltage (V^DD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM.

<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V^DD) < detection

voltage (VLVI)).

Figure 19-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers

in this timing chart correspond to <1> to <6> above.

Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately

after the processing in <3>.

2. If supply voltage (V^DD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset

signal is not generated.

•

When stopping operation

Either of the following procedures must be executed.

•

When using 8-bit memory manipulation instruction:

Write 00H to LVIM.

•

When using 1-bit memory manipulation instruction:

Clear LVIMD to 0 first, and then clear LVION to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-4. Timing of Low-Voltage Detector Internal Reset Signal Generation

Supply voltage (VDD

)

LVI detection voltage

(VLVI

)

POC detection voltage

(V^POC

)

Time

<2>

H

LVIMK flag

(set by software)

<1>^{Note 1}

LVION flag

(set by software)

Not cleared

<3>

Clear

<4> 0.2 ms or longer

LVIF flag

Clear

<5>

Note 2

LVIMD flag

(set by software)

Not cleared

<6>

LVIRF flag^{Note 3}

LVI reset signal

POC reset signal

Cleared by

software

Cleared by

software

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by RESET input.

2. The LVIF flag may be set (1).

3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 16

RESET FUNCTION.

Remark <1> to <6> in Figure 19-4 above correspond to <1> to <6> in the description of “when starting operation”

in 19.4 (1) When used as reset.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

(2) When used as interrupt

When starting operation

•

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Confirm that “supply voltage (V^DD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM.

<6> Clear the interrupt request flag of LVI (LVIIF) to 0.

<7> Release the interrupt mask flag of LVI (LVIMK).

<8> Execute the EI instruction (when vector interrupts are used).

Figure 19-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in

this timing chart correspond to <1> to <7> above.

•

When stopping operation

Either of the following procedures must be executed.

• When using 8-bit memory manipulation instruction:

Write 00H to LVIM.

• When using 1-bit memory manipulation instruction:

Clear LVION to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-5. Timing of Low-Voltage Detector Interrupt Signal Generation

Supply voltage (VDD

)

LVI detection voltage

(VLVI

)

POC detection voltage

(V^POC

)

Time

<2>

LVIMK flag

(set by software)

<1>^{Note 1}

<7> Cleared by software

LVION flag

(set by software)

<3>

<4> 0.2 ms or longer

<5>

LVIF flag

INTLVI

Note 2

LVIIF flag

<6>

Cleared by software

Note 2

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by RESET input.

2. The LVIF and LVIIF flags may be set (1).

Remark <1> to <7> in Figure 19-5 above correspond to <1> to <7> in the description of “when starting operation”

in 19.4 (2) When used as interrupt.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.5 Cautions for Low-Voltage Detector

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage

(V^LVI), the operation is as follows depending on how the low-voltage detector is used.

(1) When used as reset

The system may be repeatedly reset and released from the reset status.

In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set

by taking action (a) below.

(2) When used as interrupt

Interrupt requests may be frequently generated. Take action (b) below.

In this system, take the following actions.

(a) When used as reset

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-6. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage

; The internal oscillation clock is set as the CPU clock

when the reset signal is generated

Reset

Checking cause

of reset^{Note 2}

; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)

can be identified by the RESF register.

LVI

; 8-bit timer H1 can operate with the internal oscillation clock.

Start timer

(set to 50 ms)

Source: f

R

(480 kHz (MAX.))/2⁷× compare value 200 = 53 ms

(fR: internal oscillation clock frequency)

Check stabilization

of oscillation

; Check the stabilization of oscillation of the high-speed system clock

by using the OSTC register^{Note 3}

Note 1

.

; Change the CPU clock from the internal oscillation clock

to the high-speed system clock.

Change CPU clock

No

50 ms has passed?

(TMIFH1 = 1?)

; TMIFH1 = 1: Interrupt request is generated.

Yes

Initialization

processing

; Initialization of ports

Notes 1. If reset is generated again during this period, initialization processing is not started.

2. A flowchart is shown on the next page.

3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is

selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be

switched without reading the OSTC value.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-6. Example of Software Processing After Release of Reset (2/2)

• Checking reset cause

Check reset cause

Yes

No

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

CLMRF of RESF

register = 1?

No

Reset processing by

clock monitor

LVIRF of RESF

register = 1?

Yes

Power-on-clear/external

reset generated

Reset processing by

low-voltage detector

(b) When used as interrupt

Check that “supply voltage (V^DD) ≥ detection voltage (VLVI)” in the servicing routine of the LVI interrupt by using bit

0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L)

to 0 and enable interrupts (EI).

In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for

the supply voltage fluctuation period, check that “supply voltage (V^DD) ≥ detection voltage (VLVI)” using the LVIF

flag, and then enable interrupts (EI).

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<R>

CHAPTER 20 OPTION BYTE

20.1 Functions of Option Bytes

The flash memory at 0080H to 0084H of the 78K0/KB1+ is an option byte area. When power is turned on or when

the device is restarted from the reset status, the device automatically references the option bytes and sets specified

functions. When using the product, be sure to set the following functions by using the option bytes.

When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H.

Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance.

{0080H/1080H

1. Selection of high-speed system clock oscillation

• Crystal/ceramic oscillator

• External RC oscillator

2. Internal oscillator operation

• Can be stopped by software

• Cannot be stopped

Caution Be sure to set 00H to 0081H, 0082H, 0083H, and 0084H (0081H/1081H, 0082H/1082H, 0083H/1083H,

and 0084H/1084H when the boot swap function is used).

20.2 Format of Option Byte

The format of the option byte is shown below.

Figure 20-1. Format of Option Byte (1/2)

Address: 0080H/1080H^Note

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OSCSEL0

LSROSC

OSCSEL0

Selection of high-speed system clock oscillation

0

1

Crystal/ceramic oscillator

External RC oscillator

LSROSC

Internal oscillator operation

0

1

Can be stopped by software (stopped when 1 is written to bit 0 (RSTOP) of RCM register)

Cannot be stopped (not stopped even if 1 is written to RSTOP bit)

Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the

boot swap operation.

Cautions 1. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the

watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (RSTOP) of

the internal oscillation mode register (RCM).

When 8-bit timer H1 operates with the internal oscillation clock, the count clock is supplied to

8-bit timer H1 even in the HALT/STOP mode.

2. Be sure to clear bit 2 to 7 to 0.

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CHAPTER 20 OPTION BYTE

Figure 20-1. Format of Option Byte (2/2)

Address: 0081H/1081H, 0082H/1082H, 0083H/1083H^Note

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Note Be sure to set 00H to 0081H, 0082H, and 0083H, as these addresses are reserved areas. Also set 00H to

1081H, 1082H, and 1083H because 0081H, 0082H, and 0083H are switched with 1081H, 1082H, and

1083H when the boot swap operation is used.

Address: 0084H/1084H^Note

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OCDEN1

OCDEN0

OCDEN1

0

OCDEN0

0

On-chip debug operation control

Operation disabled

Setting prohibited

Other than above

Note Be sure to set 00H (on-chip debug operation disabled) to 0084H, as 78K0/KB1+ has not equipped the on-

chip debug function. Also set 00H to 1084H because 0084H and 1084H are switched at boot swapping.

Here is an example of description of the software for setting the option bytes.

OPT

CSEG AT 0080H

OPTION: DB

00H

; Crystal/ceramic oscillator

; Internal oscillator can be stopped by software.

; Reserved area

DB

00H

; Reserved area

; On-chip debug operation disabled

Remark Referencing of the option byte is performed during reset processing. For the reset processing timing,

see CHAPTER 16 RESET FUNCTION.

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CHAPTER 21 FLASH MEMORY

The µPD78F0101H, 78F0102H, and 78F0103H replace the µPD780101, 780102, and 780103 of the 78K0/KB1

with flash memory to which a program can be written, erased, and overwritten while mounted on the board. Table 21-

1 lists the differences between the 78K0/KB1+ and the 78K0/KB1.

Table 21-1. Differences Between 78K0/KB1+ and 78K0/KB1

Item

78K0/KB1+

78K0/KB1

µPD78F0101H, 78F0102H,

µPD78F0103

µPD780101, 780102,

78F0103H

780103

Internal ROM

Flash memory

Mask ROM

configuration

(single power supply)

(two power supplies)

Internal ROM capacity

µPD78F0101H: 8 KB

µPD78F0102H: 16 KB

µPD78F0103H: 24 KB

µPD78F0103: 24 KB^Note

µPD780101: 8 KB

µPD780102: 16 KB

µPD780103: 24 KB

Internal high-speed RAM

capacity

µPD78F0101H: 512 bytes

µPD78F0102H: 768 bytes

µPD78F0103H: 768 bytes

µPD78F0103: 768 bytes^Note

µPD780101: 512 bytes

µPD780102: 768 bytes

µPD780103: 768 bytes

Pin 5

FLMD0 pin

VPP pin

IC pin

Pin 22

P17/TI50/TO50/FLMD1 pin

P17/TI50/TO50 pin

Enabling use of POC and

Power-on clear (POC)

function

Detection voltage is fixed

(V^POC= 2.1 V 0.1 V)

Enabling use of POC and

detection voltage selectable detection voltage selectable

by product

by mask option

Self-programming function Available

Electrical specifications

None

−

Refer to the electrical specifications chapter in the user’s manual of each product.

Note The same capacity as the mask ROM versions can be specified by means of the internal memory size

switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and

mask ROM versions. When pre-producing an application set with the flash memory version

and then mass-producing it with the mask ROM version, be sure to conduct sufficient

evaluations for the commercial samples (not engineering samples) of the mask ROM versions.

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CHAPTER 21 FLASH MEMORY

21.1 Internal Memory Size Switching Register

The internal memory capacity can be selected using the internal memory size switching register (IMS).

IMS is set by an 8-bit memory manipulation instruction.

RESET input sets IMS to CFH.

Caution The initial value of IMS is “setting prohibited (CFH)”. Be sure to set the value shown in Table 21-

2 for each product at initialization. When using the 78K0/KB1+ to evaluate the program of a mask

ROM version of the 78K0/KB1, be sure to set the values shown in Table 21-2.

Figure 21-1. Format of Internal Memory Size Switching Register (IMS)

Address: FFF0H After reset: CFH R/W

Symbol

IMS

7

6

5

4

0

3

2

1

0

RAM2

RAM1

RAM0

ROM3

ROM2

ROM1

ROM0

RAM2

RAM1

RAM0

Internal high-speed RAM capacity selection

0

768 bytes

512 bytes

1

Other than above

Setting prohibited

ROM3

ROM2

ROM1

ROM0

Internal ROM capacity selection

0

1

0

1

0

8 KB

16 KB

24 KB

Other than above

Setting prohibited

The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 21-2.

Table 21-2. Internal Memory Size Switching Register Settings

Flash Memory Version

(78K0/KB1+)

Target Mask ROM Version

(78K0/KB1)

Internal Memory Size

Switching Register (IMS)

µPD78F0101H

µPD78F0102H

µPD78F0103H

µPD780101

µPD780102

µPD780103

42H

04H

06H

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CHAPTER 21 FLASH MEMORY

21.2 Writing with Flash Programmer

Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer.

(1) On-board programming

The contents of the flash memory can be rewritten after the 78K0/KB1+ has been mounted on the target system.

The connectors that connect the dedicated flash programmer must be mounted on the target system.

(2) Off-board programming

Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/KB1+ is

mounted on the target system.

Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.

Table 21-3. Wiring Between 78K0/KB1+ and Dedicated Flash Programmer

Pin Configuration of Dedicated Flash Programmer

With CSI10

With CSI10 + HS

With UART6

Signal Name

SI/RxD

I/O

Pin Function

Receive signal

Pin Name

Pin No.

17

Pin Name

SO10/P12

Pin No.

Pin Name

Pin No.

18

Input

SO10/P12

17

16

TxD6/P13

RxD6/P14

SO/TxD

Output Transmit signal

Output Transfer clock

Output Clock to 78K0/KB1+

SI10/RxD0/

P11

16

SI10/RxD0/

P11

19

SCK

CLK

SCK10/TxD0/

P10

15

SCK10/TxD0/

P10

15

Not needed

Not

needed

X1[CL1]

X2[CL2]^Note

RESET

8

9

X1[CL1]

X2[CL2]^Note

RESET

8

9

X1[CL1]

X2[CL2]^Note

RESET

8

9

/RESET

FLMD0

FLMD1

Output Reset signal

Output Mode signal

10

5

10

5

10

5

FLMD0

FLMD1/TI50/

TO50/P17

22

FLMD1/TI50/

TO50/P17

22

FLMD1/TI50/

TO50/P17

22

H/S

Input

I/O

Handshake signal

Not needed

Not

HS/P15/TOH0

20

Not needed

Not

needed

VDD

V^DDvoltage generation/

voltage monitoring

VDD

7

28

6

VDD

7

28

6

VDD

7

28

6

AV^REF

VSS

AVREF

VSS

AVREF

VSS

GND

−

Ground

AV^SS

29

AVSS

29

AVSS

29

Note When using the clock out of the flash programmer, connect CLK of the programmer to X1[CL1], and connect

its inverse signal to X2[CL2].

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CHAPTER 21 FLASH MEMORY

Examples of the recommended connection when using the adapter for flash memory writing are shown below.

Figure 21-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode

VDD (2.7 to 5.5 V)

GND

1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

2

3

4

5

6

7

8

9

10

11

12

13

14

15

GND

VDD

LVDD

FLASH WRITER

INTERFACE

SI SO SCK

CLK

/RESET FLMD0

FLMD1

HS

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Figure 21-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode

V

DD (2.7 to 5.5 V)

GND

1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

2

3

4

5

6

7

8

9

10

11

12

13

14

15

GND

VDD

LVDD

FLASH WRITER

INTERFACE

HS

SI SO SCK

CLK

/RESET FLMD0

FLMD1

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Figure 21-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode

VDD (2.7 to 5.5 V)

GND

1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

2

3

4

5

6

7

8

9

10

11

12

13

14

15

GND

VDD

LVDD

FLASH WRITER

INTERFACE

SI SO SCK

CLK

/RESET FLMD0

HS

FLMD1

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21.3 Programming Environment

The environment required for writing a program to the flash memory of the 78K0/KB1+ is illustrated below.

Figure 21-5. Environment for Writing Program to Flash Memory

FLMD0

FLMD1

Axxxx

RS-232C

Bxxxxx

Cxxxxxx

A

TVE

(F^Sl^Tash Pro4)

VDD

PG-FP4

V

SS

USB

78K0/KB1+

Dedicated flash

programmer

RESET

CSI10/UART6

Host machine

A host machine that controls the dedicated flash programmer is necessary.

To interface between the dedicated flash programmer and the 78K0/KB1+, CSI10 or UART6 is used for

manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA

series) is necessary.

21.4 Communication Mode

Communication between the dedicated flash programmer and the 78K0/KB1+ is established by serial

communication via CSI10 or UART6 of the 78K0/KB1+.

(1) CSI10

Transfer rate: 2.4 kHz to 2.5 MHz

Figure 21-6. Communication with Dedicated Flash Programmer (CSI10)

FLMD0

FLMD1

FLMD0

FLMD1

V

DD

V

DD/AVREF

SS/AVSS

Axxxx

GND

/RESET

SI/RxD

SO/TxD

SCK

Bxxxxx

Cxxxxxx

(F^Sl^Tash Pro4)

A

TVE

PG-FP4

RESET

SO10

SI10

78K0/KB1+

Dedicated flash

programmer

SCK10

X1[CL1]

X2[CL2]

CLK

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(2) CSI communication mode supporting handshake

Transfer rate: 2.4 kHz to 2.5 MHz

Figure 21-7. Communication with Dedicated Flash Programmer (CSI10 + HS)

FLMD0

FLMD1

FLMD0

FLMD1

V

DD

V

DD/AVREF

SS/AVSS

GND

/RESET

SI/RxD

SO/TxD

SCK

Axxxx

Bxxxxx

Cxxxxxx

RESET

SO10

SI10

A

TVE

(F^Sl^Tash Pro4)

PG-FP4

78K0/KB1+

Dedicated flash

programmer

SCK10

X1[CL1]

X2[CL2]

HS

CLK

H/S

(3) UART6

Transfer rate: 9600 to 153600 bps

Figure 21-8. Communication with Dedicated Flash Programmer (UART6)

FLMD0

FLMD1

FLMD0

FLMD1

V

DD

V

DD/AVREF

SS/AVSS

GND

/RESET

SI/RxD

SO/TxD

CLK

V

Axxxx

Bxxxxx

Cxxxxxx

RESET

TxD6

(F^Sl^Tash Pro4)

A

TVE

PG-FP4

RxD6

78K0/KB1+

Dedicated flash

programmer

X1[CL1]

X2[CL2]

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If FlashPro4 is used as the dedicated flash programmer, FlashPro4 generates the following signal for the

78K0/KB1+. For details, refer to the FlashPro4 Manual.

Table 21-4. Pin Connection

FlashPro4

78K0/KB1+

Pin Name

Connection

Signal Name

FLMD0

FLMD1

VDD

I/O

Output

Pin Function

CSI10

UART6

Mode signal

FLMD0

Output

I/O

FLMD1

VDD voltage generation/voltage monitoring

Ground

VDD, AVREF

VSS, AVSS

X1[CL1], X2[CL2]^Note

RESET

GND

−

CLK

Output

Input

Clock output to 78K0/KB1+

Reset signal

{

/RESET

SI/RxD

SO/TxD

SCK

Receive signal

SO10/TxD6

SI10/RxD6

SCK10

Output

Input

Transmit signal

Transfer clock

×

H/S

Handshake signal

HS

Note When using the clock out of the flash programmer, connect CLK of the programmer to X1[CL1], and connect its

inverse signal to X2[CL2].

Remark

: Be sure to connect the pin.

{: The pin does not have to be connected if the signal is generated on the target board.

×: The pin does not have to be connected.

: In handshake mode

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21.5 Connection of Pins on Board

To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on

the target system. First provide a function that selects the normal operation mode or flash memory programming

mode on the board.

When the flash memory programming mode is set, all the pins not used for programming the flash memory are in

the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately

after reset, the pins must be connected as described below.

21.5.1 FLMD0 pin

In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the V^DD

write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below.

Figure 21-9. FLMD0 Pin Connection Example

78K0/KB1+

Dedicated flash programmer connection pin

FLMD0

21.5.2 FLMD1 pin

When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin,

the flash memory programming mode is entered, so the FLMD1 pin must be the same voltage as V^SS. An FLMD1 pin

connection example is shown below.

Figure 21-10. FLMD1 Pin Connection Example

78K0/KB1+

Dedicated flash programmer

Signal collision

connection pin

Other device

Output pin

FLMD1

If the VDD signal is input to the FLMD1 pin from another device during

on-board programming and immediately after reset, isolate this signal.

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21.5.3 Serial interface pins

The pins used by each serial interface are listed below.

Table 21-5. Pins Used by Each Serial Interface

Serial Interface

Pins Used

SO10, SI10, SCK10

SO10, SI10, SCK10, HS/P15

TxD6, RxD6

CSI10

CSI10 + HS

UART6

To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on

the board, care must be exercised so that signals do not collide or that the other device does not malfunction.

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(1) Signal collision

If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another

device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other

device, or make the other device go into an output high-impedance state.

Figure 21-11. Signal Collision (Input Pin of Serial Interface)

78K0/KB1+

Dedicated flash programmer

Signal collision

connection pin

Other device

Output pin

Input pin

In the flash memory programming mode, the signal output by the device

collides with the signal sent from the dedicated flash programmer.

Therefore, isolate the signal of the other device.

(2) Malfunction of other device

If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface

connected to another device (input), a signal may be output to the other device, causing the device to malfunction.

To avoid this malfunction, either isolate the connection with the other device.

Figure 21-12. Malfunction of Other Device

78K0/KB1+

Dedicated flash programmer

connection pin

Other device

Input pin

If the signal output by the 78K0/KB1+ in the flash memory programming

mode affects the other device, isolate the signal of the other device.

78K0/KB1+

Dedicated flash programmer

connection pin

Other device

Input pin

If the signal output by the dedicated flash programmer in the flash memory

programming mode affects the other device, isolate the signal of the other

device.

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CHAPTER 21 FLASH MEMORY

21.5.4 RESET pin

If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset

signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the

reset signal generator.

If the reset signal is input from the user system while the flash memory programming mode is set, the flash

memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash

programmer.

Figure 21-13. Signal Collision (RESET Pin)

78K0/KB1+

Dedicated flash programmer

Signal collision

connection signal

Reset signal generator

Output pin

RESET

In the flash memory programming mode, the signal output by the reset

signal generator collides with the signal output by the dedicated flash

programmer. Therefore, isolate the signal of the reset signal generator.

21.5.5 Port pins

When the flash memory programming mode is set, all the pins not used for flash memory programming enter the

same status as that immediately after reset. If external devices connected to the ports do not recognize the port

status immediately after reset, the port pin must be connected to V^DDor VSS via a resistor.

21.5.6 Other signal pins

Connect X1[CL1] and X2[CL2] in the same status as in the normal operation mode when using the on-board clock.

To input the operating clock from the programmer, however, connect the clock out of the programmer to X1[CL1],

and its inverse signal to X2[CL2].

21.5.7 Power supply

To use the supply voltage output of the flash programmer, connect the V^DDpin to VDD of the flash programmer, and

the V^SSpin to VSS of the flash programmer.

To use the on-board supply voltage, connect in compliance with the normal operation mode.

However, be sure to connect the V^DDand VSS pins to VDD and GND of the flash programmer, respectively, because

the power is monitored by the flash programmer.

Supply the same other power supplies (AV^REFand AVSS) as those in the normal operation mode.

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21.6 Programming Method

21.6.1 Controlling flash memory

The following figure illustrates the procedure to manipulate the flash memory.

Figure 21-14. Flash Memory Manipulation Procedure

Start

Flash memory programming

FLMD0 pulse supply

mode is set

Selecting communication mode

Manipulate flash memory

No

End?

Yes

End

21.6.2 Flash memory programming mode

To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/KB1+ in the

flash memory programming mode. To set the mode, set the FLMD0 pin to V^DDand clear the reset signal.

Change the mode by using a jumper when writing the flash memory on-board.

Figure 21-15. Flash Memory Programming Mode

5.5 V

V

DD

0 V

V

DD

RESET

0 V

FLMD0 pulse

V

DD

FLMD0

FLMD1

0 V

V

DD

Hi-Z

Flash memory programming mode

0 V

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Table 21-6. Relationship Between FLMD0, FLMD1 Pins and Operation Mode After Reset Release

FLMD0

0

FLMD1

Any

0

Operation Mode

Normal operation mode

VDD

Flash memory programming mode

Setting prohibited

VDD

21.6.3 Selecting communication mode

In the 78K0/KB1+, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after

the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash

programmer.

The following table shows the relationship between the number of pulses and communication modes.

<R>

Table 21-7. Communication Modes

Communication

Mode

Standard Setting^{Note 1}

On Target

Pins Used

Number of

FLMD0 Pulses

Port

Speed

Frequency

Multiply Rate

UART

UART-ch0

9600, 19200, 31250, Arbitrary

38400, 76800,

153600^{Note 3}bps^{Note 4}

2 to 16 MHz^{Note 2}1.0

TxD6, RxD6

0

(UART6)

3-wire serial I/O

(CSI10)

SIO-ch0

SIO-H/S

2.4 kHz to 2.5 MHz

SO10, SI10,

SCK10

8

3-wire serial I/O

with handshake

(CSI10 + HS)

SO10, SI10,

11

SCK10, HS/P15

Notes 1. Selection items for Standard settings on FlashPro4.

2. The possible setting range differs depending on the voltage. For details, refer to the chapters of electrical

specifications.

3. When peripheral hardware clock frequency is 2.5 MHz or less, this cannot be selected.

4. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART

communication, thoroughly evaluate the slew as well as the baud rate error.

Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the

dedicated flash programmer after the FLMD0 pulse has been received.

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21.6.4 Communication commands

The 78K0/KB1+ communicates with the dedicated flash programmer by using commands. The signals sent from

the flash programmer to the 78K0/KB1+ are called commands, and the commands sent from the 78K0/KB1+ to the

dedicated flash programmer are called response commands.

Figure 21-16. Communication Commands

Command

Axxxx

Bxxxxx

Cxxxxxx

(F^Sl^Tash Pro4)

A

TVE

PG-FP4

Response command

78K0/KB1+

Dedicated flash

programmer

The flash memory control commands of the 78K0/KB1+ are listed in the table below. All these commands are

issued from the programmer and the 78K0/KB1+ performs processing corresponding to the respective commands.

Table 21-8. Flash Memory Control Commands

Classification

Command Name

Batch verify command

Function

Verify

Erase

Compares the contents of the entire memory

with the input data.

Batch erase command

Erases the contents of the entire memory.

Blank check

Data write

Batch blank check command

High-speed write command

Checks the erasure status of the entire memory.

Writes data by specifying the write address and

number of bytes to be written, and executes a

verify check.

Successive write command

Writes data from the address following that of

the high-speed write command executed

immediately before, and executes a verify

check.

System setting, control

Status read command

Obtains the operation status

Oscillation frequency setting command

Erase time setting command

Write time setting command

Baud rate setting command

Silicon signature command

Reset command

Sets the oscillation frequency

Sets the erase time for batch erase

Sets the write time for writing data

Sets the baud rate when UART is used

Reads the silicon signature information

Escapes from each status

The 78K0/KB1+ returns a response command for the command issued by the dedicated flash programmer. The

response commands sent from the 78K0/KB1+ are listed below.

Table 21-9. Response Commands

Command Name

Function

ACK

NAK

Acknowledges command/data.

Acknowledges illegal command/data.

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21.7 Flash Memory Programming by Self-Writing

The 78K0/KB1+ supports a self-programming function that can be used to rewrite the flash memory via a user

program, so that the program can be upgraded in the field.

The programming mode is selected by bits 0 and 1 (FLSPM0 and FLSPM1) of the flash programming mode control

register (FLPMC).

The procedure of self-programming is illustrated below.

Remark For details of the self programming function, refer to the 78K0/Kx1+ Flash Memory Self Programming

User’s Manual (U16701E).

Figure 21-17. Self-Programming Procedure

Start self-programming

Secure entry RAM area

FLSPM1, FLSPM0 = 0, 1

Entry program

(user program)

FLMD0 pin = High level

Mask all interrupts

Set parameters

to entry RAM

CALL #8100H

Read parameters on RAM

and access flash memory

Firmware

according to parameter contents

Mask interrupts again

FLMD0 pin = Low level

Entry program

(user program)

FLSPM1, FLSPM0 = 0, 0

End of self-programming

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21.7.1 Registers used for self-programming function

The following three registers are used for the self-programming function.

• Flash programming mode control register (FLPMC)

• Flash protect command register (PFCMD)

• Flash status register (PFS)

(1) Flash programming mode control register (FLPMC)

This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode

during self-programming.

FLPMC can be written only in a specific sequence (see 21.7.1 (2) Flash protect command register) so that the

application system does not stop inadvertently due to malfunction caused by noise or program hang-up.

FLPMC can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 0xH^Note

.

Note Differs depending on the operation mode.

• User mode: 08H

• On-board mode: 0CH

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Figure 21-18. Format of Flash Programming Mode Control Register (FLPMC)

Address: FFC4H

Symbol

After reset: 0×H^{Note 1}

R/W^{Note 2}

FLPMC

0

FWEDIS FWEPR FLSPM1 FLSPM0

FWEDIS

Control of flash memory writing/erasing

Writing/erasing enabled^{Note 3}

Writing/erasing disabled

0

1

FWEPR

Status of FLMD0 pin

0

1

Low level

High level^{Note 3}

FLSPM1^{Note 4}FLSPM0^{Note 4}

Selection of operation mode during self-programming

Normal mode

0

Instructions of flash memory can be fetched from all

addresses.

Self-programming mode A1

Firmware can be called (CALL #8100H).

0

1

Self-programming mode A2

Instructions are fetched from firmware ROM.

This mode is set in firmware and cannot be set by the user.

Setting prohibited

1

0

Notes 1. Differs depending on the operation mode.

• User mode: 08H

• On-board mode: 0CH

2. Bit 2 (FWEPR) is read-only.

3. For actual writing/erasing, the FLMD0 pin must be high (FWEPR = 1), as well as

FWEDIS = 0.

FWEDIS FWEPR

Enable or disable of flash memory writing/erasing

Writing/erasing enabled

Writing/erasing disabled

0

1

Other than above

4. The user ROM (flash memory) or firmware ROM can be selected by FLSPM1

and FLSPM0, and the operation mode set on the application system by the

mode pin or the self-programming mode can be selected.

Cautions 1. Be sure to keep FWEDIS at 0 until writing or erasing of the flash memory

is completed.

2. Make sure that FWEDIS = 1 in the normal mode.

3. Manipulate FLSPM1 and FLSPM0 after execution branches to the

internal RAM. The address of the flash memory is specified by an

address signal from the CPU when FLSPM1 = 0 or the set value of the

firmware written when FLSPM1 = 1. In the on-board mode, the

specifications of FLSPM1 and FLSPM0 are ignored.

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(2) Flash protect command register (PFCMD)

If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an

operation to write the flash programming mode control register (FLPMC) may have a serious effect on the system.

PFCMD is used to protect FLPMC from being written, so that the application system does not stop inadvertently.

Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.

<1> Write a specific value to PFCMD (PFCMD = A5H)

<2> Write the value to be set to FLPMC (writing in this step is invalid)

<3> Write the inverted value of the value to be set to FLPMC (writing in this step is invalid)

<4> Write the value to be set to FLPMC (writing in this step is valid)

This rewrites the value of the register, so that the register cannot be written illegally.

Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).

A5H must be written to PFCMD each time the value of FLPMC is changed.

PFCMD can be set by an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

Figure 21-19. Format of Flash Protect Command Register (PFCMD)

Address: FFC0H

Symbol

After reset: Undefined

W

PFCMD

REG7

REG6

REG5

REG4

REG3

REG2

REG1

REG0

(3) Flash status register (PFS)

If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct

sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error

occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.

This bit is a cumulative flag. After checking FPRERR, clear it by writing 0 to it.

PFS can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 21-20. Format of Flash Status Register (PFS)

Address: FFC2H

Symbol

After reset: 00H

R/W

PFS

0

FPRERR

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The operating conditions of the FPRERR flag are as follows.

• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to

write a specific value (A5H) to PFCMD

• If the first store instruction operation after <1> is on a peripheral register other than FLPMC

• If the first store instruction operation after <2> is on a peripheral register other than FLPMC

• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction

after <2>

• If the first store instruction operation after <3> is on a peripheral register other than FLPMC

• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction

after <3>

Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command

register (PFCMD).

• If 0 is written to the FPRERR flag

• If RESET is input

To write 05H to FLPMC

MOV

PFCMD, #0A5H

FLPMC, #05H

FLPMC, #0FAH

FLPMC, #05H

; Writes A5H to PFCMD.

; Writes 05H to FLPMC.

; Writes 0FAH (inverted value of 05H) to FLPMC.

; Writes 05H to FLPMC.

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21.8 Boot Swap Function

The 78K0/KB1+ has a boot swap function.

Even if a momentary power failure occurs for some reason while the boot area is being rewritten by self-

programming and the program in the boot area is lost, the boot swap function can execute the program correctly after

re-application of power, reset, and start.

21.8.1 Outline of boot swap function

Before erasing the boot program area by self-programming, write a new boot program to the block to be swapped,

and also set the boot flag^Note. Even if a momentary power failure occurs, the address is swapped when the system is

reset and started next time. Consequently, the above area to be swapped is used as a boot area, and the program is

executed correctly. Figure 21-21 shows an image of the boot swap function.

Note The boot flag is controlled by the flash memory control firmware of the 78K0/KB1+.

Figure 21-21. Image of Boot Swap Function

(1) If boot swap is not supported

X X X X H

User program

Boot program

User program

Undefined data

Self-

programming

Momentary

power failure

User program

Erasure in progress

0 0 0 0 H

Not restarted

(2) If boot swap is supported

X X X X H

User program

Boot program

User program

Self-

programming

Momentary

power failure

User program

New boot program

Undefined data

New boot program

Erasure in progress

0 0 0 0 H

Started correctly

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21.8.2 Memory map and boot area

Figure 21-22 shows the memory map and boot area. The boot program area of the 78K0/KB1+ is in 4 KB units.

When boot swap is executed, boot cluster 0 and boot cluster 1 in the figure are exchanged.

Figure 21-22. Memory Map and Boot Area (1/3)

(1) µPD78F0101H

F F F F H

Special function registers (SFR)

256 × 8 bits

F F 0 0 H

F E F F H

General-purpose registers

32 × 8 bits

F E E 0 H

F E D F H

Internal high-speed RAM

512 × 8 bits

F D 0 0 H

FCFFH

Data memory space

Reserved

1 F F F H

Boot cluster 1

4096 × 8 bits

2 0 0 0 H

1 F F F H

1 0 0 0 H

0 F F F H

Program

memory space

Flash memory

8192 × 8 bits

Boot cluster 0

4096 × 8 bits

0 0 0 0 H

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Figure 21-22. Memory Map and Boot Area (2/3)

(2) µPD78F0102H

F F F F H

Special function registers (SFR)

256 × 8 bits

F F 0 0 H

F E F F H

General-purpose registers

32 × 8 bits

F E E 0 H

F E D F H

Internal high-speed RAM

768 × 8 bits

3 F F F H

F C 0 0 H

F B F F H

Data memory space

8192 × 8 bits

Reserved

2 0 0 0 H

1 F F F H

Boot cluster 1

4096 × 8 bits

4 0 0 0 H

3 F F F H

1 0 0 0 H

0 F F F H

Program

memory space

Flash memory

16384 × 8 bits

Boot cluster 0

4096 × 8 bits

0 0 0 0 H

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Figure 21-22. Memory Map and Boot Area (3/3)

(3) µPD78F0103H

F F F F H

Special function registers (SFR)

256 × 8 bits

F F 0 0 H

F E F F H

General-purpose registers

32 × 8 bits

F E E 0 H

F E D F H

Internal high-speed RAM

768 × 8 bits

5 F F F H

F C 0 0 H

F B F F H

Data memory space

16384 × 8 bits

Reserved

2 0 0 0 H

1 F F F H

Boot cluster 1

4096 × 8 bits

6 0 0 0 H

5 F F F H

1 0 0 0 H

0 F F F H

Program

memory space

Flash memory

24576 × 8 bits

Boot cluster 0

4096 × 8 bits

0 0 0 0 H

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CHAPTER 22 INSTRUCTION SET

This chapter lists each instruction set of the 78K0/KB1+ in table form. For details of each operation and operation

code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).

22.1 Conventions Used in Operation List

22.1.1 Operand identifiers and specification methods

Operands are written in the “Operand” column of each instruction in accordance with the specification method of

the instruction operand identifier (refer to the assembler specifications for details). When there are two or more

methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as

they are. Each symbol has the following meaning.

•

#: Immediate data specification

!: Absolute address specification

$: Relative address specification

[ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

write the #, !, $, and [ ] symbols.

For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for specification.

Table 22-1. Operand Identifiers and Specification Methods

Identifier

Specification Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

rp

sfr

sfrp

Special function register symbol^Note

Special function register symbol (16-bit manipulatable register even addresses only)^Note

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even address only)

addr16

0000H to FFFFH Immediate data or labels

(Only even addresses for 16-bit data transfer instructions)

0800H to 0FFFH Immediate data or labels

addr11

addr5

0040H to 007FH Immediate data or labels (even address only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

RBn

RB0 to RB3

Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.

Remark For special function register symbols, see Table 3-5 Special Function Register List.

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CHAPTER 22 INSTRUCTION SET

22.1.2 Description of operation column

A:

A register; 8-bit accumulator

X register

X:

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

PSW: Program status word

CY:

AC:

Z:

Carry flag

Auxiliary carry flag

Zero flag

RBS:

IE:

Register bank select flag

Interrupt request enable flag

( ):

Memory contents indicated by address or register contents in parentheses

X^H, XL: Higher 8 bits and lower 8 bits of 16-bit register

∧:

∨:

Logical product (AND)

Logical sum (OR)

∨:



Exclusive logical sum (exclusive OR)

Inverted data

:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

22.1.3 Description of flag operation column

(Blank): Not affected

0:

1:

×:

R:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is restored

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CHAPTER 22 INSTRUCTION SET

22.2 Operation List

Clocks

Bytes

Flag

Instruction

Mnemonic

Group

Operands

r, #byte

Operation

Z AC CY

Note 1 Note 2

8-bit data

transfer

MOV

2

3

1

2

3

2

1

2

1

2

3

1

2

4

6

−

2

4

−

8

−

4

8

6

2

4

−

8

4

8

−

7

r ← byte

saddr, #byte

sfr, #byte

A, r

(saddr) ← byte

sfr ← byte

7

Note 3

−

A ← r

r, A

−

r ← A

A, saddr

saddr, A

A, sfr

5

A ← (saddr)

(saddr) ← A

A ← sfr

5

sfr, A

5

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

9

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

9

7

×

5

PSW, A

5

PSW ← A

A, [DE]

5

A ← (DE)

[DE], A

5

(DE) ← A

A, [HL]

5

A ← (HL)

[HL], A

5

(HL) ← A

A, [HL + byte]

[HL + byte], A

A, [HL + B]

[HL + B], A

A, [HL + C]

[HL + C], A

A, r

9

A ← (HL + byte)

(HL + byte) ← A

A ← (HL + B)

(HL + B) ← A

A ← (HL + C)

(HL + C) ← A

A ↔ r

9

7

Note 3

XCH

−

A, saddr

A, sfr

6

A ↔ (saddr)

A ↔ (sfr)

6

A, !addr16

A, [DE]

10

6

A ↔ (addr16)

A ↔ (DE)

A, [HL]

6

A ↔ (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

10

A ↔ (HL + byte)

A ↔ (HL + B)

A ↔ (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

rp, #word

Operation

Z AC CY

Note 1 Note 2

16-bit data MOVW

3

4

2

1

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

−

6

−

4

10

4

6

4

8

4

8

4

6

4

8

4

8

−

10

8

rp ← word

transfer

saddrp, #word

sfrp, #word

AX, saddrp

saddrp, AX

AX, sfrp

(saddrp) ← word

sfrp ← word

AX ← (saddrp)

(saddrp) ← AX

AX ← sfrp

8

sfrp, AX

8

sfrp ← AX

Note 3

AX, rp

−

AX ← rp

rp, AX

−

rp ← AX

AX, !addr16

!addr16, AX

AX, rp

12

−

AX ← (addr16)

(addr16) ← AX

AX ↔ rp

Note 3

XCHW

8-bit

ADD

A, #byte

−

A, CY ← A + byte

×

operation

saddr, #byte

A, r

8

(saddr), CY ← (saddr) + byte

A, CY ← A + r

Note 4

−

r, A

−

r, CY ← r + A

A, saddr

A, !addr16

A, [HL]

5

A, CY ← A + (saddr)

9

A, CY ← A + (addr16)

A, CY ← A + (HL)

5

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

9

A, CY ← A + (HL + byte)

A, CY ← A + (HL + B)

A, CY ← A + (HL + C)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

9

ADDC

−

saddr, #byte

A, r

8

Note 4

−

r, A

−

r, CY ← r + A + CY

A, saddr

A, !addr16

A, [HL]

5

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A + (HL + B) + CY

A, CY ← A + (HL + C) + CY

9

5

A, [HL + byte]

A, [HL + B]

A, [HL + C]

9

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Only when rp = BC, DE or HL

4. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Operation

A, CY ← A − byte

Z AC CY

Note 1 Note 2

8-bit

SUB

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

4

8

4

6

4

8

4

8

4

6

4

8

4

8

−

8

−

5

9

5

9

−

8

−

5

9

5

9

−

8

−

5

9

5

9

×

operation

saddr, #byte

A, r

(saddr), CY ← (saddr) − byte

A, CY ← A − r

Note 3

r, A

r, CY ← r − A

A, saddr

A, !addr16

A, [HL]

A, CY ← A − (saddr)

A, CY ← A − (addr16)

A, CY ← A − (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

A, CY ← A − (HL + byte)

A, CY ← A − (HL + B)

A, CY ← A − (HL + C)

A, CY ← A − byte − CY

(saddr), CY ← (saddr) − byte − CY

A, CY ← A − r − CY

r, CY ← r − A − CY

A, CY ← A − (saddr) − CY

A, CY ← A − (addr16) − CY

A, CY ← A − (HL) − CY

A, CY ← A − (HL + byte) − CY

A, CY ← A − (HL + B) − CY

A, CY ← A − (HL + C) − CY

A ← A ∧ byte

SUBC

r, A

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

AND

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

r, A

r ← r ∧ A

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (saddr)

A ← A ∧ (addr16)

A ← A ∧ (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A ← A ∧ (HL + byte)

A ← A ∧ (HL + B)

A ← A ∧ (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Operation

Z AC CY

Note 1 Note 2

8-bit

OR

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

4

8

4

6

4

8

4

8

4

6

4

8

4

8

−

8

−

5

9

5

9

−

8

−

5

9

5

9

−

8

−

5

9

5

9

A ← A ∨ byte

×

operation

saddr, #byte

A, r

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

Note 3

r, A

r ← r ∨ A

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A ← A ∨ (HL + B)

A ← A ∨ (HL + C)

A ← A ∨ byte

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

XOR

r, A

r ← r ∨ A

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A ← A ∨ (HL + B)

A ← A ∨ (HL + C)

A − byte

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

CMP

×

(saddr) − byte

A − r

r, A

r − A

A, saddr

A, !addr16

A, [HL]

A − (saddr)

A − (addr16)

A − (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A − (HL + byte)

A − (HL + B)

A − (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

AX, #word

Operation

AX, CY ← AX + word

Z AC CY

Note 1 Note 2

16-bit

ADDW

SUBW

CMPW

MULU

DIVUW

3

2

1

2

1

2

1

2

6

−

6

−

6

−

12

×

operation

AX, #word

AX, CY ← AX − word

AX − word

AX, #word

6

Multiply/

divide

X

16

25

2

AX ← A × X

C

AX (Quotient), C (Remainder) ← AX ÷ C

r ← r + 1

Increment/ INC

r

×

decrement

saddr

r

4

(saddr) ← (saddr) + 1

r ← r − 1

DEC

2

saddr

rp

4

(saddr) ← (saddr) − 1

rp ← rp + 1

INCW

4

DECW

rp

4

rp ← rp − 1

Rotate

ROR

A, 1

[HL]

2

(CY, A7 ← A0, Am − 1 ← Am) × 1 time

(CY, A0 ← A7, Am + 1 ← Am) × 1 time

(CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time

(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time

×

ROL

2

RORC

ROLC

ROR4

2

10

A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,

(HL)^{3 − 0}← (HL)7 − 4

ROL4

[HL]

2

10

12

A^{3 − 0}← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,

(HL)^{7 − 4}← (HL)3 − 0

BCD

ADJBA

ADJBS

MOV1

2

3

2

3

2

3

2

3

2

4

6

−

4

−

6

−

4

−

6

−

7

−

7

8

−

8

Decimal Adjust Accumulator after Addition

Decimal Adjust Accumulator after Subtract

CY ← (saddr.bit)

×

adjustment

Bit

CY, saddr.bit

CY, sfr.bit

manipulate

CY ← sfr.bit

CY, A.bit

CY ← A.bit

CY, PSW.bit

CY, [HL].bit

saddr.bit, CY

sfr.bit, CY

CY ← PSW.bit

CY ← (HL).bit

(saddr.bit) ← CY

sfr.bit ← CY

A.bit, CY

A.bit ← CY

PSW.bit, CY

[HL].bit, CY

PSW.bit ← CY

×

(HL).bit ← CY

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

CY, saddr.bit

Operation

CY ← CY ∧ (saddr.bit)

Z AC CY

Note 1 Note 2

Bit

manipulate

AND1

3

2

3

2

3

2

3

2

3

2

3

2

3

2

3

2

1

6

−

4

−

6

−

4

−

6

−

4

−

6

4

−

4

−

6

4

−

4

−

6

2

7

−

7

−

7

−

7

6

8

−

6

8

6

8

−

6

8

−

×

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

saddr.bit

sfr.bit

CY ← CY ∧ sfr.bit

CY ← CY ∧ A.bit

CY ← CY ∧ PSW.bit

CY ← CY ∧ (HL).bit

CY ← CY ∨ (saddr.bit)

CY ← CY ∨ sfr.bit

CY ← CY ∨ A.bit

CY ← CY ∨ PSW.bit

CY ← CY ∨ (HL).bit

CY ← CY ∨ (saddr.bit)

CY ← CY ∨ sfr.bit

CY ← CY ∨ A.bit

CY ← CY ∨ PSW.bit

CY ← CY ∨ (HL).bit

(saddr.bit) ← 1

sfr.bit ← 1

OR1

XOR1

SET1

CLR1

A.bit

A.bit ← 1

PSW.bit

[HL].bit

PSW.bit ← 1

×

(HL).bit ← 1

saddr.bit

sfr.bit

(saddr.bit) ← 0

sfr.bit ← 0

A.bit

A.bit ← 0

PSW.bit

[HL].bit

PSW.bit ← 0

×

(HL).bit ← 0

SET1

CLR1

NOT1

CY

CY ← 1

1

0

×

CY

CY ← 0

CY

CY ← CY

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

!addr16

Operation

Z AC CY

Note 1 Note 2

Call/return CALL

3

2

7

5

−

(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,

PC ← addr16, SP ← SP − 2

CALLF

!addr11

[addr5]

(SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,

PC^{15 − 11}← 00001, PC10 − 0 ← addr11,

SP ← SP − 2

CALLT

BRK

1

6

−

(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,

PC^H← (00000000, addr5 + 1),

PC^L← (00000000, addr5),

SP ← SP − 2

(SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,

(SP − 3) ← (PC + 1)^L, PCH ← (003FH),

PC^L← (003EH), SP ← SP − 3, IE ← 0

RET

1

6

−

PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI

RETB

PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3

R

PC^H← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3

−

Stack

PUSH

POP

PSW

rp

1

2

4

(SP − 1) ← PSW, SP ← SP − 1

manipulate

(SP − 1) ← rp^H, (SP − 2) ← rpL,

SP ← SP − 2

−

PSW

rp

1

2

4

PSW ← (SP), SP ← SP + 1

R

rp^H← (SP + 1), rpL ← (SP),

SP ← SP + 2

−

6

8

6

MOVW

SP, #word

SP, AX

AX, SP

!addr16

$addr16

AX

4

2

3

2

10

8

−

SP ← word

SP ← AX

AX ← SP

Unconditional BR

PC ← addr16

branch

−

PC ← PC + 2 + jdisp8

PC^H← A, PCL ← X

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

−

Conditional BC

$addr16

branch

−

BNC

−

BZ

−

BNZ

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clocks

Bytes

Flag

Instruction

Group

Mnemonic

Operands

Operation

Z AC CY

Note 1 Note 2

Conditional BT

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

3

4

3

4

3

4

3

4

8

−

9

PC ← PC + 3 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 3 + jdisp8 if PSW.bit = 1

PC ← PC + 3 + jdisp8 if (HL).bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW. bit = 0

PC ← PC + 3 + jdisp8 if (HL).bit = 0

branch

11

−

8

PSW.bit, $addr16

[HL].bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

−

9

10

−

11

−

BF

8

PSW.bit, $addr16

[HL].bit, $addr16

saddr.bit, $addr16

−

11

12

10

BTCLR

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

then reset (saddr.bit)

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

[HL].bit, $addr16

B, $addr16

4

3

4

3

2

3

−

8

12

−

PC ← PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

PC ← PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

−

12

−

PC ← PC + 4 + jdisp8 if PSW.bit = 1

then reset PSW.bit

×

10

6

PC ← PC + 3 + jdisp8 if (HL).bit = 1

then reset (HL).bit

DBNZ

B ← B − 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16

6

−

C ← C −1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

saddr, $addr16

RBn

8

10

(saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

CPU

SEL

NOP

EI

2

1

2

4

2

−

6

−

6

−

RBS1, 0 ← n

control

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

22.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Second Operand

#byte

A

r^Note

sfr

saddr !addr16 PSW

[DE]

[HL] [HL + byte] $addr16

[HL + B]

1

None

First Operand

[HL + C]

ADD

ADDC

SUB

SUBC

AND

OR

MOV MOV MOV MOV MOV MOV MOV MOV

ROR

A

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XCH

ADD

XCH

ADD

XCH

ADD

XCH

ADD

ROL

RORC

ROLC

ADDC ADDC

SUB SUB

SUBC SUBC

ADDC ADDC

SUB SUB

SUBC SUBC

XOR

CMP

AND

OR

AND

OR

AND

OR

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

OR

XOR

CMP

B, C

sfr

DBNZ

MOV MOV

saddr

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

OR

XOR

CMP

!addr16

PSW

MOV

MOV MOV

PUSH

POP

[DE]

[HL]

MOV

ROR4

ROL4

[HL + byte]

[HL + B]

MOV

[HL + C]

X

C

MULU

DIVUW

Note Except r = A

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CHAPTER 22 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second Operand

First Operand

#word

AX

rp^Note

sfrp

saddrp

!addr16

SP

None

AX

ADDW

MOVW

XCHW

MOVW

SUBW

CMPW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

sfrp

MOVW

saddrp

!addr16

SP

MOVW

Note Only when rp = BC, DE, HL

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second Operand

First Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY

$addr16

None

A.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

sfr.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

saddr.bit

PSW.bit

[HL].bit

CY

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

MOV1

AND1

OR1

MOV1

SET1

CLR1

NOT1

AND1

OR1

AND1

OR1

AND1

OR1

AND1

OR1

XOR1

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CHAPTER 22 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second Operand

First Operand

AX

!addr16

!addr11

[addr5]

$addr16

Basic instruction

BR

CALL

BR

CALLF

CALLT

BR

BC

BNC

BZ

BNZ

Compound

instruction

BT

BF

BTCLR

DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

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CHAPTER 23 ELECTRICAL SPECIFICATIONS

(STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Target products: µPD78F0101H, 78F0102H, 78F0103H, 78F0101H(A), 78F0102H(A), 78F0103H(A)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

−0.3 to +6.5

Unit

V

VDD

VSS

−0.3 to +0.3

V

AVREF

AV^SS

VI

−0.3 to VDD + 0.3^Note

V

−0.3 to +0.3

−0.3 to VDD + 0.3^Note

V

Input voltage

P00 to P03, P10 to P17, P20 to P23,

P30 to P33, P120, X1, X2, RESET

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

AV^SS− 0.3 to AVREF + 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

Per pin

−10

−30

mA

Total of pins

P30 to P33, P120

−60 mA

P00 to P03,

P10 to P17, P130

IOL

Per pin

20

35

mA

Total of all pins

70 mA

P30 to P33, P120

P00 to P03,

P10 to P17, P130

Operating ambient

temperature

T^A

In normal operation mode

−40 to +85

−10 to +65

−65 to +150

−40 to +125

°C

In flash memory programming

In flash memory blank state

In flash memory programmed state

<R> Storage temperature

Tstg

Note Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Crystal/Ceramic Oscillator Characteristics

(T^A= −40 to +85°C, 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

2.0

TYP. MAX.

16

Unit

Ceramic resonator

Oscillation frequency

(f^XP)^Note

4.0 V ≤ VDD ≤ 5.5 V

MHz

V

^SSX1

C1

X2

3.5 V ≤ VDD < 4.0 V

3.0 V ≤ VDD < 3.5 V

2.5 V ≤ V^DD< 3.0 V

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.0 V ≤ VDD < 3.5 V

2.5 V ≤ V^DD< 3.0 V

2.0

10

8.38

5.0

16

C2

Crystal resonator

Oscillation frequency

(f^XP)^Note

MHz

V

^SSX1

C1

X2

10

C2

8.38

5.0

External clock

X1 input frequency

(f^XP)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.0 V ≤ VDD < 3.5 V

2.5 V ≤ V^DD< 3.0 V

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.0 V ≤ VDD < 3.5 V

2.5 V ≤ V^DD< 3.0 V

2.0

30

16

10

MHz

8.38

5.0

X1

X2

X1 input high-/low-

250

ns

level width (t^XPH, tXPL)

46

56

96

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Cautions 1. When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. Since the CPU is started by the internal oscillation clock after reset is released, check the

oscillation stabilization time of the crystal/ceramic oscillation clock using the oscillation

stabilization time counter status register (OSTC). Determine the oscillation stabilization time of

the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently

evaluating the oscillation stabilization time with the resonator to be used.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

External RC Oscillator Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

RC oscillation

Recommended Circuit

Parameter

Conditions

MIN.

3.0

TYP. MAX.

4.0

Unit

Oscillation frequency

(f^XP)^Note

MHz

V

^SSCL1 CL2

R

C

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the above

figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC Oscillation Frequency Characteristics (T

SS = 0 V)

Resonator

A

= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD,

V

Conditions

MIN.

2.5

TYP. MAX.

Unit

Oscillation frequency

(f^XP)

R = 6.8 kΩ, C = 22 pF

Target value: 3 MHz

2.7 V ≤ V^DD≤ 5.5 V

3.0

3.5

MHz

R = 4.7 kΩ, C = 22 pF

3.5

4.0

4.7

MHz

Target value: 4 MHz

Caution Set one of the above values to R and C.

Internal Oscillator Characteristics (T = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, 2.0 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

A

Resonator

Parameter

Oscillation frequency (fR)

Conditions

MIN.

120

TYP. MAX.

240 480

Unit

kHz

Internal oscillator

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Recommended Oscillator Constants

Ceramic Resonator (T^A= −40 to +85°C)

Manufacturer

Part Number

SMD/Lead

Lead

Frequency

(MHz)

Recommended Circuit

Constants

Oscillation Voltage Range

C1

C2

MIN.

(V)

MAX.

(V)

(pF)

Murata Mfg.

CSTLS4M00G56-B0

CSTLS4M19G56-B0

CSTLS4M91G56-B0

CSTLS5M00G56-B0

CSTLS6M00G56-B0

CSTLS8M00G56-B0

CSTLS8M38G56-B0

CSTLS10M0G53-B0

4.00

4.19

4.915

5.00

6.00

8.00

8.388

10.0

Internal

(47)

Internal

(47)

2.5

5.5

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(47)

Internal

(15)

Internal

(15)

Caution The oscillator constants shown above are reference values based on evaluation in a specific

environment by the resonator manufacturer. If it is necessary to optimize the oscillator

characteristics in the actual application, apply to the resonator manufacturer for evaluation on the

implementation circuit. The oscillation voltage and oscillation frequency only indicate the oscillator

characteristic. Use the 78K0/KB1+ so that the internal operation conditions are within the

specifications of the DC and AC characteristics.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

DC Characteristics (TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V^{Note 1}, 2.0 V ≤ AVREF ≤ VDD^{Note 1}, VSS = AVSS = 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP. MAX.

−5

Unit

mA

V

Output current, high

IOH

Per pin

Total of P30 to P33, P120

4.0 V ≤ VDD ≤ 5.5 V

−25

Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V

−25

Total of all pins

Per pin

2.0 V ≤ V^DD< 4.0 V

4.0 V ≤ VDD ≤ 5.5 V

−10

Output current, low

Input voltage, high

IOL

10

Total of P30 to P33, P120

30

Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V

30

Total of all pins

P12, P13, P15

2.0 V ≤ V^DD< 4.0 V

10

VIH1

VIH2

VIH3

V^IH4

VIL1

VIL2

VIL3

V^IL4

VOH

2.7 V ≤ VDD ≤ 5.5 V 0.7VDD

2.0 V ≤ V^DD< 2.7 V 0.8VDD

2.7 V ≤ VDD ≤ 5.5 V 0.8VDD

2.0 V ≤ V^DD< 2.7 V 0.85VDD

2.7 V ≤ VDD ≤ 5.5 V 0.7AVREF

2.0 V ≤ V^DD< 2.7 V 0.8AVREF

2.7 V ≤ VDD ≤ 5.5 V VDD − 0.5

2.5 V ≤ V^DD< 2.7 V VDD − 0.2

VDD

V

P00 to P03, P10, P11, P14, P16,

P17, P30 to P33, P120, RESET

VDD

V

VDD

V

P20 to P23^{Note 2}

AVREF

VDD

V

X1, X2

V

VDD

V

Input voltage, low

P12, P13, P15

2.7 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.5 V ≤ V^DD< 2.7 V

0

0.3VDD

0.2VDD

0.15VDD

0.3AVREF

0.2AVREF

0.4

V

P00 to P03, P10, P11, P14, P16,

P17, P30 to P33, P120, RESET

V

P20 to P23^{Note 2}

V

X1, X2

V

0.2

V

Output voltage, high

Output voltage, low

Total of P30 to P33, P120 pins

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −5 mA

V

I^OH= −25 mA

Total of P00 to P03, P10 to P17,

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −5 mA

V

P130 pins

I^OH= −25 mA

I^OH= −100 µA

2.0 V ≤ VDD < 4.0 V VDD − 0.5

V

VOL

Total of P30 to P33, P120 pins

I^OL= 30 mA

4.0 V ≤ V^DD≤ 5.5 V,

I^OL= 10 mA

1.3

Total of P00 to P03, P10 to P17,

4.0 V ≤ V^DD≤ 5.5 V,

V

P130 pins

I^OL= 30 mA

I^OL= 10 mA

IOL = 400 µA

2.7 V ≤ VDD < 4.0 V

2.0 V ≤ V^DD< 2.7 V

0.4

0.5

3

V

Input leakage current, high

Input leakage current, low

ILIH1

VI = VDD

P00 to P03, P10 to P17, P30 to P33,

P120, RESET

µA

V^I= AVREF

VI = VDD

V^I= 0 V

P20 to P23

X1, X2^{Note 3}

3

µA

I^LIH2

20

−3

ILIL1

P00 to P03, P10 to P17, P20 to P23,

P30 to P33, P120, RESET

I^LIL2

X1, X2^{Note 3}

−20

3

µA

kΩ

V

Output leakage current, high ILOH

Output leakage current, low ILOL

VO = VDD

VO = 0 V

VI = 0 V

−3

Pull-up resistance value

FLMD0 supply voltage

RL

10

0

30

100

Flmd

In normal operation mode

0.2VDD

Notes 1. When crystal/ceramic oscillation clock is used: 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, when external

RC oscillation clock is used: 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD

2. When used as a digital input port, set AVREF = VDD.

3. When the inverse level of X1 is input to X2.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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DC Characteristics (TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V^{Note 1}, 2.0 V ≤ AVREF ≤ VDD^{Note 1}, VSS = AVSS = 0 V) (2/2)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

11.5 22.5 mA

12.5 24.5 mA

7.5 15.0 mA

Supply

current^{Note 2}

IDD1

Crystal/

fXP = 16 MHz,

When A/D converter is stopped

When A/D converter is operating^{Note 5}

ceramic

V^DD= 5.0 V 10%^{Note 4}

oscillation

operating

mode^{Notes 3, 7}

fXP = 10 MHz,

When A/D converter is stopped

V^DD= 5.0 V 10%^{Note 4}

When A/D converter is operating^{Note 5}

When A/D converter is stopped

8.5 17.0 mA

f^XP= 5 MHz,

2.2

2.8

2.5

4.3

5.5

5.7

mA

V^DD= 3.0 V 10%^{Note 4}

When A/D converter is operating^{Note 5}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When A/D converter is stopped

IDD2

Crystal/

ceramic

oscillation

HALT

fXP = 16 MHz,

V^DD= 5.0 V 10%

11.0 mA

fXP = 10 MHz,

1.8

0.6

4.2

7.7

1.4

2.5

mA

V^DD= 5.0 V 10%

mode^{Note 7}

f^XP= 5 MHz,

V^DD= 3.0 V 10%

IDD3

RC

fXP = 4 MHz,

6.5 12.0 mA

7.5 14.0 mA

When A/D converter is operating^{Note 5}

oscillation

operating

mode^{Note 8}

V^DD= 5.0 V 10%

f^XP= 4 MHz,

When A/D converter is stopped

4.4

5.0

3.8

8.3

9.5

8.0

9.0

6.5

7.0

3.2

1.6

mA

When A/D converter is operating^{Note 5}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

V^DD= 3.0 V 10%

IDD4

RC

fXP = 4 MHz,

oscillation

HALT

mode^{Note 8}

V^DD= 5.0 V 10%

f^XP= 4 MHz,

3.0

V^DD= 3.0 V 10%

IDD5

IDD6

I^DD7

Internal

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.8

0.4

oscillation

operating

mode^{Note 6}

Internal

oscillation

HALT

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.4

1.6

mA

0.25 1.0

mode^{Note 6}

STOP

mode

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

Internal oscillator: OFF

Internal oscillator: ON

Internal oscillator: OFF

Internal oscillator: ON

3.5 35.5 µA

17.5 63.5 µA

3.5 15.5 µA

11.0 30.5 µA

Notes 1. When crystal/ceramic oscillation clock is used: 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, when external

RC oscillation clock is used: 2.7 V ≤ V^DD≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD

2. Total current flowing through the internal power supply (V^DD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

3. I^DD1includes peripheral operation current.

4. When PCC = 00H.

5. Total current flowing through V^DDand AVREF pins.

6. When high-speed system clock oscillator is stopped.

7. When crystal/ceramic oscillation is selected as the high-speed system clock using the option byte.

8. When an external RC is selected as the high-speed system clock using the option byte.

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AC Characteristics

(1) Basic operation (TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V^{Note 1}, 2.0 V ≤ AVREF ≤ VDD^{Note 1}, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

16

Unit

µs

Instruction cycle (minimum T^CY

instruction execution time)

High-speed Crystal/ceramic 4.0 V ≤ VDD ≤ 5.5 V 0.125

system

clock

oscillation clock

3.5 V ≤ VDD < 4.0 V

3.0 V ≤ VDD < 3.5 V 0.238

2.5 V ≤ V^DD< 3.0 V 0.4

0.2

16

µs

16

µs

16

µs

External RC

2.7 V ≤ V^DD≤ 5.5 V 0.426

12.8

µs

oscillation clock

Internal oscillation clock

4.17

8.33

33.3

µs

TI000, TI010 input high-

tTIH0,

4.0 V ≤ VDD ≤ 5.5 V

2/f^sam+

0.1^{Note 2}

level width, low-level width t^TIL0

2.7 V ≤ VDD < 4.0 V

2.5 V ≤ V^DD< 2.7 V

2/f^sam+

0.2^{Note 2}

µs

2/f^sam+

0.5^{Note 2}

TI50 input frequency

fTI5

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.5 V ≤ V^DD< 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.5 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 2.7 V

10

5

MHz

ns

2.5

TI50 input high-level width, tTIH5,

50

100

200

1

low-level width

t^TIL5

ns

Interrupt input high-level

width, low-level width

tINTH,

µs

t^INTL

2

µs

RESET low-level width

tRSL

10

20

µs

Notes 1. When crystal/ceramic oscillation clock is used: 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, when external

RC oscillation clock is used: 2.7 V ≤ V^DD≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD

2. Selection of f^sam= fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f^sam= fXP.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

TCY vs. VDD (System Clock)

33.3

20.0

16.0

10.0

µ

5.0

4.17

Guaranteed

operation range

2.0

1.0

0.4

0.238

0.2

0.125

0.1

2.5

3.5

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

Supply voltage VDD [V]

Remark The values indicated by the shaded section are only when the internal oscillation clock is selected.

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(2) Serial interface (TA = −40 to +85°C, 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

(a) UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(b) UART mode (UART0, dedicated baud rate generator output):

µPD78F0102H, 78F0103H, 78F0102H(A) and 78F0103H(A) only

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)

Parameter

SCK10 cycle time

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

MIN.

200

MAX.

Unit

ns

tKCY1

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ VDD < 3.3 V

2.5 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.5 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.5 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.5 V ≤ V^DD< 2.7 V

C = 100 pF^Note2.7 V ≤ VDD ≤ 5.5 V

2.5 V ≤ VDD < 2.7 V

240

400

800

SCK10 high-/low-level width

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

t^KH1,

t^KL1

tKCY1/2 − 10

tKCY1/2 − 50

30

tSIK1

tKSI1

t^KSO1

70

30

70

Delay time from SCK10↓ to

SO10 output

30

120

Note C is the load capacitance of the SCK10 and SO10 output lines.

(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)

Parameter

SCK10 cycle time

Symbol

Conditions

2.7 V ≤ VDD ≤ 5.5 V

MIN.

400

TYP.

MAX.

Unit

ns

tKCY2

2.5 V ≤ V^DD< 2.7 V

800

ns

SCK10 high-/low-level width

t^KH2,

t^KL2

t^KCY2/2

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK2

tKSI2

t^KSO2

80

50

ns

Delay time from SCK10↓ to

C = 100 pF^Note

120

SO10 output

Note C is the load capacitance of the SO10 output line.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

AC Timing Test Points (Excluding X1)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f^XP

tXL

t

XH

V

IH4 (MIN.)

IL4 (MAX.)

X1

V

TI Timing

tTIL0

tTIH0

TI000, TI010

1/f^TI5

tTIL5

tTIH5

TI50

Interrupt Request Input Timing

tINTL

t

INTH

INTP0 to INTP5

RESET Input Timing

tRSL

RESET

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Serial Transfer Timing

3-wire serial I/O mode:

tKCYm

t

KLm

t

KHm

SCK10

t

SIKm

t

KSIm

SI10

Input data

t

KSOm

SO10

Output data

Remark m = 1, 2

A/D Converter Characteristics (T = −40 to +85°C, 2.5 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

A

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 1, 2}

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.6

0.4

0.6

1.2

100

0.4

0.6

1.2

0.4

0.6

1.2

2.5

4.5

8.5

1.5

2.0

3.5

AVREF

%FSR

µs

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.0 V

2.5 V ≤ AV^REF< 2.7 V

Conversion time

tCONV

14

17

48

µs

Zero-scale error^{Notes 1, 2}

Full-scale error^{Notes 1, 2}

%FSR

LSB

Integral non-linearity error^{Note 1}

Differential non-linearity error^{Note 1}

Analog input voltage

LSB

VAIN

AVSS

V

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

POC Circuit Characteristics (TA = −40 to +85°C)

Parameter

Detection voltage

Symbol

VPOC

Conditions

MIN.

2.0

TYP.

2.1

MAX.

2.2

Unit

V

Power supply rise time

tPTH

VDD: 0 V → 2.0 V

0.0015

ms

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

Response delay time 2^{Note 2}

Minimum pulse width

tPD

When VDD falls

ms

tPW

0.2

Notes 1. Time required from voltage detection to reset release.

2. Time required from voltage detection to internal reset output.

POC Circuit Timing

Supply voltage

(VDD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

tPTH

tPTHD

tPD

Time

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

LVI Circuit Characteristics (TA = −40 to +85°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

VLVI7

VLVI8

V^LVI9

tLD

Conditions

MIN.

4.1

TYP.

4.3

MAX.

4.5

Unit

V

3.9

4.1

4.3

V

3.7

3.9

4.1

V

3.5

3.7

3.9

V

3.3

3.5

3.7

V

3.15

2.95

2.7

3.3

3.45

3.25

3.0

V

3.1

V

2.85

2.6

V

2.5

2.7

V

2.25

2.35

0.2

2.45

2.0

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or internal reset output.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9

2. VPOC < VLVIm (m = 0 to 9)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

LW

t

LWAIT

t

LD

LVION ← 1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.0

0

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Release signal set time

µs

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Flash Memory Programming Characteristics

(T^A= −10 to +65°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Basic characteristics

Parameter

VDD supply current

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

30.5

Unit

mA

ms

s

fXP = 16 MHz, VDD = 5.5 V

Unit erase time^{Note 1}

Erase time^{Note 2}

Terass

Teraca

T^erasa

Twrwa

Cerwr

10

0.01

50

All blocks

Block unit

2.55

500

100

s

Write time

µs

Number of rewrites per chip^{Note 3}

1 erase + 1 write after erase = 1 rewrite^{Note 4}

Times

Notes 1. Time required for one erasure execution

2. The total time for repetition of the unit erase time (255 times max.) until the data is erased completely.

Note that the prewrite time and the erase verify time (writeback time) before data erasure are not included.

3. Number of rewrites per block

4. If a block erasure is executed after word units of data are written 512 times to a block (2 KB), it is

considered as one rewrite. Overwriting the same address without erasing the data in it is prohibited.

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<R>

CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Target products: µPD78F0101H(A1), 78F0102H(A1), 78F0103H(A1)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

−0.3 to +6.5

Unit

V

VDD

VSS

−0.3 to +0.3

V

AVREF

AV^SS

VI

−0.3 to VDD + 0.3^Note

V

−0.3 to +0.3

−0.3 to VDD + 0.3^Note

V

Input voltage

P00 to P03, P10 to P17, P20 to P23,

P30 to P33, P120, X1, X2, RESET

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

AV^SS− 0.3 to AVREF + 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

Per pin

−8

mA

Total of pins

P30 to P33, P120

−24

−48 mA

P00 to P03,

P10 to P17, P130

IOL

Per pin

16

28

mA

Total of all pins

56 mA

P30 to P33, P120

P00 to P03,

P10 to P17, P130

Operating ambient

temperature

T^A

In normal operation mode

−40 to +110

−10 to +65

−65 to +150

−40 to +125

°C

In flash memory programming

In flash memory blank state

In flash memory programmed state

Storage temperature

Tstg

Note Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Crystal/Ceramic Oscillator Characteristics

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

2.0

TYP. MAX.

16

Unit

Ceramic resonator

Oscillation frequency

(f^XP)^Note

4.0 V ≤ VDD ≤ 5.5 V

MHz

V

^SSX1

C1

X2

3.5 V ≤ VDD < 4.0 V

3.3 V ≤ VDD < 3.5 V

2.7 V ≤ V^DD< 3.3 V

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.3 V ≤ VDD < 3.5 V

2.7 V ≤ V^DD< 3.3 V

2.0

10

8.38

5.0

16

C2

Crystal resonator

Oscillation frequency

(f^XP)^Note

MHz

V

^SSX1

C1

X2

10

C2

8.38

5.0

External clock

X1 input frequency

(f^XP)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.3 V ≤ VDD < 3.5 V

2.7 V ≤ V^DD< 3.3 V

4.0 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.0 V

3.3 V ≤ VDD < 3.5 V

2.7 V ≤ V^DD< 3.3 V

2.0

30

16

10

MHz

8.38

5.0

X1

X2

X1 input high-/low-

250

ns

level width (t^XPH, tXPL)

46

56

96

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Cautions 1. When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

2. Since the CPU is started by the internal oscillation clock after reset is released, check the

oscillation stabilization time of the crystal/ceramic oscillation clock using the oscillation

stabilization time counter status register (OSTC). Determine the oscillation stabilization time of

the OSTC register and oscillation stabilization time select register (OSTS) after sufficiently

evaluating the oscillation stabilization time with the resonator to be used.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

External RC Oscillator Characteristics (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

RC oscillation

Recommended Circuit

Parameter

Conditions

MIN.

3.0

TYP. MAX.

4.0

Unit

Oscillation frequency

(f^XP)^Note

MHz

V

^SSCL1 CL2

R

C

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the above

figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC Oscillation Frequency Characteristics (T

SS = 0 V)

Resonator

A

= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD,

V

Conditions

MIN.

2.5

TYP. MAX.

Unit

Oscillation frequency

(f^XP)

R = 6.8 kΩ, C = 22 pF

Target value: 3 MHz

2.7 V ≤ V^DD≤ 5.5 V

3.0

3.5

MHz

R = 4.7 kΩ, C = 22 pF

3.5

4.0

4.7

MHz

Target value: 4 MHz

Caution Set one of the above values to R and C.

Internal Oscillator Characteristics (T = −40 to +110°C, 2.0 V ≤ VDD ≤ 5.5 V, 2.0 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

A

Resonator

Parameter

Oscillation frequency (fR)

Conditions

MIN.

120

TYP. MAX.

240 490

Unit

kHz

Internal oscillator

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

DC Characteristics (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP. MAX.

Unit

mA

V

Output current, high

IOH

Per pin

Total of P30 to P33, P120

4.0 V ≤ VDD ≤ 5.5 V

−4

−20

−25

−8

Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V

Total of all pins

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

4.0 V ≤ VDD ≤ 5.5 V

Output current, low

IOL

Per pin

8

Total of P30 to P33, P120

24

Total of P00 to P03, P10 to P17, P130 4.0 V ≤ VDD ≤ 5.5 V

24

Total of all pins

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

30

8

Input voltage, high

Input voltage, low

VIH1

VIH2

P12, P13, P15

0.7VDD

VDD

P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120, 0.8VDD

RESET

V

VIH3

V^IH4

VIL1

VIL2

P20 to P23^{Note 1}

0.7AVREF

AVREF

VDD

V

X1, X2

VDD − 0.5

P12, P13, P15

0

0.3VDD

0.2VDD

P00 to P03, P10, P11, P14, P16, P17, P30 to P33, P120,

RESET

VIL3

V^IL4

VOH

P20 to P23^{Note 1}

0

0.3AVREF

0.4

V

X1, X2

Output voltage, high

Output voltage, low

Total of P30 to P33, P120 pins

I^OH= −20 mA

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −4 mA

Total of P00 to P03, P10 to P17,

P130 pins

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −4 mA

V

I^OH= −20 mA

I^OH= −100 µA

2.7 V ≤ VDD < 4.0 V VDD − 0.5

V

VOL

Total of P30 to P33, P120 pins

I^OL= 24 mA

4.0 V ≤ V^DD≤ 5.5 V,

I^OL= 8 mA

1.3

Total of P00 to P03, P10 to P17,

4.0 V ≤ V^DD≤ 5.5 V,

V

P130 pins

I^OL= 400 µA

VI = VDD

I^OL= 24 mA

I^OL= 8 mA

2.7 V ≤ VDD < 4.0 V

0.4

10

V

Input leakage current, high

Input leakage current, low

ILIH1

P00 to P03, P10 to P17, P30 to P33,

P120, RESET

µA

V^I= AVREF

VI = VDD

V^I= 0 V

P20 to P23

X1, X2^{Note 2}

10

20

µA

I^LIH2

ILIL1

P00 to P03, P10 to P17, P20 to P23,

P30 to P33, P120, RESET

−10

ILIL2

X1, X2^{Note 2}

−20

10

µA

kΩ

V

Output leakage current, high ILOH

Output leakage current, low ILOL

VO = VDD

VO = 0 V

VI = 0 V

−10

Pull-up resistance value

FLMD0 supply voltage

RL

10

0

30

120

Flmd

In normal operation mode

0.2VDD

Notes 1. When used as a digital input port, set AVREF = VDD.

2. When the inverse level of X1 is input to X2.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

DC Characteristics (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V) (2/2)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

11.5 23.6 mA

12.5 25.6 mA

7.5 16.1 mA

Supply

current^{Note 1}

IDD1

Crystal/

fXP = 16 MHz,

When A/D converter is stopped

When A/D converter is operating^{Note 4}

ceramic

V^DD= 5.0 V 10%^{Note 3}

oscillation

operating

mode^{Notes 2, 6}

fXP = 10 MHz,

When A/D converter is stopped

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is operating^{Note 4}

When A/D converter is stopped

8.5 18.1 mA

f^XP= 5 MHz,

2.2

2.8

2.5

5.1

6.3

6.8

mA

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is operating^{Note 4}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When A/D converter is stopped

IDD2

Crystal/

ceramic

oscillation

HALT

fXP = 16 MHz,

V^DD= 5.0 V 10%

12.1 mA

fXP = 10 MHz,

1.8

0.6

5.3

8.8

2.2

3.3

mA

V^DD= 5.0 V 10%

mode^{Note 6}

f^XP= 5 MHz,

V^DD= 3.0 V 10%

IDD3

RC

fXP = 4 MHz,

6.5 13.1 mA

7.5 15.1 mA

When A/D converter is operating^{Note 4}

oscillation

operating

mode^{Note 7}

V^DD= 5.0 V 10%

f^XP= 4 MHz,

When A/D converter is stopped

4.4

9.1

mA

When A/D converter is operating^{Note 4}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

5.0 10.3 mA

V^DD= 3.0 V 10%

IDD4

RC

fXP = 4 MHz,

3.8

3.0

9.1

mA

oscillation

HALT

mode^{Note 7}

V^DD= 5.0 V 10%

10.1 mA

f^XP= 4 MHz,

7.3

7.8

4.3

2.4

mA

V^DD= 3.0 V 10%

IDD5

IDD6

I^DD7

Internal

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.8

0.4

oscillation

operating

mode^{Note 5}

Internal

oscillation

HALT

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.4

2.7

mA

0.25 1.8

mode^{Note 5}

STOP

mode

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

Internal oscillator: OFF

Internal oscillator: ON

Internal oscillator: OFF

Internal oscillator: ON

3.5 1100 µA

17.5 1200 µA

3.5 800

11.0 800

µA

Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. I^DD1includes peripheral operation current.

3. When PCC = 00H.

4. Total current flowing through V^DDand AVREF pins.

5. When high-speed system clock oscillator is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using the option byte.

7. When an external RC is selected as the high-speed system clock using the option byte.

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AC Characteristics

(1) Basic operation (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

16

Unit

µs

Instruction cycle (minimum T^CY

instruction execution time)

High-speed Crystal/ceramic 4.0 V ≤ VDD ≤ 5.5 V 0.125

system

clock

oscillation clock

3.5 V ≤ VDD < 4.0 V

3.3 V ≤ VDD < 3.5 V 0.238

2.7 V ≤ V^DD< 3.3 V 0.4

0.2

16

µs

16

µs

16

µs

External RC

2.7 V ≤ V^DD≤ 5.5 V 0.426

12.8

µs

oscillation clock

Internal oscillation clock^{Note 1}

4.09

8.33

16.67

µs

TI000, TI010 input high-

tTIH0,

4.0 V ≤ VDD ≤ 5.5 V

2/f^sam+

0.1^{Note 2}

level width, low-level width t^TIL0

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

2/f^sam+

0.2^{Note 2}

µs

2/f^sam+

0.5^{Note 2}

TI50 input frequency

fTI5

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 3.3 V

3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 3.3 V

10

5

MHz

ns

2.5

TI50 input high-level width, tTIH5,

50

100

200

1

low-level width

t^TIL5

ns

Interrupt input high-level

width, low-level width

tINTH,

µs

t^INTL

2

µs

RESET low-level width

tRSL

10

20

µs

Notes 1. When the internal oscillation clock is used, the CPU can operate at 2.0 V ≤ VDD ≤ 5.5 V. However,

perform I/O operations at 2.7 V ≤ V^DD≤ 5.5 V and 2.7 V ≤ AVREF ≤ VDD.

2. Selection of f^sam= fXP, fXP/4, fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f^sam= fXP.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

TCY vs. VDD (System Clock)

20.0

16.67

16.0

10.0

µ

5.0

Guaranteed

operation range

2.0

1.0

0.4

0.238

0.2

0.125

0.1

2.7

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

3.3 3.5

Supply voltage VDD [V]

Remark The values indicated by the shaded section are only when the internal oscillation clock is selected.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

(2) Serial interface (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

(a) UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(b) UART mode (UART0, dedicated baud rate generator output):

µPD78F0102H(A1) and 78F0103H(A1) only

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)

Parameter

SCK10 cycle time

Symbol

Conditions

4.5 V ≤ VDD ≤ 5.5 V

MIN.

200

MAX.

Unit

ns

tKCY1

4.0 V ≤ VDD < 4.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 3.3 V

3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 3.3 V

3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 3.3 V

C = 100 pF^Note3.3 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 3.3 V

240

400

800

SCK10 high-/low-level width

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

t^KH1,

t^KL1

tKCY1/2 − 10

tKCY1/2 − 50

30

tSIK1

tKSI1

t^KSO1

70

30

70

Delay time from SCK10↓ to

SO10 output

30

120

Note C is the load capacitance of the SCK10 and SO10 output lines.

(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)

Parameter

SCK10 cycle time

Symbol

Conditions

3.3 V ≤ VDD ≤ 5.5 V

MIN.

400

TYP.

MAX.

Unit

ns

tKCY2

2.7 V ≤ V^DD< 3.3 V

800

ns

SCK10 high-/low-level width

t^KH2,

t^KL2

t^KCY2/2

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK2

tKSI2

t^KSO2

80

50

ns

Delay time from SCK10↓ to

C = 100 pF^Note

120

SO10 output

Note C is the load capacitance of the SO10 output line.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

AC Timing Test Points (Excluding X1)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f^XP

tXL

tXH

V

IH4 (MIN.)

IL4 (MAX.)

X1

V

TI Timing

t

TIL0

t

TIH0

TI000, TI010

1/f^TI5

t

TIL5

t

TIH5

TI50

Interrupt Request Input Timing

tINTL

t

INTH

INTP0 to INTP5

RESET Input Timing

tRSL

RESET

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Serial Transfer Timing

3-wire serial I/O mode:

tKCYm

t

KLm

t

KHm

SCK10

t

SIKm

t

KSIm

SI10

Input data

t

KSOm

SO10

Output data

Remark m = 1, 2

A/D Converter Characteristics (T = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)

A

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 1, 2}

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.6

0.8

60

%FSR

µs

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

Conversion time

tCONV

14

19

60

µs

Zero-scale error^{Notes 1, 2}

Full-scale error^{Notes 1, 2}

0.6

0.8

0.6

0.8

4.5

6.5

2.0

2.5

AVREF

%FSR

LSB

V

Integral non-linearity error^{Note 1}

Differential non-linearity error^{Note 1}

Analog input voltage

VAIN

AVSS

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

POC Circuit Characteristics (TA = −40 to +110°C)

Parameter

Detection voltage

Symbol

VPOC

Conditions

MIN.

2.0

TYP.

2.1

MAX.

2.25

Unit

V

Power supply rise time

tPTH

VDD: 0 V → 2.0 V

0.0015

ms

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

Response delay time 2^{Note 2}

Minimum pulse width

tPD

When VDD falls

ms

tPW

0.2

Notes 1. Time required from voltage detection to reset release.

2. Time required from voltage detection to internal reset output.

POC Circuit Timing

Supply voltage

(VDD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

t

PTH

t

PTHD

t

PD

Time

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

LVI Circuit Characteristics (TA = −40 to +110°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

VLVI7

VLVI8

V^LVI9

tLD

Conditions

MIN.

4.1

TYP.

4.3

MAX.

4.52

4.32

4.12

3.92

3.72

3.50

3.30

3.05

2.7

Unit

V

3.9

4.1

V

3.7

3.9

V

3.5

3.7

V

3.3

3.5

V

3.15

2.95

2.7

3.3

V

3.1

V

2.85

2.6

V

2.5

V

2.25

2.35

0.2

2.50

2.0

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or internal reset output.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9

2. VPOC < VLVIm (m = 0 to 9)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tLW

t

LWAIT

tLD

LVION ← 1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +110°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.0

0

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Release signal set time

µs

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Flash Memory Programming Characteristics

(T^A= −10 to +65°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Basic characteristics

Parameter

VDD supply current

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

30.5

Unit

mA

ms

s

fXP = 16 MHz, VDD = 5.5 V

Unit erase time^{Note 1}

Erase time^{Note 2}

Terass

Teraca

T^erasa

Twrwa

Cerwr

10

0.01

50

All blocks

Block unit

2.55

500

100

s

Write time

µs

Number of rewrites per chip^{Note 3}

1 erase + 1 write after erase = 1 rewrite^{Note 4}

Times

Notes 1. Time required for one erasure execution

2. The total time for repetition of the unit erase time (255 times max.) until the data is erased completely.

Note that the prewrite time and the erase verify time (writeback time) before data erasure are not included.

3. Number of rewrites per block

4. If a block erasure is executed after word units of data are written 512 times to a block (2 KB), it is

considered as one rewrite. Overwriting the same address without erasing the data in it is prohibited.

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CHAPTER 25 PACKAGE DRAWING

30-PIN PLASTIC SSOP (7.62 mm (300))

30

16

detail of lead end

F

G

T

P

L

1

15

U

E

A

H

I

J

S

B

C

N

S

M

D

M

K

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

A

B

C

9.85 0.15

0.45 MAX.

0.65 (T.P.)

+0.08

0.24

D

−0.07

E

F

G

H

I

0.1 0.05

1.3 0.1

1.2

8.1 0.2

6.1 0.2

1.0 0.2

0.17 0.03

0.5

J

K

L

M

N

0.13

0.10

+5°

3°

P

−3°

T

0.25

U

0.6 0.15

S30MC-65-5A4-2

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<R>

CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, please contact an NEC Electronics

sales representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 26-1. Surface Mounting Type Soldering Conditions

(1) µPD78F0101HMC-5A4, 78F0102HMC-5A4, 78F0103HMC-5A4, 78F0101HMC(A)-5A4, 78F0102HMC(A)-5A4,

78F0103HMC(A)-5A4, 78F0101HMC(A1)-5A4, 78F0102HMC(A1)-5A4, 78F0103HMC(A1)-5A4

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

IR35-207-3

VP15-207-3

WS60-207-1

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

VPS

Wave soldering

Partial heating

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature), Exposure

limit: 7 days^Note(after that, prebake at 125°C for 20 to 72 hours)

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

−

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

(2) µPD78F0101HMC-5A4-A, 78F0102HMC-5A4-A, 78F0103HMC-5A4-A, 78F0101HMC(A)-5A4-A,

78F0102HMC(A)-5A4-A, 78F0103HMC(A)-5A4-A, 78F0101HMC(A1)-5A4-A, 78F0102HMC(A1)-5A4-A,

78F0103HMC(A1)-5A4-A

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: Three times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C

for 20 to 72 hours)

IR60-207-3

Partial heating

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

−

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remarks Products that have the part numbers suffixed by "-A" are lead-free products.

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CHAPTER 27 CAUTIONS FOR WAIT

27.1 Cautions for Wait

This product has two internal system buses.

One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.

Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data

may be passed if an access to the CPU conflicts with an access to the peripheral hardware.

When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes

processing, until the correct data is passed.

As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of

execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 27-

1). This must be noted when real-time processing is performed.

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CHAPTER 27 CAUTIONS FOR WAIT

27.2 Peripheral Hardware That Generates Wait

Table 27-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait

clocks.

Table 27-1. Registers That Generate Wait and Number of CPU Wait Clocks

Peripheral Hardware

Watchdog timer

Register

Access

Number of Wait Clocks

3 clocks (fixed)

WDTM

ASIS0

ASIS6

ADM

Write

Read

Write

Read

Serial interface UART0

Serial interface UART6

A/D converter

1 clock (fixed)

2 to 5 clocks^Note

(when ADM.5 flag = “1”)

2 to 9 clocks^Note

ADS

PFM

(when ADM.5 flag = “0”)

PFT

ADCR

1 to 5 clocks

(when ADM.5 flag = “1”)

1 to 9 clocks

(when ADM.5 flag = “0”)

{(1/f^MACRO) × 2/(1/fCPU)} + 1

*The result after the decimal point is truncated if it is less than t^CPULafter it has been multiplied by

(1/f^CPU), and is rounded up if it exceeds tCPUL.

f^MACRO:

Macro operating frequency

(When bit 5 (FR2) of ADM = “1”: f^X/2, when bit 5 (FR2) of ADM = “0”: fX/2²)

f^CPU:

CPU clock frequency

t^CPUL:

Low-level width of CPU clock

Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1.

Remark The clock is the CPU clock (f^CPU).

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CHAPTER 27 CAUTIONS FOR WAIT

27.3 Example of Wait Occurrence

<1> Watchdog timer

Number of execution clocks: 8

(5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).)

Number of execution clocks: 10

(7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).)

<2> Serial interface UART6

Number of execution clocks: 6

(5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).)

<3> A/D converter

Table 27-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter)

• When f^X= 10 MHz, tCPUL = 50 ns

Value of Bit 5 (FR2)

f^CPU

Number of Wait Clocks

9 clocks

Number of Execution Clocks

14 clocks

of ADM Register

0

1

fX

fX/2

fX/2²

fX/2³

fX/2⁴

fX

5 clocks

10 clocks

3 clocks

8 clocks

2 clocks

7 clocks

0 clocks (1 clock^Note

5 clocks

)

5 clocks (6 clocks^Note

10 clocks

)

fX/2

fX/2²

fX/2³

f^X/2⁴

3 clocks

8 clocks

2 clocks

7 clocks

0 clocks (1 clock^Note

)

5 clocks (6 clocks^Note

)

Note On execution of MOV A, ADCR

Remark The clock is the CPU clock (f^CPU).

f^X: High-speed system clock oscillation frequency

t^CPUL: Low-level width of CPU clock

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems that employ the 78K0/KB1+.

Figure A-1 shows the development tool configuration.

•

Support for PC98-NX series

Unless otherwise specified, products supported by IBM PC/AT^TMcompatibles are compatible with PC98-NX

series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.

•

Windows^TM

Unless otherwise specified, “Windows” means the following OSs.

•

Windows 3.1

Windows 95

Windows 98

Windows NT^TMVer 4.0

Windows 2000

Windows XP^TM

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration (1/2)

•

When using the in-circuit emulator QB-78K0KX1H

Software package

• Software package

Debugging software

Language processing software

• Assembler package

• C compiler package

• Device file

• Integrated debugger

• System simulator

• C library source file^{Note 1}

Control software

• Project manager

(Windows only)^{Note 2}

Host machine (PC or EWS)

USB interface cable

Power supply unit

Flash memory

writing environment

Flash programmer

In-circuit emulator^{Note 3}

Flash memory

writing adapter

Emulation probe

Flash memory

Conversion socket or

conversion adapter

Target system

Notes 1. The C library source file is not included in the software package.

2. The project manager PM+ is included in the assembler package.

PM+ is only used for Windows.

3. In-circuit emulator QB-78K0KX1H is supplied with integrated debugger ID78K0-QB, flash memory

programmer PG-FPL, power supply unit, and USB interface cable. Any other products are sold

separately.

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APPENDIX A DEVELOPMENT TOOLS

<R>

Figure A-1. Development Tool Configuration (2/2)

•

When using the on-chip debug emulator QB-78K0MINI

Software package

• Software package

Debugging software

Language processing software

• Assembler package

• C compiler package

• Device file

• Integrated debugger

• System simulator

• C library source file^{Note 1}

Control software

• Project manager

(Windows only)^{Note 2}

Host machine (PC or EWS)

USB interface cable

Flash memory

writing environment

Flash programmer

On-chip debug emulator^{Note 3}

Flash memory

writing adapter

Connection cable

Flash memory

Debugging adapter

Target system

Notes 1. The C library source file is not included in the software package.

2. The project manager PM+ is included in the assembler package.

PM+ is only used for Windows.

3. On-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB

interface cable, and connection cable. Any other products are sold separately.

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APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

SP78K0

Development tools (software) common to the 78K/0 Series are combined in this package.

78K/0 Series software package

Part number: µS××××SP78K0

Remark ×××× in the part number differs depending on the host machine and OS used.

µS××××SP78K0

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT compatibles

OS

Supply Medium

Windows (Japanese version) CD-ROM

Windows (English version)

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APPENDIX A DEVELOPMENT TOOLS

A.2 Language Processing Software

RA78K0

This assembler converts programs written in mnemonics into object codes executable

with a microcontroller.

Assembler package

This assembler is also provided with functions capable of automatically creating symbol

tables and branch instruction optimization.

This assembler should be used in combination with a device file (DF780103) (sold

separately).

This assembler package is a DOS-based application. It can also be used in Windows,

however, by using the project manager (included in assembler package) on Windows.

Part number: µS××××RA78K0

CC78K0

This compiler converts programs written in C language into object codes executable with

a microcontroller.

C compiler package

This compiler should be used in combination with an assembler package and device file

(both sold separately).

This C compiler package is a DOS-based application. It can also be used in Windows,

however, by using the project manager (included in assembler package) on Windows.

Part number: µS××××CC78K0

DF780103^{Note 1}

Device file

This file contains information peculiar to the device.

This device file should be used in combination with a tool (RA78K0, CC78K0, SM+ for

78K0, and ID78K0-QB) (all sold separately).

The corresponding OS and host machine differ depending on the tool to be used.

Part number: µS××××DF780103

CC78K0-L^{Note 2}

This is a source file of the functions that configure the object library included in the C

compiler package.

C library source file

This file is required to match the object library included in the C compiler package to the

user’s specifications.

Since this is a source file, its working environment does not depend on any particular

operating system.

Part number: µS××××CC78K0-L

Notes 1. The DF780103 can be used in common with the RA78K0, CC78K0, SM+ for 78K0, and ID78K0-QB.

2. The CC78K0-L is not included in the software package (SP78K0).

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APPENDIX A DEVELOPMENT TOOLS

Remark ×××× in the part number differs depending on the host machine and OS used.

µS××××RA78K0

µS××××CC78K0

µS××××CC78K0-L

××××

AB17

Host Machine

PC-9800 series,

OS

Supply Medium

Windows (Japanese version) CD-ROM

Windows (English version)

IBM PC/AT compatibles

BB17

3P17

3K17

HP9000 series 700^TM

SPARCstation^TM

HP-UX^TM(Rel. 10.10)

SunOS^TM(Rel. 4.1.4),

Solaris^TM(Rel. 2.5.1)

µS××××DF780103

××××

Host Machine

OS

Supply Medium

AB13

BB13

PC-9800 series,

Windows (Japanese version) 3.5-inch 2HD FD

Windows (English version)

IBM PC/AT compatibles

A.3 Control Software

PM+

This is control software designed to enable efficient user program development in the

Windows environment. All operations used in development of a user program, such as

starting the editor, building, and starting the debugger, can be performed from PM+.

Project manager

PM+ is included in the assembler package (RA78K0).

It can only be used in Windows.

A.4 Flash Memory Writing Tools

FlashPro4

Flash programmer dedicated to microcontrollers with on-chip flash memory.

(part number: FL-PR4, PG-FP4)

Flash programmer

PG-FPL

Flash memory programmer dedicated to microcontrollers with on-chip flash memory.

Included with in-circuit emulator QB-78K0KX1H.

Flash memory programmer

FA-30MC-A

Flash memory writing adapter used connected to FlashPro4.

Flash memory writing adapter

• FA-30MC-A: For 30-pin plastic SSOP (MC-5A4 type)

Remark FL-PR4 and FA-30MC-A are products of Naito Densei Machida Mfg. Co., Ltd.

TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.

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APPENDIX A DEVELOPMENT TOOLS

A.5 Debugging Tools (Hardware)

A.5.1 When using in-circuit emulator QB-78K0KX1H

QB-78K0KX1H^Note

In-circuit emulator

This in-circuit emulator serves to debug hardware and software when developing

application systems using the 78K0/Kx1 and 78K0/Kx1+. It corresponds to the integrated

debugger (ID78K0-QB). This emulator should be used in combination with a power

supply unit and emulation probe, and the USB is used to connect this emulator to the

host machine.

QB-144-CA-01

This check pin adapter is used in waveform monitoring using the oscilloscope, etc.

Check pin adapter

QB-80-EP-01T

Emulation probe

This emulation probe is flexible type and used to connect the in-circuit emulator and

target system.

QB-30MC-EA-01T

Exchange adapter

This exchange adapter is used to perform pin conversion from the in-circuit emulator to

target connector.

QB-30MC-YS-01T

Space adapter

This space adapter is used to adjust the height between the target system and in-circuit

emulator.

QB-30MC-YQ-01T

This YQ connector is used to connect the target connector and exchange adapter.

(YSPACK30BK+YQGUIDE-S3)

YQ connector

QB-30MC-HQ-01T (HSPACK30BK)

Mount adapter

This mount adapter is used to mount the target device with socket.

This target connector is used to mount on the target system.

QB-30MC-NQ-01T (NSPACK30BK)

Target connector

Note The QB-78K0KX1H is supplied with a power supply unit, USB interface cable, and flash memory

programmer PG-FPL. It is also supplied with integrated debugger ID78K0-QB as control software.

Remarks 1. The packed contents differ depending on the part number, as follows.

• QB-78K0KX1H-ZZZ:

In-circuit emulator only

• QB-78K0KX1H-T30MC: In-circuit emulator and supplied products (emulation probe, exchange

adapter, YQ connector, and target connector)

<R>

2. YSPACK30BK, YQGUIDE-S3, HSPACK30BK, and NSPACK30BK are products of TOKYO

ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronic Device Department

(TEL: +81-3-3820-7141)

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APPENDIX A DEVELOPMENT TOOLS

<R>

A.5.2 When using on-chip debug emulator QB-78K0MINI

QB-78K0MINI^Note

The on-chip debug emulator serves to debug hardware and software when developing

application systems using the 78K0/Kx1+. It supports the integrated debugger (ID78K0-

QB). This emulator uses a connection cable and a USB interface cable that is used to

connect the host machine.

On-chip debug emulator

QB-78K0KX1H-DA

The debugging adapter is used to emulate 78K0/KB1+. It operates as in-circuit emulator

when used in combination with the QB-78K0MINI.

Debugging adapter for QB-78K0MINI

QB-30MC-YQ-01T

This YQ connector is used to connect the target connector and debugging adapter.

(YSPACK30BK+YQGUIDE-S3)

YQ connector

QB-30MC-NQ-01T (NSPACK30BK)

Target connector

This target connector is used to mount on the target system.

Note The QB-78K0MINI is supplied with a USB interface cable and a connection cable. It is also supplied with

integrated debugger ID78K0-QB as control software.

Remark YSPACK30BK, YQGUIDE-S3, and NSPACK30BK are products of TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronic Device Department

(TEL: +81-3-3820-7141)

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APPENDIX A DEVELOPMENT TOOLS

A.6 Debugging Tools (Software)

SM+ for 78K0^Note

System simulator

This is a system simulator for the 78K/0 Series. SM+ for 78K0 is Windows-based

software.

It is used to perform debugging at the C source level or assembler level while simulating

the operation of the target system on a host machine.

Use of SM+ for 78K0 allows the execution of application logical testing and performance

testing on an independent basis from hardware development, thereby providing higher

development efficiency and software quality.

SM+ for 78K0 should be used in combination with the device file (DF780103) (sold

separately).

<R>

Part number: µS××××SM780148H-B

ID78K0-QB

This debugger supports the in-circuit emulators for the 78K0/Kx1+ Series. The ID78K0-

QB is Windows-based software.

Integrated debugger

It has improved C-compatible debugging functions and can be display the results of

tracing with the source program using an integrating window function that associates the

source program, disassemble display, and memory display with the trace result. It

should be used in combination with the device file (sold separately).

Part number: µS××××ID78K0-QB

Note Under development

Remark ×××× in the part number differs depending on the host machine and OS used.

<R>

µS×××× SM780148H-B

µS××××ID78K0-QB

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT compatibles

OS

Supply Medium

Windows (Japanese version) CD-ROM

Windows (English version)

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APPENDIX B NOTES ON TARGET SYSTEM DESIGN

This section shows areas on the target system where component mounting is prohibited and areas where there are

component mounting height restrictions when using the QB-78K0KX1H.

Figure B-1. Restricted Area on Target System

12.5

13.375

17.375

: Exchange adapter area:

Components up to 17.45 mm in height can be mounted^Note

: Emulation probe tip area: Components up to 24.45 mm in height can be mounted^Note

Note Height can be regulated by using space adapters (each adds 2.4 mm)

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APPENDIX C REGISTER INDEX

C.1 Register Index (In Alphabetical Order with Respect to Register Names)

[A]

A/D conversion result register (ADCR) … 186

A/D converter mode register (ADM) … 184

Analog input channel specification register (ADS) … 186

Asynchronous serial interface control register 6 (ASICL6) … 236

Asynchronous serial interface operation mode register 0 (ASIM0) … 205

Asynchronous serial interface operation mode register 6 (ASIM6) … 229

Asynchronous serial interface reception error status register 0 (ASIS0) … 207

Asynchronous serial interface reception error status register 6 (ASIS6) … 231

Asynchronous serial interface transmission status register 6 (ASIF6) … 232

[B]

Baud rate generator control register 0 (BRGC0) … 208

Baud rate generator control register 6 (BRGC6) … 235

[C]

Capture/compare control register 00 (CRC00) … 110

Clock monitor mode register (CLM) … 310

Clock selection register 6 (CKSR6) … 233

[E]

8-bit timer compare register 50 (CR50) … 143

8-bit timer counter 50 (TM50) … 142

8-bit timer H compare register 00 (CMP00) … 157

8-bit timer H compare register 01 (CMP01) … 157

8-bit timer H compare register 10 (CMP10) … 157

8-bit timer H compare register 11 (CMP11) … 157

8-bit timer H mode register 0 (TMHMD0) … 158

8-bit timer H mode register 1 (TMHMD1) … 158

8-bit timer mode control register 50 (TMC50) … 145

External interrupt falling edge enable register (EGN) … 282

External interrupt rising edge enable register (EGP) … 282

[F]

Flash programming mode control register (FLPMC) … 349

Flash protect command register (PFCMD) … 351

Flash status register (PFS) … 351

[I]

Input switch control register (ISC) … 238

Internal memory size switching register (IMS) … 333

Internal oscillation mode register (RCM) … 85

Interrupt mask flag register 0H (MK0H) … 280

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APPENDIX C REGISTER INDEX

Interrupt mask flag register 0L (MK0L) … 280

Interrupt mask flag register 1L (MK1L) … 280

Interrupt request flag register 0H (IF0H) … 279

Interrupt request flag register 0L (IF0L) … 279

Interrupt request flag register 1L (IF1L) … 279

[L]

Low-voltage detection level selection register (LVIS) … 322

Low-voltage detection register (LVIM) … 321

[M]

Main clock mode register (MCM) … 86

Main OSC control register (MOC) … 87

[O]

Oscillation stabilization time counter status register (OSTC) … 87, 293

Oscillation stabilization time select register (OSTS) … 89, 294

[P]

Port mode register 0 (PM0) … 77, 113

Port mode register 1 (PM1) … 77, 146, 161, 209, 238, 265

Port mode register 3 (PM3) … 77

Port mode register 12 (PM12) … 77

Port register 0 (P0) … 79

Port register 1 (P1) … 79

Port register 2 (P2) … 79

Port register 3 (P3) … 79

Port register 12 (P12) … 79

Port register 13 (P13) … 79

Power-fail comparison mode register (PFM) … 187

Power-fail comparison threshold register (PFT) … 187

Prescaler mode register 00 (PRM00) … 112

Priority specification flag register 0H (PR0H) … 281

Priority specification flag register 0L (PR0L) … 281

Priority specification flag register 1L (PR1L) … 281

Processor clock control register (PCC) … 84

Pull-up resistor option register 0 (PU0) … 80

Pull-up resistor option register 1 (PU1) … 80

Pull-up resistor option register 3 (PU3) … 80

Pull-up resistor option register 12 (PU12) … 80

[R]

Receive buffer register 0 (RXB0) … 204

Receive buffer register 6 (RXB6) … 228

Reset control flag register (RESF) … 308

[S]

Serial clock selection register 10 (CSIC10) … 264

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APPENDIX C REGISTER INDEX

Serial I/O shift register 10 (SIO10) … 262

Serial operation mode register 10 (CSIM10) … 263

16-bit timer capture/compare register 000 (CR000) … 105

16-bit timer capture/compare register 010 (CR010) … 107

16-bit timer counter 00 (TM00) … 105

16-bit timer mode control register 00 (TMC00) … 108

16-bit timer output control register 00 (TOC00) … 111

[T]

Timer clock selection register 50 (TCL50) … 144

Transmit buffer register 6 (TXB6) … 228

Transmit buffer register 10 (SOTB10) … 262

Transmit shift register 0 (TXS0) … 204

[W]

Watchdog timer enable register (WDTE) … 175

Watchdog timer mode register (WDTM) … 173

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APPENDIX C REGISTER INDEX

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)

[A]

ADCR:

ADM:

A/D conversion result register … 186

A/D converter mode register … 184

ADS:

Analog input channel specification register … 186

ASICL6:

ASIF6:

ASIM0:

ASIM6:

ASIS0:

ASIS6:

Asynchronous serial interface control register 6 … 236

Asynchronous serial interface transmission status register 6 … 232

Asynchronous serial interface operation mode register 0 … 205

Asynchronous serial interface operation mode register 6 … 229

Asynchronous serial interface reception error status register 0 … 207

Asynchronous serial interface reception error status register 6 … 231

[B]

BRGC0:

BRGC6:

Baud rate generator control register 0 … 208

Baud rate generator control register 6 … 235

[C]

CKSR6:

CLM:

Clock selection register 6 … 233

Clock monitor mode register … 310

CMP00:

CMP01:

CMP10:

CMP11:

CR000:

CR010:

CR50:

8-bit timer H compare register 00 … 157

8-bit timer H compare register 01 … 157

8-bit timer H compare register 10 … 157

8-bit timer H compare register 11 … 157

16-bit timer capture/compare register 000 … 105

16-bit timer capture/compare register 010 … 107

8-bit timer compare register 50 … 143

Capture/compare control register 00 … 110

Serial clock selection register 10 … 264

Serial operation mode register 10 … 263

CRC00:

CSIC10:

CSIM10:

[E]

EGN:

EGP:

External interrupt falling edge enable register … 282

External interrupt rising edge enable register … 282

[F]

FLPMC:

Flash programming mode control register … 349

[I]

IF0H:

IF0L:

IF1L:

IMS:

ISC:

Interrupt request flag register 0H … 279

Interrupt request flag register 0L … 279

Interrupt request flag register 1L … 279

Internal memory size switching register … 333

Input switch control register … 238

[L]

LVIM:

LVIS:

Low-voltage detection register … 321

Low-voltage detection level selection register … 322

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APPENDIX C REGISTER INDEX

[M]

MCM:

MK0H:

MK0L:

MK1L:

MOC:

Main clock mode register … 86

Interrupt mask flag register 0H … 280

Interrupt mask flag register 0L … 280

Interrupt mask flag register 1L … 280

Main OSC control register … 87

[O]

OSTC:

OSTS:

Oscillation stabilization time counter status register … 87, 293

Oscillation stabilization time select register … 89, 294

[P]

P0:

Port register 0 … 79

P1:

Port register 1 … 79

P2:

Port register 2 … 79

P3:

Port register 3 … 79

P12:

Port register 12 … 79

P13:

Port register 13 … 79

PCC:

PFCMD

PFM:

PFS

Processor clock control register … 84

Flash protect command register … 351

Power-fail comparison mode register … 187

Flash status register … 351

PFT:

PM0:

PM1:

PM3:

PM12:

PR0H:

PR0L:

PR1L:

PRM00:

PU0:

PU1:

PU3:

PU12:

Power-fail comparison threshold register … 187

Port mode register 0 … 77, 113

Port mode register 1 … 77, 146, 161, 209, 238, 265

Port mode register 3 … 77

Port mode register 12 … 77

Priority specification flag register 0H … 281

Priority specification flag register 0L … 281

Priority specification flag register 1L … 281

Prescaler mode register 00 … 112

Pull-up resistor option register 0 … 80

Pull-up resistor option register 1 … 80

Pull-up resistor option register 3 … 80

Pull-up resistor option register 12 … 80

[R]

RCM:

RESF:

RXB0:

RXB6:

Internal oscillation mode register … 85

Reset control flag register … 308

Receive buffer register 0 … 204

Receive buffer register 6 … 228

[S]

SIO10:

SOTB10:

Serial I/O shift register 10 … 262

Transmit buffer register 10 … 262

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APPENDIX C REGISTER INDEX

[T]

TCL50:

TM00:

Timer clock selection register 50 … 144

16-bit timer counter 00 … 105

TM50:

8-bit timer counter 50 … 142

TMC00:

TMC50:

TMHMD0:

TMHMD1:

TOC00:

TXB6:

16-bit timer mode control register 00 … 108

8-bit timer mode control register 50 … 145

8-bit timer H mode register 0 … 158

8-bit timer H mode register 1 … 158

16-bit timer output control register 00 … 111

Transmit buffer register 6 … 228

TXS0:

Transmit shift register 0 … 204

[W]

WDTE:

WDTM:

Watchdog timer enable register … 175

Watchdog timer mode register … 173

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APPENDIX D LIST OF CAUTIONS

This appendix lists cautions described in this document.

“Classification (hard/soft)” in table is as follows.

Hard: Cautions for microcontroller internal/external hardware

Soft: Cautions for software such as register settings or programs

(1/17)

Function

Details of Function

Cautions

Page

−

Connect the AVSS pin to VSS

.

p. 17

configuration

Memory

space

IMS: Memory

size switching

register

Regardless of the internal memory capacity, the initial values of internal memory size

switching register (IMS) of all products in the 78K0/KB1+ are fixed (IMS = CFH). Therefore,

set the value corresponding to each product as indicated below. In addition, set the

following values to the internal memory size switching register (IMS) when using the

78K0/KB1+ to evaluate the program of a mask ROM version of the 78K0/KB1.

µPD78F0101H, 780101: 42H

p. 34

µPD78F0102H, 780102: 04H

µPD78F0103H, 780103: 06H

SFR area:

Special function

register

Do not access addresses to which SFRs are not assigned.

p. 39

SP: Stack pointer Since RESET input makes the SP contents undefined, be sure to initialize the SP before

use.

p. 44

p. 69

Port function P10, P11, P12

To use P10/SCK10 (/TxD0), P11/SI10 (/RxD0), and P12/SO10 as general-purpose ports,

set serial operation mode register 10 (CSIM10) and serial clock selection register 10

(CSIC10) to the default status (00H).

−

In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, p. 81

the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output

pins, the output latch contents for pins specified as input are undefined, even for bits other

than the manipulated bit.

−

PCC: Processor Be sure to clear bits 3 to 7 to 0.

p. 84

clock control

register (PCC)

Internal

RCM: Internal

oscillation mode

register

Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting

RSTOP.

p. 85

p. 86

oscillator

Main clock

MCM: Main clock When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

mode register

divided clock of the internal oscillator output (f

X

) is supplied to the peripheral hardware (f =

X

240 kHz (TYP.)).

Operation of the peripheral hardware with the internal oscillation clock cannot be

guaranteed. Therefore, when the internal oscillation clock is selected as the clock supplied

to the CPU, do not use peripheral hardware. In addition, stop the peripheral hardware

before switching the clock supplied to the CPU from the high-speed system clock to the

internal oscillation clock. Note, however, that the following peripheral hardware can be

used when the CPU operates on the internal oscillation clock.

• Watchdog timer

• Clock monitor

• 8-bit timer H1 when f

/2⁷is selected as the count clock

R

• Peripheral hardware with an external clock selected as the clock source

(Except when the external count clock of TM00 is selected (TI000 valid edge))

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APPENDIX D LIST OF CAUTIONS

(2/17)

Function

Details of Function

Cautions

Page

Main clock

MOC: Main OSC Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting

control register MSTOP.

p. 87

OSTC: Oscillation Waiting for the oscillation stabilization time is not required when the external RC oscillation p. 87

stabilization time clock is selected as the high-speed system clock by the option byte. Therefore, the CPU

counter status

register

clock can be switched without reading the OSTC value.

After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 88

If the STOP mode is entered and then released while the internal oscillation clock is being p. 88

used as the CPU clock, set the oscillation stabilization time as follows.

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS

The oscillation stabilization time counter counts up to the oscillation stabilization time set by

OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by

OSTS is set to OSTC after STOP mode is released.

The wait time when STOP mode is released does not include the time after STOP mode

release until clock oscillation starts (“a” below) regardless of whether STOP mode is

released by RESET input or interrupt generation.

p. 88

p. 89

OSTS: Oscillation To set the STOP mode when the high-speed system clock is used as the CPU clock, set

stabilization time OSTS before executing a STOP instruction.

select register

Execute the OSTS setting after confirming that the oscillation stabilization time has elapsed p. 89

as expected in OSTC.

If the STOP mode is entered and then released while the internal oscillation clock is being p. 89

used as the CPU clock, set the oscillation stabilization time as follows.

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS

The oscillation stabilization time counter counts up to the oscillation stabilization time set by

OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by

OSTS is set to OSTC after STOP mode is released.

The wait time when STOP mode is released does not include the time after STOP mode

release until clock oscillation starts (“a” below) regardless of whether STOP mode is

released by RESET input or interrupt generation.

p. 89

p. 90

High-speed

Crystal/ceramic

When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the

broken lines in the Figure 5-8 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

system clock oscillator

oscillator

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS. Do

not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC

oscillator

When using the external RC oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-10 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

p. 92

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal

line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS. Do

not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Prescaler

−

When the internal oscillation clock is selected as the clock supplied to the CPU, the prescaler p. 94

generates various clocks by dividing the internal oscillator output (f = 240 kHz (TYP.)).

X

Internal

The RSTOP setting is valid only when “Can be stopped by software” is set for the internal

oscillator by the option byte.

p. 98

oscillator

To calculate the maximum time, set f = 120 kHz.

R

p. 99

CPU clock

Setting the following values is prohibited when the CPU operates on the internal oscillation p. 99

clock.

• PCC2, PCC1, PCC0 = 0, 1, 0

• PCC2, PCC1, PCC0 = 0, 1, 1

• PCC2, PCC1, PCC0 = 1, 0, 0

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APPENDIX D LIST OF CAUTIONS

(3/17)

Function

Details of Function

Cautions

Page

16-bit

CR000: 16-bit

timer

Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a

match of TM00 and CR000.

p. 106

timer/event

counter 00

(TM00)

capture/compare

register 000

If CR000 is set to 0000H in the free-running mode and in the clear mode using the valid

edge of the TI000 pin, an interrupt request (INTTM000) is generated when the value of

CR000 changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover,

INTTM000 is generated after a match of TM00 and CR000 is detected, a valid edge of the

TI010 pin is detected, and the timer is cleared by a one-shot trigger.

p. 106

When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00). p. 106

When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.

When CR000 is used as a capture register, read data is undefined if the register read time p. 106

and capture trigger input conflict (the capture data itself is the correct value).

If timer count stop and capture trigger input conflict, the captured data is undefined.

Do not rewrite CR000 during TM00 operation.

pp. 106,

114, 119,

131

CR010: 16-bit

timer

If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when the value p. 107

of CR010 changes from 0000H to 0001H following TM00 overflow (FFFFH). Moreover,

capture/compare INTTM010 is generated after a match of TM00 and CR010 is detected, a valid edge of the

register 010

TI000 pin is detected, and the timer is cleared by a one-shot trigger.

When CR010 is used as a capture register, read data is undefined if the register read time p. 107

and capture trigger input conflict (the capture data itself is the correct value).

If count stop input and capture trigger input conflict, the captured data is undefined.

CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15. p. 107

TMC00: 16-bit

timer mode

16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are

set to values other than 0, 0 (operation stop mode), respectively. Clear TMC002 and

p. 108

control register 00 TMC003 to 0, 0 to stop operation.

Timer operation must be stopped before writing to bits other than the OVF00 flag.

p. 109

Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).

If any of the following modes: the mode in which clear & start occurs on match between

TM00 and CR000, the mode in which clear & start occurs at the valid edge of the TI000 pin

or free-running mode is selected, when the set value of CR000 is FFFFH and the TM00

value changes from FFFFH to 0000H, the OVF00 flag is set to 1.

CRC00:

Timer operation must be stopped before setting CRC00.

p. 110

Capture/compare

control register 00

When the mode in which clear & start occurs on a match between TM00 and CR000 is

selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified

as a capture register.

To ensure that the capture operation is performed properly, the capture trigger requires a

pulse two cycles longer than the count clock selected by prescaler mode register 00

(PRM00).

p. 110

TOC00: 16-bit

timer output

Timer operation must be stopped before setting other than TOC004.

LVS00 and LVR00 are 0 when they are read.

p. 111

control register 00

OSPT00 is automatically cleared after data is set, so 0 is read.

Do not set OSPT00 to 1 other than in one-shot pulse output mode.

A write interval of two cycles or more of the count clock selected by prescaler mode register p. 111

00 (PRM00) is required to write to OSPT00 successively.

Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1

simultaneously.

p. 111

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Cautions

Page

16-bit

TOC00: 16-bit

timer output

Do not make settings <1> and <2> below simultaneously. In addition, follow the setting

procedure shown below.

p. 111

timer/event

counter 00

(TM00)

control register 00 <1> Setting of TOC001, TOC004, TOE00, and OSPE00: Setting of timer output operation

<2> Setting of LVS00 and LVR00: Setting of timer output F/F

PRM00: Prescaler When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

mode register 00 clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 16-bit timer/event counter 00 is not

guaranteed. When an external clock is used and when the internal oscillation clock is

selected and supplied to the CPU, the operation of 16-bit timer/event counter 00 is not

guaranteed, either, because the internal oscillation clock is supplied as the sampling clock

to eliminate noise.

p. 113

Always set data to PRM00 after stopping the timer operation.

p. 113

If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start p. 113

mode using the valid edge of the TI000 pin and the capture trigger.

If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is

immediately detected after the rising edge or both the rising and falling edges are set as the

valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00

(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when

re-enabling operation after the operation has been stopped, the rising edge is not detected

if the TI000 or TI010 pin is high level.

p. 113

When the TI010 pin valid edge is used, P01 cannot be used as the timer output pin (TO00). p. 113

When P01 is used as the TO00 pin, the TI010 pin valid edge cannot be used.

CR010: 16-bit

timer

To change the value of the duty factor (the value of the CR010 register) during operation,

see Caution 2 in Figure 6-15 PPG Output Operation Timing.

p. 117

capture/compare

register 010

CR000, CR010:

16-bit timer

Values in the following range should be set in CR000 and CR010:

p. 118

0000H ≤ CR010 < CR000 ≤ FFFFH

capture/compare

registers 000, 010

The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty p. 118

of (CR010 setting value + 1)/(CR000 setting value + 1).

PPG output

In the PPG output operation, change the pulse width (rewrite CR010) during TM00

operation using the following procedure.

p. 119

<1> Disable the timer output inversion operation by match of TM00 and CR010

(TOC004 = 0)

<2> Disable the INTTM010 interrupt (TMMK010 = 1)

<3> Rewrite CR010

<4> Wait for 1 cycle of the TM00 count clock

<5> Enable the timer output inversion operation by match of TM00 and CR010

(TOC004 = 1)

<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)

<7> Enable the INTTM010 interrupt (TMMK010 = 0)

Pulse width

To use two capture registers, set the TI000 and TI010 pins.

p. 120

p. 130

measurement

External event

counter

When reading the external event counter count value, TM00 should be read.

One-shot pulse

output: Software

trigger

Do not set the OSPT00 bit to 1 while the one-shot pulse is being output. To output the one- p. 133

shot pulse again, wait until the current one-shot pulse output is completed.

When using the one-shot pulse output of 16-bit timer/event counter 00 with a software

trigger, do not change the level of the TI000 pin or its alternate-function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even

at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a

pulse at an undesired timing.

p. 133

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Cautions

Page

p. 134

16-bit

One-shot pulse

output: Software

trigger

Do not set 0000H to the CR000 and CR010 registers.

timer/event

counter 00

(TM00)

p. 135

16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002 bits are set to

a value other than 00 (operation stop mode).

p. 135

One-shot pulse

output: External

trigger

Even if the external trigger is generated again while the one-shot pulse is being output, it is

ignored.

p. 136

p. 137

Do not set the CR000 and CR010 registers to 0000H.

16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003 bits are set to

a value other than 00 (operation stop mode).

p. 138

Timer start errors An error of up to one clock may occur in the time required for a match signal to be

generated after timer start. This is because 16-bit timer counter 00 (TM00) is started

asynchronously to the count clock.

16-bit timer

In the mode in which clear & start occurs on a match between TM00 and CR000, set 16-bit

capture/compare timer capture/compare register 000 (CR000) to other than 0000H. This means a 1-pulse

register setting

count operation cannot be performed when 16-bit timer/event counter 00 is used as an

external event counter.

p. 138

Capture register

data retention

timing

The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) are

not guaranteed after 16-bit timer/event counter 00 has been stopped.

Valid edge setting Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-

bit timer mode control register 00 (TMC00) to 0, 0, respectively, and then stopping timer

operation. The valid edge is set using bits 4 and 5 (ES000 and ES001) of prescaler mode

register 00 (PRM00).

p. 138

One-shot pulse

output: Software

trigger

When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-

shot pulse again until INTTM000, which occurs upon a match with the CR000 register, or

INTTM010, which occurs upon a match with the CR010 register, occurs.

One-shot pulse

output: External

trigger

If the external trigger occurs again while a one-shot pulse is output, it is ignored.

One-shot pulse

output function

When using the one-shot pulse output of 16-bit timer/event counter 00 with a software

trigger, do not change the level of the TI000 pin or its alternate function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even

at the level of the TI000 pin or its alternate function port pin, resulting in the output of a

pulse at an undesired timing.

p. 139

Operation of

OVF00 flag

The OVF00 flag is also set to 1 in the following case.

When of the following modes: the mode in which clear & start occurs on a match between

TM00 and CR000, the mode in which clear & start occurs at the TI000 pin valid edge, or the

free-running mode, is selected

→ CR000 is set to FFFFH

→ TM00 is counted up from FFFFH to 0000H.

p. 139

Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes

0001H) after the occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is

disabled.

Conflicting

operations

When the read period of the 16-bit timer capture/compare register (CR000/CR010) and

capture trigger input (CR000/CR010 used as capture register) conflict, the priority is given

to the capture trigger input. The data read from CR000/CR010 is undefined.

p. 140

Timer operation

Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer

capture/compare register 010 (CR010).

Regardless of the CPU’s operation mode, when the timer stops, the input signals to the

TI000/TI010 pins are not acknowledged.

The one-shot pulse output mode operates correctly only in the free-running mode and the

mode in which clear & start occurs at the TI000 valid edge. In the mode in which clear &

start occurs on a match between the TM00 register and CR000 register, one-shot pulse

output is not possible because an overflow does not occur.

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Details of Function

Cautions

Page

16-bit

Capture operation If the TI000 pin valid edge is specified as the count clock, a capture operation by the

capture register specified as the trigger for TI000 is not possible.

p. 140

timer/event

counter 00

(TM00)

To ensure the reliability of the capture operation, the capture trigger requires a pulse two

cycles longer than the count clock selected by prescaler mode register 00 (PRM00).

p. 140

The capture operation is performed at the falling edge of the count clock. An interrupt

request input (INTTM000/INTTM010), however, is generated at the rise of the next count

clock.

Compare

operation

A capture operation may not be performed for CR000/CR010 set in compare mode even if p. 140

a capture trigger has been input.

Edge detection

If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or p. 140

both the rising and falling edges are specified as the valid edge of the TI000 or TI010 pin to

enable the 16-bit timer counter 00 (TM00) operation, a rising edge is detected immediately

after the operation is enabled. Be careful therefore when pulling up the TI000 or TI010 pin.

However, when re-enabling operation after the operation has been stopped, the rising edge

is not detected if the TI000 or TI010 pin is high level.

The sampling clock used to eliminate noise differs when the TI000 pin valid edge is used as p. 140

the count clock and when it is used as a capture trigger. In the former case, the count clock

is fX, and in the latter case the count clock is selected by prescaler mode register 00

(PRM00). The capture operation is started only after a valid level is detected twice by

sampling the valid edge, thus eliminating noise with a short pulse width.

8-bit

CR50: 8-bit timer In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not

compare register write other values to CR50 during operation.

p. 143

p. 144

timer/event

counter 50

(TM50)

50

In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock

selected by TCL50) or more.

TCL50: Timer

clock selection

register 50

When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer/event counter 50 is not

guaranteed.

When rewriting TCL50 to other than the same data, stop the timer operation beforehand.

Be sure to set bits 3 to 7 to 0.

p. 144

p. 146

TMC50: 8-bit

timer mode

The settings of LVS50 and LVR50 are valid in other than PWM mode.

Do not make settings <1> to <4> below simultaneously. In addition, follow the setting

procedure shown below.

control register 50

<1> Setting of TMC501 and TMC506: Setting of operation mode

<2> Setting of TOE50 if enabling output: Enabling timer output

<3> Setting of LVS50 and LVR50 (see Caution 1): Setting of timer output F/F

<4> Setting of TCE50

Stop operation before rewriting TMC506.

p. 146

Interval

Do not write other values to CR50 during operation.

pp. 147,

150

timer/square wave

output

PWM output

In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock

selected by TCL50) or more.

p. 151

When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from p. 153

the actual value (read value: M, actual value of CR50: N).

Timer start error

An error of up to one clock may occur in the time required for a match signal to be

generated after timer start. This is because 8-bit timer counter 50 (TM50) is started

asynchronously to the count clock.

p. 153

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Function

Details of Function

Cautions

Page

8-bit timers

H0, H1

CMP0n: 8-bit

timer H compare

register 0n

CMP0n cannot be rewritten during timer count operation.

p. 157

(TMH0,

TMH1)

CMP1n: 8-bit

In the PWM output mode be sure to set CMP1n when starting the timer count operation

p. 157

p. 160

timer H compare (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set

register 1n

again even if setting the same value to CMP1n).

TMHMD0: 8-bit

timer H mode

register 0

When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer H0 is not guaranteed.

When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.

p. 160

In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when

starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped

(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).

TMHMD1: 8-bit

timer H mode

register 1

When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the count clock

is the internal oscillation clock, the operation of 8-bit timer H1 is not guaranteed (except

p. 161

when CKS12, CKS11, CKS10 = 1, 0, 1 (f

/2⁷)).

R

When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.

p. 161

In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when

starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped

(TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).

PWM output

In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0

bits of the TMHMDn register) are required to transfer the CMP1n register value after

rewriting the register.

p. 166

Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1)

after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if

setting the same value to the CMP1n register).

Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) p. 167

are within the following range.

00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH

Watchdog

timer

WDTM: Watchdog If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 27

p. 174

timer mode

register

CAUTIONS FOR WAIT.

Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Internal oscillator cannot be stopped” p. 174

is selected by the option byte, other values are ignored).

After reset is released, WDTM can be written only once by an 8-bit memory manipulation

instruction. If writing is attempted a second time, an internal reset signal is generated. If

the source clock to the watchdog timer is stopped, however, an internal reset signal is

generated when the source clock to the watchdog timer resumes operation.

p. 174

WDTM cannot be set by a 1-bit memory manipulation instruction.

p. 174

If “Internal oscillator can be stopped by software” is selected by the option byte and the

watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not resume

operation even if WDCS4 is cleared to 0. In addition, the internal reset signal is not

generated.

WDTE: Watchdog If a value other than ACH is written to WDTE, an internal reset signal is generated. If the

p. 175

timer enable

register

source clock to the watchdog timer is stopped, however, an internal reset signal is

generated when the source clock to the watchdog timer resumes operation.

If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is p. 175

generated. If the source clock to the watchdog timer is stopped, however, an internal reset

signal is generated when the source clock to the watchdog timer resumes operation.

The value read from WDTE is 9AH (this differs from the written value (ACH)).

p. 175

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Function

Details of Function

Cautions

Page

Watchdog

timer

When “Internal

oscillator cannot

be stopped” is

In this mode, operation of the watchdog timer absolutely cannot be stopped even during

STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the internal oscillation

clock can be selected as the count source, so after STOP instruction execution, clear the

p. 176

selected by option watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows. If

byte

this processing is not performed, an internal reset signal is generated when the watchdog

timer overflows after STOP instruction execution.

When “Internal

oscillator can be

stopped by

In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution. p. 177

After HALT/STOP mode is released, counting is started again using the operation clock of

the watchdog timer set before HALT/STOP instruction execution by WDTM. At this time,

the counter is not cleared to 0 but holds its value.

software” is

selected by option

byte

A/D converter ADM: A/D

converter mode

register

A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the

identical data.

p. 185

For the sampling time of the A/D converter and the A/D conversion start delay time, see

(11) in 10.6 Cautions for A/D Converter.

If data is written to ADM, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

ADS: Analog input Be sure to clear bits 2 to 7 of ADS to 0.

channel

p. 186

If data is written to ADS, a wait cycle is generated. For details, see CHAPTER 27

specification

register

CAUTIONS FOR WAIT.

ADCR: A/D

When writing to the A/D converter mode register (ADM) and analog input channel

p. 186

conversion result specification register (ADS), the contents of ADCR may become undefined. Read the

register

conversion result following conversion completion before writing to ADM and ADS. Using

timing other than the above may cause an incorrect conversion result to be read.

If data is read from ADCR, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

p. 186

p. 187

PFM: Power-fail

If data is written to PFM, a wait cycle is generated. For details, see CHAPTER 27

comparison mode CAUTIONS FOR WAIT.

register

PFT: Power-fail

comparison

If data is written to PFT, a wait cycle is generated. For details, see CHAPTER 27

p. 187

CAUTIONS FOR WAIT.

threshold register

A/D conversion

Make sure the period of <1> to <3> is 14 µs or more.

p. 193

It is no problem if the order of <1> and <2> is reversed.

<1> can be omitted. However, do not use the first conversion result after <3> in this case. p. 193

The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.

p. 193

Power-fail

Make sure the period of <3> to <6> is 14 µs or more.

It is no problem if the order of <3>, <4>, and <5> is changed.

<3> must not be omitted if the power-fail function is used.

p. 193

detection function

The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.

Operating current The A/D converter stops operating in the standby mode. At this time, the operating current p. 196

in standby mode can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode

register (ADM) to 0 (see Figure 10-2).

Input range of

ANI0 to ANI3

Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AVREF or higher

and AV^SSor lower (even in the range of absolute maximum ratings) is input to an analog

input channel, the converted value of that channel becomes undefined. In addition, the

converted values of the other channels may also be affected.

p. 196

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Function

Details of Function

Cautions

Page

A/D converter Conflicting

operations

Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction p. 196

upon the end of conversion

ADCR read has priority. After the read operation, the new conversion result is written to

ADCR.

Conflict between ADCR write and A/D converter mode register (ADM) write or analog input p. 196

channel specification register (ADS) write upon the end of conversion

ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end

interrupt signal (INTAD) generated.

Noise

To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF and

p. 197

countermeasures ANI0 to ANI3 pins. Because the effect increases in proportion to the output impedance of

the analog input source, it is recommended that a capacitor be connected externally, as

shown in Figure 10-19, to reduce noise.

ANI0/P20 to

ANI3/P23

The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).

When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2

while conversion is in progress; otherwise the conversion resolution may be degraded.

p. 197

If a digital pulse is applied to the pins adjacent to the pins currently being used for A/D

conversion, the expected value of the A/D conversion may not be obtained due to coupling

noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D

conversion.

Input impedance In this A/D converter, the internal sampling capacitor is charged and sampling is performed p. 197

of ANI0 to ANI3

pins

for approx. one sixth of the conversion time.

Since only the leakage current flows other than during sampling and the current for

charging the capacitor also flows during sampling, the input impedance fluctuates and has

no meaning.

To perform sufficient sampling, however, it is recommended to make the output impedance

of the analog input source 10 kΩ or lower, or attach a capacitor of around 100 pF to the

ANI0 to ANI3 pins (see Figure 10-19).

AVREF pin input

impedance

A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins. p. 197

Therefore, if the output impedance of the reference voltage source is high, this will result in

a series connection to the series resistor string between the AV^REFand AVSS pins, resulting

in a large reference voltage error.

Interrupt request The interrupt request flag (ADIF) is not cleared even if the analog input channel

p. 198

flag (ADIF)

specification register (ADS) is changed.

Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion

result and ADIF for the pre-change analog input may be set just before the ADS rewrite.

Caution is therefore required since, at this time, when ADIF is read immediately after the

ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change analog input

has not finished.

When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion

operation is resumed.

Conversion

results just after

A/D conversion

start

The first A/D conversion value immediately after A/D conversion starts may not fall within

the rating range if the ADCS bit is set to 1 within 14 µs after the ADCE bit was set to 1, or if

the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D

conversion end interrupt request (INTAD) and removing the first conversion result.

p. 198

A/D conversion

result register

(ADCR) read

operation

When a write operation is performed to the A/D converter mode register (ADM) and analog p. 198

input channel specification register (ADS), the contents of ADCR may become undefined.

Read the conversion result following conversion completion before writing to ADM and

ADS. Using a timing other than the above may cause an incorrect conversion result to be

read.

A/D converter

The A/D converter sampling time differs depending on the set value of the A/D converter

p. 199

sampling time and mode register (ADM). A delay time exists until actual sampling is started after A/D

A/D conversion

start delay time

converter operation is enabled.

When using a set in which the A/D conversion time must be strictly observed, care is

required regarding the contents shown in Figure 10-21 and Table 10-3.

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Function

Details of Function

UART mode

Cautions

Page

If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The TXD0 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.

Serial

p. 201

interface

UART0

Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start

communication.

p. 201

TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable

transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock

after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of

base clock, the transmission circuit or reception circuit may not be initialized.

TXS0: Transmit

shift register 0

Do not write the next transmit data to TXS0 before the transmission completion interrupt

signal (INTST0) is generated.

p. 204

p. 206

ASIM0:

At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to

0, and then clear POWER0 to 0.

Asynchronous

serial interface

operation mode

register 0

At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to

0, and then clear POWER0 to 0.

Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If

POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.

TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable

transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock

after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of

base clock, the transmission circuit or reception circuit may not be initialized.

Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.

p. 206

Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with

“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.

Be sure to set bit 0 to 1.

p. 206

p. 207

ASIS0:

The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits

of asynchronous serial interface operation mode register 0 (ASIM0).

Asynchronous

serial interface

reception error

status register 0

Only the first bit of the receive data is checked as the stop bit, regardless of the number of

stop bits.

p. 207

p. 209

If an overrun error occurs, the next receive data is not written to receive buffer register 0

(RXB0) but discarded.

If data is read from ASIS0, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

BRGC0: Baud

rate generator

When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the base clock is

control register 0 the internal oscillation clock, the operation of serial interface UART0 is not guaranteed.

Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the

MDL04 to MDL00 bits.

p. 209

p. 210

The baud rate value is the output clock of the 5-bit counter divided by 2.

POWER0, TXE0, Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.

RXE0: Bits 7, 6, 5 To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1.

of ASIM0

UART mode

Take relationship with the other party of communication when setting the port mode register

and port register.

p. 211

p. 214

p. 215

UART

After transmit data is written to TXS0, do not write the next transmit data before the

transmission completion interrupt signal (INTST0) is generated.

transmission

UART reception

Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

Reception is always performed with the “number of stop bits = 1”. The second stop bit is

ignored.

p. 215

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Function

Details of Function

UART reception

Cautions

Page

Serial

Be sure to read asynchronous serial interface reception error status register 0 (ASIS0)

before reading RXB0.

p. 215

interface

UART0

Error of baud rate Keep the baud rate error during transmission to within the permissible error range at the

reception destination.

p. 218

p. 220

Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Permissible baud Make sure that the baud rate error during reception is within the permissible error range, by

rate range during using the calculation expression shown below.

reception

Serial

UART mode

The TXD6 output inversion function inverts only the transmission side and not the reception

side. To use this function, the reception side must be ready for reception of inverted data.

p. 222

interface

UART6

If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The TXD6 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.

If data is continuously transmitted, the communication timing from the stop bit to the next

start bit is extended two operating clocks of the macro. However, this does not affect the

result of communication because the reception side initializes the timing when it has

detected a start bit. Do not use the continuous transmission function if the interface is

incorporated in LIN.

p. 222

TXB6: Transmit

buffer register 6

Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission

status register 6 (ASIF6) is 1.

p. 228

Do not refresh (write the same value to) TXB6 by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface

operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of

ASIM6 are 1).

ASIM6:

At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to

0 and then clear POWER6 to 0.

p. 230

Asynchronous

serial interface

operation mode

register 6

At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to

0 and then clear POWER6 to 0.

Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If

POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.

Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.

Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.

p. 230

Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with

“the number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.

Make sure that RXE6 = 0 when rewriting the ISRM6 bit.

p. 230

p. 231

ASIS6:

The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits

of asynchronous serial interface operation mode register 6 (ASIM6).

Asynchronous

serial interface

reception error

status register 6

The first bit of the receive data is checked as the stop bit, regardless of the number of stop

bits.

p. 231

p. 232

If an overrun error occurs, the next receive data is not written to receive buffer register 6

(RXB6) but discarded.

If data is read from ASIS6, a wait cycle is generated. For details, see CHAPTER 27

CAUTIONS FOR WAIT.

ASIF6:

To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

Asynchronous

serial interface

transmission

status register 6

To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

transmit data cannot be guaranteed.

p. 232

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Function

Details of Function

CKSR6: Clock

Cautions

Page

Serial

When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

p. 234

interface

UART6

selection register clock of the internal oscillator is divided and supplied as the count clock. If the base clock

6

is the internal oscillation clock, the operation of serial interface UART6 is not guaranteed.

Make sure POWER6 = 0 when rewriting TPS63 to TPS60.

p. 234

p. 235

BRGC6: Baud

rate generator

control register 6

Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the

MDL67 to MDL60 bits.

The baud rate value is the output clock of the 8-bit counter divided by 2.

p. 235

p. 236

ASICL6:

ASICL6 can be refreshed (the same value is written) by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit

5 (RXE6) of ASIM6 = 1). Note, however, that communication is started by the refresh

Asynchronous

serial interface

control register 6 operation because bit 6 (SBRT6) of ASICL6 is cleared to 0 when communication is

completed (when an interrupt signal is generated).

In the case of an SBF reception error, return the mode to the SBF reception mode. The

status of the SBRF6 flag is held (1).

p. 237

Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = p. 237

1.

The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after

SBF reception has been correctly completed.

p. 237

Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of

ASIM6 = 1.

The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the

end of SBF transmission.

Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.

p. 237

When using the 78K0/KB1+ to evaluate the program of a mask ROM version of the

78K0/KB1, set the SBTT6, SBL62, SBL61, and SBL60 bits to 0, 1, 0, 1, respectively.

POWER6, TXE6, Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.

p. 239

RXE6: Bits 7, 6,

5 of ASIM6

To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.

UART mode

Take relationship with the other party of communication when setting the port mode

register and port register.

p. 240

p. 244

p. 246

Parity types and

operation

Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.

Continuous

The TXBF6 and TXSF6 flags of the ASIF6 register change from “10” to “11”, and to “01”

during continuous transmission. To check the status, therefore, do not use a combination

of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag when executing

continuous transmission.

transmission

When the device is incorporated in a LIN, the continuous transmission function cannot be

used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6)

is 00H before writing transmit data to transmit buffer register 6 (TXB6).

p. 246

TXBF6 when

continuous

To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second

transmission: Bit byte) to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is

1 of ASIF6

“1”, the transmit data cannot be guaranteed.

TXSF6 when

continuous

To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

p. 246

transmission: Bit and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

1 of ASIF6

transmit data cannot be guaranteed.

During continuous transmission, an overrun error may occur, which means that the next

transmission was completed before execution of INTST6 interrupt servicing after

transmission of one data frame. An overrun error can be detected by developing a

program that can count the number of transmit data and by referencing the TXSF6 flag.

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Function

Details of Function

Cautions

Page

Serial

Normal reception Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

p. 250

interface

UART6

Reception is always performed with the “number of stop bits = 1”. The second stop bit is

ignored.

p. 250

p. 256

Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)

before reading RXB6.

Generation of

serial clock

Keep the baud rate error during transmission to within the permissible error range at the

reception destination.

Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Permissible baud Make sure that the baud rate error during reception is within the permissible error range, by p. 258

rate range during using the calculation expression shown below.

reception

Serial

SOTB10:

Do not access SOTB10 when CSOT10 = 1 (during serial communication).

p. 262

interface

CSI10

Transmit buffer

register 10

SIO10: Serial I/O Do not access SIO10 when CSOT10 = 1 (during serial communication).

shift register 10

p. 262

p. 263

CSIM10: Serial

operation mode

register 10

Be sure to clear bit 5 to 0.

CSIC10: Serial

clock selection

register 10

When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of p. 265

the internal oscillator is divided and supplied as the serial clock. At this time, the operation

of serial interface CSI10 is not guaranteed.

Do not write to CSIC10 while CSIE10 = 1 (operation enabled).

p. 265

To use P10/SCK10(/TxD0), P11/SI10(/RxD0), and P12/SO10 as general-purpose ports, set p. 265

CSIC10 in the default status (00H).

The phase type of the data clock is type 1 after reset.

p. 265

3-wire serial I/O

mode

Take relationship with the other party of communication when setting the port mode register p. 267

and port register.

Communication

operation

Do not access the control register and data register when CSOT10 = 1 (during serial

communication).

p. 269

SO10 output

If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.

Be sure to set bits 2 to 7 of IF1L to 0.

p. 274

p. 279

Interrupt

IF1L: Interrupt

request flag

register

IF0L, IF0H, IF1L: When operating a timer, serial interface, or A/D converter after standby release, operate it

Interrupt request once after clearing the interrupt request flag. An interrupt request flag may be set by noise.

p. 279

flag registers

Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of the

interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0 = 0;” and

“_asm(“clr1 IF0L, 0”);” should be used when describing in C language, because assembly

instructions after compilation must be 1-bit memory manipulation instructions (CLR1).

If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C language, for

example, it is converted to the following three assembly instructions after compilation:

mov

and

mov

a, IF0L

a, #0FEH

IF0L, a

In this case, at the timing between “mov a, IF0L” and “mov IF0L, a”, if the request flag of

another bit of the identical interrupt request flag register is set to 1, it is cleared to 0 by “mov

IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation

instruction in C language.

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Function

Details of Function

Cautions

Page

Interrupt

MK1L: Interrupt

Be sure to set bits 2 to 7 of MK1L to 1.

Be sure to set bits 2 to 7 of PR1L to 1.

p. 280

mask flag register

PR1L: Priority

specification flag

register

p. 281

EGP, EGN:

Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected p. 282

External interrupt when the external interrupt function is switched to the port function.

rising, falling edge

enable registers

Software interrupt Do not use the RETI instruction for restoring from the software interrupt.

p. 286

p. 290

request

acknowledgment

Interrupt request The BRK instruction is not one of the above-listed interrupt request hold instructions.

hold

However, the software interrupt activated by executing the BRK instruction causes the IE

flag to be cleared to 0. Therefore, even if a maskable interrupt request is generated during

execution of the BRK instruction, the interrupt request is not acknowledged.

Standby

function

−

The RSTOP setting is valid only when “Can be stopped by software” is set for the internal

oscillator by the option byte.

p. 291

When shifting to the STOP mode, be sure to stop the peripheral hardware operation before p. 292

executing STOP instruction.

STOP mode,

HALT mode

The following sequence is recommended for operating current reduction of the A/D

converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of

the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then

execute the HALT or STOP instruction.

p. 292

STOP mode

If the internal oscillator is operating before the STOP mode is set, oscillation of the internal p. 292

oscillation clock cannot be stopped in the STOP mode. However, when the internal

oscillation clock is used as the CPU clock, CPU operation is stopped for 17/f

R

(s) after

STOP mode is released.

OSTC: Oscillation Waiting for the oscillation stabilization time is not required when the external RC oscillation p. 293

stabilization time clock is selected as the high-speed system clock by the option byte. Therefore, the CPU

counter status

register

clock can be switched without reading the OSTC value.

After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. p. 293

If the STOP mode is entered and then released while the internal oscillation clock is being

used as the CPU clock, set the oscillation stabilization time as follows.

p. 293

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS

The oscillation stabilization time counter counts only during the oscillation stabilization time

set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time

set by OSTS are set to OSTC after STOP mode has been released.

The wait time when STOP mode is released does not include the time after STOP mode

release until clock oscillation starts (“a” below) regardless of whether STOP mode is

released by RESET input or interrupt generation.

p. 293

p. 294

OSTS: Oscillation To set the STOP mode when the high-speed system clock is used as the CPU clock, set

stabilization time OSTS before executing a STOP instruction.

select register

Execute the OSTS setting after confirming that the oscillation stabilization time has elapsed p. 294

as expected in the OSTC.

If the STOP mode is entered and then released while the internal oscillation clock is being

used as the CPU clock, set the oscillation stabilization time as follows.

p. 294

• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS

The oscillation stabilization time counter counts only during the oscillation stabilization time

set by OSTS. Therefore, note that only the statuses during the oscillation stabilization time

set by OSTS are set to OSTC after STOP mode has been released.

The wait time when STOP mode is released does not include the time after STOP mode

release until clock oscillation starts (“a” below) regardless of whether STOP mode is

released by RESET input or interrupt generation.

p. 294

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Function

Details of Function

Cautions

Page

Standby

STOP mode

setting and

Because the interrupt request signal is used to clear the standby mode, if there is an

interrupt source with the interrupt request flag set and the interrupt mask flag reset, the

p. 298

function

operating statuses standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT

mode immediately after execution of the STOP instruction and the system returns to the

operating mode as soon as the wait time set using the oscillation stabilization time select

register (OSTS) has elapsed.

Reset function

−

For an external reset, input a low level for 10 µs or more to the RESET pin.

p. 302

During reset input, the high-speed system clock and the internal oscillation clock stop

oscillating.

When the STOP mode is released by a reset, the STOP mode contents are held during

reset input. However, the port pins become high-impedance, except for P130, which is set

to low-level output.

p. 302

An LVI circuit internal reset does not reset the LVI circuit.

p. 303

p. 304

Reset timing due A watchdog timer internal reset resets the watchdog timer.

to watchdog timer

overflow

RESF: Reset

control flag

register

Do not read data via a 1-bit memory manipulation instruction.

p. 308

Clock monitor CLM: Clock

monitor mode

Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the

internal reset signal.

p. 310

register

If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1

(CLMRF) of the reset control flag register (RESF) is set to 1.

Operation of clock Waiting for the oscillation stabilization time is not required when the external RC oscillation pp. 312,

monitor

clock is selected as the high-speed system clock by the option byte. Therefore, the CPU

clock can be switched without reading the OSTC value. However, the clock monitor starts

operation after the oscillation stabilization time (OSTS register reset value = 05H (2¹⁶/fXP))

has elapsed.

313

Power-on-

clear circuit

(POC)

Functions of

power-on-clear

circuit

If an internal reset signal is generated in the POC circuit, the reset control flag register

(RESF) is cleared to 00H.

p. 316

The supply voltage is VDD = 2.0 to 5.5 V when the internal oscillation clock is used, but be

sure to use the standard products and (A) grade products in a voltage range of 2.2 to 5.5 V

because the detection voltage (V^POC) of the POC circuit is 2.1 V 0.1 V.

The supply voltage is V^DD= 2.0 to 5.5 V when the internal oscillation clock is used, but be

sure to use the (A1) grade products in a voltage range of 2.25 to 5.5 V because the

detection voltage (V^POC) of the POC circuit is 2.0 to 2.25 V.

p. 316

p. 318

Cautions for

power-on-clear

circuit

In a system where the supply voltage (V^DD) fluctuates for a certain period in the vicinity of

the POC detection voltage (V^POC), the system may be repeatedly reset and released from

the reset status. In this case, the time from release of reset to the start of the operation of

the microcontroller can be arbitrarily set by taking the following action.

Low-voltage

LVIM: Low-

To stop LVI, follow either of the procedures below.

p. 321

detector (LVI) voltage detection • When using 8-bit manipulation instruction: Write 00H to LVIM.

register • When using 1-bit memory manipulation instruction: Clear LVION to 0.

LVIS: Low-voltage Be sure to clear bits 4 to 7 to 0.

detection level

p. 322

Clear all port pins after the supply voltage (V^DD) exceeds the preset detection voltage (VLVI

)

selection register

after POC release in the (A1) grade products.

When used as

reset

<1> must always be executed. When LVIMK = 0, an interrupt may occur immediately after p. 323

the processing in <3>.

If supply voltage (V^DD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset

p. 323

signal is not generated.

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Function

Details of Function

Cautions

Page

Low-voltage

Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of

p. 327

detector (LVI) voltage detector

the LVI detection voltage (V^LVI), the operation is as follows depending on how the low-

voltage detector is used.

(1) When used as reset

The system may be repeatedly reset and released from the reset status.

In this case, the time from release of reset to the start of the operation of the

microcontroller can be arbitrarily set by taking action (a) below.

(2) When used as interrupt

Interrupt requests may be frequently generated. Take action (b) below.

Option byte

−

Be sure to set 00H to 0081H, 0082H, 0083H, and 0084H (0081H/1081H, 0082H/1082H,

0083H/1083H, and 0084H/1084H when the boot swap function is used).

p. 330

If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to

the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0

(RSTOP) of the internal oscillation mode register (RCM). When 8-bit timer H1 operates

with the internal oscillation clock, the count clock is supplied to 8-bit timer H1 even in the

HALT/STOP mode.

Be sure to clear bits 2 to 7 to 0.

p. 330

Flash

−

There are differences in noise immunity and noise radiation between the flash memory and p. 332

mask ROM versions. When pre-producing an application set with the flash memory

version and then mass-producing it with the mask ROM version, be sure to conduct

sufficient evaluations for the commercial samples (not engineering samples) of the mask

ROM versions.

memory

IMS: Memory

size switching

register

The initial value of IMS is “setting prohibited (CFH)”. Be sure to set the value shown in

Table 21-2 for each product at initialization. When using the 78K0/KB1+ to evaluate the

program of a mask ROM version of the 78K0/KB1, be sure to set the values shown in

Table 21-2.

p. 333

UART6

When UART6 is selected, the receive clock is calculated based on the reset command sent p. 346

from the dedicated flash programmer after the FLMD0 pulse has been received.

FLPMC: Flash

programming

mode control

register

Be sure to keep FWEDIS at 0 until writing or erasing of the flash memory is completed.

Make sure that FWEDIS = 1 in the normal mode.

p. 350

Manipulate FLSPM1 and FLSPM0 after execution branches to the internal RAM. The

address of the flash memory is specified by an address signal from the CPU when

FLSPM1 = 0 or the set value of the firmware written when FLSPM1 = 1. In the on-board

mode, the specifications of FLSPM1 and FLSPM0 are ignored.

Electrical

Absolute

Product quality may suffer if the absolute maximum rating is exceeded even momentarily

for any parameter. That is, the absolute maximum ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be

used under conditions that ensure that the absolute maximum ratings are not exceeded.

p. 370

p. 371

specifications Maximum

(standard

products, (A)

grade

Ratings

High-speed

When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

products)

system clock

(crystal/ceramic) • Keep the wiring length as short as possible.

oscillator

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Since the CPU is started by the internal oscillation clock after reset is released, check the

oscillation stabilization time of the crystal/ceramic oscillation clock using the oscillation

stabilization time counter status register (OSTC). Determine the oscillation stabilization

time of the OSTC register and oscillation stabilization time select register (OSTS) after

sufficiently evaluating the oscillation stabilization time with the resonator to be used.

p. 371

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Function

Details of Function

High-speed

Cautions

Page

Electrical

When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the p. 372

above figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

specifications system clock

(standard (external RC)

products, (A) oscillator

grade

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

products)

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC

R = 6.8 kΩ, C = 22 pF Target value: 3 MHz

R = 4.7 kΩ, C = 22 pF Target value: 4 MHz

Set one of the above values to R and C.

p. 372

p. 373

oscillation

frequency

Recommended

oscillator

The oscillator constants shown above are reference values based on evaluation in a

specific environment by the resonator manufacturer. If it is necessary to optimize the

oscillator characteristics in the actual application, apply to the resonator manufacturer for

evaluation on the implementation circuit. The oscillation voltage and oscillation frequency

only indicate the oscillator characteristic. Use the 78K0/KB1+ so that the internal operation

conditions are within the specifications of the DC and AC characteristics.

constants

Electrical

Absolute

Product quality may suffer if the absolute maximum rating is exceeded even momentarily

p. 384

p. 385

specifications Maximum Ratings for any parameter. That is, the absolute maximum ratings are rated values at which the

((A1) grade

products)

product is on the verge of suffering physical damage, and therefore the product must be

used under conditions that ensure that the absolute maximum ratings are not exceeded.

High-speed

When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

system clock

(crystal/ceramic) • Keep the wiring length as short as possible.

oscillator

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Since the CPU is started by the internal oscillation clock after reset is released, check the

oscillation stabilization time of the crystal/ceramic oscillation clock using the oscillation

stabilization time counter status register (OSTC). Determine the oscillation stabilization

time of the OSTC register and oscillation stabilization time select register (OSTS) after

sufficiently evaluating the oscillation stabilization time with the resonator to be used.

p. 385

High-speed

system clock

(external RC)

oscillator

When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the p. 386

above figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS

.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

R = 6.8 kΩ, C = 22 pF Target value: 3 MHz

R = 4.7 kΩ, C = 22 pF Target value: 4 MHz

Set one of the above values to R and C.

p. 386

p. 398

Recommended

soldering

−

Do not use different soldering methods together (except for partial heating).

conditions

434

User’s Manual U16846EJ3V0UD

APPENDIX E REVISION HISTORY

E.1 Major Revisions in This Edition

Page

Description

Throughout

Addition of product name, specification, and classification by case on (A) grade products and (A1) grade

products

Modification of Note and Caution in serial operation mode register (CSIM10, CSIM11) and serial clock

selection register (CSIC10, CSIC11)

p. 15

p. 16

p. 25

p. 26

p. 35

p. 36

p. 37

p. 84

p. 85

Addition of Note 3 to 1.1 Features

Modification of 1.3 Ordering Information

Addition of Note 3 to 1.7 Outline of Functions (1/2)

Addition of Note 2 to 1.7 Outline of Functions (2/2)

Modification of Figure 3-1. Memory Map (µPD78F0101H)

Modification of Figure 3-2. Memory Map (µPD78F0102H)

Modification of Figure 3-3. Memory Map (µPD78F0103H)

Addition of Note to Figure 5-2. Format of Processor Clock Control Register (PCC)

Addition of Note 3 to Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution

Time

p. 99

Addition of Note to Table 5-5. Time Required to Switch Between Internal Oscillation Clock and High-

Speed System Clock

p. 182

p. 196

p. 322

Modification of Figure 10-2. Circuit Configuration of Series Resistor String

Modification of description to 10.6 (1) Operating current in standby mode

Modification of Note and addition of Caution 2 in Figure 19-3. Format of Low-Voltage Detection Level

Selection Register (LVIS)

p. 330

p. 346

p. 370

Revision of CHAPTER 20 OPTION BYTE

Modification of Table 21-7. Communication Modes

Addition of “Storage temperature (In flash memory blank state)” to Absolute Maximum Ratings in CHAPTER

23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

p. 384

p. 398

p. 404

Addition of CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Revision of CHAPTER 26 RECOMMENDED SOLDERING CONDITIONS

Addition of “When using the on-chip debug emulator QB-78K0MINI” to Figure A-1. Development Tool

Configuration

p. 408

p. 409

p. 410

Addition of Remark 2 to A.5.1 When using in-circuit emulator QB-78K0KX1H

Addition of A.5.2 When using on-chip debug emulator QB-78K0MINI

Modification of part number of SM+ for 78K0

435

User’s Manual U16846EJ3V0UD

APPENDIX E REVISION HISTORY

E.2 Revision History up to Previous Edition

The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of

each edition in which the revision was applied.

(1/2)

Edition

Description

Applied to:

2nd edition Modification of 1.5 Kx1 Series Lineup

CHAPTER 1 OUTLINE

Modification of recommended connection for unused RESET pin in Table 2-2 Pin I/O

CHAPTER 2 PIN

FUNCTIONS

Circuit Types

Addition of Cautions 1 and 2 to Figure 5-7 Format of Oscillation Stabilization Time

CHAPTER 5 CLOCK

GENERATOR

Select Register (OSTS)

Deletion of (7) System wait control register (VSWC) in 5.3 Registers Controlling

Clock Generator

Addition of description for when used as capture register to Interrupt request generation

CHAPTER 6 16-BIT

TIMER/EVENT

column in Figure 6-5 Format of 16-Bit Timer Mode Control Register 00 (TMC00)

COUNTER 00

Modification of Note 1 and correction of Cautions 4 and 5 in Figure 6-8 Format of

Prescaler Mode Register 00 (PRM00)

Modification of set value of TMC00 in Figure 6-32 Timing of One-Shot Pulse Output

Operation with Software Trigger

Modification of Note in Figure 7-4 Format of Timer Clock Selection Register 50

CHAPTER 7 8-BIT

TIMER/EVENT

COUNTER 50

(TCL50)

Modification of Note 1 in Figure 8-5 Format of 8-Bit Timer H Mode Register 0

CHAPTER 8 8-BIT

TIMERS H0 AND H1

(TMHMD0)

Modification of Note in Figure 8-6 Format of 8-Bit Timer H Mode Register 1

(TMHMD1)

Correction of Table 9-1 Loop Detection Time of Watchdog Timer

CHAPTER 9

WATCHDOG TIMER

Modification of Note 1 in Figure 11-4 Format of Baud Rate Generator Control

CHAPTER 11 SERIAL

INTERFACE UART0

(µ PD78F0102H AND

78F0103H ONLY)

Register 0 (BRGC0)

Modification of Note 1 in Figure 12-8 Format of Clock Selection Register 6 (CKSR6)

CHAPTER 12 SERIAL

INTERFACE UART6

Modification of (h) SBF transmission in 12.4.2 Asynchronous serial interface (UART)

mode

Modification of Note in Figure 13-3 Format of Serial Clock Selection Register 10

CHAPTER 13 SERIAL

INTERFACE CSI10

(CSIC10)

Modification of Caution 3 in Figure 14-2 Format of Interrupt Request Flag Register

CHAPTER 14

INTERRUPT

FUNCTIONS

(IF0L, IF0H, IF1L)

Addition of Cautions 1 and 2 in Figure 15-2 Format of Oscillation Stabilization Time

CHAPTER 15

Select Register (OSTS)

STANDBY FUNCTION

Modification of Figure 16-1 Block Diagram of Reset Function

CHAPTER 16 RESET

FUNCTION

Modification of Note in Figure 19-3 Format of Low-Voltage Detection Level Selection CHAPTER 19 LOW-

Register (LVIS)

VOLTAGE DETECTOR

Modification of Figure 21-10 FLMD1 Pin Connection Example

Addition of description to 21.5.7 Power supply

CHAPTER 21 FLASH

MEMORY

436

User’s Manual U16846EJ3V0UD

APPENDIX E REVISION HISTORY

(2/2)

Edition

Description

Applied to:

2nd edition Revision of CHAPTER 23 ELECTRICAL SPECIFICATIONS from target specifications to CHAPTER 23

official specifications

ELECTRICAL

SPECIFICATIONS

Addition of CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS

CHAPTER 25

RECOMMENDED

SOLDERING

CONDITIONS

Revision of APPENDIX A DEVELOPMENT TOOLS

APPENDIX A

DEVELOPMENT

TOOLS

Revision of APPENDIX B NOTES ON TARGET SYSTEM DESIGN

APPENDIX B NOTES

ON TARGET SYSTEM

DESIGN

Addition of APPENDIX D LIST OF CAUTIONS

Addition of APPENDIX E REVISION HISTORY

APPENDIX D LIST OF

CAUTIONS

APPENDIX E

REVISION HISTORY

437

User’s Manual U16846EJ3V0UD

For further information,

please contact:

NEC Electronics Corporation

1753, Shimonumabe, Nakahara-ku,

Kawasaki, Kanagawa 211-8668,

Japan

Tel: 044-435-5111

http://www.necel.com/

[Asia & Oceania]

[America]

[Europe]

NEC Electronics (China) Co., Ltd

7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian

District, Beijing 100083, P.R.China

TEL: 010-8235-1155

NEC Electronics America, Inc.

2880 Scott Blvd.

Santa Clara, CA 95050-2554, U.S.A.

Tel: 408-588-6000

NEC Electronics (Europe) GmbH

Arcadiastrasse 10

40472 Düsseldorf, Germany

Tel: 0211-65030

http://www.cn.necel.com/

800-366-9782

http://www.eu.necel.com/

http://www.am.necel.com/

NEC Electronics Shanghai Ltd.

Room 2509-2510, Bank of China Tower,

200 Yincheng Road Central,

Hanover Office

Podbielski Strasse 166 B

30177 Hanover

Pudong New Area, Shanghai P.R. China P.C:200120

Tel: 021-5888-5400

Tel: 0 511 33 40 2-0

http://www.cn.necel.com/

Munich Office

Werner-Eckert-Strasse 9

81829 München

Tel: 0 89 92 10 03-0

NEC Electronics Hong Kong Ltd.

12/F., Cityplaza 4,

12 Taikoo Wan Road, Hong Kong

Tel: 2886-9318

http://www.hk.necel.com/

Stuttgart Office

Industriestrasse 3

70565 Stuttgart

Seoul Branch

Tel: 0 711 99 01 0-0

11F., Samik Lavied’or Bldg., 720-2,

Yeoksam-Dong, Kangnam-Ku,

Seoul, 135-080, Korea

Tel: 02-558-3737

United Kingdom Branch

Cygnus House, Sunrise Parkway

Linford Wood, Milton Keynes

MK14 6NP, U.K.

NEC Electronics Taiwan Ltd.

7F, No. 363 Fu Shing North Road

Taipei, Taiwan, R. O. C.

Tel: 02-2719-2377

Tel: 01908-691-133

Succursale Française

9, rue Paul Dautier, B.P. 52180

78142 Velizy-Villacoublay Cédex

France

NEC Electronics Singapore Pte. Ltd.

238A Thomson Road,

#12-08 Novena Square,

Singapore 307684

Tel: 6253-8311

http://www.sg.necel.com/

Tel: 01-3067-5800

Sucursal en España

Juan Esplandiu, 15

28007 Madrid, Spain

Tel: 091-504-2787

Tyskland Filial

Täby Centrum

Entrance S (7th floor)

18322 Täby, Sweden

Tel: 08 638 72 00

Filiale Italiana

Via Fabio Filzi, 25/A

20124 Milano, Italy

Tel: 02-667541

Branch The Netherlands

Limburglaan 5

5616 HR Eindhoven

The Netherlands

Tel: 040 265 40 10

G05.12A


型号：	UPD78F0103HMC(A1)-5A4-A
厂家：	NEC
描述：	Microcontroller, 8-Bit, FLASH, 16MHz, CMOS, PDSO30, 0.300 INCH, PLASTIC, SSOP-30 微控制器光电二极管
文件：	总438页 (文件大小：2819K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78F0103HMC(A1)-5A4-A [NEC]

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