UPD78P014 [NEC]
8-BIT SINGLE-CHIP MICROCOMPUTER; 8位单片机
| 型号： | UPD78P014 |
| 厂家： | 
NEC |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总62页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P014
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78P014 is a member of the µPD78014 subseries of 78K/0 series products. It uses a one-time-programmable
(OTP) ROM or EPROM instead of the mask ROM of the µPD78014.
Because the µPD78P014 can be programmed by users, it is ideally suited for applications involving the evaluation
ofsystemsindevelopmentstages,small-scaleproductionofmanydifferentproducts,andrapiddevelopmentandtime-
to-market of a new product.
Detailed information about product features and specifications can be found in the following document. Please
make sure to read this document before starting design.
µPD78014, 78014Y Series User’s Manual : IEU-1343
FEATURES
• Pin compatible with mask ROM versions (except VPP pin)
• Internal PROM: 32K bytesNote
• µPD78P014DW
: Reprogrammable (ideal for system evaluation)
• µPD78P014CW, 78P014GC-AB8 : Programmable once only (ideal for small-scale production)
• Internal high-speed RAM: 1024 bytesNote
• Buffer RAM: 32 bytes
• Operable over same supply voltage range as mask ROM version (2.7 to 6.0 V)
• Available for the QTOPTM microcomputer
Note The internal PROM and internal high-speed RAM size can be set by means of the memory size switching
register.
Remark The QTOP microcomputer is the general term for a single-chip microcomputer with on-chip one-time
PROM. NEC supports its program writing, marking, screening, and verification.
Differences from mask ROM versions are as follows:
• The same memory mapping as on a mask ROM version is possible by setting the memory size
switching register.
• There is no function for incorporating pull-up resistors by means of a mask option in P60 to P63
pins.
ORDERING INFORMATION
Part No.
Package
Internal ROM
One-time PROM
EPROM
µPD78P014CW
µPD78P014DW
µPD78P014GC-AB8
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window) (750 mil)
64-pin plastic QFP (14 × 14 mm)
One-time PROM
In this document, the common parts of the one-time PROM version and EPROM version are represented by PROM.
The information in this document is subject to change without notice.
Document No. IC-3098C
The mark ★ shows revised points.
(O. D. No. IC-8111C)
Date Published January 1995 P
Printed in Japan
1992
©
µPD78P014
★
78K/0 SERIES DEVELOPMENT
µ PD78078Y Subseries
µ PD78078 Subseries
µ PD78064Y Subseries
µ PD78064 Subseries
100-pin package
8-bit timer/event counter
added
100-pin package
LCD controller/driver,
UART added
16-bit timer/event counter
function enhanced
External expansion function
enhanced
Products in Volume Production
Products under Development
µ PD78098 Subseries
Y subseries are products compatible with I2C bus.
µ PD78054Y Subseries
µ PD78054 Subseries
80-pin package
IEBus™ controller added
80-pin package
UART, D/A converter,
real-time output port added
16-bit timer/event counter
function enhanced
µ PD78083 Subseries
42/44-pin package
UART, A/D converter,
8-bit timer/event counter
function
µ PD78014Y Subseries
µ PD78014 Subseries
µ
PD78018FY Subseries
64-pin package
A/D converter,
µ PD78018F Subseries
16-bit timer/event counter,
SIO with automatic transmission/
reception function added
Multiply/divide instructions
added
64-pin package
Capable of low voltage and
high-speed operation
µ
PD780208 Subseries
100-pin package
FIP controller/driver function
enhanced
µ
PD78044A Subseries
µ PD78044 Subseries
µ PD78024 Subseries
80-pin package
Automatic transmission/reception
function added
6-bit up/down counter added
FIP controller/driver function
enhanced
64-pin package
A/D converter,
µ PD78002Y Subseries
16-bit timer/event counter,
µ PD78002 Subseries
FIPTM controller/driver,
multiply/divide instructions
64-pin package
added
2
µPD78P014
OUTLINE OF FUNCTION
Item
Function
• PROM
• RAM
: 32K bytesNote
Internal memory
Internal high-speed RAM : 1024 bytesNote
Buffer RAM
: 32 bytes
Memory space
General registers
Instruction cycle
64K bytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip instruction execution time cycle modification function
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)
Main system clock
selected
Subsystem clock
selected
122 µs (at 32.768 kHz operation)
Instruction set
• 16-bit operation
• Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, Boolean operation)
• BCD correction, etc.
I/O ports
Total
:
:
:
53
2
• CMOS input
• CMOS I/O
47
4
• N-channel open-drain I/O (15 V withstand voltage) :
A/D converter
Serial interface
Timer
• 8-bit resolution × 8 channels
• Operable over a wide power supply voltage range: VDD = 2.7 to 6.0 V
• 3-wire/SBI/2-wire mode selectable
: 1 channel
• 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Clock timer
: 1 channel
: 1 channel
• Watchdog timer
Timer output
Clock output
3 (14-bit PWM output : 1)
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation)
32.768 kHz (at subsystem clock 32.768 kHz operation)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation)
Internal : 8, External : 4
Vectored
interrupts
Maskable
interrupts
Internal : 1
Internal : 1
Non-maskable
interrupt
Software
interrupt
Test input
Internal : 1
External : 1
Operating voltage range
VDD = 2.7 to 6.0 V
Operating temperature
range
–40 to +85 °C
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 14 mm)
• 64-pin ceramic shrink DIP (with window) (750 mil)
Note The capacity of the internal PROM and internal high-speed RAM can be set by means of the memory size
switching register.
3
µPD78P014
PIN CONFIGURATION (Top View)
(1) Normal operating mode
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window) (750 mil)
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
P31/TO1
P32/TO2
P33/TI1
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVREF
2
AVDD
3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVSS
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P04/XT1
XT2
P34/TI2
µ
µ
P35/PCL
P36/BUZ
P37
V
PP
X1
X2
V
SS
V
DD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P62
P61
P60
P57/A15
P56/A14
V
SS
Cautions 1. VPP pin should be connected to VSS directly.
2. AVDD pin should be connected to VDD.
3. AVSS pin should be connected to VSS.
4
µPD78P014
64-pin plastic QFP (14 × 14 mm)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
1
P11/ANI1
P10/ANI0
AVSS
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
P04/XT1
XT2
5
µ
6
V
PP
7
X1
X2
8
V
SS
9
V
DD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
10
11
12
13
14
15
16
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Cautions 1. VPP pin should be connected to VSS directly.
2. AVDD pin should be connected to VDD.
3. AVSS pin should be connected to VSS.
5
µPD78P014
P00 to P04
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
: Port 0
: Port 1
: Port 2
: Port 3
: Port 4
: Port 5
: Port 6
AD0 to AD7
A8 to A15
RD
: Address/Data Bus
: Address Bus
: Read Strobe
: Write Strobe
: Wait
WR
WAIT
ASTB
: Address Strobe
X1, X2
XT1, XT2
RESET
ANI0 to ANI7
AVDD
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Reset
INTP0 to INTP3 : Interrupt From Peripherals
TI0 to TI2
TO0 to TO2
SB0, SB1
SI0, SI1
SO0, SO1
SCK0, SCK1
PCL
: Timer Input
: Timer Output
: Serial Bus
: Analog Input
: Analog Power Supply
: Analog Ground
: Serial Input
: Serial Output
: Serial Clock
: Programmable Clock
: Buzzer Clock
: Strobe
AVSS
AVREF
: Analog Reference Voltage
: Power Supply
VDD
VPP
: Programming Power Supply
: Ground
BUZ
VSS
STB
BUSY
: Busy
6
µPD78P014
(2) PROM programming mode
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window) (750 mil)
1
2
3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
V
SS
DD
4
(L)
5
6
7
8
(L)
D0
D1
D2
D3
D4
D5
D6
D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
SS
(L)
Open
µ
µ
V
PP
(L)
Open
V
SS
V
DD
A0
A1
(L)
A2
A3
A9
A4
RESET
A5
(L)
A6
A7
CE
OE
A8
(L)
A10
A11
A12
A13
(L)
V
SS
A14
Cautions 1. (L)
2. VSS
: Connect to VSS individually via a pull-down resistor.
: Connect to ground.
3. RESET : Set to low level.
4. Open : Do not make any connection.
7
µPD78P014
64-pin plastic QFP (14 × 14 mm)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
D0
D1
D2
D3
D4
D5
D6
D7
1
(L)
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
V
SS
(L)
4
5
Open
6
V
PP
µ
(L)
7
Open
8
V
SS
A0
A1
A2
A3
A4
A5
A6
9
V
DD
10
11
12
13
14
15
16
(L)
A9
RESET
(L)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Cautions 1. (L)
2. VSS
: Connect to VSS individually with a pull-down resistor.
: Connect to ground.
3. RESET : Set to low level.
4. Open : Do not make any connection.
A0 to A14
: Address Bus
: Data Bus
RESET
VDD
: Reset
: Power Supply
D0 to D7
CE
: Chip Enable
: Output Enable
VPP
: Programming Power Supply
: Ground
OE
VSS
8
µPD78P014
BLOCK DIAGRAM
9
µPD78P014
CONTENTS
1. DIFFERENCES BETWEEN µPD78P014 AND MASK ROM VERSION ...................................................11
2. PIN FUNCTIONS ....................................................................................................................................... 12
2.1 Normal Operating Mode Pins ......................................................................................................................... 12
2.2 PROM Programming Mode Pins ..................................................................................................................... 15
2.3 Pin Input/Output Circuits and Connection of Unused Pins........................................................................ 16
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ...................................................................18
4. PROM PROGRAMMING ........................................................................................................................... 19
4.1 Operating Modes ..............................................................................................................................................19
4.2 PROM Write Procedure .................................................................................................................................... 20
4.3 PROM Read Procedure ..................................................................................................................................... 22
5. ERASURE PROCEDURE (µPD78P014DW ONLY) ................................................................................... 23
6. OPAQUE FILM FOR ERASURE WINDOW (µPD78P014DW ONLY) ......................................................23
7. ONE-TIME PROM VERSION SCREENING .............................................................................................. 23
8. ELECTRICAL SPECIFICATIONS ............................................................................................................... 24
9. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................................ 49
10. PACKAGE DRAWINGS ............................................................................................................................. 53
11. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 56
APPENDIX A. DEVELOPMENT TOOLS.........................................................................................................57
APPENDIX B. RELATED DOCUMENTS ........................................................................................................59
10
µPD78P014
1. DIFFERENCES BETWEEN µPD78P014 AND MASK ROM VERSION
The µPD78P014 incorporates one-time PROM which can be written to once only, or EPROM to which programs
can be written, erased and rewritten.
By setting the internal memory size switching register, it is possible to make the functions of this device, except
for the PROM specification and mask option for pins P60 to P63, identical to those of a mask ROM version.
The differences between µPD78P014 and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences Between µPD78P014 and Mask ROM Version
Item
µPD78P014
Mask ROM Version
IC pin
VPP pin
Yes
No
No
Yes
Mask option for pins P60 to P63
Pull-up resistor incorporation possible by
means of mask option
No mask option for incorporation of pull-
up resistor
Caution In the µPD78P014, the capacity of the internal PROM and internal high-speed RAM can be changed by using
the internal memory size switching register.
RESET input sets internal PROM to 32K bytes and internal high-speed RAM to 1K bytes.
11
µPD78P014
2. PIN FUNCTIONS
2.1 Normal Operating Mode Pins
(1) Port pins (1/2)
Alternate
After Reset
Pin Name
I/O
Function
Input only
Function
INTP0/TI0
INTP1
Input
Port 0
Input
Input
P00
P01
5-bit I/O port
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can
be used by software.
Input/
output
P02
INTP2
P03
INTP3
P04Note 1
P10 to P17
XT1
Input only
Input
Input
Input
Port 1
Input/
ANI0 to
ANI7
8-bit input/output port.
output
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by
software.Note 2
P20
P21
SI1
SO1
Input/
Port 2
Input
output
8-bit input/output port.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
P22
SCK1
STB
P23
P24
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
P25
P26
P27
Input
P30
Port 3
Input/
output
8-bit input/output port.
P31
TO1
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
–
P40 to P47
Port 4
AD0 to AD7
Input/
Input
output
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, pull-up resistor can be used by software.
(Test input flag (KRIF) is set to 1 by falling edge detection.)
Notes 1. When P04/XT1 pins are used as the input ports, set processor clock control register bit 6 (FRC) to 1. (Do
not use the on-chip feedback resistor of the subsystem clock oscillation circuit.)
2. When P10/ANI0 to P17/ANI7 pins are used as the analog inputs for A/D converter, the pull-up resistor is
automatically disabled.
12
µPD78P014
(1) Port pins (2/2)
Alternate
After Reset
Pin Name
I/O
Function
Function
Input/
P50 to P57
Port 5
A8 to A15
Input
output
8-bit input/output port.
LED can be driven directly.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
Port 6
Input
—
P60
P61
Input/
N-ch open-drain input/
output port.
8-bit input/output port. Input/output can
be specified in 1-bit unit.
output
LED can be driven
directly.
P62
P63
P64
P65
P66
P67
When used as an input
port, pull-up resistor can
be used by software.
RD
WR
WAIT
ASTB
13
µPD78P014
(2) Non port pins (1/2)
Altrnate
After Reset
Pin Name
I/O
Function
Function
P00/TI0
P01
INTP0
INTP1
INTP2
INTP3
SI0
Input
Input
External interrupt input with specifiable valid edge (rising edge, falling
edge, or both rising and falling edges).
P02
P03
Falling edge detection external interrupt input.
Serial interface serial data input.
P25/SB0
P20
Input
Input
Input
Input
SI1
Output
Serial interface serial data output.
P26/SB1
P21
SO0
SO1
SB0
P25/SI0
P26/SO0
P27
Input/
Serial interface serial data input/output.
output
SB1
SCK0
SCK1
STB
BUSY
TI0
Input/
Serial interface serial clock input/output.
Input
Input
output
P22
P23
Output
Input
Serial interface automatic transmission/reception strobe output.
P24
Serial interface automatic transmission/reception busy input.
Input of external count clock to 16-bit timer (TM0).
Input
Input
Input
P00/INTP0
P33
Input of external count clock to 8-bit timer (TM1).
Input of external count clock to 8-bit timer (TM2).
16-bit timer (TM0) output (alternate function with 14-bit PWM output).
8-bit timer (TM1) output.
TI1
P34
TI2
P30
TO0
TO1
TO2
PCL
Input
Output
P31
P32
8-bit timer (TM2) output.
Input
Input
Input
Clock output (for trimming main system clock or subsystem clock).
Buzzer output.
P35
Output
Output
P36
BUZ
Low address/data bus when memory is expanded externally.
P40 to P47
AD0 to AD7 Input/
output
High address bus when memory is expanded externally.
External memory read operation strobe signal output.
External memory write operation strobe signal output.
Wait insertion at external memory access.
P50 to P57
P64
A8 to A15
RD
Input
Input
Output
Output
WR
P65
Input
Input
WAIT
ASTB
Input
P66
Output
Output of strobe which externally latches address information to be
output to ports 4 and 5 when accessing external memory.
P67
14
µPD78P014
(2) Non port pins (2/2)
Alternate
After Reset
Pin Name
I/O
Function
Function
Input
—
ANI0 to ANI7
AVREF
AVDD
AVSS
RESET
X1
Input
Input
—
P10 to P17
A/D converter analog input.
—
—
A/D converter reference voltage input.
A/D converter analog power supply. Connect to VDD.
A/D converter ground potential. Connect to VSS.
System reset input.
—
—
—
—
—
Input
Input
—
—
—
—
Main system clock oscillation crystal connection.
—
X2
—
Input
—
Input
—
P04
—
XT1
Subsystem clock oscillation crystal connection.
Positive power supply.
XT2
—
VDD
—
—
(High voltage application for program write/verify. Directly connected
to VSS in normal operating mode.)
—
—
—
—
—
—
VPP
VSS
Ground potential
2.2 PROM Programming Mode Pins
I/O
Pin Name
RESET
Function
Input
PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal to the RESET pin, the PROM
programming mode is set.
Input
Input
Input/
output
Input
Input
—
VPP
PROM programming mode setting and high voltage application for program write/verify.
A0 to A14
D0 to D7
Address bus.
Data bus.
CE
OE
PROM enable input/program pulse input.
PROM read strobe input.
Positive power supply.
VDD
VSS
—
Ground potential.
15
µPD78P014
2.3 Pin Input/Output Circuits and Connection of Unused Pins
The input/output circuit type of each pin and the recommended connection of unused pins are shown in Table
2-1.
The configuration of each type of input/output circuit is shown in Figure 2-1.
Table 2-1. Type of Pin Input/Output Circuits
Input/Output
Pin Name
I/O
Input
Recommended Connection for Used Pins
Connect to VSS .
Circuit Type
P00/INTP0/TI0
P01/INTP1
2
Input/output
8-A
Input
: Connect to VSS .
: Leave open.
P02/INTP2
Output
P03/INTP3
Input
16
11
Connected to VSS .
P04/XT1
P10/ANI0 to P17/ANI7
Input
: Connect to VDD or VSS .
Input/output
Output
: Leave open.
P20/SI1
8-A
5-A
8-A
5-A
8-A
10-A
Input
: Connect to VDD or VSS .
: Leave open.
Input/output
Output
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
5-A
Input/output
Input
: Connect to VDD or VSS .
: Leave open.
Output
P31/TO1
P32/TO2
8-A
5-A
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
Input/output
Input/output
Input
: Connect to VDD or VSS .
: Leave open.
Output
P50/A8 to P57/A15
P60 to P63
P64/RD
P65/WR
P66/WAIT
P67/ASTB
RESET
5-A
13
Input
: Connect to VDD or VSS .
: Leave open.
Output
5-A
2
Input
—
—
16
XT2
Leave open.
AVREF
Connect to VSS .
—
AVDD
Connect to VDD.
Connect to VSS .
AVSS
Directly connect to VSS.
VPP
16
µPD78P014
Figure 2-1. Pin Input/Output Circuits
VDD
Type 2
Type 10-A
pullup
enable
P-ch
IN
VDD
data
P-ch
IN/OUT
open-drain
output disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
VDD
VDD
Type 11
pullup
Type 5-A
P-ch
pullup
enable
enable
P-ch
VDD
data
P-ch
VDD
IN/OUT
data
P-ch
N-ch
output
disable
P-ch
N-ch
IN/OUT
Comparator
output
disable
+
–
N-ch
REF (Threshold Voltage)
V
input
enable
input
enable
VDD
Type 5-E
Type 13
pullup
enable
P-ch
IN/OUT
data
output disable
VDD
P-ch
N-ch
data
IN/OUT
output
disable
N-ch
Middle-High Voltage Input Buffer
Type 16
Type 8-A
VDD
pullup
enable
feedback
cut-off
P-ch
VDD
P-ch
P-ch
data
IN/OUT
output
disable
N-ch
XT2
XT1
17
µPD78P014
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is used to prevent part of the internal memory from being used by software. Setting the internal
memory size switching register (IMS) enables memory mapping identical to that of a mask ROM version with
different internal memory (ROM and RAM) to be used.
The IMS register is set by an 8-bit memory manipulation instruction.
RESET input sets this register to C8H.
Figure 3-1. Internal Memory Size Switching Register Format
7
6
5
4
0
3
2
1
0
Address
FFF0H
At Reset R/W
C8H
IMS
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
W
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
4 K bytes
8 K bytes
16 K bytes
24 K bytes
32K bytes
Setting prohibited
Other than above
RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selec-
tion
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
768 bytes
640 bytes
512 bytes
384 bytes
256 bytes
Setting prohibited
1024 bytes
896 bytes
The IMS set values to make the memory map identical to various mask ROM versions are shown in Table 3-1.
Table 3-1. Examples of Internal Memory Size Switching Register Settings
Target Mask ROM Version
IMS Set Value
IMS Set Value
Target Mask ROM Version
µPD78001B
µPD78002B
µPD78011B
44H
C6H
C8H
82H
64H
42H
µPD78012B
µPD78013
µPD78014
18
µPD78P014
4. PROM PROGRAMMING
The µPD78P014 incorporates a 32K-byte PROM as program memory. When programming the µPD78P014, the
PROM programming mode is set by means of the VPP and RESET pins. For the connection of unused pins, see “PIN
CONFIGURATION (2) PROM programming mode”.
4.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the µPD78P014
enters the programming mode. This is one of the operating modes shown in Table 4-1 below according to the setting
of the CE and OE pins.
Also, the PROM contents can be read by setting the read mode.
Table 4-1. PROM Programming Operating Modes
Pins
VDD
CE
OE
D0 to D7
RESET
VPP
Operating Mode
Program write
Program verify
Program inhibit
Read
Data input
L
H
H
L
H
L
+12.5 V
Data output
+6 V
High-impedance
Data output
H
L
L
Output disable
Standby
High-impedance
High-impedance
L
H
+5 V
+5 V
H
L/H
19
µPD78P014
4.2 PROM Write Procedure
The PROM write procedure is as shown below, allowing high-speed writing.
(1) Fix the RESET pin low. Supply +5 V to the VPP pin. Unused pins are handled as shown in “PIN CONFIGURATION
(2) PROM programming mode”.
(2) Supply +6 V to the VDD pin and +12.5 V to the VPP pin.
(3) Supply the initial address.
(4) Supply the write data.
(5) Supply a 1 ms program pulse (active low) to the CE pin.
(6) Verify mode. If written, go to (8); if not written, repeat (4) through (6). When the write operation has been
repeated 25 times, go to (7).
(7) Halt write operation due to defective device.
(8) Supply write data and supply (times repeated in (4) through (6)) × 3 ms program pulse (additional write).
(9) Increment the address.
(10) Repeat (4) through (9) until the final address.
Timing for steps (2) through (8) above is shown in Figure 4-1.
Figure 4-1. PROM Write/Verify Timing
Repeated X Times
Additional
Write
Verify
Write
A0-A14
D0-D7
Address Input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data
Data Input
Data Input
Output
+12.5 V
VPP
VDD
+6 V
VDD
3Xms
VDD
CE(Input)
OE(Input)
20
µPD78P014
Figure 4-2. Write Procedure Flowchart
(1)
Start write
Supply power supply voltage
Supply initial address
(2)
(3)
Supply write data
(4)
(5)
Supply program pulse
(6)
Write Not Possible
(Less than 25 Times)
Write Not Possible
(25th Times)
Verify mode
Write OK
X: Number of Write
Repetitions
Additional write (3X ms pulse)
(8)
(9)
Address increment
(10)
≤ Final Address
Final address
(7)
>Final Address
Write completed
Defective device
21
µPD78P014
4.3 PROM Read Procedure
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.
(1) Fix the RESET pin low. Supply +5 V to the VPP pin. Unused pins are handled as shown in “PIN CONFIGURATION
(2) PROM programming mode”.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of data to be read to pins A0 through A14.
(4) Read mode .
(5) Output data to pins D0 through D7.
Timing for steps (2) through (5) above is shown in Figure 4-3.
Figure 4-3. PROM Read Timing
A0-A14
CE (Input)
OE (Input)
D0-D7
Address Input
Hi-Z
Hi-Z
Data Output
22
µPD78P014
5. ERASURE PROCEDURE (µPD78P014DW ONLY)
With the µPD78P014DW, it is possible to erase (set to FFH) data written to the program memory, and rewrite the
memory.
The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or less.
Usually, exposure is performed with ultraviolet light with a wavelength of 254 nm. The amount of exposing required
for complete erasure is shown below.
•
•
UV intensity x erasure time: 15 W•s/cm2 or more
Erasure time: 15 to 20 minutes (using a 12,000 µW/cm2 ultraviolet lamp. A longer erasure time may be
required in case of deterioration of the ultraviolet lamp or dirt on the erasure window).
Erasure should be carried out with the ultraviolet lamp placed at a distance of 2.5 cm or less from the window.
If the ultraviolet lamp is fitted with a filter, this should be removed before performing exposure.
6. OPAQUE FILM FOR ERASURE WINDOW (µPD78P014DW ONLY)
An opaque film should be applied to the erasure window except when erasing the EPROM contents, in order to
prevent the EPROM contents from being unintentionally erased by light other than from the erasure lamp, and the
internal circuits other than EPROM from misoperation due to light.
7. ONE-TIME PROM VERSION SCREENING
One-time PROM versions (µPD78P014CW and µPD78P014GC-AB8) cannot be fully tested and shipped by NEC for
reasons related to their structure. It is recommended that after writing the necessary data and storing at high
temperature under the following conditions, screening should be conducted to verify the PROM.
Storage Temperature
Storage Time
24 hours
125 °C
NEC provides charged services for one-time PROM writing, marking, screening, and verification, under the name
“QTOP Microcomputer”. Contact NEC for details.
★
23
µPD78P014
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Supply voltage
Symbol
Ratings
Unit
V
Test Conditions
VDD
–0.3 to +7.0
–0.3 to +13.5
V
VPP
AVDD
AVREF
AVSS
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to + 0.3
V
V
V
Input voltage
P00 to P04, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, X1, X2, XT2
–0.3 to VDD + 0.3
V
VI1
–0.3 to +16
–0.3 to +13.5
V
V
P60 to P63
A9
Open-drain
VI2
VI3
PROM programming mode
Output voltage
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF + 0.3
–10
V
Analog input voltage
Output current high
VO
V
P10 to P17
1 pin
Analog input pins
VAN
mA
–15
–15
mA
mA
Total for P10 to P17, P20 to P27, P30 to P37
IOH
Total for P01 to P03, P40 to P47, P50 to P57,
P60 to P67
Output current low
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
Peak value
1 pin
15
R.m.s. value
100
Total for P40 to P47,
P50 to P55
Peak value
R.m.s. value
Peak value
R.m.s. value
Peak value
R.m.s. value
Peak value
R.m.s. value
70
100
Total for P01 to P03,
P56, P57, P60 to P67
Total for P01 to P03,
P64 to P67
Note
IOL
70
50
20
50
Total for P10 to P17,
P20 to P27, P30 to P37
20
Operating temperature
Storage temperature
Topt
Tstg
–40 to +85
–65 to +150
°C
Note The r.m.s. value should be calculated as follows: [R.m.s. value] = [Peak value] x √Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even
momentarily. In other words, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions which
ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
24
µPD78P014
Main System Clock Oscillator Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Parameter
Test Conditions
Resonator
Ceramic
MIN.
1
TYP.
MAX.
10
Unit
MHz
Circuit
VDD = Oscillation voltage
range
Oscillation frequency
(fX)Note 1
resonator
Vss X1
X2
R1
After VDD has reached
MIN. of oscillation
voltage range
Oscillation stabiliza-
tion timeNote 2
C2
C1
4
ms
Crystal
Oscillation frequency
(fX)Note 1
X2
C2
V
ss X1
1
8.38
10
MHz
ms
resonator
C1
VDD = 4.5 to 6.0 V
10
30
Oscillation stabiliza-
tion timeNote 2
X1 input frequency
(fX)Note 1
External clock
1.0
10.0
500
MHz
ns
X2
X1
X1 input high-/low-
level width (tXH/tXL)
µPD74HCU04
42.5
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. This is the time required for oscillation to stabilize after a reset or STOP mode release.
Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring in
the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
•
•
•
•
•
•
The wiring should be kept as short as possible.
No other signal lines should be crossed.
Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as VSS.
Do not connect to a ground pattern carrying a high current.
A signal should not be taken from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until
the oscillation stabilization time has been secured by the program before switching back to the main
system clock.
25
µPD78P014
Subsystem Clock Oscillator Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
Parameter
Test Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
Resonator
Crystal
Circuit
Oscillation frequency
(fXT)Note 1
Vss
XT1 XT2
32.768
1.2
resonator
R2
C4
C3
2
VDD = 4.5 to 6.0 V
Oscillation stabiliza-
tion timeNote 2
s
10
External clock
XT1 input frequency
(fXT)Note 1
32
5
100
15
kHz
XT2
XT1
XT1 input high-/low-
level width (tXTH/tXTL)
µs
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. Time required to stabilize oscillation after VDD reaches MIN. of oscillation voltage range.
Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring in the
area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
•
•
•
•
•
•
The wiring should be kept as short as possible.
No other signal lines should be crossed.
Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as VSS.
Do not connect to a ground pattern carrying a high current.
A signal should not be taken from the oscillator.
2. The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation
due to noise than the main system clock. When using the subsystem clock, special care is needed
regarding the wiring method.
26
µPD78P014
Recommended Oscillation Constants
Main System Clock: Ceramic Resonator (Ta = –40 to +85 °C)
Recommended Oscillator
Oscillation Voltage
Frequency
Constant
Range
C2 (pF)
100
Manufacturer
Murata Mfg.
Product Name
(MHz)
C1 (pF)
100
R1 (kΩ)
MIN. (V)
2.8
MAX. (V)
6.0
CSB1000J
6.8
4.7
0
1.00
1.01 to 1.25
1.26 to 1.79
CSB××××J
100
100
2.8
6.0
CSA×. ×××MK
CSA×. ××MG093
CST×. ××MG093
100
100
2.8
6.0
100
100
0
2.7
6.0
1.80 to 2.44
Incorporated Incorporated
0
2.7
6.0
30
30
0
2.7
6.0
CSA×. ××MG
CST×. ××MGW
CSA×. ××MGU
2.45 to 4.18
4.19 to 6.00
6.01 to 10.0
Incorporated Incorporated
0
2.7
6.0
30
30
0
2.7
6.0
Incorporated Incorporated
0
2.7
6.0
CST×. ××MGWU
CSA×. ××MT
30
30
0
3.0
6.0
Incorporated Incorporated
0
3.0
6.0
CST×. ××MTW
Remark ×. ××, ×. ××× and ×××× indicate frequency.
Subsystem Clock: Crystal Resonator (Ta = –40 to +60 °C)
Recommended Oscillator
Oscillation Voltage
Frequency
Manufacturer
Product Name
Constant
Range
(kHz)
C3 (pF)
C4 (pF)
R2 (kΩ)
MIN. (V)
2.7
MAX. (V)
6.0
Daishinku Corp.
DT-38 (1TA632E00,
10
10
100
32.768
load capacitance 6.3 pF)
Capacitance (Ta = 25 °C, VDD = VSS = 0 V)
MIN.
TYP.
MAX.
Unit
pF
Symbol
Test Conditions
Parameter
Input capacitance
CIN
f = 1 MHz Unmeasured pins returned to 0 V
P01 to P03, P10 to P17,
15
Input/output capacitance
P20 to P27, P30 to P37,
f = 1 MHz Unmeasured
15
pF
pF
CIO
P40 to P47, P50 to P57,
pins returned to 0 V
P64 to P67
P60 to P63
20
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
27
µPD78P014
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Test Conditions
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
V
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
Input voltage high
VIH1
0.7 VDD
VDD
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET 0.8 VDD
VDD
V
V
VIH2
VIH3
P60 to P63
X1, X2
Open-drain
0.7 VDD
15
VDD – 0.5
VDD – 0.5
VDD
VDD
V
V
VIH4
VIH5
VDD = 4.5 to 6.0 V
XT1/P04, XT2
VDD – 0.3
0
VDD
V
V
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
Input voltage low
0.3 VDD
VIL1
VIL2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0
0
0.2 VDD
0.3 VDD
V
V
VDD = 4.5 to 6.0 V
P60 to P63
VIL3
VIL4
VIL5
0
0
0.2 VDD
0.4
V
V
X1, X2
VDD = 4.5 to 6.0 V
XT1/P04, XT2
0
0
0.4
0.3
V
V
V
VDD = 4.5 to 6.0 V, IOH = –1 mA
Output voltage high
Output voltage low
VDD – 1.0
VOH1
VOL1
IOH = –100 µA
VDD – 0.5
V
V
VDD = 4.5 to 6.0 V,
P50 to P57, P60 to P63
0.4
2.0
0.4
IOL = 15 mA
P01 to P03, P10 to P17,
VDD = 4.5 to 6.0 V,
P20 to P27, P30 to P37,
IOL = 1.6 mA
V
P40 to P47, P64 to P67
VDD = 4.5 to 6.0 V,
VOL2
VOL3
0.2 VDD
0.5
V
V
SB0, SB1, SCK0
open-drain, pulled
high (R = 1 kΩ)
IOL = 400 µA
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, RESET
Input leakage current
high
ILIH1
3
µA
VIN = VDD
VIN = 15 V
VIN = 0 V
X1, X2, XT1/P04, XT2
ILIH2
ILIH3
20
80
µA
µA
P60 to P63
Input leakage current low
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, RESET
–3
µA
µA
ILIL1
–20
X1, X2, XT1/P04, XT2
ILIL2
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
28
µPD78P014
DC Characteristics (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
3
Unit
Output leakage current
high
VOUT = VDD
VOUT = 0 V
µA
ILOH1
Output leakage current
low
–3
µA
ILOL
Software pull-up resistor
Supply currentNote 3
VIN = 0 V, P01 to P03,
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
15
20
40
90
kΩ
kΩ
R2
500
8.38 MHz crystal oscilla- VDD = 5.0 V ± 10%Note 1
9
1
27
3
mA
mA
mA
µA
IDD1
tion operating mode
8.38 MHz crystal oscilla-
tion HALT mode
VDD = 3.0 V ± 10%Note 2
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
1.4
550
90
50
25
5
4.2
1650
180
100
50
IDD2
IDD3
IDD4
32.768 kHz crystal oscilla- VDD = 5.0 V ± 10%
tion operating mode VDD = 3.0 V ± 10%
32.768 kHz crystal oscilla- VDD = 5.0 V ± 10%
µA
µA
µA
tion HALT mode
XT1 = 0 V
VDD = 3.0 V ± 10%
10
µA
1
30
µA
VDD = 5.0 V ± 10%
STOP mode
Feedback resistor used
IDD5
IDD6
VDD = 3.0 V ± 10%
0.5
10
µA
XT1 = 0 V
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
0.1
30
10
µA
µA
STOP mode
Feedback resistor
not used
0.05
Notes 1. High-speed mode operation (when processor clock control register is set to 00H).
2. Low-speed mode operation (when processor clock control register is set to 04H).
3. Not including AVREF currents or port currents
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
29
µPD78P014
AC Characteristics
(1) Basic operation (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
Unit
Parameter
Cycle time
(Min. instruction
execution time)
Symbol
0.48
1.91
64
64
µs
µs
Operating with main
system clock
Ta = –40 to +40 °C
VDD = 4.75 to 6.0 V
Ta = –40 to +40 °C
TCY
0.4
64
µs
0.96
40
0
64
125
4
µs
µs
Operating with subsystem clock
VDD = 4.5 to 6.0 V
122
MHz
kHz
ns
TI input frequency
fTI
0
275
VDD = 4.5 to 6.0 V
100
1.8
TI input high-/low-level
width
tTIH
tTIL
µs
Note
Interrupt input high-/low-
level width
INTP0
8/fsam
µs
tINTH
tINTL
INTP1 to INTP3
KR0 to KR7
10
10
µs
µs
RESET low-level width
10
µs
tRSL
Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible
between fX/2N+1, fX/64, and fX/128 (N = 0 to 4).
TCY VS VDD (At main system clock operation)
60
10
µ
Operation Guaranteed
Range
(Ta = –40 to +85 °C)
2.0
1.0
0.5
0.4
0
1
2
3
4
5
6
Supply Voltage VDD [V]
Caution When Ta = –40 to +40 °C, the operation guaranteed range is extended to the dotted line.
30
µPD78P014
(2) Read/write operation (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
ASTB high-level width
Address setup time
Address hold time
Symbol
tASTH
tADS
Test Conditions
MIN.
0.5tCY
MAX.
Unit
ns
0.5tCY – 30
10
ns
tADH
Load resistance ≥ 5 kΩ
ns
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 50
(3 + 2n)tCY – 100
(1 + 2n)tCY – 25
(2.5 + 2n)tCY – 100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input time from address
5
Data input time from RD↓
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 20
(2.5 + 2n)tCY – 20
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
0.5tCY
1.5tCY
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
WAIT low-level width
0.5tCY
(0.5 + 2n)tCY + 10
100
(2 + 2n)tCY
Write data setup time
tWDS
Write data hold time
tWDH
5
WR low-level width
tWRL1
tASTRD
tASTWR
(2.5 + 2n)tCY – 20
0.5tCY – 30
1.5tCY – 30
RD↓ delay time from ASTB↓
WR↓ delay time from ASTB↓
ASTB↑ delay time from
RD↑ in external fetch
tRDAST
tCY – 10
tCY
tCY + 40
tCY + 50
ns
ns
Address hold time from
tRDADH
tRDWD
RD↑ in external fetch
Write data output time from RD↑
10
0.5tCY – 120
0.5tCY – 170
tCY
ns
ns
ns
ns
ns
ns
ns
VDD = 4.5 to 6.0 V
VDD =4.5 to 6.0 V
0.5tCY
0.5tCY
WR↓ delay time from write data
tWDWR
tCY + 60
Address hold time from WR↑
tWRADH
tCY
tCY + 100
2.5tCY + 80
2.5tCY + 80
RD↑ delay time from WAIT↑
WR↑ delay time from WAIT↑
tWTRD
tWTWR
0.5tCY
0.5tCY
Remarks 1.
tCY = TCY/4
2. n indicates number of waits.
3. CL = 100 pF (CL indicates the load capacitance of pins P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/
RD, P65/WR, P66/WAIT, P67/ASTB.)
31
µPD78P014
(3) Serial interface (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
(a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
Test Conditions
VDD = 4.5 to 6.0 V
Symbol
MIN.
800
TYP.
MAX.
Unit
ns
tKCY1
SCK cycle time
3200
ns
tKH1
tKL1
VDD = 4.5 to 6.0 V
tKCY1/2 – 50
tKCY1/2 – 150
100
ns
SCK high-/low-level
width
ns
tSIK1
tKSI1
ns
SI setup time (to SCK↑)
SI hold time (from SCK↑)
400
ns
VDD = 4.5 to 6.0 V
300
ns
SO output delay time
C = 100 pFNote
tKSO1
from SCK↓
1000
ns
Note C is the load capacitance of SO output line.
(b) 3-wire serial I/O mode (SCK...External clock input)
Parameter
Symbol
tKCY2
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle time
3200
400
ns
tKH2
tKL2
VDD = 4.5 to 6.0 V
ns
SCK high-/low-level
width
1600
100
ns
tSIK2
tKSI2
ns
SI setup time (to SCK↑)
SI hold time (from SCK↑)
400
ns
300
ns
VDD = 4.5 to 6.0 V
SO output delay time
C = 100 pFNote
tKSO2
from SCK↓
1000
ns
ns
When using the external device
expansion function
★
★
160
700
When using the
SCK rise and fall times
(For serial interface
channel 0)
tR2
tF2
When not
using the
16-bit timer
ns
ns
output function
external device
expansion
function
When not using
the 16-bit timer
output function
★
1000
When using the external device
expansion function
★
★
160
ns
ns
SCK rise and fall times
(For serial interface
channel 1)
tR2
tF2
When not using the external
device expansion function
1000
Note C is the load capacitance of SO output line.
32
µPD78P014
(c) SBI mode (SCK...Internal clock output)
MIN.
800
TYP.
MAX.
Unit
ns
Parameter
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
SCK cycle time
tKCY3
3200
ns
tKCY3/2 - 50
tKCY3/2 - 150
100
ns
tKH3
tKL3
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
SCK high-/low-level
width
ns
ns
SB0, SB1 setup time
tSIK3
(to SCK↑)
300
ns
SB0, SB1 hold time
tKSI3
tKCY3/2
ns
ns
(from SCK↑)
0
250
VDD = 4.5 to 6.0 V
SB0, SB1 output
R = 1 kΩ,
C = 100 pFNote
tKSO3
delay time from SCK↓
0
1000
ns
ns
ns
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
tKCY3
tKCY3
tKSB
tSBK
SB0, SB1 high-level
width
tKCY3
tKCY3
ns
ns
tSBH
tSBL
SB0, SB1 low-level
width
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
33
µPD78P014
(d) SBI mode (SCK...External clock input)
Symbol
MIN.
800
TYP.
MAX.
Unit
ns
Parameter
Test Conditions
VDD = 4.5 to 6.0 V
SCK cycle time
tKCY4
3200
400
ns
tKH4
tKL4
ns
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
SCK high-/low-level
width
1600
100
ns
ns
SB0, SB1 setup time
tSIK4
(to SCK↑)
300
ns
SB0, SB1 hold time
tKSI4
tKCY4/2
ns
ns
(from SCK↑)
0
300
VDD = 4.5 to 6.0 V
SB0, SB1 output
R = 1 kΩ,
C = 100 pFNote
tKSO4
delay time from SCK↓
0
1000
ns
ns
ns
SB0, SB1↓ from SCK↑
SCK↓ from SB0, SB1↓
tKCY4
tKCY4
tKSB
tSBK
SB0, SB1 high-level
width
tSBH
tSBL
tKCY4
tKCY4
ns
ns
SB0, SB1 low-level
width
When using the external device
expansion function
160
700
ns
ns
★
★
When using the
tR4
tF4
SCK rise and fall
times
When not
using the
16-bit timer
output function
external device
expansion
function
When not using
the 16-bit timer
output function
★
1000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
34
µPD78P014
(e) 2-wire serial I/O mode (SCK... Internal clock output)
Parameter
MIN.
1600
TYP.
MAX.
Unit
ns
Test Conditions
VDD = 4.5 to 6.0 V
Symbol
SCK cycle time
tKCY5
3800
ns
R = 1 kΩ, C = 100 pFNote
tKCY5/2 – 50
tKCY5/2 – 50
300
ns
SCK high-level width
tKH5
tKL5
ns
SCK low-level width
tSIK5
tKSI5
ns
SB0, SB1 setup time (to SCK↑)
SB0, SB1 hold time (from SCK↑)
600
ns
0
250
ns
VDD = 4.5 to 6.0 V
SB0, SB1 output delay time
R = 1 kΩ,
C = 100 pFNote
tKSO5
from SCK↓
0
1000
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(f) 2-wire serial I/O mode (SCK... External clock input)
Parameter
Test Conditions
MIN.
1600
3800
650
TYP.
MAX.
Unit
ns
Symbol
VDD = 4.5 to 6.0 V
SCK cycle time
tKCY6
ns
ns
SCK high-level width
tKH6
tKL6
800
ns
SCK low-level width
tSIK6
tKSI6
100
ns
SB0, SB1 setup time (to SCK↑)
SB0, SB1 hold time (from SCK↑)
tKCY6/2
0
ns
VDD = 4.5 to 6.0 V
300
ns
SB0, SB1 output delay time
R = 1 kΩ,
C = 100 pFNote
tKSO6
from SCK↓
0
1000
ns
ns
When using the external device
expansion function
★
★
160
700
When using the
ns
ns
When not
tR6
tF6
16-bit timer
SCK rise and fall times
using the
output function
external device
When not using
the 16-bit timer
output function
expansion
function
★
1000
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
35
µPD78P014
(g) 3-wire serial I/O mode with automatic transmit/receive function (SCK...Internal clock output)
Parameter
MIN.
800
TYP.
MAX.
Unit
ns
Symbol
Test Conditions
VDD = 4.5 to 6.0 V
tKCY7
SCK cycle time
3200
ns
VDD = 4.5 to 6.0 V
tKCY7/2 – 50
tKCY7/2 – 150
100
ns
tKH7
tKL7
SCK high/low-level
width
ns
ns
SI setup time (to SCK↑)
SI hold time (from SCK↑)
tSIK7
tKSI7
400
ns
300
ns
VDD = 4.5 to 6.0 V
SO output delay time
C = 100 pFNote
tKSO7
from SCK↓
1000
tKCY7
ns
ns
400
tSBD
STB↑ from SCK↑
Strobe signal high-
level width
tKCY7 – 30
tKCY7 + 30
ns
ns
tSBW
Busy signal setup time
(to busy signal
100
100
tBYS
detection timing)
Busy signal hold time
(from busy signal
detection timing)
tBYH
tSPS
ns
ns
SCK↓ from busy
2tKCY7
inactive
Note C is the load capacitance of the SO output line.
(h) 3-wire serial I/O mode with automatic transmit/receive function (SCK...External clock input)
Parameter
Symbol
tKCY8
Test Conditions
VDD = 4.5 to 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
SCK cycle time
3200
400
ns
tKH8
tKL8
VDD = 4.5 to 6.0 V
ns
SCK high/low-level
width
1600
100
ns
tSIK8
tKSI8
ns
SI setup time (to SCK↑)
SI hold time (from SCK↑)
400
ns
300
ns
VDD = 4.5 to 6.0 V
SO output delay time
C = 100 pFNote
tKSO8
from SCK↓
1000
ns
ns
When using the external device
expansion function
★
★
160
tR8
tF8
SCK rise and fall times
When not using the external
device expansion function
1000
ns
Note C is the load capacitance of the SO output line.
36
µPD78P014
A/D Converter Characteristics (Ta = –40 to +85 °C, AVDD = VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Resolution
Test Conditions
Symbol
MIN.
8
TYP.
8
MAX.
Unit
8
bit
%
Overall errorNote
Conversion time
Sampling time
0.6
tCONV
19.1
24/fx
AVSS
2.7
200
µs
µs
V
tSAMP
VIAN
Analog input voltage
Reference voltage
AVREF current
AVREF
AVDD
1.5
AVREF
IREF
V
0.5
mA
Note Excluding quantization error (±1/2LSB). Shown as a percentage of the full scale value.
37
µPD78P014
AC Timing Test Point (Excluding X1 and XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Point of
measurement
Clock Timing
1/f
X
t
XL
t
XH
V
DD - 0.5 V
X1 Input
0.4V
1/fXT
t
XTL
t
XTH
V
DD - 0.5 V
XT1 Input
0.4V
TI Timing
1/fTI
tTIL
tTIH
TI0-TI2
38
µPD78P014
Read/Write Operation
External fetch (no wait):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
t
ADD1
Hi-z
Operation
Code
AD0-AD7
t
RDADH
t
ADS
t
RDD1
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External fetch (wait insertion):
A8-A15
Upper 8-Bit Address
Lower 8-Bit
Address
t
ADD1
Hi-z
Operation
Code
AD0-AD7
t
RDD1
t
RDADH
t
ADS
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
WAIT
t
WTRD
t
WTL
t
RDWT1
39
µPD78P014
External data access (no wait):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
t
ADD2
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
t
ADS
t
RDD2
t
ADH
t
RDH
t
ASTH
ASTB
RD
t
RDWD
t
WDS
t
WDH
t
ASTRD
t
RDL2
t
WDWR
t
WRADH
WR
t
ASTWR
t
WRL1
External data access (wait insertion):
A8-A15
Upper 8-Bit Address
Lower
8-Bit
Address
t
ADD2
Hi-z
Hi-z
AD0-AD7
Read Data
Write Data
t
RDD2
t
ADS
t
ADH
t
RDH
t
ASTH
ASTB
RD
t
ASTRD
t
WDH
t
RDL2
t
WDS
t
RDWD
t
WDWR
WR
t
ASTWR
t
WRL1
t
WRADH
WAIT
t
RDWT2
t
WTRD
t
WTL
t
WRWT
t
WTL
t
WTWR
40
µPD78P014
Serial Transfer Timing
3-wire serial I/O mode:
t
KCY 1.2
t
KL1.2
t
KH1.2
t
R2
t
F2
★
SCK
t
SIK1.2
t
KSI1.2
SI
Input Data
t
KSO1.2
SO
Output Data
SBI mode (bus release signal transfer):
t
KCY3.4
t
KL3.4
R4
t
KH3.4
t
t
F4
★
SCK
t
KSB
t
SBL
t
SBK
t
SIK3.4
t
KSI3.4
t
SBH
SB0, SB1
t
KSO3.4
SBI mode (command signal transfer):
tKCY3.4
tKL3.4
tR4
tKH3.4
★
tF4
SCK
tSIK3.4
tKSI3.4
tKSB
tSBK
SB0, SB1
tKSO3.4
41
µPD78P014
2-wire serial I/O mode:
t
KCY5.6
t
KL5.6
R6
t
KH5.6
t
t
F6
★
SCK
t
SIK5.6
t
KSI5.6
t
KSO5.6
SB0, SB1
3-wire serial I/O mode with automatic transmit/receive function:
SO
SI
D2
D1
D0
D7
D2
D1
D0
D7
t
SIK7.8
t
KSI7.8
t
KH7.8
t
KSO7.8
t
F8
★
SCK
STB
t
SBD
t
SBW
t
KL7.8
t
R8
t
KCY7.8
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
7
8
9Note
10Note
10+nNote
1
SCK
t
BYS
t
BYH
t
SPS
BUSY
(Active high)
Note The signal is not actually low here, but is represented in this way to show the timing.
42
µPD78P014
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = –40 to +85 °C)
Symbol
VDDDR
MIN.
2.0
TYP.
MAX.
6.0
Unit
V
Parameter
Test Conditions
Data retention power
supply voltage
VDDDR = 2.0 V
Data retention power
supply current
IDDDR
tSREL
0.1
10
µA
µs
Subsystem clock stop and
feedback resistor disconnected
0
Release signal set time
218/fx
ms
ms
Release by RESET
Oscillation
tWAIT
stabilization wait time
Release by interrupt
Note
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection
of 213/fx and 215/fx to 218/fx is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
V
DD
VDDDR
t
SREL
Stop Instruction Execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
Stop Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
43
µPD78P014
Interrupt Input Timing
t
INTL
t
INTH
INTP0-INTP2
t
INTL
INTP3
RESET Input Timing
t
RSL
RESET
44
µPD78P014
DC Programming Characteristics (Ta = 25 ± 5 °C, VSS = 0 V)
Symbol SymbolNote
Test Conditions
MIN.
TYP.
MAX.
Unit
V
Parameter
Input voltage
high
0.7 VDDP
VDDP
VIH
VIH
Input voltage
low
0
0.3 VDDP
10
V
VIL
ILIP
VIL
ILI
Input leakage
current
0 ≤ VI ≤ VDDP
µA
IOH = –400 µA
IOH = –100 µA
2.4
V
V
VOH1
VOH2
VOH1
VOH2
Output
voltage high
VDD – 0.7
Output
IOL = 2.1 mA
0.45
10
V
VOL
ILO
VOL
voltage low
Output
leakage
current
0 ≤ VO ≤ VDDP, OE = VIH
µA
—
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
5.75
4.5
6.0
5.0
6.25
5.5
V
V
V
VDDP supply
voltage
VDDP
VPP
VCC
VPP
12.5
12.5
12.8
VPP supply
voltage
VPP = VDDP
5
30
30
mA
mA
VDDP supply
current
Program memory read mode
CE = VIL, VI = VIH
IDD
IPP
ICC
5
5
1
Program memory write mode
CE = VIL, OE = VIH
30
mA
VPP supply
current
IPP
Program memory read mode
100
µA
Note Corresponding µPD27C256A symbol.
45
µPD78P014
Program Operation
AC Characteristics (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
SymbolNote
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Symbol
2
2
2
2
µs
µs
µs
µs
Address setup time (to CE↓)
OE↓ delay time from data
tAS
tOES
tDS
tSAC
tDDOO
tSIDC
tHCA
Input data setup time (to CE↓)
Address hold time (from CE↑)
tAH
Input data hold time
2
0
µs
tDH
tDF
tHCID
(from CE↑)
Output data hold time
130
ns
tHOOD
(from OE↑)
VPP setup time (to CE↓)
VDDP setup time (to CE↓)
1
1
ms
ms
ms
tVPS
tVDS
tPW
tSVPC
tSVDC
tWL1
0.95
1.0
1.05
Initial program pulse width
Additional program pulse width
Data output time from OE↓
2.85
78.75
1
ms
tOPW
tOE
tWL2
µs
tDOOD
Note Corresponding µPD27C256A symbol.
Read Operation
AC Characteristics (Ta = 25 ± 5 °C, VDD = 5.0 ± 0.5 V, VPP = VDD, VSS = 0 V)
Symbol SymbolNote
Parameter
Test Conditions
MIN.
TYP.
MAX. Unit
200
200
75
ns
ns
ns
ns
ns
Data output time from address
tDAOD
tDCOD
tDOOD
tHCOD
tHAOD
tACC
tCE
Data output time from CE
↓
Data output time from OE
↓
tOE
tDF
0
0
60
Data hold time (from OE↑)
Data hold time (from address)
tOH
Note Corresponding µPD27C256A symbol.
PROM Mode Setting
AC Characteristics (Ta = 25 ± 5 °C, VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
10
TYP.
MAX.
Unit
tSMA
µs
PROM mode setup time
46
µPD78P014
PROM Write Mode Timing
Valid Address
Data Output
A0-A14
t
SAC
t
HCA
D0-D7
Data Input
Data Input
t
t
SIDC
t
HCID
t
HOOD
t
SIDC
t
HCID
V
PP
V
PP
V
DDP
SVPC
V
DDP+1
V
DDP
V
DDP
t
SVDC
V
IH
IL
CE
V
t
WL1
t
DOOD
t
WL2
t
DDOO
V
IH
OE
V
IL
Cautions 1. VDDP should be applied before VPP, and cut after VPP.
2. VPP should not reach +13V or above including overshoot.
47
µPD78P014
PROM Read Mode Timing
Valid Address
A0-A14
CE
OE
t
DCOD
t
DOOD
t
HAOD
t
DAOO
t
HCOD
Hi-z
Hi-z
Data Output
D0-D7
PROM Mode Setting Timing
VDDP
VDD
0
RESET
VDDP
VPP
0
tSMA
A0-A14
Valid Address
48
µPD78P014
9. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs VDD (Main System Clock : 8.38 MHz)
(Ta = 25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
and HALT (X1 Oscillation,
XT1 Oscillation)
1.0
0.5
PCC=B0H
0.1
0.05
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Stop, XT1
Oscillation) and Reset
0.01
f
f
X
= 8.38 MHz
0.005
XT= 32.768 kHz
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
49
µPD78P014
IDD vs VDD (Main System Clock : 4.19 MHz)
(T
a
= 25°C)
10.0
5.0
PCC=00H
PCC=01H
PCC=02H
PCC=03H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
1.0
0.5
PCC=B0H
0.1
0.05
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Stop, XT1
Oscillation)
0.01
f
f
X
= 4.19 MHz
0.005
XT= 32.768 kHz
0.001
0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
50
µPD78P014
VOL vs IOL (Ports 0 , 2 to 5, P64 to P67)
(T
a
= 25 °C)
V
DD = 5 V
V
DD = 6 V
30
20
10
0
VDD = 4 V
VDD = 3 V
0
0.5
1.0
Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
(Ta = 25 °C)
VDD = 6 V
VDD = 5 V
30
20
10
0
VDD = 4 V
V
DD = 3 V
0
0.5
1.0
Output Voltage Low VOL [V]
51
µPD78P014
VOL vs IOL (P60 to P63)
(Ta = 25 °C)
VDD = 6 V VDD = 5 V
30
20
10
0
VDD = 4 V
VDD = 3 V
0
0.5
1.0
Output Voltage Low VOL [V]
VOH vs IOH (Ports 0 to 5, P64 to P67)
(Ta = 25 °C)
VDD = 6 VVDD = 5 V
–10
VDD = 4 V
VDD = 3 V
–5
0
0
0.5
1.0
Output Voltage High VDD – VOH [V]
52
µPD78P014
10. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
32
1
A
K
L
F
D
M
R
B
C
M
N
NOTE
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P64C-70-750A,C-1
53
µPD78P014
64 PIN CERAMIC SHRINK DIP (750 mil)
S
64
33
1
32
A
K
L
F
M
D
N
CB
0 to 15°
M
P64DW-70-750A
NOTES
ITEM
MILLIMETERS
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
0.46 +–0.05
INCHES
1) Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maxi-mum
material condition.
A
B
C
D
F
2.310 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed
parallel.
+0.002
0.018 –
0.8 MIN.
0.031 MIN.
+0.012
+0.3
0.138 –
–
G
H
I
3.5
1.0 MIN.
3.0
0.039 MIN.
0.118
J
5.08 MAX.
19.05 (T.P.)
18.8
0.200 MAX.
0.750 (T.P.)
0.740
K
L
+0.05
–
M
N
S
0.25
0.010+–00..000023
0.25
8.89
0.01
0.350
54
µPD78P014
64 PIN PLASTIC QFP ( 14)
A
B
48
49
33
32
detail of lead end
64
1
17
16
G
H
M
I
J
K
N
L
P64GC-80-AB8-3
INCHES
NOTE
ITEM
A
MILLIMETERS
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
±
±
17.6 0.4
0.693 0.016
+0.009
–0.008
±
B
14.0 0.2
0.551
+0.009
±
C
D
F
14.0 0.2
0.551
–0.008
±
±
0.693 0.016
17.6 0.4
1.0
1.0
0.039
G
H
I
0.039
+0.004
–0.005
±
0.35 0.10
0.014
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
±
±
K
1.8 0.2
0.071 0.008
+0.009
–0.008
±
0.031
L
0.8 0.2
+0.10
+0.004
–0.003
0.15
M
N
P
0.006
–0.05
0.10
2.55
0.004
0.100
±
Q
S
0.1 0.1
±
0.004 0.004
2.85 MAX.
0.112 MAX.
55
µPD78P014
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78P014 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device
Mounting Technology Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 11-1. Surface Mounted Type Soldering Conditions
µPD78P014GC-AB8: 64-pin plastic QFP (14 × 14 mm)
Symbol
Soldering Method
Infrared ray reflow
Soldering Conditions
Package peak temperature: 230 °C
Duration: 30 sec. max. (at 210 °C or above) Number of times: Once
Time limit: 2 daysNote (thereafter 20 hours prebaking required at 125 °C)
IR30-202-1
Package peak temperature: 215 °C
VPS
Duration: 40 sec. max. (at 200 °C or above) Number of times: Once
Time limit: 2 daysNote (thereafter 20 hours prebaking required at 125 °C)
VP15-202-1
Pin temperature: 300 °C max. Duration: 3 sec. max.
Pin partial heating
(Per side of the device)
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH.
Caution Use of more than one soldering method should be avoided (except in the case of pin partial heating).
Table 11-2. Insert Type Soldering Conditions
µPD78P014CW: 64-pin plastic shrink DIP (750 mil)
µPD78P014DW: 64-pin ceramic shrink DIP (with window) (750 mil)
Soldering Method
Soldering Conditions
Wave soldering
(Pin only)
Solder bath temperature : 260 °C max. Duration: 10 sec. max.
★
Pin partial heating
Pin temperature: 300 °C max. Duration: 3 sec. max (per 1 pin).
Caution The wave soldering applies to the pin only. Ensure that no solder touches the body directly.
56
µPD78P014
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78P014.
Language Processing Software
Note 1, 2, 3
RA78K/0
CC78K/0
DF78014
78K/0 series common assembler package
78K/0 series common C compiler package
µPD78014 subseries device file
Note 1, 2, 3
Note 1, 2, 3
Note 1, 2, 3
★
CC78K/0-L
78K/0 series common C compiler library source file
PROM Writing Tools
PG-1500
PROM programmer
PA-78P014CW
PA-78P014GC
Programmer adapter connected to PG-1500
PG-1500 control program
PG-1500 controller Note 1, 2
Debugging Tools
IE-78000-R
78K/0 series common in-circuit emulators
78K/0 series common break board
IE-78000-R-BK
IE-78014-R-EM
EP-78240CW-R
EP-78240GC-R
EV-9200GC-64
SD78K/0 Note 1, 2
SM78K/0 Note 3, 4, 5, 6
DF78014 Note 1, 2, 3, 4, 5
µPD78002/78014 subseries evaluation emulation boards
µPD78244 subseries common emulation probes
Socket to be mounted on a user system board made for 64-pin plastic QFP
IE-78000-R screen debugger
78K/0 series common system simulator
µPD78014 subseries device file
★
Real-Time OS
RX78K/0 Note 1, 2, 3
78K/0 series common real-time OS
78K/0 series common OS
MX78K/0 Note 1, 2, 3, 6
★
57
µPD78P014
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note 5
FT9080 Note 1/FT9085 Note 2
FI78K0 Note 1, 2
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fuzzy inference debugger
FD78K0 Note 1, 2
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/ATTM (PC DOSTM) based
3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM) based, EWS-4800
★
series (EWS-UX/V) based
4. PC-9800 series (MS-DOS+WindowsTM) based
5. IBM PC/AT (PC DOS + Windows) based
6. Under development
Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (IF-1185).
2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used together with the DF78014.
★
58
µPD78P014
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No. (Japanese) Document No. (English)
µPD78014/78014Y Series User’s Manual
IEU-780
IEU-849
IEU-1343
78K/0 Series User's Manual Instructions
IEU-1372
Basic I
IEA-715
IEA-740
IEA-744
IEA-1288
IEA-1299
IEA-1301
78K/0 Series Application Notes
Basic II
Electronic Notebook
Development Tool Related Documents (User’s Manual)
Document Name
Document No. (Japanese) Document No. (English)
Operation
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
EEU-651
EEU-704
EEU-810
EEU-867
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
EEU-1335
EEU-1291
EEU-1398
EEU-1427
RA78K Series Assembler Package
Language
RA78K Series Structured Assembler Preprocessor
Operation
CC78K Series C Compiler
Language
PG-1500 PROM Programmer
PG-1500 Controller
IE-78000-R
IE-78000-R-BK
Basic
EEU-852
EEU-816
EEU-1414
EEU-1413
SD78K/0 Screen Debugger
Reference
Other Related Documents
Document Name
Document No. (Japanese) Document No. (English)
Package Manual
IEI-635
IEI-616
IEI-620
MEI-603
IEI-1213
IEI-1207
IEI-1209
MEI-1202
Semiconductor Device Mounting Technology Manual
Quality Grades on Semiconductor Devices
Semiconductor Devices Quality Guarantee Guide
Caution The above related documents are subject to change without notice. For design purposes, etc., be
sure to use the latest documents.
59
µPD78P014
[MEMO]
60
µPD78P014
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
61
µPD78P014
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
FIP is a trademark of NEC Corporation.
IEBus and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
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