UPD8884A [NEC]
(10680 PIXELS x 4 LINES) x 3 COLOR CCD LINEAR IMAGE SENSOR; （ 10680像素× 4行）× 3彩色CCD线性图像传感器
| 型号： | UPD8884A |
| 厂家： | 
NEC |
| 描述： | (10680 PIXELS x 4 LINES) x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 文件： | 总28页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD8884A
(10680 PIXELS × 4 LINES) × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The μPD8884A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The μPD8884A has 3 rows of (10680 × 4) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
4800 dpi/A4 color image scanners.
FEATURES
• Valid photocell : (10680 pixels × 4) × 3
• Photocell’s size : 4 μm
• Line spacing
: Quad staggered pixels
96 μm (24 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 192 dot/mm A4 (210 × 297 mm) size (shorter side)
4800 dpi US letter (8.5” × 11”) size (shorter side)
• Color filter
• Resolution
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 5.0 MHz Max.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
μPD8884ACY-A
Remark The μPD8884ACY-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17546EJ1V0DS00 (1st edition)
Date Published May 2005 NS CP (K)
2005
Printed in Japan
μPD8884A
BLOCK DIAGRAM
φ
φ
φ
V
OD GND GND
SEL2
30
2-2 1-2
29 14 4
11 22
Drain gate
Transfer gate
CCD analog shift register
Transfer gate
Photocell
(Blue)
Transfer gate
V
(Blue)
OUT
1
31
32
1
φ
TG1
(Blue)
18
17
16
CCD analog shift register
Transfer gate
Drain gate
Drain gate
Transfer gate
CCD analog shift register
Transfer gate
Photocell
(Green)
Transfer gate
V
OUT2
(Green)
φ
TG2
(Green)
CCD analog shift register
Transfer gate
Drain gate
Drain gate
Transfer gate
CCD analog shift register
Transfer gate
Photocell
V
(Red)
OUT3
(Red)
φ
TG3
(Red)
Transfer gate
CCD analog shift register
Transfer gate
Drain gate
2
3
5
28
19
15
φ
φ
φ
φ
φ
φ
SEL3
CLB RB 2-1 1-1
SEL1
2
Data Sheet S17546EJ1V0DS
μPD8884A
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
• μPD8884ACY-A
Output signal 3 (Red)
V
OUT
3
1
2
3
4
5
6
7
8
9
32
31
30
29
28
V
V
φ
OUT
2
1
Output signal 2 (Green)
Output signal 1 (Blue)
Reset feed-through level
clamp clock
φ
OUT
CLB
RB
GND
Reset gate clock
Ground
φ
SEL2 Dpi selector 2
VOD
Output drain voltage
Shift register clock 2-1
Internal connection
Internal connection
No connection
φ
2-1
IC
φ
1-1
Shift register clock 1-1
Internal connection
Internal connection
No connection
27 IC
26 IC
25 NC
24 NC
23 NC
IC
NC
NC
No connection
No connection
No connection
NC 10
2-2 11
IC 12
IC 13
No connection
Shift register clock 2-2
Internal connection
Internal connection
Ground
φ
22
φ
1-2
Shift register clock 1-2
Internal connection
Internal connection
21 IC
20 IC
GND 14
19
18
17
φ
φ
φ
SEL1 Dpi selector 1
Transfer gate clock 1
(for Blue)
Dpi selector 3
φ
15
16
TG1
TG2
SEL3
Transfer gate clock 3
(for Red)
Transfer gate clock 2
(for Green)
φ
TG3
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
3
Data Sheet S17546EJ1V0DS
μPD8884A
PHOTOCELL STRUCTURE DIAGRAM (4800 dpi, for each color)
2
6
10
14
18
22
4
μ
m
1.0
μ
m
3.0
μ
m
CCD
33.5
μ
m
1
5
9
13
17
21
8
μ
m
3
7
11
15
19
23
33.5
μ
m
CCD
4
8
12
16
20
24
4
Data Sheet S17546EJ1V0DS
μPD8884A
PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
Drain gate
4
μ
Blue photocell array
CCD analog shift register
Blue photocell array
m
(33.5
μ
m)
m)
4
4
4
μ
μ
μ
m
m
m
2 lines
(8
μ
m)
Blue photocell array
24 lines
(96
μ
m)
(33.5
μ
CCD analog shift register
Resolution Select
4
μ
m
m
Blue photocell array
Drain gate
(21
μ
m)
Drain gate
Blue photocell array
4
μ
(33.5
μ
m)
CCD analog shift register
Blue photocell array
4
4
4
μ
μ
μ
m
m
m
2 lines
(8
271
μ
m
μ
m)
Blue photocell array
24 lines
(96
μ
m)
(33.5
μ
m)
CCD analog shift register
Resolution Select
4
μ
m
m
Blue photocell array
Drain gate
(21
μ
m)
Drain gate
Blue photocell array
4
μ
(33.5
μ
m)
CCD analog shift register
Blue photocell array
4
4
4
μ
μ
μ
m
m
m
2 lines
(8
μ
m)
Blue photocell array
(33.5
μ
m)
CCD analog shift register
Resolution Select
4
μ
m
Blue photocell array
Drain gate
PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Dummy, OB, for each color)
Dummy
Optical black
(192 pixels)
Invalid photocell
(16 pixels)
Valid photocell
(42720 pixels)
Invalid photocell
(8 pixels)
(160 pixels)
4800 dpi
2400 dpi
4800 dpi
2
158 162
350 354 358 362 366 370 374
43082 43086
1
157 161
349 353 357 361 365 369 373
351 355 359 363 367 371 375
43081 43085
43083 43087
3
159 163
4
160 164
352 356 360 364 368 372 376
43084 43088
5
Data Sheet S17546EJ1V0DS
μPD8884A
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
−0.3 to +8
0 to +60
Unit
V
VOD
Shift register clock voltage
Vφ 1, Vφ 2
Vφ RB
V
Reset gate clock voltage
V
Reset feed-through level clamp clock voltage
Dpi select signal voltage
Vφ CLB
V
Vφ SEL1 to Vφ SEL3
Vφ TG1 to Vφ TG3
TA
V
Transfer gate clock voltage
Operating ambient temperature Note
Storage temperature
V
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.5
4.75
−0.3
4.5
Typ.
12.0
5.0
0
Max.
12.5
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ RBH
V
+0.3
5.5
V
5.0
0
V
Vφ RBL
−0.3
4.5
+0.3
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Dpi select signal high level
Dpi select signal low level
Vφ CLBH
5.0
0
V
Vφ CLBL
−0.3
4.5
+0.3
5.5
V
Vφ SEL1H to Vφ SEL3H
Vφ SEL1L to Vφ SEL3L
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
5.0
0
V
−0.3
4.5
+0.3
5.5
V
Transfer gate clock high level
Transfer gate clock low level
Data rate
5.0
0
V
−0.3
−
+0.3
5.0
V
2.0
1.0
MHz
MHz
Clock pulse frequency
fφ 1, fφ 2
−
10.0
6
Data Sheet S17546EJ1V0DS
μPD8884A
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
Min.
2.3
−
Typ.
2.7
Max.
−
Unit
V
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
0.79
0.87
1.35
6
−
lx•s
lx•s
lx•s
%
Green
Blue
−
−
−
−
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
−
20
Light shielding
Light shielding
−
0.1
4.0
8.0
540
1.0
4.42
4.03
2.60
7.5
−
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
−
2.0
−
380
0.4
Output impedance
ZO
−
Response
Red
RR
2.38
2.17
1.40
4.5
92
3.40
3.10
2.00
6.0
V/lx•s
V/lx•s
V/lx•s
V
Green
Blue
RG
RB
Offset level Note
VOS
Total transfer efficiency
TTE
VOUT = 1.0 V
98
%
Clock pulse frequency = 10 MHz
Response peak
Image lag
Red
−
−
−
−
−
630
540
460
0.05
1.0
−
−
nm
nm
nm
%
Green
Blue
−
IL
VOUT = 1.0 V
VOUT = 1.0 V
3.0
6.0
Response difference between
inside and outside
RDIO
%
Potocell array imbalance
PAIIN
VOUT = 1.0 V
VOUT = 1.0 V
Light shielding
Light shielding
−
−
−
−
1.0
1.0
6.0
6.0
%
%
PAIOUT
RFTN
σCDS
Reset feed-through noise Note
Random noise (CDS)
−500
1.2
+1000
−
mV
mV
Note Refer to TIMING CHART 2-1 to 2-3.
7
Data Sheet S17546EJ1V0DS
μPD8884A
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Shift register clock pin capacitance 1
Shift register clock pin capacitance 2
Shift register clock pin capacitance 3
Shift register clock pin capacitance 4
Reset gate clock pin capacitance
Symbol
Pin name Pin No.
Min.
−
Typ.
750
750
750
750
20
Max.
−
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Cφ 1-1
φ 1-1
28
22
5
Cφ 1-2
Cφ 2-1
Cφ 2-2
Cφ RB
φ 1-2
−
−
φ 2-1
−
−
φ 2-2
11
3
−
−
φ RB
−
−
Reset feed-through level clamp clock pin capacitance Cφ CLB
φ CLB
φ SEL1
φ SEL2
φ SEL3
φ TG1
φ TG2
φ TG3
2
−
20
−
Select signal and gain pin capacitance
Cφ SEL1
Cφ SEL2
Cφ SEL3
Cφ TG
19
30
15
18
17
16
−
20
−
−
20
−
−
20
−
Transfer gate clock pin capacitance
−
20
−
−
20
−
−
20
−
Remark Cφ 1-1 to Cφ 2-2 show the equivalent capacity of the real drive including the capacity of between each clock
pin (φ 1-1, φ 1-2, φ 2-1 and φ 2-2).
INPUT SIGNAL TABLE
Mode
φ SEL1
φ SEL2
φ SEL3
Note
(Even-line enable
switch)
(CCD-drain switch) (TG-select switch)
4800 dpi
High level
High level
Low level
High level
High level
High level
High level
Low level
Low level
Even-line electron read photodiode to CCD
Odd-line electron read photodiode to CCD
Odd-line electron read photodiode to CCD
Even-line electron sink to drain
2400 dpi
1200 dpi
600 dpi
Low level
Low level
Low level
1, 5, 9, 13, … : Line photodiode use
2 to 4, 6 to 8, 10 to 12, … : Sink to drain
8
Data Sheet S17546EJ1V0DS
TIMING CHART 1-1 (4800 dpi, for each color)
Storage time (l2, l4)
Storage time (l1, l3)
φ
TG1 to φTG3
2400 dpi cycle
Odd line read
2400 dpi cycle
Even line read
φ
SEL3
φ
SEL1,
φ
SEL2 “H”
φ
φ
1-2400
2-2400
21360 pixels
Odd 2400 dpi
Data read
21360 pixels
Even 2400 dpi
Data read
21360 pixels
Odd 2400 dpi
Data read
21360 pixels
Even 2400 dpi
Data read
Remark Above means, storage time of each photocell array is “TG period × 2”. And storage time of (l1, l3) and (l2, l4) is a half overlap each other.
μ
TIMING CHART 1-2 (2400 dpi, for each color)
Storage time
φ
TG1 to φTG3
φ
φ
1
2
φ
RB
Note
Note
φ
CLB
φ
SEL1
SEL2
SEL3
“L”
“H”
φ
φ
“L”
V
OUT1 to VOUT3
Optical black
(96 pixels)
Valid photocell
(21360 pixels)
μ
Invalid photocell
(8 pixels)
Invalid photocell
(4 pixels)
Note Set the φ RB and the φ CLB to high level during this period.
TIMING CHART 1-3 (1200 dpi, for each color)
Storage time
φ
TG1 to φTG3
φ
φ
1
2
φ
RB
Note
Note
φ
CLB
φ
SEL1
SEL2
SEL3
“L”
“L”
“L”
φ
φ
V
OUT1 to VOUT3
Optical black
(48 pixels)
Valid photocell
(10680 pixels)
μ
Invalid photocell
(4 pixels)
Invalid photocell
(2 pixels)
Note Set the φ RB and the φ CLB to high level during this period.
TIMING CHART 1-4 (600 dpi, for each color)
Storage time
φ
TG1 to φTG3
φ
φ
1
2
φ
RB
Note
Note
φ
CLB
φ
SEL1
SEL2
SEL3
“L”
“L”
“L”
φ
φ
V
OUT1 to VOUT3
Optical black
(24 pixels)
Valid photocell
(5340 pixels)
μ
Invalid photocell
(2 pixels)
Invalid photocell
(1 pixels)
N Note Set the φ RB and the φ CLB to high level during this period.
Remark 2 pixels data merge at the charge detected capacitance.
μPD8884A
TIMING CHART 2-1 (4800 dpi / 2400 dpi, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t5
t6
t5
t6
t3
t3
t4
t4
90%
10%
φ
RB
t9 t10
t8 t11
t9 t10
t7
t7
t8 t11
90%
10%
φ
CLB
t
d
t
d
RFTN
V
OS
V
OUT
10%
10%
Symbol
t1, t2
Min.
0
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
t3
20
40
0
100
150
10
t4
t5, t6
t7
−10
20
0
+25
100
10
t8
t9, t10
t11
td
10
−
25
15
13
Data Sheet S17546EJ1V0DS
μPD8884A
TIMING CHART 2-2 (1200 dpi, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t5
t6
t3
t4
90%
10%
φ
RB
t9 t10
t8 t11
t7
90%
10%
φ
CLB
t
d
RFTN
V
OS
V
OUT
10%
Symbol
t1, t2
Min.
0
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
t3
20
40
0
100
150
10
t4
t5, t6
t7
−10
20
0
+25
100
10
t8
t9, t10
t11
td
10
−
25
15
14
Data Sheet S17546EJ1V0DS
μPD8884A
TIMING CHART 2-3 (600 dpi, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t5
t6
t3
t4
90%
10%
φ
RB
t9 t10
t8 t11
t7
90%
10%
φ
CLB
t
d
RFTN
10%
V
OUT
V
OS
Symbol
t1, t2
Min.
0
Typ.
30
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
t3
20
40
0
100
150
10
t4
t5, t6
t7
−10
20
0
+25
100
10
t8
t9, t10
t11
td
10
−
25
15
15
Data Sheet S17546EJ1V0DS
μPD8884A
TIMING CHART 3 (readout)
t13
t14
t12
90%
10%
t15
φ
TG1 to φ TG3
t16
90%
10%
φ
SEL3
t17
t18
90%
φ
φ
1
2
t19
t20
90%
φ
RB,
φ
CLB
Symbol
Min.
Typ.
Max.
Unit
t12
8000
0
15000
50
(50000)
ns
ns
ns
ns
ns
ns
t13, t14
t15, t16
t17
−
−
−
−
−
1000
1000
7000
500
2000
2000
10000
1000
t18
t19, t20
φ 1, φ 2 CROSS POINTS
φ
φ
2
1
2.0 V or more
2.0 V or more
Remark Adjust cross points of φ 1 and φ 2 with input resistance of each pin.
16
Data Sheet S17546EJ1V0DS
μPD8884A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
Photo pixel and CCD register electron saturate level.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. PRNU of 4800 dpi is calculated by the following formula.
x
y
Δ
y
Δ
PRNUIN (%) =
× 100
PRNUOUT (%) =
× 100
x
Δ
x : maximum of ⎪x
j
− x ⎪
Δ
x : maximum of ⎪y − y ⎪
j
IV
IO
x
j
y
j
Σ
Σ
j = 1
j = 1
x =
y =
IV
IO
xj
: Output voltage of valid pixel number j
y
j
: Output voltage of valid pixel number j
IV : Number of inside valid pixels (21360 bits)
IO : Number of outside valid pixels (21360 bits)
The following figure shows output waveform of 4800 dpi mode.
V
OUT
x
y
Register Dark
DC level
Δ
x
Δ
y
Inside 2400 dpi data set
Outnside 2400 dpi data set
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
Vaild pixels
d
j
Σ
j = 1
Valid pixels
ADS (mV) =
d
j
: Dark signal of valid pixel number j
17
Data Sheet S17546EJ1V0DS
μPD8884A
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of ⎪d
j
− ADS ⎪j = 1 to Valid pixels
dj
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral
characteristic). R of 4800 dpi is defined as following (refer to 3. Photo response non-uniformity).
¯¯
RIN : x divided by exposure (lx•s)
¯¯
ROUT : y divided by exposure (lx•s)
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
VOUT
V1
VOUT
V
1
IL (%) =
× 100
OUT
V
18
Data Sheet S17546EJ1V0DS
μPD8884A
9. Response difference between inside and outside : RDIO
Difference of average output voltage between inside 2400 dpi and outside 2400 dpi (refer to 3. Photo
response non-uniformity).
2 ⎪ x − y ⎪
RDIO (%) =
× 100
x + y
10. Photocell array imbalance : PAI
PAI is calculated by following formula (refer to 3. Photo response non-uniformity).
n
2
m
2
2
n
2
m
∑
(
x
2j –1
n
–
x
2j
)
∑
(
y
2j –1
–
y2j)
j = 1
j = 1
PAIIN (%) =
× 100
PAIOUT (%) =
× 100
m
1
n
1
n
∑
x
j
∑
y
j
j = 1
j = 1
x
j
: Output voltage of each pixel
y
j
: Output voltage of each pixel
n : Number of valid pixels (21360 bits)
m : Number of valid pixels (21360 bits)
11. Offset level : VOS
DC level of output signal is defined as follows.
12. Reset feed-through noise : RFTN
Reset feed-through noise (RFTN) are defined as follows.
RFTN
V
OS
V
OUT
19
Data Sheet S17546EJ1V0DS
μPD8884A
13. Random noise (CDS) : σCDS
Random noise σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding). σCDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by the following formula.
VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σ CDS using the following formula equation.
100
100
(VCDS
100
i
– V)2
1
Σ
σ
CDS (mV) =
, V =
VCDS
i
100 Σ
i = 1
i = 1
The following figure shows output waveform (valid photocell under dark condition).
Reset feed-through
Video output
20
Data Sheet S17546EJ1V0DS
μPD8884A
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
8
2
4
1
2
1
0.5
0.2
0.25
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature T
A
(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T = +25°C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
21
Data Sheet S17546EJ1V0DS
μPD8884A
APPLICATION CIRCUIT EXAMPLE
+12 V
μ
PD8884A
B3
B2
B1
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
+
V
OUT
3
V
OUT
OUT
2
1
47
Ω
Ω
φ
φ
V
CLB
CLB
RB
0.1
μ
F
47
μ
F/25 V
47
Ω
47
3
φ
φ
φ
SEL2
φ
SEL2
RB
4
GND
2-1
VOD
5.1
Ω
5.1 Ω
5
φ
φ
φ
1-1
IC
φ
1-1
2-1
6
IC
7
IC
IC
8
NC
NC
NC
NC
NC
NC
1-2
IC
9
10
11
12
13
14
15
16
5.1
Ω
5.1 Ω
φ
φ
2-2
φ
φ
1-2
2-2
IC
IC
IC
47 Ω
47 Ω
47 Ω
GND
φ
SEL1
φ
φ
SEL1
TG
47
47
Ω
Ω
φ
φ
φ
φ
TG1
TG2
SEL3
SEL3
TG3
φ
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remarks 1. φRB, φCLB, φTG1 to φTG3 and φSEL1 to φSEL3 driving inverters shown in the above application
circuit example are the 74HC04.
φ1-1 to φ2-2 driving inverters shown in the above application circuit example are the 74HC04 (≤ 2.0
MHz) or the 74AC04 (> 2.0 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
μ
47 F/25 V
100 Ω
CCD
2SC1842
2 kΩ
VOUT
100 Ω
22
Data Sheet S17546EJ1V0DS
μPD8884A
PACKAGE DRAWING
μ
PD8884ACY
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm)
55.2 0.5
54.8 0.5
1st valid pixel
1
5.85 0.3
17
16
32
1
4
46.7
4
2.0
12.6 0.5
4.1 0.5
10.16 0.20
4.55 0.5
1.02 0.15
2
(1.775)
3
2.725 0.3
0.25 0.05
(5.42)
4.21 0.5
0.46 0.1
2.54 0.25
+0.70
−0.20
10.16
Name
Dimensions
Refractive index
5
)
Plastic cap
52.2×6.4×0.8 (0.7
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
4 Mirror finishied surface
The top of the cap
The surface of the CCD chip
5 Thickness of mirror finished surface
23
Data Sheet S17546EJ1V0DS
μPD8884A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Through-hole Device
μPD8884ACY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
2.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
24
Data Sheet S17546EJ1V0DS
μPD8884A
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
25
Data Sheet S17546EJ1V0DS
μPD8884A
[MEMO]
26
Data Sheet S17546EJ1V0DS
μPD8884A
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
27
Data Sheet S17546EJ1V0DS
μPD8884A
•
The information in this document is current as of May, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
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and industrial robots.
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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