UPD98502N7-H6-A [NEC]
LAN Controller, 3 Channel(s), 12.5MBps, CMOS, PBGA500, 40 X 40 MM, BGA-500;
| 型号： | UPD98502N7-H6-A |
| 厂家： | 
NEC |
| 描述： | LAN Controller, 3 Channel(s), 12.5MBps, CMOS, PBGA500, 40 X 40 MM, BGA-500 局域网 外围集成电路 |
| 文件： | 总52页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98502
NETWORK CONTROLLER
The µPD98502 network controller is an LSI for network terminal applications such as ADSL systems. The
controller integrates a VR4120A MIPS RISC CPU core, memory interface, PCI, and other network interface
functions such as ATM, Ethernet, and USB on one chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD98502 User’s Manual: S15543E
FEATURES
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Includes high performance MIPS based 64-bit RISC processor VR4120A
Can perform RTOS and network middleware (M/W) on the chip
Includes interface for PROM and flash ROM used for storing boot program
Includes 32-bit RISC controller in ATM Cell Processor
Software SAR processing by RISC controller affords flexibility for specification update
Supports CBR/VBR/UBR service classes
Include 2-channel 10/100-Mbps Ethernet controllers compliant to IEEE802.3, IEEE 802.3u and IEEE802.3x
Can directly connect external Ethernet PHY device through 3.3 V MII interface
Includes USB full speed function controller compliant to USB specification 1.1
Supports operation conforming to the USB Communication Device Class Specification
Can directly connect 64-Mbit and 128-Mbit SDRAM as external memory
Includes 32-bit 33-MHz PCI Bus Master compliant to PCI Specification Rev. 2.2
Includes 8-bit 16.5/25/33-MHz UTOPIA level 2 interface compliant to ATM Forum af-phy-0039
Includes boundary scan function (JTAG) compliant to IEEE 1149.1
Include UART and Micro Wire™ interfaces
Include 2-ch general purpose timers
Using advanced CMOS technology
Power supply 2.5V(Core)/3.3V(I/O)
Package 500-pin T-BGA
ORDERING INFORMATION
Part Number
Package
500-pin tape BGA (Heat spreader type) (40 × 40)
µPD98502N7-H6
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15409EJ2V0DS00 (2nd edition)
Date Published July 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2001
©
µPD98502
INTERNAL BLOCK DIAGRAM
IBUS
VR4120A RISC
Processor Core
USB
Full-Speed USB
Controller
PROM/Flash
SDRAM
3.3V MII
Ethernet
Controller
#1, #2
System
Controller
RS-232C/
Micro Wire
16.5/25/33 MHz
UTOPIA 2
Parallel Port
ATM Cell
Processor
PHY
Management
PCI
Controller
32-bit
PCI Interface
JTAG
JTAG
Control
Clock
Control
2
Data Sheet S15409EJ2V0DS
µPD98502
PIN CONFIGURATION (Bottom View)
• 500-pin tape BGA (Heat spreader type) (40 × 40)
µ PD98502N7-H6
Index Mark
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AK AJ AH AG AF AE AD AC AB AA
Y W V U T R P N M L K J H G F E D C B A
3
Data Sheet S15409EJ2V0DS
µPD98502
PINTABLE
(1/3)
Pin No.
Pin Name
Pin No.
B10
Pin Name
URSDO
RMSL1
MWDO
POM3
Pin No.
C19
Pin Name
IC-PDnR
IC-OPEN
JDI
Pin No.
D28
Pin Name
PGTO2_B
PRQI1_B
PAD0
Pin No.
F27
Pin Name
A1
SMA13
SMD0
GND
A2
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
C1
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
D1
D29
D30
E1
F28
F29
F30
G1
GND
A3
SMD4
PAD5
A4
SMD7
GND
GND
PAD6
A5
SMD19
SMD22
SRMCS_B
URDSR_B
URDCD_B
URDTR_B
MWSK
MWDI
POM5
USBDM
IC-OPEN
PUDGND
IVDD
E2
SDRAS_B
SMA0
SMA8
SMA15
SDCLK1
EVDD
SDCAS_B
PAD1
A6
EVDD
E3
G2
A7
IC-OPEN
IC-OPEN
IC-PUpR
IC-OPEN
GND
E4
SMA10
GND
G3
A8
E5
G4
A9
PMODE
PGTO3_B
PGTO1_B
PRQI0_B
SDWE_B
SMA1
E6
EVDD
SMD16
GND
G5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B1
E7
G26
G27
G28
G29
G30
H1
E8
PAD3
IC-PDn
JDO
E9
EVDD
GND
EVDD
PAD7
EXNMI_B
POM6
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
F1
GND
D2
RMSL0
GND
PAD8
EXINT_B
IVDD
USBDP
PUDVD
IC-OPEN
PUMD_B
PHINT_B
PRSTO_B
PGTO0_B
SMA2
D3
SMA11
IVDD
SMA4
SMA7
SMA9
IVDD
D4
POM0
GND
H2
IC-PUpR
IC-PDnR
IC-OPEN
IC-OPEN
IC-PDn
JCK
D5
SMD3
H3
D6
SMD6
POM7
GND
H4
D7
EVDD
H5
GND
D8
IVDD
GND
H26
H27
H28
H29
H30
J1
GND
D9
URCLK
IVDD
IC-OPEN
GND
IVDD
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
PCBE0_B
PAD9
JMS
C2
GND
GND
IC-PDn
GND
EVDD
C3
SMA16
SMD2
IVDD
GND
EVDD
C4
POM1
EVDD
GND
SMA18
SMA3
SMA5
SMA6
EVDD
EVDD
PAD10
PAD11
PAD12
PAD13
SMD31
SMA20
SMA19
IVDD
PUAVD
GND
C5
GND
IVDD
J2
C6
SMD18
SMD21
SRMOE_B
GND
IC-PDnR
BIG
USBCLK
EVDD
GND
J3
IC-OPEN
GND
C7
J4
C8
IVDD
J5
PSERI_B
SMA12
SMA14
SMD1
C9
IC-OPEN
IVDD
PRQI3_B
PRQI2_B
PAD2
J26
J27
J28
J29
J30
K1
C10
C11
C12
C13
C14
C15
C16
C17
C18
URRTS_B
EVDD
B2
IC-OPEN
IVDD
B3
MWCS
POM2
PAD4
B4
SMD5
JRSTB_B
IVDD
SMA17
SDCKE1
SDCS_B
GND
B5
SMD17
SMD20
SMD23
URCTS_B
URSDI
POM4
F2
B6
ENDCEN
GND
PUAGND
PUSTBY
PARBN
IVDD
F3
K2
B7
F4
K3
B8
IC-PDnR
IC-OPEN
F5
EVDD
EVDD
K4
B9
F26
K5
GND
4
Data Sheet S15409EJ2V0DS
µPD98502
(2/3)
Pin No.
K26
Pin Name
GND
Pin No.
P5
Pin Name
GND
Pin No.
V4
Pin Name
IVDD
Pin No.
AB3
Pin Name
IC-PUp
IC-PDn
EVDD
Pin No.
Pin Name
MICRS
MIMCLK
MITD3
GND
AF2
K27
K28
K29
K30
L1
IVDD
P26
P27
P28
P29
P30
R1
GND
V5
GND
AB4
AF3
PAD14
PAD15
EVDD
IVDD
V26
V27
V28
V29
V30
W1
PAD26
PAD25
PAD24
GND
AB5
AF4
PAD16
PAD17
PAD18
EVDD
SMD12
SMD9
SMD10
SMD11
EVDD
PAD19
PAD20
GND
AB26
AB27
AB28
AB29
AB30
AC1
EVDD
AF5
IC-OPEN
IC-OPEN
GND
AF6
EVDD
MI2TE
GND
SDCLK0
GND
AF7
L2
PSCLK
IC-PUp
IVDD
AF8
L3
SDCKE0
SMD30
EVDD
R2
RST_B
IC-PUp
MIRD3
GND
AF9
EVDD
GND
L4
R3
W2
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG1
L5
R4
W3
IC-PUp
IVDD
AC2
UDRD1
GND
L26
L27
L28
L29
L30
M1
M2
M3
M4
M5
M26
M27
M28
M29
M30
N1
PCBE1_B
GND
R5
W4
AC3
R26
R27
R28
R29
R30
T1
W5
GND
AC4
IVDD
UDRAD2
GND
PAR
W26
W27
W28
W29
W30
Y1
GND
AC5
GND
PSERO_B
PER_B
EVDD
IVDD
AC26
AC27
AC28
AC29
AC30
AD1
GND
UDTAD3
UDTD7
GND
PAD28
EVDD
PAD27
IC-OPEN
PSDGND
PSAGND
PSAVD
PSDVD
PAD31
PME_B
PRQO_B
PAD30
PAD29
IC-OPEN
PSTBY
PSMD_B
IVDD
IVDD
PAD21
SMD8
GND
IC-OPEN
IC-OPEN
PINT_B
MIRD2
MIRD1
MIRCLK
MIRER
MIRDV
GND
SMD28
SMD29
IVDD
EVDD
GND
T2
T3
CLKUSL1
CLKUSL0
EVDD
PAD22
IVDD
Y2
UMWR_B
GND
GND
T4
Y3
AD2
GND
T5
Y4
AD3
EVDD
GND
IVDD
T26
T27
T28
T29
T30
U1
Y5
AD4
PSTP_B
PDSEL_B
EVDD
Y26
Y27
Y28
Y29
Y30
AA1
AA2
AA3
AA4
AA5
AA26
AA27
AA28
AA29
AA30
AB1
AB2
AD5
GND
GND
AD26
AD27
AD28
AD29
AD30
AE1
EVDD
GND
PAD23
PCBE3_B
CLKSL
GND
EVDD
SMD24
SMD25
GND
IC-PDnR
IC-OPEN
GND
GND
N2
IC-PDnR
IC-PDnR
IC-PDnR
MIMD
N3
U2
N4
SMD26
SMD27
PTRY_B
PIRY_B
GND
U3
IC-PUp
IVDD
MIRD0
GND
N5
U4
AE2
N26
N27
N28
N29
N30
P1
U5
GND
AE3
MITER
IVDD
AG2
GND
U26
U27
U28
U29
U30
V1
GND
GND
AE4
AG3
MITD2
IVDD
IVDD
GND
AE5
EVDD
AG4
PFRA_B
PCBE2_B
SMD13
SMD14
SMD15
IVDD
PIDSEL
GND
IVDD
AE26
AE27
AE28
AE29
AE30
AF1
EVDD
AG5
MI2COL
IVDD
PGTI_B
GND
IC-PDnR
IC-PDnR
IC-PDnR
IC-PDnR
MITE
AG6
EVDD
SCLK
AG7
MI2CRS
IVDD
P2
EVDD
IC-OPEN
GND
AG8
P3
V2
GND
AG9
UDRSC
IVDD
P4
V3
IC-PUp
AG10
5
Data Sheet S15409EJ2V0DS
µPD98502
(3/3)
Pin No.
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AH1
Pin Name
UDRD0
IVDD
Pin No.
AH3
Pin Name
MICOL
Pin No.
AH25
AH26
AH27
AH28
AH29
AH30
AJ1
Pin Name
EVDD
Pin No.
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AK1
Pin Name
UDTD5
GND
Pin No.
AK9
Pin Name
UDRD5
UDRD2
UDRCLK
UDRAD3
UDRAD0
UDTE_B
UDTAD4
UDTCLK
UDTD6
UDTD3
UDTD0
UMRST_B
UMRD_B
UMD14
UMD12
UMD8
AH4
MI2RD0
MI2MD
MI2TER
MI2TD3
GND
IVDD
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
UDRAD1
IVDD
AH5
UMAD8
UMAD7
UMAD3
UMAD1
MITD0
MI2MCLK
MI2RD1
GND
UMRDY_B
GND
AH6
UDTAD2
UDTAD0
IVDD
AH7
EVDD
AH8
UMD13
UMD9
AH9
UDRCLV
UDRD4
UDTCLV
IC-OPEN
EVDD
UDTD1
IVDD
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AJ2
UMD7
AJ3
UMD4
UMMD
IVDD
AJ4
UMD1
AJ5
MI2RER
GND
GND
UMD10
IVDD
UDTSC
EVDD
AJ6
GND
AJ7
MI2TD1
UDRE_B
UDRD6
UDRD3
UDRAD4
IC-OPEN
GND
UMAD6
UMAD4
MI2RD3
MI2RD2
MI2RCLK
MI2RDV
MI2TCLK
MI2TD2
MI2TD0
UDRD7
UMD2
UDTAD1
UDTD4
UDTD2
UMINT_B
UMSL_B
UMD15
UMD11
GND
AJ8
UMAD11
UMAD9
IVDD
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AK2
AK3
UMD6
UMAD2
UMAD0
IVDD
AK4
UMD3
AK5
UMD0
GND
AK6
UMAD10
IC-PUp
UMAD5
MITCLK
MITD1
IVDD
AK7
AH2
UMD5
GND
AK8
Special pin name description:
IC-PDn:
Pull Down
IC-PDnR:
IC-PUp:
Pull Down with Resistor
Pull Up
IC-PUpR:
Pull Up with Resistor
Remark In this document, XXX_B stands for active low pin.
6
Data Sheet S15409EJ2V0DS
µPD98502
CONTENTS
1. PIN FUNCTIONS ................................................................................................................................... 8
1.1 Power Supply................................................................................................................................ 8
1.2 System PLL Power Supply .......................................................................................................... 8
1.3 USB PLL Power Supply ............................................................................................................... 8
1.4 System Control Interface............................................................................................................. 9
1.5 Memory Interface.......................................................................................................................... 9
1.6 PCI Interface................................................................................................................................ 10
1.7 ATM Interface.............................................................................................................................. 12
1.7.1 UTOPIA Management Interface.......................................................................................................12
1.7.2 UTOPIA Data Interface ....................................................................................................................12
1.8 Ethernet Interface ....................................................................................................................... 13
1.8.1 Ethernet Interface (Channel 1).........................................................................................................13
1.8.2 Ethernet Interface (Channel 2).........................................................................................................13
1.9 USB Interface .............................................................................................................................. 14
1.10 UART Interface............................................................................................................................ 14
1.11 Micro Wire Interface ................................................................................................................... 14
1.12 Parallel Port Interface................................................................................................................. 14
1.13 Boundary SCAN Interface.......................................................................................................... 14
1.14 I.C. – open.................................................................................................................................... 15
1.15 I.C.– pull down ............................................................................................................................ 15
1.16 I.C. – pull down with resistor..................................................................................................... 15
1.17 I.C. – pull up ................................................................................................................................ 15
1.18 I.C. – pull up with resistor.......................................................................................................... 15
2. ELECTRICAL SPECIFICATIONS ....................................................................................................... 16
3. PACKAGE DRAWING......................................................................................................................... 47
4. RECOMMENDED SOLDERING CONDITIONS................................................................................. 48
7
Data Sheet S15409EJ2V0DS
µPD98502
1. PIN FUNCTIONS
Symbol of I/O column indicates following status in this section.
I
:
:
:
:
:
:
Input
O
Output
I/O
I/OZ
OZ
OD
Bidirection
Bidirection (Include Hi-Z state)
Output (Include Hi-Z state)
Output (Open drain)
1.1 Power Supply
Pin Name
GND
Pin No.
I/O
Active Level
Function
GND (0 V)
A27, A29, B20, B23, C2, C5, C9, C16, C22, D11, E1, E5,
E8, E10, E12, E14, E16, E17, E19, E21, E23, E26, F4,
F27, F28, H5, H26, H30, K5, K26, L2, L27, M5, M26, N3,
N28, P5, P26, R29, T2, T28, U2, U5, U26, U29, V2, V5,
V29, W5, W26, AA5, AA26, AA29, AB2, AB29, AC3, AC5,
AC26, AD26, AD30, AE2, AF5, AF8, AF10, AF12, AF14,
AF17, AF19, AF21, AF23, AF24, AF26, AF27, AG2, AH8,
AH23, AJ4, AJ6, AJ13, AJ14, AJ16, AJ18, AJ20, AJ27,
AJ28
IVDD
A16, C26, D4, D8, D10, D12, D14, D17, D19, D21, D23,
D27, H4, H27, K4, K27, M4, M27, P4, P27, T27, U4, U27,
V4, W2, W4, W27, AA4, AA27, AC4, AC27, AE4, AG4,
AG6, AG8, AG10, AG12, AG14, AG17, AG19, AG21,
AG23, AG27, AG30, AH26, AJ15
Internal logic core
power supply (+2.5 V)
EVDD
A24, A25, B15, C11, D7, E6, E9, E22, E25, F5, F26, G4,
G28, J5, J26, K30, L5, M1, M30, R1, R26, T5, U30, W29,
AA30, AB5, AB26, AD27, AE5, AE26, AF6, AF9, AF18,
AF22, AF25, AH13, AH15, AH25, AJ21
External (I/O) power
supply (+3.3 V)
1.2 System PLL Power Supply
Pin Name
PSAGND
Pin No.
I/O
Active Level
Function
Y3
Y4
Y2
Y5
Analog ground (0 V)
PSAVD
Analog power supply (+2.5 V)
Digital ground (0 V)
PSDGND
PSDVD
Digital power supply (+2.5 V)
1.3 USB PLL Power Supply
Pin Name
PUAGND
Pin No.
I/O
Active Level
Function
D24
A26
C25
B25
Analog ground (0 V)
PUAVD
Analog power supply (+2.5 V)
Digital ground (0 V)
PUDGND
PUDVD
Digital power supply (+2.5 V)
8
Data Sheet S15409EJ2V0DS
µPD98502
1.4 System Control Interface
Pin Name
Pin No.
I/O
Active Level
Function
SCLK
V1
U1
I
I
System clock (33 MHz)
CLKSL
Clock select (L: 100 MHz/H: 66 MHz) for VR4120A and
SDRAM
System PLL mode control (L: normal, H: through) Note
System PLL standby mode control (L: active, H: standby)
USB PLL mode control (L: normal, H: through) Note
PSMD_B
AA3
I
L
PSTBY
AA2
B27
I
I
H
L
PUMD_B
PUSTBY
BIG
D25
I
I
I
I
I
I
I
H
H
USB PLL standby mode control (L: active, H: standby)
VR4120A big endian mode
D16
ENDCEN
EXINT_B
EXNMI_B
RST_B
C15
Endian converter enable
A15
L
L
L
External interrupt
A13
External non-maskable interrupt
System reset
AB30
E11, B11
RMSL0, RMSL1
ROM access bus width select
(RMSL1/0 = L/L: 32-bit, L/H: 16-bit, H/L: 8-bit)
Note PSMD_B and PUMD_B pins shall be connected to GND.
1.5 Memory Interface
Pin Name
SDCLK0, SDCLK1
SDCKE0, SDCKE1
SDCS_B
Pin No.
I/O
O
O
O
O
O
O
O
O
O
Active Level
Function
SDRAM clock
L1, G3
L3, F2
F3
H
L
L
L
L
L
L
SDRAM clock enable
Chip select
SDRAS_B
E2
Row address strobe
Column address strobe
Write enable
SDCAS_B
G5
SDWE_B
D1
SRMCS_B
A7
PROM/FLASH chip select
PROM/FLASH output enable
Memory address
SRMOE_B
C8
SMA0 - SMA20
E3, D2, C1, J2, H1,
J3, J4, H2, G1, H3,
E4, D3, B1, A1, B2,
G2, C3, F1, J1, K3,
K2
SMD0 - SMD31
A2, B3, C4, D5, A3,
B4, D6, A4, T1, R3,
R4, R5, R2, P1, P2,
P3, E7, B5, C6, A5,
B6, C7, A6, B7, N1,
N2, N4, N5, M2, M3,
L4, K1
I/O
Memory data
9
Data Sheet S15409EJ2V0DS
µPD98502
1.6 PCI Interface
(1/2)
Pin Name
PSCLK
Pin No.
I/O
Active Level
H
Function
V30
D26
I
I
PCI clock (33 MHz)
PCI arbiter enable
PARBN
NIC Mode : Not available (Connect to GND)
Host Mode : Control for Internal Bus Arbiter
High -> Enable
Low -> Disable
PMODE
PIDSEL
C27
U28
I
I
PCI mode select (L: host, H: NIC)
Initialization device select
NIC Mode : Available
H
Host Mode : Not Available (Connect to GND)
Device select
PDSEL_B
PER_B
M29
L30
N29
B28
I/OZ
I/OZ
I/OZ
I
L
L
L
L
Parity error
PFRA_B
PHINT_B
Cycle frame
PCI host interrupt
NIC Mode : Not available (Connect to EVDD)
Host Mode : Available
PINT_B
AC30
O
L
Interrupt_A
NIC Mode : Available
Host Mode : Not Available (Leave open)
Initiator ready
PIRY_B
PME_B
N27
Y27
I/OZ
OD
L
L
Power management event
NIC Mode : Available
Host Mode : Not Available (Leave open)
PCI system reset out
PRSTO_B
PSERI_B
PSERO_B
B29
A30
L29
O
I
L
L
L
NIC Mode : Not Available (Leave open)
Host Mode : Available
System error in
NIC Mode : Not available (Connect to EVDD)
Host Mode : Available
O
System error out
NIC Mode : Available
Host Mode : Not Available (Leave open)
Target ready
PTRY_B
N26
M28
I/OZ
I/OZ
I/OZ
O
L
L
L
L
PSTP_B
Stop request from target
Bus command and byte enable
Bus request out
PCBE[0:3]_B
PRQO_B
H28, L26, N30, T30
Y28
NIC Mode : Available
Host Mode : Not Available (Leave open)
Bus request in
PRQI[0:3]_B
PGTI_B
C30, D29, E28, E27
AA28
I
I
L
L
NIC Mode : Not available (Connect to EVDD)
Host Mode : Available
Bus grant in
NIC Mode : Available
Host Mode : Not available (Connect to EVDD)
10
Data Sheet S15409EJ2V0DS
µPD98502
(2/2)
Pin Name
PGTO[0:3]_B
Pin No.
I/O
O
Active Level
L
Function
B30, C29, D28, C28
Bus grant out
NIC Mode : Not Available (Leave open)
Host Mode : Available
PAR
L28
I/OZ
I/OZ
Parity of address/data
PAD0 - PAD31
D30, G26, E29, G27,
E30, F29, F30, G29,
G30, H29, J27, J28,
J29, J30, K28, K29,
P28, P29, P30, R27,
R28, R30, T26, T29,
V28, V27, V26, W30,
W28, Y30, Y29, Y26
PCI address and data
11
Data Sheet S15409EJ2V0DS
µPD98502
1.7 ATM Interface
1.7.1 UTOPIA Management Interface
Pin Name
UMMD
Pin No.
I/O
O
I
Active Level
Function
Management mode select
AG20
AH19
AK21
AJ19
AK20
AH20
AF20
UMINT_B
L
L
L
L
L
L
Interrupt from PHY
Management read enable
Management data ready
PHY reset
UMRD_B
O
I
UMRDY_B
UMRST_B
UMSL_B
O
O
O
O
PHY select
UMWR_B
Management write enable
PHY address
UMAD0 - UMAD11
AG29, AH30, AG28,
AH29, AJ30, AK30,
AJ29, AH28, AH27,
AG26, AK28, AG25
UMD0 - UMD15
AK27, AJ26, AG24,
AK26, AJ25, AH24,
AK25, AJ24, AK24,
AJ23, AG22, AH22,
AK23, AJ22, AK22,
AH21
I/O
Management data
1.7.2 UTOPIA Data Interface
Pin Name
Pin No.
I/O
I
Active Level
Function
CLKUSL0, CLKUSL1 T4, T3
UTOPIA clock select
(CLKUSL1/0 = L/L: 33 MHz, H/L: 25 MHz, L/H: 16.5 MHz)
Receive clock
UDRCLK
AK11
AH9
AJ8
O
I
UDRCLV
H
L
Receive cell available
UDRE_B
O
I
Receive enable
UDRSC
AG9
H
Receive cell start
UDRAD0 - UDRAD4
AK13, AG13, AF13,
AK12, AJ11
O
Receive PHY address
UDRD0 - UDRD7
AG11, AF11, AK10,
AJ10, AH10, AK9,
AJ9, AK8
I
Receive data
UDTCLK
AK16
AH11
AK14
AH14
O
I
Transmit clock
UDTCLV
H
L
Transmit cell available
Transmit enable
UDTE_B
O
O
O
UDTSC
H
Transmit cell start position
Transmit PHY address
UDTAD0 - UDTAD4
AG16, AH16, AG15,
AF15, AK15
UDTD0 - UDTD7
AK19, AG18, AH18,
AK18, AH17, AJ17,
AK17, AF16
O
Transmit data
12
Data Sheet S15409EJ2V0DS
µPD98502
1.8 Ethernet Interface
1.8.1 Ethernet Interface (Channel 1)
Pin Name
MIMCLK
Pin No.
I/O
Active Level
Function
AF3
AG1
AH3
AF2
AD3
AD5
AD4
O
I/O
I
MII management clock
MII management data
Collision
MIMD
MICOL
MICRS
I
Carrier sense
MIRCLK
MIRDV
I
Receive clock (2.5 MHz/25 MHz)
Receive data valid
Receive error
I
MIRER
I
MIRD0 - MIRD3
MITCLK
MITE
AE1, AD2, AD1, AC2
I
Receive data
AH1
I
Transmit clock (2.5 MHz/25 MHz)
Transmit enable
AF1
O
O
O
MITER
AE3
Transmit error
MITD0 - MITD3
AJ1, AH2, AG3, AF4
Transmit data
1.8.2 Ethernet Interface (Channel 2)
Pin Name
MI2MCLK
Pin No.
I/O
Active Level
Function
MII management clock
MII management data
Collision
AJ2
AH5
AG5
AG7
AK3
AK4
AJ5
O
I/O
I
MI2MD
MI2COL
MI2CRS
I
Carrier sense
MI2RCLK
MI2RDV
I
Receive clock (2.5 MHz/25 MHz)
Receive data valid
Receive error
I
MI2RER
I
MI2RD0 - MI2RD3
MI2TCLK
MI2TE
AH4, AJ3, AK2, AK1
I
Receive data
AK5
I
Transmit clock (2.5 MHz/25 MHz)
Transmit enable
AF7
O
O
O
MI2TER
AH6
Transmit error
MI2TD0 - MI2TD3
AK7, AJ7, AK6, AH7
Transmit data
13
Data Sheet S15409EJ2V0DS
µPD98502
1.9 USB Interface
Pin Name
USBCLK
Pin No.
I/O
I
Active Level
Function
External USB clock (12 MHz)
E24
C23
B24
USBDM
I/O
I/O
USB data(–)
USB data(+)
USBDP
1.10 UART Interface
Pin Name
URCLK
Pin No.
I/O
I
Active Level
Function
D9
UART external clock (18.432 MHz)
UART clear to send
URCTS_B
URDCD_B
URDSR_B
URDTR_B
URRTS_B
URSDI
B8
I
L
L
L
L
L
A9
I
UART data carrier detect
UART data set ready
A8
I
A10
C10
B9
O
O
I
UART data terminal ready
UART data request to send
UART serial data input
URSDO
B10
O
UART serial data output
1.11 Micro Wire Interface
Pin Name
Pin No.
I/O
O
I
Active Level
Function
Micro Wire chip select
MWCS
MWDI
C12
A12
B12
A11
Micro Wire data in
MWDO
MWSK
O
O
Micro Wire data out
Micro Wire sampling clock out
1.12 Parallel Port Interface
Pin Name
Pin No.
I/O
O
Active Level
Function
POM0 - POM7
E13, D13, C13, B13,
C14, B14, A14, E15
Parallel port signal output
1.13 Boundary SCAN Interface
Pin Name
Pin No.
I/O
Active Level
Function
B-SCAN clock
JCK
JDI
A22
C21
B22
A23
D22
I
I
B-SCAN input-data
B-SCAN output-data
B-SCAN mode select
B-SCAN reset
JDO
JMS
OZ
I
I
JRSTB_B
L
14
Data Sheet S15409EJ2V0DS
µPD98502
1.14 I.C. – open
Pin Name
IC-OPEN
Pin No.
I/O
O
Active Level
Function
A19, A20, A28, B16, B17, B19, B26, C18, C20, C24, D18,
D20, E18, Y1, AA1, AB1, AB27, AB28, AC28, AC29,
AD29, AH12, AJ12
Leave open
1.15 I.C.– pull down
Pin Name
IC-PDn
Pin No.
I/O
I
Active Level
Active Level
Function
A21, B21, E20, AB4
Connect to GND
1.16 I.C. – pull down with resistor
Pin Name
Pin No.
I/O
I/O
Function
IC-PDnR
A18, C17, C19, D15, AD28, AE27, AE28, AE29, AE30,
AF28, AF29, AF30
Connect to GND via
pull-down resistor
1.17 I.C. – pull up
Pin Name
IC-PUp
Pin No.
I/O
I
Active Level
Active Level
Function
U3, V3, W1, W3, AB3, AC1, AK29
Connect to EVDD
1.18 I.C. – pull up with resistor
Pin Name
Pin No.
I/O
I/O
Function
IC-PUpR
A17, B18
Connect to EVDD via
pull-up resistor
15
Data Sheet S15409EJ2V0DS
µPD98502
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
IVDD
Conditions
Internal logic core
I/O buffer
Rating
−0.5 to +3.6
−0.5 to +4.6
−0.5 to +4.6
−0.5 to +4.6
−0.5 to +3.6
30
Unit
V
Supply voltage
EVDD
VI1/VO1
VI2/VO2
VI3/VO3
IO1
V
Input/output voltage
Output current
LVTTL-level pin
V
PCI I/O buffer
V
USB I/O buffer
V
LVTTL-level pin; IOL= 9 mA
PCI I/O buffer
mA
mA
mA
°C
IO2
30
IO3
USB I/O buffer; IOL= 18 mA
55
Storage temperature
Tstg
−65 to +150
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Symbol
IVDD
Conditions
Min.
2.3
3.15
0
Typ.
2.5
Max.
2.7
Unit
V
Supply voltage
EVDD
VIL1
3.3
3.45
0.8
V
Low-level input voltage
High-level input voltage
LVTTL-level pin
V
VIL2
PCI I/O buffer
0
0.3EVDD
0.8
V
VIL3
USB I/O buffer, refer to (10)
V
USB interface parameters
(Single-end operation)
LVTTL-level pin
VIH1
VIH2
VIH3
2.0
0.5EVDD
2.0
V
V
V
PCI I/O buffer
EVDD
USB I/O buffer, refer to (10)
USB interface parameters
(Single-end operation)
USB differential input voltage
Operating ambient temperature
VIDF
USB I/O buffer, refer to (10)
0.2
0
V
USB interface parameters
(Differential operation)
TA
70
°C
16
Data Sheet S15409EJ2V0DS
µPD98502
DC Characteristics (IVDD = 2.5 0.2 Vꢀ EVDD = 3.3 0.15 VꢀTA = 0 to +70°C)
Parameter
Symbol
IIDD
Conditions
Min.
Typ.
Max.
1310
132
Unit
mA
mA
µA
µA
V
Supply current
EIDD
ILI
Input leakage current
Off state output current
Low-level output voltage
VI = EVDD or GND
10
IOZ
VO = VDD or GND
10
VOL1
VOL2
VOL3
LVTTL-level pin; IOL = 9 mA
PCI I/O buffer
0.4
0.1EVDD
0.3
V
USB I/O buffer, refer to (10)
V
USB interface parameters
High-level output voltage
VOH1
VOH2
VOH3
LVTTL-level pin; IOL = 9 mA
PCI I/O buffer
2.4
0.1EVDD
2.8
V
V
V
USB I/O buffer, refer to (10)
EVDD
USB interface parameters
Capacitance (TA = 25°C, VDD = 0 V)
Parameter
Input Capacitance
Symbol
Conditions
fC = 1 MHz,
Min.
4
Typ.
Max.
Unit
pF
CI
8
8
8
Output Capacitance
I/O Capacitance
CO
CIO
Unmeasured pins returned to
0 V
4
pF
4
pF
17
Data Sheet S15409EJ2V0DS
µPD98502
Pin Classifications
Input pins
Type
Pin Names
Number of Pins
LVTTL-level pin
VI1, VIL1/VIH1
SCLK, CLKSL, PSMD, PSTBY, PUMD, PUSTBY, BIG,
ENDCEN, EXINT_B, EXNMI_B, RMSL[1:0], SMD[31:0],
UMINT_B, UMRDY_B, UMD[15:0], UDRCLV, UDRSC,
UDRD[7:0], UDTCLV, USBCLK, URCLK, URSDI, MWDI,
URCTS_B, URDCD_B, URDSR_B, JCK, JDI, JMS,
JRSTB_B, MIRCLK, MIMD, MICOL, MICRS, MIRDV,
MIRER, MIRD[3:0], MITCLK, MI2RCLK, MI2MD,
MI2COL, MI2CRS, MI2RDV, MI2RER, MI2RD[3:0],
MI2TCLK
106
PCI I/O buffer
VI2, VIL2/VIH2
PARBN, PMODE, PSERI_B, PHINT_B, PRQI[3:0]_B,
PAD[31:0], PCBE[3:0]_B, PFRA_B, PDSEL_B, PTRY_B,
PIRY_B, PSTP_B, PAR, PER_B, PIDSEL, RST_B,
PGTI_B, PSCLK
55
2
USB I/O buffer
VI3, VIL3/VIH3, VIDF
USBDP, USBDM
Output pins
Type
Pin Names
Number of Pins
150
LVTTL-level pins
IO1
VO1, VOL1/VOH1
SDCLK0, SDCLK1, SDCKE0, SDCKE1, SDCS_B,
SDRAS_B, SDCAS_B, SDWE_B, SRMCS_B,
SRMOE_B, SMA[20:0], SMD[31:0], UMMD, UMRD_B,
UMRST_B, UMSL_B, UMWR_B, UMAD[11:0],
UMD[15:0], UDRCLK, UDRE_B, UDRAD[4:0], UDTCLK,
UDTE_B, UDTSC, UDTAD[4:0], UDTD[7:0], URSDO,
URDTR_B, URRTS_B, MWSK, MWCS, MWDO,
POM[7:0], JDO, MIMCLK, MIMD, MITE, MITER,
MITD[3:0], MI2MCLK, MI2MD, MI2TE, MI2TER,
MI2TD[3:0]
PCI I/O buffer
USB I/O buffer
IO2
VO2, VOL2/VOH2
PRSTO_B, PGTO[3:0]_B, PAD[31:0], PCBE[3:0]_B,
PFRA_B, PDSEL_B, PTRY_B, PIRY_B, PSTP_B, PAR,
PER_B, PINT_B, PSERO_B, PME_B, PRQO_B
52
2
IO3
VO3, VOL3/VOH3
USBDP, USBDM
18
Data Sheet S15409EJ2V0DS
µPD98502
AC Characteristics (IVDD = 2.5 0.2 Vꢀ EVDD = 3.3 0.15 Vꢀ TA = 0 to +70°C)
(1) AC test waveform
Input signal
0.5EVDD
Test points
0.5EVDD
Ouput signal
0.5EVDD
Test points
0.5EVDD
(2) Clock parameters
Clock timing (except PCI clock)
Clock Cycle
Clock High Width
Clock Low Width
Clock input parameters (except PCI clock)
Parameter
SCLK input cycle
Symbol
tCYSCK
Conditions
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30.00
33.00
SCLK input high width
SCLK input low width
MITCLK input cycle
tWHSCK
tWLSCK
tCYMTK
tWHMTK
tWLMTK
tCYMRK
tWHMRK
tWLMRK
tCY2TK
tWH2TK
tWL2TK
tCY2RK
tWH2RK
tWL2RK
tCYUBK
tWHUBK
tWLUBK
tCYJCK
tWHJCK
tWLJCK
0.4 × tCYSCK
0.4 × tCYSCK
40.00
0.6 × tCYSCK
0.6 × tCYSCK
400.00
MITCLK input high width
MITCLK input low width
MIRCLK input cycle
0.4 × tCYMTK
0.4 × tCYMTK
40.00
0.6 × tCYMTK
0.6 × tCYMTK
400.00
MIRCLK input high width
MIRCLK input low width
MI2TCLK input cycle
MI2TCLK input high width
MI2TCLK input low width
MI2RCLK input cycle
MI2RCLK input high width
MI2RCLK input low width
USBCLK input cycle
0.4 × tCYMRK
0.4 × tCYMRK
40.00
0.6 × tCYMRK
0.6 × tCYMRK
400.00
0.4 × tCY2TK
0.4 × tCY2TK
40.00
0.6 × tCY2TK
0.6 × tCY2TK
400.00
0.4 × tCY2RK
0.4 × tCY2RK
83.1
0.6 × tCY2RK
0.6 × tCY2RK
84.6
USBCLK input high width
USBCLK input low width
JCK input cycle
0.4 × tCYUBK
0.4 × tCYUBK
150.00
0.6 × tCYUBK
0.6 × tCYUBK
1000.00
JCK input high width
JCK input low width
0.4 × tCYJCK
0.4 × tCYJCK
0.6 × tCYJCK
0.6 × tCYJCK
19
Data Sheet S15409EJ2V0DS
µPD98502
Clock timing (PCI clock)
Clock Cycle
Clock High Width
0.5VDD
Clock Low Width
0.4VDD
0.3VDD
Clock input parameters (PCI clock)
Parameter
PSCLK input cycle
Symbol
Conditions
Min.
Max.
Unit
ns
tCYpCK
tWHpCK
tWLpCK
30.00
60.00
PSCLK input high width
PSCLK input low width
0.4 × tCYSCK
0.4 × tCYSCK
ns
ns
Clock output parameters
Parameter
SDCLK0 output cycle
Symbol
tCYSK0
Conditions
Load 50 pF
Min.
Max.
Unit
ns
10.00
15.00
SDCLK0 output high width
SDCLK0 output low width
SDCLK1 output cycle
tWHSK0
tWLSK0
tCYSK1
tWHSK1
tWLSK1
tCYUTK
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
0.4 × tCYSK0
0.4 × tCYSK0
10.00
0.6 × tCYSK0
0.6 × tCYSK0
15.00
ns
ns
ns
ns
ns
ns
SDCLK1 output high width
SDCLK1 output low width
UDTCLK output cycle
0.4 × tCYSK1
0.4 × tCYSK1
0.6 × tCYSK1
0.6 × tCYSK1
30.00/40.00/
60.00
UDTCLK output high width
UDTCLK output low width
UDRCLK output cycle
tWHUTK
tWLUTK
tCYURK
Load 50 pF
Load 50 pF
Load 50 pF
0.4 × tCYUTK
0.4 × tCYUTK
ns
ns
ns
30.00/40.00/
60.00
UDRCLK output high width
UDRCLK output low width
MIMCLK output cycle
tWHURK
tWLURK
tCYMCK
tWHMCK
tWLMCK
tCYM2K
tWHM2K
tWLM2K
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
0.4 × tCYURK
0.4 × tCYURK
420.00
ns
ns
ns
ns
ns
ns
ns
ns
MIMCLK output high width
MIMCLK output low width
MI2MCLK output cycle
0.4 × tCYMCK
0.4 × tCYMCK
420.00
MI2MCLK output high width
MI2MCLK output low width
0.4 × tCYM2K
0.4 × tCYM2K
20
Data Sheet S15409EJ2V0DS
µPD98502
(3) Reset, PLL parameters
IVDD, EVDD
PSTBY (System PLL),
PUSTBY (USB PLL)
tWHPSY, tWHUSY
SCLK
(System Clock)
External OSC
Unstable Period
Internal PLL OSC
tWLPLK, tWLULK
Stable Period
RST_B
(System Reset)
tWLRSB
Parameter
Symbol
tWLRSB
Conditions
Min.
240
Max.
4000 Note
Unit
ns
RST_B Input Low Level Width
PSTBY Hold High Level Width
PSTBY Lookup Time
tWHPSY
tWLPLK
tWHUSY
tWLULK
1
µs
µs
µs
µs
Load 50 pF
1000
PUSTBY Hold High Level Width
PUSTBY Lookup Time
1
Load 50 pF
1000
Note If RST_B is applied longer, operation of the µPD98502 will start anyhow. Therefore it shall be made sure, that
other logic is also out of RESET state after 4 µs, even if RST_B is applied for longer period.
21
Data Sheet S15409EJ2V0DS
µPD98502
(4) Interrupt interface parameters
tWLEIN , tWLENM
EXINT_B,
EXNMI_B
(input)
Parameter
EXINT_B input low width
EXNMI_B input low width
Symbol
tWLEIN
tWLENM
Conditions
Min.
Max.
Unit
ns
4 × tCYSK0/1
4 × tCYSK0/1
ns
22
Data Sheet S15409EJ2V0DS
µPD98502
(5) Memory interface parameters
(a) SDCLK0 memory interface parameters
SDCLK0
(output)
tDSE0SK0
tDSE0SK0
SDCKE0
(output)
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
SDCS_B
(output)
SDRAS_B
(output)
SDCAS_B
(output)
SDWE_B
(output)
tDSMASK0
tDSMASK0
SMA[20:0]
(output)
tDSMDSK0
tDSMDSK0
tDSMDSK0
Hi-Z
Hi-Z
Hi-Z
SMD[31:0]
(output)
tASMDSK0
tFSMDSK0
tSSMDSK0 tHSMDSK0
Hi-Z
SMD[31:0]
(input)
Parameter
Symbol
tDSE0SK0
tDSCSSK0
tDSRASK0
tDSCASK0
tDSWESK0
tDSMASK0
Conditions
Load 50 pF
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
8.0
8.0
8.0
8.0
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SDCKE0 output delay from SDCLK0
SDCS_B output delay from SDCLK0
SDRAS_B output delay from SDCLK0
SDCAS_B output delay from SDCLK0
SDWE_B output delay from SDCLK0
SMA[20:0] output delay from SDCLK0
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
SMD[31:0] output floating to active delay from SDCLK0 tASMDSK0
SMD[31:0] output delay from SDCLK0 tDSMDSK0
SMD[31:0] output active to floating delay from SDCLK0 tFSMDSK0
8.0
8.0
SMD[31:0] input setup to SDCLK0
SMD[31:0] input hold from SDCLK0
tSSMDSK0
tHSMDSK0
4.0
1.00
23
Data Sheet S15409EJ2V0DS
µPD98502
(b) SDCLK1 memory interface parameters
SDCLK1
(output)
tDSE1SK1
tDSE0SK1
SDCKE1
(output)
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
SDCS_B
(output)
SDRAS_B
(output)
SDCAS_B
(output)
SDWE_B
(output)
tDSMASK1
tDSMASK1
SMA[20:0]
(output)
tDSMDSK1
tDSMDSK1
tDSMDSK1
Hi-Z
SMD[31:0]
(output)
Hi-Z
Hi-Z
tASMDSK1
tFSMDSK1
tSSMDSK1 tHSMDSK1
Hi-Z
SMD[31:0]
(input)
Parameter
Symbol
tDSE1SK1
tDSCSSK1
tDSRASK1
tDSCASK1
tDSWESK1
tDSMASK1
tASMDSK1
Conditions
Load 50 pF
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
8.0
8.0
8.0
8.0
8.0
8.0
Unit
SDCKE1 output delay from SDCLK1
SDCS_B output delay from SDCLK1
SDRAS_B output delay from SDCLK1
SDCAS_B output delay from SDCLK1
SDWE_B output delay from SDCLK1
SMA[20:0] output delay from SDCLK1
ns
ns
ns
ns
ns
ns
ns
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
SMD[31:0] output floating to active delay from
SDCLK1
SMD[31:0] output delay from SDCLK1
tDSMDSK1
tFSMDSK1
Load 50 pF
Load 50 pF
1.0
8.0
8.0
ns
ns
SMD[31:0] output active to floating delay from
SDCLK1
SMD[31:0] input setup to SDCLK1
SMD[31:0] input hold from SDCLK1
tSSMDSK1
tHSMDSK1
4.0
1.0
ns
ns
24
Data Sheet S15409EJ2V0DS
µPD98502
(6) Flash ROM interface parameters
(a) Flash ROM interface read cycle parameters
tSSMAROE
tHSMAROE
SMA[20:0]
(output)
tSRCSROE
tHRCSROE
SRMCS_B
(output)
tSSWEROE
tHSWEROE
SDWE_B
(output)
tWLROE
tWHROE
SRMOE_B
(output)
tSSMDROE
tHSMDROE
Hi-Z
Hi-Z
SMD[31:0]
(input)
Parameter
SMA[20:0] setup to SRMOE_B
SMA[20:0] hold from SRMOE_B
SRMCS_B setup to SRMOE_B
SRMCS_B hold from SRMOE_B
SDWE_B setup time to SRMOE_B
SDWE_B hold time from SRMOE_B
SRMOE_B low pulse width
Symbol
Conditions
Load 50 pF
Min.
5 × tCYSK0/1 – 8
Max.
tCYSK0/1 – 8
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSSMAROE
tHSMAROE
tSRCSROE
tHRCSROE
tSSWEROE
tHSWEROE
tWLROE
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5 × tCYSK0/1 – 8
2 × tCYSK0/1 – 8
4 × tCYSK0/1 – 8
5 × tCYSK0/1 – 8
1 × tCYSK0/1 – 8
10
SRMOE_B high pulse width
tWHROE
SMD[31:0] setup to SRMOE_B
SMD[31:0] hold from SRMOE_B
tSSMDROE
tHSMDROE
0
25
Data Sheet S15409EJ2V0DS
µPD98502
(b) Flash ROM interface write cycle parameters
tSSMASWE
tSRCSSWE
tWLSWE
tHSMASWE
SMA[20:0]
(output)
tHRCSSWE
SRMCS_B
(output)
tWHSWE
SDWE_B
(output)
tSROESWE
tHROESWE
SRMOE_B
(output)
tSSMDSWE
tHSMDSWE
Hi-Z
Hi-Z
SMD[31:0]
(output)
tASMDSWE
tFSMDSWE
Parameter
SMA[20:0] setup to SDWE_B
SMA[20:0] hold from SDWE_B
SRMCS_B setup to SDWE_B
SRMCS_B hold from SDWE_B
SRMOE_B setup time to SDWE_B
SRMOE_B hold time from SDWE_B
SDWE_B low pulse width
Symbol
Conditions
Load 50 pF
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSSMASWE
tHSMASWE
tSRCSSWE
tHRCSSWE
tSROESWE
tHROESWE
tWLSWE
4 × tCYSK0/1 − 8
2.0
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
4 × tCYSK0/1 − 8
2.0
4 × tCYSK0/1 − 8
2 × tCYSK0/1 − 8
3 × tCYSK0/1 − 8
7 × tCYSK0/1 − 8
4 × tCYSK0/1 − 8
SDWE_B high pulse width
tWHSWE
SMD[31:0] setup to SDWE_B
SMD[31:0] hold from SDWE_B
SMD[31:0] output Hi-Z to valid delay
SMD[31:0] output valid to Hi-Z delay
tSSMDSWE
tHSMDSWE
tASMDSWE
tFSMDSWE
1 × tCYSK0/1 + 8
ns
ns
ns
4 × tCYSK0/1 − 8
1 × tCYSK0/1 + 8
26
Data Sheet S15409EJ2V0DS
µPD98502
(7) PCI interface parameters
Output timing measurement conditions
V_th
V_tl
Clock
Output
V_pcitest
V_pcitest
tDPCIPCK
tDPCIPCK
V_pcitfall
V_pcitrise
tFPCIPCK
tAPCIPCK
3-state output
Input timing measurement conditions
V_th
V_tl
V_th
V_tl
Clock
V_pcitest
tSPCIPCK
tHPCIPCK
Inputs
valid
Input
V_pcitest
V_pcitest
Symbol
Voltage Level
0.6EVDD
Unit
V
V_th
V_tl
0.2EVDD
V
V_pcitest
V_pcitrise
V_pcitfall
0.4EVDD
V
0.285EVDD
0.615EVDD
V
V
Parameter
Symbol
tDPCIPCK
tAPCIPCK
tFPCIPCK
tSPCIPCK
tHPCIPCK
Conditions
Min.
Max.
12
Unit
ns
PCI output delay
PCI active delay
PCI floating delay
PCI setup time
PCI hold time
Load 10 pF
Load 10 pF
Load 10 pF
2
2
ns
28
ns
7
0
ns
ns
27
Data Sheet S15409EJ2V0DS
µPD98502
(8) ATM interface parameters
(a) UTOPIA2 interface parameters
Data transmission parameters
UDTCLK
(output)
tSUTLUTK
tHUTLUTK
UDTCLV
(input)
tDUTAUTK
tDUTDUTK
tDUTEUTK
tDUTSUTK
UDTAD[4:0]
(output)
UDTD[7:0]
(output)
UDTE_B
(output)
UDTSC
(output)
Parameter
UDTCLV setup time
Symbol
Conditions
Min.
8
Max.
Unit
ns
ns
ns
ns
ns
ns
tSUTLUTK
tHUTLUTK
tDUTAUTK
tDUTDUTK
tDUTEUTK
tDUTSUTK
UDTCLV hold time
1
UDTAD[4:0] output delay
UDTD[7:0] output delay
UDTE_B output delay
UDTSC output delay
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
1
15
15
15
15
1
1
1
28
Data Sheet S15409EJ2V0DS
µPD98502
Data reception parameters
UDRCLK
(output)
tSURLURK
tSURDURK
tSURSURK
tHURLURK
UDRCLV
(input)
tDURAURK
UDRAD[4:0]
(output)
tHURDURK
UDRD[7:0]
(input)
tDUREURK
UDRE_B
(output)
tHURSURK
UDRSC
(input)
Parameter
Symbol
Conditions
Min.
8
Max.
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
UDRCLV setup time
UDRCLV hold time
tSURLURK
tHURLURK
tDURAURK
tSURDURK
tHURDURK
tDUREURK
tSURSURK
tHURSURK
1
UDRAD[4:0] output delay
UDRD[7:0] setup time
UDRD[7:0] hold time
UDRE_B output delay
UDRSC setup time
Load 50 pF
Load 50 pF
1
8
1
1
15
8
UDRSC hold time
1
29
Data Sheet S15409EJ2V0DS
µPD98502
(b) UTOPIA management interface parameters
tWLURT
UMRST_B
(output)
tWLUIT
UMINT_B
(input)
Parameter
UMRST_B low pulse width
UMINT_B low pulse width
Symbol
tWLURT
tWLUIT
Conditions
Min.
Max.
Unit
ns
3 × tCYSCK
3 × tCYSCK
ns
30
Data Sheet S15409EJ2V0DS
µPD98502
(c) Intel Mode
Read cycle parameters
tSUMAURD
tHUMAURD
tHUSLURD
tHUWRURD
UMAD[11:0]
(output)
tSUSLURD
UMSL_B
(output)
tSUWRURD
UMWR_B
(output)
tWLURD
UMRD_B
(output)
tSURYURD
tHURYURD
UMRDY_B
(input)
tSUMDURD
tHUMDURD
Hi-Z
Hi-Z
UMD[15:0]
(input)
Parameter
Symbol
tSUMAURD
tHUMAURD
tSUSLURD
tHUSLURD
tSUWRURD
tHUWRURD
tWLURD
Conditions
Load 50 pF
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to UMRD_B
UMAD[11:0] hold from UMRD_B
UMSL_B setup to UMRD_B
UMSL_B hold from UMRD_B
UMWR_B setup to UMRD_B
UMWR_B hold from UMRD_B
UMRD_B low pulse width
10
4
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
0
50
25
10
10
15
UMRDY_B setup to UMRD_B
UMRDY_B hold from UMRD_B
UMD[15:0] setup to UMRD_B
UMD[15:0] hold from UMRD_B
tSURYURD
tHURYURD
tSUMDURD
tHUMDURD
31
Data Sheet S15409EJ2V0DS
µPD98502
Write cycle parameters
tSUMAUWR
tHUMAUWR
UMAD[11:0]
(output)
tSUSLUWR
tHUSLUWR
UMSL_B
(output)
tWLUWR
UMWR_B
(output)
tSURDUWR
tHURDUWR
UMRD_B
(output)
tSURYUWR
tHURYUWR
UMRDY_B
(input)
tSUMDUWR
tHUMDUWR
Hi-Z
Hi-Z
UMD[15:0]
(output)
tAUMDUWR
tFUMDUWR
Parameter
Symbol
tSUMAUWR
tHUMAUWR
tSUSLUWR
tHUSLUWR
tSURDUWR
tHURDUWR
tWLUWR
Conditions
Min.
10
4
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to UMWR_B
UMAD[11:0] hold from UMWR_B
UMSL_B setup to UMWR_B
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
UMSL_B hold from UMWR_B
UMRD_B setup to UMWR_B
UMRD_B hold from UMWR_B
UMWR_B low pulse width
0
5
0
50
25
10
15
4
UMRDY_B setup to UMWR_B
UMRDY_B hold from UMWR_B
UMD[15:0] setup to UMWR_B
UMD[15:0] hold from UMWR_B
UMD[15:0] active time to UMWR_B
UMD[15:0] floating time from UMWR_B
tSURYUWR
tHURYUWR
tSUMDUWR
tHUMDUWR
tAUMDUWR
tFUMDUWR
Load 30 pF
Load 30 pF
15
4
32
Data Sheet S15409EJ2V0DS
µPD98502
(d) Motorola Mode
Read cycle parameters
tSUMADSR
tHUMADSR
tHUSLDSR
tHRWDSR
UMAD[11:0]
(output)
tSUSLDSR
UMSL_B
(output)
tSRWDSR
UMWR_B
(as R/W : output)
tWLDSR
UMRD_B
(as DS : output)
tSDAKDSR
tHDAKDSR
UMRDY_B
(as DACK : input)
tSUMDDSR
tHUMDDSR
Hi-Z
Hi-Z
UMD[15:0]
(input)
Parameter
Symbol
tSUMADSR
tHUMADSR
tSUSLDSR
tHUSLDSR
tSRWDSR
tHRWDSR
tWLDSR
Conditions
Load 50 pF
Min.
10
4
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to DS
UMAD[11:0] hold from DS
UMSL_B setup to DS
UMSL_B hold from DS
R/W setup to DS
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
R/W hold from DS
0
DS low pulse width
50
25
10
10
15
DACK setup to DS
tSDAKDSR
tHDAKDSR
tSUMDDSR
tHUMDDSR
DACK hold from DS
UMD[15:0] setup to DS
UMD[15:0] hold from DS
33
Data Sheet S15409EJ2V0DS
µPD98502
Write cycle parameters
tSUMADSW
tHUMADSW
tHUSLDSW
tHRWDSW
UMAD[11:0]
(output)
tSUSLDSW
UMSL_B
(output)
tSRWDSW
UMWR_B
(as R/W : output)
tWLDSW
UMRD_B
(as DS: output)
tSDAKDSW
tHDAKDSW
UMRDY_B
(as DACK: input)
tSUMDDSW
tHUMDDSW
Hi-Z
Hi-Z
UMD[15:0]
(output)
tAUMDDSW
tFUMDDSW
Parameter
Symbol
tSUMADSW
tHUMADSW
tSUSLDSW
tHUSLDSW
tSRWDSW
tHRWDSW
tWLDSW
Conditions
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UMAD[11:0] setup to DS
UMAD[11:0] hold from DS
UMSL_B setup to DS
UMSL_B hold from DS
R/W setup to DS
Load 50 pF
10
4
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
5
0
5
R/W hold from DS
0
DS low pulse width
50
25
10
15
4
DACK setup to DS
tSDAKDSW
tHDAKDSW
tSUMDDSW
tHUMDDSW
tAUMDDSW
tFUMDDSW
DACK hold from DS
UMD[15:0] setup to DS
UMD[15:0] hold from DS
UMD[15:0] active time to DS
UMD[15:0] floating time from DS
Load 30 pF
Load 30 pF
15
4
34
Data Sheet S15409EJ2V0DS
µPD98502
(9) Ethernet interface parameters
(a) Ethernet interface 1
MII data transmission parameters
MITCLK
(input)
tDMTEMTK
tDMTEMTK
MITE
(output)
tDMTDMTK
tDMTDMTK
MITD[3:0]
(output)
tDMTRMTK
tDMTRMTK
MITER
(output)
Parameter
Symbol
tDMTEMTK
Conditions
Min.
0
Max.
Unit
ns
20 Note
20 Note
20 Note
MITE output delay
Load 50 pF
Load 50 pF
Load 50 pF
MITD[3:0] output delay
MITER output delay
tDMTDMTK
tDMTRMTK
0
0
ns
ns
Note In the MII specification, maximum output delay is specified as 25 ns.
35
Data Sheet S15409EJ2V0DS
µPD98502
MII data reception parameters
MIRCLK
(input)
tSMRVMRK
tHMRVMRK
MIRDV
(input)
tSMRDMRK
tHMRDMRK
MIRD[3:0]
(input)
tSMRRMRK
tHMRRMRK
MIRER
(input)
Parameter
Symbol
tSMRVMRK
tHMRVMRK
tSMRDMRK
tHMRDMRK
tSMRRMRK
tHMRRMRK
Conditions
Min.
10
Max.
Unit
ns
ns
ns
ns
ns
ns
MIRDV setup time
MIRDV hold time
10
MIRD[3:0] setup time
MIRD[3:0] hold time
MIRER setup time
MIRER hold time
10
10
10
10
MII interface signal parameters
tWHMCL
MICOL
(input)
tWHMCS
MICRS
(input)
Parameter
MICOL high pulse width
MICRS high pulse width
Symbol
tWHMCL
Conditions
Min.
Max.
Unit
ns
2 × tCYMTK
2 × tCYMTK
tWHMCS
ns
36
Data Sheet S15409EJ2V0DS
µPD98502
MII management interface parameters
MIMCLK
(output)
tSMMDMCK tHMMDMCK
MIMD
(input)
tAMMDMCK
tDMMDMCK
tFMMDMCK
Hi-Z
Hi-Z
MIMD
(output)
Parameter
MIMD setup to MIMCLK
Symbol
tSMMDMCK
tHMMDMCK
tAMMDMCK
tDMMDMCK
tFMMDMCK
Conditions
Min.
20
0
Max.
30
Unit
ns
MIMD hold from MIMCLK
ns
MIMD active delay from MIMCLK
MIMD output delay from MIMCLK
MIMD floating delay from MIMCLK
Load 50 pF
Load 50 pF
Load 50 pF
10
10
10
ns
ns
ns
37
Data Sheet S15409EJ2V0DS
µPD98502
(b) Ethernet Interface 2
MII data transmission parameters
MI2TCLK
(input)
tD2TE2TK
tD2TE2TK
MI2TE
(output)
tD2TD2TK
tD2TD2TK
MI2TD[3:0]
(output)
tD2TR2TK
tD2TR2TK
MI2TER
(output)
Parameter
Symbol
tD2TE2TK
Conditions
Min.
0
Max.
Unit
ns
20 Note
20 Note
20 Note
MI2TE output delay
Load 50 pF
Load 50 pF
Load 50 pF
MI2TD[3:0] output delay
MI2TER output delay
tD2TD2TK
tD2TR2TK
0
0
ns
ns
Note In the MII specification, maximum output delay is specified as 25 ns.
38
Data Sheet S15409EJ2V0DS
µPD98502
MII data reception parameters
MI2RCLK
(input)
tS2RV2RK
tH2RV2RK
MI2RDV
(input)
tS2RD2RK
tH2RD2RK
MI2RD[3:0]
(input)
tS2RR2RK
tH2RR2RK
MI2RER
(input)
Parameter
Symbol
tS2RV2RK
tH2RV2RK
tS2RD2RK
tH2RD2RK
tS2RR2RK
tH2RR2RK
Conditions
Min.
10
Max.
Unit
ns
ns
ns
ns
ns
ns
MI2RDV setup time
MI2RDV hold time
10
MI2RD[3:0] setup time
MI2RD[3:0] hold time
MI2RER setup time
MI2RER hold time
10
10
10
10
MII interface signal parameters
tWH2CL
MI2COL
(input)
tWH2CS
MI2CRS
(input)
Parameter
MI2COL high pulse width
MI2CRS high pulse width
Symbol
tWH2CL
Conditions
Min.
Max.
Unit
ns
2 × tCY2TK
2 × tCY2TK
tWH2CS
ns
39
Data Sheet S15409EJ2V0DS
µPD98502
MII management interface parameters
MI2MCLK
(output)
tS2MD2CK tH2MD2CK
MI2MD
(input)
tA2MD2CK
tD2MD2CK
tF2MD2CK
Hi-Z
Hi-Z
MI2MD
(output)
Parameter
MI2MD setup to MI2MCLK
Symbol
tS2MD2CK
tH2MD2CK
tA2MD2CK
tD2MD2CK
tF2MD2CK
Conditions
Min.
20
0
Max.
Unit
ns
MI2MD hold from MI2MCLK
ns
MI2MD active delay from MI2MCLK
MI2MD output delay from MI2MCLK
MI2MD floating delay from MI2MCLK
Load 50 pF
Load 50 pF
Load 50 pF
10
10
10
ns
30
ns
ns
40
Data Sheet S15409EJ2V0DS
µPD98502
(10) USB interface parameters
External circuitry
The USB line I/O signals (refer to chapter 1.9 USB interface) need 4 external resistors to adjust the output
impedance (R1 and R2 = 22 Ω each), to code the full speed USB mode (R3 = 1.5 kΩ) and to protect the output driver
of the USBDM pin (R4 = 51 kΩ).The following figure shows a typical connection diagram.
R3
EVDD = 3.3 V
µPD98502
R1
R2
USBDP
to USB Connector
USBDM
GND
R4
Data signal rise and fall time
Rise time
Fall time
90%
90%
CL
CL
Differential
Data Lines
10%
10%
tR
tF
Differential data jitter
tPERIOD = 1/tDRATE
Crossover points
Differential
Data Lines
Next transitions
tDJ1
n x tPERIOD + tJR1
Paired transitions
tDJ2
(n+1) x tPERIOD + tJR1
Differential-to-EOP transition skew and EOP width
tPERIOD = 1/tDRATE
Crossover
points extended
Crossover point
Differential
Data Lines
n x tPERIOD + tDEOP
tEOPT, tEOPR
41
Data Sheet S15409EJ2V0DS
µPD98502
Differential transition interval width
tPERIOD = 1/tDRATE
Differential
Data Lines
VIL
tFST
Receiver jitter tolerance
tPERIOD = 1/tDRATE
Differential
Data Lines
tJR1
tJR2
Next transitions
n x tPERIOD + tJR1
Paired transitions
(n+1) x tPERIOD + tJR2
USB interface parameters (USBDM and USBDP)
Parameter
Symbol
Conditions
Min.
1
Max.
20
Unit
ns
Rise time
Fall time
tR
tF
1
20
ns
Differential rise and fall time matching
Full-speed data rate
tFRFM
tDRATE
tR/tF
90
111.11
12.03
%
11.97
Mbps
Source jitter total (including frequency tolerance):
To next transition
tDJ1
−3.5
−4
+3.5
+4
ns
ns
ns
For paired transitions
tDJ2
Source jitter for differential transition to SE0
transition
tDEOP
−2
+5
Receiver jitter:
To next transition
tJR1
−18.5
−9
+18.5
+9
ns
ns
ns
ns
ns
For paired transitions
tJR2
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential transition
tEOPT
tEOPR
tFST
160
82
175
14
42
Data Sheet S15409EJ2V0DS
µPD98502
(11) Parallel port interface parameters
SDCLK0
tDPOM
POM[7:0]
(output)
Parameter
Symbol
Conditions
Load 50 pF
Min.
0.0
Max.
8.0
Unit
ns
POM[7:0] output delay
tDPOM
43
Data Sheet S15409EJ2V0DS
µPD98502
(12) UART interface parameters
T
BAUDOUT
(internal)
tWLUDO
START
URSDO
(output)
DATA(5-8) PARITY STOP START
tWLUDI
START
URSDI
(input)
DATA(5-8)
PARITY STOP START
Remark The BAUDOUT is equal to the 16X of transmisson baud rate (1/T = 16 × Baud Rate). Customize Baud
Rates can be achieved by selecting proper divisor values for MSB and LSB of baud rate generator.
Parameter
URCLK input frequency
Symbol
tCYUCK
tWLUDO
tWLUDI
Conditions
Min.
Max.
Unit
MHz
ns
18.432
URSDO low level width
URSDI low level width
16 × T
16 × T
ns
44
Data Sheet S15409EJ2V0DS
µPD98502
(13) Micro Wire interface parameters
tWHWSK
tWLWSK
tCYWSK
MWSK
(output)
tSWSKWCS
tSWCSWSK
tHWCSWSK
MWCS
(output)
tAWDOWSK
tDWDOWSK
tDWDOWSK
tFWDOWSK
MWDO
(output)
tSWDIWSK tHWDIWSK
Hi-Z
MWDI (Read)
(input)
Hi-Z
Hi-Z
tAWDIWSK
tFWDIWSK
Hi-Z
MWDI (Status)
(input)
Parameter
MWSK clock frequency
MWSK high time
Symbol
tCYWSK
Conditions
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load 50 pF
400 × tCYSK0
190 × tCYSK0
190 × tCYSK0
90 × tCYSK0
90 × tCYSK0
90 × tCYSK0
190 × tCYSK0
190 × tCYSK0
190 × tCYSK0
10 × tCYSK0
10 × tCYSK0
tWHWSK
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
Load 50 pF
MWSK low time
tWLWSK
MWSK setup to MWCS
MWCS setup to MWSK
MWCS hold from MWSK
tSWSKWCS
tSWCSWSK
tHWCSWSK
MWDO output active to floating delay from MWSK tAWDOWSK
MWDO output delay from MWSK tDWDOWSK
MWDO output floating to active delay from MWSK tFWDOWSK
MWDI setup to MWSK
tSWDIWSK
tHWDIWSK
tAWDIWSK
tFWDIWSK
MWDI hold from MWSK
MWCS to status time from MWSK
MWCS to MWDO in 3-state
100 × tCYSK0
40 × tCYSK0
45
Data Sheet S15409EJ2V0DS
µPD98502
(14) JTAG boundary scan parameters
JCK
(input)
tSJMS
tHJMS
JMS
(input)
tSJDI
tHJDI
JDI
(input)
tDJDO
tDJDO
JDO
(output)
tWLJRT
JRSTB_B
(input)
Parameter
JMS setup time
Symbol
Conditions
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
tSJMS
tHJMS
tSJDI
5
10
5
JMS hold time
JDI setup time
JDI hold rime
tHJDI
12
JDO output delay
JRSTB_B low pulse width
tDJDO
tWLJRT
Load 50 pF
30
5 × tCYJCK
46
Data Sheet S15409EJ2V0DS
µPD98502
3. PACKAGE DRAWING
500-PIN TAPE BGA (HEAT SPREADER TYPE) (40x40)
A
A1
A
B
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Q
R
S
T
B W
D
A2
8
7
5
3
6
4
2
1
AJ AG AE AC AA W U R N L J G E C A
AK AH AF AD AB Y V T P M K H F D B
X
C
Index area
A
Y
J
H
B
G
S
ITEM MILLIMETERS
A
A
A
40.00 0.20
23.00 MAX.
23.00 MAX.
1
2
F
E
B
C
D
E
F
39.60 0.15
39.60 0.15
40.00 0.20
1.585
M
L
φ
M
P
S
S
A B
M
φ
1.27 (T.P.)
0.60 0.10
detail of B part
detail of A part
(Z)
G
+0.20
0.80
H
J
−0.10
+0.30
1.40
−0.20
K
S
K
L
0.15
φ
0.75 0.15
N
M
N
P
Q
R
S
T
0.30
0.25 MIN.
0.10
3.0
2.0
2.0
3.0
W
X
Y
Z
22.73
22.73
C 0.40
0.20
S500N7-127-H6-1
47
Data Sheet S15409EJ2V0DS
µPD98502
4. RECOMMENDED SOLDERING CONDITIONS
The µPD98502 should be soldered and mounted under the following recommended conditions. For the details of
the recommended soldering conditions, refer to the document Semiconductor Device MountingTechnology
Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC
sales representative.
Table 4-1. Surface Mounting Type Soldering Conditions
µPD98502N7-H6:
500-pin tape BGA (Heat spreader type) (40 × 40)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),
Count: three times or less, Exposure limit: 7 days Note (after that, prebake at 125°C
IR35-107-3
for 10 hours)
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),
VP15-107-3
Count: three times or less, Exposure limit: 7 days Note (after that, prebake at 125°C
for 10 hours)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
48
Data Sheet S15409EJ2V0DS
µPD98502
[MEMO]
49
Data Sheet S15409EJ2V0DS
µPD98502
[MEMO]
50
Data Sheet S15409EJ2V0DS
µPD98502
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
51
Data Sheet S15409EJ2V0DS
µPD98502
VR4120A is a trademark of NEC Corporation.
Micro Wire is a trademark of National Semiconductor Corp.
Ethernet is a trademark of Xerox Corp.
MIPS is a trademark of MIPS Technologies, Inc.
•
The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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