UPG506B [NEC]

14 GHz DIVIDE-BY-8 DYNAMIC PRESCALER; 14 GHz的分频8动态预分频器


型号：	UPG506B
厂家：	NEC
描述：	14 GHz DIVIDE-BY-8 DYNAMIC PRESCALER 14 GHz的分频8动态预分频器预分频器多谐振动器 CD 时钟
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14 GHz DIVIDE-BY-8

DYNAMIC PRESCALER

UPG506B

FEATURES

INPUT POWER vs. INPUT FREQUENCY

• WIDE OPERATING FREQUENCY RANGE:

A=-25°C

f = 8 to 14 GHz (TA = 25°C)

to +75°C

• LOW PHASE NOISE

Recommended

Operating

Region

• GUARANTEED OPERATING TEMPERATURE RANGE

(TA = -25°C to +75°C)

TA=+25°C

DD = 3.8V

SS1=0V

SS2=-2.2V

DESCRIPTION

= -25°C

= +25°C

= +75°C

The UPG506B is a GaAs divide-by-8 prescaler capable of

operating up to 14 GHz. It is designed for use in frequency

synthesizers of microwave communication systems and

measurement equipment. The UPG506B is a dynamic fre-

quency divider and employs BFL (Buffered FET Logic) cir-

cuits. The UPG506B is available in a hermetic 8-lead ceramic

flat package.

-10

Input Frequency, f (GHz)

ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V)

PART NUMBER

PACKAGE OUTLINE

UPG506B

BF08

SYMBOLS

IDD

PARAMETERS AND CONDITIONS

SupplyCurrent

UNITS

MIN

TYP

105

MAX

140

ISS1

Sink Current¹ISS1 = IDD - ISS2

ISS2

Sink Current¹

fIN(U)

Upper Limit of Input Frequency at PIN = +6 dBm

Lower Limit of Input Frequency at PIN = +6 dBm

Input Power at f = 9 to 13 GHz

GHz

dBm

°C/W

fIN(L)

2.0

10.0

POUT

RTH(CH-C)

Output Power at fIN = 14 GHz

2.0

Thermal Resistance (Channel to Case)

10.0

Note:

1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins.

California Eastern Laboratories

UPG506B

ELECTRICAL CHARACTERISTICS (TA = -25°C to +75°C, VDD = +3.8 V, VSS1 = 0 V, VSS2 = -2.2 V)

PART NUMBER

PACKAGE OUTLINE

UPG506B

BF08

SYMBOLS

IDD

PARAMETERS AND CONDITIONS

SupplyCurrent

UNITS

MIN

TYP

105

MAX

ISS1

Sink Current¹ISS1 = IDD - ISS2

ISS2

Sink Current¹

fIN(U)

fIN(L)

Upper Limit of Input Frequency at PIN = +6 dBm

Lower Limit of Input Frequency at PIN = +6 dBm

Input Power at f = 9 to 13 GHz

Output Power at fIN = 14 GHz

GHz

dBm

13.2

8.2

2.0

10.0

POUT

-1.0

1.0

Note:

1. Current is positive into the IDD pin and returns through the ISS1 and ISS2 pins.

ABSOLUTE MAXIMUM RATINGS¹(TA = 25°C)

POWER DERATING CURVES

SYMBOLS

VDD - VSS1

VSS2 - VSS1

PARAMETERS

UNITS

RATINGS

2.5

2.0

1.5

1.0

0.5

SupplyVoltage

SupplyCurrent

-5

1.5

Total Power Dissipation²

Input Power Level

CaseTemperature

dBm

°C

-65 to +125

TSTG

StorageTemperature

°C

-65 to +175

Notes:

TCASE MAX = 125°C

1. Operation in excess of any one of these conditions may result in

permanent damage.

2. TC ≤ 125˚C.

100 110

150

200

250

Case Temperature, TC (°C)

TYPICAL PERFORMANCE CURVES (TA = 25°C)

SSB PHASE NOISE vs. OFFSET FROM CARRIER

fIN = 12.7 GHz

OUTPUT POWER vs. INPUT FREQUENCY

2.5

-70

-80

-90

PIN = +10dBm

2.0

-100

-110

-120

1.5

1.0

= -25°C

= +25°C

= +75°C

-130

+25°C

-140

0.5

+75°C

-150

-160

10 12

14 16

100

10K

100K

Input Frequency, f (GHz)

Offset from Carrier (Hz)

UPG506B

TEST CIRCUITS

CONFIGURATION 1

2 Bias Supply

Zo = 50 Ω

5 IN

DD 4

(3.8 V)

10 µF

See Note 1

6 VGG1

7 VGG2

8 VSS2

NC 3

OPEN

VSS1 (0 V) GND

SS1 2

OUT

VSS2

OUT 1

(-2.2 V)

Zo = 50 Ω

10 µF

VDD = 3.8 V

VSS1 = 0 V (GND)

VSS2 = –2.2 V

C: 1000 - 5000 pF Chip Capacitor

CONFIGURATION 2

Single Positive Bias Supply

Zo = 50 Ω

VDD 4

5 IN

(+6 V)

10 µF

See Note 1

6 VGG1

7 VGG2

8 VSS2

NC 3

10 µF

OPEN

SS1 2

2.2 V

OUT 1

OUT

GND (0 V) VSS2

Zo = 50 Ω

VDD = +6.0 V

VSS2 = 0 V (GND)

* VSS1 should be connected to GND through a 2.2 V Zener Diode

(RD2.2FB or IN3394).

C: 1000 - 5000 pF Chip Capacitor

CONFIGURATION 3

Single Negative Bias Supply

Zo = 50 Ω

VDD 4

5 IN

See Note 1

NC 3

6 V^GG1

7 VGG2

8 VSS2

10 µF

OPEN

-6 V*

SS1 2

2.2 V

Zo = 50 Ω

(-6 V)

SS2

OUT

OUT 1

10 µF

VDD = 0 V (GND)

VSS2 = –6 V

* For VSS1, the bias voltage of -6.0 should be applied through a 2.2 V

Zener Diode (RD2.2FB or IN3394).

C: 1000 - 5000 pF Chip Capacitor

Notes:

1. Because of the high internal gain and gain compression of the UPG506B, the device is prone to self-oscillation in the absence of an RF input

signal. This self-oscillation can be suppressed by either of the following means:

• Add a shunt resistor to the RF input line. Typically a resistor value between 50 and 1000 ohms will suppress the self-

oscillation (see the test circuit schematic).

• Apply a negative voltage through a 1000 ohm resistor to the normally open VGG1 connection. Typically voltages between 0

and -9 volts will suppress the self-oscillation.

Both of these approaches will reduce the input sensitivity of the device (by as much as 3 dB for a 50 ohm shunt resistor), but otherwise have no

effect on the reliability or electrical characteristics of the device.

UPG506B

OUTLINE DIMENSIONS (Units in mm)

UPG506B

PACKAGE OUTLINE BFO8

7.0±0.5

1.7 MAX

1.27

±0.1

1.27

±0.1

1.27

±0.1

10.4±0.5

2.6

4.4±0.2

0.4

5.0±0.2

+0.05

0.2

-0.02

LEAD CONNECTIONS

1. OUTPUT

2. VSS1

3. NC*

5. INPUT

6. VGG1

7. VGG2

8. VSS2

4. VDD

* No Connection

EXCLUSIVE NORTH AMERICAN AGENT FOR

RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS

CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279

24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM

PRINTED IN USA ON RECYCLED PAPER -4/97

DATA SUBJECT TO CHANGE WITHOUT NOTICE

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