74AHC3GU04DP [NEXPERIA]
Triple unbuffered inverterProduction;
| 型号： | 74AHC3GU04DP |
| 厂家： | 
Nexperia |
| 描述： | Triple unbuffered inverterProduction 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC3GU04
Triple unbuffered inverter
Rev. 6 — 27 February 2019
Product data sheet
1. General description
The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates
with unbuffered outputs.
2. Features and benefits
•
Symmetrical output impedance
•
•
High noise immunity
ESD protection:
•
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
•
•
•
Low power dissipation
Balanced propagation delays
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC3GU04DP
74AHC3GU04DC
-40 °C to +125 °C
TSSOP8 plastic thin shrink small outline package;
8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
-40 °C to +125 °C
VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
4. Marking
Table 2. Marking codes
Type number
Marking code [1]
74AHC3GU04DP
74AHC3GU04DC
AU4
AU4
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Nexperia
74AHC3GU04
Triple unbuffered inverter
5. Functional diagram
1
1
1
3
6
7
5
2
1
3
6
1A
2A
3A
1Y
2Y
3Y
7
5
2
1
A
Y
mna720
mna721
mna045
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram (one gate)
6. Pinning information
6.1. Pinning
74AHC3GU04
1
2
3
4
8
7
6
5
1A
3Y
V
CC
1Y
3A
2Y
2A
GND
001aaj517
Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
6.2. Pin description
Table 3. Pin description
Symbol
1A, 2A, 3A
GND
Pin
1, 3, 6
4
Description
data input
ground (0 V)
data output
supply voltage
1Y, 2Y, 3Y
VCC
7, 5, 2
8
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level
Input
Output
A
L
Y
H
L
H
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74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
2 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-20
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
IIK
input clamping current
output clamping current
output current
VI < -0.5 V
[1]
[1]
mA
mA
mA
mA
mA
°C
IOK
IO
VO < -0.5 V or VO > VCC + 0.5 V
-0.5 V < VO < VCC + 0.5 V
±20
±25
75
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-75
-65
-
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
2.0
0
Typ
Max
5.5
Unit
V
VCC
VI
supply voltage
5.0
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
+25
°C
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
-
-
ns/V
ns/V
-
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
3 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
10. Static characteristics
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
1.7
2.4
4.4
-
Typ
Max
-
Min
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
VI = VIH or VIL
-
-
-
-
-
-
1.7
2.4
4.4
-
-
1.7
2.4
4.4
-
-
V
V
V
V
V
V
-
-
-
-
-
-
VIL
LOW-level
input voltage
0.3
0.6
1.1
0.3
0.6
1.1
0.3
0.6
1.1
-
-
-
-
-
-
VOH
HIGH-level
output voltage
IO = -50 μA; VCC = 2.0 V
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
IO = -50 μA; VCC = 3.0 V
IO = -50 μA; VCC = 4.5 V
IO = -4.0 mA; VCC = 3.0 V
IO = -8.0 mA; VCC = 4.5 V
4.4
4.4
4.4
2.58
3.94
2.48
3.8
2.40
3.70
-
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 50 μA; VCC = 2.0 V
IO = 50 μA; VCC = 3.0 V
IO = 50 μA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
-
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
2.0 μA
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
1.0
10
-
-
10
10
-
-
40
10
μA
pF
input
3.0
capacitance
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74AHC3GU04
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
4 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
10.1. Typical transfer characteristics
mna397
mna398
2.0
V
O
1.0
3.0
10
V
V
O
I
O
CC
I
CC
V
O
(V)
1.6
(mA)
0.8
(mA)
(V)
8
6
4
2
0
1.2
0.8
0.4
0.6
0.4
0.2
0
1.5
I
(drain current)
D
I
(drain current)
D
0
0
0
0
1
2
3
0.4
0.8
1.2
1.6
2.0
V (V)
I
V (V)
I
a. VCC = 2.0 V; IO = 0 A
b. VCC = 3.0 V; IO = 0 A
mna399
6
50
I
CC
V
(mA)
40
O
V
O
(V)
30
20
10
0
3
I
(drain current)
D
4
0
0
2
6
V (V)
I
c. VCC = 5.5 V; IO = 0 A
Fig. 5. Typical transfer characteristic
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74AHC3GU04
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
5 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
mna400
40
g
fs
(mA/V)
30
R
bias
= 560 kΩ
20
10
0
V
CC
0.47 µF
100 µF
input
output
V
I
A
I
O
(f = 1 kHz)
GND
mna050
0
2
4
6
V
(V)
CC
gfs = ΔIO/ΔVI at VO is constant
Fig. 6. Typical forward transconductance gfs as a
function of the supply voltage at Tamb = 25 °C
Fig. 7. Test set-up for measuring forward
transconductance
11. Dynamic characteristics
Table 8. Dynamic characteristics
GND = 0 V; For test circuit see Fig. 9.
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ Max Min Max Min Max
tpd
propagation nA to nY; see Fig. 8
delay
[1]
VCC = 3.0 V to 3.6 V; CL = 15 pF [2]
VCC = 3.0 V to 3.6 V; CL = 50 pF [2]
VCC = 4.5 V to 5.5 V; CL = 15 pF [3]
VCC = 4.5 V to 5.5 V; CL = 50 pF [3]
-
-
-
-
-
3.0
4.3
2.5
3.5
4
7.1
10.6
5.5
7.0
-
1.0
1.0
1.0
1.0
-
8.5
12.0
6.0
8.0
-
1.0
1.0
1.0
1.0
-
10.0 ns
13.5 ns
7.0 ns
9.0 ns
CPD
power
per buffer; VI = GND to VCC
[4]
-
pF
dissipation
capacitance
[1] tpd is the same as tPLH and tPHL
.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
6 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
11.1. Waveforms and test circuit
V
I
V
V
M
nA input
M
GND
t
t
PHL
PLH
V
OH
V
M
V
M
nY output
V
mna344
OL
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 8. The input (nA) to output (nY) propagation delays.
Table 9. Measurement points
Input
VM
Output
VM
0.5VCC
0.5VCC
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 9. Test circuit for measuring switching times
Table 10. Test data
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
tPZH, tPHZ
tPZL, tPLZ
VCC
≤ 3 ns
15 pF, 50 pF
1 kΩ
GND
VCC
©
74AHC3GU04
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
7 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
12. Application information
Some applications are:
•
•
Linear amplifier (see Fig. 10)
In crystal oscillator design (see Fig. 11)
Remark: All values given are typical unless otherwise specified.
R2
V
CC
1 µF
R1
R1
U04
Z
L
R2
U04
C1
C2
mna052
out
Maximum Vo(p-p) = VCC - 1.5 V centered at
0.5 × VCC
.
mna053
C1 = 47 pF (typ.)
C2 = 22 pF (typ.)
Gol = open loop gain
R1 = 1 MΩ to 10 MΩ (typ.)
Gv = voltage gain
R2 optimum value depends on the frequency
and required stability against changes in VCC or
average minimum ICC (ICC is typically 2 mA at
VCC = 3 V and f = 1 MHz).
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ
ZL > 10 kΩ; Gol = 20 (typ.)
Typical unity gain bandwidth product is 5 MHz.
Fig. 10. Used as a linear amplifier
Fig. 11. Crystal oscillator configuration
Table 11. External components for resonator (f < 1 MHz)
All values given are typical and must be used as an initial set-up.
Frequency
R1
R2
C1
C2
10 kHz to 15.9 kHz
16 kHz to 24.9 kHz
25 kHz to 54.9 kHz
55 kHz to 129.9 kHz
130 kHz to 199.9 kHz
200 kHz to 349.9 kHz
350 kHz to 600 kHz
22 MΩ
22 MΩ
22 MΩ
22 MΩ
22 MΩ
22 MΩ
22 MΩ
220 kΩ
220 kΩ
100 kΩ
100 kΩ
47 kΩ
47 kΩ
47 kΩ
56 pF
56 pF
56 pF
47 pF
47 pF
47 pF
47 pF
20 pF
10 pF
10 pF
5 pF
5 pF
5 pF
5 pF
Table 12. Optimum value for R2
Frequency
R2
Optimum for
minimum required ICC
3 kHz
2.0 kΩ
8.0 kΩ
1.0 kΩ
4.7 kΩ
0.5 kΩ
2.0 kΩ
0.5 kΩ
1.0 kΩ
-
minimum influence due to change in VCC
minimum required ICC
6 kHz
minimum influence by VCC
minimum required ICC
10 kHz
14 kHz
>14 kHz
minimum influence by VCC
minimum required ICC
minimum influence by VCC
replace R2 by C3 with a typical value of 35 pF
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
8 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.5
0.2
0.13
0.1
0.25
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig. 12. Package outline SOT505-2 (TSSOP8)
©
74AHC3GU04
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Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
9 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
E
v
A
Z
5
8
Q
A
2
A
A
(A )
3
1
pin 1 index
θ
L
p
detail X
1
4
L
e
w
b
p
0
5 mm
scale
Dimensions (mm are the original dimensions)
A
(1)
(2)
(1)
Unit
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
max
mm nom
min
0.15 0.85
0.00 0.60
0.27 0.23 2.1 2.4
0.17 0.08 1.9 2.2
3.2
3.0
0.40 0.21
0.15 0.19
0.4
8°
0°
1
0.12
0.5
0.4
0.2 0.08 0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
sot765-1_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
07-06-02
16-05-31
SOT765-1
MO-187
Fig. 13. Package outline SOT765-1 (VSSOP8)
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
10 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
14. Abbreviations
Table 13. Abbreviations
Acronym
Description
CDM
CMOS
DUT
ESD
HBM
MM
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
15. Revision history
Table 14. Revision history
Document ID
74AHC3GU04 v.6
Modifications:
Release date
20190227
Data sheet status
Change notice Supersedes
- 74AHC3GU04 v.5
Product data sheet
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74AHC3GU04GD (SOT996-2) removed.
Package outline drawing SOT765-1 (VSSOP8) updated
74AHC3GU04 v.5
Modifications:
20130508
For type number 74AHC3GU04GD XSON8U has changed to XSON8.
20100107 Product data sheet 74AHC3GU04 v.3
Marking code for 74AHC3GU04DP package changed from AU04 to AU4
Product data sheet
-
74AHC3GU04 v.4
•
74AHC3GU04 v.4
-
•
74AHC3GU04 v.3
74AHC3GU04 v.2
74AHC3GU04 v.1
20090126
20040923
20040305
Product data sheet
Product specification
Product specification
-
-
-
74AHC3GU04 v.2
74AHC3GU04 v.1
-
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
11 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
16. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
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©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
12 / 13
Nexperia
74AHC3GU04
Triple unbuffered inverter
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Marking..........................................................................1
5. Functional diagram.......................................................2
6. Pinning information......................................................2
6.1. Pinning.........................................................................2
6.2. Pin description.............................................................2
7. Functional description................................................. 2
8. Limiting values............................................................. 3
9. Recommended operating conditions..........................3
10. Static characteristics..................................................4
10.1. Typical transfer characteristics.................................. 5
11. Dynamic characteristics.............................................6
11.1. Waveforms and test circuit........................................ 7
12. Application information............................................. 8
13. Package outline.......................................................... 9
14. Abbreviations............................................................11
15. Revision history........................................................11
16. Legal information......................................................12
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 27 February 2019
©
74AHC3GU04
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 6 — 27 February 2019
13 / 13
相关型号：
74AHC3GU04DP-G
Inverter - Description: Triple Hex Inverter (Unbuffered) ; Logic switching levels: CMOS ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.5@5V ns; Voltage: 2.0-5.5 V
NXP
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