74ALVCH16843DGG [NEXPERIA]
18-bit bus-interface D-type latch; 3-stateProduction;型号: | 74ALVCH16843DGG |
厂家: | Nexperia |
描述: | 18-bit bus-interface D-type latch; 3-stateProduction 驱动 光电二极管 逻辑集成电路 |
文件: | 总16页 (文件大小:200K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
Rev. 3 — 20 November 2017
Product data sheet
1 General description
The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each
latch and 3-State outputs for bus oriented applications. The two sections of each register
are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and
output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH,
the outputs are in the high impedance OFF state. Operation of the nOE input does not
affect the state of the flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2 Features and benefits
• Wide supply voltage range of 1.2V to 3.6V
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ±24 mA at VCC = 3.0 V.
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimize noise and ground bounce
• All data inputs have bushold
• Output drive capability 50 Ω transmission lines at 85 °C
• 3-state non-inverting outputs for bus oriented applications
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Temperature range Name
Description
Version
74ALVCH16843DGG -40 °C to +85 °C
TSSOP56
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
SOT364-1
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
4 Functional diagram
2
55
1
1
55
2
56
EN4
S2
R3
1OE
1PRE
1CLR
1LE
1CLR 1PRE 1OE
1LE
56
27
30
28
29
C1
3
5
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
2OE
EN8
S6
R7
2PRE
2CLR
2LE
6
C5
8
9
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
3
5
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1D 2, 3, 4
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
10
12
13
14
15
16
17
19
20
21
23
24
26
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
5D 6, 7, 8
2CLR 2PRE 2OE
2LE
29
aaa-027720
28
30
27
aaa-027721
Figure 1.ꢀLogic symbol
Figure 2.ꢀIEC logic symbol
LATCH 1
LATCH 10
1D0
D
Q
1Q0
2D0
D
Q
2Q0
1CLR
CLR
PRE
LE
2CLR
CLR
PRE
LE
1PRE
1LE
2PRE
2LE
1OE
2OE
to 8 other channels
to 8 other channels
aaa-027722
Figure 3.ꢀLogic diagram
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
2 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
V
CC
data
input
to internal circuit
mna004
Figure 4.ꢀBushold circuit
5 Pinning information
5.1 Pinning
74ALVCH16843
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q0
GND
1Q1
1Q2
1LE
2
1PRE
1D0
3
4
GND
1D1
5
6
1D2
7
V
V
CC
CC
8
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
V
CC
CC
2Q6
2Q7
2D6
2D7
GND
2Q8
GND
2D8
2OE
2CLR
2PRE
2LE
aaa-027723
Figure 5.ꢀPin configuration for TSSOP56
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
3 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
5.2 Pin description
Table 2.ꢀPin description
Symbol
Pin
Description
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8
54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs
data outputs
42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8 3, 5, 6, 8, 9, 10, 12, 13, 14
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8
1OE, 2OE
1PRE, 2PRE
1CLR, 2CLR
1LE, 2LE
GND
2, 27
output enable inputs (active LOW)
preset inputs (active LOW)
clear inputs (active LOW)
latch enable inputs (active HIGH)
ground (0 V)
55, 30
1, 28
56, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
VCC
supply voltage
6 Functional description
Table 3.ꢀFunction selection [1]
Inputs
Output
nPRE
nCLR
nOE
nLE
X
nDn
nQn
H
L
X
L
L
L
L
L
L
H
X
X
L
H
H
H
H
X
X
L
H
H
H
X
H
L
H
H
X
X
H
L
NC
Z
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
4 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
7 Limiting values
Table 4.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-0.5
-0.5
-50
-
Max
+4.6
+4.6
VCC + 0.5
VCC + 0.5
-
Unit
V
VCC
VI
supply voltage
input voltage
[1]
[1]
[1]
For control pins
For data inputs
V
V
VO
IIK
output voltage
V
input clamping current
output clamping current
output current
VI < 0 V
mA
mA
mA
mA
mA
°C
IOK
IO
VO > VCC or VO < 0 V
VO = 0 V to VCC
±50
-
±50
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-100
-65
-
-
storage temperature
total power dissipation
+150
600
[2]
Tamb = -40 °C to +85 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.
8 Recommended operating conditions
Table 5.ꢀRecommended operating conditions
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
maximum speed performance
CL = 30 pF
2.3
3.0
0
2.7
3.6
VCC
VCC
+85
20
V
CL = 50 pF
V
VI
input voltage
V
VO
output voltage
0
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
in free air
-40
-
°C
ns/V
ns/V
VCC = 2.3 V to 3.0 V
VCC = 3.0 V to 3.6 V
-
10
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
5 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
9 Static characteristics
Table 6.ꢀStatic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C
Symbol Parameter
Conditions
Min
1.7
2.0
-
Typ[1]
Max
-
Unit
V
VIH
HIGH-level
VCC = 2.3 V to 2.7 V
1.2
input voltage
VCC = 2.7 V to 3.6 V
1.5
-
V
VIL
LOW-level
VCC = 2.3 V to 2.7 V
1.2
0.7
0.8
V
input voltage
VCC = 2.7 V to 3.6 V
-
1.5
V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -100 μA; VCC = 2.3 V to 3.6 V
IO = -6 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -12 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
VI = VIH or VIL
VCC - 0.2
VCC - 0.3
VCC - 0.6
VCC - 0.5
VCC - 0.6
VCC - 1.0
VCC
-
-
-
-
-
-
V
V
V
V
V
V
VCC - 0.08
VCC - 0.26
VCC - 0.14
VCC - 0.09
VCC - 0.28
VOL
LOW-level
output voltage
IO = 100 μA; VCC = 2.3 V to 3.6 V
IO = 6 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 2.3 V to 3.6 V; VI = VCC or GND
-
-
-
-
-
-
GND
0.07
0.15
0.14
0.27
0.1
0.20
0.40
0.70
0.40
0.55
5
V
V
V
V
V
II
input
μA
leakage current
IOZ
ICC
ΔICC
IBHL
OFF-state
output current
VCC = 2.3 V to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
-
-
-
0.1
0.2
10
40
μA
μA
μA
supply current
VCC = 2.3 V to 3.6 V; VI = VCC or GND;
IO = 0 A
additional
supply current
VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V;
IO = 0 A
150
750
bus hold LOW
current
VCC = 2.3 V; VI = 0.7 V
VCC = 3.0 V; VI = 0.8 V
VCC = 2.3 V; VI = 1.7 V
VCC = 3.0 V; VI = 2.0 V
VCC = 3.6 V
45
75
-
150
-
-
-
-
-
-
μA
μA
μA
μA
μA
IBHH
bus hold HIGH
current
-45
-75
500
-175
-
IBHLO
IBHHO
CI
bus hold LOW
overdrive current
bus hold HIGH
overdrive current
VCC = 3.6 V
-500
-
-
-
-
μA
pF
input capacitance
5.0
[1] All typical values are measured at Tamb = 25 °C.
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
6 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
10 Dynamic characteristics
Table 7.ꢀDynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11;
Tamb = -40 °C to +85 °C
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
[2]
tpd
propagation delay
nDn to nQn; see Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
2.2
2.3
2.1
4.3
4.0
3.5
ns
ns
ns
VCC = 3.0 V to 3.6 V
nLE to nQn; see Figure 7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
2.3
2.1
2.0
4.6
3.9
3.5
ns
ns
ns
VCC = 3.0 V to 3.6 V
nPRE to nQn; see Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
1.0
1.0
1.0
2.5
2.6
2.2
4.8
4.5
3.8
ns
ns
ns
VCC = 3.0 V to 3.6 V
nCLR to nQn; see Figure 6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
2.5
2.5
2.3
4.8
4.3
3.9
ns
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nQn; see Figure 10
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[3]
[4]
ten
tdis
tsu
th
enable time
disable time
set-up time
hold time
1.0
1.0
1.0
2.8
3.0
2.5
5.8
5.3
4.4
ns
ns
ns
VCC = 3.0 V to 3.6 V
nOE to nQn; see Figure 10
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.1
1.3
1.3
2.2
2.8
2.6
4.3
4.4
4.0
ns
ns
ns
VCC = 3.0 V to 3.6 V
nDn to nLE; see Figure 8
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.5
0.5
0.5
−0.1
−0.3
0.0
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nDn to nLE; see Figure 8
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.9
0.9
0.9
0.5
0.5
0.5
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
7 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
tW
pulse width
nLE HIGH; see Figure 7
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.5
0.5
0.5
0.5
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nPRE LOW; see Figure 9
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.5
0.5
0.6
0.5
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nCLR LOW; see Figure 9
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.5
0.5
0.5
0.5
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nPRE to nLE; see Figure 9
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
trec
recovery time
0.5
0.8
1.0
1.1
−0.2
0.4
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
nCLR to nLE; see Figure 9
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
0.5
0.6
0.8
1.0
−0.4
0.2
-
-
-
ns
ns
ns
VCC = 3.0 V to 3.6 V
per latch; VI = GND to VCC
transparent mode; outputs enabled
transparent mode; outputs disabled
clocked mode; outputs enabled
clocked mode; outputs disabled
[5]
CPD
power dissipation
capacitance
-
-
-
-
17
3
-
-
-
-
pF
pF
pF
pF
19
9
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V.
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V.
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZL and tPZH
[4] tdis is the same as tPLZ and tPHZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
8 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
10.1 Waveforms and test circuit
V
I
nCLR, nDn
input
V
V
M
M
nPRE
GND
t
t
PHL
PLH
V
OH
V
V
M
nQn output
M
V
OL
aaa-027724
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Figure 6.ꢀData input (nDn) to output (nQn), clear input (nCLR) to output (nQn) and preset input (nPRE) to output
(nQn) propagation delay
V
I
nLE input
V
V
V
t
M
M
M
GND
t
W
t
PHL
PLH
V
OH
nQn output
V
V
M
M
V
OL
001aam012
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Figure 7.ꢀLatch enable input (nLE) to data output (nQn) propagation delay and pulse width (nLE)
V
I
nDn input
nLE input
V
M
GND
t
t
h
h
t
t
su
su
V
I
V
M
GND
001aam013
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 8.ꢀData setup and hold times for input (nDn) to input (nLE)
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
9 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
V
I
nCLR, nPRE
input
V
V
M
M
GND
t
W
t
rec
V
I
nLE input
GND
V
M
aaa-027725
Measurement points are given in Table 8.
Figure 9.ꢀClear (nCLR) and preset (nPRE) pulse width, the clear (nCLR) and preset (nPRE) to latch (nLE) recovery
time
V
I
nOE input
V
V
M
M
t
GND
t
PLZ
PZL
V
CC
nQn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nQn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal795
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Figure 10.ꢀ3-State enable and disable times
Table 8.ꢀMeasurement points
Input
Output
VM
VCC
VI
VM
Vx
Vy
2.3 V to 2.7 V
2.7 V
VCC
2.7 V
2.7 V
0.5VCC
1.5 V
1.5 V
0.5VCC
1.5 V
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
3.0 V to 3.6 V
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
10 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
PULSE
GENERATOR
DUT
R
T
C
L
R
L
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Figure 11.ꢀTest circuit for measuring switching times
Table 9.ꢀTest data
Input
Load
RL
VEXT
VCC
VI
tr, tf
CL
tPHZ, tPZH
GND
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
tPLH, tPHL
open
2.3 V to 2.7 V
2.7 V
VCC
2.7 V
2.7 V
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
500 Ω
500 Ω
500 Ω
30 pF
50 pF
50 pF
GND
open
3.0 V to 3.6 V
GND
open
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
11 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.08
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Figure 12.ꢀPackage outline SOT364-1 (TSSOP56)
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
12 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
12 Abbreviations
Table 10.ꢀAbbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
13 Revision history
Table 11.ꢀRevision history
Document ID
Release date
20171120
Data sheet status
Change notice
Supersedes
74ALVCH16843 v.3
Modifications:
Product data sheet
-
74ALVCH16843 v.2
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
74ALVCH16843 v.2
74ALVCH16843 v.1
19980804
19980804
Product specification
Product specification
-
-
74ALVCH16843 v.2
-
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
13 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
14 Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
14.2 Definitions
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
Draft — The document is a draft version only. The content is still under
such equipment or applications and therefore such inclusion and/or use is at
internal review and subject to formal approval, which may result in
the customer’s own risk.
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
Short data sheet — A short data sheet is an extract from a full data sheet
without further testing or modification. Customers are responsible for the
with the same product type number(s) and title. A short data sheet is
design and operation of their applications and products using Nexperia
intended for quick reference only and should not be relied upon to contain
products, and Nexperia accepts no liability for any assistance with
detailed and full information. For detailed and full information see the
applications or customer product design. It is customer’s sole responsibility
relevant full data sheet, which is available on request via the local Nexperia
to determine whether the Nexperia product is suitable and fit for the
sales office. In case of any inconsistency or conflict with the short data sheet,
customer’s applications and products planned, as well as for the planned
the full data sheet shall prevail.
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
any liability related to any default, damage, costs or problem which is based
Nexperia and its customer, unless Nexperia and customer have explicitly
on any weakness or default in the customer’s applications or products, or
agreed otherwise in writing. In no event however, shall an agreement be
the application or use by customer’s third party customer(s). Customer is
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Limited warranty and liability — Information in this document is believed
damage to the device. Limiting values are stress ratings only and (proper)
to be accurate and reliable. However, Nexperia does not give any
operation of the device at these or any other conditions above those
representations or warranties, expressed or implied, as to the accuracy
given in the Recommended operating conditions section (if present) or the
or completeness of such information and shall have no liability for the
Characteristics sections of this document is not warranted. Constant or
consequences of use of such information. Nexperia takes no responsibility
repeated exposure to limiting values will permanently and irreversibly affect
for the content in this document if provided by an information source outside
the quality and reliability of the device.
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
or replacement of any products or rework charges) whether or not such
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
damages are based on tort (including negligence), warranty, breach of
in a valid written individual agreement. In case an individual agreement is
contract or any other legal theory. Notwithstanding any damages that
concluded only the terms and conditions of the respective agreement shall
customer might incur for any reason whatsoever, Nexperia's aggregate and
apply. Nexperia hereby expressly objects to applying the customer’s general
cumulative liability towards customer for the products described herein shall
terms and conditions with regard to the purchase of Nexperia products by
customer.
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
No offer to sell or license — Nothing in this document may be interpreted
Right to make changes — Nexperia reserves the right to make changes
or construed as an offer to sell products that is open for acceptance or
to information published in this document, including without limitation
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74ALVCH16843
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
14 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74ALVCH16843
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 20 November 2017
15 / 16
Nexperia
74ALVCH16843
18-bit bus-interface D-type latch; 3-State
Contents
1
General description ............................................ 1
2
3
4
5
5.1
5.2
6
7
8
Features and benefits .........................................1
Ordering information .......................................... 1
Functional diagram .............................................2
Pinning information ............................................ 3
Pinning ...............................................................3
Pin description ...................................................4
Functional description ........................................4
Limiting values ....................................................5
Recommended operating conditions ................5
Static characteristics ..........................................6
Dynamic characteristics .....................................7
Waveforms and test circuit ................................9
Package outline .................................................12
Abbreviations .................................................... 13
Revision history ................................................ 13
Legal information ..............................................14
9
10
10.1
11
12
13
14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 20 November 2017
Document identifier: 74ALVCH16843
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