74AUP1T97GW-Q100 [NEXPERIA]
Low-power configurable gate with voltage-level translatorProduction;
| 型号： | 74AUP1T97GW-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Low-power configurable gate with voltage-level translatorProduction |
| 文件： | 总15页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
Rev. 3 — 27 January 2022
Product data sheet
1. General description
The 74AUP1T97-Q100 is a configurable multiple function gate with level translating, Schmitt-trigger
inputs. The device can be configured as any of the following logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to
VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic
levels in 3.3 V applications. This device ensures very low static and dynamic power consumption
across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II
Low static power consumption; ICC = 1.5 μA (maximum)
Complies with JEDEC standards:
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
•
ESD protection:
•
•
•
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1T97GW-Q100
-40 °C to +125 °C
TSSOP6
plastic thin shrink small outline package;
6 leads; body width 1.25 mm
SOT363-2
4. Marking
Table 2. Marking
Type number
Marking code[1]
74AUP1T97GW-Q100
59
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
A
4
Y
1
B
6
C
001aad998
Fig. 1. Logic symbol
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
2 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1. Pinning
74AUP1T97
1
2
3
6
5
4
B
GND
A
C
V
Y
CC
001aag500
Fig. 2. Pin configuration SOT363-2 (TSSOP6)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
data input
B
GND
A
2
ground (0 V)
data input
3
Y
4
data output
supply voltage
data input
VCC
C
5
6
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
C
L
B
L
A
L
Y
L
L
L
H
L
L
L
H
H
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
L
H
H
H
H
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
3 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
7.1. Logic configurations
Table 5. Function selection table
Logic function
Figure
2-input MUX
see Fig. 3
see Fig. 4
see Fig. 5
see Fig. 5
see Fig. 6
see Fig. 6
see Fig. 7
see Fig. 8
see Fig. 9
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
V
V
CC
CC
B
A
1
6
5
4
C
Y
1
2
3
6
5
4
C
Y
B
A
C
A
C
Y
2
3
Y
A
001aae002
001aae003
Fig. 3. 2-input MUX
Fig. 4. 2-input AND gate
V
V
CC
CC
A
C
B
Y
C
Y
Y
1
2
3
6
5
4
C
Y
B
1
2
3
6
5
4
C
Y
A
C
B
Y
C
A
001aae004
001aae005
Fig. 5. 2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig. 6. 2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
V
V
CC
CC
B
1
2
3
6
5
4
C
1
2
3
6
5
4
C
B
C
Y
C
Y
Y
Y
001aae006
001aae007
Fig. 7. 2-input OR gate
Fig. 8. Inverter
V
CC
B
1
2
3
6
5
4
B
Y
Y
001aae008
Fig. 9. Buffer
©
74AUP1T97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
4 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
[1]
+4.6
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
50
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT363-2 (TSSOP6) package: Ptot derates linearly with 3.7 mW/K above 83 °C.
9. Recommended operating conditions
Table 7. Recommended operating conditions
Symbol Parameter
Conditions
Min
2.3
0
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
+125
°C
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
5 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
10. Static characteristics
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 25 °C
Conditions
Min
Typ
Max
Unit
VT+
VT-
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.16
0.60
0.85
V
V
V
V
negative-going threshold VCC = 2.3 V to 2.7 V
voltage
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.23
0.25
-
-
0.60
0.56
V
V
VOH
HIGH-level output voltage VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
VCC - 0.1
2.05
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
2.72
2.6
VOL
LOW-level output voltage VI = VT+ or VT-
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.31
0.44
0.31
0.44
±0.1
±0.1
±0.2
V
V
IO = 3.1 mA; VCC = 2.3 V
V
IO = 2.7 mA; VCC = 3.0 V
V
IO = 4.0 mA; VCC = 3.0 V
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V
ICC
CI
supply current
VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
-
-
1.2
μA
pF
pF
input capacitance
output capacitance
0.8
1.7
-
-
CO
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74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
6 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +85 °C
VT+
VT-
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.19
0.60
0.85
V
V
V
V
negative-going threshold VCC = 2.3 V to 2.7 V
voltage
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.10
0.15
-
-
0.60
0.56
V
V
VOH
HIGH-level output voltage VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
VCC - 0.1
1.97
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.85
2.67
2.55
VOL
LOW-level output voltage VI = VT+ or VT-
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.5
V
IO = 3.1 mA; VCC = 2.3 V
V
IO = 2.7 mA; VCC = 3.0 V
V
IO = 4.0 mA; VCC = 3.0 V
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V
-
-
-
-
-
-
1.5
4
μA
μA
μA
ΔICC
additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
[1]
[2]
12
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74AUP1T97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
7 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +125 °C
VT+
VT-
VH
positive-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.60
0.75
0.33
0.46
-
-
-
-
1.10
1.19
0.64
0.85
V
V
V
V
negative-going threshold VCC = 2.3 V to 2.7 V
voltage
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.10
0.15
-
-
0.60
0.56
V
V
VOH
HIGH-level output voltage VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
VCC - 0.11
1.77
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.67
2.40
2.30
VOL
LOW-level output voltage VI = VT+ or VT-
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
0.36
V
V
IO = 3.1 mA; VCC = 2.3 V
0.50
V
IO = 2.7 mA; VCC = 3.0 V
0.36
V
IO = 4.0 mA; VCC = 3.0 V
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
±0.75
±0.75
±0.75
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V
additional power-off
leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A; VCC = 2.3 V to 3.6 V
-
-
-
-
-
-
3.5
7
μA
μA
μA
ΔICC
additional supply current VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
[1]
[2]
22
[1] One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2] One input at 0.45 V or 1.2 V, other input at VCC or GND.
©
74AUP1T97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
8 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
11. Dynamic characteristics
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 11.
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ [1] Max
Min
Max
Min
Max
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
[2]
[2]
[2]
[2]
[2]
[2]
2.2
2.6
2.9
3.7
3.5
4.1
4.6
5.8
5.5
6.3
6.9
8.4
0.5
1.0
1.0
1.5
6.8
7.9
0.5
1.0
1.0
1.5
7.5
8.7
9.6
ns
ns
ns
CL = 10 pF
CL = 15 pF
8.7
CL = 30 pF
10.8
11.9 ns
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
1.8
2.2
2.5
3.2
3.4
4.0
4.4
5.6
5.5
6.2
6.8
8.3
0.5
1.0
1.0
1.5
6.0
7.1
0.5
1.0
1.0
1.5
6.6
7.9
8.7
ns
ns
ns
CL = 10 pF
CL = 15 pF
7.9
CL = 30 pF
10.0
11.0 ns
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
1.4
1.8
2.2
2.9
3.1
3.7
4.2
5.3
5.0
5.7
6.3
7.9
0.5
1.0
1.0
1.5
5.5
6.5
7.4
9.5
0.5
1.0
1.0
1.5
6.1
7.2
8.2
ns
ns
ns
CL = 10 pF
CL = 15 pF
CL = 30 pF
10.5 ns
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
2.1
2.5
2.9
3.6
2.9
3.4
3.9
5.0
3.9
4.6
5.2
6.7
0.5
1.0
1.0
1.5
8.0
8.5
9.1
9.8
0.5
1.0
1.0
1.5
8.8
9.4
ns
ns
CL = 10 pF
CL = 15 pF
10.1 ns
10.8 ns
CL = 30 pF
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
1.7
2.1
2.4
3.2
2.8
3.4
3.8
5.0
4.2
5.0
5.6
7.1
0.5
1.0
1.0
1.5
5.3
6.1
6.8
8.5
0.5
1.0
1.0
1.5
5.9
6.8
7.5
9.4
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
CL = 30 pF
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
tpd
propagation
delay
A, B, C to Y; see Fig. 10
CL = 5 pF
1.4
1.8
2.1
2.9
2.7
3.3
3.8
4.9
4.2
5.0
5.6
7.1
0.5
1.0
1.0
1.5
4.7
5.7
6.2
7.8
0.5
1.0
1.0
1.5
5.2
6.3
6.9
8.6
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
CL = 30 pF
©
74AUP1T97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
9 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
Symbol Parameter
Tamb = 25 °C
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ [1] Max
Min
Max
Min
Max
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC [3]
VCC = 2.3 V to 2.7 V
-
-
3.6
4.3
-
-
-
-
-
-
-
-
-
-
pF
pF
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
11.1. Waveform and test circuit
V
I
A, B, C input
GND
V
V
M
M
t
t
PLH
PHL
V
OH
V
V
V
M
Y output
M
t
V
OL
t
PLH
PHL
V
OH
Y output
V
M
M
V
OL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. Input A, B and C to output Y propagation delay times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VI
tr = tf
2.3 V to 3.6 V
0.5 × VI
1.65 V to 3.6 V
≤ 3.0 ns
0.5 × VCC
©
74AUP1T97_Q100
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
10 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
V
V
EXT
CC
5 kΩ
V
I
V
O
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator;
CL = load capacitance including jig and probe capacitance;
RL = load resistance.
Fig. 11. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
RL [1]
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
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74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
11 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
12. Package outline
TSSOP6: plastic thin shrink small outline package; 6 leads; body width 1.25 mm
SOT363-2
D
B
E
A
X
c
(6x)
y
H
E
v
M
A
e
1
6
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(6x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot363-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT363-2
SC-88A
MO-203
Fig. 12. Package outline SOT363-2 (TSSOP6)
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74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
12 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
13. Abbreviations
Table 12. Abbreviations
Acronym
Description
CDM
CMOS
DUT
ESD
HBM
MM
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
14. Revision history
Table 13. Revision history
Document ID
Release date Data sheet status
20220127 Product data sheet
Package SOT363 (SC-88) changed to SOT363-2 (TSSOP6).
Change notice Supersedes
74AUP1T97_Q100 v.3
Modifications:
- 74AUP1T97_Q100 v.2
•
74AUP1T97_Q100 v.2
Modifications:
20211104
Section 1 and Section 2 updated.
20210715 Product data sheet
Product data sheet
-
74AUP1T97_Q100 v.1
•
74AUP1T97_Q100 v.1
-
-
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
13 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
equipment, nor in applications where failure or malfunction of an Nexperia
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15. Legal information
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
products are for illustrative purposes only. Nexperia makes no representation
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without further testing or modification.
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This document contains data from
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Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
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Nexperia does not accept any liability related to any default, damage, costs
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Limiting values — Stress above one or more limiting values (as defined in
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Characteristics sections of this document is not warranted. Constant or
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be suitable for use in life support, life-critical or safety-critical systems or
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
14 / 15
Nexperia
74AUP1T97-Q100
Low-power configurable gate with voltage-level translator
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
7.1. Logic configurations.....................................................4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................5
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................9
11.1. Waveform and test circuit........................................ 10
12. Package outline........................................................ 12
13. Abbreviations............................................................13
14. Revision history........................................................13
15. Legal information......................................................14
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 27 January 2022
©
74AUP1T97_Q100
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 3 — 27 January 2022
15 / 15
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