74AVC1T45GM [NEXPERIA]

Dual-supply voltage level translator/transceiver; 3-stateProduction;
74AVC1T45GM
型号: 74AVC1T45GM
厂家: Nexperia    Nexperia
描述:

Dual-supply voltage level translator/transceiver; 3-stateProduction

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74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Rev. 10 — 2 February 2022  
Product data sheet  
1. General description  
The 74AVC1T45 is a single bit, dual supply transceiver with 3-state output that enables  
bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control  
input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any  
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low  
voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A)  
and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on  
DIR allows transmission from B to A.  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing any damaging backflow current through the device when it is  
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are  
in the high-impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.8 V to 3.6 V  
VCC(B): 0.8 V to 3.6 V  
High noise immunity  
CMOS low power dissipation  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11( 0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114E Class 3B exceeds 8000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Maximum data rates:  
500 Mbit/s (1.8 V to 3.3 V translation)  
320 Mbit/s (< 1.8 V to 3.3 V translation)  
320 Mbit/s (translate to 2.5 V or 1.8 V)  
280 Mbit/s (translate to 1.5 V)  
240 Mbit/s (translate to 1.2 V)  
Suspend mode  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Overvoltage tolerant inputs to 3.6 V  
Dynamically controlled outputs  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AVC1T45GW  
74AVC1T45GM  
74AVC1T45GN  
74AVC1T45GS  
74AVC1T45GX  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
TSSOP6  
plastic thin shrink small outline package; 6 leads;  
body width 1.25 mm  
SOT363-2  
XSON6  
XSON6  
XSON6  
X2SON6  
plastic extremely thin small outline package;  
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm  
SOT886  
extremely thin small outline package; no leads;  
6 terminals; body 0.9 × 1.0 × 0.35 mm  
SOT1115  
SOT1202  
SOT1255-2  
extremely thin small outline package; no leads;  
6 terminals; body 1.0 × 1.0 × 0.35 mm  
plastic thermal enhanced extremely  
thin small outline package; no leads;  
6 terminals; body 1.0 × 0.8 × 0.32 mm  
4. Marking  
Table 2. Marking  
Type number  
Marking code[1]  
74AVC1T45GW  
74AVC1T45GM  
74AVC1T45GN  
74AVC1T45GS  
74AVC1T45GX  
B5  
B5  
B5  
B5  
B5  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5. Functional diagram  
5
DIR  
DIR  
3
A
A
4
B
B
V
V
CC(B)  
CC(A)  
V
V
CC(A)  
CC(B)  
001aag886  
001aag885  
Fig. 1. Logic symbol  
Fig. 2. Logic diagram  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
2 / 22  
 
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
6. Pinning information  
6.1. Pinning  
74AVC1T45  
74AVC1T45  
V
1
2
3
6
5
4
V
CC(B)  
CC(A)  
GND  
1
2
3
6
5
4
V
V
CC(B)  
CC(A)  
GND  
DIR  
B
DIR  
B
A
A
001aag972  
Transparent top view  
001aag971  
Fig. 3. Pin configuration SOT363-2 (TSSOP6)  
74AVC1T45  
Fig. 4. Pin configuration SOT886 (XSON6)  
V
1
2
3
6
5
4
V
CC(B)  
CC(A)  
74AVC1T45  
V
1
3
6
4
V
CC(B)  
CC(A)  
GND  
A
GND  
DIR  
2
5
DIR  
B
A
B
aaa-000876  
aaa-022602  
Transparent top view  
Transparent top view  
Fig. 5. Pin configuration SOT1115 and SOT1202  
(XSON6)  
Fig. 6. Pin configuration SOT1255-2 (X2SON6)  
6.2. Pin description  
Table 3. Pin description  
Symbol  
VCC(A)  
GND  
A
Pin  
1
Description  
supply voltage port A and DIR  
ground (0 V)  
2
3
data input or output  
data input or output  
direction control  
B
4
DIR  
5
VCC(B)  
6
supply voltage port B  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
3 / 22  
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
7. Functional description  
Table 4. Function table  
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
Supply voltage  
VCC(A), VCC(B)  
0.8 V to 3.6 V  
0.8 V to 3.6 V  
GND[3]  
Input  
Input/output[1]  
DIR[2]  
A
B
L
A = B  
input  
Z
input  
B = A  
Z
H
X
[1] The input circuit of the data I/O is always active.  
[2] The DIR input circuit is referenced to VCC(A)  
.
[3] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.  
8. Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC(A)  
VCC(B)  
IIK  
Parameter  
Conditions  
Min  
-0.5  
-0.5  
-50  
-0.5  
-50  
-0.5  
-0.5  
-
Max  
+4.6  
+4.6  
-
Unit  
V
supply voltage A  
supply voltage B  
input clamping current  
input voltage  
V
VI < 0 V  
mA  
V
VI  
[1]  
+4.6  
-
IOK  
output clamping current  
output voltage  
VO < 0 V  
mA  
VO  
Active mode  
[1][2][3]  
[1]  
VCCO + 0.5 V  
Suspend or 3-state mode  
VO = 0 V to VCCO  
ICC(A) or ICC(B)  
+4.6  
±50  
100  
-
V
IO  
output current  
mA  
mA  
mA  
°C  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
-100  
-65  
-
storage temperature  
total power dissipation  
+150  
250  
Tamb = -40 °C to +125 °C  
[4]  
mW  
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] VCCO is the supply voltage associated with the output port.  
[3] VCCO + 0.5 V should not exceed 4.6 V.  
[4] For SOT363-2 (TSSOP6) package: Ptot derates linearly with 3.7 mW/K above 83 °C.  
For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.  
For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C.  
For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.  
For SOT1255-2 (X2SON6) package: Ptot derates linearly with 3.3 mW/K above 75 °C.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
4 / 22  
 
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
9. Recommended operating conditions  
Table 6. Recommended operating conditions  
Symbol  
VCC(A)  
VCC(B)  
VI  
Parameter  
Conditions  
Min  
0.8  
0.8  
0
Max  
3.6  
Unit  
V
supply voltage A  
supply voltage B  
input voltage  
3.6  
V
3.6  
V
VO  
output voltage  
Active mode  
[1]  
[2]  
0
VCCO  
3.6  
V
Suspend or 3-state mode  
0
V
Tamb  
ambient temperature  
-40  
-
+125  
5
°C  
ns/V  
Δt/ΔV  
input transition rise and fall rate  
VCCI = 0.8 V to 3.6 V  
[1] VCCO is the supply voltage associated with the output port.  
[2] VCCI is the supply voltage associated with the input port.  
10. Static characteristics  
Table 7. Typical static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter Conditions  
Tamb = 25 °C  
Typ  
Unit  
Min  
Max  
VOH  
HIGH-level output voltage VI = VIH or VIL  
IO = -1.5 mA; VCC(A) = VCC(B) = 0.8 V  
LOW-level output voltage VI = VIH or VIL  
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V  
-
0.69  
0.07  
-
-
V
V
VOL  
-
-
II  
input leakage current  
DIR input; VI = 0 V or 3.6 V;  
±0.025 ±0.25 μA  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
IOZ  
IOFF  
OFF-state output current  
A or B port; VO = 0 V or VCCO  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
;
[1]  
[2]  
-
-
-
-
-
±0.5  
±0.1  
±0.1  
1.0  
±2.5 μA  
power-off leakage current A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V;  
VCC(B) = 0.8 V to 3.6 V  
±1  
±1  
-
μA  
μA  
pF  
pF  
B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V;  
VCC(A) = 0.8 V to 3.6 V  
CI  
input capacitance  
DIR input; VI = 0 V or 3.3 V;  
VCC(A) = VCC(B) = 3.3 V  
CI/O  
input/output capacitance  
A and B port; Suspend mode;  
[1]  
4.0  
-
VO = VCCO or GND; VCC(A) = VCC(B) = 3.3 V  
[1] VCCO is the supply voltage associated with the output port.  
[2] For I/O ports, the parameter IOZ includes the input leakage current.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
5 / 22  
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Table 8. Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
VCCO is the supply voltage associated with the output port.  
VCCI is the supply voltage associated with the data input port.  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C  
Unit  
Min  
Max  
Min  
Max  
VIH  
HIGH-level  
data input  
input voltage  
VCCI = 0.8 V  
0.70 × VCCI  
-
-
-
-
0.70 × VCCI  
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
0.65 × VCCI  
0.65 × VCCI  
1.6  
2
1.6  
2
DIR input  
VCC(A) = 0.8 V  
0.70 × VCC(A)  
-
-
-
-
0.70 × VCC(A)  
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V  
VCC(A) = 2.3 V to 2.7 V  
VCC(A) = 3.0 V to 3.6 V  
0.65 × VCC(A)  
0.65 × VCC(A)  
1.6  
2
1.6  
2
VIL  
LOW-level  
data input  
input voltage  
VCCI = 0.8 V  
-
-
-
-
0.30 × VCCI  
0.35 × VCCI  
0.7  
-
-
-
-
0.30 × VCCI  
0.35 × VCCI  
0.7  
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
0.9  
0.9  
DIR input  
VCC(A) = 0.8 V  
-
-
-
-
0.30 × VCC(A)  
0.35 × VCC(A)  
0.7  
-
-
-
-
0.30 × VCC(A)  
0.35 × VCC(A)  
0.7  
V
V
V
V
VCC(A) = 1.1 V to 1.95 V  
VCC(A) = 2.3 V to 2.7 V  
VCC(A) = 3.0 V to 3.6 V  
0.9  
0.9  
VOH  
HIGH-  
VI = VIH or VIL  
level output  
voltage  
IO = -100 μA;  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
VCCO - 0.1  
0.85  
-
-
-
-
-
-
VCCO - 0.1  
0.85  
-
-
-
-
-
-
V
V
V
V
V
V
IO = -3 mA;  
VCC(A) = VCC(B) = 1.1 V  
IO = -6 mA;  
VCC(A) = VCC(B) = 1.4 V  
1.05  
1.05  
IO = -8 mA;  
VCC(A) = VCC(B) = 1.65 V  
1.2  
1.2  
IO = -9 mA;  
VCC(A) = VCC(B) = 2.3 V  
1.75  
1.75  
IO = -12 mA;  
2.3  
2.3  
VCC(A) = VCC(B) = 3.0 V  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
6 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Symbol Parameter  
Conditions  
-40 °C to +85 °C  
-40 °C to +125 °C  
Unit  
Min  
Max  
Min  
Max  
VOL  
LOW-level  
output  
voltage  
VI = VIH or VIL  
IO = 100 μA;  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
-
-
-
-
-
-
-
-
-
-
0.1  
0.25  
0.35  
0.45  
0.55  
0.7  
±1  
-
-
-
-
-
-
-
-
-
-
0.1  
0.25  
0.35  
0.45  
0.55  
0.7  
V
IO = 3 mA;  
VCC(A) = VCC(B) = 1.1 V  
V
IO = 6 mA;  
VCC(A) = VCC(B) = 1.4 V  
V
IO = 8 mA;  
VCC(A) = VCC(B) = 1.65 V  
V
IO = 9 mA;  
VCC(A) = VCC(B) = 2.3 V  
V
IO = 12 mA;  
VCC(A) = VCC(B = 3.0 V  
V
II  
input leakage DIR input; VI = 0 V or 3.6 V;  
±1.5  
±7.5  
±35  
±35  
μA  
μA  
μA  
μA  
current  
VCC(A) = VCC(B) = 0.8 V to 3.6 V  
IOZ  
IOFF  
OFF-state  
A or B port; VO = 0 V or VCCO  
output current VCC(A) = VCC(B) = 3.6 V  
;
[1]  
±5  
power-off  
leakage  
current  
A port; VI or VO = 0 V to 3.6 V;  
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V  
±5  
B port; VI or VO = 0 V to 3.6 V;  
±5  
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V  
ICC  
supply  
current  
A port; VI = 0 V or VCCI; IO = 0 A  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
-
8
-
12  
μA  
VCC(A) = 3.6 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 3.6 V  
B port; VI = 0 V or VCCI; IO = 0 A  
-
8
-
-
12  
-
μA  
μA  
-2  
-8  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
-
8
-
12  
μA  
VCC(A) = 3.6 V; VCC(B) = 0 V  
VCC(A) = 0 V; VCC(B) = 3.6 V  
A plus B port (ICC(A) + ICC(B));  
-2  
-
-
-8  
-
-
μA  
μA  
μA  
8
12  
24  
-
16  
-
IO = 0 A; VI = 0 V or VCCI  
VCC(A) = 0.8 V to 3.6 V;  
VCC(B) = 0.8 V to 3.6 V  
;
[1] For I/O ports, the parameter IOZ includes the input leakage current.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
7 / 22  
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
11. Dynamic characteristics  
Table 9. Typical dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9; for wave forms see Fig. 7 and Fig. 8.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
0.8 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
VCC(A) = 0.8 V and Tamb = 25 °C  
tpd  
tdis  
ten  
propagation delay [1] A to B  
15.5  
15.5  
12.2  
11.7  
27.2  
27.7  
8.1  
12.7  
12.2  
7.9  
7.6  
12.3  
12.2  
7.6  
7.7  
12.2  
12.2  
8.2  
8.4  
12.0  
12.2  
8.7  
9.2  
ns  
ns  
ns  
ns  
ns  
ns  
B to A  
11.8  
12.2  
10.2  
22.0  
21.4  
disable time  
enable time  
[2] DIR to A  
DIR to B  
[3] DIR to A  
DIR to B  
20.6  
20.3  
19.9  
19.8  
20.4  
19.9  
20.7  
20.6  
[1] tpd is the same as tPLH and tPHL  
.
[2] tdis is the same as tPLZ and tPHZ  
.
[3] ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 12.4.  
Table 10. Typical dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9; for wave forms see Fig. 7 and Fig. 8.  
Symbol Parameter  
Conditions  
VCC(A)  
Unit  
0.8 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
VCC(B) = 0.8 V and Tamb = 25 °C  
tpd  
tdis  
ten  
propagation delay [1] A to B  
15.5  
15.5  
12.2  
11.7  
27.2  
27.7  
12.7  
8.1  
12.3  
7.6  
12.2  
7.7  
12.0  
8.4  
11.8  
9.2  
ns  
ns  
ns  
ns  
ns  
ns  
B to A  
disable time  
enable time  
[2] DIR to A  
4.9  
3.8  
3.7  
2.8  
3.4  
DIR to B  
[3] DIR to A  
DIR to B  
9.2  
9.0  
8.8  
8.7  
8.6  
17.3  
17.6  
16.6  
16.1  
16.5  
15.9  
17.1  
14.8  
17.8  
15.2  
[1] tpd is the same as tPLH and tPHL  
.
[2] tdis is the same as tPLZ and tPHZ  
.
[3] ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 12.4.  
Table 11. Typical power dissipation capacitance  
Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
VCC(A) = VCC(B)  
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V  
Unit  
Tamb = 25 °C  
CPD  
power dissipation  
capacitance  
A port: (direction A to B);  
B port: (direction B to A)  
[1][2]  
[1][2]  
1
9
2
2
2
2
2
pF  
pF  
A port: (direction B to A);  
B port: (direction A to B)  
11  
11  
12  
14  
17  
[1] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC 2 x fi x N + Σ(CL x VCC 2 × fo) where:  
fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V;  
N = number of inputs switching; Σ(CL × VCC 2× fo) = sum of the outputs.  
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
8 / 22  
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Table 12. Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9; for waveforms see Fig. 7 and Fig. 8.  
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
ten is a calculated value using the formula shown in Section 12.4.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.2 V±0.1 V  
1.5 V±0.1 V  
1.8 V±0.15 V  
2.5 V±0.2 V  
3.3 V±0.3 V  
Min  
VCC(A) = 1.1 V to 1.3 V; Tamb = -40 °C to +85 °C  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
2.2  
2.2  
-
9.0  
9.0  
0.7  
0.8  
2.2  
1.8  
-
6.8  
8.0  
0.6  
0.7  
2.2  
2.0  
-
6.1  
7.7  
0.5  
0.6  
2.2  
1.7  
-
5.7  
7.2  
0.5  
0.5  
2.2  
2.4  
-
6.1 ns  
7.1 ns  
8.8 ns  
7.2 ns  
14.3 ns  
14.9 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
8.8  
8.8  
8.8  
8.8  
8.4  
6.7  
6.9  
6.2  
enable time DIR to A  
DIR to B  
17.4  
17.8  
14.7  
15.6  
14.6  
14.9  
13.4  
14.5  
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V; Tamb = -40 °C to +85 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.6  
2.0  
-
8.0  
6.8  
0.7  
0.8  
1.6  
1.8  
-
5.4  
5.4  
0.6  
0.7  
1.6  
1.6  
-
4.6  
5.1  
0.5  
0.6  
1.6  
1.2  
-
3.7  
4.7  
0.5  
0.5  
1.6  
1.7  
-
3.5 ns  
4.5 ns  
6.3 ns  
5.5 ns  
10.0 ns  
9.8 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
6.3  
6.3  
6.3  
6.3  
7.6  
5.9  
6.0  
4.8  
enable time DIR to A  
DIR to B  
14.4  
14.3  
11.3  
11.7  
11.1  
10.9  
9.5  
-
-
-
-
10.0  
-
VCC(A) = 1.65 V to 1.95 V; Tamb = -40 °C to +85 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.6  
1.8  
-
7.7  
6.1  
0.6  
0.7  
1.6  
1.8  
-
5.1  
4.6  
0.5  
0.5  
1.6  
1.4  
-
4.3  
4.4  
0.5  
0.5  
1.6  
1.0  
-
3.4  
3.9  
5.5  
4.5  
8.4  
8.9  
0.5  
0.5  
1.6  
1.5  
-
3.1 ns  
3.7 ns  
5.5 ns  
5.2 ns  
8.9 ns  
8.6 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
5.5  
5.5  
5.5  
7.7  
5.7  
5.8  
enable time DIR to A  
DIR to B  
13.8  
13.2  
10.3  
10.6  
10.2  
9.8  
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V; Tamb = -40 °C to +85 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.5  
1.7  
-
7.2  
5.7  
0.5  
0.6  
1.5  
2.0  
-
4.7  
3.8  
4.2  
5.2  
9.0  
8.9  
0.5  
0.5  
1.5  
1.5  
-
3.9  
3.4  
4.2  
5.1  
8.5  
8.1  
0.5  
0.5  
1.5  
0.6  
-
3.0  
3.0  
4.2  
4.2  
7.2  
7.2  
0.5  
0.5  
1.5  
1.1  
-
2.6 ns  
2.8 ns  
4.2 ns  
4.8 ns  
7.6 ns  
6.8 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
4.2  
7.3  
enable time DIR to A  
DIR to B  
13.0  
11.4  
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V; Tamb = -40 °C to +85 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.5  
1.7  
-
7.1  
6.1  
0.5  
0.6  
1.5  
0.7  
-
4.5  
3.6  
4.7  
5.5  
9.1  
9.2  
0.5  
0.5  
1.5  
0.6  
-
3.7  
3.1  
4.7  
5.5  
8.6  
8.4  
0.5  
0.5  
1.5  
0.7  
-
2.8  
2.6  
4.7  
4.1  
6.7  
7.5  
0.5  
0.5  
1.5  
1.7  
-
2.4 ns  
2.4 ns  
4.7 ns  
4.7 ns  
7.1 ns  
7.1 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
4.7  
7.2  
enable time DIR to A  
DIR to B  
13.3  
11.8  
-
-
-
-
-
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
9 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Table 13. Dynamic characteristics  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9; for wave forms see Fig. 7 and Fig. 8.  
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
ten is a calculated value using the formula shown in Section 12.4.  
Symbol Parameter  
Conditions  
VCC(B)  
Unit  
1.2 V±0.1 V  
Min Max  
VCC(A) = 1.1 V to 1.3 V; Tamb = -40 °C to +125 °C  
1.5 V±0.1 V  
1.8 V±0.15 V  
2.5 V±0.2 V  
3.3 V±0.3 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
2.2  
2.2  
-
9.9  
9.9  
0.7  
0.8  
2.2  
1.8  
-
7.5  
8.8  
0.6  
0.7  
2.2  
2.0  
-
6.8  
8.5  
0.5  
0.6  
2.2  
1.7  
-
6.3  
8.0  
0.5  
0.5  
2.2  
2.4  
-
6.8 ns  
7.9 ns  
9.7 ns  
8.0 ns  
15.9 ns  
16.5 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
9.7  
9.7  
9.7  
9.7  
9.2  
7.4  
7.6  
6.9  
enable time DIR to A  
DIR to B  
19.1  
19.6  
16.2  
17.2  
16.1  
16.5  
14.9  
16.0  
-
-
-
-
-
VCC(A) = 1.4 V to 1.6 V; Tamb = -40 °C to +125 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.6  
2.0  
-
8.8  
7.5  
0.7  
0.8  
1.6  
1.8  
-
6.0  
6.0  
0.6  
0.7  
1.6  
1.6  
-
5.1  
5.7  
0.5  
0.6  
1.6  
1.2  
-
4.1  
5.2  
0.5  
0.5  
1.6  
1.7  
-
3.9 ns  
5.0 ns  
7.0 ns  
6.1 ns  
11.1 ns  
10.9 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
7.0  
7.0  
7.0  
7.0  
8.3  
6.5  
6.6  
5.3  
enable time DIR to A  
DIR to B  
15.8  
15.8  
12.5  
13.0  
12.3  
12.1  
10.5  
11.1  
-
-
-
-
-
VCC(A) = 1.65 V to 1.95 V; Tamb = -40 °C to +125 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.6  
1.8  
-
8.5  
6.8  
0.6  
0.7  
1.6  
1.8  
-
5.7  
5.1  
0.5  
0.5  
1.6  
1.4  
-
4.8  
4.9  
0.5  
0.5  
1.6  
1.0  
-
3.8  
4.3  
6.1  
5.0  
9.3  
9.9  
0.5  
0.5  
1.6  
1.5  
-
3.5 ns  
4.1 ns  
6.1 ns  
5.8 ns  
9.9 ns  
9.6 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
6.1  
6.1  
6.1  
8.5  
6.3  
6.4  
enable time DIR to A  
DIR to B  
15.3  
14.6  
11.4  
11.8  
11.3  
10.9  
-
-
-
-
-
VCC(A) = 2.3 V to 2.7 V; Tamb = -40 °C to +125 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.5  
1.7  
-
8.0  
6.3  
0.5  
0.6  
1.5  
2.0  
-
5.2  
4.2  
0.5  
0.5  
1.5  
1.5  
-
4.3  
3.8  
4.7  
5.7  
9.5  
9.0  
0.5  
0.5  
1.5  
0.6  
-
3.3  
3.3  
4.7  
4.7  
8.0  
8.0  
0.5  
0.5  
1.5  
1.1  
-
2.9 ns  
3.1 ns  
4.7 ns  
5.3 ns  
8.4 ns  
7.6 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
4.7  
4.7  
8.0  
5.8  
enable time DIR to A  
DIR to B  
14.3  
12.7  
10.0  
9.9  
-
-
-
-
-
VCC(A) = 3.0 V to 3.6 V; Tamb = -40 °C to +125 °C  
tpd  
tdis  
ten  
propagation A to B  
1.0  
1.0  
1.5  
1.7  
-
7.9  
6.8  
0.5  
0.6  
1.5  
0.7  
-
5.0  
4.0  
0.5  
0.5  
1.5  
0.6  
-
4.1  
3.5  
5.2  
6.1  
9.6  
9.3  
0.5  
0.5  
1.5  
0.7  
-
3.1  
2.9  
5.2  
4.6  
7.5  
8.3  
0.5  
0.5  
1.5  
1.7  
-
2.7 ns  
2.7 ns  
5.2 ns  
5.2 ns  
7.9 ns  
7.9 ns  
delay  
B to A  
disable time DIR to A  
DIR to B  
5.2  
5.2  
7.9  
6.1  
enable time DIR to A  
DIR to B  
14.7  
13.1  
10.1  
10.2  
-
-
-
-
-
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
10 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
11.1. Waveforms and test circuit  
V
I
V
A, B input  
M
GND  
t
t
PLH  
PHL  
V
OH  
B, A output  
V
M
001aae967  
V
OL  
Measurement points are given in Table 14.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 7. The data input (A, B) to output (B, A) propagation delay times  
V
I
DIR input  
V
M
t
GND  
t
PLZ  
PZL  
V
CCO  
output  
V
LOW-to-OFF  
OFF-to-LOW  
M
V
X
V
OL  
t
t
PZH  
PHZ  
V
OH  
V
Y
output  
HIGH-to-OFF  
V
M
OFF-to-HIGH  
GND  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
001aae968  
Measurement points are given in Table 14.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 8. Enable and disable times  
Table 14. Measurement points  
Supply voltage  
VCC(A), VCC(B)  
1.1 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 3.6 V  
Input [1]  
Output [2]  
VM  
VM  
VX  
VOL + 0.1 V  
VY  
0.5 × VCCI  
0.5 × VCCI  
0.5 × VCCI  
0.5 × VCCO  
0.5 × VCCO  
0.5 × VCCO  
VOH - 0.1 V  
VOH - 0.15 V  
VOH - 0.3 V  
VOL + 0.15 V  
VOL + 0.3 V  
[1] VCCI is the supply voltage associated with the data input port.  
[2] VCCO is the supply voltage associated with the output port.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
11 / 22  
 
 
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 15.  
RL = Load resistance;  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance;  
VEXT = External voltage for measuring switching times.  
Fig. 9. Test circuit for measuring switching times  
Table 15. Test data  
Supply voltage  
VCC(A), VCC(B)  
1.1 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 3.6 V  
Input  
VI [1]  
VCCI  
VCCI  
VCCI  
Load  
CL  
VEXT  
Δt/ΔV [2]  
≤ 1.0 ns/V  
≤ 1.0 ns/V  
≤ 1.0 ns/V  
RL  
tPLH, tPHL  
open  
tPZH, tPHZ  
GND  
tPZL, tPLZ [3]  
2 × VCCO  
2 × VCCO  
2 × VCCO  
15 pF  
15 pF  
15 pF  
2 kΩ  
2 kΩ  
2 kΩ  
open  
GND  
open  
GND  
[1] VCCI is the supply voltage associated with the data input port.  
[2] dV/dt ≥ 1.0 V/ns.  
[3] VCCO is the supply voltage associated with the output port.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
12 / 22  
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
12. Application information  
12.1. Unidirectional logic level-shifting application  
The circuit given in Fig. 10 is an example of the 74AVC1T45 being used in an unidirectional logic  
level-shifting application.  
V
V
CC2  
CC1  
V
V
CC(B)  
CC(A)  
GND  
A
1
2
3
6
5
4
74AVC1T45  
DIR  
B
V
CC1  
V
CC2  
system-1  
system-2  
001aag973  
Fig. 10. Unidirectional logic level-shifting application  
Table 16. Description unidirectional logic level-shifting application  
Pin  
1
Name  
VCC(A)  
GND  
A
Function  
VCC1  
GND  
OUT  
IN  
Description  
supply voltage of system-1 (0.8 V to 3.6 V)  
device GND  
2
3
output level depends on VCC1 voltage  
input threshold value depends on VCC2 voltage  
the GND (LOW level) determines B port to A port direction  
supply voltage of system-2 (0.8 V to 3.6 V)  
4
B
5
DIR  
DIR  
6
VCC(B)  
VCC2  
12.2. Bidirectional logic level-shifting application  
Fig. 11 shows the 74AVC1T45 being used in a bidirectional logic level-shifting application. Since  
the device does not have an output enable pin, the system designer should take precautions to  
avoid bus contention between system-1 and system-2 when changing directions.  
V
V
V
V
CC2  
CC1  
CC1  
CC2  
V
V
CC(B)  
CC(A)  
GND  
A
I/O-1  
I/O-2  
6
5
4
1
2
3
74AVC1T45  
PULL-UP/DOWN  
PULL-UP/DOWN  
DIR  
B
DIR CTRL  
system-1  
system-2  
001aag974  
Fig. 11. Bidirectional logic level-shifting application  
Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then  
from system-2 to system-1.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
13 / 22  
 
 
 
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Table 17. Description bidirectional logic level-shifting application  
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.  
State DIR CTRL I/O-1  
I/O-2  
input  
Z
Description  
1
2
H
H
output  
Z
system-1 data to system-2  
system-2 is getting ready to send data to system-1.  
I/O-1 and I/O-2 are disabled. The bus-line state depends  
on bus hold.  
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The  
bus-line state depends on bus hold.  
input  
output  
system-2 data to system-1  
12.3. Power-up considerations  
The device is designed such that no special power-up sequence is required other than GND being  
applied first.  
Table 18. Typical total supply current (ICC(A) + ICC(B)  
)
VCC(A)  
VCC(B)  
0 V  
0
Unit  
0.8 V  
0.1  
0.1  
0.1  
0.1  
0.1  
0.7  
2.3  
1.2 V  
0.1  
0.1  
0.1  
0.1  
0.1  
0.3  
1.4  
1.5 V  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.9  
1.8 V  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.5  
2.5 V  
0.1  
0.7  
0.3  
0.1  
0.1  
0.1  
0.1  
3.3 V  
0.1  
2.3  
1.4  
0.9  
0.5  
0.1  
0.1  
0 V  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
0.8 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
12.4. Enable times  
Calculate the enable times for the 74AVC1T45 using the following formulas:  
ten (DIR to A) = tdis (DIR to B) + tpd (B to A)  
ten (DIR to B) = tdis (DIR to A) + tpd (A to B)  
In a bidirectional application, these enable times provide the maximum delay from the time  
the DIR bit is switched until an output is expected. For example, if the 74AVC1T45 initially is  
transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled  
before presenting it with an input. After the B port has been disabled, an input signal applied to it  
appears on the corresponding A port after the specified propagation delay.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
14 / 22  
 
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
13. Package outline  
TSSOP6: plastic thin shrink small outline package; 6 leads; body width 1.25 mm  
SOT363-2  
D
B
E
A
X
c
(6x)  
y
H
E
v
M
A
e
1
6
5
4
pin 1 index  
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B  
p
b
p
(6x)  
detail X  
e
e
0
3 mm  
scale  
Dimensions (mm are the original dimensions)  
Unit  
(1)  
(1)  
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0  
0.8 0.8  
0.30 0.25 2.2 1.35  
0.15 0.08 1.8 1.15  
2.4 0.46  
1.8 0.26  
8°  
0°  
mm  
0.15  
0.65 1.3  
0.3 0.1 0.1  
0
min  
Note  
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.  
sot363-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
21-12-15  
21-12-16  
SOT363-2  
SC-88A  
MO-203  
Fig. 12. Package outline SOT363-2 (TSSOP6)  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
15 / 22  
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm  
SOT886  
b
1
2
3
4x  
(2)  
L
L
1
e
6
5
4
e
e
1
1
6x  
(2)  
A
A
1
D
E
terminal 1  
index area  
0
1
2 mm  
scale  
Dimensions (mm are the original dimensions)  
(1)  
Unit  
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05  
0.35 0.40  
0.30 0.35  
0.27 0.32  
nom  
min  
0.20 1.45 1.00 0.6  
0.17 1.40 0.95  
mm  
0.5  
Notes  
1. Including plating thickness.  
2. Can be visible in some manufacturing processes.  
sot886_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
MO-252  
JEITA  
04-07-22  
12-01-05  
SOT886  
Fig. 13. Package outline SOT886 (XSON6)  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
16 / 22  
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
XSON6: extremely thin small outline package; no leads;  
6 terminals; body 0.9 x 1.0 x 0.35 mm  
SOT1115  
b
3
(2)  
(4×)  
1
2
L
L
1
e
6
5
4
e
e
1
1
(2)  
(6×)  
A
1
A
D
E
terminal 1  
index area  
0
L
0.5  
scale  
1 mm  
Dimensions  
Unit  
(1)  
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05  
0.35 0.40  
0.15 0.90 1.00 0.55 0.3 0.30 0.35  
0.12 0.85 0.95 0.27 0.32  
mm nom  
min  
Note  
1. Including plating thickness.  
2. Visible depending upon used manufacturing technology.  
sot1115_po  
Issue date  
References  
Outline  
version  
European  
projection  
IEC  
JEDEC  
JEITA  
10-04-02  
10-04-07  
SOT1115  
Fig. 14. Package outline SOT1115 (XSON6)  
©
74AVC1T45  
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Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
17 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
XSON6: extremely thin small outline package; no leads;  
6 terminals; body 1.0 x 1.0 x 0.35 mm  
SOT1202  
b
(2)  
1
2
3
(4×)  
L
L
1
e
6
5
4
e
e
1
1
(2)  
(6×)  
A
1
A
D
E
terminal 1  
index area  
0
L
0.5  
1 mm  
scale  
Dimensions  
Unit  
(1)  
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05  
0.35 0.40  
0.15 1.00 1.00 0.55 0.35 0.30 0.35  
0.12 0.95 0.95 0.27 0.32  
mm nom  
min  
Note  
1. Including plating thickness.  
2. Visible depending upon used manufacturing technology.  
sot1202_po  
Issue date  
References  
Outline  
version  
European  
projection  
IEC  
JEDEC  
JEITA  
10-04-02  
10-04-06  
SOT1202  
Fig. 15. Package outline SOT1202 (XSON6)  
©
74AVC1T45  
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Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
18 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
X2SON6: plastic thermal enhanced extremely thin small outline package; no leads;  
6 terminals; body 1.0 x 0.8 x 0.32 mm  
SOT1255-2  
C
Seating Plane  
y
C
X
D
A
B
E
pin 1  
ID area  
A
A
3
u
C
A
1
detail X  
2x  
u
C
2x  
e
1
b
(4x)  
y
C
1
v
w
C A  
C
B
3
4
L
(4x)  
2
5
Dh  
(6x)  
pin 1  
ID area  
1
6
e
2
0
1 mm  
scale  
Dimensions (mm are the original dimensions)  
Unit  
A
A
A
b
D
D
E
e
1
e
L
y
y
1
u
v
w
1
3
h
2
max 0.35 0.04  
mm nom 0.32 0.02  
0.31  
0.26  
0.21  
0.30  
0.25  
0.10  
(Typ.)  
0.25 0.80 0.60 0.40 0.20 0.05 0.05 0.05 0.10 0.05  
0.20  
1.00  
0.30 0.00  
0.15  
min  
sot1255-2_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
- - -  
JEITA  
19-11-07  
19-11-08  
SOT1255-2  
Fig. 16. Package outline SOT1255-2 (X2SON6)  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
19 / 22  
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
14. Abbreviations  
Table 19. Abbreviations  
Acronym  
CDM  
Description  
Charged Device Model  
CMOS  
DUT  
Complementary Metal Oxide Semiconductor  
Device Under Test  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
MM  
Machine Model  
15. Revision history  
Table 20. Revision history  
Document ID  
Release date Data sheet status  
20220202 Product data sheet  
Change notice Supersedes  
- 74AVC1T45 v.9  
74AVC1T45 v.10  
Modifications:  
SOT363 (SC-88) package changed to SOT363-2 (TSSOP6) package.  
Section 2 updated.  
74AVC1T45 v.9  
Modifications:  
20210706  
Product data sheet  
-
74AVC1T45 v.8  
SOT1255 (X2SON6) package changed to SOT1255-2 (X2SON6) package.  
Table 5: Derating values for Ptot total power dissipation updated.  
74AVC1T45 v.8  
74AVC1T45 v.7  
Modifications:  
20181210  
20170824  
Product data sheet  
Product data sheet  
-
-
74AVC1T45 v.7  
74AVC1T45 v.6  
The format of this data sheet has been redesigned to comply with the identity  
guidelines of Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
74AVC1T45 v.6  
Modifications:  
20160420  
Product data sheet  
-
74AVC1T45 v.5  
Added type number 74AVC1T45GX(SOT1255/X2SON6 package).  
74AVC1T45 v.5  
Modifications:  
20160106  
Table 16: Labels for pins 4 and 5 corrected.  
20120622 Product data sheet  
Package outline drawing of SOT886 (Fig. 13) modified.  
20111021 Product data sheet  
Product data sheet  
-
74AVC1T45 v.4  
74AVC1T45 v.3  
74AVC1T45 v.2  
74AVC1T45 v.4  
Modifications:  
-
74AVC1T45 v.3  
Modifications:  
-
Added type number 74AVC1T45GN (SOT1115/XSON6 package).  
Added type number 74AVC1T45GS (SOT1202/XSON6 package).  
74AVC1T45 v.2  
74AVC1T45 v.1  
20090505  
20080118  
Product data sheet  
Product data sheet  
-
-
74AVC1T45 v.1  
-
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
20 / 22  
 
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
injury, death or severe property or environmental damage. Nexperia and its  
suppliers accept no liability for inclusion and/or use of Nexperia products in  
such equipment or applications and therefore such inclusion and/or use is at  
the customer’s own risk.  
16. Legal information  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Data sheet status  
Document status Product  
Definition  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
[1][2]  
status [3]  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
changed since this document was published and may differ in case of  
multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Definitions  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
warranties as to the accuracy or completeness of information included herein  
and shall have no liability for the consequences of use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is  
intended for quick reference only and should not be relied upon to contain  
detailed and full information. For detailed and full information see the relevant  
full data sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of commercial sale — Nexperia products are  
sold subject to the general terms and conditions of commercial sale, as  
published at http://www.nexperia.com/profile/terms, unless otherwise agreed  
in a valid written individual agreement. In case an individual agreement is  
concluded only the terms and conditions of the respective agreement shall  
apply. Nexperia hereby expressly objects to applying the customer’s general  
terms and conditions with regard to the purchase of Nexperia products by  
customer.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
Nexperia and its customer, unless Nexperia and customer have explicitly  
agreed otherwise in writing. In no event however, shall an agreement be  
valid in which the Nexperia product is deemed to offer functions and qualities  
beyond those described in the Product data sheet.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Disclaimers  
Limited warranty and liability — Information in this document is believed  
to be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no responsibility  
for the content in this document if provided by an information source outside  
of Nexperia.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific Nexperia product is automotive qualified, the  
product is not suitable for automotive use. It is neither qualified nor tested in  
accordance with automotive testing or application requirements. Nexperia  
accepts no liability for inclusion and/or use of non-automotive qualified  
products in automotive equipment or applications.  
In no event shall Nexperia be liable for any indirect, incidental, punitive,  
special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal  
or replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards,  
customer (a) shall use the product without Nexperia’s warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
Nexperia’s specifications such use shall be solely at customer’s own risk,  
and (c) customer fully indemnifies Nexperia for any liability, damages or failed  
product claims resulting from customer design and use of the product for  
automotive applications beyond Nexperia’s standard warranty and Nexperia’s  
product specifications.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Trademarks  
Suitability for use — Nexperia products are not designed, authorized or  
warranted to be suitable for use in life support, life-critical or safety-critical  
systems or equipment, nor in applications where failure or malfunction  
of an Nexperia product can reasonably be expected to result in personal  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
21 / 22  
 
Nexperia  
74AVC1T45  
Dual-supply voltage level translator/transceiver; 3-state  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................2  
4. Marking..........................................................................2  
5. Functional diagram.......................................................2  
6. Pinning information......................................................3  
6.1. Pinning.........................................................................3  
6.2. Pin description.............................................................3  
7. Functional description................................................. 4  
8. Limiting values............................................................. 4  
9. Recommended operating conditions..........................5  
10. Static characteristics..................................................5  
11. Dynamic characteristics.............................................8  
11.1. Waveforms and test circuit.......................................11  
12. Application information........................................... 13  
12.1. Unidirectional logic level-shifting application............13  
12.2. Bidirectional logic level-shifting application..............13  
12.3. Power-up considerations......................................... 14  
12.4. Enable times............................................................14  
13. Package outline........................................................ 15  
14. Abbreviations............................................................20  
15. Revision history........................................................20  
16. Legal information......................................................21  
© Nexperia B.V. 2022. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 2 February 2022  
©
74AVC1T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 10 — 2 February 2022  
22 / 22  

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